intel-driver-1.3.0/000077500000000000000000000000001231401140700141105ustar00rootroot00000000000000intel-driver-1.3.0/.gitignore000066400000000000000000000004731231401140700161040ustar00rootroot00000000000000*~ *.o *.lo *.la *.orig *.rej *.loT *.bin *.pc *.g[4-7]s .deps .libs install-sh libtool ltmain.sh compile missing Makefile Makefile.in config.h config.h.in stamp-h1 aclocal.m4 autom4te.cache config.guess config.log config.status config.sub configure depcomp TAGS /debian.upstream/changelog /debian.upstream/control intel-driver-1.3.0/AUTHORS000066400000000000000000000002741231401140700151630ustar00rootroot00000000000000Intel Linux graphics team working on the driver: Chang Zhou Gwenole Beauchesne Haihao Xiang (primary author) Nanhai Zou Additional contributors: Alexander Osin Damien Lespiau Edgar Hucek intel-driver-1.3.0/Android.mk000066400000000000000000000001201231401140700160120ustar00rootroot00000000000000# Recursive call sub-folder Android.mk # include $(call all-subdir-makefiles) intel-driver-1.3.0/COPYING000066400000000000000000000021521231401140700151430ustar00rootroot00000000000000 Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sub license, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. intel-driver-1.3.0/Makefile.am000066400000000000000000000011341231401140700161430ustar00rootroot00000000000000AUTOMAKE_OPTIONS = foreign SUBDIRS = debian.upstream src # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = \ aclocal.m4 compile config.guess config.sub \ configure depcomp install-sh ltmain.sh \ Makefile.in missing DEB_BUILDDIR = debian.build deb: @[ -d debian ] || ln -s debian.upstream debian dpkg-buildpackage -rfakeroot -uc -us deb.upstream: dist -mkdir -p $(DEB_BUILDDIR) cd $(DEB_BUILDDIR) && \ rm -rf $(PACKAGE)-$(VERSION) && \ tar zxvf ../$(PACKAGE)-$(VERSION).tar.gz && \ cd $(PACKAGE)-$(VERSION) && \ $(MAKE) deb -f Makefile.am intel-driver-1.3.0/NEWS000066400000000000000000000130631231401140700146120ustar00rootroot00000000000000libva-intel-driver NEWS -- summary of changes. 2014-03-24 Copyright (C) 2009-2014 Intel Corporation Version 1.3.0 - 24.Mar.2014 * Add support for Broadwell - Decoding: H.264/MPEG-2/VC-1/JPEG/VP8 - Encoding: H.264/MPEG-2 - VPP: CSC/scaling/NoiseReduction/Deinterlacing{Bob, MotionAdaptive, MotionCompensated}/Sharpening/ColorBalance * Fix the wrong setting in MI_BATCH_BATCH_START Version 1.2.2 - 16.Dec.2013 * Motion compensation DI on HSW * Optimization of FPS for H.264 encoding on HSW * Add brightness/contrast/hue/saturation support for rendering. * Support BT601/BT709/SMPTE240 in vaPutSurface() * Expose Constrained Baseline Profile instead of Baseline Profile for H.264 * Bug fixes Version 1.2.1 - 23.Sep.2013 * Add PCI IDs for Bay Trail * Performance improvement for MPEG-2 Encoding on IVB/HSW * Add basic processing support for packed YUV to packed YUV on ILK+ * Check the underlying OS support for VEBOX on HSW * Quality improvement for BobDI on SNB/IVB * Add support for Motion Adaptive Deinterlacing on IVB * vaDeriveImage() works for UYVY formats * Fix thread safety issue * Fix GPU hang issue when decoding some videos on SNB * Fix output filter count from QueryVideoProcFilters() Version 1.2.0 - 26.Jun.2013 * The new H.264 encoding API on SNB/IVB/HSW - Profile: BP/MP/HP - Entropy Coding: CAVLC/CABAC - Rate Control: CQP, CBR - Progressive frame - Multi Slice encoding - Configurable GOP Structure * MPEG-2 encoding on IVB/HSW - Profile: SP/MP - Progressive frame - Configurable GOP Structure * Video process on ILK/SNB/IVB/HSW - CSC/scaling on ILK - CSC/scaling/NoiseReduction/Deinterlacing{Bob} on SNB/IVB - CSC/scaling/NoiseReduction/Deinterlacing{Bob,MotionAdaptive}/Sharpening/ColorBalance on HSW * Implement vaQuerySurfaceAttributes() * Implement the new version of vaCreateSurfaces() - Create VA surface with specified fourcc - Create VA surface from external buffer . flinked GEM buffer . prime/dma buffer * Optimize H.264 encoding on IVB/HSW * More reserved PCI IDs for HSW * A lot of bug fixes Version 1.0.20 - 19.Mar.2013 * Add support for wayland 1.0 protocol (Rob Bradford) * Add global alpha support for subpicture * Add support for IA88/AI88 subpicture * Support up to 4 subpictures for each VA surface * Update PCI IDs for Haswell CRW * Automake 1.13 fixups (Armin K) * Fix libva-intel-driver-1.0.19 display corruption on IVB GT1 https://bugs.freedesktop.org/show_bug.cgi?id=57323 * Fix decoding with FREXT02_JVC_C.264 on SNB https://bugs.freedesktop.org/show_bug.cgi?id=57720 * Fix H.264 decoding broken/visual errors on ILK (Tobias Jakobi) https://bugs.freedesktop.org/show_bug.cgi?id=58875 * Fix GPU hung with h.264 video and a resolution of 1920x816 on IVB https://bugs.freedesktop.org/show_bug.cgi?id=59050 Version 1.0.19 - 09.Nov.2012 * Add support for Haswell * Add raw DRM support (Dmitry Ermilov) * Add Wayland support * Add support for display rotation attribute * Support 4K encoding on IVB and HSW * Drop explicit dependency on X11 and libva-x11 * Fix VC-1 decoding when VSTRANSFORM is 0 * Fix SIGSEGV caused by use-after-free of the bufmgr (Stéphane Marchesin) * Fix thread safety issue (Gautam) * Fix vaUnlockSurface() for libva trace Version 1.0.18 - 02.Aug.2012 * Add JPEG decoding on Ivy Bridge * Add support for a new Ivy Bridge chip * Add support for vaSyncSurface() and vaQuerySurfaceStatus() (Dmitry Ermilov) * Fix decoding of MPEG-2 videos with implicit IQ matrices * Fix concurrent creation of VA objects (MT safety) * Fix decoding of large resolution videos (up to 4K on IVB) Version 1.0.17 - 02.Apr.2012 * Add support for IMC1/IMC3 surface formats * Fix rendering of interlaced surfaces * Fix MPEG-2 decoding of interlaced streams (SNB, IVB) * Fix H.264 weighted prediction indicator (SNB) * Fix and simplify calculation of H.264 macroblock bit offset (ILK, SNB, IVB) Version 1.0.16 - 14.Feb.2012 * Fix VC-1 bitplane buffer size (SNB, IVB) * Fix VC-1 motion vector modes for Ivy Bridge * Fix MFX_QM_STATE for H.264 flat scaling lists (IVB) * Fix and simplify AVC_REF_IDX_STATE setup (ILK, SNB, IVB) * Fix memory leak of encoder buffers * Fix check for internal VA surface format prior to rendering * Add support for B43 chipset (Alexander Inyukhin) Version 1.0.15 - 28.Oct.2011 * Add auto-generated Debian packaging * Fix VC-1 decoding (TTFRM packing) * Fix MPEG-2 decoding on Ivy Bridge * Fix MPEG-2 decoding with sparse QM matrices updates * Fix slice-param & slice-data buffer memory leaks Version 1.0.14 - 28.Jul.2011 * Add H.264 encoding support to Ivy Bridge * Add support for VA_SUBPICTURE_DESTINATION_IS_SCREEN_COORD * Fix next slice vertical position for MPEG-2 (#38628) * Fix subpicture scale factor for Y axis * Fix GPU hang when decoding field coded MPEG-2 picture * Fix memory leaks (Edgar Hucek) Version 1.0.13 - 25.May.2011 * Add H.264 encoding support to Sandy Bridge * Add MPEG-2, VC-1 and H.264 decoding support to Ivy Bridge * Fix thread safety issues Version 1.0.11 - 14.Mar.2011 * Add deinterlacing & scaling support to Sandy Bridge * Add vaDeriveImage() implementation * Fix VC-1 decoding for Main/Simple profiles Version 1.0.9 - 27.Jan.2011 * Add VC-1 decoding support to Sandy Bridge Version 1.0.8 - 21.Jan.2011 * Add support for IA44/AI44 subpicture formats (#32868) Version 1.0.7 - 17.Dec.2011 * Add MPEG-2 and H.264 decoding support to Sandy Bridge Version 1.0.5 - 02.Sep.2010 * Add deinterlacing & scaling support to Ironlake Version 1.0.4 - 13.Jul.2010 * Add vaGetImage() implementation * Add support for RGBA subpictures * Fix H.264 decoding on Ironlake Version 1.0.3 - 10.Jun.2010 * Add H.264 decoding support to Ironlake intel-driver-1.3.0/README000066400000000000000000000012561231401140700147740ustar00rootroot00000000000000 libva-intel-driver VA driver for Intel G45 & HD Graphics family Copyright (C) 2009-2011 Intel Corporation License ------- Please read the COPYING file available in this package. Overview -------- libva-intel-driver is the VA-API implementation for Intel G45 chipsets and Intel HD Graphics for Intel Core processor family. Platform definitions: CTG: Cantiga, Intel GMA 4500MHD (GM45) ILK: Ironlake, Intel HD Graphics for 2010 Intel Core processor family SNB: Sandybridge, Intel HD Graphics for 2011 Intel Core processor family IVB: Ivybridge Codecs ------ H.264 D ILK+ H.264 E SNB+ MPEG-2 D CTG+ VC-1 D SNB+ Requirements ------------ libva >= 1.0.16 intel-driver-1.3.0/autogen.sh000077500000000000000000000001351231401140700161100ustar00rootroot00000000000000#! /bin/sh autoreconf -v --install if test -z "$NOCONFIGURE"; then ./configure "$@" fi intel-driver-1.3.0/configure.ac000066400000000000000000000151271231401140700164040ustar00rootroot00000000000000# intel-driver package version number m4_define([intel_driver_major_version], [1]) m4_define([intel_driver_minor_version], [3]) m4_define([intel_driver_micro_version], [0]) m4_define([intel_driver_pre_version], [0]) m4_define([intel_driver_version], [intel_driver_major_version.intel_driver_minor_version.intel_driver_micro_version]) m4_if(intel_driver_pre_version, [0], [], [ m4_append([intel_driver_version], intel_driver_pre_version, [.pre]) ]) # libva minimum version requirement m4_define([va_api_version], [0.35]) m4_define([libva_package_version], [1.3.0]) # libdrm minimum version requirement m4_define([libdrm_version], [2.4.45]) AC_PREREQ([2.57]) AC_INIT([intel_driver], [intel_driver_version], [haihao.xiang@intel.com], [libva-intel-driver]) AC_CONFIG_SRCDIR([Makefile.am]) AM_INIT_AUTOMAKE([1.9 tar-ustar]) AC_CONFIG_HEADERS([src/config.h]) INTEL_DRIVER_MAJOR_VERSION=intel_driver_major_version INTEL_DRIVER_MINOR_VERSION=intel_driver_minor_version INTEL_DRIVER_MICRO_VERSION=intel_driver_micro_version AC_DEFINE([INTEL_DRIVER_MAJOR_VERSION], [intel_driver_major_version], [Major version of the driver]) AC_DEFINE([INTEL_DRIVER_MINOR_VERSION], [intel_driver_minor_version], [Minor version of the driver]) AC_DEFINE([INTEL_DRIVER_MICRO_VERSION], [intel_driver_micro_version], [Micro version of the driver]) AC_DEFINE([INTEL_DRIVER_PRE_VERSION], [intel_driver_pre_version], [Preversion of the driver]) INTEL_DRIVER_LT_LDFLAGS="-avoid-version" AC_SUBST(INTEL_DRIVER_LT_LDFLAGS) dnl Use pretty build output with automake >= 1.11 m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])], [ AM_DEFAULT_VERBOSITY=1 AC_SUBST(AM_DEFAULT_VERBOSITY) ]) AC_ARG_ENABLE(drm, [AC_HELP_STRING([--enable-drm], [build with VA/DRM API support @<:@default=yes@:>@])], [], [enable_drm="yes"]) AC_ARG_ENABLE(x11, [AC_HELP_STRING([--enable-x11], [build with VA/X11 API support @<:@default=yes@:>@])], [], [enable_x11="yes"]) AC_ARG_ENABLE([wayland], [AC_HELP_STRING([--enable-wayland], [build with VA/Wayland API support @<:@default=yes@:>@])], [], [enable_wayland="yes"]) AC_DISABLE_STATIC AC_PROG_LIBTOOL AC_PROG_CC AM_PROG_CC_C_O AC_C_BIGENDIAN AC_HEADER_STDC AC_SYS_LARGEFILE AC_CHECK_LIB([m], [sin]) AC_CHECK_FUNCS([log2f]) LIBVA_PACKAGE_VERSION=libva_package_version AC_SUBST(LIBVA_PACKAGE_VERSION) dnl Check for recent enough DRM LIBDRM_VERSION=libdrm_version PKG_CHECK_MODULES([DRM], [libdrm >= $LIBDRM_VERSION]) AC_SUBST(LIBDRM_VERSION) dnl Check for gen4asm PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.5], [gen4asm=yes], [gen4asm=no]) AM_CONDITIONAL(HAVE_GEN4ASM, test x$gen4asm = xyes) AC_PATH_PROG([GEN4ASM], [intel-gen4asm]) dnl Check for VA-API PKG_CHECK_MODULES(LIBVA_DEPS, [libva >= va_api_version]) dnl Check for VA/DRM API USE_DRM="$enable_drm" if test "$USE_DRM" = "yes"; then PKG_CHECK_MODULES(LIBVA_DRM_DEPS, [libva-drm], [AC_DEFINE([HAVE_VA_DRM], [1], [Defined to 1 if VA/DRM API is enabled])], [USE_DRM="no"]) # Check for if test "$USE_DRM" = "yes"; then saved_CPPFLAGS="$CPPFLAGS" CPPFLAGS="$CPPFLAGS $DRM_CFLAGS" AC_CHECK_HEADERS([drm_fourcc.h], [:], [USE_DRM="no"]) CPPFLAGS="$saved_CPPFLAGS" fi fi AM_CONDITIONAL(USE_DRM, test "$USE_DRM" = "yes") VA_VERSION=`$PKG_CONFIG --modversion libva` VA_MAJOR_VERSION=`echo "$VA_VERSION" | cut -d'.' -f1` VA_MINOR_VERSION=`echo "$VA_VERSION" | cut -d'.' -f2` VA_MICRO_VERSION=`echo "$VA_VERSION" | cut -d'.' -f3` VA_VERSION_STR="$VA_VERSION" va_full_version_int=`expr ${VA_MAJOR_VERSION:-0} "*" 1000000 + \ ${VA_MINOR_VERSION:-0} "*" 10000 + \ ${VA_MICRO_VERSION:-0} "*" 100 + \ 0` VA_DRIVER_INIT_FUNC="__vaDriverInit_${VA_MAJOR_VERSION}_${VA_MINOR_VERSION}" AC_DEFINE_UNQUOTED([VA_DRIVER_INIT_FUNC], [$VA_DRIVER_INIT_FUNC], [Define driver entry-point]) dnl Check for VA/DRM API USE_X11="$enable_x11" if test "$USE_X11" = "yes"; then PKG_CHECK_MODULES(LIBVA_X11_DEPS, [libva-x11], [AC_DEFINE([HAVE_VA_X11], [1], [Defined to 1 if VA/X11 API is enabled])], [USE_X11="no"]) fi AM_CONDITIONAL(USE_X11, test "$USE_X11" = "yes") dnl Check for VA-API drivers path AC_MSG_CHECKING([for VA drivers path]) LIBVA_DRIVERS_PATH=`$PKG_CONFIG libva --variable driverdir` if test -z "$LIBVA_DRIVERS_PATH"; then LIBVA_DRIVERS_PATH="/usr/lib/xorg/modules/drivers" fi AC_MSG_RESULT([$LIBVA_DRIVERS_PATH]) AC_SUBST(LIBVA_DRIVERS_PATH) # Check for EGL if test "$enable_wayland" = "yes"; then enable_egl="yes" fi USE_EGL="no" if test "$enable_egl" = "yes"; then PKG_CHECK_MODULES([EGL], [egl], [USE_EGL="yes"], [USE_EGL="no"]) saved_CPPFLAGS="$CPPFLAGS" saved_LIBS="$LIBS" CPPFLAGS="$CPPFLAGS $EGL_CFLAGS" LIBS="$LIBS $EGL_LIBS" AC_CHECK_HEADERS([EGL/egl.h], [:], [USE_EGL="no"]) AC_CHECK_LIB([EGL], [eglGetDisplay], [:], [USE_EGL="no"]) CPPFLAGS="$saved_CPPFLAGS" LIBS="$saved_LIBS" fi AM_CONDITIONAL(USE_EGL, test "$USE_EGL" = "yes") # Check for Wayland USE_WAYLAND="no" if test "$enable_wayland" = "yes"; then PKG_CHECK_MODULES([WAYLAND], [wayland-client], [USE_WAYLAND="yes"], [:]) PKG_CHECK_MODULES([LIBVA_WAYLAND_DEPS], [libva-wayland], [AC_DEFINE([HAVE_VA_WAYLAND], [1], [Defined to 1 if VA/Wayland API is enabled])], [USE_WAYLAND="no"]) fi AM_CONDITIONAL(USE_WAYLAND, test "$USE_WAYLAND" = "yes") m4_ifdef([WAYLAND_SCANNER_RULES], [WAYLAND_SCANNER_RULES(['$(top_srcdir)/src/wayland'])], [wayland_scanner_rules=""; AC_SUBST(wayland_scanner_rules)]) AC_OUTPUT([ Makefile debian.upstream/Makefile src/Makefile src/shaders/Makefile src/shaders/h264/Makefile src/shaders/h264/ildb/Makefile src/shaders/h264/mc/Makefile src/shaders/mpeg2/Makefile src/shaders/mpeg2/vld/Makefile src/shaders/post_processing/Makefile src/shaders/post_processing/gen5_6/Makefile src/shaders/post_processing/gen7/Makefile src/shaders/post_processing/gen75/Makefile src/shaders/post_processing/gen8/Makefile src/shaders/render/Makefile src/shaders/utils/Makefile src/shaders/vme/Makefile src/wayland/Makefile ]) dnl Print summary BACKENDS="" AS_IF([test "$USE_DRM" = "yes"], [BACKENDS="$BACKENDS drm"]) AS_IF([test "$USE_X11" = "yes"], [BACKENDS="$BACKENDS x11"]) AS_IF([test "$USE_WAYLAND" = "yes"], [BACKENDS="$BACKENDS wayland"]) echo echo $PACKAGE configuration summary: echo echo VA-API version ................... : $VA_VERSION_STR echo VA-API drivers path .............. : $LIBVA_DRIVERS_PATH echo Windowing systems ................ : $BACKENDS echo intel-driver-1.3.0/debian.upstream/000077500000000000000000000000001231401140700171715ustar00rootroot00000000000000intel-driver-1.3.0/debian.upstream/Makefile.am000066400000000000000000000012521231401140700212250ustar00rootroot00000000000000DEBIANFILES = \ changelog.in \ compat \ control.in \ copyright \ libva-intel-driver.install \ rules \ $(NULL) DEBIANGENFILES = \ changelog \ control \ $(NULL) EXTRA_DIST = $(DEBIANFILES) dist_noinst_DATA = $(DEBIANGENFILES) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in $(DEBIANGENFILES) $(DEBIANGENFILES): %: %.in Makefile -$(AM_V_GEN)sed \ -e 's|\@DATE\@|'"`LC_ALL=C date +'%a, %d %b %Y %X %z'`"'|' \ -e 's|\@LIBDRM_VERSION\@|$(LIBDRM_VERSION)|' \ -e 's|\@LIBVA_PACKAGE_VERSION\@|$(LIBVA_PACKAGE_VERSION)|' \ -e 's|\@PACKAGE_VERSION\@|$(PACKAGE_VERSION)|' \ $< > $@ intel-driver-1.3.0/debian.upstream/changelog.in000066400000000000000000000002671231401140700214550ustar00rootroot00000000000000libva-intel-driver (@PACKAGE_VERSION@-1) unstable; urgency=low * Autogenerated package, see NEWS file for ChangeLog. -- Gwenole Beauchesne @DATE@ intel-driver-1.3.0/debian.upstream/compat000066400000000000000000000000021231401140700203670ustar00rootroot000000000000005 intel-driver-1.3.0/debian.upstream/control.in000066400000000000000000000016531231401140700212060ustar00rootroot00000000000000Source: libva-intel-driver Section: libs Priority: optional Maintainer: Gwenole Beauchesne Build-Depends: debhelper (>= 5), cdbs, libdrm-dev (>= @LIBDRM_VERSION@), libva-dev (>= @LIBVA_PACKAGE_VERSION@) Standards-Version: 3.7.2 Package: libva-intel-driver Section: libs Architecture: any Depends: libva1 (>= @LIBVA_PACKAGE_VERSION@), ${shlibs:Depends}, ${misc:Depends} Description: VA driver for Intel G45 & HD Graphics family Video decode & encode driver for Intel G45 chipsets and Intel HD Graphics for Intel Core processor family. Package: libva-intel-driver-dbg Section: libdevel Architecture: any Depends: libva-intel-driver (= ${Source-Version}) Description: VA driver for Intel G45 & HD Graphics family (debug symbols) Video decode & encode driver for Intel G45 chipsets and Intel HD Graphics for Intel Core processor family. . This package contains the debug files. intel-driver-1.3.0/debian.upstream/copyright000066400000000000000000000023071231401140700211260ustar00rootroot00000000000000This package is maintained by: Gwenole Beauchesne License: Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sub license, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. intel-driver-1.3.0/debian.upstream/libva-intel-driver.install000066400000000000000000000000341231401140700242550ustar00rootroot00000000000000debian/tmp/usr/lib/dri/*.so intel-driver-1.3.0/debian.upstream/rules000077500000000000000000000006001231401140700202450ustar00rootroot00000000000000#!/usr/bin/make -f include /usr/share/cdbs/1/rules/debhelper.mk include /usr/share/cdbs/1/class/autotools.mk include /usr/share/cdbs/1/rules/utils.mk # Allow SMP build ifeq ($(DEBIAN_BUILD_NCPUS),) DEBIAN_BUILD_NCPUS = $(shell /usr/bin/getconf _NPROCESSORS_ONLN) endif ifneq ($(DEBIAN_BUILD_NCPUS),) EXTRA_MAKE_FLAGS += -j$(DEBIAN_BUILD_NCPUS) endif MAKE += $(EXTRA_MAKE_FLAGS) intel-driver-1.3.0/src/000077500000000000000000000000001231401140700146775ustar00rootroot00000000000000intel-driver-1.3.0/src/Android.mk000077500000000000000000000054171231401140700166220ustar00rootroot00000000000000# Copyright (c) 2012 Intel Corporation. All Rights Reserved. # # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the # "Software"), to deal in the Software without restriction, including # without limitation the rights to use, copy, modify, merge, publish, # distribute, sub license, and/or sell copies of the Software, and to # permit persons to whom the Software is furnished to do so, subject to # the following conditions: # # The above copyright notice and this permission notice (including the # next paragraph) shall be included in all copies or substantial portions # of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. # IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR # ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, # TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE # SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # LOCAL_PATH:= $(call my-dir) include $(CLEAR_VARS) LOCAL_SRC_FILES := \ gen6_mfc_common.c \ gen6_mfc.c \ gen6_mfd.c \ gen6_vme.c \ gen7_mfd.c \ gen7_mfc.c \ gen7_vme.c \ gen75_mfc.c \ gen75_mfd.c \ gen75_vme.c \ gen75_picture_process.c \ gen75_vpp_vebox.c \ gen75_vpp_gpe.c \ i965_avc_bsd.c \ i965_avc_hw_scoreboard.c\ i965_avc_ildb.c \ i965_decoder_utils.c \ i965_drv_video.c \ i965_encoder.c \ i965_encoder_utils.c \ i965_gpe_utils.c \ i965_media.c \ i965_media_h264.c \ i965_media_mpeg2.c \ i965_post_processing.c \ i965_render.c \ intel_media_common.c \ intel_batchbuffer.c \ intel_batchbuffer_dump.c\ intel_driver.c \ intel_memman.c \ object_heap.c LOCAL_CFLAGS := -DLINUX -DANDROID -g -Wall -Wno-unused -fvisibility=hidden LOCAL_C_INCLUDES := \ $(TARGET_OUT_HEADERS)/libva \ $(TARGET_OUT_HEADERS)/libdrm LOCAL_MODULE_TAGS := optional LOCAL_MODULE := i965_drv_video LOCAL_SHARED_LIBRARIES := libdl libdrm libdrm_intel libcutils \ libva libva-android libstdc++ ifeq ($(strip $(DRIVER_LOG_ENABLE)),true) LOCAL_CFLAGS += -DDRIVER_LOG_ENABLE LOCAL_SHARED_LIBRARIES += liblog endif include $(BUILD_SHARED_LIBRARY) intel-driver-1.3.0/src/Makefile.am000077500000000000000000000073501231401140700167430ustar00rootroot00000000000000# Copyright (c) 2007 Intel Corporation. All Rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the # "Software"), to deal in the Software without restriction, including # without limitation the rights to use, copy, modify, merge, publish, # distribute, sub license, and/or sell copies of the Software, and to # permit persons to whom the Software is furnished to do so, subject to # the following conditions: # # The above copyright notice and this permission notice (including the # next paragraph) shall be included in all copies or substantial portions # of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. # IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR # ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, # TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE # SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. SUBDIRS = shaders AM_CPPFLAGS = \ -DPTHREADS \ $(DRM_CFLAGS) \ $(LIBVA_DEPS_CFLAGS) \ $(NULL) driver_cflags = \ -Wall \ -fvisibility=hidden \ $(NULL) driver_ldflags = \ -module -avoid-version \ -no-undefined \ -Wl,--no-undefined \ $(NULL) driver_libs = \ -lpthread -lm -ldl \ $(DRM_LIBS) -ldrm_intel \ $(LIBVA_DEPS_LIBS) \ $(NULL) source_c = \ dso_utils.c \ gen6_mfc.c \ gen6_mfc_common.c \ gen6_mfd.c \ gen6_vme.c \ gen7_vme.c \ gen7_mfc.c \ gen7_mfd.c \ gen75_mfd.c \ gen75_mfc.c \ gen8_mfc.c \ gen8_mfd.c \ gen8_vme.c \ gen75_picture_process.c \ gen75_vme.c \ gen75_vpp_gpe.c \ gen75_vpp_vebox.c \ i965_avc_bsd.c \ i965_avc_hw_scoreboard.c\ i965_avc_ildb.c \ i965_decoder_utils.c \ i965_drv_video.c \ i965_encoder.c \ i965_encoder_utils.c \ i965_media.c \ i965_media_h264.c \ i965_media_mpeg2.c \ i965_gpe_utils.c \ i965_post_processing.c \ i965_render.c \ intel_batchbuffer.c \ intel_batchbuffer_dump.c\ intel_driver.c \ intel_memman.c \ object_heap.c \ intel_media_common.c \ $(NULL) source_h = \ dso_utils.h \ gen6_mfc.h \ gen6_mfd.h \ gen6_vme.h \ gen7_mfd.h \ gen75_picture_process.h \ gen75_vpp_gpe.h \ gen75_vpp_vebox.h \ i965_avc_bsd.h \ i965_avc_hw_scoreboard.h\ i965_avc_ildb.h \ i965_decoder.h \ i965_decoder_utils.h \ i965_defines.h \ i965_drv_video.h \ i965_encoder.h \ i965_encoder_utils.h \ i965_media.h \ i965_media_h264.h \ i965_media_mpeg2.h \ i965_mutext.h \ i965_gpe_utils.h \ i965_post_processing.h \ i965_render.h \ i965_structs.h \ intel_batchbuffer.h \ intel_batchbuffer_dump.h\ intel_compiler.h \ intel_driver.h \ intel_media.h \ intel_memman.h \ object_heap.h \ sysdeps.h \ va_backend_compat.h \ $(NULL) i965_drv_video_la_LTLIBRARIES = i965_drv_video.la i965_drv_video_ladir = $(LIBVA_DRIVERS_PATH) i965_drv_video_la_CFLAGS = $(driver_cflags) i965_drv_video_la_LDFLAGS = $(driver_ldflags) i965_drv_video_la_LIBADD = $(driver_libs) i965_drv_video_la_SOURCES = $(source_c) noinst_HEADERS = $(source_h) if USE_X11 source_c += i965_output_dri.c source_h += i965_output_dri.h endif if USE_WAYLAND source_c += i965_output_wayland.c source_h += i965_output_wayland.h driver_cflags += $(WAYLAND_CFLAGS) endif # Wayland protocol protocol_source_h = wayland-drm-client-protocol.h i965_output_wayland.c: $(protocol_source_h) @wayland_scanner_rules@ DIST_SUBDIRS = $(SUBDIRS) wayland # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in config.h.in intel-driver-1.3.0/src/config_android.h000066400000000000000000000061151231401140700200200ustar00rootroot00000000000000/* src/config.h. Generated from config.h.in by configure. */ /* src/config.h.in. Generated from configure.ac by autoheader. */ /* NOTE: THIS VERSION IS FOR ANDROID ONLY and manually adjusted */ /* Define if building universal (internal helper macro) */ /* #undef AC_APPLE_UNIVERSAL_BUILD */ /* Define to 1 if you have the header file. */ #define HAVE_DLFCN_H 1 /* Define to 1 if you have the header file. */ #define HAVE_INTTYPES_H 1 /* Defined to 1 if VA-API exposes JPEG decoding */ #define HAVE_JPEG_DECODING 1 /* Define to 1 if you have the header file. */ #define HAVE_MEMORY_H 1 /* Define to 1 if you have the header file. */ #define HAVE_STDINT_H 1 /* Define to 1 if you have the header file. */ #define HAVE_STDLIB_H 1 /* Define to 1 if you have the header file. */ #define HAVE_STRINGS_H 1 /* Define to 1 if you have the header file. */ #define HAVE_STRING_H 1 /* Define to 1 if you have the header file. */ #define HAVE_SYS_STAT_H 1 /* Define to 1 if you have the header file. */ #define HAVE_SYS_TYPES_H 1 /* Define to 1 if you have the header file. */ #define HAVE_UNISTD_H 1 /* Major version of the driver */ #define INTEL_DRIVER_MAJOR_VERSION 1 /* Micro version of the driver */ #define INTEL_DRIVER_MICRO_VERSION 16 /* Minor version of the driver */ #define INTEL_DRIVER_MINOR_VERSION 0 /* Preversion of the driver */ #define INTEL_DRIVER_PRE_VERSION 1 /* Define to the sub-directory in which libtool stores uninstalled libraries. */ #define LT_OBJDIR ".libs/" /* Define to 1 if your C compiler doesn't accept -c and -o together. */ /* #undef NO_MINUS_C_MINUS_O */ /* Name of package */ #define PACKAGE "libva-driver-intel" /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "haihao.xiang@intel.com" /* Define to the full name of this package. */ #define PACKAGE_NAME "intel_driver" /* Define to the full name and version of this package. */ #define PACKAGE_STRING "intel_driver 1.0.16.pre1" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "libva-driver-intel" /* Define to the home page for this package. */ #define PACKAGE_URL "" /* Define to the version of this package. */ #define PACKAGE_VERSION "1.0.16.pre1" /* Define to 1 if you have the ANSI C header files. */ #define STDC_HEADERS 1 /* Define driver entry-point */ #define VA_DRIVER_INIT_FUNC __vaDriverInit_0_33 /* Version number of package */ #define VERSION "1.0.16.pre1" /* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most significant byte first (like Motorola and SPARC, unlike Intel). */ #if defined AC_APPLE_UNIVERSAL_BUILD # if defined __BIG_ENDIAN__ # define WORDS_BIGENDIAN 1 # endif #else # ifndef WORDS_BIGENDIAN /* # undef WORDS_BIGENDIAN */ # endif #endif /* Number of bits in a file offset, on hosts where this is settable. */ /* #undef _FILE_OFFSET_BITS */ /* Define for large files, on AIX-style hosts. */ /* #undef _LARGE_FILES */ #ifdef ANDROID #define Drawable unsigned int #endif intel-driver-1.3.0/src/dso_utils.c000066400000000000000000000056551231401140700170630ustar00rootroot00000000000000/* * Copyright (C) 2012 Intel Corporation. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #define _GNU_SOURCE 1 #include #include #include #include "dso_utils.h" struct dso_handle { void *handle; }; /* Opens the named shared library */ struct dso_handle * dso_open(const char *path) { struct dso_handle *h; h = calloc(1, sizeof(*h)); if (!h) return NULL; if (path) { h->handle = dlopen(path, RTLD_LAZY|RTLD_LOCAL); if (!h->handle) goto error; } else h->handle = RTLD_DEFAULT; return h; error: dso_close(h); return NULL; } /* Closes and disposed any allocated data */ void dso_close(struct dso_handle *h) { if (!h) return; if (h->handle) { if (h->handle != RTLD_DEFAULT) dlclose(h->handle); h->handle = NULL; } free(h); } /* Load symbol into the supplied location */ static bool get_symbol(struct dso_handle *h, void *func_vptr, const char *name) { dso_generic_func func, * const func_ptr = func_vptr; const char *error; dlerror(); func = (dso_generic_func)dlsym(h->handle, name); error = dlerror(); if (error) { fprintf(stderr, "error: failed to resolve %s(): %s\n", name, error); return false; } *func_ptr = func; return true; } /* Loads symbols into the supplied vtable */ bool dso_get_symbols( struct dso_handle *h, void *vtable, unsigned int vtable_length, const struct dso_symbol *symbols ) { const struct dso_symbol *s; for (s = symbols; s->name != NULL; s++) { if (s->offset + sizeof(dso_generic_func) > vtable_length) return false; if (!get_symbol(h, ((char *)vtable) + s->offset, s->name)) return false; } return true; } intel-driver-1.3.0/src/dso_utils.h000066400000000000000000000046341231401140700170640ustar00rootroot00000000000000/* * Copyright (C) 2012 Intel Corporation. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef DSO_UTILS_H #define DSO_UTILS_H #include /** Generic pointer to function. */ typedef void (*dso_generic_func)(void); /** Library handle (opaque). */ struct dso_handle; /** Symbol lookup table. */ struct dso_symbol { /** Symbol name */ const char *name; /** Offset into the supplied vtable where symbol is to be loaded. */ unsigned int offset; }; /** * Opens the named shared library. * * @param[in] path the library name, or NULL to lookup into loaded libraries * @return the newly allocated library handle */ struct dso_handle * dso_open(const char *path); /** Closes and disposed any allocated data. */ void dso_close(struct dso_handle *h); /** * Loads symbols into the supplied vtable. * * @param[in] handle the DSO handle * @param[in] vtable the function table to fill in * @param[in] vtable_length the size (in bytes) of the function table * @param[in] symbols the NULL terminated array of symbols to lookup * @return true on success, false otherwise **/ bool dso_get_symbols( struct dso_handle *h, void *vtable, unsigned int vtable_length, const struct dso_symbol *symbols ); #endif /* DSO_UTILS_H */ intel-driver-1.3.0/src/gen6_mfc.c000066400000000000000000001727701231401140700165450ustar00rootroot00000000000000/* * Copyright © 2010-2011 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Zhou Chang * */ #include #include #include #include #include #include "intel_batchbuffer.h" #include "i965_defines.h" #include "i965_structs.h" #include "i965_drv_video.h" #include "i965_encoder.h" #include "i965_encoder_utils.h" #include "gen6_mfc.h" #include "gen6_vme.h" #include "intel_media.h" #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7) #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index) static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = { #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b" }; static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = { #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b" }; static struct i965_kernel gen6_mfc_kernels[] = { { "MFC AVC INTRA BATCHBUFFER ", MFC_BATCHBUFFER_AVC_INTRA, gen6_mfc_batchbuffer_avc_intra, sizeof(gen6_mfc_batchbuffer_avc_intra), NULL }, { "MFC AVC INTER BATCHBUFFER ", MFC_BATCHBUFFER_AVC_INTER, gen6_mfc_batchbuffer_avc_inter, sizeof(gen6_mfc_batchbuffer_avc_inter), NULL }, }; static void gen6_mfc_pipe_mode_select(VADriverContextP ctx, int standard_select, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; assert(standard_select == MFX_FORMAT_AVC); BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2)); OUT_BCS_BATCH(batch, (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/ ((!!mfc_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */ ((!!mfc_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */ (0 << 7) | /* disable TLB prefectch */ (0 << 5) | /* not in stitch mode */ (1 << 4) | /* encoding mode */ (2 << 0)); /* Standard Select: AVC */ OUT_BCS_BATCH(batch, (0 << 20) | /* round flag in PB slice */ (0 << 19) | /* round flag in Intra8x8 */ (0 << 7) | /* expand NOA bus flag */ (1 << 6) | /* must be 1 */ (0 << 5) | /* disable clock gating for NOA */ (0 << 4) | /* terminate if AVC motion and POC table error occurs */ (0 << 3) | /* terminate if AVC mbdata error occurs */ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ (0 << 1) | /* AVC long field motion vector */ (0 << 0)); /* always calculate AVC ILDB boundary strength */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, ((mfc_context->surface_state.height - 1) << 19) | ((mfc_context->surface_state.width - 1) << 6)); OUT_BCS_BATCH(batch, (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */ (0 << 22) | /* surface object control state, FIXME??? */ ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */ (0 << 2) | /* must be 0 for interleave U/V */ (1 << 1) | /* must be y-tiled */ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */ OUT_BCS_BATCH(batch, (0 << 16) | /* must be 0 for interleave U/V */ (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } void gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int i; BEGIN_BCS_BATCH(batch, 24); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2)); if (mfc_context->pre_deblocking_output.bo) OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); /* pre output addr */ if (mfc_context->post_deblocking_output.bo) OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* post output addr */ else OUT_BCS_BATCH(batch, 0); OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* uncompressed data */ OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* StreamOut data*/ OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* 7..22 Reference pictures*/ for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) { if ( mfc_context->reference_surfaces[i].bo != NULL) { OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); } else { OUT_BCS_BATCH(batch, 0); } } OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* Macroblock status buffer*/ ADVANCE_BCS_BATCH(batch); } static void gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* MFX Indirect MV Object Base Address */ OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /*MFC Indirect PAK-BSE Object Base Address for Encoder*/ OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, mfc_context->mfc_indirect_pak_bse_object.end_offset); ADVANCE_BCS_BATCH(batch); } void gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2)); OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; BEGIN_BCS_BATCH(batch, 13); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2)); OUT_BCS_BATCH(batch, ((width_in_mbs * height_in_mbs) & 0xFFFF)); OUT_BCS_BATCH(batch, (height_in_mbs << 16) | (width_in_mbs << 0)); OUT_BCS_BATCH(batch, (0 << 24) | /*Second Chroma QP Offset*/ (0 << 16) | /*Chroma QP Offset*/ (0 << 14) | /*Max-bit conformance Intra flag*/ (0 << 13) | /*Max Macroblock size conformance Inter flag*/ (1 << 12) | /*Should always be written as "1" */ (0 << 10) | /*QM Preset FLag */ (0 << 8) | /*Image Structure*/ (0 << 0) ); /*Current Decoed Image Frame Store ID, reserved in Encode mode*/ OUT_BCS_BATCH(batch, (400 << 16) | /*Mininum Frame size*/ (0 << 15) | /*Disable reading of Macroblock Status Buffer*/ (0 << 14) | /*Load BitStream Pointer only once, 1 slic 1 frame*/ (0 << 13) | /*CABAC 0 word insertion test enable*/ (1 << 12) | /*MVUnpackedEnable,compliant to DXVA*/ (1 << 10) | /*Chroma Format IDC, 4:2:0*/ (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/ (0 << 6) | /*Only valid for VLD decoding mode*/ (0 << 5) | /*Constrained Intra Predition Flag, from PPS*/ (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4) | /*Direct 8x8 inference flag*/ (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/ (1 << 2) | /*Frame MB only flag*/ (0 << 1) | /*MBAFF mode is in active*/ (0 << 0) ); /*Field picture flag*/ OUT_BCS_BATCH(batch, (1<<16) | /*Frame Size Rate Control Flag*/ (1<<12) | (1<<9) | /*MB level Rate Control Enabling Flag*/ (1 << 3) | /*FrameBitRateMinReportMask*/ (1 << 2) | /*FrameBitRateMaxReportMask*/ (1 << 1) | /*InterMBMaxSizeReportMask*/ (1 << 0) ); /*IntraMBMaxSizeReportMask*/ OUT_BCS_BATCH(batch, /*Inter and Intra Conformance Max size limit*/ (0x0600 << 16) | /*InterMbMaxSz 192 Byte*/ (0x0800) ); /*IntraMbMaxSz 256 Byte*/ OUT_BCS_BATCH(batch, 0x00000000); /*Reserved : MBZReserved*/ OUT_BCS_BATCH(batch, 0x01020304); /*Slice QP Delta for bitrate control*/ OUT_BCS_BATCH(batch, 0xFEFDFCFB); OUT_BCS_BATCH(batch, 0x80601004); /*MAX = 128KB, MIN = 64KB*/ OUT_BCS_BATCH(batch, 0x00800001); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int i; BEGIN_BCS_BATCH(batch, 69); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2)); /* Reference frames and Current frames */ for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) { if ( mfc_context->direct_mv_buffers[i].bo != NULL) { OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } else { OUT_BCS_BATCH(batch, 0); } } /* POL list */ for(i = 0; i < 32; i++) { OUT_BCS_BATCH(batch, i/2); } OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfc_avc_slice_state(VADriverContextP ctx, VAEncPictureParameterBufferH264 *pic_param, VAEncSliceParameterBufferH264 *slice_param, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int rate_control_enable, int qp, struct intel_batchbuffer *batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; int beginmb = slice_param->macroblock_address; int endmb = beginmb + slice_param->num_macroblocks; int beginx = beginmb % width_in_mbs; int beginy = beginmb / width_in_mbs; int nextx = endmb % width_in_mbs; int nexty = endmb / width_in_mbs; int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); int last_slice = (endmb == (width_in_mbs * height_in_mbs)); int maxQpN, maxQpP; unsigned char correct[6], grow, shrink; int i; int weighted_pred_idc = 0; unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom; unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom; int num_ref_l0 = 0, num_ref_l1 = 0; if (batch == NULL) batch = encoder_context->base.batch; if (slice_type == SLICE_TYPE_I) { luma_log2_weight_denom = 0; chroma_log2_weight_denom = 0; } else if (slice_type == SLICE_TYPE_P) { weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag; num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1; if (slice_param->num_ref_idx_active_override_flag) num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; } else if (slice_type == SLICE_TYPE_B) { weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc; num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1; num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1; if (slice_param->num_ref_idx_active_override_flag) { num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1; } if (weighted_pred_idc == 2) { /* 8.4.3 - Derivation process for prediction weights (8-279) */ luma_log2_weight_denom = 5; chroma_log2_weight_denom = 5; } } maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier; maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier; for (i = 0; i < 6; i++) correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i]; grow = mfc_context->bit_rate_control_context[slice_type].GrowInit + (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4); shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit + (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4); BEGIN_BCS_BATCH(batch, 11);; OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) ); OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/ OUT_BCS_BATCH(batch, (num_ref_l0 << 16) | (num_ref_l1 << 24) | (chroma_log2_weight_denom << 8) | (luma_log2_weight_denom << 0)); OUT_BCS_BATCH(batch, (weighted_pred_idc << 30) | (slice_param->direct_spatial_mv_pred_flag<<29) | /*Direct Prediction Type*/ (slice_param->disable_deblocking_filter_idc << 27) | (slice_param->cabac_init_idc << 24) | (qp<<16) | /*Slice Quantization Parameter*/ ((slice_param->slice_beta_offset_div2 & 0xf) << 8) | ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0)); OUT_BCS_BATCH(batch, (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/ (beginx << 16) | slice_param->macroblock_address ); OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/ OUT_BCS_BATCH(batch, (0/*rate_control_enable*/ << 31) | /*in CBR mode RateControlCounterEnable = enable*/ (1 << 30) | /*ResetRateControlCounter*/ (0 << 28) | /*RC Triggle Mode = Always Rate Control*/ (4 << 24) | /*RC Stable Tolerance, middle level*/ (0/*rate_control_enable*/ << 23) | /*RC Panic Enable*/ (0 << 22) | /*QP mode, don't modfiy CBP*/ (0 << 21) | /*MB Type Direct Conversion Enabled*/ (0 << 20) | /*MB Type Skip Conversion Enabled*/ (last_slice << 19) | /*IsLastSlice*/ (0 << 18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/ (1 << 17) | /*HeaderPresentFlag*/ (1 << 16) | /*SliceData PresentFlag*/ (1 << 15) | /*TailPresentFlag*/ (1 << 13) | /*RBSP NAL TYPE*/ (0 << 12) ); /*CabacZeroWordInsertionEnable*/ OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset); OUT_BCS_BATCH(batch, (maxQpN << 24) | /*Target QP - 24 is lowest QP*/ (maxQpP << 16) | /*Target QP + 20 is highest QP*/ (shrink << 8) | (grow << 0)); OUT_BCS_BATCH(batch, (correct[5] << 20) | (correct[4] << 16) | (correct[3] << 12) | (correct[2] << 8) | (correct[1] << 4) | (correct[0] << 0)); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; int i; BEGIN_BCS_BATCH(batch, 58); OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56); OUT_BCS_BATCH(batch, 0xFF ) ; for( i = 0; i < 56; i++) { OUT_BCS_BATCH(batch, 0x10101010); } ADVANCE_BCS_BATCH(batch); } static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; int i; BEGIN_BCS_BATCH(batch, 113); OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2)); for(i = 0; i < 112;i++) { OUT_BCS_BATCH(batch, 0x10001000); } ADVANCE_BCS_BATCH(batch); } static void gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context, unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw, int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag, struct intel_batchbuffer *batch) { if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, lenght_in_dws + 2); OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2)); OUT_BCS_BATCH(batch, (0 << 16) | /* always start at offset 0 */ (data_bits_in_last_dw << 8) | (skip_emul_byte_count << 4) | (!!emulation_flag << 3) | ((!!is_last_header) << 2) | ((!!is_end_of_slice) << 1) | (0 << 0)); /* FIXME: ??? */ intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4); ADVANCE_BCS_BATCH(batch); } void gen6_mfc_init(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; dri_bo *bo; int i; int width_in_mbs = 0; int height_in_mbs = 0; int slice_batchbuffer_size; if (encoder_context->codec == CODEC_H264) { VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; width_in_mbs = pSequenceParameter->picture_width_in_mbs; height_in_mbs = pSequenceParameter->picture_height_in_mbs; } else { VAEncSequenceParameterBufferMPEG2 *pSequenceParameter = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; assert(encoder_context->codec == CODEC_MPEG2); width_in_mbs = ALIGN(pSequenceParameter->picture_width, 16) / 16; height_in_mbs = ALIGN(pSequenceParameter->picture_height, 16) / 16; } slice_batchbuffer_size = 64 * width_in_mbs * height_in_mbs + 4096 + (SLICE_HEADER + SLICE_TAIL) * encode_state->num_slice_params_ext; /*Encode common setup for MFC*/ dri_bo_unreference(mfc_context->post_deblocking_output.bo); mfc_context->post_deblocking_output.bo = NULL; dri_bo_unreference(mfc_context->pre_deblocking_output.bo); mfc_context->pre_deblocking_output.bo = NULL; dri_bo_unreference(mfc_context->uncompressed_picture_source.bo); mfc_context->uncompressed_picture_source.bo = NULL; dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo); mfc_context->mfc_indirect_pak_bse_object.bo = NULL; for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){ if ( mfc_context->direct_mv_buffers[i].bo != NULL); dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo); mfc_context->direct_mv_buffers[i].bo = NULL; } for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){ if (mfc_context->reference_surfaces[i].bo != NULL) dri_bo_unreference(mfc_context->reference_surfaces[i].bo); mfc_context->reference_surfaces[i].bo = NULL; } dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", width_in_mbs * 64, 64); assert(bo); mfc_context->intra_row_store_scratch_buffer.bo = bo; dri_bo_unreference(mfc_context->macroblock_status_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", width_in_mbs * height_in_mbs * 16, 64); assert(bo); mfc_context->macroblock_status_buffer.bo = bo; dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */ 64); assert(bo); mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo; dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", 128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */ 0x1000); assert(bo); mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo; dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo); mfc_context->mfc_batchbuffer_surface.bo = NULL; dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo); mfc_context->aux_batchbuffer_surface.bo = NULL; if (mfc_context->aux_batchbuffer) intel_batchbuffer_free(mfc_context->aux_batchbuffer); mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, slice_batchbuffer_size); mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer; dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo); mfc_context->aux_batchbuffer_surface.pitch = 16; mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16; mfc_context->aux_batchbuffer_surface.size_block = 16; i965_gpe_context_init(ctx, &mfc_context->gpe_context); } static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context); mfc_context->set_surface_state(ctx, encoder_context); mfc_context->ind_obj_base_addr_state(ctx, encoder_context); gen6_mfc_pipe_buf_addr_state(ctx, encoder_context); gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context); mfc_context->avc_img_state(ctx, encode_state, encoder_context); mfc_context->avc_qm_state(ctx, encoder_context); mfc_context->avc_fqm_state(ctx, encoder_context); gen6_mfc_avc_directmode_state(ctx, encoder_context); intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context); } VAStatus gen6_mfc_run(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; intel_batchbuffer_flush(batch); //run the pipeline return VA_STATUS_SUCCESS; } VAStatus gen6_mfc_stop(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int *encoded_bits_size) { VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VACodedBufferSegment *coded_buffer_segment; vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment); assert(vaStatus == VA_STATUS_SUCCESS); *encoded_bits_size = coded_buffer_segment->size * 8; i965_UnmapBuffer(ctx, pPicParameter->coded_buf); return VA_STATUS_SUCCESS; } #if __SOFTWARE__ static int gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg, struct intel_encoder_context *encoder_context, unsigned char target_mb_size, unsigned char max_mb_size, struct intel_batchbuffer *batch) { int len_in_dwords = 11; if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, len_in_dwords); OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, (0 << 24) | /* PackedMvNum, Debug*/ (0 << 20) | /* No motion vector */ (1 << 19) | /* CbpDcY */ (1 << 18) | /* CbpDcU */ (1 << 17) | /* CbpDcV */ (msg[0] & 0xFFFF) ); OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x); /* Code Block Pattern for Y*/ OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */ /*Stuff for Intra MB*/ OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/ OUT_BCS_BATCH(batch, msg[2]); OUT_BCS_BATCH(batch, msg[3]&0xFC); /*MaxSizeInWord and TargetSzieInWord*/ OUT_BCS_BATCH(batch, (max_mb_size << 24) | (target_mb_size << 16) ); ADVANCE_BCS_BATCH(batch); return len_in_dwords; } static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int *msg, unsigned int offset, struct intel_encoder_context *encoder_context, unsigned char target_mb_size,unsigned char max_mb_size, int slice_type, struct intel_batchbuffer *batch) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int len_in_dwords = 11; if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, len_in_dwords); OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); OUT_BCS_BATCH(batch, msg[2]); /* 32 MV*/ OUT_BCS_BATCH(batch, offset); OUT_BCS_BATCH(batch, msg[0]); OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/ OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ #if 0 if ( slice_type == SLICE_TYPE_B) { OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */ } else { OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ } #else OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ #endif /*Stuff for Inter MB*/ OUT_BCS_BATCH(batch, msg[1]); OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[0]); OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[1]); /*MaxSizeInWord and TargetSzieInWord*/ OUT_BCS_BATCH(batch, (max_mb_size << 24) | (target_mb_size << 16) ); ADVANCE_BCS_BATCH(batch); return len_in_dwords; } static void gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int slice_index, struct intel_batchbuffer *slice_batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer; unsigned int *msg = NULL, offset = 0; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs); int i,x,y; int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta; unsigned int rate_control_mode = encoder_context->rate_control_mode; unsigned char *slice_header = NULL; int slice_header_length_in_bits = 0; unsigned int tail_data[] = { 0x0, 0x0 }; int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type); int is_intra = slice_type == SLICE_TYPE_I; if (rate_control_mode == VA_RC_CBR) { qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY; pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp; } /* only support for 8-bit pixel bit-depth */ assert(pSequenceParameter->bit_depth_luma_minus8 == 0); assert(pSequenceParameter->bit_depth_chroma_minus8 == 0); assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52); assert(qp >= 0 && qp < 52); gen6_mfc_avc_slice_state(ctx, pPicParameter, pSliceParameter, encode_state, encoder_context, (rate_control_mode == VA_RC_CBR), qp, slice_batch); if ( slice_index == 0) intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header); // slice hander mfc_context->insert_object(ctx, encoder_context, (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f, 5, /* first 5 bytes are start code + nal unit type */ 1, 0, 1, slice_batch); dri_bo_map(vme_context->vme_output.bo , 1); msg = (unsigned int *)vme_context->vme_output.bo->virtual; if (is_intra) { msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS; } else { msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS; msg += 32; /* the first 32 DWs are MVs */ offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES; } for (i = pSliceParameter->macroblock_address; i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) { int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) ); x = i % width_in_mbs; y = i / width_in_mbs; if (is_intra) { assert(msg); gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch); msg += INTRA_VME_OUTPUT_IN_DWS; } else { if (msg[0] & INTRA_MB_FLAG_MASK) { gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch); } else { gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, slice_type, slice_batch); } msg += INTER_VME_OUTPUT_IN_DWS; offset += INTER_VME_OUTPUT_IN_BYTES; } } dri_bo_unmap(vme_context->vme_output.bo); if ( last_slice ) { mfc_context->insert_object(ctx, encoder_context, tail_data, 2, 8, 2, 1, 1, 0, slice_batch); } else { mfc_context->insert_object(ctx, encoder_context, tail_data, 1, 8, 1, 1, 1, 0, slice_batch); } free(slice_header); } static dri_bo * gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct intel_batchbuffer *batch;; dri_bo *batch_bo; int i; batch = mfc_context->aux_batchbuffer; batch_bo = batch->buffer; for (i = 0; i < encode_state->num_slice_params_ext; i++) { gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch); } intel_batchbuffer_align(batch, 8); BEGIN_BCS_BATCH(batch, 2); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END); ADVANCE_BCS_BATCH(batch); dri_bo_reference(batch_bo); intel_batchbuffer_free(batch); mfc_context->aux_batchbuffer = NULL; return batch_bo; } #else static void gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; assert(vme_context->vme_output.bo); mfc_context->buffer_suface_setup(ctx, &mfc_context->gpe_context, &vme_context->vme_output, BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT), SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT)); assert(mfc_context->aux_batchbuffer_surface.bo); mfc_context->buffer_suface_setup(ctx, &mfc_context->gpe_context, &mfc_context->aux_batchbuffer_surface, BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER), SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER)); } static void gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1; mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */ mfc_context->mfc_batchbuffer_surface.pitch = 16; mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr, "MFC batchbuffer", mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block, 0x1000); mfc_context->buffer_suface_setup(ctx, &mfc_context->gpe_context, &mfc_context->mfc_batchbuffer_surface, BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER), SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER)); } static void gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context); gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context); } static void gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_interface_descriptor_data *desc; int i; dri_bo *bo; bo = mfc_context->gpe_context.idrt.bo; dri_bo_map(bo, 1); assert(bo->virtual); desc = bo->virtual; for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) { struct i965_kernel *kernel; kernel = &mfc_context->gpe_context.kernels[i]; assert(sizeof(*desc) == 32); /*Setup the descritor table*/ memset(desc, 0, sizeof(*desc)); desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6); desc->desc2.sampler_count = 0; desc->desc2.sampler_state_pointer = 0; desc->desc3.binding_table_entry_count = 2; desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5); desc->desc4.constant_urb_entry_read_offset = 0; desc->desc4.constant_urb_entry_read_length = 4; /*kernel start*/ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0), kernel->bo); desc++; } dri_bo_unmap(bo); } static void gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; (void)mfc_context; } static void gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch, int index, int head_offset, int batchbuffer_offset, int head_size, int tail_size, int number_mb_cmds, int first_object, int last_object, int last_slice, int mb_x, int mb_y, int width_in_mbs, int qp, unsigned int ref_index[2]) { BEGIN_BATCH(batch, 14); OUT_BATCH(batch, CMD_MEDIA_OBJECT | (14 - 2)); OUT_BATCH(batch, index); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /*inline data */ OUT_BATCH(batch, head_offset); OUT_BATCH(batch, batchbuffer_offset); OUT_BATCH(batch, head_size << 16 | tail_size); OUT_BATCH(batch, number_mb_cmds << 16 | first_object << 2 | last_object << 1 | last_slice); OUT_BATCH(batch, mb_y << 8 | mb_x); OUT_BATCH(batch, qp << 16 | width_in_mbs); OUT_BATCH(batch, ref_index[0]); OUT_BATCH(batch, ref_index[1]); ADVANCE_BATCH(batch); } static void gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx, struct intel_encoder_context *encoder_context, VAEncSliceParameterBufferH264 *slice_param, int head_offset, unsigned short head_size, unsigned short tail_size, int batchbuffer_offset, int qp, int last_slice) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int total_mbs = slice_param->num_macroblocks; int number_mb_cmds = 128; int starting_mb = 0; int last_object = 0; int first_object = 1; int i; int mb_x, mb_y; int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER; for (i = 0; i < total_mbs / number_mb_cmds; i++) { last_object = (total_mbs - starting_mb) == number_mb_cmds; mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs; mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs; assert(mb_x <= 255 && mb_y <= 255); starting_mb += number_mb_cmds; gen6_mfc_batchbuffer_emit_object_command(batch, index, head_offset, batchbuffer_offset, head_size, tail_size, number_mb_cmds, first_object, last_object, last_slice, mb_x, mb_y, width_in_mbs, qp, vme_context->ref_index_in_mb); if (first_object) { head_offset += head_size; batchbuffer_offset += head_size; } if (last_object) { head_offset += tail_size; batchbuffer_offset += tail_size; } batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD; first_object = 0; } if (!last_object) { last_object = 1; number_mb_cmds = total_mbs % number_mb_cmds; mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs; mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs; assert(mb_x <= 255 && mb_y <= 255); starting_mb += number_mb_cmds; gen6_mfc_batchbuffer_emit_object_command(batch, index, head_offset, batchbuffer_offset, head_size, tail_size, number_mb_cmds, first_object, last_object, last_slice, mb_x, mb_y, width_in_mbs, qp, vme_context->ref_index_in_mb); } } /* * return size in Owords (16bytes) */ static int gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int slice_index, int batchbuffer_offset) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs); int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta; unsigned int rate_control_mode = encoder_context->rate_control_mode; unsigned char *slice_header = NULL; int slice_header_length_in_bits = 0; unsigned int tail_data[] = { 0x0, 0x0 }; long head_offset; int old_used = intel_batchbuffer_used_size(slice_batch), used; unsigned short head_size, tail_size; int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type); if (rate_control_mode == VA_RC_CBR) { qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY; pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp; } /* only support for 8-bit pixel bit-depth */ assert(pSequenceParameter->bit_depth_luma_minus8 == 0); assert(pSequenceParameter->bit_depth_chroma_minus8 == 0); assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52); assert(qp >= 0 && qp < 52); head_offset = old_used / 16; gen6_mfc_avc_slice_state(ctx, pPicParameter, pSliceParameter, encode_state, encoder_context, (rate_control_mode == VA_RC_CBR), qp, slice_batch); if (slice_index == 0) intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header); // slice hander mfc_context->insert_object(ctx, encoder_context, (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f, 5, /* first 5 bytes are start code + nal unit type */ 1, 0, 1, slice_batch); free(slice_header); intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */ used = intel_batchbuffer_used_size(slice_batch); head_size = (used - old_used) / 16; old_used = used; /* tail */ if (last_slice) { mfc_context->insert_object(ctx, encoder_context, tail_data, 2, 8, 2, 1, 1, 0, slice_batch); } else { mfc_context->insert_object(ctx, encoder_context, tail_data, 1, 8, 1, 1, 1, 0, slice_batch); } intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */ used = intel_batchbuffer_used_size(slice_batch); tail_size = (used - old_used) / 16; gen6_mfc_avc_batchbuffer_slice_command(ctx, encoder_context, pSliceParameter, head_offset, head_size, tail_size, batchbuffer_offset, qp, last_slice); return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD; } static void gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct intel_batchbuffer *batch = encoder_context->base.batch; int i, size, offset = 0; intel_batchbuffer_start_atomic(batch, 0x4000); gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch); for ( i = 0; i < encode_state->num_slice_params_ext; i++) { size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset); offset += size; } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static void gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context); gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context); gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context); gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context); } static dri_bo * gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context); dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo); return mfc_context->mfc_batchbuffer_surface.bo; } #endif static void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; dri_bo *slice_batch_bo; if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) { fprintf(stderr, "Current VA driver don't support interlace mode!\n"); assert(0); return; } #if __SOFTWARE__ slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context); #else slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context); #endif // begin programing intel_batchbuffer_start_atomic_bcs(batch, 0x4000); intel_batchbuffer_emit_mi_flush(batch); // picture level programing gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context); BEGIN_BCS_BATCH(batch, 2); OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8)); OUT_BCS_RELOC(batch, slice_batch_bo, I915_GEM_DOMAIN_COMMAND, 0, 0); ADVANCE_BCS_BATCH(batch); // end programing intel_batchbuffer_end_atomic(batch); dri_bo_unreference(slice_batch_bo); } VAStatus gen6_mfc_avc_encode_picture(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; unsigned int rate_control_mode = encoder_context->rate_control_mode; int current_frame_bits_size; int sts; for (;;) { gen6_mfc_init(ctx, encode_state, encoder_context); intel_mfc_avc_prepare(ctx, encode_state, encoder_context); /*Programing bcs pipeline*/ gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline gen6_mfc_run(ctx, encode_state, encoder_context); if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) { gen6_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size); sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size); if (sts == BRC_NO_HRD_VIOLATION) { intel_mfc_hrd_context_update(encode_state, mfc_context); break; } else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) { if (!mfc_context->hrd.violation_noted) { fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow"); mfc_context->hrd.violation_noted = 1; } return VA_STATUS_SUCCESS; } } else { break; } } return VA_STATUS_SUCCESS; } VAStatus gen6_mfc_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { VAStatus vaStatus; switch (profile) { case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context); break; /* FIXME: add for other profile */ default: vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE; break; } return vaStatus; } void gen6_mfc_context_destroy(void *context) { struct gen6_mfc_context *mfc_context = context; int i; dri_bo_unreference(mfc_context->post_deblocking_output.bo); mfc_context->post_deblocking_output.bo = NULL; dri_bo_unreference(mfc_context->pre_deblocking_output.bo); mfc_context->pre_deblocking_output.bo = NULL; dri_bo_unreference(mfc_context->uncompressed_picture_source.bo); mfc_context->uncompressed_picture_source.bo = NULL; dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo); mfc_context->mfc_indirect_pak_bse_object.bo = NULL; for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){ dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo); mfc_context->direct_mv_buffers[i].bo = NULL; } dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo); mfc_context->intra_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(mfc_context->macroblock_status_buffer.bo); mfc_context->macroblock_status_buffer.bo = NULL; dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo); mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo); mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){ dri_bo_unreference(mfc_context->reference_surfaces[i].bo); mfc_context->reference_surfaces[i].bo = NULL; } i965_gpe_context_destroy(&mfc_context->gpe_context); dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo); mfc_context->mfc_batchbuffer_surface.bo = NULL; dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo); mfc_context->aux_batchbuffer_surface.bo = NULL; if (mfc_context->aux_batchbuffer) intel_batchbuffer_free(mfc_context->aux_batchbuffer); mfc_context->aux_batchbuffer = NULL; free(mfc_context); } Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context)); mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS; mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data); mfc_context->gpe_context.curbe.length = 32 * 4; mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1; mfc_context->gpe_context.vfe_state.num_urb_entries = 16; mfc_context->gpe_context.vfe_state.gpgpu_mode = 0; mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1; mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1; i965_gpe_load_kernels(ctx, &mfc_context->gpe_context, gen6_mfc_kernels, NUM_MFC_KERNEL); mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select; mfc_context->set_surface_state = gen6_mfc_surface_state; mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state; mfc_context->avc_img_state = gen6_mfc_avc_img_state; mfc_context->avc_qm_state = gen6_mfc_avc_qm_state; mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state; mfc_context->insert_object = gen6_mfc_avc_insert_object; mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup; encoder_context->mfc_context = mfc_context; encoder_context->mfc_context_destroy = gen6_mfc_context_destroy; encoder_context->mfc_pipeline = gen6_mfc_pipeline; encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare; return True; } intel-driver-1.3.0/src/gen6_mfc.h000066400000000000000000000222721231401140700165410ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Zhou Chang * */ #ifndef _GEN6_MFC_H_ #define _GEN6_MFC_H_ #include #include #include #include "i965_gpe_utils.h" struct encode_state; #define MAX_MFC_REFERENCE_SURFACES 16 #define NUM_MFC_DMV_BUFFERS 34 #define INTRA_MB_FLAG_MASK 0x00002000 /* The space required for slice header SLICE_STATE + header. * Is it enough? */ #define SLICE_HEADER 80 /* the space required for slice tail. */ #define SLICE_TAIL 16 #define __SOFTWARE__ 0 #define MFC_BATCHBUFFER_AVC_INTRA 0 #define MFC_BATCHBUFFER_AVC_INTER 1 #define NUM_MFC_KERNEL 2 #define BIND_IDX_VME_OUTPUT 0 #define BIND_IDX_MFC_SLICE_HEADER 1 #define BIND_IDX_MFC_BATCHBUFFER 2 #define CMD_LEN_IN_OWORD 4 typedef enum _gen6_brc_status { BRC_NO_HRD_VIOLATION = 0, BRC_UNDERFLOW = 1, BRC_OVERFLOW = 2, BRC_UNDERFLOW_WITH_MAX_QP = 3, BRC_OVERFLOW_WITH_MIN_QP = 4, } gen6_brc_status; struct gen6_mfc_avc_surface_aux { dri_bo *dmv_top; dri_bo *dmv_bottom; }; struct gen6_mfc_context { struct { unsigned int width; unsigned int height; unsigned int w_pitch; unsigned int h_pitch; } surface_state; //MFX_PIPE_BUF_ADDR_STATE struct { dri_bo *bo; } post_deblocking_output; //OUTPUT: reconstructed picture struct { dri_bo *bo; } pre_deblocking_output; //OUTPUT: reconstructed picture with deblocked struct { dri_bo *bo; } uncompressed_picture_source; //INPUT: original compressed image struct { dri_bo *bo; } intra_row_store_scratch_buffer; //INTERNAL: struct { dri_bo *bo; } macroblock_status_buffer; //INTERNAL: struct { dri_bo *bo; } deblocking_filter_row_store_scratch_buffer; //INTERNAL: struct { dri_bo *bo; } reference_surfaces[MAX_MFC_REFERENCE_SURFACES]; //INTERNAL: refrence surfaces //MFX_IND_OBJ_BASE_ADDR_STATE struct{ dri_bo *bo; } mfc_indirect_mv_object; //INPUT: the blocks' mv info struct { dri_bo *bo; int offset; int end_offset; } mfc_indirect_pak_bse_object; //OUTPUT: the compressed bitstream //MFX_BSP_BUF_BASE_ADDR_STATE struct { dri_bo *bo; } bsd_mpc_row_store_scratch_buffer; //INTERNAL: //MFX_AVC_DIRECTMODE_STATE struct { dri_bo *bo; } direct_mv_buffers[NUM_MFC_DMV_BUFFERS]; //INTERNAL: 0-31 as input,32 and 33 as output //Bit rate tracking context struct { unsigned int QpPrimeY; unsigned int MaxQpNegModifier; unsigned int MaxQpPosModifier; unsigned char MaxSizeInWord; unsigned char TargetSizeInWord; unsigned char Correct[6]; unsigned char GrowInit; unsigned char GrowResistance; unsigned char ShrinkInit; unsigned char ShrinkResistance; unsigned int target_mb_size; unsigned int target_frame_size; } bit_rate_control_context[3]; //INTERNAL: for I, P, B frames struct { int mode; int gop_nums[3]; int target_frame_size[3]; // I,P,B double bits_per_frame; double qpf_rounding_accumulator; } brc; struct { double current_buffer_fullness; double target_buffer_fullness; double buffer_capacity; unsigned int buffer_size; unsigned int violation_noted; } hrd; //HRD control context struct { int i_bit_rate_value; int i_cpb_size_value; int i_initial_cpb_removal_delay; int i_cpb_removal_delay; int i_frame_number; int i_initial_cpb_removal_delay_length; int i_cpb_removal_delay_length; int i_dpb_output_delay_length; }vui_hrd; struct i965_gpe_context gpe_context; struct i965_buffer_surface mfc_batchbuffer_surface; struct intel_batchbuffer *aux_batchbuffer; struct i965_buffer_surface aux_batchbuffer_surface; void (*pipe_mode_select)(VADriverContextP ctx, int standard_select, struct intel_encoder_context *encoder_context); void (*set_surface_state)(VADriverContextP ctx, struct intel_encoder_context *encoder_context); void (*ind_obj_base_addr_state)(VADriverContextP ctx, struct intel_encoder_context *encoder_context); void (*avc_img_state)(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context); void (*avc_qm_state)(VADriverContextP ctx, struct intel_encoder_context *encoder_context); void (*avc_fqm_state)(VADriverContextP ctx, struct intel_encoder_context *encoder_context); void (*insert_object)(VADriverContextP ctx, struct intel_encoder_context *encoder_context, unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw, int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag, struct intel_batchbuffer *batch); void (*buffer_suface_setup)(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_buffer_surface *buffer_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); }; VAStatus gen6_mfc_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context); void gen6_mfc_context_destroy(void *context); extern Bool gen75_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context); extern int intel_mfc_update_hrd(struct encode_state *encode_state, struct gen6_mfc_context *mfc_context, int frame_bits); extern int intel_mfc_brc_postpack(struct encode_state *encode_state, struct gen6_mfc_context *mfc_context, int frame_bits); extern void intel_mfc_hrd_context_update(struct encode_state *encode_state, struct gen6_mfc_context *mfc_context); extern int intel_mfc_interlace_check(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context); extern void intel_mfc_brc_prepare(struct encode_state *encode_state, struct intel_encoder_context *encoder_context); extern void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, struct intel_batchbuffer *slice_batch); extern VAStatus intel_mfc_avc_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context); extern int intel_avc_enc_slice_type_fixup(int type); extern void intel_mfc_avc_ref_idx_state(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context); extern Bool gen8_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context); #endif /* _GEN6_MFC_BCS_H_ */ intel-driver-1.3.0/src/gen6_mfc_common.c000066400000000000000000001574661231401140700201220ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * Zhao Yakui * */ #include #include #include #include #include #include "intel_batchbuffer.h" #include "i965_defines.h" #include "i965_structs.h" #include "i965_drv_video.h" #include "i965_encoder.h" #include "i965_encoder_utils.h" #include "gen6_mfc.h" #include "gen6_vme.h" #include "intel_media.h" #define BRC_CLIP(x, min, max) \ { \ x = ((x > (max)) ? (max) : ((x < (min)) ? (min) : x)); \ } #define BRC_P_B_QP_DIFF 4 #define BRC_I_P_QP_DIFF 2 #define BRC_I_B_QP_DIFF (BRC_I_P_QP_DIFF + BRC_P_B_QP_DIFF) #define BRC_PWEIGHT 0.6 /* weight if P slice with comparison to I slice */ #define BRC_BWEIGHT 0.25 /* weight if B slice with comparison to I slice */ #define BRC_QP_MAX_CHANGE 5 /* maximum qp modification */ #define BRC_CY 0.1 /* weight for */ #define BRC_CX_UNDERFLOW 5. #define BRC_CX_OVERFLOW -4. #define BRC_PI_0_5 1.5707963267948966192313216916398 #ifndef HAVE_LOG2F #define log2f(x) (logf(x)/(float)M_LN2) #endif int intel_avc_enc_slice_type_fixup(int slice_type) { if (slice_type == SLICE_TYPE_SP || slice_type == SLICE_TYPE_P) slice_type = SLICE_TYPE_P; else if (slice_type == SLICE_TYPE_SI || slice_type == SLICE_TYPE_I) slice_type = SLICE_TYPE_I; else { if (slice_type != SLICE_TYPE_B) WARN_ONCE("Invalid slice type for H.264 encoding!\n"); slice_type = SLICE_TYPE_B; } return slice_type; } static void intel_mfc_bit_rate_control_context_init(struct encode_state *encode_state, struct gen6_mfc_context *mfc_context) { VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; float fps = pSequenceParameter->time_scale * 0.5 / pSequenceParameter->num_units_in_tick ; int inter_mb_size = pSequenceParameter->bits_per_second * 1.0 / (fps+4.0) / width_in_mbs / height_in_mbs; int intra_mb_size = inter_mb_size * 5.0; int i; mfc_context->bit_rate_control_context[SLICE_TYPE_I].target_mb_size = intra_mb_size; mfc_context->bit_rate_control_context[SLICE_TYPE_I].target_frame_size = intra_mb_size * width_in_mbs * height_in_mbs; mfc_context->bit_rate_control_context[SLICE_TYPE_P].target_mb_size = inter_mb_size; mfc_context->bit_rate_control_context[SLICE_TYPE_P].target_frame_size = inter_mb_size * width_in_mbs * height_in_mbs; mfc_context->bit_rate_control_context[SLICE_TYPE_B].target_mb_size = inter_mb_size; mfc_context->bit_rate_control_context[SLICE_TYPE_B].target_frame_size = inter_mb_size * width_in_mbs * height_in_mbs; for(i = 0 ; i < 3; i++) { mfc_context->bit_rate_control_context[i].QpPrimeY = 26; mfc_context->bit_rate_control_context[i].MaxQpNegModifier = 6; mfc_context->bit_rate_control_context[i].MaxQpPosModifier = 6; mfc_context->bit_rate_control_context[i].GrowInit = 6; mfc_context->bit_rate_control_context[i].GrowResistance = 4; mfc_context->bit_rate_control_context[i].ShrinkInit = 6; mfc_context->bit_rate_control_context[i].ShrinkResistance = 4; mfc_context->bit_rate_control_context[i].Correct[0] = 8; mfc_context->bit_rate_control_context[i].Correct[1] = 4; mfc_context->bit_rate_control_context[i].Correct[2] = 2; mfc_context->bit_rate_control_context[i].Correct[3] = 2; mfc_context->bit_rate_control_context[i].Correct[4] = 4; mfc_context->bit_rate_control_context[i].Correct[5] = 8; } mfc_context->bit_rate_control_context[SLICE_TYPE_I].TargetSizeInWord = (intra_mb_size + 16)/ 16; mfc_context->bit_rate_control_context[SLICE_TYPE_P].TargetSizeInWord = (inter_mb_size + 16)/ 16; mfc_context->bit_rate_control_context[SLICE_TYPE_B].TargetSizeInWord = (inter_mb_size + 16)/ 16; mfc_context->bit_rate_control_context[SLICE_TYPE_I].MaxSizeInWord = mfc_context->bit_rate_control_context[SLICE_TYPE_I].TargetSizeInWord * 1.5; mfc_context->bit_rate_control_context[SLICE_TYPE_P].MaxSizeInWord = mfc_context->bit_rate_control_context[SLICE_TYPE_P].TargetSizeInWord * 1.5; mfc_context->bit_rate_control_context[SLICE_TYPE_B].MaxSizeInWord = mfc_context->bit_rate_control_context[SLICE_TYPE_B].TargetSizeInWord * 1.5; } static void intel_mfc_brc_init(struct encode_state *encode_state, struct intel_encoder_context* encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; VAEncMiscParameterBuffer* pMiscParamHRD = (VAEncMiscParameterBuffer*)encode_state->misc_param[VAEncMiscParameterTypeHRD]->buffer; VAEncMiscParameterHRD* pParameterHRD = (VAEncMiscParameterHRD*)pMiscParamHRD->data; double bitrate = pSequenceParameter->bits_per_second; double framerate = (double)pSequenceParameter->time_scale /(2 * (double)pSequenceParameter->num_units_in_tick); int inum = 1, pnum = 0, bnum = 0; /* Gop structure: number of I, P, B frames in the Gop. */ int intra_period = pSequenceParameter->intra_period; int ip_period = pSequenceParameter->ip_period; double qp1_size = 0.1 * 8 * 3 * (pSequenceParameter->picture_width_in_mbs<<4) * (pSequenceParameter->picture_height_in_mbs<<4)/2; double qp51_size = 0.001 * 8 * 3 * (pSequenceParameter->picture_width_in_mbs<<4) * (pSequenceParameter->picture_height_in_mbs<<4)/2; double bpf; if (pSequenceParameter->ip_period) { pnum = (intra_period + ip_period - 1)/ip_period - 1; bnum = intra_period - inum - pnum; } mfc_context->brc.mode = encoder_context->rate_control_mode; mfc_context->brc.target_frame_size[SLICE_TYPE_I] = (int)((double)((bitrate * intra_period)/framerate) / (double)(inum + BRC_PWEIGHT * pnum + BRC_BWEIGHT * bnum)); mfc_context->brc.target_frame_size[SLICE_TYPE_P] = BRC_PWEIGHT * mfc_context->brc.target_frame_size[SLICE_TYPE_I]; mfc_context->brc.target_frame_size[SLICE_TYPE_B] = BRC_BWEIGHT * mfc_context->brc.target_frame_size[SLICE_TYPE_I]; mfc_context->brc.gop_nums[SLICE_TYPE_I] = inum; mfc_context->brc.gop_nums[SLICE_TYPE_P] = pnum; mfc_context->brc.gop_nums[SLICE_TYPE_B] = bnum; bpf = mfc_context->brc.bits_per_frame = bitrate/framerate; mfc_context->hrd.buffer_size = (double)pParameterHRD->buffer_size; mfc_context->hrd.current_buffer_fullness = (double)(pParameterHRD->initial_buffer_fullness < mfc_context->hrd.buffer_size)? pParameterHRD->initial_buffer_fullness: mfc_context->hrd.buffer_size/2.; mfc_context->hrd.target_buffer_fullness = (double)mfc_context->hrd.buffer_size/2.; mfc_context->hrd.buffer_capacity = (double)mfc_context->hrd.buffer_size/qp1_size; mfc_context->hrd.violation_noted = 0; if ((bpf > qp51_size) && (bpf < qp1_size)) { mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY = 51 - 50*(bpf - qp51_size)/(qp1_size - qp51_size); } else if (bpf >= qp1_size) mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY = 1; else if (bpf <= qp51_size) mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY = 51; mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY = mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY; mfc_context->bit_rate_control_context[SLICE_TYPE_B].QpPrimeY = mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY; BRC_CLIP(mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY, 1, 51); BRC_CLIP(mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY, 1, 51); BRC_CLIP(mfc_context->bit_rate_control_context[SLICE_TYPE_B].QpPrimeY, 1, 51); } int intel_mfc_update_hrd(struct encode_state *encode_state, struct gen6_mfc_context *mfc_context, int frame_bits) { double prev_bf = mfc_context->hrd.current_buffer_fullness; mfc_context->hrd.current_buffer_fullness -= frame_bits; if (mfc_context->hrd.buffer_size > 0 && mfc_context->hrd.current_buffer_fullness <= 0.) { mfc_context->hrd.current_buffer_fullness = prev_bf; return BRC_UNDERFLOW; } mfc_context->hrd.current_buffer_fullness += mfc_context->brc.bits_per_frame; if (mfc_context->hrd.buffer_size > 0 && mfc_context->hrd.current_buffer_fullness > mfc_context->hrd.buffer_size) { if (mfc_context->brc.mode == VA_RC_VBR) mfc_context->hrd.current_buffer_fullness = mfc_context->hrd.buffer_size; else { mfc_context->hrd.current_buffer_fullness = prev_bf; return BRC_OVERFLOW; } } return BRC_NO_HRD_VIOLATION; } int intel_mfc_brc_postpack(struct encode_state *encode_state, struct gen6_mfc_context *mfc_context, int frame_bits) { gen6_brc_status sts = BRC_NO_HRD_VIOLATION; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int slicetype = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type); int qpi = mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY; int qpp = mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY; int qpb = mfc_context->bit_rate_control_context[SLICE_TYPE_B].QpPrimeY; int qp; // quantizer of previously encoded slice of current type int qpn; // predicted quantizer for next frame of current type in integer format double qpf; // predicted quantizer for next frame of current type in float format double delta_qp; // QP correction int target_frame_size, frame_size_next; /* Notes: * x - how far we are from HRD buffer borders * y - how far we are from target HRD buffer fullness */ double x, y; double frame_size_alpha; qp = mfc_context->bit_rate_control_context[slicetype].QpPrimeY; target_frame_size = mfc_context->brc.target_frame_size[slicetype]; if (mfc_context->hrd.buffer_capacity < 5) frame_size_alpha = 0; else frame_size_alpha = (double)mfc_context->brc.gop_nums[slicetype]; if (frame_size_alpha > 30) frame_size_alpha = 30; frame_size_next = target_frame_size + (double)(target_frame_size - frame_bits) / (double)(frame_size_alpha + 1.); /* frame_size_next: avoiding negative number and too small value */ if ((double)frame_size_next < (double)(target_frame_size * 0.25)) frame_size_next = (int)((double)target_frame_size * 0.25); qpf = (double)qp * target_frame_size / frame_size_next; qpn = (int)(qpf + 0.5); if (qpn == qp) { /* setting qpn we round qpf making mistakes: now we are trying to compensate this */ mfc_context->brc.qpf_rounding_accumulator += qpf - qpn; if (mfc_context->brc.qpf_rounding_accumulator > 1.0) { qpn++; mfc_context->brc.qpf_rounding_accumulator = 0.; } else if (mfc_context->brc.qpf_rounding_accumulator < -1.0) { qpn--; mfc_context->brc.qpf_rounding_accumulator = 0.; } } /* making sure that QP is not changing too fast */ if ((qpn - qp) > BRC_QP_MAX_CHANGE) qpn = qp + BRC_QP_MAX_CHANGE; else if ((qpn - qp) < -BRC_QP_MAX_CHANGE) qpn = qp - BRC_QP_MAX_CHANGE; /* making sure that with QP predictions we did do not leave QPs range */ BRC_CLIP(qpn, 1, 51); /* checking wthether HRD compliance is still met */ sts = intel_mfc_update_hrd(encode_state, mfc_context, frame_bits); /* calculating QP delta as some function*/ x = mfc_context->hrd.target_buffer_fullness - mfc_context->hrd.current_buffer_fullness; if (x > 0) { x /= mfc_context->hrd.target_buffer_fullness; y = mfc_context->hrd.current_buffer_fullness; } else { x /= (mfc_context->hrd.buffer_size - mfc_context->hrd.target_buffer_fullness); y = mfc_context->hrd.buffer_size - mfc_context->hrd.current_buffer_fullness; } if (y < 0.01) y = 0.01; if (x > 1) x = 1; else if (x < -1) x = -1; delta_qp = BRC_QP_MAX_CHANGE*exp(-1/y)*sin(BRC_PI_0_5 * x); qpn = (int)(qpn + delta_qp + 0.5); /* making sure that with QP predictions we did do not leave QPs range */ BRC_CLIP(qpn, 1, 51); if (sts == BRC_NO_HRD_VIOLATION) { // no HRD violation /* correcting QPs of slices of other types */ if (slicetype == SLICE_TYPE_P) { if (abs(qpn + BRC_P_B_QP_DIFF - qpb) > 2) mfc_context->bit_rate_control_context[SLICE_TYPE_B].QpPrimeY += (qpn + BRC_P_B_QP_DIFF - qpb) >> 1; if (abs(qpn - BRC_I_P_QP_DIFF - qpi) > 2) mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY += (qpn - BRC_I_P_QP_DIFF - qpi) >> 1; } else if (slicetype == SLICE_TYPE_I) { if (abs(qpn + BRC_I_B_QP_DIFF - qpb) > 4) mfc_context->bit_rate_control_context[SLICE_TYPE_B].QpPrimeY += (qpn + BRC_I_B_QP_DIFF - qpb) >> 2; if (abs(qpn + BRC_I_P_QP_DIFF - qpp) > 2) mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY += (qpn + BRC_I_P_QP_DIFF - qpp) >> 2; } else { // SLICE_TYPE_B if (abs(qpn - BRC_P_B_QP_DIFF - qpp) > 2) mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY += (qpn - BRC_P_B_QP_DIFF - qpp) >> 1; if (abs(qpn - BRC_I_B_QP_DIFF - qpi) > 4) mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY += (qpn - BRC_I_B_QP_DIFF - qpi) >> 2; } BRC_CLIP(mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY, 1, 51); BRC_CLIP(mfc_context->bit_rate_control_context[SLICE_TYPE_P].QpPrimeY, 1, 51); BRC_CLIP(mfc_context->bit_rate_control_context[SLICE_TYPE_B].QpPrimeY, 1, 51); } else if (sts == BRC_UNDERFLOW) { // underflow if (qpn <= qp) qpn = qp + 1; if (qpn > 51) { qpn = 51; sts = BRC_UNDERFLOW_WITH_MAX_QP; //underflow with maxQP } } else if (sts == BRC_OVERFLOW) { if (qpn >= qp) qpn = qp - 1; if (qpn < 1) { // < 0 (?) overflow with minQP qpn = 1; sts = BRC_OVERFLOW_WITH_MIN_QP; // bit stuffing to be done } } mfc_context->bit_rate_control_context[slicetype].QpPrimeY = qpn; return sts; } static void intel_mfc_hrd_context_init(struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; unsigned int rate_control_mode = encoder_context->rate_control_mode; int target_bit_rate = pSequenceParameter->bits_per_second; // current we only support CBR mode. if (rate_control_mode == VA_RC_CBR) { mfc_context->vui_hrd.i_bit_rate_value = target_bit_rate >> 10; mfc_context->vui_hrd.i_cpb_size_value = (target_bit_rate * 8) >> 10; mfc_context->vui_hrd.i_initial_cpb_removal_delay = mfc_context->vui_hrd.i_cpb_size_value * 0.5 * 1024 / target_bit_rate * 90000; mfc_context->vui_hrd.i_cpb_removal_delay = 2; mfc_context->vui_hrd.i_frame_number = 0; mfc_context->vui_hrd.i_initial_cpb_removal_delay_length = 24; mfc_context->vui_hrd.i_cpb_removal_delay_length = 24; mfc_context->vui_hrd.i_dpb_output_delay_length = 24; } } void intel_mfc_hrd_context_update(struct encode_state *encode_state, struct gen6_mfc_context *mfc_context) { mfc_context->vui_hrd.i_frame_number++; } int intel_mfc_interlace_check(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncSliceParameterBufferH264 *pSliceParameter; int i; int mbCount = 0; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; for (i = 0; i < encode_state->num_slice_params_ext; i++) { pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[i]->buffer; mbCount += pSliceParameter->num_macroblocks; } if ( mbCount == ( width_in_mbs * height_in_mbs ) ) return 0; return 1; } void intel_mfc_brc_prepare(struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { unsigned int rate_control_mode = encoder_context->rate_control_mode; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; if (rate_control_mode == VA_RC_CBR) { assert(encoder_context->codec != CODEC_MPEG2); /*Programing bit rate control */ if ( mfc_context->bit_rate_control_context[SLICE_TYPE_I].MaxSizeInWord == 0 ) { intel_mfc_bit_rate_control_context_init(encode_state, mfc_context); intel_mfc_brc_init(encode_state, encoder_context); } /*Programing HRD control */ if ( mfc_context->vui_hrd.i_cpb_size_value == 0 ) intel_mfc_hrd_context_init(encode_state, encoder_context); } } void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, struct intel_batchbuffer *slice_batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SPS); unsigned int rate_control_mode = encoder_context->rate_control_mode; if (encode_state->packed_header_data[idx]) { VAEncPackedHeaderParameterBuffer *param = NULL; unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer; unsigned int length_in_bits; assert(encode_state->packed_header_param[idx]); param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer; length_in_bits = param->bit_length; mfc_context->insert_object(ctx, encoder_context, header_data, ALIGN(length_in_bits, 32) >> 5, length_in_bits & 0x1f, 5, /* FIXME: check it */ 0, 0, !param->has_emulation_bytes, slice_batch); } idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_PPS); if (encode_state->packed_header_data[idx]) { VAEncPackedHeaderParameterBuffer *param = NULL; unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer; unsigned int length_in_bits; assert(encode_state->packed_header_param[idx]); param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer; length_in_bits = param->bit_length; mfc_context->insert_object(ctx, encoder_context, header_data, ALIGN(length_in_bits, 32) >> 5, length_in_bits & 0x1f, 5, /* FIXME: check it */ 0, 0, !param->has_emulation_bytes, slice_batch); } idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SEI); if (encode_state->packed_header_data[idx]) { VAEncPackedHeaderParameterBuffer *param = NULL; unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer; unsigned int length_in_bits; assert(encode_state->packed_header_param[idx]); param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer; length_in_bits = param->bit_length; mfc_context->insert_object(ctx, encoder_context, header_data, ALIGN(length_in_bits, 32) >> 5, length_in_bits & 0x1f, 5, /* FIXME: check it */ 0, 0, !param->has_emulation_bytes, slice_batch); } else if (rate_control_mode == VA_RC_CBR) { // this is frist AU struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; unsigned char *sei_data = NULL; int length_in_bits = build_avc_sei_buffer_timing( mfc_context->vui_hrd.i_initial_cpb_removal_delay_length, mfc_context->vui_hrd.i_initial_cpb_removal_delay, 0, mfc_context->vui_hrd.i_cpb_removal_delay_length, mfc_context->vui_hrd.i_cpb_removal_delay * mfc_context->vui_hrd.i_frame_number, mfc_context->vui_hrd.i_dpb_output_delay_length, 0, &sei_data); mfc_context->insert_object(ctx, encoder_context, (unsigned int *)sei_data, ALIGN(length_in_bits, 32) >> 5, length_in_bits & 0x1f, 4, 0, 0, 1, slice_batch); free(sei_data); } } VAStatus intel_mfc_avc_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct object_surface *obj_surface; struct object_buffer *obj_buffer; GenAvcSurface *gen6_avc_surface; dri_bo *bo; VAStatus vaStatus = VA_STATUS_SUCCESS; int i, j, enable_avc_ildb = 0; VAEncSliceParameterBufferH264 *slice_param; struct i965_coded_buffer_segment *coded_buffer_segment; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; if (IS_GEN6(i965->intel.device_id)) { /* On the SNB it should be fixed to 128 for the DMV buffer */ width_in_mbs = 128; } for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb == 0; j++) { assert(encode_state->slice_params_ext && encode_state->slice_params_ext[j]->buffer); slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer; for (i = 0; i < encode_state->slice_params_ext[j]->num_elements; i++) { assert((slice_param->slice_type == SLICE_TYPE_I) || (slice_param->slice_type == SLICE_TYPE_SI) || (slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP) || (slice_param->slice_type == SLICE_TYPE_B)); if (slice_param->disable_deblocking_filter_idc != 1) { enable_avc_ildb = 1; break; } slice_param++; } } /*Setup all the input&output object*/ /* Setup current frame and current direct mv buffer*/ obj_surface = encode_state->reconstructed_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); if ( obj_surface->private_data == NULL) { gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1); gen6_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr, "Buffer", 68 * width_in_mbs * height_in_mbs, 64); gen6_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr, "Buffer", 68 * width_in_mbs * height_in_mbs, 64); assert(gen6_avc_surface->dmv_top); assert(gen6_avc_surface->dmv_bottom); obj_surface->private_data = (void *)gen6_avc_surface; obj_surface->free_private_data = (void *)gen_free_avc_surface; } gen6_avc_surface = (GenAvcSurface *) obj_surface->private_data; mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo = gen6_avc_surface->dmv_top; mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 1].bo = gen6_avc_surface->dmv_bottom; dri_bo_reference(gen6_avc_surface->dmv_top); dri_bo_reference(gen6_avc_surface->dmv_bottom); if (enable_avc_ildb) { mfc_context->post_deblocking_output.bo = obj_surface->bo; dri_bo_reference(mfc_context->post_deblocking_output.bo); } else { mfc_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(mfc_context->pre_deblocking_output.bo); } mfc_context->surface_state.width = obj_surface->orig_width; mfc_context->surface_state.height = obj_surface->orig_height; mfc_context->surface_state.w_pitch = obj_surface->width; mfc_context->surface_state.h_pitch = obj_surface->height; /* Setup reference frames and direct mv buffers*/ for(i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++) { obj_surface = encode_state->reference_objects[i]; if (obj_surface && obj_surface->bo) { mfc_context->reference_surfaces[i].bo = obj_surface->bo; dri_bo_reference(obj_surface->bo); /* Check DMV buffer */ if ( obj_surface->private_data == NULL) { gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1); gen6_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr, "Buffer", 68 * width_in_mbs * height_in_mbs, 64); gen6_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr, "Buffer", 68 * width_in_mbs * height_in_mbs, 64); assert(gen6_avc_surface->dmv_top); assert(gen6_avc_surface->dmv_bottom); obj_surface->private_data = gen6_avc_surface; obj_surface->free_private_data = gen_free_avc_surface; } gen6_avc_surface = (GenAvcSurface *) obj_surface->private_data; /* Setup DMV buffer */ mfc_context->direct_mv_buffers[i*2].bo = gen6_avc_surface->dmv_top; mfc_context->direct_mv_buffers[i*2+1].bo = gen6_avc_surface->dmv_bottom; dri_bo_reference(gen6_avc_surface->dmv_top); dri_bo_reference(gen6_avc_surface->dmv_bottom); } else { break; } } mfc_context->uncompressed_picture_source.bo = encode_state->input_yuv_object->bo; dri_bo_reference(mfc_context->uncompressed_picture_source.bo); obj_buffer = encode_state->coded_buf_object; bo = obj_buffer->buffer_store->bo; mfc_context->mfc_indirect_pak_bse_object.bo = bo; mfc_context->mfc_indirect_pak_bse_object.offset = I965_CODEDBUFFER_HEADER_SIZE; mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN(obj_buffer->size_element - 0x1000, 0x1000); dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo); dri_bo_map(bo, 1); coded_buffer_segment = (struct i965_coded_buffer_segment *)bo->virtual; coded_buffer_segment->mapped = 0; coded_buffer_segment->codec = encoder_context->codec; dri_bo_unmap(bo); return vaStatus; } /* * The LUT uses the pair of 4-bit units: (shift, base) structure. * 2^K * X = value . * So it is necessary to convert one cost into the nearest LUT format. * The derivation is: * 2^K *x = 2^n * (1 + deltaX) * k + log2(x) = n + log2(1 + deltaX) * log2(x) = n - k + log2(1 + deltaX) * As X is in the range of [1, 15] * 4 > n - k + log2(1 + deltaX) >= 0 * => n + log2(1 + deltaX) >= k > n - 4 + log2(1 + deltaX) * Then we can derive the corresponding K and get the nearest LUT format. */ int intel_format_lutvalue(int value, int max) { int ret; int logvalue, temp1, temp2; if (value <= 0) return 0; logvalue = (int)(log2f((float)value)); if (logvalue < 4) { ret = value; } else { int error, temp_value, base, j, temp_err; error = value; j = logvalue - 4 + 1; ret = -1; for(; j <= logvalue; j++) { if (j == 0) { base = value >> j; } else { base = (value + (1 << (j - 1)) - 1) >> j; } if (base >= 16) continue; temp_value = base << j; temp_err = abs(value - temp_value); if (temp_err < error) { error = temp_err; ret = (j << 4) | base; if (temp_err == 0) break; } } } temp1 = (ret & 0xf) << ((ret & 0xf0) >> 4); temp2 = (max & 0xf) << ((max & 0xf0) >> 4); if (temp1 > temp2) ret = max; return ret; } #define QP_MAX 52 static float intel_lambda_qp(int qp) { float value, lambdaf; value = qp; value = value / 6 - 2; if (value < 0) value = 0; lambdaf = roundf(powf(2, value)); return lambdaf; } void intel_vme_update_mbmv_cost(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int qp, m_cost, j, mv_count; uint8_t *vme_state_message = (uint8_t *)(vme_context->vme_state_message); float lambda, m_costf; int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); if (encoder_context->rate_control_mode == VA_RC_CQP) qp = pic_param->pic_init_qp + slice_param->slice_qp_delta; else qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY; if (vme_state_message == NULL) return; assert(qp <= QP_MAX); lambda = intel_lambda_qp(qp); if (slice_type == SLICE_TYPE_I) { vme_state_message[MODE_INTRA_16X16] = 0; m_cost = lambda * 4; vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f); m_cost = lambda * 16; vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f); m_cost = lambda * 3; vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost, 0x6f); } else { m_cost = 0; vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost, 0x6f); for (j = 1; j < 3; j++) { m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda; m_cost = (int)m_costf; vme_state_message[MODE_INTER_MV0 + j] = intel_format_lutvalue(m_cost, 0x6f); } mv_count = 3; for (j = 4; j <= 64; j *= 2) { m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda; m_cost = (int)m_costf; vme_state_message[MODE_INTER_MV0 + mv_count] = intel_format_lutvalue(m_cost, 0x6f); mv_count++; } if (qp <= 25) { vme_state_message[MODE_INTRA_16X16] = 0x4a; vme_state_message[MODE_INTRA_8X8] = 0x4a; vme_state_message[MODE_INTRA_4X4] = 0x4a; vme_state_message[MODE_INTRA_NONPRED] = 0x4a; vme_state_message[MODE_INTER_16X16] = 0x4a; vme_state_message[MODE_INTER_16X8] = 0x4a; vme_state_message[MODE_INTER_8X8] = 0x4a; vme_state_message[MODE_INTER_8X4] = 0x4a; vme_state_message[MODE_INTER_4X4] = 0x4a; vme_state_message[MODE_INTER_BWD] = 0x2a; return; } m_costf = lambda * 10; vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost, 0x8f); m_cost = lambda * 14; vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f); m_cost = lambda * 24; vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f); m_costf = lambda * 3.5; m_cost = m_costf; vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost, 0x6f); if (slice_type == SLICE_TYPE_P) { m_costf = lambda * 2.5; m_cost = m_costf; vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f); m_costf = lambda * 4; m_cost = m_costf; vme_state_message[MODE_INTER_16X8] = intel_format_lutvalue(m_cost, 0x8f); m_costf = lambda * 1.5; m_cost = m_costf; vme_state_message[MODE_INTER_8X8] = intel_format_lutvalue(m_cost, 0x6f); m_costf = lambda * 3; m_cost = m_costf; vme_state_message[MODE_INTER_8X4] = intel_format_lutvalue(m_cost, 0x6f); m_costf = lambda * 5; m_cost = m_costf; vme_state_message[MODE_INTER_4X4] = intel_format_lutvalue(m_cost, 0x6f); /* BWD is not used in P-frame */ vme_state_message[MODE_INTER_BWD] = 0; } else { m_costf = lambda * 2.5; m_cost = m_costf; vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f); m_costf = lambda * 5.5; m_cost = m_costf; vme_state_message[MODE_INTER_16X8] = intel_format_lutvalue(m_cost, 0x8f); m_costf = lambda * 3.5; m_cost = m_costf; vme_state_message[MODE_INTER_8X8] = intel_format_lutvalue(m_cost, 0x6f); m_costf = lambda * 5.0; m_cost = m_costf; vme_state_message[MODE_INTER_8X4] = intel_format_lutvalue(m_cost, 0x6f); m_costf = lambda * 6.5; m_cost = m_costf; vme_state_message[MODE_INTER_4X4] = intel_format_lutvalue(m_cost, 0x6f); m_costf = lambda * 1.5; m_cost = m_costf; vme_state_message[MODE_INTER_BWD] = intel_format_lutvalue(m_cost, 0x6f); } } } #define MB_SCOREBOARD_A (1 << 0) #define MB_SCOREBOARD_B (1 << 1) #define MB_SCOREBOARD_C (1 << 2) void gen7_vme_scoreboard_init(VADriverContextP ctx, struct gen6_vme_context *vme_context) { vme_context->gpe_context.vfe_desc5.scoreboard0.enable = 1; vme_context->gpe_context.vfe_desc5.scoreboard0.type = SCOREBOARD_STALLING; vme_context->gpe_context.vfe_desc5.scoreboard0.mask = (MB_SCOREBOARD_A | MB_SCOREBOARD_B | MB_SCOREBOARD_C); /* In VME prediction the current mb depends on the neighbour * A/B/C macroblock. So the left/up/up-right dependency should * be considered. */ vme_context->gpe_context.vfe_desc6.scoreboard1.delta_x0 = -1; vme_context->gpe_context.vfe_desc6.scoreboard1.delta_y0 = 0; vme_context->gpe_context.vfe_desc6.scoreboard1.delta_x1 = 0; vme_context->gpe_context.vfe_desc6.scoreboard1.delta_y1 = -1; vme_context->gpe_context.vfe_desc6.scoreboard1.delta_x2 = 1; vme_context->gpe_context.vfe_desc6.scoreboard1.delta_y2 = -1; vme_context->gpe_context.vfe_desc7.dword = 0; return; } /* check whether the mb of (x_index, y_index) is out of bound */ static inline int loop_in_bounds(int x_index, int y_index, int first_mb, int num_mb, int mb_width, int mb_height) { int mb_index; if (x_index < 0 || x_index >= mb_width) return -1; if (y_index < 0 || y_index >= mb_height) return -1; mb_index = y_index * mb_width + x_index; if (mb_index < first_mb || mb_index > (first_mb + num_mb)) return -1; return 0; } void gen7_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, int transform_8x8_mode_flag, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int mb_row; int s; unsigned int *command_ptr; #define USE_SCOREBOARD (1 << 21) dri_bo_map(vme_context->vme_batchbuffer.bo, 1); command_ptr = vme_context->vme_batchbuffer.bo->virtual; for (s = 0; s < encode_state->num_slice_params_ext; s++) { VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer; int first_mb = pSliceParameter->macroblock_address; int num_mb = pSliceParameter->num_macroblocks; unsigned int mb_intra_ub, score_dep; int x_outer, y_outer, x_inner, y_inner; int xtemp_outer = 0; x_outer = first_mb % mb_width; y_outer = first_mb / mb_width; mb_row = y_outer; for (; x_outer < (mb_width -2 ) && !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) { x_inner = x_outer; y_inner = y_outer; for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) { mb_intra_ub = 0; score_dep = 0; if (x_inner != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; score_dep |= MB_SCOREBOARD_A; } if (y_inner != mb_row) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; score_dep |= MB_SCOREBOARD_B; if (x_inner != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (x_inner != (mb_width -1)) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; score_dep |= MB_SCOREBOARD_C; } } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = USE_SCOREBOARD; /* Indirect data */ *command_ptr++ = 0; /* the (X, Y) term of scoreboard */ *command_ptr++ = ((y_inner << 16) | x_inner); *command_ptr++ = score_dep; /*inline data */ *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner); *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8)); x_inner -= 2; y_inner += 1; } x_outer += 1; } xtemp_outer = mb_width - 2; if (xtemp_outer < 0) xtemp_outer = 0; x_outer = xtemp_outer; y_outer = first_mb / mb_width; for (;!loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) { y_inner = y_outer; x_inner = x_outer; for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) { mb_intra_ub = 0; score_dep = 0; if (x_inner != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; score_dep |= MB_SCOREBOARD_A; } if (y_inner != mb_row) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; score_dep |= MB_SCOREBOARD_B; if (x_inner != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (x_inner != (mb_width -1)) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; score_dep |= MB_SCOREBOARD_C; } } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = USE_SCOREBOARD; /* Indirect data */ *command_ptr++ = 0; /* the (X, Y) term of scoreboard */ *command_ptr++ = ((y_inner << 16) | x_inner); *command_ptr++ = score_dep; /*inline data */ *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner); *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8)); x_inner -= 2; y_inner += 1; } x_outer++; if (x_outer >= mb_width) { y_outer += 1; x_outer = xtemp_outer; } } } *command_ptr++ = 0; *command_ptr++ = MI_BATCH_BUFFER_END; dri_bo_unmap(vme_context->vme_batchbuffer.bo); } static uint8_t intel_get_ref_idx_state_1(VAPictureH264 *va_pic, unsigned int frame_store_id) { unsigned int is_long_term = !!(va_pic->flags & VA_PICTURE_H264_LONG_TERM_REFERENCE); unsigned int is_top_field = !!(va_pic->flags & VA_PICTURE_H264_TOP_FIELD); unsigned int is_bottom_field = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD); return ((is_long_term << 6) | ((is_top_field ^ is_bottom_field ^ 1) << 5) | (frame_store_id << 1) | ((is_top_field ^ 1) & is_bottom_field)); } void intel_mfc_avc_ref_idx_state(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct intel_batchbuffer *batch = encoder_context->base.batch; int slice_type; struct object_surface *obj_surface; unsigned int fref_entry, bref_entry; int frame_index, i; VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; fref_entry = 0x80808080; bref_entry = 0x80808080; slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); if (slice_type == SLICE_TYPE_P || slice_type == SLICE_TYPE_B) { int ref_idx_l0 = (vme_context->ref_index_in_mb[0] & 0xff); if (ref_idx_l0 > 3) { WARN_ONCE("ref_idx_l0 is out of range\n"); ref_idx_l0 = 0; } obj_surface = vme_context->used_reference_objects[0]; frame_index = -1; for (i = 0; i < 16; i++) { if (obj_surface && obj_surface == encode_state->reference_objects[i]) { frame_index = i; break; } } if (frame_index == -1) { WARN_ONCE("RefPicList0 is not found in DPB!\n"); } else { int ref_idx_l0_shift = ref_idx_l0 * 8; fref_entry &= ~(0xFF << ref_idx_l0_shift); fref_entry += (intel_get_ref_idx_state_1(vme_context->used_references[0], frame_index) << ref_idx_l0_shift); } } if (slice_type == SLICE_TYPE_B) { int ref_idx_l1 = (vme_context->ref_index_in_mb[1] & 0xff); if (ref_idx_l1 > 3) { WARN_ONCE("ref_idx_l1 is out of range\n"); ref_idx_l1 = 0; } obj_surface = vme_context->used_reference_objects[1]; frame_index = -1; for (i = 0; i < 16; i++) { if (obj_surface && obj_surface == encode_state->reference_objects[i]) { frame_index = i; break; } } if (frame_index == -1) { WARN_ONCE("RefPicList1 is not found in DPB!\n"); } else { int ref_idx_l1_shift = ref_idx_l1 * 8; bref_entry &= ~(0xFF << ref_idx_l1_shift); bref_entry += (intel_get_ref_idx_state_1(vme_context->used_references[1], frame_index) << ref_idx_l1_shift); } } BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8); OUT_BCS_BATCH(batch, 0); //Select L0 OUT_BCS_BATCH(batch, fref_entry); //Only 1 reference for(i = 0; i < 7; i++) { OUT_BCS_BATCH(batch, 0x80808080); } ADVANCE_BCS_BATCH(batch); BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8); OUT_BCS_BATCH(batch, 1); //Select L1 OUT_BCS_BATCH(batch, bref_entry); //Only 1 reference for(i = 0; i < 7; i++) { OUT_BCS_BATCH(batch, 0x80808080); } ADVANCE_BCS_BATCH(batch); } void intel_vme_mpeg2_state_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; uint32_t *vme_state_message = (uint32_t *)(vme_context->vme_state_message); VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; uint32_t mv_x, mv_y; VAEncSliceParameterBufferMPEG2 *slice_param = NULL; VAEncPictureParameterBufferMPEG2 *pic_param = NULL; slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer; if (vme_context->mpeg2_level == MPEG2_LEVEL_LOW) { mv_x = 512; mv_y = 64; } else if (vme_context->mpeg2_level == MPEG2_LEVEL_MAIN) { mv_x = 1024; mv_y = 128; } else if (vme_context->mpeg2_level == MPEG2_LEVEL_HIGH) { mv_x = 2048; mv_y = 128; } else { WARN_ONCE("Incorrect Mpeg2 level setting!\n"); mv_x = 512; mv_y = 64; } pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; if (pic_param->picture_type != VAEncPictureTypeIntra) { int qp, m_cost, j, mv_count; float lambda, m_costf; slice_param = (VAEncSliceParameterBufferMPEG2 *) encode_state->slice_params_ext[0]->buffer; qp = slice_param->quantiser_scale_code; lambda = intel_lambda_qp(qp); /* No Intra prediction. So it is zero */ vme_state_message[MODE_INTRA_8X8] = 0; vme_state_message[MODE_INTRA_4X4] = 0; vme_state_message[MODE_INTER_MV0] = 0; for (j = 1; j < 3; j++) { m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda; m_cost = (int)m_costf; vme_state_message[MODE_INTER_MV0 + j] = intel_format_lutvalue(m_cost, 0x6f); } mv_count = 3; for (j = 4; j <= 64; j *= 2) { m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda; m_cost = (int)m_costf; vme_state_message[MODE_INTER_MV0 + mv_count] = intel_format_lutvalue(m_cost, 0x6f); mv_count++; } m_cost = lambda; /* It can only perform the 16x16 search. So mode cost can be ignored for * the other mode. for example: 16x8/8x8 */ vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost, 0x8f); vme_state_message[MODE_INTER_16X16] = intel_format_lutvalue(m_cost, 0x8f); vme_state_message[MODE_INTER_16X8] = 0; vme_state_message[MODE_INTER_8X8] = 0; vme_state_message[MODE_INTER_8X4] = 0; vme_state_message[MODE_INTER_4X4] = 0; vme_state_message[MODE_INTER_BWD] = intel_format_lutvalue(m_cost, 0x6f); } vme_state_message[MPEG2_MV_RANGE] = (mv_y << 16) | (mv_x); vme_state_message[MPEG2_PIC_WIDTH_HEIGHT] = (height_in_mbs << 16) | width_in_mbs; } void gen7_vme_mpeg2_walker_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; unsigned int *command_ptr; #define MPEG2_SCOREBOARD (1 << 21) dri_bo_map(vme_context->vme_batchbuffer.bo, 1); command_ptr = vme_context->vme_batchbuffer.bo->virtual; { unsigned int mb_intra_ub, score_dep; int x_outer, y_outer, x_inner, y_inner; int xtemp_outer = 0; int first_mb = 0; int num_mb = mb_width * mb_height; x_outer = 0; y_outer = 0; for (; x_outer < (mb_width -2 ) && !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) { x_inner = x_outer; y_inner = y_outer; for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) { mb_intra_ub = 0; score_dep = 0; if (x_inner != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; score_dep |= MB_SCOREBOARD_A; } if (y_inner != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; score_dep |= MB_SCOREBOARD_B; if (x_inner != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (x_inner != (mb_width -1)) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; score_dep |= MB_SCOREBOARD_C; } } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = MPEG2_SCOREBOARD; /* Indirect data */ *command_ptr++ = 0; /* the (X, Y) term of scoreboard */ *command_ptr++ = ((y_inner << 16) | x_inner); *command_ptr++ = score_dep; /*inline data */ *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner); *command_ptr++ = ((1 << 18) | (1 << 16) | (mb_intra_ub << 8)); x_inner -= 2; y_inner += 1; } x_outer += 1; } xtemp_outer = mb_width - 2; if (xtemp_outer < 0) xtemp_outer = 0; x_outer = xtemp_outer; y_outer = 0; for (;!loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) { y_inner = y_outer; x_inner = x_outer; for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) { mb_intra_ub = 0; score_dep = 0; if (x_inner != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; score_dep |= MB_SCOREBOARD_A; } if (y_inner != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; score_dep |= MB_SCOREBOARD_B; if (x_inner != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (x_inner != (mb_width -1)) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; score_dep |= MB_SCOREBOARD_C; } } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = MPEG2_SCOREBOARD; /* Indirect data */ *command_ptr++ = 0; /* the (X, Y) term of scoreboard */ *command_ptr++ = ((y_inner << 16) | x_inner); *command_ptr++ = score_dep; /*inline data */ *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner); *command_ptr++ = ((1 << 18) | (1 << 16) | (mb_intra_ub << 8)); x_inner -= 2; y_inner += 1; } x_outer++; if (x_outer >= mb_width) { y_outer += 1; x_outer = xtemp_outer; } } } *command_ptr++ = 0; *command_ptr++ = MI_BATCH_BUFFER_END; dri_bo_unmap(vme_context->vme_batchbuffer.bo); return; } static int avc_temporal_find_surface(VAPictureH264 *curr_pic, VAPictureH264 *ref_list, int num_pictures, int dir) { int i, found = -1, min = 0x7FFFFFFF; for (i = 0; i < num_pictures; i++) { int tmp; if ((ref_list[i].flags & VA_PICTURE_H264_INVALID) || (ref_list[i].picture_id == VA_INVALID_SURFACE)) break; tmp = curr_pic->TopFieldOrderCnt - ref_list[i].TopFieldOrderCnt; if (dir) tmp = -tmp; if (tmp > 0 && tmp < min) { min = tmp; found = i; } } return found; } void intel_avc_vme_reference_state(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int list_index, int surface_index, void (* vme_source_surface_state)( VADriverContextP ctx, int index, struct object_surface *obj_surface, struct intel_encoder_context *encoder_context)) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct object_surface *obj_surface = NULL; struct i965_driver_data *i965 = i965_driver_data(ctx); VASurfaceID ref_surface_id; VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int max_num_references; VAPictureH264 *curr_pic; VAPictureH264 *ref_list; int ref_idx; if (list_index == 0) { max_num_references = pic_param->num_ref_idx_l0_active_minus1 + 1; ref_list = slice_param->RefPicList0; } else { max_num_references = pic_param->num_ref_idx_l1_active_minus1 + 1; ref_list = slice_param->RefPicList1; } if (max_num_references == 1) { if (list_index == 0) { ref_surface_id = slice_param->RefPicList0[0].picture_id; vme_context->used_references[0] = &slice_param->RefPicList0[0]; } else { ref_surface_id = slice_param->RefPicList1[0].picture_id; vme_context->used_references[1] = &slice_param->RefPicList1[0]; } if (ref_surface_id != VA_INVALID_SURFACE) obj_surface = SURFACE(ref_surface_id); if (!obj_surface || !obj_surface->bo) { obj_surface = encode_state->reference_objects[list_index]; vme_context->used_references[list_index] = &pic_param->ReferenceFrames[list_index]; } ref_idx = 0; } else { curr_pic = &pic_param->CurrPic; /* select the reference frame in temporal space */ ref_idx = avc_temporal_find_surface(curr_pic, ref_list, max_num_references, list_index == 1); ref_surface_id = ref_list[ref_idx].picture_id; if (ref_surface_id != VA_INVALID_SURFACE) /* otherwise warning later */ obj_surface = SURFACE(ref_surface_id); vme_context->used_reference_objects[list_index] = obj_surface; vme_context->used_references[list_index] = &ref_list[ref_idx]; } if (obj_surface && obj_surface->bo) { assert(ref_idx >= 0); vme_context->used_reference_objects[list_index] = obj_surface; vme_source_surface_state(ctx, surface_index, obj_surface, encoder_context); vme_context->ref_index_in_mb[list_index] = (ref_idx << 24 | ref_idx << 16 | ref_idx << 8 | ref_idx); } else { vme_context->used_reference_objects[list_index] = NULL; vme_context->used_references[list_index] = NULL; vme_context->ref_index_in_mb[list_index] = 0; } } intel-driver-1.3.0/src/gen6_mfd.c000077500000000000000000002343041231401140700165410ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #include "sysdeps.h" #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_decoder_utils.h" #include "gen6_mfd.h" #include "intel_media.h" static const uint32_t zigzag_direct[64] = { 0, 1, 8, 16, 9, 2, 3, 10, 17, 24, 32, 25, 18, 11, 4, 5, 12, 19, 26, 33, 40, 48, 41, 34, 27, 20, 13, 6, 7, 14, 21, 28, 35, 42, 49, 56, 57, 50, 43, 36, 29, 22, 15, 23, 30, 37, 44, 51, 58, 59, 52, 45, 38, 31, 39, 46, 53, 60, 61, 54, 47, 55, 62, 63 }; static void gen6_mfd_init_avc_surface(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, struct object_surface *obj_surface) { struct i965_driver_data *i965 = i965_driver_data(ctx); GenAvcSurface *gen6_avc_surface = obj_surface->private_data; int height_in_mbs; obj_surface->free_private_data = gen_free_avc_surface; height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */ if (!gen6_avc_surface) { gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1); assert((obj_surface->size & 0x3f) == 0); obj_surface->private_data = gen6_avc_surface; } gen6_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag && !pic_param->seq_fields.bits.direct_8x8_inference_flag); if (gen6_avc_surface->dmv_top == NULL) { gen6_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", 128 * height_in_mbs * 64, /* scalable with frame height */ 0x1000); } if (gen6_avc_surface->dmv_bottom_flag && gen6_avc_surface->dmv_bottom == NULL) { gen6_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", 128 * height_in_mbs * 64, /* scalable with frame height */ 0x1000); } } static void gen6_mfd_pipe_mode_select(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; assert(standard_select == MFX_FORMAT_MPEG2 || standard_select == MFX_FORMAT_AVC || standard_select == MFX_FORMAT_VC1); BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2)); OUT_BCS_BATCH(batch, (MFD_MODE_VLD << 16) | /* VLD mode */ (0 << 10) | /* disable Stream-Out */ (gen6_mfd_context->post_deblocking_output.valid << 9) | /* Post Deblocking Output */ (gen6_mfd_context->pre_deblocking_output.valid << 8) | /* Pre Deblocking Output */ (0 << 7) | /* disable TLB prefectch */ (0 << 5) | /* not in stitch mode */ (MFX_CODEC_DECODE << 4) | /* decoding mode */ (standard_select << 0)); OUT_BCS_BATCH(batch, (0 << 20) | /* round flag in PB slice */ (0 << 19) | /* round flag in Intra8x8 */ (0 << 7) | /* expand NOA bus flag */ (1 << 6) | /* must be 1 */ (0 << 5) | /* disable clock gating for NOA */ (0 << 4) | /* terminate if AVC motion and POC table error occurs */ (0 << 3) | /* terminate if AVC mbdata error occurs */ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ (0 << 1) | /* AVC long field motion vector */ (1 << 0)); /* always calculate AVC ILDB boundary strength */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_surface_state(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; struct object_surface *obj_surface = decode_state->render_object; BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, ((obj_surface->orig_height - 1) << 19) | ((obj_surface->orig_width - 1) << 6)); OUT_BCS_BATCH(batch, (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */ (0 << 22) | /* surface object control state, FIXME??? */ ((obj_surface->width - 1) << 3) | /* pitch */ (0 << 2) | /* must be 0 for interleave U/V */ (1 << 1) | /* must be y-tiled */ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, FIXME: must be 1 ??? */ OUT_BCS_BATCH(batch, (0 << 16) | /* must be 0 for interleave U/V */ (obj_surface->height)); /* y offset for U(cb) */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_pipe_buf_addr_state(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; int i; BEGIN_BCS_BATCH(batch, 24); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2)); if (gen6_mfd_context->pre_deblocking_output.valid) OUT_BCS_RELOC(batch, gen6_mfd_context->pre_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (gen6_mfd_context->post_deblocking_output.valid) OUT_BCS_RELOC(batch, gen6_mfd_context->post_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ if (gen6_mfd_context->intra_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen6_mfd_context->intra_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); /* DW 7..22 */ for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) { struct object_surface *obj_surface; if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID && gen6_mfd_context->reference_surface[i].obj_surface && gen6_mfd_context->reference_surface[i].obj_surface->bo) { obj_surface = gen6_mfd_context->reference_surface[i].obj_surface; OUT_BCS_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } else { OUT_BCS_BATCH(batch, 0); } } OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */ ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_ind_obj_base_addr_state(VADriverContextP ctx, dri_bo *slice_data_bo, int standard_select, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_bsp_buf_base_addr_state(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2)); if (gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (gen6_mfd_context->mpr_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen6_mfd_context->mpr_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (gen6_mfd_context->bitplane_read_buffer.valid) OUT_BCS_RELOC(batch, gen6_mfd_context->bitplane_read_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_avc_img_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; int qm_present_flag; int img_struct; int mbaff_frame_flag; unsigned int width_in_mbs, height_in_mbs; VAPictureParameterBufferH264 *pic_param; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) qm_present_flag = 1; else qm_present_flag = 0; /* built-in QM matrices */ if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD) img_struct = 1; else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD) img_struct = 3; else img_struct = 0; if ((img_struct & 0x1) == 0x1) { assert(pic_param->pic_fields.bits.field_pic_flag == 0x1); } else { assert(pic_param->pic_fields.bits.field_pic_flag == 0x0); } if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */ assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0); assert(pic_param->pic_fields.bits.field_pic_flag == 0); } else { assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */ } mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag && !pic_param->pic_fields.bits.field_pic_flag); width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff); height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */ assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */ /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */ assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */ pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */ assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */ BEGIN_BCS_BATCH(batch, 13); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2)); OUT_BCS_BATCH(batch, ((width_in_mbs * height_in_mbs) & 0x7fff)); OUT_BCS_BATCH(batch, (height_in_mbs << 16) | (width_in_mbs << 0)); OUT_BCS_BATCH(batch, ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) | ((pic_param->chroma_qp_index_offset & 0x1f) << 16) | (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */ (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */ (1 << 12) | /* always 1, hardware requirement */ (qm_present_flag << 10) | (img_struct << 8) | (16 << 0)); OUT_BCS_BATCH(batch, (pic_param->seq_fields.bits.chroma_format_idc << 10) | (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) | ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) | (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) | (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) | (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) | (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) | (mbaff_frame_flag << 1) | (pic_param->pic_fields.bits.field_pic_flag << 0)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_avc_qm_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; int cmd_len; VAIQMatrixBufferH264 *iq_matrix; VAPictureParameterBufferH264 *pic_param; if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer) return; iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */ if (pic_param->pic_fields.bits.transform_8x8_mode_flag) cmd_len += 2 * 16; /* load two 8x8 scaling matrices */ BEGIN_BCS_BATCH(batch, cmd_len); OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | (cmd_len - 2)); if (pic_param->pic_fields.bits.transform_8x8_mode_flag) OUT_BCS_BATCH(batch, (0x0 << 8) | /* don't use default built-in matrices */ (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */ else OUT_BCS_BATCH(batch, (0x0 << 8) | /* don't use default built-in matrices */ (0x3f << 0)); /* six 4x4 scaling matrices */ intel_batchbuffer_data(batch, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4); if (pic_param->pic_fields.bits.transform_8x8_mode_flag) intel_batchbuffer_data(batch, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_avc_directmode_state(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; struct object_surface *obj_surface; GenAvcSurface *gen6_avc_surface; VAPictureH264 *va_pic; int i, j; BEGIN_BCS_BATCH(batch, 69); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2)); /* reference surfaces 0..15 */ for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) { if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID && gen6_mfd_context->reference_surface[i].obj_surface && gen6_mfd_context->reference_surface[i].obj_surface->private_data) { obj_surface = gen6_mfd_context->reference_surface[i].obj_surface; gen6_avc_surface = obj_surface->private_data; OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); if (gen6_avc_surface->dmv_bottom_flag == 1) OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } /* the current decoding frame/field */ va_pic = &pic_param->CurrPic; obj_surface = decode_state->render_object; assert(obj_surface->bo && obj_surface->private_data); gen6_avc_surface = obj_surface->private_data; OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); if (gen6_avc_surface->dmv_bottom_flag == 1) OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* POC List */ for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) { if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) { int found = 0; assert(gen6_mfd_context->reference_surface[i].obj_surface != NULL); for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) { va_pic = &pic_param->ReferenceFrames[j]; if (va_pic->flags & VA_PICTURE_H264_INVALID) continue; if (va_pic->picture_id == gen6_mfd_context->reference_surface[i].surface_id) { found = 1; break; } } assert(found == 1); assert(!(va_pic->flags & VA_PICTURE_H264_INVALID)); OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt); OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } va_pic = &pic_param->CurrPic; OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt); OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_avc_slice_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, VASliceParameterBufferH264 *next_slice_param, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos; int num_ref_idx_l0, num_ref_idx_l1; int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag && pic_param->seq_fields.bits.mb_adaptive_frame_field_flag); int weighted_pred_idc = 0; int first_mb_in_slice = 0, first_mb_in_next_slice = 0; unsigned int chroma_log2_weight_denom, luma_log2_weight_denom; int slice_type; if (slice_param->slice_type == SLICE_TYPE_I || slice_param->slice_type == SLICE_TYPE_SI) { slice_type = SLICE_TYPE_I; } else if (slice_param->slice_type == SLICE_TYPE_P || slice_param->slice_type == SLICE_TYPE_SP) { slice_type = SLICE_TYPE_P; } else { assert(slice_param->slice_type == SLICE_TYPE_B); slice_type = SLICE_TYPE_B; } luma_log2_weight_denom = slice_param->luma_log2_weight_denom; chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom; if (slice_type == SLICE_TYPE_I) { assert(slice_param->num_ref_idx_l0_active_minus1 == 0); assert(slice_param->num_ref_idx_l1_active_minus1 == 0); num_ref_idx_l0 = 0; num_ref_idx_l1 = 0; } else if (slice_type == SLICE_TYPE_P) { assert(slice_param->num_ref_idx_l1_active_minus1 == 0); num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = 0; weighted_pred_idc = (pic_param->pic_fields.bits.weighted_pred_flag == 1); } else { num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1; weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc; if (weighted_pred_idc == 2) { /* 8.4.3 - Derivation process for prediction weights (8-279) */ luma_log2_weight_denom = 5; chroma_log2_weight_denom = 5; } } first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture; slice_hor_pos = first_mb_in_slice % width_in_mbs; slice_ver_pos = first_mb_in_slice / width_in_mbs; if (next_slice_param) { first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture; next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs; next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs; } else { next_slice_hor_pos = 0; next_slice_ver_pos = height_in_mbs; } BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */ OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2)); OUT_BCS_BATCH(batch, slice_type); OUT_BCS_BATCH(batch, (num_ref_idx_l1 << 24) | (num_ref_idx_l0 << 16) | (chroma_log2_weight_denom << 8) | (luma_log2_weight_denom << 0)); OUT_BCS_BATCH(batch, (weighted_pred_idc << 30) | (slice_param->direct_spatial_mv_pred_flag << 29) | (slice_param->disable_deblocking_filter_idc << 27) | (slice_param->cabac_init_idc << 24) | ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) | ((slice_param->slice_beta_offset_div2 & 0xf) << 8) | ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0)); OUT_BCS_BATCH(batch, (slice_ver_pos << 24) | (slice_hor_pos << 16) | (first_mb_in_slice << 0)); OUT_BCS_BATCH(batch, (next_slice_ver_pos << 16) | (next_slice_hor_pos << 0)); OUT_BCS_BATCH(batch, (next_slice_param == NULL) << 19); /* last slice flag */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_avc_phantom_slice_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *next_slice_param, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */ int slice_hor_pos, slice_ver_pos, slice_start_mb_num, next_slice_hor_pos, next_slice_ver_pos; int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag && pic_param->seq_fields.bits.mb_adaptive_frame_field_flag); if (next_slice_param) { int first_mb_in_next_slice; slice_hor_pos = 0; slice_ver_pos = 0; slice_start_mb_num = 0; first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture; next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs; next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs; } else { slice_hor_pos = 0; slice_ver_pos = height_in_mbs; slice_start_mb_num = width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag); next_slice_hor_pos = 0; next_slice_ver_pos = 0; } BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */ OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, slice_ver_pos << 24 | slice_hor_pos << 16 | slice_start_mb_num << 0); OUT_BCS_BATCH(batch, next_slice_ver_pos << 16 | next_slice_hor_pos << 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static inline void gen6_mfd_avc_ref_idx_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen6_mfd_context *gen6_mfd_context) { gen6_send_avc_ref_idx_state( gen6_mfd_context->base.batch, slice_param, gen6_mfd_context->reference_surface ); } static void gen6_mfd_avc_weightoffset_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; int i, j, num_weight_offset_table = 0; short weightoffsets[32 * 6]; if ((slice_param->slice_type == SLICE_TYPE_P || slice_param->slice_type == SLICE_TYPE_SP) && (pic_param->pic_fields.bits.weighted_pred_flag == 1)) { num_weight_offset_table = 1; } if ((slice_param->slice_type == SLICE_TYPE_B) && (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) { num_weight_offset_table = 2; } for (i = 0; i < num_weight_offset_table; i++) { BEGIN_BCS_BATCH(batch, 98); OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2)); OUT_BCS_BATCH(batch, i); if (i == 0) { for (j = 0; j < 32; j++) { weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j]; weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j]; weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0]; weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0]; weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1]; weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1]; } } else { for (j = 0; j < 32; j++) { weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j]; weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j]; weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0]; weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0]; weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1]; weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1]; } } intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets)); ADVANCE_BCS_BATCH(batch); } } static void gen6_mfd_avc_bsd_object(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, dri_bo *slice_data_bo, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; unsigned int slice_data_bit_offset; slice_data_bit_offset = avc_get_first_mb_bit_offset( slice_data_bo, slice_param, pic_param->pic_fields.bits.entropy_coding_mode_flag ); BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2)); OUT_BCS_BATCH(batch, (slice_param->slice_data_size - slice_param->slice_data_offset)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset); OUT_BCS_BATCH(batch, (0 << 31) | (0 << 14) | (0 << 12) | (0 << 10) | (0 << 8)); OUT_BCS_BATCH(batch, ((slice_data_bit_offset >> 3) << 16) | (1 << 7) | (1 << 6) | ((0x7 - (slice_data_bit_offset & 0x7)) << 0)); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_avc_phantom_slice_bsd_object(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_avc_phantom_slice(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *next_slice_param, struct gen6_mfd_context *gen6_mfd_context) { gen6_mfd_avc_phantom_slice_state(ctx, pic_param, next_slice_param, gen6_mfd_context); gen6_mfd_avc_phantom_slice_bsd_object(ctx, pic_param, gen6_mfd_context); } static void gen6_mfd_avc_phantom_slice_first(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *next_slice_param, struct gen6_mfd_context *gen6_mfd_context) { gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen6_mfd_context); } static void gen6_mfd_avc_phantom_slice_last(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, struct gen6_mfd_context *gen6_mfd_context) { gen6_mfd_avc_phantom_slice(ctx, pic_param, NULL, gen6_mfd_context); } static void gen6_mfd_avc_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { VAPictureParameterBufferH264 *pic_param; VASliceParameterBufferH264 *slice_param; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *bo; int i, j, enable_avc_ildb = 0; int width_in_mbs; for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); assert((slice_param->slice_type == SLICE_TYPE_I) || (slice_param->slice_type == SLICE_TYPE_SI) || (slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP) || (slice_param->slice_type == SLICE_TYPE_B)); if (slice_param->disable_deblocking_filter_idc != 1) { enable_avc_ildb = 1; break; } slice_param++; } } assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; intel_update_avc_frame_store_index(ctx, decode_state, pic_param, gen6_mfd_context->reference_surface); width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff); /* Current decoded picture */ obj_surface = decode_state->render_object; obj_surface->flags &= ~SURFACE_REF_DIS_MASK; obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0); i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); /* initial uv component for YUV400 case */ if (pic_param->seq_fields.bits.chroma_format_idc == 0) { unsigned int uv_offset = obj_surface->width * obj_surface->height; unsigned int uv_size = obj_surface->width * obj_surface->height / 2; drm_intel_gem_bo_map_gtt(obj_surface->bo); memset(obj_surface->bo->virtual + uv_offset, 0x80, uv_size); drm_intel_gem_bo_unmap_gtt(obj_surface->bo); } gen6_mfd_init_avc_surface(ctx, pic_param, obj_surface); dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo); gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo); gen6_mfd_context->post_deblocking_output.valid = enable_avc_ildb; dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo); gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo); gen6_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb; dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", width_in_mbs * 64, 0x1000); assert(bo); gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo; gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "deblocking filter row store", width_in_mbs * 64 * 4, 0x1000); assert(bo); gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo; gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 96, 0x1000); assert(bo); gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "mpr row store", width_in_mbs * 64, 0x1000); assert(bo); gen6_mfd_context->mpr_row_store_scratch_buffer.bo = bo; gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 1; gen6_mfd_context->bitplane_read_buffer.valid = 0; } static void gen6_mfd_avc_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; VAPictureParameterBufferH264 *pic_param; VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; gen6_mfd_avc_decode_init(ctx, decode_state, gen6_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context); gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context); gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context); gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context); gen6_mfd_avc_img_state(ctx, decode_state, gen6_mfd_context); gen6_mfd_avc_qm_state(ctx, decode_state, gen6_mfd_context); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen6_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer; if (j == 0 && slice_param->first_mb_in_slice) gen6_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen6_mfd_context); for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); assert((slice_param->slice_type == SLICE_TYPE_I) || (slice_param->slice_type == SLICE_TYPE_SI) || (slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP) || (slice_param->slice_type == SLICE_TYPE_B)); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen6_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen6_mfd_context); gen6_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context); gen6_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen6_mfd_context); gen6_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen6_mfd_context); gen6_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, gen6_mfd_context); slice_param++; } } gen6_mfd_avc_phantom_slice_last(ctx, pic_param, gen6_mfd_context); intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static void gen6_mfd_mpeg2_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { VAPictureParameterBufferMPEG2 *pic_param; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *bo; unsigned int width_in_mbs; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16; mpeg2_set_reference_surfaces( ctx, gen6_mfd_context->reference_surface, decode_state, pic_param ); /* Current decoded picture */ obj_surface = decode_state->render_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo); gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo); gen6_mfd_context->pre_deblocking_output.valid = 1; dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 96, 0x1000); assert(bo); gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; gen6_mfd_context->post_deblocking_output.valid = 0; gen6_mfd_context->intra_row_store_scratch_buffer.valid = 0; gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0; gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0; gen6_mfd_context->bitplane_read_buffer.valid = 0; } static void gen6_mfd_mpeg2_pic_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; VAPictureParameterBufferMPEG2 *pic_param; unsigned int tff, pic_structure; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; pic_structure = pic_param->picture_coding_extension.bits.picture_structure; if (pic_structure == MPEG_FRAME) tff = pic_param->picture_coding_extension.bits.top_field_first; else tff = !(pic_param->picture_coding_extension.bits.is_first_field ^ (pic_structure & MPEG_TOP_FIELD)); BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (4 - 2)); OUT_BCS_BATCH(batch, (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */ ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */ ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */ ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */ pic_param->picture_coding_extension.bits.intra_dc_precision << 14 | pic_param->picture_coding_extension.bits.picture_structure << 12 | tff << 11 | pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 | pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 | pic_param->picture_coding_extension.bits.q_scale_type << 8 | pic_param->picture_coding_extension.bits.intra_vlc_format << 7 | pic_param->picture_coding_extension.bits.alternate_scan << 6); OUT_BCS_BATCH(batch, pic_param->picture_coding_type << 9); OUT_BCS_BATCH(batch, (ALIGN(pic_param->vertical_size, 16) / 16) << 16 | (ALIGN(pic_param->horizontal_size, 16) / 16)); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_mpeg2_qm_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen6_mfd_context->iq_matrix.mpeg2; int i, j; /* Update internal QM state */ if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) { VAIQMatrixBufferMPEG2 * const iq_matrix = (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer; gen_iq_matrix->load_intra_quantiser_matrix = iq_matrix->load_intra_quantiser_matrix; if (iq_matrix->load_intra_quantiser_matrix) { for (j = 0; j < 64; j++) gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] = iq_matrix->intra_quantiser_matrix[j]; } gen_iq_matrix->load_non_intra_quantiser_matrix = iq_matrix->load_non_intra_quantiser_matrix; if (iq_matrix->load_non_intra_quantiser_matrix) { for (j = 0; j < 64; j++) gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] = iq_matrix->non_intra_quantiser_matrix[j]; } } /* Commit QM state to HW */ for (i = 0; i < 2; i++) { unsigned char *qm = NULL; if (i == 0) { if (gen_iq_matrix->load_intra_quantiser_matrix) qm = gen_iq_matrix->intra_quantiser_matrix; } else { if (gen_iq_matrix->load_non_intra_quantiser_matrix) qm = gen_iq_matrix->non_intra_quantiser_matrix; } if (!qm) continue; BEGIN_BCS_BATCH(batch, 18); OUT_BCS_BATCH(batch, MFX_MPEG2_QM_STATE | (18 - 2)); OUT_BCS_BATCH(batch, i); intel_batchbuffer_data(batch, qm, 64); ADVANCE_BCS_BATCH(batch); } } static void gen6_mfd_mpeg2_bsd_object(VADriverContextP ctx, VAPictureParameterBufferMPEG2 *pic_param, VASliceParameterBufferMPEG2 *slice_param, VASliceParameterBufferMPEG2 *next_slice_param, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16; int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0; if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD || pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD) is_field_pic = 1; is_field_pic_wa = is_field_pic && gen6_mfd_context->wa_mpeg2_slice_vertical_position > 0; vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa); hpos0 = slice_param->slice_horizontal_position; if (next_slice_param == NULL) { vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic); hpos1 = 0; } else { vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa); hpos1 = next_slice_param->slice_horizontal_position; } mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0); BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2)); OUT_BCS_BATCH(batch, slice_param->slice_data_size - (slice_param->macroblock_offset >> 3)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3)); OUT_BCS_BATCH(batch, hpos0 << 24 | vpos0 << 16 | mb_count << 8 | (next_slice_param == NULL) << 5 | (next_slice_param == NULL) << 3 | (slice_param->macroblock_offset & 0x7)); OUT_BCS_BATCH(batch, slice_param->quantiser_scale_code << 24); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_mpeg2_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; VAPictureParameterBufferMPEG2 *pic_param; VASliceParameterBufferMPEG2 *slice_param, *next_slice_param; dri_bo *slice_data_bo; int group_idx = 0, pre_group_idx = -1, element_idx = 0; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; gen6_mfd_mpeg2_decode_init(ctx, decode_state, gen6_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context); gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context); gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context); gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context); gen6_mfd_mpeg2_pic_state(ctx, decode_state, gen6_mfd_context); gen6_mfd_mpeg2_qm_state(ctx, decode_state, gen6_mfd_context); if (gen6_mfd_context->wa_mpeg2_slice_vertical_position < 0) gen6_mfd_context->wa_mpeg2_slice_vertical_position = mpeg2_wa_slice_vertical_position(decode_state, pic_param); slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[group_idx]->buffer; for (; slice_param;) { if (pre_group_idx != group_idx) { slice_data_bo = decode_state->slice_datas[group_idx]->bo; gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen6_mfd_context); pre_group_idx = group_idx; } next_slice_param = intel_mpeg2_find_next_slice(decode_state, pic_param, slice_param, &group_idx, &element_idx); gen6_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context); slice_param = next_slice_param; } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static const int va_to_gen6_vc1_pic_type[5] = { GEN6_VC1_I_PICTURE, GEN6_VC1_P_PICTURE, GEN6_VC1_B_PICTURE, GEN6_VC1_BI_PICTURE, GEN6_VC1_P_PICTURE, }; static const int va_to_gen6_vc1_mv[4] = { 1, /* 1-MV */ 2, /* 1-MV half-pel */ 3, /* 1-MV half-pef bilinear */ 0, /* Mixed MV */ }; static const int b_picture_scale_factor[21] = { 128, 85, 170, 64, 192, 51, 102, 153, 204, 43, 215, 37, 74, 111, 148, 185, 222, 32, 96, 160, 224, }; static const int va_to_gen6_vc1_condover[3] = { 0, 2, 3 }; static const int va_to_gen6_vc1_profile[4] = { GEN6_VC1_SIMPLE_PROFILE, GEN6_VC1_MAIN_PROFILE, GEN6_VC1_RESERVED_PROFILE, GEN6_VC1_ADVANCED_PROFILE }; static void gen6_mfd_free_vc1_surface(void **data) { struct gen6_vc1_surface *gen6_vc1_surface = *data; if (!gen6_vc1_surface) return; dri_bo_unreference(gen6_vc1_surface->dmv); free(gen6_vc1_surface); *data = NULL; } static void gen6_mfd_init_vc1_surface(VADriverContextP ctx, VAPictureParameterBufferVC1 *pic_param, struct object_surface *obj_surface) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vc1_surface *gen6_vc1_surface = obj_surface->private_data; int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16; obj_surface->free_private_data = gen6_mfd_free_vc1_surface; if (!gen6_vc1_surface) { gen6_vc1_surface = calloc(sizeof(struct gen6_vc1_surface), 1); assert((obj_surface->size & 0x3f) == 0); obj_surface->private_data = gen6_vc1_surface; } gen6_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type; if (gen6_vc1_surface->dmv == NULL) { gen6_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", 128 * height_in_mbs * 64, /* scalable with frame height */ 0x1000); } } static void gen6_mfd_vc1_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { VAPictureParameterBufferVC1 *pic_param; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *bo; int width_in_mbs; int picture_type; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; picture_type = pic_param->picture_fields.bits.picture_type; intel_update_vc1_frame_store_index(ctx, decode_state, pic_param, gen6_mfd_context->reference_surface); /* Current decoded picture */ obj_surface = decode_state->render_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); gen6_mfd_init_vc1_surface(ctx, pic_param, obj_surface); dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo); gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo); gen6_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter; dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo); gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo); gen6_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter; dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", width_in_mbs * 64, 0x1000); assert(bo); gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo; gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "deblocking filter row store", width_in_mbs * 7 * 64, 0x1000); assert(bo); gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo; gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 96, 0x1000); assert(bo); gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0; gen6_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value; dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo); if (gen6_mfd_context->bitplane_read_buffer.valid) { int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16; int bitplane_width = ALIGN(width_in_mbs, 2) / 2; int src_w, src_h; uint8_t *src = NULL, *dst = NULL; assert(decode_state->bit_plane->buffer); src = decode_state->bit_plane->buffer; bo = dri_bo_alloc(i965->intel.bufmgr, "VC-1 Bitplane", bitplane_width * height_in_mbs, 0x1000); assert(bo); gen6_mfd_context->bitplane_read_buffer.bo = bo; dri_bo_map(bo, True); assert(bo->virtual); dst = bo->virtual; for (src_h = 0; src_h < height_in_mbs; src_h++) { for(src_w = 0; src_w < width_in_mbs; src_w++) { int src_index, dst_index; int src_shift; uint8_t src_value; src_index = (src_h * width_in_mbs + src_w) / 2; src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4; src_value = ((src[src_index] >> src_shift) & 0xf); if (picture_type == GEN6_VC1_SKIPPED_PICTURE){ src_value |= 0x2; } dst_index = src_w / 2; dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4)); } if (src_w & 1) dst[src_w / 2] >>= 4; dst += bitplane_width; } dri_bo_unmap(bo); } else gen6_mfd_context->bitplane_read_buffer.bo = NULL; } static void gen6_mfd_vc1_pic_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; VAPictureParameterBufferVC1 *pic_param; struct object_surface *obj_surface; int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq; int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel; int unified_mv_mode; int ref_field_pic_polarity = 0; int scale_factor = 0; int trans_ac_y = 0; int dmv_surface_valid = 0; int brfd = 0; int fcm = 0; int picture_type; int profile; int overlap; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; profile = va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile]; dquant = pic_param->pic_quantizer_fields.bits.dquant; dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame; dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile; dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge; dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge; dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level; alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer; if (dquant == 0) { alt_pquant_config = 0; alt_pquant_edge_mask = 0; } else if (dquant == 2) { alt_pquant_config = 1; alt_pquant_edge_mask = 0xf; } else { assert(dquant == 1); if (dquantfrm == 0) { alt_pquant_config = 0; alt_pquant_edge_mask = 0; alt_pq = 0; } else { assert(dquantfrm == 1); alt_pquant_config = 1; switch (dqprofile) { case 3: if (dqbilevel == 0) { alt_pquant_config = 2; alt_pquant_edge_mask = 0; } else { assert(dqbilevel == 1); alt_pquant_config = 3; alt_pquant_edge_mask = 0; } break; case 0: alt_pquant_edge_mask = 0xf; break; case 1: if (dqdbedge == 3) alt_pquant_edge_mask = 0x9; else alt_pquant_edge_mask = (0x3 << dqdbedge); break; case 2: alt_pquant_edge_mask = (0x1 << dqsbedge); break; default: assert(0); } } } if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) { assert(pic_param->mv_fields.bits.mv_mode2 < 4); unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode2]; } else { assert(pic_param->mv_fields.bits.mv_mode < 4); unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode]; } if (pic_param->sequence_fields.bits.interlace == 1 && pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */ /* FIXME: calculate reference field picture polarity */ assert(0); ref_field_pic_polarity = 0; } if (pic_param->b_picture_fraction < 21) scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction]; picture_type = va_to_gen6_vc1_pic_type[pic_param->picture_fields.bits.picture_type]; if (profile == GEN6_VC1_ADVANCED_PROFILE && picture_type == GEN6_VC1_I_PICTURE) picture_type = GEN6_VC1_BI_PICTURE; if (picture_type == GEN6_VC1_I_PICTURE || picture_type == GEN6_VC1_BI_PICTURE) /* I picture */ trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2; else { trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1; /* * 8.3.6.2.1 Transform Type Selection * If variable-sized transform coding is not enabled, * then the 8x8 transform shall be used for all blocks. * it is also MFX_VC1_PIC_STATE requirement. */ if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) { pic_param->transform_fields.bits.mb_level_transform_type_flag = 1; pic_param->transform_fields.bits.frame_level_transform_type = 0; } } if (picture_type == GEN6_VC1_B_PICTURE) { struct gen6_vc1_surface *gen6_vc1_surface = NULL; obj_surface = decode_state->reference_objects[1]; if (obj_surface) gen6_vc1_surface = obj_surface->private_data; if (!gen6_vc1_surface || (va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_I_PICTURE || va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_BI_PICTURE)) dmv_surface_valid = 0; else dmv_surface_valid = 1; } assert(pic_param->picture_fields.bits.frame_coding_mode < 3); if (pic_param->picture_fields.bits.frame_coding_mode < 2) fcm = pic_param->picture_fields.bits.frame_coding_mode; else { if (pic_param->picture_fields.bits.top_field_first) fcm = 2; else fcm = 3; } if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_B_PICTURE) { /* B picture */ brfd = pic_param->reference_fields.bits.reference_distance; brfd = (scale_factor * brfd) >> 8; brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1; if (brfd < 0) brfd = 0; } overlap = 0; if (profile != GEN6_VC1_ADVANCED_PROFILE){ if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 && pic_param->picture_fields.bits.picture_type != GEN6_VC1_B_PICTURE) { overlap = 1; } }else { if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_P_PICTURE && pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){ overlap = 1; } if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_I_PICTURE || pic_param->picture_fields.bits.picture_type == GEN6_VC1_BI_PICTURE){ if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){ overlap = 1; } else if (va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 2 || va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 3) { overlap = 1; } } } assert(pic_param->conditional_overlap_flag < 3); assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */ BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_VC1_PIC_STATE | (6 - 2)); OUT_BCS_BATCH(batch, (ALIGN(pic_param->coded_height, 16) / 16) << 16 | (ALIGN(pic_param->coded_width, 16) / 16)); OUT_BCS_BATCH(batch, pic_param->sequence_fields.bits.syncmarker << 31 | 1 << 29 | /* concealment */ alt_pq << 24 | pic_param->entrypoint_fields.bits.loopfilter << 23 | overlap << 22 | (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 21 | /* implicit quantizer */ pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 16 | alt_pquant_edge_mask << 12 | alt_pquant_config << 10 | pic_param->pic_quantizer_fields.bits.half_qp << 9 | pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 8 | va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] << 6 | !pic_param->picture_fields.bits.is_first_field << 5 | picture_type << 2 | fcm << 0); OUT_BCS_BATCH(batch, !!pic_param->bitplane_present.value << 23 | !pic_param->bitplane_present.flags.bp_forward_mb << 22 | !pic_param->bitplane_present.flags.bp_mv_type_mb << 21 | !pic_param->bitplane_present.flags.bp_skip_mb << 20 | !pic_param->bitplane_present.flags.bp_direct_mb << 19 | !pic_param->bitplane_present.flags.bp_overflags << 18 | !pic_param->bitplane_present.flags.bp_ac_pred << 17 | !pic_param->bitplane_present.flags.bp_field_tx << 16 | pic_param->mv_fields.bits.extended_dmv_range << 14 | pic_param->mv_fields.bits.extended_mv_range << 12 | pic_param->mv_fields.bits.four_mv_switch << 11 | pic_param->fast_uvmc_flag << 10 | unified_mv_mode << 8 | ref_field_pic_polarity << 6 | pic_param->reference_fields.bits.num_reference_pictures << 5 | pic_param->reference_fields.bits.reference_distance << 0); OUT_BCS_BATCH(batch, scale_factor << 24 | pic_param->mv_fields.bits.mv_table << 20 | pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 | pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 | pic_param->transform_fields.bits.frame_level_transform_type << 12 | pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 | pic_param->mb_mode_table << 8 | trans_ac_y << 6 | pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 | pic_param->transform_fields.bits.intra_transform_dc_table << 3 | pic_param->cbp_table << 0); OUT_BCS_BATCH(batch, dmv_surface_valid << 13 | brfd << 8 | ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1)); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_vc1_pred_pipe_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; VAPictureParameterBufferVC1 *pic_param; int interpolation_mode = 0; int intensitycomp_single; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear || (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation && pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear)) interpolation_mode = 2; /* Half-pel bilinear */ else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel || (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation && pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel)) interpolation_mode = 0; /* Half-pel bicubic */ else interpolation_mode = 1; /* Quarter-pel bicubic */ assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation); BEGIN_BCS_BATCH(batch, 7); OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (7 - 2)); OUT_BCS_BATCH(batch, 0 << 8 | /* FIXME: interlace mode */ pic_param->rounding_control << 4 | va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile] << 2); OUT_BCS_BATCH(batch, pic_param->luma_shift << 16 | pic_param->luma_scale << 0); /* FIXME: Luma Scaling */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, interpolation_mode << 19 | pic_param->fast_uvmc_flag << 18 | 0 << 17 | /* FIXME: scale up or down ??? */ pic_param->range_reduction_frame << 16 | 0 << 6 | /* FIXME: double ??? */ 0 << 4 | intensitycomp_single << 2 | intensitycomp_single << 0); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_vc1_directmode_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; struct object_surface *obj_surface; dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL; obj_surface = decode_state->render_object; if (obj_surface && obj_surface->private_data) { dmv_write_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv; } obj_surface = decode_state->reference_objects[1]; if (obj_surface && obj_surface->private_data) { dmv_read_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv; } BEGIN_BCS_BATCH(batch, 3); OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2)); if (dmv_write_buffer) OUT_BCS_RELOC(batch, dmv_write_buffer, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (dmv_read_buffer) OUT_BCS_RELOC(batch, dmv_read_buffer, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static int gen6_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile) { int out_slice_data_bit_offset; int slice_header_size = in_slice_data_bit_offset / 8; int i, j; if (profile != 3) out_slice_data_bit_offset = in_slice_data_bit_offset; else { for (i = 0, j = 0; i < slice_header_size; i++, j++) { if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) { i++, j += 2; } } out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8; } return out_slice_data_bit_offset; } static void gen6_mfd_vc1_bsd_object(VADriverContextP ctx, VAPictureParameterBufferVC1 *pic_param, VASliceParameterBufferVC1 *slice_param, VASliceParameterBufferVC1 *next_slice_param, dri_bo *slice_data_bo, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; int next_slice_start_vert_pos; int macroblock_offset; uint8_t *slice_data = NULL; dri_bo_map(slice_data_bo, 0); slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset); macroblock_offset = gen6_mfd_vc1_get_macroblock_bit_offset(slice_data, slice_param->macroblock_offset, pic_param->sequence_fields.bits.profile); dri_bo_unmap(slice_data_bo); if (next_slice_param) next_slice_start_vert_pos = next_slice_param->slice_vertical_position; else next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16; BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (4 - 2)); OUT_BCS_BATCH(batch, slice_param->slice_data_size - (macroblock_offset >> 3)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset + (macroblock_offset >> 3)); OUT_BCS_BATCH(batch, slice_param->slice_vertical_position << 24 | next_slice_start_vert_pos << 16 | (macroblock_offset & 0x7)); ADVANCE_BCS_BATCH(batch); } static void gen6_mfd_vc1_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen6_mfd_context *gen6_mfd_context) { struct intel_batchbuffer *batch = gen6_mfd_context->base.batch; VAPictureParameterBufferVC1 *pic_param; VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; gen6_mfd_vc1_decode_init(ctx, decode_state, gen6_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context); gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context); gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context); gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context); gen6_mfd_vc1_pic_state(ctx, decode_state, gen6_mfd_context); gen6_mfd_vc1_pred_pipe_state(ctx, decode_state, gen6_mfd_context); gen6_mfd_vc1_directmode_state(ctx, decode_state, gen6_mfd_context); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen6_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen6_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen6_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static VAStatus gen6_mfd_decode_picture(VADriverContextP ctx, VAProfile profile, union codec_state *codec_state, struct hw_context *hw_context) { struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context; struct decode_state *decode_state = &codec_state->decode; VAStatus vaStatus; assert(gen6_mfd_context); vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state); if (vaStatus != VA_STATUS_SUCCESS) goto out; switch (profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: gen6_mfd_mpeg2_decode_picture(ctx, decode_state, gen6_mfd_context); break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: gen6_mfd_avc_decode_picture(ctx, decode_state, gen6_mfd_context); break; case VAProfileVC1Simple: case VAProfileVC1Main: case VAProfileVC1Advanced: gen6_mfd_vc1_decode_picture(ctx, decode_state, gen6_mfd_context); break; default: assert(0); break; } vaStatus = VA_STATUS_SUCCESS; out: return vaStatus; } static void gen6_mfd_context_destroy(void *hw_context) { struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context; dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo); gen6_mfd_context->post_deblocking_output.bo = NULL; dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo); gen6_mfd_context->pre_deblocking_output.bo = NULL; dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo); gen6_mfd_context->intra_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo); gen6_mfd_context->mpr_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo); gen6_mfd_context->bitplane_read_buffer.bo = NULL; intel_batchbuffer_free(gen6_mfd_context->base.batch); free(gen6_mfd_context); } struct hw_context * gen6_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config) { struct intel_driver_data *intel = intel_driver_data(ctx); struct gen6_mfd_context *gen6_mfd_context = calloc(1, sizeof(struct gen6_mfd_context)); int i; gen6_mfd_context->base.destroy = gen6_mfd_context_destroy; gen6_mfd_context->base.run = gen6_mfd_decode_picture; gen6_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0); for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) { gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID; gen6_mfd_context->reference_surface[i].frame_store_id = -1; gen6_mfd_context->reference_surface[i].obj_surface = NULL; } gen6_mfd_context->wa_mpeg2_slice_vertical_position = -1; return (struct hw_context *)gen6_mfd_context; } intel-driver-1.3.0/src/gen6_mfd.h000066400000000000000000000047161231401140700165450ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #ifndef _GEN6_MFD_H_ #define _GEN6_MFD_H_ #include #include #include #include #include "i965_decoder.h" #define GEN6_VC1_I_PICTURE 0 #define GEN6_VC1_P_PICTURE 1 #define GEN6_VC1_B_PICTURE 2 #define GEN6_VC1_BI_PICTURE 3 #define GEN6_VC1_SKIPPED_PICTURE 4 #define GEN6_VC1_SIMPLE_PROFILE 0 #define GEN6_VC1_MAIN_PROFILE 1 #define GEN6_VC1_ADVANCED_PROFILE 2 #define GEN6_VC1_RESERVED_PROFILE 3 struct gen6_vc1_surface { dri_bo *dmv; int picture_type; }; struct hw_context; struct gen6_mfd_context { struct hw_context base; union { VAIQMatrixBufferMPEG2 mpeg2; } iq_matrix; GenFrameStore reference_surface[MAX_GEN_REFERENCE_FRAMES]; GenBuffer post_deblocking_output; GenBuffer pre_deblocking_output; GenBuffer intra_row_store_scratch_buffer; GenBuffer deblocking_filter_row_store_scratch_buffer; GenBuffer bsd_mpc_row_store_scratch_buffer; GenBuffer mpr_row_store_scratch_buffer; GenBuffer bitplane_read_buffer; int wa_mpeg2_slice_vertical_position; }; #endif /* _GEN6_MFD_H_ */ intel-driver-1.3.0/src/gen6_vme.c000066400000000000000000000615421231401140700165610ustar00rootroot00000000000000/* * Copyright © 2010-2011 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Zhou Chang * */ #include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_encoder.h" #include "gen6_vme.h" #include "gen6_mfc.h" #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7) #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index) #define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */ #define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */ #define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */ enum VIDEO_CODING_TYPE{ VIDEO_CODING_AVC = 0, VIDEO_CODING_SUM }; enum AVC_VME_KERNEL_TYPE{ AVC_VME_INTRA_SHADER = 0, AVC_VME_INTER_SHADER, AVC_VME_BATCHBUFFER, AVC_VME_KERNEL_SUM }; static const uint32_t gen6_vme_intra_frame[][4] = { #include "shaders/vme/intra_frame.g6b" }; static const uint32_t gen6_vme_inter_frame[][4] = { #include "shaders/vme/inter_frame.g6b" }; static const uint32_t gen6_vme_batchbuffer[][4] = { #include "shaders/vme/batchbuffer.g6b" }; static struct i965_kernel gen6_vme_kernels[] = { { "AVC VME Intra Frame", AVC_VME_INTRA_SHADER, /*index*/ gen6_vme_intra_frame, sizeof(gen6_vme_intra_frame), NULL }, { "AVC VME inter Frame", AVC_VME_INTER_SHADER, gen6_vme_inter_frame, sizeof(gen6_vme_inter_frame), NULL }, { "AVC VME BATCHBUFFER", AVC_VME_BATCHBUFFER, gen6_vme_batchbuffer, sizeof(gen6_vme_batchbuffer), NULL }, }; /* only used for VME source surface state */ static void gen6_vme_source_surface_state(VADriverContextP ctx, int index, struct object_surface *obj_surface, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; vme_context->vme_surface2_setup(ctx, &vme_context->gpe_context, obj_surface, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen6_vme_media_source_surface_state(VADriverContextP ctx, int index, struct object_surface *obj_surface, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; vme_context->vme_media_rw_surface_setup(ctx, &vme_context->gpe_context, obj_surface, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen6_vme_output_buffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs; vme_context->vme_output.pitch = 16; /* in bytes, always 16 */ if (is_intra) vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES; else vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES; vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr, "VME output buffer", vme_context->vme_output.num_blocks * vme_context->vme_output.size_block, 0x1000); assert(vme_context->vme_output.bo); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_output, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen6_vme_output_vme_batchbuffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1; vme_context->vme_batchbuffer.size_block = 32; /* 2 OWORDs */ vme_context->vme_batchbuffer.pitch = 16; vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr, "VME batchbuffer", vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block, 0x1000); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_batchbuffer, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static VAStatus gen6_vme_surface_setup(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct object_surface *obj_surface; /*Setup surfaces state*/ /* current picture for encoding */ obj_surface = encode_state->input_yuv_object; gen6_vme_source_surface_state(ctx, 0, obj_surface, encoder_context); gen6_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context); if (!is_intra) { VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int slice_type; slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI); intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 0, 1, gen6_vme_source_surface_state); if (slice_type == SLICE_TYPE_B) intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 1, 2, gen6_vme_source_surface_state); } /* VME output */ gen6_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context); gen6_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context); return VA_STATUS_SUCCESS; } static VAStatus gen6_vme_interface_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct gen6_interface_descriptor_data *desc; int i; dri_bo *bo; bo = vme_context->gpe_context.idrt.bo; dri_bo_map(bo, 1); assert(bo->virtual); desc = bo->virtual; for (i = 0; i < vme_context->vme_kernel_sum; i++) { struct i965_kernel *kernel; kernel = &vme_context->gpe_context.kernels[i]; assert(sizeof(*desc) == 32); /*Setup the descritor table*/ memset(desc, 0, sizeof(*desc)); desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6); desc->desc2.sampler_count = 1; /* FIXME: */ desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5); desc->desc3.binding_table_entry_count = 1; /* FIXME: */ desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5); desc->desc4.constant_urb_entry_read_offset = 0; desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH; /*kernel start*/ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0), kernel->bo); /*Sampler State(VME state pointer)*/ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, (1 << 2), // i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2), vme_context->vme_state.bo); desc++; } dri_bo_unmap(bo); return VA_STATUS_SUCCESS; } static VAStatus gen6_vme_constant_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; // unsigned char *constant_buffer; unsigned int *vme_state_message; int mv_num = 32; if (vme_context->h264_level >= 30) { mv_num = 16; if (vme_context->h264_level >= 31) mv_num = 8; } dri_bo_map(vme_context->gpe_context.curbe.bo, 1); assert(vme_context->gpe_context.curbe.bo->virtual); // constant_buffer = vme_context->curbe.bo->virtual; vme_state_message = (unsigned int *)vme_context->gpe_context.curbe.bo->virtual; vme_state_message[31] = mv_num; /*TODO copy buffer into CURB*/ dri_bo_unmap( vme_context->gpe_context.curbe.bo); return VA_STATUS_SUCCESS; } static const unsigned int intra_mb_mode_cost_table[] = { 0x31110001, // for qp0 0x09110001, // for qp1 0x15030001, // for qp2 0x0b030001, // for qp3 0x0d030011, // for qp4 0x17210011, // for qp5 0x41210011, // for qp6 0x19210011, // for qp7 0x25050003, // for qp8 0x1b130003, // for qp9 0x1d130003, // for qp10 0x27070021, // for qp11 0x51310021, // for qp12 0x29090021, // for qp13 0x35150005, // for qp14 0x2b0b0013, // for qp15 0x2d0d0013, // for qp16 0x37170007, // for qp17 0x61410031, // for qp18 0x39190009, // for qp19 0x45250015, // for qp20 0x3b1b000b, // for qp21 0x3d1d000d, // for qp22 0x47270017, // for qp23 0x71510041, // for qp24 ! center for qp=0..30 0x49290019, // for qp25 0x55350025, // for qp26 0x4b2b001b, // for qp27 0x4d2d001d, // for qp28 0x57370027, // for qp29 0x81610051, // for qp30 0x57270017, // for qp31 0x81510041, // for qp32 ! center for qp=31..51 0x59290019, // for qp33 0x65350025, // for qp34 0x5b2b001b, // for qp35 0x5d2d001d, // for qp36 0x67370027, // for qp37 0x91610051, // for qp38 0x69390029, // for qp39 0x75450035, // for qp40 0x6b3b002b, // for qp41 0x6d3d002d, // for qp42 0x77470037, // for qp43 0xa1710061, // for qp44 0x79490039, // for qp45 0x85550045, // for qp46 0x7b4b003b, // for qp47 0x7d4d003d, // for qp48 0x87570047, // for qp49 0xb1810071, // for qp50 0x89590049 // for qp51 }; static void gen6_vme_state_setup_fixup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, unsigned int *vme_state_message) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; if (slice_param->slice_type != SLICE_TYPE_I && slice_param->slice_type != SLICE_TYPE_SI) return; if (encoder_context->rate_control_mode == VA_RC_CQP) vme_state_message[16] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta]; else vme_state_message[16] = intra_mb_mode_cost_table[mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY]; } static VAStatus gen6_vme_vme_state_setup(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; unsigned int *vme_state_message; int i; //building VME state message dri_bo_map(vme_context->vme_state.bo, 1); assert(vme_context->vme_state.bo->virtual); vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual; vme_state_message[0] = 0x01010101; vme_state_message[1] = 0x10010101; vme_state_message[2] = 0x0F0F0F0F; vme_state_message[3] = 0x100F0F0F; vme_state_message[4] = 0x01010101; vme_state_message[5] = 0x10010101; vme_state_message[6] = 0x0F0F0F0F; vme_state_message[7] = 0x100F0F0F; vme_state_message[8] = 0x01010101; vme_state_message[9] = 0x10010101; vme_state_message[10] = 0x0F0F0F0F; vme_state_message[11] = 0x000F0F0F; vme_state_message[12] = 0x00; vme_state_message[13] = 0x00; vme_state_message[14] = 0x4a4a; vme_state_message[15] = 0x0; vme_state_message[16] = 0x4a4a4a4a; vme_state_message[17] = 0x4a4a4a4a; vme_state_message[18] = 0x21110100; vme_state_message[19] = 0x61514131; for(i = 20; i < 32; i++) { vme_state_message[i] = 0; } //vme_state_message[16] = 0x42424242; //cost function LUT set 0 for Intra gen6_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message); dri_bo_unmap( vme_context->vme_state.bo); return VA_STATUS_SUCCESS; } static void gen6_vme_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, int transform_8x8_mode_flag, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int number_mb_cmds; int mb_x = 0, mb_y = 0; int i, s; unsigned int *command_ptr; dri_bo_map(vme_context->vme_batchbuffer.bo, 1); command_ptr = vme_context->vme_batchbuffer.bo->virtual; for (s = 0; s < encode_state->num_slice_params_ext; s++) { VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer; int slice_mb_begin = pSliceParameter->macroblock_address; int slice_mb_number = pSliceParameter->num_macroblocks; for (i = 0; i < slice_mb_number; ) { int mb_count = i + slice_mb_begin; mb_x = mb_count % mb_width; mb_y = mb_count / mb_width; if( i == 0 ) { number_mb_cmds = mb_width; // we must mark the slice edge. } else if ( (i + 128 ) <= slice_mb_number) { number_mb_cmds = 128; } else { number_mb_cmds = slice_mb_number - i; } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; /*inline data */ *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x); *command_ptr++ = (number_mb_cmds << 16 | transform_8x8_mode_flag | ((i==0) << 1)); i += number_mb_cmds; } } *command_ptr++ = 0; *command_ptr++ = MI_BATCH_BUFFER_END; dri_bo_unmap(vme_context->vme_batchbuffer.bo); } static void gen6_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; dri_bo *bo; i965_gpe_context_init(ctx, &vme_context->gpe_context); /* VME output buffer */ dri_bo_unreference(vme_context->vme_output.bo); vme_context->vme_output.bo = NULL; dri_bo_unreference(vme_context->vme_batchbuffer.bo); vme_context->vme_batchbuffer.bo = NULL; /* VME state */ dri_bo_unreference(vme_context->vme_state.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", 1024*16, 64); assert(bo); vme_context->vme_state.bo = bo; } static void gen6_vme_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct intel_batchbuffer *batch = encoder_context->base.batch; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; gen6_vme_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, is_intra ? AVC_VME_INTRA_SHADER : AVC_VME_INTER_SHADER, pPicParameter->pic_fields.bits.transform_8x8_mode_flag, encoder_context); intel_batchbuffer_start_atomic(batch, 0x1000); gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8)); OUT_RELOC(batch, vme_context->vme_batchbuffer.bo, I915_GEM_DOMAIN_COMMAND, 0, 0); ADVANCE_BATCH(batch); intel_batchbuffer_end_atomic(batch); } static VAStatus gen6_vme_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { VAStatus vaStatus = VA_STATUS_SUCCESS; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; struct gen6_vme_context *vme_context = encoder_context->vme_context; if (!vme_context->h264_level || (vme_context->h264_level != pSequenceParameter->level_idc)) { vme_context->h264_level = pSequenceParameter->level_idc; } /*Setup all the memory object*/ gen6_vme_surface_setup(ctx, encode_state, is_intra, encoder_context); gen6_vme_interface_setup(ctx, encode_state, encoder_context); gen6_vme_constant_setup(ctx, encode_state, encoder_context); gen6_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context); /*Programing media pipeline*/ gen6_vme_pipeline_programing(ctx, encode_state, encoder_context); return vaStatus; } static VAStatus gen6_vme_run(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; intel_batchbuffer_flush(batch); return VA_STATUS_SUCCESS; } static VAStatus gen6_vme_stop(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { return VA_STATUS_SUCCESS; } static VAStatus gen6_vme_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen6_vme_media_init(ctx, encoder_context); gen6_vme_prepare(ctx, encode_state, encoder_context); gen6_vme_run(ctx, encode_state, encoder_context); gen6_vme_stop(ctx, encode_state, encoder_context); return VA_STATUS_SUCCESS; } static void gen6_vme_context_destroy(void *context) { struct gen6_vme_context *vme_context = context; i965_gpe_context_destroy(&vme_context->gpe_context); dri_bo_unreference(vme_context->vme_output.bo); vme_context->vme_output.bo = NULL; dri_bo_unreference(vme_context->vme_state.bo); vme_context->vme_state.bo = NULL; dri_bo_unreference(vme_context->vme_batchbuffer.bo); vme_context->vme_batchbuffer.bo = NULL; free(vme_context); } Bool gen6_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = NULL; if (encoder_context->codec != CODEC_H264) { /* Never get here */ assert(0); return False; } vme_context = calloc(1, sizeof(struct gen6_vme_context)); vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6; vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data); vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH; vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1; vme_context->gpe_context.vfe_state.num_urb_entries = 16; vme_context->gpe_context.vfe_state.gpgpu_mode = 0; vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1; vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1; vme_context->video_coding_type = VIDEO_CODING_AVC; vme_context->vme_kernel_sum = AVC_VME_KERNEL_SUM; i965_gpe_load_kernels(ctx, &vme_context->gpe_context, gen6_vme_kernels, vme_context->vme_kernel_sum); encoder_context->vme_pipeline = gen6_vme_pipeline; vme_context->vme_surface2_setup = i965_gpe_surface2_setup; vme_context->vme_media_rw_surface_setup = i965_gpe_media_rw_surface_setup; vme_context->vme_buffer_suface_setup = i965_gpe_buffer_suface_setup; encoder_context->vme_context = vme_context; encoder_context->vme_context_destroy = gen6_vme_context_destroy; return True; } intel-driver-1.3.0/src/gen6_vme.h000066400000000000000000000156001231401140700165600ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWAR * * Authors: * Zhou Chang * */ #ifndef _GEN6_VME_H_ #define _GEN6_VME_H_ #include #include #include #include #include "i965_gpe_utils.h" #define INTRA_VME_OUTPUT_IN_BYTES 16 /* in bytes */ #define INTRA_VME_OUTPUT_IN_DWS (INTRA_VME_OUTPUT_IN_BYTES / 4) #define INTER_VME_OUTPUT_IN_BYTES 160 /* the first 128 bytes for MVs and the last 32 bytes for other info */ #define INTER_VME_OUTPUT_IN_DWS (INTER_VME_OUTPUT_IN_BYTES / 4) #define MAX_INTERFACE_DESC_GEN6 MAX_GPE_KERNELS #define MAX_MEDIA_SURFACES_GEN6 34 #define GEN6_VME_KERNEL_NUMBER 3 struct encode_state; struct intel_encoder_context; struct gen6_vme_context { struct i965_gpe_context gpe_context; struct { dri_bo *bo; } vme_state; struct i965_buffer_surface vme_output; struct i965_buffer_surface vme_batchbuffer; void (*vme_surface2_setup)(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); void (*vme_media_rw_surface_setup)(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); void (*vme_buffer_suface_setup)(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_buffer_surface *buffer_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); void (*vme_media_chroma_surface_setup)(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); void *vme_state_message; unsigned int h264_level; unsigned int video_coding_type; unsigned int vme_kernel_sum; unsigned int mpeg2_level; struct object_surface *used_reference_objects[2]; void *used_references[2]; unsigned int ref_index_in_mb[2]; }; #define MPEG2_PIC_WIDTH_HEIGHT 30 #define MPEG2_MV_RANGE 29 #define MPEG2_LEVEL_MASK 0x0f #define MPEG2_LEVEL_LOW 0x0a #define MPEG2_LEVEL_MAIN 0x08 #define MPEG2_LEVEL_HIGH 0x04 Bool gen75_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context); extern void intel_vme_update_mbmv_cost(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context); Bool gen7_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context); #define MODE_INTRA_NONPRED 0 #define MODE_INTRA_16X16 1 #define MODE_INTRA_8X8 2 #define MODE_INTRA_4X4 3 #define MODE_INTER_16X8 4 #define MODE_INTER_8X16 4 #define MODE_INTER_8X8 5 #define MODE_INTER_8X4 6 #define MODE_INTER_4X8 6 #define MODE_INTER_4X4 7 #define MODE_INTER_16X16 8 #define MODE_INTER_BWD 9 #define MODE_REFID_COST 10 #define MODE_CHROMA_INTRA 11 #define MODE_INTER_MV0 12 #define MODE_INTER_MV1 13 #define MODE_INTER_MV2 14 #define MODE_INTER_MV3 15 #define MODE_INTER_MV4 16 #define MODE_INTER_MV5 17 #define MODE_INTER_MV6 18 #define MODE_INTER_MV7 19 #define INTRA_PRED_AVAIL_FLAG_AE 0x60 #define INTRA_PRED_AVAIL_FLAG_B 0x10 #define INTRA_PRED_AVAIL_FLAG_C 0x8 #define INTRA_PRED_AVAIL_FLAG_D 0x4 #define INTRA_PRED_AVAIL_FLAG_BCD_MASK 0x1C extern void gen7_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, int transform_8x8_mode_flag, struct intel_encoder_context *encoder_context); extern void gen7_vme_scoreboard_init(VADriverContextP ctx, struct gen6_vme_context *vme_context); extern void intel_vme_mpeg2_state_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context); extern void gen7_vme_mpeg2_walker_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, struct intel_encoder_context *encoder_context); void intel_avc_vme_reference_state(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int list_index, int surface_index, void (* vme_source_surface_state)( VADriverContextP ctx, int index, struct object_surface *obj_surface, struct intel_encoder_context *encoder_context)); extern Bool gen8_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context); #endif /* _GEN6_VME_H_ */ intel-driver-1.3.0/src/gen75_mfc.c000066400000000000000000003156111231401140700166240ustar00rootroot00000000000000/* * Copyright © 2010-2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Zhao Yakui * Xiang Haihao * */ #include #include #include #include #include #include "intel_batchbuffer.h" #include "i965_defines.h" #include "i965_structs.h" #include "i965_drv_video.h" #include "i965_encoder.h" #include "i965_encoder_utils.h" #include "gen6_mfc.h" #include "gen6_vme.h" #include "intel_media.h" #define AVC_INTRA_RDO_OFFSET 4 #define AVC_INTER_RDO_OFFSET 10 #define AVC_INTER_MSG_OFFSET 8 #define AVC_INTER_MV_OFFSET 48 #define AVC_RDO_MASK 0xFFFF #define MFC_SOFTWARE_HASWELL 0 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7) #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index) #define B0_STEP_REV 2 #define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV) static const uint32_t gen75_mfc_batchbuffer_avc[][4] = { #include "shaders/utils/mfc_batchbuffer_hsw.g75b" }; static struct i965_kernel gen75_mfc_kernels[] = { { "MFC AVC INTRA BATCHBUFFER ", MFC_BATCHBUFFER_AVC_INTRA, gen75_mfc_batchbuffer_avc, sizeof(gen75_mfc_batchbuffer_avc), NULL }, }; #define INTER_MODE_MASK 0x03 #define INTER_8X8 0x03 #define INTER_16X8 0x01 #define INTER_8X16 0x02 #define SUBMB_SHAPE_MASK 0x00FF00 #define INTER_MV8 (4 << 20) #define INTER_MV32 (6 << 20) static void gen75_mfc_pipe_mode_select(VADriverContextP ctx, int standard_select, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; assert(standard_select == MFX_FORMAT_MPEG2 || standard_select == MFX_FORMAT_AVC); BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2)); OUT_BCS_BATCH(batch, (MFX_LONG_MODE << 17) | /* Must be long format for encoder */ (MFD_MODE_VLD << 15) | /* VLD mode */ (0 << 10) | /* Stream-Out Enable */ ((!!mfc_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */ ((!!mfc_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */ (0 << 5) | /* not in stitch mode */ (1 << 4) | /* encoding mode */ (standard_select << 0)); /* standard select: avc or mpeg2 */ OUT_BCS_BATCH(batch, (0 << 7) | /* expand NOA bus flag */ (0 << 6) | /* disable slice-level clock gating */ (0 << 5) | /* disable clock gating for NOA */ (0 << 4) | /* terminate if AVC motion and POC table error occurs */ (0 << 3) | /* terminate if AVC mbdata error occurs */ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ (0 << 1) | (0 << 0)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, ((mfc_context->surface_state.height - 1) << 18) | ((mfc_context->surface_state.width - 1) << 4)); OUT_BCS_BATCH(batch, (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */ (0 << 22) | /* surface object control state, FIXME??? */ ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */ (0 << 2) | /* must be 0 for interleave U/V */ (1 << 1) | /* must be tiled */ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */ OUT_BCS_BATCH(batch, (0 << 16) | /* must be 0 for interleave U/V */ (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_ind_obj_base_addr_state_bplus(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; BEGIN_BCS_BATCH(batch, 26); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2)); /* the DW1-3 is for the MFX indirect bistream offset */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW4-5 is the MFX upper bound */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW6-10 is for MFX Indirect MV Object Base Address */ OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ OUT_BCS_BATCH(batch, 0); /* the DW11-15 is for MFX IT-COFF. Not used on encoder */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW16-20 is for MFX indirect DBLK. Not used on encoder */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW21-25 is for MFC Indirect PAK-BSE Object Base Address for Encoder*/ OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, mfc_context->mfc_indirect_pak_bse_object.end_offset); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; struct i965_driver_data *i965 = i965_driver_data(ctx); if (IS_STEPPING_BPLUS(i965)) { gen75_mfc_ind_obj_base_addr_state_bplus(ctx, encoder_context); return; } BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* MFX Indirect MV Object Base Address */ OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /*MFC Indirect PAK-BSE Object Base Address for Encoder*/ OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, mfc_context->mfc_indirect_pak_bse_object.end_offset); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; BEGIN_BCS_BATCH(batch, 16); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2)); /*DW1. MB setting of frame */ OUT_BCS_BATCH(batch, ((width_in_mbs * height_in_mbs - 1) & 0xFFFF)); OUT_BCS_BATCH(batch, ((height_in_mbs - 1) << 16) | ((width_in_mbs - 1) << 0)); /* DW3 QP setting */ OUT_BCS_BATCH(batch, (0 << 24) | /* Second Chroma QP Offset */ (0 << 16) | /* Chroma QP Offset */ (0 << 14) | /* Max-bit conformance Intra flag */ (0 << 13) | /* Max Macroblock size conformance Inter flag */ (pPicParameter->pic_fields.bits.weighted_pred_flag << 12) | /*Weighted_Pred_Flag */ (pPicParameter->pic_fields.bits.weighted_bipred_idc << 10) | /* Weighted_BiPred_Idc */ (0 << 8) | /* FIXME: Image Structure */ (0 << 0) ); /* Current Decoed Image Frame Store ID, reserved in Encode mode */ OUT_BCS_BATCH(batch, (0 << 16) | /* Mininum Frame size */ (0 << 15) | /* Disable reading of Macroblock Status Buffer */ (0 << 14) | /* Load BitStream Pointer only once, 1 slic 1 frame */ (0 << 13) | /* CABAC 0 word insertion test enable */ (1 << 12) | /* MVUnpackedEnable,compliant to DXVA */ (1 << 10) | /* Chroma Format IDC, 4:2:0 */ (0 << 8) | /* FIXME: MbMvFormatFlag */ (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/ (0 << 6) | /* Only valid for VLD decoding mode */ (0 << 5) | /* Constrained Intra Predition Flag, from PPS */ (0 << 4) | /* Direct 8x8 inference flag */ (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/ (1 << 2) | /* Frame MB only flag */ (0 << 1) | /* MBAFF mode is in active */ (0 << 0)); /* Field picture flag */ /* DW5 Trellis quantization */ OUT_BCS_BATCH(batch, 0); /* Mainly about MB rate control and debug, just ignoring */ OUT_BCS_BATCH(batch, /* Inter and Intra Conformance Max size limit */ (0xBB8 << 16) | /* InterMbMaxSz */ (0xEE8) ); /* IntraMbMaxSz */ OUT_BCS_BATCH(batch, 0); /* Reserved */ /* DW8. QP delta */ OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */ OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */ /* DW10. Bit setting for MB */ OUT_BCS_BATCH(batch, 0x8C000000); OUT_BCS_BATCH(batch, 0x00010000); /* DW12. */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0x02010100); /* DW14. For short format */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_qm_state(VADriverContextP ctx, int qm_type, unsigned int *qm, int qm_length, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; unsigned int qm_buffer[16]; assert(qm_length <= 16); assert(sizeof(*qm) == 4); memcpy(qm_buffer, qm, qm_length * 4); BEGIN_BCS_BATCH(batch, 18); OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2)); OUT_BCS_BATCH(batch, qm_type << 0); intel_batchbuffer_data(batch, qm_buffer, 16 * 4); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned int qm[16] = { 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010 }; gen75_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, encoder_context); gen75_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, encoder_context); gen75_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, encoder_context); gen75_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, encoder_context); } static void gen75_mfc_fqm_state(VADriverContextP ctx, int fqm_type, unsigned int *fqm, int fqm_length, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; unsigned int fqm_buffer[32]; assert(fqm_length <= 32); assert(sizeof(*fqm) == 4); memcpy(fqm_buffer, fqm, fqm_length * 4); BEGIN_BCS_BATCH(batch, 34); OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2)); OUT_BCS_BATCH(batch, fqm_type << 0); intel_batchbuffer_data(batch, fqm_buffer, 32 * 4); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned int qm[32] = { 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000 }; gen75_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, encoder_context); gen75_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, encoder_context); gen75_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, encoder_context); gen75_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, encoder_context); } static void gen75_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context, unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw, int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag, struct intel_batchbuffer *batch) { if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, lenght_in_dws + 2); OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws + 2 - 2)); OUT_BCS_BATCH(batch, (0 << 16) | /* always start at offset 0 */ (data_bits_in_last_dw << 8) | (skip_emul_byte_count << 4) | (!!emulation_flag << 3) | ((!!is_last_header) << 2) | ((!!is_end_of_slice) << 1) | (0 << 0)); /* FIXME: ??? */ intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_init(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; dri_bo *bo; int i; int width_in_mbs = 0; int height_in_mbs = 0; int slice_batchbuffer_size; if (encoder_context->codec == CODEC_H264) { VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; width_in_mbs = pSequenceParameter->picture_width_in_mbs; height_in_mbs = pSequenceParameter->picture_height_in_mbs; } else { VAEncSequenceParameterBufferMPEG2 *pSequenceParameter = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; assert(encoder_context->codec == CODEC_MPEG2); width_in_mbs = ALIGN(pSequenceParameter->picture_width, 16) / 16; height_in_mbs = ALIGN(pSequenceParameter->picture_height, 16) / 16; } slice_batchbuffer_size = 64 * width_in_mbs * height_in_mbs + 4096 + (SLICE_HEADER + SLICE_TAIL) * encode_state->num_slice_params_ext; /*Encode common setup for MFC*/ dri_bo_unreference(mfc_context->post_deblocking_output.bo); mfc_context->post_deblocking_output.bo = NULL; dri_bo_unreference(mfc_context->pre_deblocking_output.bo); mfc_context->pre_deblocking_output.bo = NULL; dri_bo_unreference(mfc_context->uncompressed_picture_source.bo); mfc_context->uncompressed_picture_source.bo = NULL; dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo); mfc_context->mfc_indirect_pak_bse_object.bo = NULL; for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){ if ( mfc_context->direct_mv_buffers[i].bo != NULL); dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo); mfc_context->direct_mv_buffers[i].bo = NULL; } for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){ if (mfc_context->reference_surfaces[i].bo != NULL) dri_bo_unreference(mfc_context->reference_surfaces[i].bo); mfc_context->reference_surfaces[i].bo = NULL; } dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", width_in_mbs * 64, 64); assert(bo); mfc_context->intra_row_store_scratch_buffer.bo = bo; dri_bo_unreference(mfc_context->macroblock_status_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", width_in_mbs * height_in_mbs * 16, 64); assert(bo); mfc_context->macroblock_status_buffer.bo = bo; dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */ 64); assert(bo); mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo; dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", 2 * width_in_mbs * 64, /* 2 * width_in_mbs * 64 */ 0x1000); assert(bo); mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo; dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo); mfc_context->mfc_batchbuffer_surface.bo = NULL; dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo); mfc_context->aux_batchbuffer_surface.bo = NULL; if (mfc_context->aux_batchbuffer) intel_batchbuffer_free(mfc_context->aux_batchbuffer); mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, slice_batchbuffer_size); mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer; dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo); mfc_context->aux_batchbuffer_surface.pitch = 16; mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16; mfc_context->aux_batchbuffer_surface.size_block = 16; i965_gpe_context_init(ctx, &mfc_context->gpe_context); } static void gen75_mfc_pipe_buf_addr_state_bplus(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int i; BEGIN_BCS_BATCH(batch, 61); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2)); /* the DW1-3 is for pre_deblocking */ if (mfc_context->pre_deblocking_output.bo) OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); /* pre output addr */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW4-6 is for the post_deblocking */ if (mfc_context->post_deblocking_output.bo) OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* post output addr */ else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW7-9 is for the uncompressed_picture */ OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* uncompressed data */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW10-12 is for the mb status */ OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* StreamOut data*/ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW13-15 is for the intra_row_store_scratch */ OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW16-18 is for the deblocking filter */ OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW 19-50 is for Reference pictures*/ for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) { if ( mfc_context->reference_surfaces[i].bo != NULL) { OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); } else { OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); /* The DW 52-54 is for the MB status buffer */ OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* Macroblock status buffer*/ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW 55-57 is the ILDB buffer */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW 58-60 is the second ILDB buffer */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct i965_driver_data *i965 = i965_driver_data(ctx); int i; if (IS_STEPPING_BPLUS(i965)) { gen75_mfc_pipe_buf_addr_state_bplus(ctx, encoder_context); return; } BEGIN_BCS_BATCH(batch, 25); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2)); if (mfc_context->pre_deblocking_output.bo) OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); /* pre output addr */ if (mfc_context->post_deblocking_output.bo) OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* post output addr */ else OUT_BCS_BATCH(batch, 0); OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* uncompressed data */ OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* StreamOut data*/ OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* 7..22 Reference pictures*/ for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) { if ( mfc_context->reference_surfaces[i].bo != NULL) { OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); } else { OUT_BCS_BATCH(batch, 0); } } OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* Macroblock status buffer*/ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_avc_directmode_state_bplus(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int i; BEGIN_BCS_BATCH(batch, 71); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2)); /* Reference frames and Current frames */ /* the DW1-32 is for the direct MV for reference */ for(i = 0; i < NUM_MFC_DMV_BUFFERS - 2; i += 2) { if ( mfc_context->direct_mv_buffers[i].bo != NULL) { OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } OUT_BCS_BATCH(batch, 0); /* the DW34-36 is the MV for the current reference */ OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* POL list */ for(i = 0; i < 32; i++) { OUT_BCS_BATCH(batch, i/2); } OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct i965_driver_data *i965 = i965_driver_data(ctx); int i; if (IS_STEPPING_BPLUS(i965)) { gen75_mfc_avc_directmode_state_bplus(ctx, encoder_context); return; } BEGIN_BCS_BATCH(batch, 69); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2)); /* Reference frames and Current frames */ for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) { if ( mfc_context->direct_mv_buffers[i].bo != NULL) { OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } else { OUT_BCS_BATCH(batch, 0); } } /* POL list */ for(i = 0; i < 32; i++) { OUT_BCS_BATCH(batch, i/2); } OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_bsp_buf_base_addr_state_bplus(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2)); OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW4-6 is for MPR Row Store Scratch Buffer Base Address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW7-9 is for Bitplane Read Buffer Base Address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct i965_driver_data *i965 = i965_driver_data(ctx); if (IS_STEPPING_BPLUS(i965)) { gen75_mfc_bsp_buf_base_addr_state_bplus(ctx, encoder_context); return; } BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2)); OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_avc_pipeline_picture_programing( VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context); mfc_context->set_surface_state(ctx, encoder_context); mfc_context->ind_obj_base_addr_state(ctx, encoder_context); gen75_mfc_pipe_buf_addr_state(ctx, encoder_context); gen75_mfc_bsp_buf_base_addr_state(ctx, encoder_context); mfc_context->avc_img_state(ctx, encode_state, encoder_context); mfc_context->avc_qm_state(ctx, encoder_context); mfc_context->avc_fqm_state(ctx, encoder_context); gen75_mfc_avc_directmode_state(ctx, encoder_context); intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context); } static VAStatus gen75_mfc_run(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; intel_batchbuffer_flush(batch); //run the pipeline return VA_STATUS_SUCCESS; } static VAStatus gen75_mfc_stop(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int *encoded_bits_size) { VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VACodedBufferSegment *coded_buffer_segment; vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment); assert(vaStatus == VA_STATUS_SUCCESS); *encoded_bits_size = coded_buffer_segment->size * 8; i965_UnmapBuffer(ctx, pPicParameter->coded_buf); return VA_STATUS_SUCCESS; } static void gen75_mfc_avc_slice_state(VADriverContextP ctx, VAEncPictureParameterBufferH264 *pic_param, VAEncSliceParameterBufferH264 *slice_param, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int rate_control_enable, int qp, struct intel_batchbuffer *batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; int beginmb = slice_param->macroblock_address; int endmb = beginmb + slice_param->num_macroblocks; int beginx = beginmb % width_in_mbs; int beginy = beginmb / width_in_mbs; int nextx = endmb % width_in_mbs; int nexty = endmb / width_in_mbs; int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); int last_slice = (endmb == (width_in_mbs * height_in_mbs)); int maxQpN, maxQpP; unsigned char correct[6], grow, shrink; int i; int weighted_pred_idc = 0; unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom; unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom; int num_ref_l0 = 0, num_ref_l1 = 0; if (batch == NULL) batch = encoder_context->base.batch; if (slice_type == SLICE_TYPE_I) { luma_log2_weight_denom = 0; chroma_log2_weight_denom = 0; } else if (slice_type == SLICE_TYPE_P) { weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag; num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1; if (slice_param->num_ref_idx_active_override_flag) num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; } else if (slice_type == SLICE_TYPE_B) { weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc; num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1; num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1; if (slice_param->num_ref_idx_active_override_flag) { num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1; } if (weighted_pred_idc == 2) { /* 8.4.3 - Derivation process for prediction weights (8-279) */ luma_log2_weight_denom = 5; chroma_log2_weight_denom = 5; } } maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier; maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier; for (i = 0; i < 6; i++) correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i]; grow = mfc_context->bit_rate_control_context[slice_type].GrowInit + (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4); shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit + (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4); BEGIN_BCS_BATCH(batch, 11);; OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) ); OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/ OUT_BCS_BATCH(batch, (num_ref_l0 << 16) | (num_ref_l1 << 24) | (chroma_log2_weight_denom << 8) | (luma_log2_weight_denom << 0)); OUT_BCS_BATCH(batch, (weighted_pred_idc << 30) | (slice_param->direct_spatial_mv_pred_flag<<29) | /*Direct Prediction Type*/ (slice_param->disable_deblocking_filter_idc << 27) | (slice_param->cabac_init_idc << 24) | (qp<<16) | /*Slice Quantization Parameter*/ ((slice_param->slice_beta_offset_div2 & 0xf) << 8) | ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0)); OUT_BCS_BATCH(batch, (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/ (beginx << 16) | slice_param->macroblock_address ); OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/ OUT_BCS_BATCH(batch, (0/*rate_control_enable*/ << 31) | /*in CBR mode RateControlCounterEnable = enable*/ (1 << 30) | /*ResetRateControlCounter*/ (0 << 28) | /*RC Triggle Mode = Always Rate Control*/ (4 << 24) | /*RC Stable Tolerance, middle level*/ (0/*rate_control_enable*/ << 23) | /*RC Panic Enable*/ (0 << 22) | /*QP mode, don't modfiy CBP*/ (0 << 21) | /*MB Type Direct Conversion Enabled*/ (0 << 20) | /*MB Type Skip Conversion Enabled*/ (last_slice << 19) | /*IsLastSlice*/ (0 << 18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/ (1 << 17) | /*HeaderPresentFlag*/ (1 << 16) | /*SliceData PresentFlag*/ (1 << 15) | /*TailPresentFlag*/ (1 << 13) | /*RBSP NAL TYPE*/ (0 << 12) ); /*CabacZeroWordInsertionEnable*/ OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset); OUT_BCS_BATCH(batch, (maxQpN << 24) | /*Target QP - 24 is lowest QP*/ (maxQpP << 16) | /*Target QP + 20 is highest QP*/ (shrink << 8) | (grow << 0)); OUT_BCS_BATCH(batch, (correct[5] << 20) | (correct[4] << 16) | (correct[3] << 12) | (correct[2] << 8) | (correct[1] << 4) | (correct[0] << 0)); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } #if MFC_SOFTWARE_HASWELL static int gen75_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg, struct intel_encoder_context *encoder_context, unsigned char target_mb_size, unsigned char max_mb_size, struct intel_batchbuffer *batch) { int len_in_dwords = 12; unsigned int intra_msg; #define INTRA_MSG_FLAG (1 << 13) #define INTRA_MBTYPE_MASK (0x1F0000) if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, len_in_dwords); intra_msg = msg[0] & 0xC0FF; intra_msg |= INTRA_MSG_FLAG; intra_msg |= ((msg[0] & INTRA_MBTYPE_MASK) >> 8); OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, (0 << 24) | /* PackedMvNum, Debug*/ (0 << 20) | /* No motion vector */ (1 << 19) | /* CbpDcY */ (1 << 18) | /* CbpDcU */ (1 << 17) | /* CbpDcV */ intra_msg); OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x); /* Code Block Pattern for Y*/ OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */ /*Stuff for Intra MB*/ OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/ OUT_BCS_BATCH(batch, msg[2]); OUT_BCS_BATCH(batch, msg[3]&0xFF); /*MaxSizeInWord and TargetSzieInWord*/ OUT_BCS_BATCH(batch, (max_mb_size << 24) | (target_mb_size << 16) ); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); return len_in_dwords; } static int gen75_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int *msg, unsigned int offset, struct intel_encoder_context *encoder_context, unsigned char target_mb_size,unsigned char max_mb_size, int slice_type, struct intel_batchbuffer *batch) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int len_in_dwords = 12; unsigned int inter_msg = 0; if (batch == NULL) batch = encoder_context->base.batch; { #define MSG_MV_OFFSET 4 unsigned int *mv_ptr; mv_ptr = msg + MSG_MV_OFFSET; /* MV of VME output is based on 16 sub-blocks. So it is necessary * to convert them to be compatible with the format of AVC_PAK * command. */ if ((msg[0] & INTER_MODE_MASK) == INTER_8X16) { /* MV[0] and MV[2] are replicated */ mv_ptr[4] = mv_ptr[0]; mv_ptr[5] = mv_ptr[1]; mv_ptr[2] = mv_ptr[8]; mv_ptr[3] = mv_ptr[9]; mv_ptr[6] = mv_ptr[8]; mv_ptr[7] = mv_ptr[9]; } else if ((msg[0] & INTER_MODE_MASK) == INTER_16X8) { /* MV[0] and MV[1] are replicated */ mv_ptr[2] = mv_ptr[0]; mv_ptr[3] = mv_ptr[1]; mv_ptr[4] = mv_ptr[16]; mv_ptr[5] = mv_ptr[17]; mv_ptr[6] = mv_ptr[24]; mv_ptr[7] = mv_ptr[25]; } else if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) && !(msg[1] & SUBMB_SHAPE_MASK)) { /* Don't touch MV[0] or MV[1] */ mv_ptr[2] = mv_ptr[8]; mv_ptr[3] = mv_ptr[9]; mv_ptr[4] = mv_ptr[16]; mv_ptr[5] = mv_ptr[17]; mv_ptr[6] = mv_ptr[24]; mv_ptr[7] = mv_ptr[25]; } } BEGIN_BCS_BATCH(batch, len_in_dwords); OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); inter_msg = 32; /* MV quantity */ if ((msg[0] & INTER_MODE_MASK) == INTER_8X8) { if (msg[1] & SUBMB_SHAPE_MASK) inter_msg = 128; } OUT_BCS_BATCH(batch, inter_msg); /* 32 MV*/ OUT_BCS_BATCH(batch, offset); inter_msg = msg[0] & (0x1F00FFFF); inter_msg |= INTER_MV8; inter_msg |= ((1 << 19) | (1 << 18) | (1 << 17)); if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) && (msg[1] & SUBMB_SHAPE_MASK)) { inter_msg |= INTER_MV32; } OUT_BCS_BATCH(batch, inter_msg); OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/ OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ #if 0 if ( slice_type == SLICE_TYPE_B) { OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */ } else { OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ } #else OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ #endif inter_msg = msg[1] >> 8; /*Stuff for Inter MB*/ OUT_BCS_BATCH(batch, inter_msg); OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[0]); OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[1]); /*MaxSizeInWord and TargetSzieInWord*/ OUT_BCS_BATCH(batch, (max_mb_size << 24) | (target_mb_size << 16) ); OUT_BCS_BATCH(batch, 0x0); ADVANCE_BCS_BATCH(batch); return len_in_dwords; } static void gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int slice_index, struct intel_batchbuffer *slice_batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer; unsigned int *msg = NULL, offset = 0; unsigned char *msg_ptr = NULL; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs); int i,x,y; int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta; unsigned int rate_control_mode = encoder_context->rate_control_mode; unsigned char *slice_header = NULL; int slice_header_length_in_bits = 0; unsigned int tail_data[] = { 0x0, 0x0 }; int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type); int is_intra = slice_type == SLICE_TYPE_I; if (rate_control_mode == VA_RC_CBR) { qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY; pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp; } /* only support for 8-bit pixel bit-depth */ assert(pSequenceParameter->bit_depth_luma_minus8 == 0); assert(pSequenceParameter->bit_depth_chroma_minus8 == 0); assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52); assert(qp >= 0 && qp < 52); gen75_mfc_avc_slice_state(ctx, pPicParameter, pSliceParameter, encode_state, encoder_context, (rate_control_mode == VA_RC_CBR), qp, slice_batch); if ( slice_index == 0) intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header); // slice hander mfc_context->insert_object(ctx, encoder_context, (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f, 5, /* first 5 bytes are start code + nal unit type */ 1, 0, 1, slice_batch); dri_bo_map(vme_context->vme_output.bo , 1); msg_ptr = (unsigned char *)vme_context->vme_output.bo->virtual; if (is_intra) { msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block); } else { msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block); } for (i = pSliceParameter->macroblock_address; i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) { int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) ); x = i % width_in_mbs; y = i / width_in_mbs; msg = (unsigned int *) (msg_ptr + i * vme_context->vme_output.size_block); if (is_intra) { assert(msg); gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch); } else { int inter_rdo, intra_rdo; inter_rdo = msg[AVC_INTER_RDO_OFFSET] & AVC_RDO_MASK; intra_rdo = msg[AVC_INTRA_RDO_OFFSET] & AVC_RDO_MASK; offset = i * vme_context->vme_output.size_block + AVC_INTER_MV_OFFSET; if (intra_rdo < inter_rdo) { gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch); } else { msg += AVC_INTER_MSG_OFFSET; gen75_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, slice_type, slice_batch); } } } dri_bo_unmap(vme_context->vme_output.bo); if ( last_slice ) { mfc_context->insert_object(ctx, encoder_context, tail_data, 2, 8, 2, 1, 1, 0, slice_batch); } else { mfc_context->insert_object(ctx, encoder_context, tail_data, 1, 8, 1, 1, 1, 0, slice_batch); } free(slice_header); } static dri_bo * gen75_mfc_avc_software_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch; dri_bo *batch_bo; int i; int buffer_size; batch = mfc_context->aux_batchbuffer; batch_bo = batch->buffer; for (i = 0; i < encode_state->num_slice_params_ext; i++) { gen75_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch); } intel_batchbuffer_align(batch, 8); BEGIN_BCS_BATCH(batch, 2); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END); ADVANCE_BCS_BATCH(batch); dri_bo_reference(batch_bo); intel_batchbuffer_free(batch); mfc_context->aux_batchbuffer = NULL; return batch_bo; } #else static void gen75_mfc_batchbuffer_surfaces_input(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; assert(vme_context->vme_output.bo); mfc_context->buffer_suface_setup(ctx, &mfc_context->gpe_context, &vme_context->vme_output, BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT), SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT)); } static void gen75_mfc_batchbuffer_surfaces_output(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; assert(mfc_context->aux_batchbuffer_surface.bo); mfc_context->buffer_suface_setup(ctx, &mfc_context->gpe_context, &mfc_context->aux_batchbuffer_surface, BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER), SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER)); } static void gen75_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen75_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context); gen75_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context); } static void gen75_mfc_batchbuffer_idrt_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_interface_descriptor_data *desc; int i; dri_bo *bo; bo = mfc_context->gpe_context.idrt.bo; dri_bo_map(bo, 1); assert(bo->virtual); desc = bo->virtual; for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) { struct i965_kernel *kernel; kernel = &mfc_context->gpe_context.kernels[i]; assert(sizeof(*desc) == 32); /*Setup the descritor table*/ memset(desc, 0, sizeof(*desc)); desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6); desc->desc2.sampler_count = 0; desc->desc2.sampler_state_pointer = 0; desc->desc3.binding_table_entry_count = 2; desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5); desc->desc4.constant_urb_entry_read_offset = 0; desc->desc4.constant_urb_entry_read_length = 4; /*kernel start*/ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0), kernel->bo); desc++; } dri_bo_unmap(bo); } static void gen75_mfc_batchbuffer_constant_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; (void)mfc_context; } #define AVC_PAK_LEN_IN_BYTE 48 #define AVC_PAK_LEN_IN_OWORD 3 static void gen75_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch, uint32_t intra_flag, int head_offset, int number_mb_cmds, int slice_end_x, int slice_end_y, int mb_x, int mb_y, int width_in_mbs, int qp, uint32_t fwd_ref, uint32_t bwd_ref) { uint32_t temp_value; BEGIN_BATCH(batch, 14); OUT_BATCH(batch, CMD_MEDIA_OBJECT | (14 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /*inline data */ OUT_BATCH(batch, head_offset / 16); OUT_BATCH(batch, (intra_flag) | (qp << 16)); temp_value = (mb_x | (mb_y << 8) | (width_in_mbs << 16)); OUT_BATCH(batch, temp_value); OUT_BATCH(batch, number_mb_cmds); OUT_BATCH(batch, ((slice_end_y << 8) | (slice_end_x))); OUT_BATCH(batch, fwd_ref); OUT_BATCH(batch, bwd_ref); OUT_BATCH(batch, MI_NOOP); ADVANCE_BATCH(batch); } static void gen75_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx, struct intel_encoder_context *encoder_context, VAEncSliceParameterBufferH264 *slice_param, int head_offset, int qp, int last_slice) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_vme_context *vme_context = encoder_context->vme_context; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int total_mbs = slice_param->num_macroblocks; int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); int number_mb_cmds = 128; int starting_offset = 0; int mb_x, mb_y; int last_mb, slice_end_x, slice_end_y; int remaining_mb = total_mbs; uint32_t fwd_ref , bwd_ref, mb_flag; last_mb = slice_param->macroblock_address + total_mbs - 1; slice_end_x = last_mb % width_in_mbs; slice_end_y = last_mb / width_in_mbs; if (slice_type == SLICE_TYPE_I) { fwd_ref = 0; bwd_ref = 0; mb_flag = 1; } else { fwd_ref = vme_context->ref_index_in_mb[0]; bwd_ref = vme_context->ref_index_in_mb[1]; mb_flag = 0; } if (width_in_mbs >= 100) { number_mb_cmds = width_in_mbs / 5; } else if (width_in_mbs >= 80) { number_mb_cmds = width_in_mbs / 4; } else if (width_in_mbs >= 60) { number_mb_cmds = width_in_mbs / 3; } else if (width_in_mbs >= 40) { number_mb_cmds = width_in_mbs / 2; } else { number_mb_cmds = width_in_mbs; } do { if (number_mb_cmds >= remaining_mb) { number_mb_cmds = remaining_mb; } mb_x = (slice_param->macroblock_address + starting_offset) % width_in_mbs; mb_y = (slice_param->macroblock_address + starting_offset) / width_in_mbs; gen75_mfc_batchbuffer_emit_object_command(batch, mb_flag, head_offset, number_mb_cmds, slice_end_x, slice_end_y, mb_x, mb_y, width_in_mbs, qp, fwd_ref, bwd_ref); head_offset += (number_mb_cmds * AVC_PAK_LEN_IN_BYTE); remaining_mb -= number_mb_cmds; starting_offset += number_mb_cmds; } while (remaining_mb > 0); } /* * return size in Owords (16bytes) */ static void gen75_mfc_avc_batchbuffer_slice(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int slice_index) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs); int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta; unsigned int rate_control_mode = encoder_context->rate_control_mode; unsigned char *slice_header = NULL; int slice_header_length_in_bits = 0; unsigned int tail_data[] = { 0x0, 0x0 }; long head_offset; int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type); if (rate_control_mode == VA_RC_CBR) { qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY; pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp; } /* only support for 8-bit pixel bit-depth */ assert(pSequenceParameter->bit_depth_luma_minus8 == 0); assert(pSequenceParameter->bit_depth_chroma_minus8 == 0); assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52); assert(qp >= 0 && qp < 52); gen75_mfc_avc_slice_state(ctx, pPicParameter, pSliceParameter, encode_state, encoder_context, (rate_control_mode == VA_RC_CBR), qp, slice_batch); if (slice_index == 0) intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header); // slice hander mfc_context->insert_object(ctx, encoder_context, (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f, 5, /* first 5 bytes are start code + nal unit type */ 1, 0, 1, slice_batch); free(slice_header); intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */ head_offset = intel_batchbuffer_used_size(slice_batch); slice_batch->ptr += pSliceParameter->num_macroblocks * AVC_PAK_LEN_IN_BYTE; gen75_mfc_avc_batchbuffer_slice_command(ctx, encoder_context, pSliceParameter, head_offset, qp, last_slice); /* Aligned for tail */ intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */ if (last_slice) { mfc_context->insert_object(ctx, encoder_context, tail_data, 2, 8, 2, 1, 1, 0, slice_batch); } else { mfc_context->insert_object(ctx, encoder_context, tail_data, 1, 8, 1, 1, 1, 0, slice_batch); } return; } static void gen75_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct intel_batchbuffer *batch = encoder_context->base.batch; int i; intel_batchbuffer_start_atomic(batch, 0x4000); gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch); for ( i = 0; i < encode_state->num_slice_params_ext; i++) { gen75_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i); } { struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer; intel_batchbuffer_align(slice_batch, 8); BEGIN_BCS_BATCH(slice_batch, 2); OUT_BCS_BATCH(slice_batch, 0); OUT_BCS_BATCH(slice_batch, MI_BATCH_BUFFER_END); ADVANCE_BCS_BATCH(slice_batch); mfc_context->aux_batchbuffer = NULL; intel_batchbuffer_free(slice_batch); } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static void gen75_mfc_build_avc_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen75_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context); gen75_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context); gen75_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context); gen75_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context); } static dri_bo * gen75_mfc_avc_hardware_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo); gen75_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context); return mfc_context->aux_batchbuffer_surface.bo; } #endif static void gen75_mfc_avc_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; dri_bo *slice_batch_bo; if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) { fprintf(stderr, "Current VA driver don't support interlace mode!\n"); assert(0); return; } #if MFC_SOFTWARE_HASWELL slice_batch_bo = gen75_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context); #else slice_batch_bo = gen75_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context); #endif // begin programing intel_batchbuffer_start_atomic_bcs(batch, 0x4000); intel_batchbuffer_emit_mi_flush(batch); // picture level programing gen75_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context); BEGIN_BCS_BATCH(batch, 2); OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8)); OUT_BCS_RELOC(batch, slice_batch_bo, I915_GEM_DOMAIN_COMMAND, 0, 0); ADVANCE_BCS_BATCH(batch); // end programing intel_batchbuffer_end_atomic(batch); dri_bo_unreference(slice_batch_bo); } static VAStatus gen75_mfc_avc_encode_picture(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; unsigned int rate_control_mode = encoder_context->rate_control_mode; int current_frame_bits_size; int sts; for (;;) { gen75_mfc_init(ctx, encode_state, encoder_context); intel_mfc_avc_prepare(ctx, encode_state, encoder_context); /*Programing bcs pipeline*/ gen75_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline gen75_mfc_run(ctx, encode_state, encoder_context); if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) { gen75_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size); sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size); if (sts == BRC_NO_HRD_VIOLATION) { intel_mfc_hrd_context_update(encode_state, mfc_context); break; } else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) { if (!mfc_context->hrd.violation_noted) { fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow"); mfc_context->hrd.violation_noted = 1; } return VA_STATUS_SUCCESS; } } else { break; } } return VA_STATUS_SUCCESS; } /* * MPEG-2 */ static const int va_to_gen75_mpeg2_picture_type[3] = { 1, /* I */ 2, /* P */ 3 /* B */ }; static void gen75_mfc_mpeg2_pic_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context, struct encode_state *encode_state) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncPictureParameterBufferMPEG2 *pic_param; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; VAEncSliceParameterBufferMPEG2 *slice_param = NULL; assert(encode_state->pic_param_ext && encode_state->pic_param_ext->buffer); pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer; BEGIN_BCS_BATCH(batch, 13); OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2)); OUT_BCS_BATCH(batch, (pic_param->f_code[1][1] & 0xf) << 28 | /* f_code[1][1] */ (pic_param->f_code[1][0] & 0xf) << 24 | /* f_code[1][0] */ (pic_param->f_code[0][1] & 0xf) << 20 | /* f_code[0][1] */ (pic_param->f_code[0][0] & 0xf) << 16 | /* f_code[0][0] */ pic_param->picture_coding_extension.bits.intra_dc_precision << 14 | pic_param->picture_coding_extension.bits.picture_structure << 12 | pic_param->picture_coding_extension.bits.top_field_first << 11 | pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 | pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 | pic_param->picture_coding_extension.bits.q_scale_type << 8 | pic_param->picture_coding_extension.bits.intra_vlc_format << 7 | pic_param->picture_coding_extension.bits.alternate_scan << 6); OUT_BCS_BATCH(batch, 0 << 14 | /* LoadSlicePointerFlag, 0 means only loading bitstream pointer once */ va_to_gen75_mpeg2_picture_type[pic_param->picture_type] << 9 | 0); OUT_BCS_BATCH(batch, 1 << 31 | /* slice concealment */ (height_in_mbs - 1) << 16 | (width_in_mbs - 1)); if (slice_param && slice_param->quantiser_scale_code >= 14) OUT_BCS_BATCH(batch, (3 << 1) | (1 << 4) | (5 << 8) | (1 << 12)); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0xFFF << 16 | /* InterMBMaxSize */ 0xFFF << 0 | /* IntraMBMaxSize */ 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfc_mpeg2_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned char intra_qm[64] = { 8, 16, 19, 22, 26, 27, 29, 34, 16, 16, 22, 24, 27, 29, 34, 37, 19, 22, 26, 27, 29, 34, 34, 38, 22, 22, 26, 27, 29, 34, 37, 40, 22, 26, 27, 29, 32, 35, 40, 48, 26, 27, 29, 32, 35, 40, 48, 58, 26, 27, 29, 34, 38, 46, 56, 69, 27, 29, 35, 38, 46, 56, 69, 83 }; unsigned char non_intra_qm[64] = { 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16 }; gen75_mfc_qm_state(ctx, MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX, (unsigned int *)intra_qm, 16, encoder_context); gen75_mfc_qm_state(ctx, MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX, (unsigned int *)non_intra_qm, 16,encoder_context); } static void gen75_mfc_mpeg2_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned short intra_fqm[64] = { 65536/0x8, 65536/0x10, 65536/0x13, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, 65536/0x10, 65536/0x10, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1b, 65536/0x1b, 65536/0x1d, 65536/0x13, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, 65536/0x1d, 65536/0x1d, 65536/0x23, 65536/0x16, 65536/0x18, 65536/0x1b, 65536/0x1b, 65536/0x13, 65536/0x20, 65536/0x22, 65536/0x26, 65536/0x1a, 65536/0x1b, 65536/0x13, 65536/0x13, 65536/0x20, 65536/0x23, 65536/0x26, 65536/0x2e, 65536/0x1b, 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x23, 65536/0x28, 65536/0x2e, 65536/0x38, 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x25, 65536/0x28, 65536/0x30, 65536/0x38, 65536/0x45, 65536/0x22, 65536/0x25, 65536/0x26, 65536/0x28, 65536/0x30, 65536/0x3a, 65536/0x45, 65536/0x53, }; unsigned short non_intra_fqm[64] = { 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, }; gen75_mfc_fqm_state(ctx, MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX, (unsigned int *)intra_fqm, 32, encoder_context); gen75_mfc_fqm_state(ctx, MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX, (unsigned int *)non_intra_fqm, 32, encoder_context); } static void gen75_mfc_mpeg2_slicegroup_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context, int x, int y, int next_x, int next_y, int is_fisrt_slice_group, int is_last_slice_group, int intra_slice, int qp, struct intel_batchbuffer *batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, 8); OUT_BCS_BATCH(batch, MFC_MPEG2_SLICEGROUP_STATE | (8 - 2)); OUT_BCS_BATCH(batch, 0 << 31 | /* MbRateCtrlFlag */ !!is_last_slice_group << 19 | /* IsLastSliceGrp */ 1 << 17 | /* Insert Header before the first slice group data */ 1 << 16 | /* SliceData PresentFlag: always 1 */ 1 << 15 | /* TailPresentFlag: always 1 */ 0 << 14 | /* FirstSliceHdrDisabled: slice header for each slice */ !!intra_slice << 13 | /* IntraSlice */ !!intra_slice << 12 | /* IntraSliceFlag */ 0); OUT_BCS_BATCH(batch, next_y << 24 | next_x << 16 | y << 8 | x << 0 | 0); OUT_BCS_BATCH(batch, qp); /* FIXME: SliceGroupQp */ /* bitstream pointer is only loaded once for the first slice of a frame when * LoadSlicePointerFlag is 0 */ OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset); OUT_BCS_BATCH(batch, 0); /* FIXME: */ OUT_BCS_BATCH(batch, 0); /* FIXME: CorrectPoints */ OUT_BCS_BATCH(batch, 0); /* FIXME: CVxxx */ ADVANCE_BCS_BATCH(batch); } static int gen75_mfc_mpeg2_pak_object_intra(VADriverContextP ctx, struct intel_encoder_context *encoder_context, int x, int y, int first_mb_in_slice, int last_mb_in_slice, int first_mb_in_slice_group, int last_mb_in_slice_group, int mb_type, int qp_scale_code, int coded_block_pattern, unsigned char target_size_in_word, unsigned char max_size_in_word, struct intel_batchbuffer *batch) { int len_in_dwords = 9; if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, len_in_dwords); OUT_BCS_BATCH(batch, MFC_MPEG2_PAK_OBJECT | (len_in_dwords - 2)); OUT_BCS_BATCH(batch, 0 << 24 | /* PackedMvNum */ 0 << 20 | /* MvFormat */ 7 << 17 | /* CbpDcY/CbpDcU/CbpDcV */ 0 << 15 | /* TransformFlag: frame DCT */ 0 << 14 | /* FieldMbFlag */ 1 << 13 | /* IntraMbFlag */ mb_type << 8 | /* MbType: Intra */ 0 << 2 | /* SkipMbFlag */ 0 << 0 | /* InterMbMode */ 0); OUT_BCS_BATCH(batch, y << 16 | x); OUT_BCS_BATCH(batch, max_size_in_word << 24 | target_size_in_word << 16 | coded_block_pattern << 6 | /* CBP */ 0); OUT_BCS_BATCH(batch, last_mb_in_slice << 31 | first_mb_in_slice << 30 | 0 << 27 | /* EnableCoeffClamp */ last_mb_in_slice_group << 26 | 0 << 25 | /* MbSkipConvDisable */ first_mb_in_slice_group << 24 | 0 << 16 | /* MvFieldSelect */ qp_scale_code << 0 | 0); OUT_BCS_BATCH(batch, 0); /* MV[0][0] */ OUT_BCS_BATCH(batch, 0); /* MV[1][0] */ OUT_BCS_BATCH(batch, 0); /* MV[0][1] */ OUT_BCS_BATCH(batch, 0); /* MV[1][1] */ ADVANCE_BCS_BATCH(batch); return len_in_dwords; } #define MPEG2_INTER_MV_OFFSET 12 static struct _mv_ranges { int low; /* in the unit of 1/2 pixel */ int high; /* in the unit of 1/2 pixel */ } mv_ranges[] = { {0, 0}, {-16, 15}, {-32, 31}, {-64, 63}, {-128, 127}, {-256, 255}, {-512, 511}, {-1024, 1023}, {-2048, 2047}, {-4096, 4095} }; static int mpeg2_motion_vector(int mv, int pos, int display_max, int f_code) { if (mv + pos * 16 * 2 < 0 || mv + (pos + 1) * 16 * 2 > display_max * 2) mv = 0; if (f_code > 0 && f_code < 10) { if (mv < mv_ranges[f_code].low) mv = mv_ranges[f_code].low; if (mv > mv_ranges[f_code].high) mv = mv_ranges[f_code].high; } return mv; } static int gen75_mfc_mpeg2_pak_object_inter(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, unsigned int *msg, int width_in_mbs, int height_in_mbs, int x, int y, int first_mb_in_slice, int last_mb_in_slice, int first_mb_in_slice_group, int last_mb_in_slice_group, int qp_scale_code, unsigned char target_size_in_word, unsigned char max_size_in_word, struct intel_batchbuffer *batch) { VAEncPictureParameterBufferMPEG2 *pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; int len_in_dwords = 9; short *mvptr, mvx0, mvy0, mvx1, mvy1; if (batch == NULL) batch = encoder_context->base.batch; mvptr = (short *)(msg + MPEG2_INTER_MV_OFFSET); mvx0 = mpeg2_motion_vector(mvptr[0] / 2, x, width_in_mbs * 16, pic_param->f_code[0][0]); mvy0 = mpeg2_motion_vector(mvptr[1] / 2, y, height_in_mbs * 16, pic_param->f_code[0][0]); mvx1 = mpeg2_motion_vector(mvptr[2] / 2, x, width_in_mbs * 16, pic_param->f_code[1][0]); mvy1 = mpeg2_motion_vector(mvptr[3] / 2, y, height_in_mbs * 16, pic_param->f_code[1][0]); BEGIN_BCS_BATCH(batch, len_in_dwords); OUT_BCS_BATCH(batch, MFC_MPEG2_PAK_OBJECT | (len_in_dwords - 2)); OUT_BCS_BATCH(batch, 2 << 24 | /* PackedMvNum */ 7 << 20 | /* MvFormat */ 7 << 17 | /* CbpDcY/CbpDcU/CbpDcV */ 0 << 15 | /* TransformFlag: frame DCT */ 0 << 14 | /* FieldMbFlag */ 0 << 13 | /* IntraMbFlag */ 1 << 8 | /* MbType: Frame-based */ 0 << 2 | /* SkipMbFlag */ 0 << 0 | /* InterMbMode */ 0); OUT_BCS_BATCH(batch, y << 16 | x); OUT_BCS_BATCH(batch, max_size_in_word << 24 | target_size_in_word << 16 | 0x3f << 6 | /* CBP */ 0); OUT_BCS_BATCH(batch, last_mb_in_slice << 31 | first_mb_in_slice << 30 | 0 << 27 | /* EnableCoeffClamp */ last_mb_in_slice_group << 26 | 0 << 25 | /* MbSkipConvDisable */ first_mb_in_slice_group << 24 | 0 << 16 | /* MvFieldSelect */ qp_scale_code << 0 | 0); OUT_BCS_BATCH(batch, (mvx0 & 0xFFFF) | mvy0 << 16); /* MV[0][0] */ OUT_BCS_BATCH(batch, (mvx1 & 0xFFFF) | mvy1 << 16); /* MV[1][0] */ OUT_BCS_BATCH(batch, 0); /* MV[0][1] */ OUT_BCS_BATCH(batch, 0); /* MV[1][1] */ ADVANCE_BCS_BATCH(batch); return len_in_dwords; } static void intel_mfc_mpeg2_pipeline_header_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, struct intel_batchbuffer *slice_batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderMPEG2_SPS); if (encode_state->packed_header_data[idx]) { VAEncPackedHeaderParameterBuffer *param = NULL; unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer; unsigned int length_in_bits; assert(encode_state->packed_header_param[idx]); param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer; length_in_bits = param->bit_length; mfc_context->insert_object(ctx, encoder_context, header_data, ALIGN(length_in_bits, 32) >> 5, length_in_bits & 0x1f, 5, /* FIXME: check it */ 0, 0, 0, /* Needn't insert emulation bytes for MPEG-2 */ slice_batch); } idx = va_enc_packed_type_to_idx(VAEncPackedHeaderMPEG2_PPS); if (encode_state->packed_header_data[idx]) { VAEncPackedHeaderParameterBuffer *param = NULL; unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer; unsigned int length_in_bits; assert(encode_state->packed_header_param[idx]); param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer; length_in_bits = param->bit_length; mfc_context->insert_object(ctx, encoder_context, header_data, ALIGN(length_in_bits, 32) >> 5, length_in_bits & 0x1f, 5, /* FIXME: check it */ 0, 0, 0, /* Needn't insert emulation bytes for MPEG-2 */ slice_batch); } } static void gen75_mfc_mpeg2_pipeline_slice_group(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int slice_index, VAEncSliceParameterBufferMPEG2 *next_slice_group_param, struct intel_batchbuffer *slice_batch) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; VAEncSliceParameterBufferMPEG2 *slice_param = NULL; unsigned char tail_delimiter[] = {MPEG2_DELIMITER0, MPEG2_DELIMITER1, MPEG2_DELIMITER2, MPEG2_DELIMITER3, MPEG2_DELIMITER4, 0, 0, 0}; unsigned char section_delimiter[] = {0x0, 0x0, 0x0, 0x0}; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; int i, j; int h_start_pos, v_start_pos, h_next_start_pos, v_next_start_pos; unsigned int *msg = NULL; unsigned char *msg_ptr = NULL; slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[slice_index]->buffer; h_start_pos = slice_param->macroblock_address % width_in_mbs; v_start_pos = slice_param->macroblock_address / width_in_mbs; assert(h_start_pos + slice_param->num_macroblocks <= width_in_mbs); dri_bo_map(vme_context->vme_output.bo , 0); msg_ptr = (unsigned char *)vme_context->vme_output.bo->virtual; if (next_slice_group_param) { h_next_start_pos = next_slice_group_param->macroblock_address % width_in_mbs; v_next_start_pos = next_slice_group_param->macroblock_address / width_in_mbs; } else { h_next_start_pos = 0; v_next_start_pos = height_in_mbs; } gen75_mfc_mpeg2_slicegroup_state(ctx, encoder_context, h_start_pos, v_start_pos, h_next_start_pos, v_next_start_pos, slice_index == 0, next_slice_group_param == NULL, slice_param->is_intra_slice, slice_param->quantiser_scale_code, slice_batch); if (slice_index == 0) intel_mfc_mpeg2_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); /* Insert '00' to make sure the header is valid */ mfc_context->insert_object(ctx, encoder_context, (unsigned int*)section_delimiter, 1, 8, /* 8bits in the last DWORD */ 1, /* 1 byte */ 1, 0, 0, slice_batch); for (i = 0; i < encode_state->slice_params_ext[slice_index]->num_elements; i++) { /* PAK for each macroblocks */ for (j = 0; j < slice_param->num_macroblocks; j++) { int h_pos = (slice_param->macroblock_address + j) % width_in_mbs; int v_pos = (slice_param->macroblock_address + j) / width_in_mbs; int first_mb_in_slice = (j == 0); int last_mb_in_slice = (j == slice_param->num_macroblocks - 1); int first_mb_in_slice_group = (i == 0 && j == 0); int last_mb_in_slice_group = (i == encode_state->slice_params_ext[slice_index]->num_elements - 1 && j == slice_param->num_macroblocks - 1); msg = (unsigned int *)(msg_ptr + (slice_param->macroblock_address + j) * vme_context->vme_output.size_block); if (slice_param->is_intra_slice) { gen75_mfc_mpeg2_pak_object_intra(ctx, encoder_context, h_pos, v_pos, first_mb_in_slice, last_mb_in_slice, first_mb_in_slice_group, last_mb_in_slice_group, 0x1a, slice_param->quantiser_scale_code, 0x3f, 0, 0xff, slice_batch); } else { int inter_rdo, intra_rdo; inter_rdo = msg[AVC_INTER_RDO_OFFSET] & AVC_RDO_MASK; intra_rdo = msg[AVC_INTRA_RDO_OFFSET] & AVC_RDO_MASK; if (intra_rdo < inter_rdo) gen75_mfc_mpeg2_pak_object_intra(ctx, encoder_context, h_pos, v_pos, first_mb_in_slice, last_mb_in_slice, first_mb_in_slice_group, last_mb_in_slice_group, 0x1a, slice_param->quantiser_scale_code, 0x3f, 0, 0xff, slice_batch); else gen75_mfc_mpeg2_pak_object_inter(ctx, encode_state, encoder_context, msg, width_in_mbs, height_in_mbs, h_pos, v_pos, first_mb_in_slice, last_mb_in_slice, first_mb_in_slice_group, last_mb_in_slice_group, slice_param->quantiser_scale_code, 0, 0xff, slice_batch); } } slice_param++; } dri_bo_unmap(vme_context->vme_output.bo); /* tail data */ if (next_slice_group_param == NULL) { /* end of a picture */ mfc_context->insert_object(ctx, encoder_context, (unsigned int *)tail_delimiter, 2, 8, /* 8bits in the last DWORD */ 5, /* 5 bytes */ 1, 1, 0, slice_batch); } else { /* end of a lsice group */ mfc_context->insert_object(ctx, encoder_context, (unsigned int *)section_delimiter, 1, 8, /* 8bits in the last DWORD */ 1, /* 1 byte */ 1, 1, 0, slice_batch); } } /* * A batch buffer for all slices, including slice state, * slice insert object and slice pak object commands * */ static dri_bo * gen75_mfc_mpeg2_software_slice_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct intel_batchbuffer *batch; VAEncSliceParameterBufferMPEG2 *next_slice_group_param = NULL; dri_bo *batch_bo; int i; batch = mfc_context->aux_batchbuffer; batch_bo = batch->buffer; for (i = 0; i < encode_state->num_slice_params_ext; i++) { if (i == encode_state->num_slice_params_ext - 1) next_slice_group_param = NULL; else next_slice_group_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[i + 1]->buffer; gen75_mfc_mpeg2_pipeline_slice_group(ctx, encode_state, encoder_context, i, next_slice_group_param, batch); } intel_batchbuffer_align(batch, 8); BEGIN_BCS_BATCH(batch, 2); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END); ADVANCE_BCS_BATCH(batch); dri_bo_reference(batch_bo); intel_batchbuffer_free(batch); mfc_context->aux_batchbuffer = NULL; return batch_bo; } static void gen75_mfc_mpeg2_pipeline_picture_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; mfc_context->pipe_mode_select(ctx, MFX_FORMAT_MPEG2, encoder_context); mfc_context->set_surface_state(ctx, encoder_context); mfc_context->ind_obj_base_addr_state(ctx, encoder_context); gen75_mfc_pipe_buf_addr_state(ctx, encoder_context); gen75_mfc_bsp_buf_base_addr_state(ctx, encoder_context); gen75_mfc_mpeg2_pic_state(ctx, encoder_context, encode_state); gen75_mfc_mpeg2_qm_state(ctx, encoder_context); gen75_mfc_mpeg2_fqm_state(ctx, encoder_context); } static void gen75_mfc_mpeg2_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; dri_bo *slice_batch_bo; slice_batch_bo = gen75_mfc_mpeg2_software_slice_batchbuffer(ctx, encode_state, encoder_context); // begin programing intel_batchbuffer_start_atomic_bcs(batch, 0x4000); intel_batchbuffer_emit_mi_flush(batch); // picture level programing gen75_mfc_mpeg2_pipeline_picture_programing(ctx, encode_state, encoder_context); BEGIN_BCS_BATCH(batch, 2); OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8)); OUT_BCS_RELOC(batch, slice_batch_bo, I915_GEM_DOMAIN_COMMAND, 0, 0); ADVANCE_BCS_BATCH(batch); // end programing intel_batchbuffer_end_atomic(batch); dri_bo_unreference(slice_batch_bo); } static VAStatus intel_mfc_mpeg2_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct object_surface *obj_surface; struct object_buffer *obj_buffer; struct i965_coded_buffer_segment *coded_buffer_segment; VAStatus vaStatus = VA_STATUS_SUCCESS; dri_bo *bo; int i; /* reconstructed surface */ obj_surface = encode_state->reconstructed_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); mfc_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(mfc_context->pre_deblocking_output.bo); mfc_context->surface_state.width = obj_surface->orig_width; mfc_context->surface_state.height = obj_surface->orig_height; mfc_context->surface_state.w_pitch = obj_surface->width; mfc_context->surface_state.h_pitch = obj_surface->height; /* forward reference */ obj_surface = encode_state->reference_objects[0]; if (obj_surface && obj_surface->bo) { mfc_context->reference_surfaces[0].bo = obj_surface->bo; dri_bo_reference(mfc_context->reference_surfaces[0].bo); } else mfc_context->reference_surfaces[0].bo = NULL; /* backward reference */ obj_surface = encode_state->reference_objects[1]; if (obj_surface && obj_surface->bo) { mfc_context->reference_surfaces[1].bo = obj_surface->bo; dri_bo_reference(mfc_context->reference_surfaces[1].bo); } else { mfc_context->reference_surfaces[1].bo = mfc_context->reference_surfaces[0].bo; if (mfc_context->reference_surfaces[1].bo) dri_bo_reference(mfc_context->reference_surfaces[1].bo); } for (i = 2; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) { mfc_context->reference_surfaces[i].bo = mfc_context->reference_surfaces[i & 1].bo; if (mfc_context->reference_surfaces[i].bo) dri_bo_reference(mfc_context->reference_surfaces[i].bo); } /* input YUV surface */ obj_surface = encode_state->input_yuv_object; mfc_context->uncompressed_picture_source.bo = obj_surface->bo; dri_bo_reference(mfc_context->uncompressed_picture_source.bo); /* coded buffer */ obj_buffer = encode_state->coded_buf_object; bo = obj_buffer->buffer_store->bo; mfc_context->mfc_indirect_pak_bse_object.bo = bo; mfc_context->mfc_indirect_pak_bse_object.offset = I965_CODEDBUFFER_HEADER_SIZE; mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN(obj_buffer->size_element - 0x1000, 0x1000); dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo); /* set the internal flag to 0 to indicate the coded size is unknown */ dri_bo_map(bo, 1); coded_buffer_segment = (struct i965_coded_buffer_segment *)bo->virtual; coded_buffer_segment->mapped = 0; coded_buffer_segment->codec = encoder_context->codec; dri_bo_unmap(bo); return vaStatus; } static VAStatus gen75_mfc_mpeg2_encode_picture(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen75_mfc_init(ctx, encode_state, encoder_context); intel_mfc_mpeg2_prepare(ctx, encode_state, encoder_context); /*Programing bcs pipeline*/ gen75_mfc_mpeg2_pipeline_programing(ctx, encode_state, encoder_context); gen75_mfc_run(ctx, encode_state, encoder_context); return VA_STATUS_SUCCESS; } static void gen75_mfc_context_destroy(void *context) { struct gen6_mfc_context *mfc_context = context; int i; dri_bo_unreference(mfc_context->post_deblocking_output.bo); mfc_context->post_deblocking_output.bo = NULL; dri_bo_unreference(mfc_context->pre_deblocking_output.bo); mfc_context->pre_deblocking_output.bo = NULL; dri_bo_unreference(mfc_context->uncompressed_picture_source.bo); mfc_context->uncompressed_picture_source.bo = NULL; dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo); mfc_context->mfc_indirect_pak_bse_object.bo = NULL; for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){ dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo); mfc_context->direct_mv_buffers[i].bo = NULL; } dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo); mfc_context->intra_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(mfc_context->macroblock_status_buffer.bo); mfc_context->macroblock_status_buffer.bo = NULL; dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo); mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo); mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){ dri_bo_unreference(mfc_context->reference_surfaces[i].bo); mfc_context->reference_surfaces[i].bo = NULL; } i965_gpe_context_destroy(&mfc_context->gpe_context); dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo); mfc_context->mfc_batchbuffer_surface.bo = NULL; dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo); mfc_context->aux_batchbuffer_surface.bo = NULL; if (mfc_context->aux_batchbuffer) intel_batchbuffer_free(mfc_context->aux_batchbuffer); mfc_context->aux_batchbuffer = NULL; free(mfc_context); } static VAStatus gen75_mfc_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { VAStatus vaStatus; switch (profile) { case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: vaStatus = gen75_mfc_avc_encode_picture(ctx, encode_state, encoder_context); break; /* FIXME: add for other profile */ case VAProfileMPEG2Simple: case VAProfileMPEG2Main: vaStatus = gen75_mfc_mpeg2_encode_picture(ctx, encode_state, encoder_context); break; default: vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE; break; } return vaStatus; } Bool gen75_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context)); mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS; mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data); mfc_context->gpe_context.curbe.length = 32 * 4; mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1; mfc_context->gpe_context.vfe_state.num_urb_entries = 16; mfc_context->gpe_context.vfe_state.gpgpu_mode = 0; mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1; mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1; i965_gpe_load_kernels(ctx, &mfc_context->gpe_context, gen75_mfc_kernels, 1); mfc_context->pipe_mode_select = gen75_mfc_pipe_mode_select; mfc_context->set_surface_state = gen75_mfc_surface_state; mfc_context->ind_obj_base_addr_state = gen75_mfc_ind_obj_base_addr_state; mfc_context->avc_img_state = gen75_mfc_avc_img_state; mfc_context->avc_qm_state = gen75_mfc_avc_qm_state; mfc_context->avc_fqm_state = gen75_mfc_avc_fqm_state; mfc_context->insert_object = gen75_mfc_avc_insert_object; mfc_context->buffer_suface_setup = gen7_gpe_buffer_suface_setup; encoder_context->mfc_context = mfc_context; encoder_context->mfc_context_destroy = gen75_mfc_context_destroy; encoder_context->mfc_pipeline = gen75_mfc_pipeline; encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare; return True; } intel-driver-1.3.0/src/gen75_mfd.c000066400000000000000000003727501231401140700166340ustar00rootroot00000000000000/* * Copyright © 2011 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * Zhao Yakui * */ #include "sysdeps.h" #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_decoder_utils.h" #include "gen7_mfd.h" #include "intel_media.h" #define B0_STEP_REV 2 #define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV) static const uint32_t zigzag_direct[64] = { 0, 1, 8, 16, 9, 2, 3, 10, 17, 24, 32, 25, 18, 11, 4, 5, 12, 19, 26, 33, 40, 48, 41, 34, 27, 20, 13, 6, 7, 14, 21, 28, 35, 42, 49, 56, 57, 50, 43, 36, 29, 22, 15, 23, 30, 37, 44, 51, 58, 59, 52, 45, 38, 31, 39, 46, 53, 60, 61, 54, 47, 55, 62, 63 }; static void gen75_mfd_init_avc_surface(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, struct object_surface *obj_surface) { struct i965_driver_data *i965 = i965_driver_data(ctx); GenAvcSurface *gen7_avc_surface = obj_surface->private_data; int width_in_mbs, height_in_mbs; obj_surface->free_private_data = gen_free_avc_surface; width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */ if (!gen7_avc_surface) { gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1); assert((obj_surface->size & 0x3f) == 0); obj_surface->private_data = gen7_avc_surface; } gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag && !pic_param->seq_fields.bits.direct_8x8_inference_flag); if (gen7_avc_surface->dmv_top == NULL) { gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", width_in_mbs * height_in_mbs * 128, 0x1000); assert(gen7_avc_surface->dmv_top); } if (gen7_avc_surface->dmv_bottom_flag && gen7_avc_surface->dmv_bottom == NULL) { gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", width_in_mbs * height_in_mbs * 128, 0x1000); assert(gen7_avc_surface->dmv_bottom); } } static void gen75_mfd_pipe_mode_select(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; assert(standard_select == MFX_FORMAT_MPEG2 || standard_select == MFX_FORMAT_AVC || standard_select == MFX_FORMAT_VC1 || standard_select == MFX_FORMAT_JPEG); BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2)); OUT_BCS_BATCH(batch, (MFX_LONG_MODE << 17) | /* Currently only support long format */ (MFD_MODE_VLD << 15) | /* VLD mode */ (0 << 10) | /* disable Stream-Out */ (gen7_mfd_context->post_deblocking_output.valid << 9) | /* Post Deblocking Output */ (gen7_mfd_context->pre_deblocking_output.valid << 8) | /* Pre Deblocking Output */ (0 << 5) | /* not in stitch mode */ (MFX_CODEC_DECODE << 4) | /* decoding mode */ (standard_select << 0)); OUT_BCS_BATCH(batch, (0 << 4) | /* terminate if AVC motion and POC table error occurs */ (0 << 3) | /* terminate if AVC mbdata error occurs */ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ (0 << 1) | (0 << 0)); OUT_BCS_BATCH(batch, 0); /* pic status/error report id */ OUT_BCS_BATCH(batch, 0); /* reserved */ ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_surface_state(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct object_surface *obj_surface = decode_state->render_object; unsigned int y_cb_offset; unsigned int y_cr_offset; assert(obj_surface); y_cb_offset = obj_surface->y_cb_offset; y_cr_offset = obj_surface->y_cr_offset; BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, ((obj_surface->orig_height - 1) << 18) | ((obj_surface->orig_width - 1) << 4)); OUT_BCS_BATCH(batch, (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */ (0 << 22) | /* surface object control state, ignored */ ((obj_surface->width - 1) << 3) | /* pitch */ (0 << 2) | /* must be 0 */ (1 << 1) | /* must be tiled */ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */ OUT_BCS_BATCH(batch, (0 << 16) | /* X offset for U(Cb), must be 0 */ (y_cb_offset << 0)); /* Y offset for U(Cb) */ OUT_BCS_BATCH(batch, (0 << 16) | /* X offset for V(Cr), must be 0 */ (y_cr_offset << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */ ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_pipe_buf_addr_state_bplus(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int i; BEGIN_BCS_BATCH(batch, 61); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2)); /* Pre-deblock 1-3 */ if (gen7_mfd_context->pre_deblocking_output.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* Post-debloing 4-6 */ if (gen7_mfd_context->post_deblocking_output.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* uncompressed-video & stream out 7-12 */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* intra row-store scratch 13-15 */ if (gen7_mfd_context->intra_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* deblocking-filter-row-store 16-18 */ if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* DW 19..50 */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { struct object_surface *obj_surface; if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID && gen7_mfd_context->reference_surface[i].obj_surface && gen7_mfd_context->reference_surface[i].obj_surface->bo) { obj_surface = gen7_mfd_context->reference_surface[i].obj_surface; OUT_BCS_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } else { OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); } /* reference property 51 */ OUT_BCS_BATCH(batch, 0); /* Macroblock status & ILDB 52-57 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the second Macroblock status 58-60 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_pipe_buf_addr_state(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct i965_driver_data *i965 = i965_driver_data(ctx); int i; if (IS_STEPPING_BPLUS(i965)) { gen75_mfd_pipe_buf_addr_state_bplus(ctx, decode_state, standard_select, gen7_mfd_context); return; } BEGIN_BCS_BATCH(batch, 25); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2)); if (gen7_mfd_context->pre_deblocking_output.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (gen7_mfd_context->post_deblocking_output.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ if (gen7_mfd_context->intra_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); /* DW 7..22 */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { struct object_surface *obj_surface; if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID && gen7_mfd_context->reference_surface[i].obj_surface && gen7_mfd_context->reference_surface[i].obj_surface->bo) { obj_surface = gen7_mfd_context->reference_surface[i].obj_surface; OUT_BCS_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } else { OUT_BCS_BATCH(batch, 0); } } OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */ OUT_BCS_BATCH(batch, 0); /* ignore DW24 for decoding */ ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_ind_obj_base_addr_state_bplus(VADriverContextP ctx, dri_bo *slice_data_bo, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 26); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2)); /* MFX In BS 1-5 */ OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* Upper bound 4-5 */ OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ OUT_BCS_BATCH(batch, 0); /* MFX indirect MV 6-10 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* MFX IT_COFF 11-15 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* MFX IT_DBLK 16-20 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* MFX PAK_BSE object for encoder 21-25 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_ind_obj_base_addr_state(VADriverContextP ctx, dri_bo *slice_data_bo, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct i965_driver_data *i965 = i965_driver_data(ctx); if (IS_STEPPING_BPLUS(i965)) { gen75_mfd_ind_obj_base_addr_state_bplus(ctx, slice_data_bo, standard_select, gen7_mfd_context); return; } BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */ OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_bsp_buf_base_addr_state_bplus(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2)); if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* MPR Row Store Scratch buffer 4-6 */ if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* Bitplane 7-9 */ if (gen7_mfd_context->bitplane_read_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_bsp_buf_base_addr_state(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct i965_driver_data *i965 = i965_driver_data(ctx); if (IS_STEPPING_BPLUS(i965)) { gen75_mfd_bsp_buf_base_addr_state_bplus(ctx, decode_state, standard_select, gen7_mfd_context); return; } BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2)); if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (gen7_mfd_context->bitplane_read_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_qm_state(VADriverContextP ctx, int qm_type, unsigned char *qm, int qm_length, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; unsigned int qm_buffer[16]; assert(qm_length <= 16 * 4); memcpy(qm_buffer, qm, qm_length); BEGIN_BCS_BATCH(batch, 18); OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2)); OUT_BCS_BATCH(batch, qm_type << 0); intel_batchbuffer_data(batch, qm_buffer, 16 * 4); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_avc_img_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int img_struct; int mbaff_frame_flag; unsigned int width_in_mbs, height_in_mbs; VAPictureParameterBufferH264 *pic_param; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID)); if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD) img_struct = 1; else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD) img_struct = 3; else img_struct = 0; if ((img_struct & 0x1) == 0x1) { assert(pic_param->pic_fields.bits.field_pic_flag == 0x1); } else { assert(pic_param->pic_fields.bits.field_pic_flag == 0x0); } if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */ assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0); assert(pic_param->pic_fields.bits.field_pic_flag == 0); } else { assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */ } mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag && !pic_param->pic_fields.bits.field_pic_flag); width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */ /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */ assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */ pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */ assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */ BEGIN_BCS_BATCH(batch, 17); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (17 - 2)); OUT_BCS_BATCH(batch, (width_in_mbs * height_in_mbs - 1)); OUT_BCS_BATCH(batch, ((height_in_mbs - 1) << 16) | ((width_in_mbs - 1) << 0)); OUT_BCS_BATCH(batch, ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) | ((pic_param->chroma_qp_index_offset & 0x1f) << 16) | (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */ (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */ (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */ (pic_param->pic_fields.bits.weighted_bipred_idc << 10) | (img_struct << 8)); OUT_BCS_BATCH(batch, (pic_param->seq_fields.bits.chroma_format_idc << 10) | (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) | ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) | (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) | (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) | (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) | (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) | (mbaff_frame_flag << 1) | (pic_param->pic_fields.bits.field_pic_flag << 0)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_avc_qm_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAIQMatrixBufferH264 *iq_matrix; VAPictureParameterBufferH264 *pic_param; if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer; else iq_matrix = &gen7_mfd_context->iq_matrix.h264; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context); gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context); if (pic_param->pic_fields.bits.transform_8x8_mode_flag) { gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context); gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context); } } static void gen75_mfd_avc_picid_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFD_AVC_PICID_STATE | (10 - 2)); OUT_BCS_BATCH(batch, 1); // disable Picture ID Remapping OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_avc_directmode_state_bplus(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct object_surface *obj_surface; GenAvcSurface *gen7_avc_surface; VAPictureH264 *va_pic; int i, j; BEGIN_BCS_BATCH(batch, 71); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2)); /* reference surfaces 0..15 */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID && gen7_mfd_context->reference_surface[i].obj_surface && gen7_mfd_context->reference_surface[i].obj_surface->private_data) { obj_surface = gen7_mfd_context->reference_surface[i].obj_surface; gen7_avc_surface = obj_surface->private_data; OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } OUT_BCS_BATCH(batch, 0); /* the current decoding frame/field */ va_pic = &pic_param->CurrPic; obj_surface = decode_state->render_object; assert(obj_surface->bo && obj_surface->private_data); gen7_avc_surface = obj_surface->private_data; OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* POC List */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) { int found = 0; assert(gen7_mfd_context->reference_surface[i].obj_surface != NULL); for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) { va_pic = &pic_param->ReferenceFrames[j]; if (va_pic->flags & VA_PICTURE_H264_INVALID) continue; if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) { found = 1; break; } } assert(found == 1); assert(!(va_pic->flags & VA_PICTURE_H264_INVALID)); OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt); OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } va_pic = &pic_param->CurrPic; OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt); OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_avc_directmode_state(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct object_surface *obj_surface; GenAvcSurface *gen7_avc_surface; VAPictureH264 *va_pic; int i, j; if (IS_STEPPING_BPLUS(i965)) { gen75_mfd_avc_directmode_state_bplus(ctx, decode_state, pic_param, slice_param, gen7_mfd_context); return; } BEGIN_BCS_BATCH(batch, 69); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2)); /* reference surfaces 0..15 */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID && gen7_mfd_context->reference_surface[i].obj_surface && gen7_mfd_context->reference_surface[i].obj_surface->private_data) { obj_surface = gen7_mfd_context->reference_surface[i].obj_surface; gen7_avc_surface = obj_surface->private_data; OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); if (gen7_avc_surface->dmv_bottom_flag == 1) OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } /* the current decoding frame/field */ va_pic = &pic_param->CurrPic; obj_surface = decode_state->render_object; assert(obj_surface->bo && obj_surface->private_data); gen7_avc_surface = obj_surface->private_data; OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); if (gen7_avc_surface->dmv_bottom_flag == 1) OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* POC List */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) { int found = 0; assert(gen7_mfd_context->reference_surface[i].obj_surface != NULL); for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) { va_pic = &pic_param->ReferenceFrames[j]; if (va_pic->flags & VA_PICTURE_H264_INVALID) continue; if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) { found = 1; break; } } assert(found == 1); assert(!(va_pic->flags & VA_PICTURE_H264_INVALID)); OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt); OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } va_pic = &pic_param->CurrPic; OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt); OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_avc_slice_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, VASliceParameterBufferH264 *next_slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos; int num_ref_idx_l0, num_ref_idx_l1; int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag && pic_param->seq_fields.bits.mb_adaptive_frame_field_flag); int first_mb_in_slice = 0, first_mb_in_next_slice = 0; int slice_type; if (slice_param->slice_type == SLICE_TYPE_I || slice_param->slice_type == SLICE_TYPE_SI) { slice_type = SLICE_TYPE_I; } else if (slice_param->slice_type == SLICE_TYPE_P || slice_param->slice_type == SLICE_TYPE_SP) { slice_type = SLICE_TYPE_P; } else { assert(slice_param->slice_type == SLICE_TYPE_B); slice_type = SLICE_TYPE_B; } if (slice_type == SLICE_TYPE_I) { assert(slice_param->num_ref_idx_l0_active_minus1 == 0); assert(slice_param->num_ref_idx_l1_active_minus1 == 0); num_ref_idx_l0 = 0; num_ref_idx_l1 = 0; } else if (slice_type == SLICE_TYPE_P) { assert(slice_param->num_ref_idx_l1_active_minus1 == 0); num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = 0; } else { num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1; } first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture; slice_hor_pos = first_mb_in_slice % width_in_mbs; slice_ver_pos = first_mb_in_slice / width_in_mbs; if (next_slice_param) { first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture; next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs; next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs; } else { next_slice_hor_pos = 0; next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag); } BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */ OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2)); OUT_BCS_BATCH(batch, slice_type); OUT_BCS_BATCH(batch, (num_ref_idx_l1 << 24) | (num_ref_idx_l0 << 16) | (slice_param->chroma_log2_weight_denom << 8) | (slice_param->luma_log2_weight_denom << 0)); OUT_BCS_BATCH(batch, (slice_param->direct_spatial_mv_pred_flag << 29) | (slice_param->disable_deblocking_filter_idc << 27) | (slice_param->cabac_init_idc << 24) | ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) | ((slice_param->slice_beta_offset_div2 & 0xf) << 8) | ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0)); OUT_BCS_BATCH(batch, (slice_ver_pos << 24) | (slice_hor_pos << 16) | (first_mb_in_slice << 0)); OUT_BCS_BATCH(batch, (next_slice_ver_pos << 16) | (next_slice_hor_pos << 0)); OUT_BCS_BATCH(batch, (next_slice_param == NULL) << 19); /* last slice flag */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static inline void gen75_mfd_avc_ref_idx_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen7_mfd_context *gen7_mfd_context) { gen6_send_avc_ref_idx_state( gen7_mfd_context->base.batch, slice_param, gen7_mfd_context->reference_surface ); } static void gen75_mfd_avc_weightoffset_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int i, j, num_weight_offset_table = 0; short weightoffsets[32 * 6]; if ((slice_param->slice_type == SLICE_TYPE_P || slice_param->slice_type == SLICE_TYPE_SP) && (pic_param->pic_fields.bits.weighted_pred_flag == 1)) { num_weight_offset_table = 1; } if ((slice_param->slice_type == SLICE_TYPE_B) && (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) { num_weight_offset_table = 2; } for (i = 0; i < num_weight_offset_table; i++) { BEGIN_BCS_BATCH(batch, 98); OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2)); OUT_BCS_BATCH(batch, i); if (i == 0) { for (j = 0; j < 32; j++) { weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j]; weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j]; weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0]; weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0]; weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1]; weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1]; } } else { for (j = 0; j < 32; j++) { weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j]; weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j]; weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0]; weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0]; weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1]; weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1]; } } intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets)); ADVANCE_BCS_BATCH(batch); } } static void gen75_mfd_avc_bsd_object(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, dri_bo *slice_data_bo, VASliceParameterBufferH264 *next_slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int slice_data_bit_offset = avc_get_first_mb_bit_offset(slice_data_bo, slice_param, pic_param->pic_fields.bits.entropy_coding_mode_flag); /* the input bitsteam format on GEN7 differs from GEN6 */ BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2)); OUT_BCS_BATCH(batch, (slice_param->slice_data_size - slice_param->slice_data_offset)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset); OUT_BCS_BATCH(batch, (0 << 31) | (0 << 14) | (0 << 12) | (0 << 10) | (0 << 8)); OUT_BCS_BATCH(batch, ((slice_data_bit_offset >> 3) << 16) | (1 << 7) | (0 << 5) | (0 << 4) | ((next_slice_param == NULL) << 3) | /* LastSlice Flag */ (slice_data_bit_offset & 0x7)); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static inline void gen75_mfd_avc_context_init( VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context ) { /* Initialize flat scaling lists */ avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264); } static void gen75_mfd_avc_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAPictureParameterBufferH264 *pic_param; VASliceParameterBufferH264 *slice_param; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *bo; int i, j, enable_avc_ildb = 0; unsigned int width_in_mbs, height_in_mbs; for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); assert((slice_param->slice_type == SLICE_TYPE_I) || (slice_param->slice_type == SLICE_TYPE_SI) || (slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP) || (slice_param->slice_type == SLICE_TYPE_B)); if (slice_param->disable_deblocking_filter_idc != 1) { enable_avc_ildb = 1; break; } slice_param++; } } assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; intel_update_avc_frame_store_index(ctx, decode_state, pic_param, gen7_mfd_context->reference_surface); width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */ assert(height_in_mbs > 0 && height_in_mbs <= 256); /* Current decoded picture */ obj_surface = decode_state->render_object; obj_surface->flags &= ~SURFACE_REF_DIS_MASK; obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0); i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); /* initial uv component for YUV400 case */ if (pic_param->seq_fields.bits.chroma_format_idc == 0) { unsigned int uv_offset = obj_surface->width * obj_surface->height; unsigned int uv_size = obj_surface->width * obj_surface->height / 2; drm_intel_gem_bo_map_gtt(obj_surface->bo); memset(obj_surface->bo->virtual + uv_offset, 0x80, uv_size); drm_intel_gem_bo_unmap_gtt(obj_surface->bo); } gen75_mfd_init_avc_surface(ctx, pic_param, obj_surface); dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb; dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb; dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", width_in_mbs * 64, 0x1000); assert(bo); gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "deblocking filter row store", width_in_mbs * 64 * 4, 0x1000); assert(bo); gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 64 * 2, 0x1000); assert(bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "mpr row store", width_in_mbs * 64 * 2, 0x1000); assert(bo); gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1; gen7_mfd_context->bitplane_read_buffer.valid = 0; } static void gen75_mfd_avc_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferH264 *pic_param; VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; gen75_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context); gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context); gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context); gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context); gen75_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context); gen75_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context); gen75_mfd_avc_picid_state(ctx, decode_state, gen7_mfd_context); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); assert((slice_param->slice_type == SLICE_TYPE_I) || (slice_param->slice_type == SLICE_TYPE_SI) || (slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP) || (slice_param->slice_type == SLICE_TYPE_B)); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen75_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen7_mfd_context); gen75_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context); gen75_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context); gen75_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context); gen75_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static void gen75_mfd_mpeg2_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAPictureParameterBufferMPEG2 *pic_param; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *bo; unsigned int width_in_mbs; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16; mpeg2_set_reference_surfaces( ctx, gen7_mfd_context->reference_surface, decode_state, pic_param ); /* Current decoded picture */ obj_surface = decode_state->render_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = 1; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 96, 0x1000); assert(bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; gen7_mfd_context->post_deblocking_output.valid = 0; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0; gen7_mfd_context->bitplane_read_buffer.valid = 0; } static void gen75_mfd_mpeg2_pic_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferMPEG2 *pic_param; unsigned int slice_concealment_disable_bit = 0; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; slice_concealment_disable_bit = 1; BEGIN_BCS_BATCH(batch, 13); OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2)); OUT_BCS_BATCH(batch, (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */ ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */ ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */ ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */ pic_param->picture_coding_extension.bits.intra_dc_precision << 14 | pic_param->picture_coding_extension.bits.picture_structure << 12 | pic_param->picture_coding_extension.bits.top_field_first << 11 | pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 | pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 | pic_param->picture_coding_extension.bits.q_scale_type << 8 | pic_param->picture_coding_extension.bits.intra_vlc_format << 7 | pic_param->picture_coding_extension.bits.alternate_scan << 6); OUT_BCS_BATCH(batch, pic_param->picture_coding_type << 9); OUT_BCS_BATCH(batch, (slice_concealment_disable_bit << 31) | ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 | ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_mpeg2_qm_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2; int i, j; /* Update internal QM state */ if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) { VAIQMatrixBufferMPEG2 * const iq_matrix = (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer; if (gen_iq_matrix->load_intra_quantiser_matrix == -1 || iq_matrix->load_intra_quantiser_matrix) { gen_iq_matrix->load_intra_quantiser_matrix = iq_matrix->load_intra_quantiser_matrix; if (iq_matrix->load_intra_quantiser_matrix) { for (j = 0; j < 64; j++) gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] = iq_matrix->intra_quantiser_matrix[j]; } } if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 || iq_matrix->load_non_intra_quantiser_matrix) { gen_iq_matrix->load_non_intra_quantiser_matrix = iq_matrix->load_non_intra_quantiser_matrix; if (iq_matrix->load_non_intra_quantiser_matrix) { for (j = 0; j < 64; j++) gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] = iq_matrix->non_intra_quantiser_matrix[j]; } } } /* Commit QM state to HW */ for (i = 0; i < 2; i++) { unsigned char *qm = NULL; int qm_type; if (i == 0) { if (gen_iq_matrix->load_intra_quantiser_matrix) { qm = gen_iq_matrix->intra_quantiser_matrix; qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX; } } else { if (gen_iq_matrix->load_non_intra_quantiser_matrix) { qm = gen_iq_matrix->non_intra_quantiser_matrix; qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX; } } if (!qm) continue; gen75_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context); } } static void gen75_mfd_mpeg2_bsd_object(VADriverContextP ctx, VAPictureParameterBufferMPEG2 *pic_param, VASliceParameterBufferMPEG2 *slice_param, VASliceParameterBufferMPEG2 *next_slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16; int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0; if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD || pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD) is_field_pic = 1; is_field_pic_wa = is_field_pic && gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0; vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa); hpos0 = slice_param->slice_horizontal_position; if (next_slice_param == NULL) { vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic); hpos1 = 0; } else { vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa); hpos1 = next_slice_param->slice_horizontal_position; } mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0); BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2)); OUT_BCS_BATCH(batch, slice_param->slice_data_size - (slice_param->macroblock_offset >> 3)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3)); OUT_BCS_BATCH(batch, hpos0 << 24 | vpos0 << 16 | mb_count << 8 | (next_slice_param == NULL) << 5 | (next_slice_param == NULL) << 3 | (slice_param->macroblock_offset & 0x7)); OUT_BCS_BATCH(batch, (slice_param->quantiser_scale_code << 24) | (vpos1 << 8 | hpos1)); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_mpeg2_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferMPEG2 *pic_param; VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; gen75_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context); gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context); gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context); gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context); gen75_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context); gen75_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context); if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0) gen7_mfd_context->wa_mpeg2_slice_vertical_position = mpeg2_wa_slice_vertical_position(decode_state, pic_param); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen75_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static const int va_to_gen7_vc1_pic_type[5] = { GEN7_VC1_I_PICTURE, GEN7_VC1_P_PICTURE, GEN7_VC1_B_PICTURE, GEN7_VC1_BI_PICTURE, GEN7_VC1_P_PICTURE, }; static const int va_to_gen7_vc1_mv[4] = { 1, /* 1-MV */ 2, /* 1-MV half-pel */ 3, /* 1-MV half-pef bilinear */ 0, /* Mixed MV */ }; static const int b_picture_scale_factor[21] = { 128, 85, 170, 64, 192, 51, 102, 153, 204, 43, 215, 37, 74, 111, 148, 185, 222, 32, 96, 160, 224, }; static const int va_to_gen7_vc1_condover[3] = { 0, 2, 3 }; static const int va_to_gen7_vc1_profile[4] = { GEN7_VC1_SIMPLE_PROFILE, GEN7_VC1_MAIN_PROFILE, GEN7_VC1_RESERVED_PROFILE, GEN7_VC1_ADVANCED_PROFILE }; static void gen75_mfd_free_vc1_surface(void **data) { struct gen7_vc1_surface *gen7_vc1_surface = *data; if (!gen7_vc1_surface) return; dri_bo_unreference(gen7_vc1_surface->dmv); free(gen7_vc1_surface); *data = NULL; } static void gen75_mfd_init_vc1_surface(VADriverContextP ctx, VAPictureParameterBufferVC1 *pic_param, struct object_surface *obj_surface) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data; int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16; obj_surface->free_private_data = gen75_mfd_free_vc1_surface; if (!gen7_vc1_surface) { gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1); assert((obj_surface->size & 0x3f) == 0); obj_surface->private_data = gen7_vc1_surface; } gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type; if (gen7_vc1_surface->dmv == NULL) { gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", width_in_mbs * height_in_mbs * 64, 0x1000); } } static void gen75_mfd_vc1_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAPictureParameterBufferVC1 *pic_param; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *bo; int width_in_mbs; int picture_type; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; picture_type = pic_param->picture_fields.bits.picture_type; intel_update_vc1_frame_store_index(ctx, decode_state, pic_param, gen7_mfd_context->reference_surface); /* Current decoded picture */ obj_surface = decode_state->render_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); gen75_mfd_init_vc1_surface(ctx, pic_param, obj_surface); dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter; dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter; dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", width_in_mbs * 64, 0x1000); assert(bo); gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "deblocking filter row store", width_in_mbs * 7 * 64, 0x1000); assert(bo); gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 96, 0x1000); assert(bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0; gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value; dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo); if (gen7_mfd_context->bitplane_read_buffer.valid) { int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16; int bitplane_width = ALIGN(width_in_mbs, 2) / 2; int src_w, src_h; uint8_t *src = NULL, *dst = NULL; assert(decode_state->bit_plane->buffer); src = decode_state->bit_plane->buffer; bo = dri_bo_alloc(i965->intel.bufmgr, "VC-1 Bitplane", bitplane_width * height_in_mbs, 0x1000); assert(bo); gen7_mfd_context->bitplane_read_buffer.bo = bo; dri_bo_map(bo, True); assert(bo->virtual); dst = bo->virtual; for (src_h = 0; src_h < height_in_mbs; src_h++) { for(src_w = 0; src_w < width_in_mbs; src_w++) { int src_index, dst_index; int src_shift; uint8_t src_value; src_index = (src_h * width_in_mbs + src_w) / 2; src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4; src_value = ((src[src_index] >> src_shift) & 0xf); if (picture_type == GEN7_VC1_SKIPPED_PICTURE){ src_value |= 0x2; } dst_index = src_w / 2; dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4)); } if (src_w & 1) dst[src_w / 2] >>= 4; dst += bitplane_width; } dri_bo_unmap(bo); } else gen7_mfd_context->bitplane_read_buffer.bo = NULL; } static void gen75_mfd_vc1_pic_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferVC1 *pic_param; struct object_surface *obj_surface; int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq; int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel; int unified_mv_mode; int ref_field_pic_polarity = 0; int scale_factor = 0; int trans_ac_y = 0; int dmv_surface_valid = 0; int brfd = 0; int fcm = 0; int picture_type; int profile; int overlap; int interpolation_mode = 0; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile]; dquant = pic_param->pic_quantizer_fields.bits.dquant; dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame; dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile; dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge; dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge; dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level; alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer; if (dquant == 0) { alt_pquant_config = 0; alt_pquant_edge_mask = 0; } else if (dquant == 2) { alt_pquant_config = 1; alt_pquant_edge_mask = 0xf; } else { assert(dquant == 1); if (dquantfrm == 0) { alt_pquant_config = 0; alt_pquant_edge_mask = 0; alt_pq = 0; } else { assert(dquantfrm == 1); alt_pquant_config = 1; switch (dqprofile) { case 3: if (dqbilevel == 0) { alt_pquant_config = 2; alt_pquant_edge_mask = 0; } else { assert(dqbilevel == 1); alt_pquant_config = 3; alt_pquant_edge_mask = 0; } break; case 0: alt_pquant_edge_mask = 0xf; break; case 1: if (dqdbedge == 3) alt_pquant_edge_mask = 0x9; else alt_pquant_edge_mask = (0x3 << dqdbedge); break; case 2: alt_pquant_edge_mask = (0x1 << dqsbedge); break; default: assert(0); } } } if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) { assert(pic_param->mv_fields.bits.mv_mode2 < 4); unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2]; } else { assert(pic_param->mv_fields.bits.mv_mode < 4); unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode]; } if (pic_param->sequence_fields.bits.interlace == 1 && pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */ /* FIXME: calculate reference field picture polarity */ assert(0); ref_field_pic_polarity = 0; } if (pic_param->b_picture_fraction < 21) scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction]; picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type]; if (profile == GEN7_VC1_ADVANCED_PROFILE && picture_type == GEN7_VC1_I_PICTURE) picture_type = GEN7_VC1_BI_PICTURE; if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */ trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2; else { trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1; /* * 8.3.6.2.1 Transform Type Selection * If variable-sized transform coding is not enabled, * then the 8x8 transform shall be used for all blocks. * it is also MFX_VC1_PIC_STATE requirement. */ if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) { pic_param->transform_fields.bits.mb_level_transform_type_flag = 1; pic_param->transform_fields.bits.frame_level_transform_type = 0; } } if (picture_type == GEN7_VC1_B_PICTURE) { struct gen7_vc1_surface *gen7_vc1_surface = NULL; obj_surface = decode_state->reference_objects[1]; if (obj_surface) gen7_vc1_surface = obj_surface->private_data; if (!gen7_vc1_surface || (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE || va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE)) dmv_surface_valid = 0; else dmv_surface_valid = 1; } assert(pic_param->picture_fields.bits.frame_coding_mode < 3); if (pic_param->picture_fields.bits.frame_coding_mode < 2) fcm = pic_param->picture_fields.bits.frame_coding_mode; else { if (pic_param->picture_fields.bits.top_field_first) fcm = 2; else fcm = 3; } if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */ brfd = pic_param->reference_fields.bits.reference_distance; brfd = (scale_factor * brfd) >> 8; brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1; if (brfd < 0) brfd = 0; } overlap = 0; if (profile != GEN7_VC1_ADVANCED_PROFILE){ if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 && pic_param->picture_fields.bits.picture_type != GEN7_VC1_B_PICTURE) { overlap = 1; } }else { if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_P_PICTURE && pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){ overlap = 1; } if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_I_PICTURE || pic_param->picture_fields.bits.picture_type == GEN7_VC1_BI_PICTURE){ if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){ overlap = 1; } else if (va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 2 || va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 3) { overlap = 1; } } } assert(pic_param->conditional_overlap_flag < 3); assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */ if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear || (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation && pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear)) interpolation_mode = 9; /* Half-pel bilinear */ else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel || (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation && pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel)) interpolation_mode = 1; /* Half-pel bicubic */ else interpolation_mode = 0; /* Quarter-pel bicubic */ BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2)); OUT_BCS_BATCH(batch, (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) | ((ALIGN(pic_param->coded_width, 16) / 16) - 1)); OUT_BCS_BATCH(batch, ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 | dmv_surface_valid << 15 | (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */ pic_param->rounding_control << 13 | pic_param->sequence_fields.bits.syncmarker << 12 | interpolation_mode << 8 | 0 << 7 | /* FIXME: scale up or down ??? */ pic_param->range_reduction_frame << 6 | pic_param->entrypoint_fields.bits.loopfilter << 5 | overlap << 4 | !pic_param->picture_fields.bits.is_first_field << 3 | (pic_param->sequence_fields.bits.profile == 3) << 0); OUT_BCS_BATCH(batch, va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 | picture_type << 26 | fcm << 24 | alt_pq << 16 | pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 | scale_factor << 0); OUT_BCS_BATCH(batch, unified_mv_mode << 28 | pic_param->mv_fields.bits.four_mv_switch << 27 | pic_param->fast_uvmc_flag << 26 | ref_field_pic_polarity << 25 | pic_param->reference_fields.bits.num_reference_pictures << 24 | pic_param->reference_fields.bits.reference_distance << 20 | pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */ pic_param->mv_fields.bits.extended_dmv_range << 10 | pic_param->mv_fields.bits.extended_mv_range << 8 | alt_pquant_edge_mask << 4 | alt_pquant_config << 2 | pic_param->pic_quantizer_fields.bits.half_qp << 1 | pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0); OUT_BCS_BATCH(batch, !!pic_param->bitplane_present.value << 31 | !pic_param->bitplane_present.flags.bp_forward_mb << 30 | !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 | !pic_param->bitplane_present.flags.bp_skip_mb << 28 | !pic_param->bitplane_present.flags.bp_direct_mb << 27 | !pic_param->bitplane_present.flags.bp_overflags << 26 | !pic_param->bitplane_present.flags.bp_ac_pred << 25 | !pic_param->bitplane_present.flags.bp_field_tx << 24 | pic_param->mv_fields.bits.mv_table << 20 | pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 | pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 | pic_param->transform_fields.bits.frame_level_transform_type << 12 | pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 | pic_param->mb_mode_table << 8 | trans_ac_y << 6 | pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 | pic_param->transform_fields.bits.intra_transform_dc_table << 3 | pic_param->cbp_table << 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_vc1_pred_pipe_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferVC1 *pic_param; int intensitycomp_single; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation); BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0 << 14 | /* FIXME: double ??? */ 0 << 12 | intensitycomp_single << 10 | intensitycomp_single << 8 | 0 << 4 | /* FIXME: interlace mode */ 0); OUT_BCS_BATCH(batch, pic_param->luma_shift << 16 | pic_param->luma_scale << 0); /* FIXME: Luma Scaling */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_vc1_directmode_state_bplus(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct object_surface *obj_surface; dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL; obj_surface = decode_state->render_object; if (obj_surface && obj_surface->private_data) { dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv; } obj_surface = decode_state->reference_objects[1]; if (obj_surface && obj_surface->private_data) { dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv; } BEGIN_BCS_BATCH(batch, 7); OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (7 - 2)); if (dmv_write_buffer) OUT_BCS_RELOC(batch, dmv_write_buffer, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); if (dmv_read_buffer) OUT_BCS_RELOC(batch, dmv_read_buffer, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_vc1_directmode_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL; if (IS_STEPPING_BPLUS(i965)) { gen75_mfd_vc1_directmode_state_bplus(ctx, decode_state, gen7_mfd_context); return; } obj_surface = decode_state->render_object; if (obj_surface && obj_surface->private_data) { dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv; } obj_surface = decode_state->reference_objects[1]; if (obj_surface && obj_surface->private_data) { dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv; } BEGIN_BCS_BATCH(batch, 3); OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2)); if (dmv_write_buffer) OUT_BCS_RELOC(batch, dmv_write_buffer, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (dmv_read_buffer) OUT_BCS_RELOC(batch, dmv_read_buffer, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static int gen75_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile) { int out_slice_data_bit_offset; int slice_header_size = in_slice_data_bit_offset / 8; int i, j; if (profile != 3) out_slice_data_bit_offset = in_slice_data_bit_offset; else { for (i = 0, j = 0; i < slice_header_size; i++, j++) { if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) { i++, j += 2; } } out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8; } return out_slice_data_bit_offset; } static void gen75_mfd_vc1_bsd_object(VADriverContextP ctx, VAPictureParameterBufferVC1 *pic_param, VASliceParameterBufferVC1 *slice_param, VASliceParameterBufferVC1 *next_slice_param, dri_bo *slice_data_bo, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int next_slice_start_vert_pos; int macroblock_offset; uint8_t *slice_data = NULL; dri_bo_map(slice_data_bo, 0); slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset); macroblock_offset = gen75_mfd_vc1_get_macroblock_bit_offset(slice_data, slice_param->macroblock_offset, pic_param->sequence_fields.bits.profile); dri_bo_unmap(slice_data_bo); if (next_slice_param) next_slice_start_vert_pos = next_slice_param->slice_vertical_position; else next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16; BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2)); OUT_BCS_BATCH(batch, slice_param->slice_data_size - (macroblock_offset >> 3)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset + (macroblock_offset >> 3)); OUT_BCS_BATCH(batch, slice_param->slice_vertical_position << 16 | next_slice_start_vert_pos << 0); OUT_BCS_BATCH(batch, (macroblock_offset & 0x7)); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_vc1_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferVC1 *pic_param; VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; gen75_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context); gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context); gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context); gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context); gen75_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context); gen75_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context); gen75_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen75_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static void gen75_mfd_jpeg_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct object_surface *obj_surface; VAPictureParameterBufferJPEGBaseline *pic_param; int subsampling = SUBSAMPLE_YUV420; int fourcc = VA_FOURCC('I', 'M', 'C', '3'); pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer; if (pic_param->num_components == 1) { subsampling = SUBSAMPLE_YUV400; fourcc = VA_FOURCC('Y', '8', '0', '0'); } else if (pic_param->num_components == 3) { int h1 = pic_param->components[0].h_sampling_factor; int h2 = pic_param->components[1].h_sampling_factor; int h3 = pic_param->components[2].h_sampling_factor; int v1 = pic_param->components[0].v_sampling_factor; int v2 = pic_param->components[1].v_sampling_factor; int v3 = pic_param->components[2].v_sampling_factor; if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV420; fourcc = VA_FOURCC('I', 'M', 'C', '3'); } else if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV422H; fourcc = VA_FOURCC('4', '2', '2', 'H'); } else if (h1 == 1 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV444; fourcc = VA_FOURCC('4', '4', '4', 'P'); } else if (h1 == 4 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV411; fourcc = VA_FOURCC('4', '1', '1', 'P'); } else if (h1 == 1 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV422V; fourcc = VA_FOURCC('4', '2', '2', 'V'); } else if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 2 && v3 == 2) { subsampling = SUBSAMPLE_YUV422H; fourcc = VA_FOURCC('4', '2', '2', 'H'); } else if (h2 == 2 && h2 == 2 && h3 == 2 && v1 == 2 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV422V; fourcc = VA_FOURCC('4', '2', '2', 'V'); } else assert(0); } else { assert(0); } /* Current decoded picture */ obj_surface = decode_state->render_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, fourcc, subsampling); dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = 1; gen7_mfd_context->post_deblocking_output.bo = NULL; gen7_mfd_context->post_deblocking_output.valid = 0; gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0; gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0; gen7_mfd_context->bitplane_read_buffer.bo = NULL; gen7_mfd_context->bitplane_read_buffer.valid = 0; } static const int va_to_gen7_jpeg_rotation[4] = { GEN7_JPEG_ROTATION_0, GEN7_JPEG_ROTATION_90, GEN7_JPEG_ROTATION_180, GEN7_JPEG_ROTATION_270 }; static void gen75_mfd_jpeg_pic_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferJPEGBaseline *pic_param; int chroma_type = GEN7_YUV420; int frame_width_in_blks; int frame_height_in_blks; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer; if (pic_param->num_components == 1) chroma_type = GEN7_YUV400; else if (pic_param->num_components == 3) { int h1 = pic_param->components[0].h_sampling_factor; int h2 = pic_param->components[1].h_sampling_factor; int h3 = pic_param->components[2].h_sampling_factor; int v1 = pic_param->components[0].v_sampling_factor; int v2 = pic_param->components[1].v_sampling_factor; int v3 = pic_param->components[2].v_sampling_factor; if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV420; else if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV422H_2Y; else if (h1 == 1 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV444; else if (h1 == 4 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV411; else if (h1 == 1 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV422V_2Y; else if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 2 && v3 == 2) chroma_type = GEN7_YUV422H_4Y; else if (h2 == 2 && h2 == 2 && h3 == 2 && v1 == 2 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV422V_4Y; else assert(0); } if (chroma_type == GEN7_YUV400 || chroma_type == GEN7_YUV444 || chroma_type == GEN7_YUV422V_2Y) { frame_width_in_blks = ((pic_param->picture_width + 7) / 8); frame_height_in_blks = ((pic_param->picture_height + 7) / 8); } else if (chroma_type == GEN7_YUV411) { frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4; frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4; } else { frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2; frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2; } BEGIN_BCS_BATCH(batch, 3); OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2)); OUT_BCS_BATCH(batch, (va_to_gen7_jpeg_rotation[0] << 4) | /* without rotation */ (chroma_type << 0)); OUT_BCS_BATCH(batch, ((frame_height_in_blks - 1) << 16) | /* FrameHeightInBlks */ ((frame_width_in_blks - 1) << 0)); /* FrameWidthInBlks */ ADVANCE_BCS_BATCH(batch); } static const int va_to_gen7_jpeg_hufftable[2] = { MFX_HUFFTABLE_ID_Y, MFX_HUFFTABLE_ID_UV }; static void gen75_mfd_jpeg_huff_table_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context, int num_tables) { VAHuffmanTableBufferJPEGBaseline *huffman_table; struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int index; if (!decode_state->huffman_table || !decode_state->huffman_table->buffer) return; huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer; for (index = 0; index < num_tables; index++) { int id = va_to_gen7_jpeg_hufftable[index]; if (!huffman_table->load_huffman_table[index]) continue; BEGIN_BCS_BATCH(batch, 53); OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2)); OUT_BCS_BATCH(batch, id); intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12); intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12); intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16); intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164); ADVANCE_BCS_BATCH(batch); } } static const int va_to_gen7_jpeg_qm[5] = { -1, MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX, MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX, MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX, MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX }; static void gen75_mfd_jpeg_qm_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAPictureParameterBufferJPEGBaseline *pic_param; VAIQMatrixBufferJPEGBaseline *iq_matrix; int index; if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer) return; iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer; pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer; assert(pic_param->num_components <= 3); for (index = 0; index < pic_param->num_components; index++) { int id = pic_param->components[index].component_id - pic_param->components[0].component_id + 1; int qm_type; unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector]; unsigned char raster_qm[64]; int j; if (id > 4 || id < 1) continue; if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector]) continue; qm_type = va_to_gen7_jpeg_qm[id]; for (j = 0; j < 64; j++) raster_qm[zigzag_direct[j]] = qm[j]; gen75_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context); } } static void gen75_mfd_jpeg_bsd_object(VADriverContextP ctx, VAPictureParameterBufferJPEGBaseline *pic_param, VASliceParameterBufferJPEGBaseline *slice_param, VASliceParameterBufferJPEGBaseline *next_slice_param, dri_bo *slice_data_bo, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int scan_component_mask = 0; int i; assert(slice_param->num_components > 0); assert(slice_param->num_components < 4); assert(slice_param->num_components <= pic_param->num_components); for (i = 0; i < slice_param->num_components; i++) { switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) { case 1: scan_component_mask |= (1 << 0); break; case 2: scan_component_mask |= (1 << 1); break; case 3: scan_component_mask |= (1 << 2); break; default: assert(0); break; } } BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2)); OUT_BCS_BATCH(batch, slice_param->slice_data_size); OUT_BCS_BATCH(batch, slice_param->slice_data_offset); OUT_BCS_BATCH(batch, slice_param->slice_horizontal_position << 16 | slice_param->slice_vertical_position << 0); OUT_BCS_BATCH(batch, ((slice_param->num_components != 1) << 30) | /* interleaved */ (scan_component_mask << 27) | /* scan components */ (0 << 26) | /* disable interrupt allowed */ (slice_param->num_mcus << 0)); /* MCU count */ OUT_BCS_BATCH(batch, (slice_param->restart_interval << 0)); /* RestartInterval */ ADVANCE_BCS_BATCH(batch); } /* Workaround for JPEG decoding on Ivybridge */ VAStatus i965_DestroySurfaces(VADriverContextP ctx, VASurfaceID *surface_list, int num_surfaces); VAStatus i965_CreateSurfaces(VADriverContextP ctx, int width, int height, int format, int num_surfaces, VASurfaceID *surfaces); static struct { int width; int height; unsigned char data[32]; int data_size; int data_bit_offset; int qp; } gen7_jpeg_wa_clip = { 16, 16, { 0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c, 0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00 }, 14, 40, 28, }; static void gen75_jpeg_wa_init(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAStatus status; struct object_surface *obj_surface; if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE) i965_DestroySurfaces(ctx, &gen7_mfd_context->jpeg_wa_surface_id, 1); status = i965_CreateSurfaces(ctx, gen7_jpeg_wa_clip.width, gen7_jpeg_wa_clip.height, VA_RT_FORMAT_YUV420, 1, &gen7_mfd_context->jpeg_wa_surface_id); assert(status == VA_STATUS_SUCCESS); obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id); assert(obj_surface); i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420); gen7_mfd_context->jpeg_wa_surface_object = obj_surface; if (!gen7_mfd_context->jpeg_wa_slice_data_bo) { gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr, "JPEG WA data", 0x1000, 0x1000); dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo, 0, gen7_jpeg_wa_clip.data_size, gen7_jpeg_wa_clip.data); } } static void gen75_jpeg_wa_pipe_mode_select(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2)); OUT_BCS_BATCH(batch, (MFX_LONG_MODE << 17) | /* Currently only support long format */ (MFD_MODE_VLD << 15) | /* VLD mode */ (0 << 10) | /* disable Stream-Out */ (0 << 9) | /* Post Deblocking Output */ (1 << 8) | /* Pre Deblocking Output */ (0 << 5) | /* not in stitch mode */ (MFX_CODEC_DECODE << 4) | /* decoding mode */ (MFX_FORMAT_AVC << 0)); OUT_BCS_BATCH(batch, (0 << 4) | /* terminate if AVC motion and POC table error occurs */ (0 << 3) | /* terminate if AVC mbdata error occurs */ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ (0 << 1) | (0 << 0)); OUT_BCS_BATCH(batch, 0); /* pic status/error report id */ OUT_BCS_BATCH(batch, 0); /* reserved */ ADVANCE_BCS_BATCH(batch); } static void gen75_jpeg_wa_surface_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object; struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, ((obj_surface->orig_width - 1) << 18) | ((obj_surface->orig_height - 1) << 4)); OUT_BCS_BATCH(batch, (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ (1 << 27) | /* interleave chroma, set to 0 for JPEG */ (0 << 22) | /* surface object control state, ignored */ ((obj_surface->width - 1) << 3) | /* pitch */ (0 << 2) | /* must be 0 */ (1 << 1) | /* must be tiled */ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */ OUT_BCS_BATCH(batch, (0 << 16) | /* X offset for U(Cb), must be 0 */ (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */ OUT_BCS_BATCH(batch, (0 << 16) | /* X offset for V(Cr), must be 0 */ (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */ ADVANCE_BCS_BATCH(batch); } static void gen75_jpeg_wa_pipe_buf_addr_state_bplus(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object; struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; dri_bo *intra_bo; int i; intra_bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", 128 * 64, 0x1000); BEGIN_BCS_BATCH(batch, 61); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2)); OUT_BCS_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* post deblocking */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* uncompressed-video & stream out 7-12 */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW 13-15 is for intra row store scratch */ OUT_BCS_RELOC(batch, intra_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW 16-18 is for deblocking filter */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* DW 19..50 */ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); /* the DW52-54 is for mb status address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW56-60 is for ILDB & second ILDB address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); dri_bo_unreference(intra_bo); } static void gen75_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object; struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; dri_bo *intra_bo; int i; if (IS_STEPPING_BPLUS(i965)) { gen75_jpeg_wa_pipe_buf_addr_state_bplus(ctx, gen7_mfd_context); return; } intra_bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", 128 * 64, 0x1000); BEGIN_BCS_BATCH(batch, 25); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2)); OUT_BCS_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); /* post deblocking */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_RELOC(batch, intra_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); /* DW 7..22 */ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); dri_bo_unreference(intra_bo); } static void gen75_jpeg_wa_bsp_buf_base_addr_state_bplus(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; dri_bo *bsd_mpc_bo, *mpr_bo; bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", 11520, /* 1.5 * 120 * 64 */ 0x1000); mpr_bo = dri_bo_alloc(i965->intel.bufmgr, "mpr row store", 7680, /* 1. 0 * 120 * 64 */ 0x1000); BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2)); OUT_BCS_RELOC(batch, bsd_mpc_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_RELOC(batch, mpr_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); dri_bo_unreference(bsd_mpc_bo); dri_bo_unreference(mpr_bo); } static void gen75_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; dri_bo *bsd_mpc_bo, *mpr_bo; if (IS_STEPPING_BPLUS(i965)) { gen75_jpeg_wa_bsp_buf_base_addr_state_bplus(ctx, gen7_mfd_context); return; } bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", 11520, /* 1.5 * 120 * 64 */ 0x1000); mpr_bo = dri_bo_alloc(i965->intel.bufmgr, "mpr row store", 7680, /* 1. 0 * 120 * 64 */ 0x1000); BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2)); OUT_BCS_RELOC(batch, bsd_mpc_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_RELOC(batch, mpr_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); dri_bo_unreference(bsd_mpc_bo); dri_bo_unreference(mpr_bo); } static void gen75_jpeg_wa_avc_qm_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { } static void gen75_jpeg_wa_avc_img_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int img_struct = 0; int mbaff_frame_flag = 0; unsigned int width_in_mbs = 1, height_in_mbs = 1; BEGIN_BCS_BATCH(batch, 16); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2)); OUT_BCS_BATCH(batch, (width_in_mbs * height_in_mbs - 1)); OUT_BCS_BATCH(batch, ((height_in_mbs - 1) << 16) | ((width_in_mbs - 1) << 0)); OUT_BCS_BATCH(batch, (0 << 24) | (0 << 16) | (0 << 14) | (0 << 13) | (0 << 12) | /* differ from GEN6 */ (0 << 10) | (img_struct << 8)); OUT_BCS_BATCH(batch, (1 << 10) | /* 4:2:0 */ (1 << 7) | /* CABAC */ (0 << 6) | (0 << 5) | (0 << 4) | (0 << 3) | (1 << 2) | (mbaff_frame_flag << 1) | (0 << 0)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_jpeg_wa_avc_directmode_state_bplus(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int i; BEGIN_BCS_BATCH(batch, 71); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2)); /* reference surfaces 0..15 */ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { OUT_BCS_BATCH(batch, 0); /* top */ OUT_BCS_BATCH(batch, 0); /* bottom */ } OUT_BCS_BATCH(batch, 0); /* the current decoding frame/field */ OUT_BCS_BATCH(batch, 0); /* top */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* POC List */ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_jpeg_wa_avc_directmode_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int i; if (IS_STEPPING_BPLUS(i965)) { gen75_jpeg_wa_avc_directmode_state_bplus(ctx, gen7_mfd_context); return; } BEGIN_BCS_BATCH(batch, 69); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2)); /* reference surfaces 0..15 */ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { OUT_BCS_BATCH(batch, 0); /* top */ OUT_BCS_BATCH(batch, 0); /* bottom */ } /* the current decoding frame/field */ OUT_BCS_BATCH(batch, 0); /* top */ OUT_BCS_BATCH(batch, 0); /* bottom */ /* POC List */ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_jpeg_wa_ind_obj_base_addr_state_bplus(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); OUT_BCS_RELOC(batch, gen7_mfd_context->jpeg_wa_slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; if (IS_STEPPING_BPLUS(i965)) { gen75_jpeg_wa_ind_obj_base_addr_state_bplus(ctx, gen7_mfd_context); return; } BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); OUT_BCS_RELOC(batch, gen7_mfd_context->jpeg_wa_slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_jpeg_wa_avc_bsd_object(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; /* the input bitsteam format on GEN7 differs from GEN6 */ BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2)); OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, (0 << 31) | (0 << 14) | (0 << 12) | (0 << 10) | (0 << 8)); OUT_BCS_BATCH(batch, ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) | (0 << 5) | (0 << 4) | (1 << 3) | /* LastSlice Flag */ (gen7_jpeg_wa_clip.data_bit_offset & 0x7)); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_jpeg_wa_avc_slice_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1; int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0; int first_mb_in_slice = 0; int slice_type = SLICE_TYPE_I; BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2)); OUT_BCS_BATCH(batch, slice_type); OUT_BCS_BATCH(batch, (num_ref_idx_l1 << 24) | (num_ref_idx_l0 << 16) | (0 << 8) | (0 << 0)); OUT_BCS_BATCH(batch, (0 << 29) | (1 << 27) | /* disable Deblocking */ (0 << 24) | (gen7_jpeg_wa_clip.qp << 16) | (0 << 8) | (0 << 0)); OUT_BCS_BATCH(batch, (slice_ver_pos << 24) | (slice_hor_pos << 16) | (first_mb_in_slice << 0)); OUT_BCS_BATCH(batch, (next_slice_ver_pos << 16) | (next_slice_hor_pos << 0)); OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen75_mfd_jpeg_wa(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; gen75_jpeg_wa_init(ctx, gen7_mfd_context); intel_batchbuffer_emit_mi_flush(batch); gen75_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context); gen75_jpeg_wa_surface_state(ctx, gen7_mfd_context); gen75_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context); gen75_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context); gen75_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context); gen75_jpeg_wa_avc_img_state(ctx, gen7_mfd_context); gen75_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context); gen75_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context); gen75_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context); gen75_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context); } void gen75_mfd_jpeg_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferJPEGBaseline *pic_param; VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j, max_selector = 0; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer; /* Currently only support Baseline DCT */ gen75_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); gen75_mfd_jpeg_wa(ctx, gen7_mfd_context); intel_batchbuffer_emit_mi_flush(batch); gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context); gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context); gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context); gen75_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context); gen75_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { int component; assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; for (component = 0; component < slice_param->num_components; component++) { if (max_selector < slice_param->components[component].dc_table_selector) max_selector = slice_param->components[component].dc_table_selector; if (max_selector < slice_param->components[component].ac_table_selector) max_selector = slice_param->components[component].ac_table_selector; } slice_param++; } } assert(max_selector < 2); gen75_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen75_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static VAStatus gen75_mfd_decode_picture(VADriverContextP ctx, VAProfile profile, union codec_state *codec_state, struct hw_context *hw_context) { struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context; struct decode_state *decode_state = &codec_state->decode; VAStatus vaStatus; assert(gen7_mfd_context); vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state); if (vaStatus != VA_STATUS_SUCCESS) goto out; gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1; switch (profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: gen75_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context); break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: gen75_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context); break; case VAProfileVC1Simple: case VAProfileVC1Main: case VAProfileVC1Advanced: gen75_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context); break; case VAProfileJPEGBaseline: gen75_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context); break; default: assert(0); break; } vaStatus = VA_STATUS_SUCCESS; out: return vaStatus; } static void gen75_mfd_context_destroy(void *hw_context) { struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context; dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.bo = NULL; dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = NULL; dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo); gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo); gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo); gen7_mfd_context->bitplane_read_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo); intel_batchbuffer_free(gen7_mfd_context->base.batch); free(gen7_mfd_context); } static void gen75_mfd_mpeg2_context_init(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1; gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1; gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1; gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1; } struct hw_context * gen75_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config) { struct intel_driver_data *intel = intel_driver_data(ctx); struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context)); int i; gen7_mfd_context->base.destroy = gen75_mfd_context_destroy; gen7_mfd_context->base.run = gen75_mfd_decode_picture; gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0); for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID; gen7_mfd_context->reference_surface[i].frame_store_id = -1; gen7_mfd_context->reference_surface[i].obj_surface = NULL; } gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE; gen7_mfd_context->jpeg_wa_surface_object = NULL; switch (obj_config->profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: gen75_mfd_mpeg2_context_init(ctx, gen7_mfd_context); break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: gen75_mfd_avc_context_init(ctx, gen7_mfd_context); break; default: break; } return (struct hw_context *)gen7_mfd_context; } intel-driver-1.3.0/src/gen75_picture_process.c000066400000000000000000000230721231401140700212650ustar00rootroot00000000000000/* * Copyright © 2011 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Li Xiaowei */ #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_structs.h" #include "i965_drv_video.h" #include "i965_post_processing.h" #include "gen75_picture_process.h" extern void i965_proc_picture(VADriverContextP ctx, VAProfile profile, union codec_state *codec_state, struct hw_context *hw_context); extern struct hw_context * i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config); static VAStatus gen75_vpp_fmt_cvt(VADriverContextP ctx, VAProfile profile, union codec_state *codec_state, struct hw_context *hw_context) { VAStatus va_status = VA_STATUS_SUCCESS; struct intel_video_process_context *proc_ctx = (struct intel_video_process_context *)hw_context; /* implicity surface format coversion and scaling */ if(proc_ctx->vpp_fmt_cvt_ctx == NULL){ proc_ctx->vpp_fmt_cvt_ctx = i965_proc_context_init(ctx, NULL); } i965_proc_picture(ctx, profile, codec_state, proc_ctx->vpp_fmt_cvt_ctx); return va_status; } static VAStatus gen75_vpp_vebox(VADriverContextP ctx, struct intel_video_process_context* proc_ctx) { VAStatus va_status = VA_STATUS_SUCCESS; VAProcPipelineParameterBuffer* pipeline_param = proc_ctx->pipeline_param; struct i965_driver_data *i965 = i965_driver_data(ctx); /* vpp features based on VEBox fixed function */ if(proc_ctx->vpp_vebox_ctx == NULL) { proc_ctx->vpp_vebox_ctx = gen75_vebox_context_init(ctx); } proc_ctx->vpp_vebox_ctx->pipeline_param = pipeline_param; proc_ctx->vpp_vebox_ctx->surface_input_object = proc_ctx->surface_pipeline_input_object; proc_ctx->vpp_vebox_ctx->surface_output_object = proc_ctx->surface_render_output_object; if (IS_HASWELL(i965->intel.device_id)) va_status = gen75_vebox_process_picture(ctx, proc_ctx->vpp_vebox_ctx); else if (IS_GEN8(i965->intel.device_id)) va_status = gen8_vebox_process_picture(ctx, proc_ctx->vpp_vebox_ctx); return va_status; } static VAStatus gen75_vpp_gpe(VADriverContextP ctx, struct intel_video_process_context* proc_ctx) { VAStatus va_status = VA_STATUS_SUCCESS; if(proc_ctx->vpp_gpe_ctx == NULL){ proc_ctx->vpp_gpe_ctx = vpp_gpe_context_init(ctx); } proc_ctx->vpp_gpe_ctx->pipeline_param = proc_ctx->pipeline_param; proc_ctx->vpp_gpe_ctx->surface_pipeline_input_object = proc_ctx->surface_pipeline_input_object; proc_ctx->vpp_gpe_ctx->surface_output_object = proc_ctx->surface_render_output_object; va_status = vpp_gpe_process_picture(ctx, proc_ctx->vpp_gpe_ctx); return va_status; } VAStatus gen75_proc_picture(VADriverContextP ctx, VAProfile profile, union codec_state *codec_state, struct hw_context *hw_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct proc_state* proc_st = &(codec_state->proc); struct intel_video_process_context *proc_ctx = (struct intel_video_process_context *)hw_context; VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_st->pipeline_param->buffer; struct object_surface *obj_dst_surf = NULL; struct object_surface *obj_src_surf = NULL; VAStatus status; proc_ctx->pipeline_param = pipeline_param; if (proc_st->current_render_target == VA_INVALID_SURFACE || pipeline_param->surface == VA_INVALID_SURFACE) { status = VA_STATUS_ERROR_INVALID_SURFACE; goto error; } obj_dst_surf = SURFACE(proc_st->current_render_target); if (!obj_dst_surf) { status = VA_STATUS_ERROR_INVALID_SURFACE; goto error; } obj_src_surf = SURFACE(proc_ctx->pipeline_param->surface); if (!obj_src_surf) { status = VA_STATUS_ERROR_INVALID_SURFACE; goto error; } if (!obj_src_surf->bo) { status = VA_STATUS_ERROR_INVALID_VALUE; /* The input surface is created without valid content */ goto error; } if (pipeline_param->num_filters && !pipeline_param->filters) { status = VA_STATUS_ERROR_INVALID_PARAMETER; goto error; } if (!obj_dst_surf->bo) { unsigned int is_tiled = 0; unsigned int fourcc = VA_FOURCC('N','V','1','2'); int sampling = SUBSAMPLE_YUV420; i965_check_alloc_surface_bo(ctx, obj_dst_surf, is_tiled, fourcc, sampling); } proc_ctx->surface_render_output_object = obj_dst_surf; proc_ctx->surface_pipeline_input_object = obj_src_surf; assert(pipeline_param->num_filters <= 4); VABufferID *filter_id = (VABufferID*) pipeline_param->filters; if(pipeline_param->num_filters == 0 || pipeline_param->filters == NULL ){ /* implicity surface format coversion and scaling */ gen75_vpp_fmt_cvt(ctx, profile, codec_state, hw_context); }else if(pipeline_param->num_filters == 1) { struct object_buffer * obj_buf = BUFFER((*filter_id) + 0); assert(obj_buf && obj_buf->buffer_store && obj_buf->buffer_store->buffer); if (!obj_buf || !obj_buf->buffer_store || !obj_buf->buffer_store->buffer) { status = VA_STATUS_ERROR_INVALID_FILTER_CHAIN; goto error; } VAProcFilterParameterBuffer* filter = (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer; if (filter->type == VAProcFilterNoiseReduction || filter->type == VAProcFilterDeinterlacing || filter->type == VAProcFilterColorBalance){ gen75_vpp_vebox(ctx, proc_ctx); }else if(filter->type == VAProcFilterSharpening){ if (obj_src_surf->fourcc != VA_FOURCC('N', 'V', '1', '2') || obj_dst_surf->fourcc != VA_FOURCC('N', 'V', '1', '2')) { status = VA_STATUS_ERROR_UNIMPLEMENTED; goto error; } gen75_vpp_gpe(ctx, proc_ctx); } }else if (pipeline_param->num_filters >= 2) { unsigned int i = 0; for (i = 0; i < pipeline_param->num_filters; i++){ struct object_buffer * obj_buf = BUFFER(pipeline_param->filters[i]); if (!obj_buf || !obj_buf->buffer_store || !obj_buf->buffer_store->buffer) { status = VA_STATUS_ERROR_INVALID_FILTER_CHAIN; goto error; } VAProcFilterParameterBuffer* filter = (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer; if (filter->type != VAProcFilterNoiseReduction && filter->type != VAProcFilterDeinterlacing && filter->type != VAProcFilterColorBalance) { printf("Do not support multiply filters outside vebox pipeline \n"); assert(0); } } gen75_vpp_vebox(ctx, proc_ctx); } return VA_STATUS_SUCCESS; error: return status; } static void gen75_proc_context_destroy(void *hw_context) { struct intel_video_process_context *proc_ctx = (struct intel_video_process_context *)hw_context; VADriverContextP ctx = (VADriverContextP)(proc_ctx->driver_context); if(proc_ctx->vpp_fmt_cvt_ctx){ proc_ctx->vpp_fmt_cvt_ctx->destroy(proc_ctx->vpp_fmt_cvt_ctx); proc_ctx->vpp_fmt_cvt_ctx = NULL; } if(proc_ctx->vpp_vebox_ctx){ gen75_vebox_context_destroy(ctx,proc_ctx->vpp_vebox_ctx); proc_ctx->vpp_vebox_ctx = NULL; } if(proc_ctx->vpp_gpe_ctx){ vpp_gpe_context_destroy(ctx,proc_ctx->vpp_gpe_ctx); proc_ctx->vpp_gpe_ctx = NULL; } free(proc_ctx); } struct hw_context * gen75_proc_context_init(VADriverContextP ctx, struct object_config *obj_config) { struct intel_video_process_context *proc_context = calloc(1, sizeof(struct intel_video_process_context)); proc_context->base.destroy = gen75_proc_context_destroy; proc_context->base.run = gen75_proc_picture; proc_context->vpp_vebox_ctx = NULL; proc_context->vpp_gpe_ctx = NULL; proc_context->vpp_fmt_cvt_ctx = NULL; proc_context->driver_context = ctx; return (struct hw_context *)proc_context; } intel-driver-1.3.0/src/gen75_picture_process.h000066400000000000000000000035751231401140700213000ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Li Xiaowei * */ #ifndef _GEN75_PICTURE_PROCESS_H #define _GEN75_PICTURE_PROCESS_H #include #include "i965_drv_video.h" #include "gen75_vpp_vebox.h" #include "gen75_vpp_gpe.h" struct intel_video_process_context { struct hw_context base; void* driver_context; struct intel_vebox_context *vpp_vebox_ctx; struct hw_context *vpp_fmt_cvt_ctx; struct vpp_gpe_context *vpp_gpe_ctx; VAProcPipelineParameterBuffer* pipeline_param; struct object_surface *surface_render_output_object; struct object_surface *surface_pipeline_input_object; }; struct hw_context * gen75_proc_context_init(VADriverContextP ctx, struct object_config *obj_config); #endif intel-driver-1.3.0/src/gen75_vme.c000066400000000000000000001212151231401140700166410ustar00rootroot00000000000000/* * Copyright © 2010-2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Zhao Yakui * Xiang Haihao * */ #include "sysdeps.h" #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_encoder.h" #include "gen6_vme.h" #include "gen6_mfc.h" #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7) #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index) #define VME_INTRA_SHADER 0 #define VME_INTER_SHADER 1 #define VME_BINTER_SHADER 3 #define VME_BATCHBUFFER 2 #define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */ #define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */ #define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */ #define VME_MSG_LENGTH 32 static const uint32_t gen75_vme_intra_frame[][4] = { #include "shaders/vme/intra_frame_haswell.g75b" }; static const uint32_t gen75_vme_inter_frame[][4] = { #include "shaders/vme/inter_frame_haswell.g75b" }; static const uint32_t gen75_vme_inter_bframe[][4] = { #include "shaders/vme/inter_bframe_haswell.g75b" }; static const uint32_t gen75_vme_batchbuffer[][4] = { #include "shaders/vme/batchbuffer.g75b" }; static struct i965_kernel gen75_vme_kernels[] = { { "VME Intra Frame", VME_INTRA_SHADER, /*index*/ gen75_vme_intra_frame, sizeof(gen75_vme_intra_frame), NULL }, { "VME inter Frame", VME_INTER_SHADER, gen75_vme_inter_frame, sizeof(gen75_vme_inter_frame), NULL }, { "VME BATCHBUFFER", VME_BATCHBUFFER, gen75_vme_batchbuffer, sizeof(gen75_vme_batchbuffer), NULL }, { "VME inter BFrame", VME_BINTER_SHADER, gen75_vme_inter_bframe, sizeof(gen75_vme_inter_bframe), NULL } }; static const uint32_t gen75_vme_mpeg2_intra_frame[][4] = { #include "shaders/vme/intra_frame_haswell.g75b" }; static const uint32_t gen75_vme_mpeg2_inter_frame[][4] = { #include "shaders/vme/mpeg2_inter_haswell.g75b" }; static const uint32_t gen75_vme_mpeg2_batchbuffer[][4] = { #include "shaders/vme/batchbuffer.g75b" }; static struct i965_kernel gen75_vme_mpeg2_kernels[] = { { "VME Intra Frame", VME_INTRA_SHADER, /*index*/ gen75_vme_mpeg2_intra_frame, sizeof(gen75_vme_mpeg2_intra_frame), NULL }, { "VME inter Frame", VME_INTER_SHADER, gen75_vme_mpeg2_inter_frame, sizeof(gen75_vme_mpeg2_inter_frame), NULL }, { "VME BATCHBUFFER", VME_BATCHBUFFER, gen75_vme_mpeg2_batchbuffer, sizeof(gen75_vme_mpeg2_batchbuffer), NULL }, }; /* only used for VME source surface state */ static void gen75_vme_source_surface_state(VADriverContextP ctx, int index, struct object_surface *obj_surface, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; vme_context->vme_surface2_setup(ctx, &vme_context->gpe_context, obj_surface, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen75_vme_media_source_surface_state(VADriverContextP ctx, int index, struct object_surface *obj_surface, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; vme_context->vme_media_rw_surface_setup(ctx, &vme_context->gpe_context, obj_surface, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen75_vme_media_chroma_source_surface_state(VADriverContextP ctx, int index, struct object_surface *obj_surface, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; vme_context->vme_media_chroma_surface_setup(ctx, &vme_context->gpe_context, obj_surface, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen75_vme_output_buffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs; vme_context->vme_output.pitch = 16; /* in bytes, always 16 */ if (is_intra) vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2; else vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24; /* * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref * + 16 FBR Info + 128 FBR MV + 32 FBR Ref. * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24. */ vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr, "VME output buffer", vme_context->vme_output.num_blocks * vme_context->vme_output.size_block, 0x1000); assert(vme_context->vme_output.bo); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_output, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen75_vme_output_vme_batchbuffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1; vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */ vme_context->vme_batchbuffer.pitch = 16; vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr, "VME batchbuffer", vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block, 0x1000); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_batchbuffer, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static VAStatus gen75_vme_surface_setup(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct object_surface *obj_surface; /*Setup surfaces state*/ /* current picture for encoding */ obj_surface = encode_state->input_yuv_object; gen75_vme_source_surface_state(ctx, 0, obj_surface, encoder_context); gen75_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context); gen75_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context); if (!is_intra) { VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int slice_type; slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI); intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 0, 1, gen75_vme_source_surface_state); if (slice_type == SLICE_TYPE_B) intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 1, 2, gen75_vme_source_surface_state); } /* VME output */ gen75_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context); gen75_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context); return VA_STATUS_SUCCESS; } static VAStatus gen75_vme_interface_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct gen6_interface_descriptor_data *desc; int i; dri_bo *bo; bo = vme_context->gpe_context.idrt.bo; dri_bo_map(bo, 1); assert(bo->virtual); desc = bo->virtual; for (i = 0; i < vme_context->vme_kernel_sum; i++) { struct i965_kernel *kernel; kernel = &vme_context->gpe_context.kernels[i]; assert(sizeof(*desc) == 32); /*Setup the descritor table*/ memset(desc, 0, sizeof(*desc)); desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6); desc->desc2.sampler_count = 0; /* FIXME: */ desc->desc2.sampler_state_pointer = 0; desc->desc3.binding_table_entry_count = 1; /* FIXME: */ desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5); desc->desc4.constant_urb_entry_read_offset = 0; desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH; /*kernel start*/ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0), kernel->bo); desc++; } dri_bo_unmap(bo); return VA_STATUS_SUCCESS; } static VAStatus gen75_vme_constant_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; unsigned char *constant_buffer; unsigned int *vme_state_message; int mv_num = 32; vme_state_message = (unsigned int *)vme_context->vme_state_message; if (encoder_context->codec == CODEC_H264) { if (vme_context->h264_level >= 30) { mv_num = 16; if (vme_context->h264_level >= 31) mv_num = 8; } } else if (encoder_context->codec == CODEC_MPEG2) { mv_num = 2; } vme_state_message[31] = mv_num; dri_bo_map(vme_context->gpe_context.curbe.bo, 1); assert(vme_context->gpe_context.curbe.bo->virtual); constant_buffer = vme_context->gpe_context.curbe.bo->virtual; /* VME MV/Mb cost table is passed by using const buffer */ /* Now it uses the fixed search path. So it is constructed directly * in the GPU shader. */ memcpy(constant_buffer, (char *)vme_context->vme_state_message, 128); dri_bo_unmap(vme_context->gpe_context.curbe.bo); return VA_STATUS_SUCCESS; } static const unsigned int intra_mb_mode_cost_table[] = { 0x31110001, // for qp0 0x09110001, // for qp1 0x15030001, // for qp2 0x0b030001, // for qp3 0x0d030011, // for qp4 0x17210011, // for qp5 0x41210011, // for qp6 0x19210011, // for qp7 0x25050003, // for qp8 0x1b130003, // for qp9 0x1d130003, // for qp10 0x27070021, // for qp11 0x51310021, // for qp12 0x29090021, // for qp13 0x35150005, // for qp14 0x2b0b0013, // for qp15 0x2d0d0013, // for qp16 0x37170007, // for qp17 0x61410031, // for qp18 0x39190009, // for qp19 0x45250015, // for qp20 0x3b1b000b, // for qp21 0x3d1d000d, // for qp22 0x47270017, // for qp23 0x71510041, // for qp24 ! center for qp=0..30 0x49290019, // for qp25 0x55350025, // for qp26 0x4b2b001b, // for qp27 0x4d2d001d, // for qp28 0x57370027, // for qp29 0x81610051, // for qp30 0x57270017, // for qp31 0x81510041, // for qp32 ! center for qp=31..51 0x59290019, // for qp33 0x65350025, // for qp34 0x5b2b001b, // for qp35 0x5d2d001d, // for qp36 0x67370027, // for qp37 0x91610051, // for qp38 0x69390029, // for qp39 0x75450035, // for qp40 0x6b3b002b, // for qp41 0x6d3d002d, // for qp42 0x77470037, // for qp43 0xa1710061, // for qp44 0x79490039, // for qp45 0x85550045, // for qp46 0x7b4b003b, // for qp47 0x7d4d003d, // for qp48 0x87570047, // for qp49 0xb1810071, // for qp50 0x89590049 // for qp51 }; static void gen75_vme_state_setup_fixup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, unsigned int *vme_state_message) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; if (slice_param->slice_type != SLICE_TYPE_I && slice_param->slice_type != SLICE_TYPE_SI) return; if (encoder_context->rate_control_mode == VA_RC_CQP) vme_state_message[0] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta]; else vme_state_message[0] = intra_mb_mode_cost_table[mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY]; } static VAStatus gen75_vme_vme_state_setup(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; unsigned int *vme_state_message; int i; //pass the MV/Mb cost into VME message on HASWell assert(vme_context->vme_state_message); vme_state_message = (unsigned int *)vme_context->vme_state_message; vme_state_message[0] = 0x4a4a4a4a; vme_state_message[1] = 0x4a4a4a4a; vme_state_message[2] = 0x4a4a4a4a; vme_state_message[3] = 0x22120200; vme_state_message[4] = 0x62524232; for (i=5; i < 8; i++) { vme_state_message[i] = 0; } switch (encoder_context->codec) { case CODEC_H264: gen75_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message); break; default: /* no fixup */ break; } return VA_STATUS_SUCCESS; } static void gen75_vme_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, int transform_8x8_mode_flag, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int mb_x = 0, mb_y = 0; int i, s; unsigned int *command_ptr; dri_bo_map(vme_context->vme_batchbuffer.bo, 1); command_ptr = vme_context->vme_batchbuffer.bo->virtual; for (s = 0; s < encode_state->num_slice_params_ext; s++) { VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer; int slice_mb_begin = pSliceParameter->macroblock_address; int slice_mb_number = pSliceParameter->num_macroblocks; unsigned int mb_intra_ub; int slice_mb_x = pSliceParameter->macroblock_address % mb_width; for (i = 0; i < slice_mb_number; ) { int mb_count = i + slice_mb_begin; mb_x = mb_count % mb_width; mb_y = mb_count / mb_width; mb_intra_ub = 0; if (mb_x != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; } if (mb_y != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; if (mb_x != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (mb_x != (mb_width -1)) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; } if (i < mb_width) { if (i == 0) mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE); mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK); if ((i == (mb_width - 1)) && slice_mb_x) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; } } if ((i == mb_width) && slice_mb_x) { mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D); } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; /*inline data */ *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x); *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8)); i += 1; } } *command_ptr++ = 0; *command_ptr++ = MI_BATCH_BUFFER_END; dri_bo_unmap(vme_context->vme_batchbuffer.bo); } static void gen75_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; i965_gpe_context_init(ctx, &vme_context->gpe_context); /* VME output buffer */ dri_bo_unreference(vme_context->vme_output.bo); vme_context->vme_output.bo = NULL; dri_bo_unreference(vme_context->vme_batchbuffer.bo); vme_context->vme_batchbuffer.bo = NULL; /* VME state */ dri_bo_unreference(vme_context->vme_state.bo); vme_context->vme_state.bo = NULL; } static void gen75_vme_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct intel_batchbuffer *batch = encoder_context->base.batch; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; int kernel_shader; bool allow_hwscore = true; int s; for (s = 0; s < encode_state->num_slice_params_ext; s++) { pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer; if ((pSliceParameter->macroblock_address % width_in_mbs)) { allow_hwscore = false; break; } } if ((pSliceParameter->slice_type == SLICE_TYPE_I) || (pSliceParameter->slice_type == SLICE_TYPE_I)) { kernel_shader = VME_INTRA_SHADER; } else if ((pSliceParameter->slice_type == SLICE_TYPE_P) || (pSliceParameter->slice_type == SLICE_TYPE_SP)) { kernel_shader = VME_INTER_SHADER; } else { kernel_shader = VME_BINTER_SHADER; if (!allow_hwscore) kernel_shader = VME_INTER_SHADER; } if (allow_hwscore) gen7_vme_walker_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, kernel_shader, pPicParameter->pic_fields.bits.transform_8x8_mode_flag, encoder_context); else gen75_vme_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, kernel_shader, pPicParameter->pic_fields.bits.transform_8x8_mode_flag, encoder_context); intel_batchbuffer_start_atomic(batch, 0x1000); gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8)); OUT_RELOC(batch, vme_context->vme_batchbuffer.bo, I915_GEM_DOMAIN_COMMAND, 0, 0); ADVANCE_BATCH(batch); intel_batchbuffer_end_atomic(batch); } static VAStatus gen75_vme_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { VAStatus vaStatus = VA_STATUS_SUCCESS; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; struct gen6_vme_context *vme_context = encoder_context->vme_context; if (!vme_context->h264_level || (vme_context->h264_level != pSequenceParameter->level_idc)) { vme_context->h264_level = pSequenceParameter->level_idc; } intel_vme_update_mbmv_cost(ctx, encode_state, encoder_context); /*Setup all the memory object*/ gen75_vme_surface_setup(ctx, encode_state, is_intra, encoder_context); gen75_vme_interface_setup(ctx, encode_state, encoder_context); //gen75_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context); gen75_vme_constant_setup(ctx, encode_state, encoder_context); /*Programing media pipeline*/ gen75_vme_pipeline_programing(ctx, encode_state, encoder_context); return vaStatus; } static VAStatus gen75_vme_run(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; intel_batchbuffer_flush(batch); return VA_STATUS_SUCCESS; } static VAStatus gen75_vme_stop(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { return VA_STATUS_SUCCESS; } static VAStatus gen75_vme_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen75_vme_media_init(ctx, encoder_context); gen75_vme_prepare(ctx, encode_state, encoder_context); gen75_vme_run(ctx, encode_state, encoder_context); gen75_vme_stop(ctx, encode_state, encoder_context); return VA_STATUS_SUCCESS; } static void gen75_vme_mpeg2_output_buffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, int is_intra, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs; vme_context->vme_output.pitch = 16; /* in bytes, always 16 */ if (is_intra) vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2; else vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24; /* * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref * + 16 FBR Info + 128 FBR MV + 32 FBR Ref. * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24. */ vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr, "VME output buffer", vme_context->vme_output.num_blocks * vme_context->vme_output.size_block, 0x1000); assert(vme_context->vme_output.bo); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_output, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen75_vme_mpeg2_output_vme_batchbuffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1; vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */ vme_context->vme_batchbuffer.pitch = 16; vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr, "VME batchbuffer", vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block, 0x1000); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_batchbuffer, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static VAStatus gen75_vme_mpeg2_surface_setup(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct object_surface *obj_surface; /*Setup surfaces state*/ /* current picture for encoding */ obj_surface = encode_state->input_yuv_object; gen75_vme_source_surface_state(ctx, 0, obj_surface, encoder_context); gen75_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context); gen75_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context); if (!is_intra) { /* reference 0 */ obj_surface = encode_state->reference_objects[0]; if (obj_surface->bo != NULL) gen75_vme_source_surface_state(ctx, 1, obj_surface, encoder_context); /* reference 1 */ obj_surface = encode_state->reference_objects[1]; if (obj_surface && obj_surface->bo != NULL) gen75_vme_source_surface_state(ctx, 2, obj_surface, encoder_context); } /* VME output */ gen75_vme_mpeg2_output_buffer_setup(ctx, encode_state, 3, is_intra, encoder_context); gen75_vme_mpeg2_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context); return VA_STATUS_SUCCESS; } static void gen75_vme_mpeg2_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, int transform_8x8_mode_flag, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int mb_x = 0, mb_y = 0; int i, s, j; unsigned int *command_ptr; dri_bo_map(vme_context->vme_batchbuffer.bo, 1); command_ptr = vme_context->vme_batchbuffer.bo->virtual; for (s = 0; s < encode_state->num_slice_params_ext; s++) { VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer; for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) { int slice_mb_begin = slice_param->macroblock_address; int slice_mb_number = slice_param->num_macroblocks; unsigned int mb_intra_ub; int slice_mb_x = slice_param->macroblock_address % mb_width; for (i = 0; i < slice_mb_number;) { int mb_count = i + slice_mb_begin; mb_x = mb_count % mb_width; mb_y = mb_count / mb_width; mb_intra_ub = 0; if (mb_x != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; } if (mb_y != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; if (mb_x != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (mb_x != (mb_width -1)) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; } if (i < mb_width) { if (i == 0) mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE); mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK); if ((i == (mb_width - 1)) && slice_mb_x) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; } } if ((i == mb_width) && slice_mb_x) { mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D); } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; /*inline data */ *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x); *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8)); i += 1; } slice_param++; } } *command_ptr++ = 0; *command_ptr++ = MI_BATCH_BUFFER_END; dri_bo_unmap(vme_context->vme_batchbuffer.bo); } static void gen75_vme_mpeg2_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct intel_batchbuffer *batch = encoder_context->base.batch; VAEncPictureParameterBufferMPEG2 *pic_param = NULL; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; bool allow_hwscore = true; int s; int kernel_shader; pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; for (s = 0; s < encode_state->num_slice_params_ext; s++) { int j; VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer; for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) { if (slice_param->macroblock_address % width_in_mbs) { allow_hwscore = false; break; } } } pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; if (pic_param->picture_type == VAEncPictureTypeIntra) { allow_hwscore = false; kernel_shader = VME_INTRA_SHADER; } else { kernel_shader = VME_INTER_SHADER; } if (allow_hwscore) gen7_vme_mpeg2_walker_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, kernel_shader, encoder_context); else gen75_vme_mpeg2_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, kernel_shader, 0, encoder_context); intel_batchbuffer_start_atomic(batch, 0x1000); gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8)); OUT_RELOC(batch, vme_context->vme_batchbuffer.bo, I915_GEM_DOMAIN_COMMAND, 0, 0); ADVANCE_BATCH(batch); intel_batchbuffer_end_atomic(batch); } static VAStatus gen75_vme_mpeg2_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { VAStatus vaStatus = VA_STATUS_SUCCESS; VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; struct gen6_vme_context *vme_context = encoder_context->vme_context; if ((!vme_context->mpeg2_level) || (vme_context->mpeg2_level != (seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK))) { vme_context->mpeg2_level = seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK; } /*Setup all the memory object*/ gen75_vme_mpeg2_surface_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context); gen75_vme_interface_setup(ctx, encode_state, encoder_context); gen75_vme_vme_state_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context); intel_vme_mpeg2_state_setup(ctx, encode_state, encoder_context); gen75_vme_constant_setup(ctx, encode_state, encoder_context); /*Programing media pipeline*/ gen75_vme_mpeg2_pipeline_programing(ctx, encode_state, slice_param->is_intra_slice, encoder_context); return vaStatus; } static VAStatus gen75_vme_mpeg2_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen75_vme_media_init(ctx, encoder_context); gen75_vme_mpeg2_prepare(ctx, encode_state, encoder_context); gen75_vme_run(ctx, encode_state, encoder_context); gen75_vme_stop(ctx, encode_state, encoder_context); return VA_STATUS_SUCCESS; } static void gen75_vme_context_destroy(void *context) { struct gen6_vme_context *vme_context = context; i965_gpe_context_destroy(&vme_context->gpe_context); dri_bo_unreference(vme_context->vme_output.bo); vme_context->vme_output.bo = NULL; dri_bo_unreference(vme_context->vme_state.bo); vme_context->vme_state.bo = NULL; dri_bo_unreference(vme_context->vme_batchbuffer.bo); vme_context->vme_batchbuffer.bo = NULL; if (vme_context->vme_state_message) { free(vme_context->vme_state_message); vme_context->vme_state_message = NULL; } free(vme_context); } Bool gen75_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context)); struct i965_kernel *vme_kernel_list = NULL; int i965_kernel_num; switch (encoder_context->codec) { case CODEC_H264: vme_kernel_list = gen75_vme_kernels; encoder_context->vme_pipeline = gen75_vme_pipeline; i965_kernel_num = sizeof(gen75_vme_kernels) / sizeof(struct i965_kernel); break; case CODEC_MPEG2: vme_kernel_list = gen75_vme_mpeg2_kernels; encoder_context->vme_pipeline = gen75_vme_mpeg2_pipeline; i965_kernel_num = sizeof(gen75_vme_mpeg2_kernels) / sizeof(struct i965_kernel); break; default: /* never get here */ assert(0); break; } vme_context->vme_kernel_sum = i965_kernel_num; vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6; vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data); vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH; vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1; vme_context->gpe_context.vfe_state.num_urb_entries = 64; vme_context->gpe_context.vfe_state.gpgpu_mode = 0; vme_context->gpe_context.vfe_state.urb_entry_size = 16; vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1; gen7_vme_scoreboard_init(ctx, vme_context); i965_gpe_load_kernels(ctx, &vme_context->gpe_context, vme_kernel_list, i965_kernel_num); vme_context->vme_surface2_setup = gen7_gpe_surface2_setup; vme_context->vme_media_rw_surface_setup = gen7_gpe_media_rw_surface_setup; vme_context->vme_buffer_suface_setup = gen7_gpe_buffer_suface_setup; vme_context->vme_media_chroma_surface_setup = gen75_gpe_media_chroma_surface_setup; encoder_context->vme_context = vme_context; encoder_context->vme_context_destroy = gen75_vme_context_destroy; vme_context->vme_state_message = malloc(VME_MSG_LENGTH * sizeof(int)); return True; } intel-driver-1.3.0/src/gen75_vpp_gpe.c000066400000000000000000001006061231401140700175130ustar00rootroot00000000000000/* * Copyright © 2011 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Li Xiaowei */ #include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_structs.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "gen75_vpp_gpe.h" #define MAX_INTERFACE_DESC_GEN6 MAX_GPE_KERNELS #define MAX_MEDIA_SURFACES_GEN6 34 #define SURFACE_STATE_OFFSET_GEN7(index) (SURFACE_STATE_PADDED_SIZE_GEN7 * (index)) #define BINDING_TABLE_OFFSET_GEN7(index) (SURFACE_STATE_OFFSET_GEN7(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * (index)) #define SURFACE_STATE_OFFSET_GEN8(index) (SURFACE_STATE_PADDED_SIZE_GEN8 * (index)) #define BINDING_TABLE_OFFSET_GEN8(index) (SURFACE_STATE_OFFSET_GEN8(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * (index)) #define CURBE_ALLOCATION_SIZE 37 #define CURBE_TOTAL_DATA_LENGTH (4 * 32) #define CURBE_URB_ENTRY_LENGTH 4 extern VAStatus i965_CreateSurfaces(VADriverContextP ctx, int width, int height, int format, int num_surfaces, VASurfaceID *surfaces); extern VAStatus i965_DestroySurfaces(VADriverContextP ctx, VASurfaceID *surface_list, int num_surfaces); /* Shaders information for sharpening */ static const unsigned int gen75_gpe_sharpening_h_blur[][4] = { #include "shaders/post_processing/gen75/sharpening_h_blur.g75b" }; static const unsigned int gen75_gpe_sharpening_v_blur[][4] = { #include "shaders/post_processing/gen75/sharpening_v_blur.g75b" }; static const unsigned int gen75_gpe_sharpening_unmask[][4] = { #include "shaders/post_processing/gen75/sharpening_unmask.g75b" }; static struct i965_kernel gen75_vpp_sharpening_kernels[] = { { "vpp: sharpening(horizontal blur)", VPP_GPE_SHARPENING, gen75_gpe_sharpening_h_blur, sizeof(gen75_gpe_sharpening_h_blur), NULL }, { "vpp: sharpening(vertical blur)", VPP_GPE_SHARPENING, gen75_gpe_sharpening_v_blur, sizeof(gen75_gpe_sharpening_v_blur), NULL }, { "vpp: sharpening(unmask)", VPP_GPE_SHARPENING, gen75_gpe_sharpening_unmask, sizeof(gen75_gpe_sharpening_unmask), NULL }, }; /* sharpening kernels for Broadwell */ static const unsigned int gen8_gpe_sharpening_h_blur[][4] = { #include "shaders/post_processing/gen8/sharpening_h_blur.g8b" }; static const unsigned int gen8_gpe_sharpening_v_blur[][4] = { #include "shaders/post_processing/gen8/sharpening_v_blur.g8b" }; static const unsigned int gen8_gpe_sharpening_unmask[][4] = { #include "shaders/post_processing/gen8/sharpening_unmask.g8b" }; static struct i965_kernel gen8_vpp_sharpening_kernels[] = { { "vpp: sharpening(horizontal blur)", VPP_GPE_SHARPENING, gen8_gpe_sharpening_h_blur, sizeof(gen8_gpe_sharpening_h_blur), NULL }, { "vpp: sharpening(vertical blur)", VPP_GPE_SHARPENING, gen8_gpe_sharpening_v_blur, sizeof(gen8_gpe_sharpening_v_blur), NULL }, { "vpp: sharpening(unmask)", VPP_GPE_SHARPENING, gen8_gpe_sharpening_unmask, sizeof(gen8_gpe_sharpening_unmask), NULL }, }; static VAStatus gen75_gpe_process_surfaces_setup(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { struct object_surface *obj_surface; unsigned int i = 0; unsigned char input_surface_sum = (1 + vpp_gpe_ctx->forward_surf_sum + vpp_gpe_ctx->backward_surf_sum) * 2; /* Binding input NV12 surfaces (Luma + Chroma)*/ for( i = 0; i < input_surface_sum; i += 2){ obj_surface = vpp_gpe_ctx->surface_input_object[i/2]; assert(obj_surface); gen7_gpe_media_rw_surface_setup(ctx, &vpp_gpe_ctx->gpe_ctx, obj_surface, BINDING_TABLE_OFFSET_GEN7(i), SURFACE_STATE_OFFSET_GEN7(i)); gen75_gpe_media_chroma_surface_setup(ctx, &vpp_gpe_ctx->gpe_ctx, obj_surface, BINDING_TABLE_OFFSET_GEN7(i + 1), SURFACE_STATE_OFFSET_GEN7(i + 1)); } /* Binding output NV12 surface(Luma + Chroma) */ obj_surface = vpp_gpe_ctx->surface_output_object; assert(obj_surface); gen7_gpe_media_rw_surface_setup(ctx, &vpp_gpe_ctx->gpe_ctx, obj_surface, BINDING_TABLE_OFFSET_GEN7(input_surface_sum), SURFACE_STATE_OFFSET_GEN7(input_surface_sum)); gen75_gpe_media_chroma_surface_setup(ctx, &vpp_gpe_ctx->gpe_ctx, obj_surface, BINDING_TABLE_OFFSET_GEN7(input_surface_sum + 1), SURFACE_STATE_OFFSET_GEN7(input_surface_sum + 1)); /* Bind kernel return buffer surface */ gen7_gpe_buffer_suface_setup(ctx, &vpp_gpe_ctx->gpe_ctx, &vpp_gpe_ctx->vpp_kernel_return, BINDING_TABLE_OFFSET_GEN7((input_surface_sum + 2)), SURFACE_STATE_OFFSET_GEN7(input_surface_sum + 2)); return VA_STATUS_SUCCESS; } static VAStatus gen75_gpe_process_interface_setup(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { struct gen6_interface_descriptor_data *desc; dri_bo *bo = vpp_gpe_ctx->gpe_ctx.idrt.bo; int i; dri_bo_map(bo, 1); assert(bo->virtual); desc = bo->virtual; /*Setup the descritor table*/ for(i = 0; i < vpp_gpe_ctx->sub_shader_sum; i++){ struct i965_kernel *kernel = &vpp_gpe_ctx->gpe_ctx.kernels[i]; assert(sizeof(*desc) == 32); memset(desc, 0, sizeof(*desc)); desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6); desc->desc2.sampler_count = 0; /* FIXME: */ desc->desc2.sampler_state_pointer = 0; desc->desc3.binding_table_entry_count = 6; /* FIXME: */ desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET_GEN7(0) >> 5); desc->desc4.constant_urb_entry_read_offset = 0; desc->desc4.constant_urb_entry_read_length = 0; dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, i* sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0), kernel->bo); desc++; } dri_bo_unmap(bo); return VA_STATUS_SUCCESS; } static VAStatus gen75_gpe_process_constant_fill(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { dri_bo_map(vpp_gpe_ctx->gpe_ctx.curbe.bo, 1); assert(vpp_gpe_ctx->gpe_ctx.curbe.bo->virtual); unsigned char* constant_buffer = vpp_gpe_ctx->gpe_ctx.curbe.bo->virtual; memcpy(constant_buffer, vpp_gpe_ctx->kernel_param, vpp_gpe_ctx->kernel_param_size); dri_bo_unmap(vpp_gpe_ctx->gpe_ctx.curbe.bo); return VA_STATUS_SUCCESS; } static VAStatus gen75_gpe_process_parameters_fill(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { unsigned int *command_ptr; unsigned int i, size = vpp_gpe_ctx->thread_param_size; unsigned char* position = NULL; /* Thread inline data setting*/ dri_bo_map(vpp_gpe_ctx->vpp_batchbuffer.bo, 1); command_ptr = vpp_gpe_ctx->vpp_batchbuffer.bo->virtual; for(i = 0; i < vpp_gpe_ctx->thread_num; i ++) { *command_ptr++ = (CMD_MEDIA_OBJECT | (size/sizeof(int) + 6 - 2)); *command_ptr++ = vpp_gpe_ctx->sub_shader_index; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; /* copy thread inline data */ position =(unsigned char*)(vpp_gpe_ctx->thread_param + size * i); memcpy(command_ptr, position, size); command_ptr += size/sizeof(int); } *command_ptr++ = 0; *command_ptr++ = MI_BATCH_BUFFER_END; dri_bo_unmap(vpp_gpe_ctx->vpp_batchbuffer.bo); return VA_STATUS_SUCCESS; } static VAStatus gen75_gpe_process_pipeline_setup(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { intel_batchbuffer_start_atomic(vpp_gpe_ctx->batch, 0x1000); intel_batchbuffer_emit_mi_flush(vpp_gpe_ctx->batch); gen6_gpe_pipeline_setup(ctx, &vpp_gpe_ctx->gpe_ctx, vpp_gpe_ctx->batch); gen75_gpe_process_parameters_fill(ctx, vpp_gpe_ctx); BEGIN_BATCH(vpp_gpe_ctx->batch, 2); OUT_BATCH(vpp_gpe_ctx->batch, MI_BATCH_BUFFER_START | (1 << 8)); OUT_RELOC(vpp_gpe_ctx->batch, vpp_gpe_ctx->vpp_batchbuffer.bo, I915_GEM_DOMAIN_COMMAND, 0, 0); ADVANCE_BATCH(vpp_gpe_ctx->batch); intel_batchbuffer_end_atomic(vpp_gpe_ctx->batch); return VA_STATUS_SUCCESS; } static VAStatus gen75_gpe_process_init(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); dri_bo *bo; unsigned int batch_buf_size = vpp_gpe_ctx->thread_num * (vpp_gpe_ctx->thread_param_size + 6 * sizeof(int)) + 16; vpp_gpe_ctx->vpp_kernel_return.num_blocks = vpp_gpe_ctx->thread_num; vpp_gpe_ctx->vpp_kernel_return.size_block = 16; vpp_gpe_ctx->vpp_kernel_return.pitch = 1; unsigned int kernel_return_size = vpp_gpe_ctx->vpp_kernel_return.num_blocks * vpp_gpe_ctx->vpp_kernel_return.size_block; dri_bo_unreference(vpp_gpe_ctx->vpp_batchbuffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vpp batch buffer", batch_buf_size, 0x1000); vpp_gpe_ctx->vpp_batchbuffer.bo = bo; dri_bo_reference(vpp_gpe_ctx->vpp_batchbuffer.bo); dri_bo_unreference(vpp_gpe_ctx->vpp_kernel_return.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vpp kernel return buffer", kernel_return_size, 0x1000); vpp_gpe_ctx->vpp_kernel_return.bo = bo; dri_bo_reference(vpp_gpe_ctx->vpp_kernel_return.bo); vpp_gpe_ctx->gpe_context_init(ctx, &vpp_gpe_ctx->gpe_ctx); return VA_STATUS_SUCCESS; } static VAStatus gen75_gpe_process_prepare(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { /*Setup all the memory object*/ gen75_gpe_process_surfaces_setup(ctx, vpp_gpe_ctx); gen75_gpe_process_interface_setup(ctx, vpp_gpe_ctx); //gen75_gpe_process_constant_setup(ctx, vpp_gpe_ctx); /*Programing media pipeline*/ gen75_gpe_process_pipeline_setup(ctx, vpp_gpe_ctx); return VA_STATUS_SUCCESS; } static VAStatus gen75_gpe_process_run(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { intel_batchbuffer_flush(vpp_gpe_ctx->batch); return VA_STATUS_SUCCESS; } static VAStatus gen75_gpe_process(VADriverContextP ctx, struct vpp_gpe_context * vpp_gpe_ctx) { VAStatus va_status = VA_STATUS_SUCCESS; va_status = gen75_gpe_process_init(ctx, vpp_gpe_ctx); if (va_status != VA_STATUS_SUCCESS) return va_status; va_status = gen75_gpe_process_prepare(ctx, vpp_gpe_ctx); if (va_status != VA_STATUS_SUCCESS) return va_status; va_status = gen75_gpe_process_run(ctx, vpp_gpe_ctx); if (va_status != VA_STATUS_SUCCESS) return va_status; return VA_STATUS_SUCCESS; } static VAStatus gen8_gpe_process_surfaces_setup(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { struct object_surface *obj_surface; unsigned int i = 0; unsigned char input_surface_sum = (1 + vpp_gpe_ctx->forward_surf_sum + vpp_gpe_ctx->backward_surf_sum) * 2; /* Binding input NV12 surfaces (Luma + Chroma)*/ for( i = 0; i < input_surface_sum; i += 2){ obj_surface = vpp_gpe_ctx->surface_input_object[i/2]; assert(obj_surface); gen8_gpe_media_rw_surface_setup(ctx, &vpp_gpe_ctx->gpe_ctx, obj_surface, BINDING_TABLE_OFFSET_GEN8(i), SURFACE_STATE_OFFSET_GEN8(i)); gen8_gpe_media_chroma_surface_setup(ctx, &vpp_gpe_ctx->gpe_ctx, obj_surface, BINDING_TABLE_OFFSET_GEN8(i + 1), SURFACE_STATE_OFFSET_GEN8(i + 1)); } /* Binding output NV12 surface(Luma + Chroma) */ obj_surface = vpp_gpe_ctx->surface_output_object; assert(obj_surface); gen8_gpe_media_rw_surface_setup(ctx, &vpp_gpe_ctx->gpe_ctx, obj_surface, BINDING_TABLE_OFFSET_GEN8(input_surface_sum), SURFACE_STATE_OFFSET_GEN8(input_surface_sum)); gen8_gpe_media_chroma_surface_setup(ctx, &vpp_gpe_ctx->gpe_ctx, obj_surface, BINDING_TABLE_OFFSET_GEN8(input_surface_sum + 1), SURFACE_STATE_OFFSET_GEN8(input_surface_sum + 1)); /* Bind kernel return buffer surface */ gen7_gpe_buffer_suface_setup(ctx, &vpp_gpe_ctx->gpe_ctx, &vpp_gpe_ctx->vpp_kernel_return, BINDING_TABLE_OFFSET_GEN8((input_surface_sum + 2)), SURFACE_STATE_OFFSET_GEN8(input_surface_sum + 2)); return VA_STATUS_SUCCESS; } static VAStatus gen8_gpe_process_interface_setup(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { struct gen8_interface_descriptor_data *desc; dri_bo *bo = vpp_gpe_ctx->gpe_ctx.dynamic_state.bo; int i; dri_bo_map(bo, 1); assert(bo->virtual); desc = (struct gen8_interface_descriptor_data *)(bo->virtual + vpp_gpe_ctx->gpe_ctx.idrt_offset); /*Setup the descritor table*/ for (i = 0; i < vpp_gpe_ctx->sub_shader_sum; i++){ struct i965_kernel *kernel; kernel = &vpp_gpe_ctx->gpe_ctx.kernels[i]; assert(sizeof(*desc) == 32); /*Setup the descritor table*/ memset(desc, 0, sizeof(*desc)); desc->desc0.kernel_start_pointer = kernel->kernel_offset >> 6; desc->desc3.sampler_count = 0; /* FIXME: */ desc->desc3.sampler_state_pointer = 0; desc->desc4.binding_table_entry_count = 6; /* FIXME: */ desc->desc4.binding_table_pointer = (BINDING_TABLE_OFFSET_GEN8(0) >> 5); desc->desc5.constant_urb_entry_read_offset = 0; desc->desc5.constant_urb_entry_read_length = 0; desc++; } dri_bo_unmap(bo); return VA_STATUS_SUCCESS; } static VAStatus gen8_gpe_process_constant_fill(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { dri_bo_map(vpp_gpe_ctx->gpe_ctx.dynamic_state.bo, 1); assert(vpp_gpe_ctx->gpe_ctx.dynamic_state.bo->virtual); unsigned char* constant_buffer = vpp_gpe_ctx->gpe_ctx.dynamic_state.bo->virtual; memcpy(constant_buffer, vpp_gpe_ctx->kernel_param, vpp_gpe_ctx->kernel_param_size); dri_bo_unmap(vpp_gpe_ctx->gpe_ctx.dynamic_state.bo); return VA_STATUS_SUCCESS; } static VAStatus gen8_gpe_process_parameters_fill(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { unsigned int *command_ptr; unsigned int i, size = vpp_gpe_ctx->thread_param_size; unsigned char* position = NULL; /* Thread inline data setting*/ dri_bo_map(vpp_gpe_ctx->vpp_batchbuffer.bo, 1); command_ptr = vpp_gpe_ctx->vpp_batchbuffer.bo->virtual; for(i = 0; i < vpp_gpe_ctx->thread_num; i ++) { *command_ptr++ = (CMD_MEDIA_OBJECT | (size/sizeof(int) + 6 - 2)); *command_ptr++ = vpp_gpe_ctx->sub_shader_index; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; /* copy thread inline data */ position =(unsigned char*)(vpp_gpe_ctx->thread_param + size * i); memcpy(command_ptr, position, size); command_ptr += size/sizeof(int); *command_ptr++ = CMD_MEDIA_STATE_FLUSH; *command_ptr++ = 0; } *command_ptr++ = 0; *command_ptr++ = MI_BATCH_BUFFER_END; dri_bo_unmap(vpp_gpe_ctx->vpp_batchbuffer.bo); return VA_STATUS_SUCCESS; } static VAStatus gen8_gpe_process_pipeline_setup(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { intel_batchbuffer_start_atomic(vpp_gpe_ctx->batch, 0x1000); intel_batchbuffer_emit_mi_flush(vpp_gpe_ctx->batch); gen8_gpe_pipeline_setup(ctx, &vpp_gpe_ctx->gpe_ctx, vpp_gpe_ctx->batch); gen8_gpe_process_parameters_fill(ctx, vpp_gpe_ctx); BEGIN_BATCH(vpp_gpe_ctx->batch, 3); OUT_BATCH(vpp_gpe_ctx->batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0)); OUT_RELOC(vpp_gpe_ctx->batch, vpp_gpe_ctx->vpp_batchbuffer.bo, I915_GEM_DOMAIN_COMMAND, 0, 0); OUT_BATCH(vpp_gpe_ctx->batch, 0); ADVANCE_BATCH(vpp_gpe_ctx->batch); intel_batchbuffer_end_atomic(vpp_gpe_ctx->batch); return VA_STATUS_SUCCESS; } static VAStatus gen8_gpe_process_init(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); dri_bo *bo; unsigned int batch_buf_size = vpp_gpe_ctx->thread_num * (vpp_gpe_ctx->thread_param_size + 6 * sizeof(int)) + 16; vpp_gpe_ctx->vpp_kernel_return.num_blocks = vpp_gpe_ctx->thread_num; vpp_gpe_ctx->vpp_kernel_return.size_block = 16; vpp_gpe_ctx->vpp_kernel_return.pitch = 1; unsigned int kernel_return_size = vpp_gpe_ctx->vpp_kernel_return.num_blocks * vpp_gpe_ctx->vpp_kernel_return.size_block; dri_bo_unreference(vpp_gpe_ctx->vpp_batchbuffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vpp batch buffer", batch_buf_size, 0x1000); vpp_gpe_ctx->vpp_batchbuffer.bo = bo; dri_bo_reference(vpp_gpe_ctx->vpp_batchbuffer.bo); dri_bo_unreference(vpp_gpe_ctx->vpp_kernel_return.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vpp kernel return buffer", kernel_return_size, 0x1000); vpp_gpe_ctx->vpp_kernel_return.bo = bo; dri_bo_reference(vpp_gpe_ctx->vpp_kernel_return.bo); vpp_gpe_ctx->gpe_context_init(ctx, &vpp_gpe_ctx->gpe_ctx); return VA_STATUS_SUCCESS; } static VAStatus gen8_gpe_process_prepare(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { /*Setup all the memory object*/ gen8_gpe_process_surfaces_setup(ctx, vpp_gpe_ctx); gen8_gpe_process_interface_setup(ctx, vpp_gpe_ctx); //gen8_gpe_process_constant_setup(ctx, vpp_gpe_ctx); /*Programing media pipeline*/ gen8_gpe_process_pipeline_setup(ctx, vpp_gpe_ctx); return VA_STATUS_SUCCESS; } static VAStatus gen8_gpe_process_run(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { intel_batchbuffer_flush(vpp_gpe_ctx->batch); return VA_STATUS_SUCCESS; } static VAStatus gen8_gpe_process(VADriverContextP ctx, struct vpp_gpe_context * vpp_gpe_ctx) { VAStatus va_status = VA_STATUS_SUCCESS; va_status = gen8_gpe_process_init(ctx, vpp_gpe_ctx); if (va_status != VA_STATUS_SUCCESS) return va_status; va_status = gen8_gpe_process_prepare(ctx, vpp_gpe_ctx); if (va_status != VA_STATUS_SUCCESS) return va_status; va_status = gen8_gpe_process_run(ctx, vpp_gpe_ctx); if (va_status != VA_STATUS_SUCCESS) return va_status; return VA_STATUS_SUCCESS; } static VAStatus vpp_gpe_process(VADriverContextP ctx, struct vpp_gpe_context * vpp_gpe_ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); if (IS_HASWELL(i965->intel.device_id)) return gen75_gpe_process(ctx, vpp_gpe_ctx); else if (IS_GEN8(i965->intel.device_id)) return gen8_gpe_process(ctx, vpp_gpe_ctx); return VA_STATUS_ERROR_UNIMPLEMENTED; } static VAStatus vpp_gpe_process_sharpening(VADriverContextP ctx, struct vpp_gpe_context * vpp_gpe_ctx) { VAStatus va_status = VA_STATUS_SUCCESS; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *origin_in_obj_surface = vpp_gpe_ctx->surface_input_object[0]; struct object_surface *origin_out_obj_surface = vpp_gpe_ctx->surface_output_object; VAProcPipelineParameterBuffer* pipe = vpp_gpe_ctx->pipeline_param; VABufferID *filter_ids = (VABufferID*)pipe->filters ; struct object_buffer *obj_buf = BUFFER((*(filter_ids + 0))); assert(obj_buf && obj_buf->buffer_store && obj_buf->buffer_store->buffer); if (!obj_buf || !obj_buf->buffer_store || !obj_buf->buffer_store->buffer) goto error; VAProcFilterParameterBuffer* filter = (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer; float sharpening_intensity = filter->value; ThreadParameterSharpening thr_param; unsigned int thr_param_size = sizeof(ThreadParameterSharpening); unsigned int i; unsigned char * pos; if(vpp_gpe_ctx->is_first_frame){ vpp_gpe_ctx->sub_shader_sum = 3; struct i965_kernel * vpp_kernels; if (IS_HASWELL(i965->intel.device_id)) vpp_kernels = gen75_vpp_sharpening_kernels; else if (IS_GEN8(i965->intel.device_id)) vpp_kernels = gen8_vpp_sharpening_kernels; vpp_gpe_ctx->gpe_load_kernels(ctx, &vpp_gpe_ctx->gpe_ctx, vpp_kernels, vpp_gpe_ctx->sub_shader_sum); } if(vpp_gpe_ctx->surface_tmp == VA_INVALID_ID){ va_status = i965_CreateSurfaces(ctx, vpp_gpe_ctx->in_frame_w, vpp_gpe_ctx->in_frame_h, VA_RT_FORMAT_YUV420, 1, &vpp_gpe_ctx->surface_tmp); assert(va_status == VA_STATUS_SUCCESS); struct object_surface * obj_surf = SURFACE(vpp_gpe_ctx->surface_tmp); assert(obj_surf); if (obj_surf) { i965_check_alloc_surface_bo(ctx, obj_surf, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); vpp_gpe_ctx->surface_tmp_object = obj_surf; } } assert(sharpening_intensity >= 0.0 && sharpening_intensity <= 1.0); thr_param.l_amount = (unsigned int)(sharpening_intensity * 128); thr_param.d_amount = (unsigned int)(sharpening_intensity * 128); thr_param.base.pic_width = vpp_gpe_ctx->in_frame_w; thr_param.base.pic_height = vpp_gpe_ctx->in_frame_h; /* Step 1: horizontal blur process */ vpp_gpe_ctx->forward_surf_sum = 0; vpp_gpe_ctx->backward_surf_sum = 0; vpp_gpe_ctx->thread_num = vpp_gpe_ctx->in_frame_h/16; vpp_gpe_ctx->thread_param_size = thr_param_size; vpp_gpe_ctx->thread_param = (unsigned char*) malloc(vpp_gpe_ctx->thread_param_size *vpp_gpe_ctx->thread_num); pos = vpp_gpe_ctx->thread_param; if (!pos) { return VA_STATUS_ERROR_ALLOCATION_FAILED; } for( i = 0 ; i < vpp_gpe_ctx->thread_num; i++){ thr_param.base.v_pos = 16 * i; thr_param.base.h_pos = 0; memcpy(pos, &thr_param, thr_param_size); pos += thr_param_size; } vpp_gpe_ctx->sub_shader_index = 0; va_status = vpp_gpe_process(ctx, vpp_gpe_ctx); free(vpp_gpe_ctx->thread_param); /* Step 2: vertical blur process */ vpp_gpe_ctx->surface_input_object[0] = vpp_gpe_ctx->surface_output_object; vpp_gpe_ctx->surface_output_object = vpp_gpe_ctx->surface_tmp_object; vpp_gpe_ctx->forward_surf_sum = 0; vpp_gpe_ctx->backward_surf_sum = 0; vpp_gpe_ctx->thread_num = vpp_gpe_ctx->in_frame_w/16; vpp_gpe_ctx->thread_param_size = thr_param_size; vpp_gpe_ctx->thread_param = (unsigned char*) malloc(vpp_gpe_ctx->thread_param_size *vpp_gpe_ctx->thread_num); pos = vpp_gpe_ctx->thread_param; if (!pos) { return VA_STATUS_ERROR_ALLOCATION_FAILED; } for( i = 0 ; i < vpp_gpe_ctx->thread_num; i++){ thr_param.base.v_pos = 0; thr_param.base.h_pos = 16 * i; memcpy(pos, &thr_param, thr_param_size); pos += thr_param_size; } vpp_gpe_ctx->sub_shader_index = 1; vpp_gpe_process(ctx, vpp_gpe_ctx); free(vpp_gpe_ctx->thread_param); /* Step 3: apply the blur to original surface */ vpp_gpe_ctx->surface_input_object[0] = origin_in_obj_surface; vpp_gpe_ctx->surface_input_object[1] = vpp_gpe_ctx->surface_tmp_object; vpp_gpe_ctx->surface_output_object = origin_out_obj_surface; vpp_gpe_ctx->forward_surf_sum = 1; vpp_gpe_ctx->backward_surf_sum = 0; vpp_gpe_ctx->thread_num = vpp_gpe_ctx->in_frame_h/4; vpp_gpe_ctx->thread_param_size = thr_param_size; vpp_gpe_ctx->thread_param = (unsigned char*) malloc(vpp_gpe_ctx->thread_param_size *vpp_gpe_ctx->thread_num); pos = vpp_gpe_ctx->thread_param; if (!pos) { return VA_STATUS_ERROR_ALLOCATION_FAILED; } for( i = 0 ; i < vpp_gpe_ctx->thread_num; i++){ thr_param.base.v_pos = 4 * i; thr_param.base.h_pos = 0; memcpy(pos, &thr_param, thr_param_size); pos += thr_param_size; } vpp_gpe_ctx->sub_shader_index = 2; va_status = vpp_gpe_process(ctx, vpp_gpe_ctx); free(vpp_gpe_ctx->thread_param); return va_status; error: return VA_STATUS_ERROR_INVALID_PARAMETER; } VAStatus vpp_gpe_process_picture(VADriverContextP ctx, struct vpp_gpe_context * vpp_gpe_ctx) { VAStatus va_status = VA_STATUS_SUCCESS; struct i965_driver_data *i965 = i965_driver_data(ctx); VAProcPipelineParameterBuffer* pipe = vpp_gpe_ctx->pipeline_param; VAProcFilterParameterBuffer* filter = NULL; unsigned int i; struct object_surface *obj_surface = NULL; if (pipe->num_filters && !pipe->filters) goto error; for(i = 0; i < pipe->num_filters; i++){ struct object_buffer *obj_buf = BUFFER(pipe->filters[i]); assert(obj_buf && obj_buf->buffer_store && obj_buf->buffer_store->buffer); if (!obj_buf || !obj_buf->buffer_store || !obj_buf->buffer_store->buffer) goto error; filter = (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer; if(filter->type == VAProcFilterSharpening){ break; } } assert(pipe->num_forward_references + pipe->num_backward_references <= 4); vpp_gpe_ctx->surface_input_object[0] = vpp_gpe_ctx->surface_pipeline_input_object; vpp_gpe_ctx->forward_surf_sum = 0; vpp_gpe_ctx->backward_surf_sum = 0; for(i = 0; i < pipe->num_forward_references; i ++) { obj_surface = SURFACE(pipe->forward_references[i]); assert(obj_surface); vpp_gpe_ctx->surface_input_object[i + 1] = obj_surface; vpp_gpe_ctx->forward_surf_sum++; } for(i = 0; i < pipe->num_backward_references; i ++) { obj_surface = SURFACE(pipe->backward_references[i]); assert(obj_surface); vpp_gpe_ctx->surface_input_object[vpp_gpe_ctx->forward_surf_sum + 1 + i ] = obj_surface; vpp_gpe_ctx->backward_surf_sum++; } obj_surface = vpp_gpe_ctx->surface_input_object[0]; vpp_gpe_ctx->in_frame_w = obj_surface->orig_width; vpp_gpe_ctx->in_frame_h = obj_surface->orig_height; if(filter && filter->type == VAProcFilterSharpening) { va_status = vpp_gpe_process_sharpening(ctx, vpp_gpe_ctx); } else { va_status = VA_STATUS_ERROR_ATTR_NOT_SUPPORTED; } vpp_gpe_ctx->is_first_frame = 0; return va_status; error: return VA_STATUS_ERROR_INVALID_PARAMETER; } void vpp_gpe_context_destroy(VADriverContextP ctx, struct vpp_gpe_context *vpp_gpe_ctx) { dri_bo_unreference(vpp_gpe_ctx->vpp_batchbuffer.bo); vpp_gpe_ctx->vpp_batchbuffer.bo = NULL; dri_bo_unreference(vpp_gpe_ctx->vpp_kernel_return.bo); vpp_gpe_ctx->vpp_kernel_return.bo = NULL; vpp_gpe_ctx->gpe_context_destroy(&vpp_gpe_ctx->gpe_ctx); if(vpp_gpe_ctx->surface_tmp != VA_INVALID_ID){ assert(vpp_gpe_ctx->surface_tmp_object != NULL); i965_DestroySurfaces(ctx, &vpp_gpe_ctx->surface_tmp, 1); vpp_gpe_ctx->surface_tmp = VA_INVALID_ID; vpp_gpe_ctx->surface_tmp_object = NULL; } free(vpp_gpe_ctx->batch); free(vpp_gpe_ctx); } struct vpp_gpe_context * vpp_gpe_context_init(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct vpp_gpe_context *vpp_gpe_ctx = calloc(1, sizeof(struct vpp_gpe_context)); struct i965_gpe_context *gpe_ctx = &(vpp_gpe_ctx->gpe_ctx); assert(IS_HASWELL(i965->intel.device_id) || IS_GEN8(i965->intel.device_id)); vpp_gpe_ctx->surface_tmp = VA_INVALID_ID; vpp_gpe_ctx->surface_tmp_object = NULL; vpp_gpe_ctx->batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_RENDER, 0); vpp_gpe_ctx->is_first_frame = 1; gpe_ctx->vfe_state.max_num_threads = 60 - 1; gpe_ctx->vfe_state.num_urb_entries = 16; gpe_ctx->vfe_state.gpgpu_mode = 0; gpe_ctx->vfe_state.urb_entry_size = 59 - 1; gpe_ctx->vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1; if (IS_HASWELL(i965->intel.device_id)) { vpp_gpe_ctx->gpe_context_init = i965_gpe_context_init; vpp_gpe_ctx->gpe_context_destroy = i965_gpe_context_destroy; vpp_gpe_ctx->gpe_load_kernels = i965_gpe_load_kernels; gpe_ctx->surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE_GEN7 + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; gpe_ctx->curbe.length = CURBE_TOTAL_DATA_LENGTH; gpe_ctx->idrt.max_entries = MAX_INTERFACE_DESC_GEN6; gpe_ctx->idrt.entry_size = sizeof(struct gen6_interface_descriptor_data); } else if (IS_GEN8(i965->intel.device_id)) { vpp_gpe_ctx->gpe_context_init = gen8_gpe_context_init; vpp_gpe_ctx->gpe_context_destroy = gen8_gpe_context_destroy; vpp_gpe_ctx->gpe_load_kernels = gen8_gpe_load_kernels; gpe_ctx->surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE_GEN8 + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; gpe_ctx->curbe_size = CURBE_TOTAL_DATA_LENGTH; gpe_ctx->idrt_size = sizeof(struct gen8_interface_descriptor_data) * MAX_INTERFACE_DESC_GEN6; } return vpp_gpe_ctx; } intel-driver-1.3.0/src/gen75_vpp_gpe.h000066400000000000000000000072561231401140700175270ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Li Xiaowei * */ #ifndef GEN75_VPP_GPE #define GEN75_VPP_GPE #include #include #include #include #include "i965_gpe_utils.h" #define MAX_SURF_IN_SUM 5 enum VPP_GPE_TYPE{ VPP_GPE_SHARPENING, VPP_GPE_BLENDING, VPP_GPE_SCENE_CHANGE_DETECTION, VPP_GPE_FILTER_SUM, }; typedef struct _KernelParameterBase{ unsigned short pic_width; unsigned short pic_height; }KernelParameterBase; typedef struct _KernelParameterSharpening{ KernelParameterBase base; }KernelParameterSharpening; typedef struct _ThreadParameterBase{ unsigned int pic_width; unsigned int pic_height; unsigned int v_pos; unsigned int h_pos; }ThreadParameterBase; typedef struct _ThreadParameterSharpenig{ ThreadParameterBase base; unsigned int l_amount; unsigned int d_amount; }ThreadParameterSharpening; struct vpp_gpe_context{ struct intel_batchbuffer *batch; struct i965_gpe_context gpe_ctx; struct i965_buffer_surface vpp_batchbuffer; struct i965_buffer_surface vpp_kernel_return; VAProcPipelineParameterBuffer *pipeline_param; enum VPP_GPE_TYPE filter_type; unsigned int sub_shader_index; unsigned int sub_shader_sum; unsigned char * kernel_param; unsigned int kernel_param_size; unsigned char * thread_param; unsigned int thread_param_size; unsigned int thread_num; struct object_surface *surface_pipeline_input_object; struct object_surface *surface_output_object; VASurfaceID surface_tmp; struct object_surface *surface_tmp_object; struct object_surface *surface_input_object[MAX_SURF_IN_SUM]; unsigned int forward_surf_sum; unsigned int backward_surf_sum; unsigned int in_frame_w; unsigned int in_frame_h; unsigned int is_first_frame; void (*gpe_context_init)(VADriverContextP ctx, struct i965_gpe_context *gpe_context); void (*gpe_context_destroy)(struct i965_gpe_context *gpe_context); void (*gpe_load_kernels)(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_kernel *kernel_list, unsigned int num_kernels); }; struct vpp_gpe_context * vpp_gpe_context_init(VADriverContextP ctx); void vpp_gpe_context_destroy(VADriverContextP ctx, struct vpp_gpe_context* vpp_context); VAStatus vpp_gpe_process_picture(VADriverContextP ctx, struct vpp_gpe_context * vpp_context); #endif intel-driver-1.3.0/src/gen75_vpp_vebox.c000066400000000000000000001676621231401140700201020ustar00rootroot00000000000000/* * Copyright © 2011 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Li Xiaowei * Li Zhong */ #include #include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_structs.h" #include "gen75_vpp_vebox.h" #include "intel_media.h" #define PI 3.1415926 extern VAStatus i965_MapBuffer(VADriverContextP ctx, VABufferID buf_id, void **); extern VAStatus i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id); extern VAStatus i965_DeriveImage(VADriverContextP ctx, VABufferID surface, VAImage *out_image); extern VAStatus i965_DestroyImage(VADriverContextP ctx, VAImageID image); extern VAStatus i965_DestroySurfaces(VADriverContextP ctx, VASurfaceID *surface_list, int num_surfaces); extern VAStatus i965_CreateSurfaces(VADriverContextP ctx, int width, int height, int format, int num_surfaces, VASurfaceID *surfaces); VAStatus vpp_surface_convert(VADriverContextP ctx, struct object_surface *src_obj_surf, struct object_surface *dst_obj_surf) { VAStatus va_status = VA_STATUS_SUCCESS; assert(src_obj_surf->orig_width == dst_obj_surf->orig_width); assert(src_obj_surf->orig_height == dst_obj_surf->orig_height); VARectangle src_rect, dst_rect; src_rect.x = dst_rect.x = 0; src_rect.y = dst_rect.y = 0; src_rect.width = dst_rect.width = src_obj_surf->orig_width; src_rect.height = dst_rect.height = dst_obj_surf->orig_height; struct i965_surface src_surface, dst_surface; src_surface.base = (struct object_base *)src_obj_surf; src_surface.type = I965_SURFACE_TYPE_SURFACE; src_surface.flags = I965_SURFACE_FLAG_FRAME; dst_surface.base = (struct object_base *)dst_obj_surf; dst_surface.type = I965_SURFACE_TYPE_SURFACE; dst_surface.flags = I965_SURFACE_FLAG_FRAME; va_status = i965_image_processing(ctx, &src_surface, &src_rect, &dst_surface, &dst_rect); return va_status; } VAStatus vpp_surface_scaling(VADriverContextP ctx, struct object_surface *dst_obj_surf, struct object_surface *src_obj_surf) { VAStatus va_status = VA_STATUS_SUCCESS; int flags = I965_PP_FLAG_AVS; assert(src_obj_surf->fourcc == VA_FOURCC('N','V','1','2')); assert(dst_obj_surf->fourcc == VA_FOURCC('N','V','1','2')); VARectangle src_rect, dst_rect; src_rect.x = 0; src_rect.y = 0; src_rect.width = src_obj_surf->orig_width; src_rect.height = src_obj_surf->orig_height; dst_rect.x = 0; dst_rect.y = 0; dst_rect.width = dst_obj_surf->orig_width; dst_rect.height = dst_obj_surf->orig_height; va_status = i965_scaling_processing(ctx, src_obj_surf, &src_rect, dst_obj_surf, &dst_rect, flags); return va_status; } void hsw_veb_dndi_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); unsigned int* p_table ; int progressive_dn = 1; int dndi_top_first = 0; int motion_compensated_enable = 0; if (proc_ctx->filters_mask & VPP_DNDI_DI) { VAProcFilterParameterBufferDeinterlacing *di_param = (VAProcFilterParameterBufferDeinterlacing *)proc_ctx->filter_di; assert(di_param); progressive_dn = 0; dndi_top_first = !(di_param->flags & VA_DEINTERLACING_BOTTOM_FIELD); motion_compensated_enable = (di_param->algorithm == VAProcDeinterlacingMotionCompensated); } /* VAProcFilterParameterBufferDeinterlacing *di_param = (VAProcFilterParameterBufferDeinterlacing *) proc_ctx->filter_di; VAProcFilterParameterBuffer * dn_param = (VAProcFilterParameterBuffer *) proc_ctx->filter_dn; */ p_table = (unsigned int *)proc_ctx->dndi_state_table.ptr; if (IS_HASWELL(i965->intel.device_id)) *p_table ++ = 0; // reserved . w0 *p_table ++ = ( 140 << 24 | // denoise STAD threshold . w1 192 << 16 | // dnmh_history_max 0 << 12 | // reserved 7 << 8 | // dnmh_delta[3:0] 38 ); // denoise ASD threshold *p_table ++ = ( 0 << 30 | // reserved . w2 0 << 24 | // temporal diff th 0 << 22 | // reserved. 0 << 16 | // low temporal diff th 2 << 13 | // STMM C2 1 << 8 | // denoise moving pixel th 38 ); // denoise th for sum of complexity measure *p_table ++ = ( 0 << 30 | // reserved . w3 12<< 24 | // good neighbor th[5:0] 9 << 20 | // CAT slope minus 1 5 << 16 | // SAD Tight in 0 << 14 | // smooth mv th 0 << 12 | // reserved 1 << 8 | // bne_edge_th[3:0] 20 ); // block noise estimate noise th *p_table ++ = ( 0 << 31 | // STMM blending constant select. w4 64 << 24 | // STMM trc1 125<< 16 | // STMM trc2 0 << 14 | // reserved 30 << 8 | // VECM_mul 150 ); // maximum STMM *p_table ++ = ( 118<< 24 | // minumum STMM . W5 0 << 22 | // STMM shift down 1 << 20 | // STMM shift up 5 << 16 | // STMM output shift 100 << 8 | // SDI threshold 5 ); // SDI delta *p_table ++ = ( 50 << 24 | // SDI fallback mode 1 T1 constant . W6 100 << 16 | // SDI fallback mode 1 T2 constant 37 << 8 | // SDI fallback mode 2 constant(angle2x1) 175 ); // FMD temporal difference threshold *p_table ++ = ( 16 << 24 | // FMD #1 vertical difference th . w7 100<< 16 | // FMD #2 vertical difference th 0 << 14 | // CAT th1 2 << 8 | // FMD tear threshold motion_compensated_enable << 7 | // MCDI Enable, use motion compensated deinterlace algorithm progressive_dn << 6 | // progressive DN 0 << 4 | // reserved dndi_top_first << 3 | // DN/DI Top First 0 ); // reserved *p_table ++ = ( 0 << 29 | // reserved . W8 32 << 23 | // dnmh_history_init[5:0] 10 << 19 | // neighborPixel th 0 << 18 | // reserved 0 << 16 | // FMD for 2nd field of previous frame 25 << 10 | // MC pixel consistency th 0 << 8 | // FMD for 1st field for current frame 10 << 4 | // SAD THB 5 ); // SAD THA *p_table ++ = ( 0 << 24 | // reserved 140<< 16 | // chr_dnmh_stad_th 0 << 13 | // reserved 1 << 12 | // chrome denoise enable 13 << 6 | // chr temp diff th 7 ); // chr temp diff low if (IS_GEN8(i965->intel.device_id)) *p_table ++ = 0; // parameters for hot pixel, } void hsw_veb_iecp_std_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { unsigned int *p_table = proc_ctx->iecp_state_table.ptr + 0 ; //VAProcFilterParameterBuffer * std_param = // (VAProcFilterParameterBuffer *) proc_ctx->filter_std; if(!(proc_ctx->filters_mask & VPP_IECP_STD_STE)){ memset(p_table, 0, 29 * 4); }else{ *p_table ++ = 0x9a6e39f0; *p_table ++ = 0x400c0000; *p_table ++ = 0x00001180; *p_table ++ = 0xfe2f2e00; *p_table ++ = 0x000000ff; *p_table ++ = 0x00140000; *p_table ++ = 0xd82e0000; *p_table ++ = 0x8285ecec; *p_table ++ = 0x00008282; *p_table ++ = 0x00000000; *p_table ++ = 0x02117000; *p_table ++ = 0xa38fec96; *p_table ++ = 0x0000c8c8; *p_table ++ = 0x00000000; *p_table ++ = 0x01478000; *p_table ++ = 0x0007c306; *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; *p_table ++ = 0x1c1bd000; *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; *p_table ++ = 0x0007cf80; *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; *p_table ++ = 0x1c080000; *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; } } void hsw_veb_iecp_ace_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { unsigned int *p_table = (unsigned int*)(proc_ctx->iecp_state_table.ptr + 116); if(!(proc_ctx->filters_mask & VPP_IECP_ACE)){ memset(p_table, 0, 13 * 4); }else{ *p_table ++ = 0x00000068; *p_table ++ = 0x4c382410; *p_table ++ = 0x9c887460; *p_table ++ = 0xebd8c4b0; *p_table ++ = 0x604c3824; *p_table ++ = 0xb09c8874; *p_table ++ = 0x0000d8c4; *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; } } void hsw_veb_iecp_tcc_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { unsigned int *p_table = (unsigned int*)(proc_ctx->iecp_state_table.ptr + 168); // VAProcFilterParameterBuffer * tcc_param = // (VAProcFilterParameterBuffer *) proc_ctx->filter_iecp_tcc; if(!(proc_ctx->filters_mask & VPP_IECP_TCC)){ memset(p_table, 0, 11 * 4); }else{ *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; *p_table ++ = 0x1e34cc91; *p_table ++ = 0x3e3cce91; *p_table ++ = 0x02e80195; *p_table ++ = 0x0197046b; *p_table ++ = 0x01790174; *p_table ++ = 0x00000000; *p_table ++ = 0x00000000; *p_table ++ = 0x03030000; *p_table ++ = 0x009201c0; } } void hsw_veb_iecp_pro_amp_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { unsigned int contrast = 0x80; //default int brightness = 0x00; //default int cos_c_s = 256 ; //default int sin_c_s = 0; //default unsigned int *p_table = (unsigned int*)(proc_ctx->iecp_state_table.ptr + 212); if(!(proc_ctx->filters_mask & VPP_IECP_PRO_AMP)){ memset(p_table, 0, 2 * 4); }else { float src_saturation = 1.0; float src_hue = 0.0; float src_contrast = 1.0; float src_brightness = 0.0; float tmp_value = 0.0; unsigned int i = 0; VAProcFilterParameterBufferColorBalance * amp_params = (VAProcFilterParameterBufferColorBalance *) proc_ctx->filter_iecp_amp; for (i = 0; i < proc_ctx->filter_iecp_amp_num_elements; i++){ VAProcColorBalanceType attrib = amp_params[i].attrib; if(attrib == VAProcColorBalanceHue) { src_hue = amp_params[i].value; //(-180.0, 180.0) }else if(attrib == VAProcColorBalanceSaturation) { src_saturation = amp_params[i].value; //(0.0, 10.0) }else if(attrib == VAProcColorBalanceBrightness) { src_brightness = amp_params[i].value; // (-100.0, 100.0) brightness = intel_format_convert(src_brightness, 7, 4, 1); }else if(attrib == VAProcColorBalanceContrast) { src_contrast = amp_params[i].value; // (0.0, 10.0) contrast = intel_format_convert(src_contrast, 4, 7, 0); } } tmp_value = cos(src_hue/180*PI) * src_contrast * src_saturation; cos_c_s = intel_format_convert(tmp_value, 7, 8, 1); tmp_value = sin(src_hue/180*PI) * src_contrast * src_saturation; sin_c_s = intel_format_convert(tmp_value, 7, 8, 1); *p_table ++ = ( 0 << 28 | //reserved contrast << 17 | //contrast value (U4.7 format) 0 << 13 | //reserved brightness << 1| // S7.4 format 1); *p_table ++ = ( cos_c_s << 16 | // cos(h) * contrast * saturation sin_c_s); // sin(h) * contrast * saturation } } void hsw_veb_iecp_csc_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { unsigned int *p_table = (unsigned int*)(proc_ctx->iecp_state_table.ptr + 220); float tran_coef[9] = {1.0, 0.0, 0.0, 0.0, 1.0, 0.0, 0.0, 0.0, 1.0}; float v_coef[3] = {0.0, 0.0, 0.0}; float u_coef[3] = {0.0, 0.0, 0.0}; int is_transform_enabled = 0; if(!(proc_ctx->filters_mask & VPP_IECP_CSC)){ memset(p_table, 0, 8 * 4); return; } if(proc_ctx->fourcc_input == VA_FOURCC('R','G','B','A') && (proc_ctx->fourcc_output == VA_FOURCC('N','V','1','2') || proc_ctx->fourcc_output == VA_FOURCC('Y','V','1','2') || proc_ctx->fourcc_output == VA_FOURCC('Y','V','Y','2') || proc_ctx->fourcc_output == VA_FOURCC('A','Y','U','V'))) { tran_coef[0] = 0.257; tran_coef[1] = 0.504; tran_coef[2] = 0.098; tran_coef[3] = -0.148; tran_coef[4] = -0.291; tran_coef[5] = 0.439; tran_coef[6] = 0.439; tran_coef[7] = -0.368; tran_coef[8] = -0.071; u_coef[0] = 16 * 4; u_coef[1] = 128 * 4; u_coef[2] = 128 * 4; is_transform_enabled = 1; }else if((proc_ctx->fourcc_input == VA_FOURCC('N','V','1','2') || proc_ctx->fourcc_input == VA_FOURCC('Y','V','1','2') || proc_ctx->fourcc_input == VA_FOURCC('Y','U','Y','2') || proc_ctx->fourcc_input == VA_FOURCC('A','Y','U','V'))&& proc_ctx->fourcc_output == VA_FOURCC('R','G','B','A')) { tran_coef[0] = 1.164; tran_coef[1] = 0.000; tran_coef[2] = 1.569; tran_coef[3] = 1.164; tran_coef[4] = -0.813; tran_coef[5] = -0.392; tran_coef[6] = 1.164; tran_coef[7] = 2.017; tran_coef[8] = 0.000; v_coef[0] = -16 * 4; v_coef[1] = -128 * 4; v_coef[2] = -128 * 4; is_transform_enabled = 1; }else if(proc_ctx->fourcc_input != proc_ctx->fourcc_output){ //enable when input and output format are different. is_transform_enabled = 1; } if(is_transform_enabled == 0){ memset(p_table, 0, 8 * 4); }else{ *p_table ++ = ( 0 << 29 | //reserved intel_format_convert(tran_coef[1], 2, 10, 1) << 16 | //c1, s2.10 format intel_format_convert(tran_coef[0], 2, 10, 1) << 3 | //c0, s2.10 format 0 << 2 | //reserved 0 << 1 | // yuv_channel swap is_transform_enabled); *p_table ++ = ( 0 << 26 | //reserved intel_format_convert(tran_coef[3], 2, 10, 1) << 13 | intel_format_convert(tran_coef[2], 2, 10, 1)); *p_table ++ = ( 0 << 26 | //reserved intel_format_convert(tran_coef[5], 2, 10, 1) << 13 | intel_format_convert(tran_coef[4], 2, 10, 1)); *p_table ++ = ( 0 << 26 | //reserved intel_format_convert(tran_coef[7], 2, 10, 1) << 13 | intel_format_convert(tran_coef[6], 2, 10, 1)); *p_table ++ = ( 0 << 13 | //reserved intel_format_convert(tran_coef[8], 2, 10, 1)); *p_table ++ = ( 0 << 22 | //reserved intel_format_convert(u_coef[0], 10, 0, 1) << 11 | intel_format_convert(v_coef[0], 10, 0, 1)); *p_table ++ = ( 0 << 22 | //reserved intel_format_convert(u_coef[1], 10, 0, 1) << 11 | intel_format_convert(v_coef[1], 10, 0, 1)); *p_table ++ = ( 0 << 22 | //reserved intel_format_convert(u_coef[2], 10, 0, 1) << 11 | intel_format_convert(v_coef[2], 10, 0, 1)); } } void hsw_veb_iecp_aoi_table(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { unsigned int *p_table = (unsigned int*)(proc_ctx->iecp_state_table.ptr + 252); // VAProcFilterParameterBuffer * tcc_param = // (VAProcFilterParameterBuffer *) proc_ctx->filter_iecp_tcc; if(!(proc_ctx->filters_mask & VPP_IECP_AOI)){ memset(p_table, 0, 3 * 4); }else{ *p_table ++ = 0x00000000; *p_table ++ = 0x00030000; *p_table ++ = 0x00030000; } } void hsw_veb_state_table_setup(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { if(proc_ctx->filters_mask & 0x000000ff) { dri_bo *dndi_bo = proc_ctx->dndi_state_table.bo; dri_bo_map(dndi_bo, 1); proc_ctx->dndi_state_table.ptr = dndi_bo->virtual; hsw_veb_dndi_table(ctx, proc_ctx); dri_bo_unmap(dndi_bo); } if(proc_ctx->filters_mask & 0x0000ff00) { dri_bo *iecp_bo = proc_ctx->iecp_state_table.bo; dri_bo_map(iecp_bo, 1); proc_ctx->iecp_state_table.ptr = iecp_bo->virtual; hsw_veb_iecp_std_table(ctx, proc_ctx); hsw_veb_iecp_ace_table(ctx, proc_ctx); hsw_veb_iecp_tcc_table(ctx, proc_ctx); hsw_veb_iecp_pro_amp_table(ctx, proc_ctx); hsw_veb_iecp_csc_table(ctx, proc_ctx); hsw_veb_iecp_aoi_table(ctx, proc_ctx); dri_bo_unmap(iecp_bo); } } void hsw_veb_state_command(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { struct intel_batchbuffer *batch = proc_ctx->batch; unsigned int is_dn_enabled = (proc_ctx->filters_mask & 0x01)? 1: 0; unsigned int is_di_enabled = (proc_ctx->filters_mask & 0x02)? 1: 0; unsigned int is_iecp_enabled = (proc_ctx->filters_mask & 0xff00)?1:0; unsigned int is_first_frame = !!((proc_ctx->frame_order == -1) && (is_di_enabled || is_dn_enabled)); unsigned int di_output_frames_flag = 2; /* Output Current Frame Only */ if(proc_ctx->fourcc_input != proc_ctx->fourcc_output || (is_dn_enabled == 0 && is_di_enabled == 0)){ is_iecp_enabled = 1; } if (is_di_enabled) { VAProcFilterParameterBufferDeinterlacing *di_param = (VAProcFilterParameterBufferDeinterlacing *)proc_ctx->filter_di; assert(di_param); if (di_param->algorithm == VAProcDeinterlacingBob) is_first_frame = 1; if ((di_param->algorithm == VAProcDeinterlacingMotionAdaptive || di_param->algorithm == VAProcDeinterlacingMotionCompensated) && proc_ctx->frame_order != -1) di_output_frames_flag = 0; /* Output both Current Frame and Previous Frame */ } BEGIN_VEB_BATCH(batch, 6); OUT_VEB_BATCH(batch, VEB_STATE | (6 - 2)); OUT_VEB_BATCH(batch, 0 << 26 | // state surface control bits 0 << 11 | // reserved. 0 << 10 | // pipe sync disable di_output_frames_flag << 8 | // DI output frame 1 << 7 | // 444->422 downsample method 1 << 6 | // 422->420 downsample method is_first_frame << 5 | // DN/DI first frame is_di_enabled << 4 | // DI enable is_dn_enabled << 3 | // DN enable is_iecp_enabled << 2 | // global IECP enabled 0 << 1 | // ColorGamutCompressionEnable 0 ) ; // ColorGamutExpansionEnable. OUT_RELOC(batch, proc_ctx->dndi_state_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_RELOC(batch, proc_ctx->iecp_state_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_RELOC(batch, proc_ctx->gamut_state_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_RELOC(batch, proc_ctx->vertex_state_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_VEB_BATCH(batch); } void hsw_veb_surface_state(VADriverContextP ctx, struct intel_vebox_context *proc_ctx, unsigned int is_output) { struct intel_batchbuffer *batch = proc_ctx->batch; unsigned int u_offset_y = 0, v_offset_y = 0; unsigned int is_uv_interleaved = 0, tiling = 0, swizzle = 0; unsigned int surface_format = PLANAR_420_8; struct object_surface* obj_surf = NULL; unsigned int surface_pitch = 0; unsigned int half_pitch_chroma = 0; if(is_output){ obj_surf = proc_ctx->frame_store[FRAME_OUT_CURRENT].obj_surface; }else { obj_surf = proc_ctx->frame_store[FRAME_IN_CURRENT].obj_surface; } assert(obj_surf->fourcc == VA_FOURCC_NV12 || obj_surf->fourcc == VA_FOURCC_YUY2 || obj_surf->fourcc == VA_FOURCC_AYUV || obj_surf->fourcc == VA_FOURCC_RGBA); if (obj_surf->fourcc == VA_FOURCC_NV12) { surface_format = PLANAR_420_8; surface_pitch = obj_surf->width; is_uv_interleaved = 1; half_pitch_chroma = 0; } else if (obj_surf->fourcc == VA_FOURCC_YUY2) { surface_format = YCRCB_NORMAL; surface_pitch = obj_surf->width * 2; is_uv_interleaved = 0; half_pitch_chroma = 0; } else if (obj_surf->fourcc == VA_FOURCC_AYUV) { surface_format = PACKED_444A_8; surface_pitch = obj_surf->width * 4; is_uv_interleaved = 0; half_pitch_chroma = 0; } else if (obj_surf->fourcc == VA_FOURCC_RGBA) { surface_format = R8G8B8A8_UNORM_SRGB; surface_pitch = obj_surf->width * 4; is_uv_interleaved = 0; half_pitch_chroma = 0; } u_offset_y = obj_surf->y_cb_offset; v_offset_y = obj_surf->y_cr_offset; dri_bo_get_tiling(obj_surf->bo, &tiling, &swizzle); BEGIN_VEB_BATCH(batch, 6); OUT_VEB_BATCH(batch, VEB_SURFACE_STATE | (6 - 2)); OUT_VEB_BATCH(batch, 0 << 1 | // reserved is_output); // surface indentification. OUT_VEB_BATCH(batch, (obj_surf->height - 1) << 18 | // height . w3 (obj_surf->width -1 ) << 4 | // width 0); // reserve OUT_VEB_BATCH(batch, surface_format << 28 | // surface format, YCbCr420. w4 is_uv_interleaved << 27 | // interleave chrome , two seperate palar 0 << 20 | // reserved (surface_pitch - 1) << 3 | // surface pitch, 64 align half_pitch_chroma << 2 | // half pitch for chrome !!tiling << 1 | // tiled surface, linear surface used (tiling == I915_TILING_Y)); // tiled walk, ignored when liner surface OUT_VEB_BATCH(batch, 0 << 29 | // reserved . w5 0 << 16 | // X offset for V(Cb) 0 << 15 | // reserved u_offset_y); // Y offset for V(Cb) OUT_VEB_BATCH(batch, 0 << 29 | // reserved . w6 0 << 16 | // X offset for V(Cr) 0 << 15 | // reserved v_offset_y ); // Y offset for V(Cr) ADVANCE_VEB_BATCH(batch); } void hsw_veb_dndi_iecp_command(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { struct intel_batchbuffer *batch = proc_ctx->batch; unsigned char frame_ctrl_bits = 0; unsigned int startingX = 0; unsigned int endingX = (proc_ctx->width_input + 63 ) / 64 * 64; /* s1:update the previous and current input */ /* tempFrame = proc_ctx->frame_store[FRAME_IN_PREVIOUS]; proc_ctx->frame_store[FRAME_IN_PREVIOUS] = proc_ctx->frame_store[FRAME_IN_CURRENT]; ; proc_ctx->frame_store[FRAME_IN_CURRENT] = tempFrame; if(proc_ctx->surface_input_vebox != -1){ vpp_surface_copy(ctx, proc_ctx->frame_store[FRAME_IN_CURRENT].surface_id, proc_ctx->surface_input_vebox); } else { vpp_surface_copy(ctx, proc_ctx->frame_store[FRAME_IN_CURRENT].surface_id, proc_ctx->surface_input); } */ /*s2: update the STMM input and output */ /* tempFrame = proc_ctx->frame_store[FRAME_IN_STMM]; proc_ctx->frame_store[FRAME_IN_STMM] = proc_ctx->frame_store[FRAME_OUT_STMM]; ; proc_ctx->frame_store[FRAME_OUT_STMM] = tempFrame; */ /*s3:set reloc buffer address */ BEGIN_VEB_BATCH(batch, 10); OUT_VEB_BATCH(batch, VEB_DNDI_IECP_STATE | (10 - 2)); OUT_VEB_BATCH(batch, startingX << 16 | (endingX-1)); OUT_RELOC(batch, proc_ctx->frame_store[FRAME_IN_CURRENT].obj_surface->bo, I915_GEM_DOMAIN_RENDER, 0, frame_ctrl_bits); OUT_RELOC(batch, proc_ctx->frame_store[FRAME_IN_PREVIOUS].obj_surface->bo, I915_GEM_DOMAIN_RENDER, 0, frame_ctrl_bits); OUT_RELOC(batch, proc_ctx->frame_store[FRAME_IN_STMM].obj_surface->bo, I915_GEM_DOMAIN_RENDER, 0, frame_ctrl_bits); OUT_RELOC(batch, proc_ctx->frame_store[FRAME_OUT_STMM].obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits); OUT_RELOC(batch, proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits); OUT_RELOC(batch, proc_ctx->frame_store[FRAME_OUT_CURRENT].obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits); OUT_RELOC(batch, proc_ctx->frame_store[FRAME_OUT_PREVIOUS].obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits); OUT_RELOC(batch, proc_ctx->frame_store[FRAME_OUT_STATISTIC].obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits); ADVANCE_VEB_BATCH(batch); } void hsw_veb_resource_prepare(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { VAStatus va_status; dri_bo *bo; struct i965_driver_data *i965 = i965_driver_data(ctx); unsigned int input_fourcc, output_fourcc; unsigned int input_sampling, output_sampling; unsigned int input_tiling, output_tiling; unsigned int i, swizzle; struct object_surface *obj_surf_out = NULL, *obj_surf_in = NULL; if (proc_ctx->surface_input_vebox_object != NULL) { obj_surf_in = proc_ctx->surface_input_vebox_object; } else { obj_surf_in = proc_ctx->surface_input_object; } if (proc_ctx->surface_output_vebox_object != NULL) { obj_surf_out = proc_ctx->surface_output_vebox_object; } else { obj_surf_out = proc_ctx->surface_output_object; } if(obj_surf_in->bo == NULL){ input_fourcc = VA_FOURCC('N','V','1','2'); input_sampling = SUBSAMPLE_YUV420; input_tiling = 0; i965_check_alloc_surface_bo(ctx, obj_surf_in, input_tiling, input_fourcc, input_sampling); } else { input_fourcc = obj_surf_in->fourcc; input_sampling = obj_surf_in->subsampling; dri_bo_get_tiling(obj_surf_in->bo, &input_tiling, &swizzle); input_tiling = !!input_tiling; } if(obj_surf_out->bo == NULL){ output_fourcc = VA_FOURCC('N','V','1','2'); output_sampling = SUBSAMPLE_YUV420; output_tiling = 0; i965_check_alloc_surface_bo(ctx, obj_surf_out, output_tiling, output_fourcc, output_sampling); }else { output_fourcc = obj_surf_out->fourcc; output_sampling = obj_surf_out->subsampling; dri_bo_get_tiling(obj_surf_out->bo, &output_tiling, &swizzle); output_tiling = !!output_tiling; } /* vebox pipelien input surface format info */ proc_ctx->fourcc_input = input_fourcc; proc_ctx->fourcc_output = output_fourcc; /* create pipeline surfaces */ for(i = 0; i < FRAME_STORE_SUM; i ++) { if(proc_ctx->frame_store[i].obj_surface){ continue; //refer external surface for vebox pipeline } VASurfaceID new_surface; struct object_surface *obj_surf = NULL; va_status = i965_CreateSurfaces(ctx, proc_ctx ->width_input, proc_ctx ->height_input, VA_RT_FORMAT_YUV420, 1, &new_surface); assert(va_status == VA_STATUS_SUCCESS); obj_surf = SURFACE(new_surface); assert(obj_surf); if( i <= FRAME_IN_PREVIOUS || i == FRAME_OUT_CURRENT_DN) { i965_check_alloc_surface_bo(ctx, obj_surf, input_tiling, input_fourcc, input_sampling); } else if( i == FRAME_IN_STMM || i == FRAME_OUT_STMM){ i965_check_alloc_surface_bo(ctx, obj_surf, 1, input_fourcc, input_sampling); } else if( i >= FRAME_OUT_CURRENT){ i965_check_alloc_surface_bo(ctx, obj_surf, output_tiling, output_fourcc, output_sampling); } proc_ctx->frame_store[i].surface_id = new_surface; proc_ctx->frame_store[i].is_internal_surface = 1; proc_ctx->frame_store[i].obj_surface = obj_surf; } /* alloc dndi state table */ dri_bo_unreference(proc_ctx->dndi_state_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vebox: dndi state Buffer", 0x1000, 0x1000); proc_ctx->dndi_state_table.bo = bo; dri_bo_reference(proc_ctx->dndi_state_table.bo); /* alloc iecp state table */ dri_bo_unreference(proc_ctx->iecp_state_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vebox: iecp state Buffer", 0x1000, 0x1000); proc_ctx->iecp_state_table.bo = bo; dri_bo_reference(proc_ctx->iecp_state_table.bo); /* alloc gamut state table */ dri_bo_unreference(proc_ctx->gamut_state_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vebox: gamut state Buffer", 0x1000, 0x1000); proc_ctx->gamut_state_table.bo = bo; dri_bo_reference(proc_ctx->gamut_state_table.bo); /* alloc vertex state table */ dri_bo_unreference(proc_ctx->vertex_state_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vertex: iecp state Buffer", 0x1000, 0x1000); proc_ctx->vertex_state_table.bo = bo; dri_bo_reference(proc_ctx->vertex_state_table.bo); } static VAStatus hsw_veb_surface_reference(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { struct object_surface * obj_surf; VEBFrameStore tmp_store; if (proc_ctx->surface_input_vebox_object != NULL) { obj_surf = proc_ctx->surface_input_vebox_object; } else { obj_surf = proc_ctx->surface_input_object; } /* update the input surface */ proc_ctx->frame_store[FRAME_IN_CURRENT].surface_id = VA_INVALID_ID; proc_ctx->frame_store[FRAME_IN_CURRENT].is_internal_surface = 0; proc_ctx->frame_store[FRAME_IN_CURRENT].obj_surface = obj_surf; /* update the previous input surface */ if (proc_ctx->frame_order != -1) { if (proc_ctx->filters_mask == VPP_DNDI_DN) { proc_ctx->frame_store[FRAME_IN_PREVIOUS] = proc_ctx->frame_store[FRAME_OUT_CURRENT_DN]; } else if (proc_ctx->filters_mask & VPP_DNDI_DI) { VAProcFilterParameterBufferDeinterlacing *di_param = (VAProcFilterParameterBufferDeinterlacing *)proc_ctx->filter_di; if (di_param && (di_param->algorithm == VAProcDeinterlacingMotionAdaptive || di_param->algorithm == VAProcDeinterlacingMotionCompensated)) { if ((proc_ctx->filters_mask & VPP_DNDI_DN) && proc_ctx->frame_order == 0) { /* DNDI */ tmp_store = proc_ctx->frame_store[FRAME_OUT_CURRENT_DN]; proc_ctx->frame_store[FRAME_OUT_CURRENT_DN] = proc_ctx->frame_store[FRAME_IN_PREVIOUS]; proc_ctx->frame_store[FRAME_IN_PREVIOUS] = tmp_store; } else { /* DI only */ VAProcPipelineParameterBuffer *pipe = proc_ctx->pipeline_param; struct object_surface *obj_surf = NULL; struct i965_driver_data * const i965 = i965_driver_data(ctx); if (!pipe || !pipe->num_forward_references || pipe->forward_references[0] == VA_INVALID_ID) { WARN_ONCE("A forward temporal reference is needed for Motion adaptive/compensated deinterlacing !!!\n"); return VA_STATUS_ERROR_INVALID_PARAMETER; } obj_surf = SURFACE(pipe->forward_references[0]); assert(obj_surf && obj_surf->bo); proc_ctx->frame_store[FRAME_IN_PREVIOUS].surface_id = pipe->forward_references[0]; proc_ctx->frame_store[FRAME_IN_PREVIOUS].is_internal_surface = 0; proc_ctx->frame_store[FRAME_IN_PREVIOUS].obj_surface = obj_surf; } } } } /* update STMM surface */ if (proc_ctx->frame_order != -1) { tmp_store = proc_ctx->frame_store[FRAME_IN_STMM]; proc_ctx->frame_store[FRAME_IN_STMM] = proc_ctx->frame_store[FRAME_OUT_STMM]; proc_ctx->frame_store[FRAME_OUT_STMM] = tmp_store; } /* update the output surface */ if (proc_ctx->surface_output_vebox_object != NULL) { obj_surf = proc_ctx->surface_output_vebox_object; } else { obj_surf = proc_ctx->surface_output_object; } if (proc_ctx->filters_mask == VPP_DNDI_DN) { proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].surface_id = VA_INVALID_ID; proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].is_internal_surface = 0; proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].obj_surface = obj_surf; proc_ctx->current_output = FRAME_OUT_CURRENT_DN; } else if (proc_ctx->filters_mask & VPP_DNDI_DI) { VAProcFilterParameterBufferDeinterlacing *di_param = (VAProcFilterParameterBufferDeinterlacing *)proc_ctx->filter_di; if (di_param && (di_param->algorithm == VAProcDeinterlacingMotionAdaptive || di_param->algorithm == VAProcDeinterlacingMotionCompensated)) { if (proc_ctx->frame_order == -1) { proc_ctx->frame_store[FRAME_OUT_CURRENT].surface_id = VA_INVALID_ID; proc_ctx->frame_store[FRAME_OUT_CURRENT].is_internal_surface = 0; proc_ctx->frame_store[FRAME_OUT_CURRENT].obj_surface = obj_surf; proc_ctx->current_output = FRAME_OUT_CURRENT; } else if (proc_ctx->frame_order == 0) { proc_ctx->frame_store[FRAME_OUT_PREVIOUS].surface_id = VA_INVALID_ID; proc_ctx->frame_store[FRAME_OUT_PREVIOUS].is_internal_surface = 0; proc_ctx->frame_store[FRAME_OUT_PREVIOUS].obj_surface = obj_surf; proc_ctx->current_output = FRAME_OUT_PREVIOUS; } else { proc_ctx->current_output = FRAME_OUT_CURRENT; proc_ctx->format_convert_flags |= POST_COPY_CONVERT; } } else { proc_ctx->frame_store[FRAME_OUT_CURRENT].surface_id = VA_INVALID_ID; proc_ctx->frame_store[FRAME_OUT_CURRENT].is_internal_surface = 0; proc_ctx->frame_store[FRAME_OUT_CURRENT].obj_surface = obj_surf; proc_ctx->current_output = FRAME_OUT_CURRENT; } } else { proc_ctx->frame_store[FRAME_OUT_CURRENT].surface_id = VA_INVALID_ID; proc_ctx->frame_store[FRAME_OUT_CURRENT].is_internal_surface = 0; proc_ctx->frame_store[FRAME_OUT_CURRENT].obj_surface = obj_surf; proc_ctx->current_output = FRAME_OUT_CURRENT; } return VA_STATUS_SUCCESS; } void hsw_veb_surface_unreference(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { /* unreference the input surface */ proc_ctx->frame_store[FRAME_IN_CURRENT].surface_id = VA_INVALID_ID; proc_ctx->frame_store[FRAME_IN_CURRENT].is_internal_surface = 0; proc_ctx->frame_store[FRAME_IN_CURRENT].obj_surface = NULL; /* unreference the shared output surface */ if (proc_ctx->filters_mask == VPP_DNDI_DN) { proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].surface_id = VA_INVALID_ID; proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].is_internal_surface = 0; proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].obj_surface = NULL; } else { proc_ctx->frame_store[FRAME_OUT_CURRENT].surface_id = VA_INVALID_ID; proc_ctx->frame_store[FRAME_OUT_CURRENT].is_internal_surface = 0; proc_ctx->frame_store[FRAME_OUT_CURRENT].obj_surface = NULL; } } int hsw_veb_pre_format_convert(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { VAStatus va_status; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface* obj_surf_input = proc_ctx->surface_input_object; struct object_surface* obj_surf_output = proc_ctx->surface_output_object; struct object_surface* obj_surf_input_vebox; struct object_surface* obj_surf_output_vebox; proc_ctx->format_convert_flags = 0; proc_ctx->width_input = obj_surf_input->orig_width; proc_ctx->height_input = obj_surf_input->orig_height; proc_ctx->width_output = obj_surf_output->orig_width; proc_ctx->height_output = obj_surf_output->orig_height; /* only partial frame is not supported to be processed */ /* assert(proc_ctx->width_input == proc_ctx->pipeline_param->surface_region->width); assert(proc_ctx->height_input == proc_ctx->pipeline_param->surface_region->height); assert(proc_ctx->width_output == proc_ctx->pipeline_param->output_region->width); assert(proc_ctx->height_output == proc_ctx->pipeline_param->output_region->height); */ if(proc_ctx->width_output != proc_ctx->width_input || proc_ctx->height_output != proc_ctx->height_input){ proc_ctx->format_convert_flags |= POST_SCALING_CONVERT; } /* convert the following format to NV12 format */ if(obj_surf_input->fourcc == VA_FOURCC('Y','V','1','2') || obj_surf_input->fourcc == VA_FOURCC('I','4','2','0') || obj_surf_input->fourcc == VA_FOURCC('I','M','C','1') || obj_surf_input->fourcc == VA_FOURCC('I','M','C','3') || obj_surf_input->fourcc == VA_FOURCC('R','G','B','A')){ proc_ctx->format_convert_flags |= PRE_FORMAT_CONVERT; } else if(obj_surf_input->fourcc == VA_FOURCC('A','Y','U','V') || obj_surf_input->fourcc == VA_FOURCC('Y','U','Y','2') || obj_surf_input->fourcc == VA_FOURCC('N','V','1','2')){ // nothing to do here } else { /* not support other format as input */ assert(0); } if (proc_ctx->format_convert_flags & PRE_FORMAT_CONVERT) { if(proc_ctx->surface_input_vebox_object == NULL){ va_status = i965_CreateSurfaces(ctx, proc_ctx->width_input, proc_ctx->height_input, VA_RT_FORMAT_YUV420, 1, &(proc_ctx->surface_input_vebox)); assert(va_status == VA_STATUS_SUCCESS); obj_surf_input_vebox = SURFACE(proc_ctx->surface_input_vebox); assert(obj_surf_input_vebox); if (obj_surf_input_vebox) { proc_ctx->surface_input_vebox_object = obj_surf_input_vebox; i965_check_alloc_surface_bo(ctx, obj_surf_input_vebox, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); } } vpp_surface_convert(ctx, proc_ctx->surface_input_vebox_object, proc_ctx->surface_input_object); } /* create one temporary NV12 surfaces for conversion*/ if(obj_surf_output->fourcc == VA_FOURCC('Y','V','1','2') || obj_surf_output->fourcc == VA_FOURCC('I','4','2','0') || obj_surf_output->fourcc == VA_FOURCC('I','M','C','1') || obj_surf_output->fourcc == VA_FOURCC('I','M','C','3') || obj_surf_output->fourcc == VA_FOURCC('R','G','B','A')) { proc_ctx->format_convert_flags |= POST_FORMAT_CONVERT; } else if(obj_surf_output->fourcc == VA_FOURCC('A','Y','U','V') || obj_surf_output->fourcc == VA_FOURCC('Y','U','Y','2') || obj_surf_output->fourcc == VA_FOURCC('N','V','1','2')){ /* Nothing to do here */ } else { /* not support other format as input */ assert(0); } if(proc_ctx->format_convert_flags & POST_FORMAT_CONVERT || proc_ctx->format_convert_flags & POST_SCALING_CONVERT){ if(proc_ctx->surface_output_vebox_object == NULL){ va_status = i965_CreateSurfaces(ctx, proc_ctx->width_input, proc_ctx->height_input, VA_RT_FORMAT_YUV420, 1, &(proc_ctx->surface_output_vebox)); assert(va_status == VA_STATUS_SUCCESS); obj_surf_output_vebox = SURFACE(proc_ctx->surface_output_vebox); assert(obj_surf_output_vebox); if (obj_surf_output_vebox) { proc_ctx->surface_output_vebox_object = obj_surf_output_vebox; i965_check_alloc_surface_bo(ctx, obj_surf_output_vebox, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); } } } if(proc_ctx->format_convert_flags & POST_SCALING_CONVERT){ if(proc_ctx->surface_output_scaled_object == NULL){ va_status = i965_CreateSurfaces(ctx, proc_ctx->width_output, proc_ctx->height_output, VA_RT_FORMAT_YUV420, 1, &(proc_ctx->surface_output_scaled)); assert(va_status == VA_STATUS_SUCCESS); obj_surf_output_vebox = SURFACE(proc_ctx->surface_output_scaled); assert(obj_surf_output_vebox); if (obj_surf_output_vebox) { proc_ctx->surface_output_scaled_object = obj_surf_output_vebox; i965_check_alloc_surface_bo(ctx, obj_surf_output_vebox, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); } } } return 0; } int hsw_veb_post_format_convert(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { struct object_surface *obj_surface = NULL; obj_surface = proc_ctx->frame_store[proc_ctx->current_output].obj_surface; if (proc_ctx->format_convert_flags & POST_COPY_CONVERT) { /* copy the saved frame in the second call */ vpp_surface_convert(ctx,proc_ctx->surface_output_object, obj_surface); } else if(!(proc_ctx->format_convert_flags & POST_FORMAT_CONVERT) && !(proc_ctx->format_convert_flags & POST_SCALING_CONVERT)){ /* Output surface format is covered by vebox pipeline and * processed picture is already store in output surface * so nothing will be done here */ } else if ((proc_ctx->format_convert_flags & POST_FORMAT_CONVERT) && !(proc_ctx->format_convert_flags & POST_SCALING_CONVERT)){ /* convert and copy NV12 to YV12/IMC3/IMC2/RGBA output*/ vpp_surface_convert(ctx,proc_ctx->surface_output_object, obj_surface); } else if(proc_ctx->format_convert_flags & POST_SCALING_CONVERT) { /* scaling, convert and copy NV12 to YV12/IMC3/IMC2/RGBA output*/ assert(obj_surface->fourcc == VA_FOURCC('N','V','1','2')); /* first step :surface scaling */ vpp_surface_scaling(ctx,proc_ctx->surface_output_scaled_object, obj_surface); /* second step: color format convert and copy to output */ obj_surface = proc_ctx->surface_output_object; if(obj_surface->fourcc == VA_FOURCC('N','V','1','2') || obj_surface->fourcc == VA_FOURCC('Y','V','1','2') || obj_surface->fourcc == VA_FOURCC('I','4','2','0') || obj_surface->fourcc == VA_FOURCC('Y','U','Y','2') || obj_surface->fourcc == VA_FOURCC('I','M','C','1') || obj_surface->fourcc == VA_FOURCC('I','M','C','3') || obj_surface->fourcc == VA_FOURCC('R','G','B','A')) { vpp_surface_convert(ctx, proc_ctx->surface_output_object, proc_ctx->surface_output_scaled_object); }else { assert(0); } } return 0; } VAStatus gen75_vebox_process_picture(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAProcPipelineParameterBuffer *pipe = proc_ctx->pipeline_param; VAProcFilterParameterBuffer* filter = NULL; struct object_buffer *obj_buf = NULL; unsigned int i; for (i = 0; i < pipe->num_filters; i ++) { obj_buf = BUFFER(pipe->filters[i]); assert(obj_buf && obj_buf->buffer_store); if (!obj_buf || !obj_buf->buffer_store) goto error; filter = (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer; if (filter->type == VAProcFilterNoiseReduction) { proc_ctx->filters_mask |= VPP_DNDI_DN; proc_ctx->filter_dn = filter; } else if (filter->type == VAProcFilterDeinterlacing) { proc_ctx->filters_mask |= VPP_DNDI_DI; proc_ctx->filter_di = filter; } else if (filter->type == VAProcFilterColorBalance) { proc_ctx->filters_mask |= VPP_IECP_PRO_AMP; proc_ctx->filter_iecp_amp = filter; proc_ctx->filter_iecp_amp_num_elements = obj_buf->num_elements; } } hsw_veb_pre_format_convert(ctx, proc_ctx); hsw_veb_surface_reference(ctx, proc_ctx); if (proc_ctx->frame_order == -1) { hsw_veb_resource_prepare(ctx, proc_ctx); } if (proc_ctx->format_convert_flags & POST_COPY_CONVERT) { assert(proc_ctx->frame_order == 1); /* directly copy the saved frame in the second call */ } else { intel_batchbuffer_start_atomic_veb(proc_ctx->batch, 0x1000); intel_batchbuffer_emit_mi_flush(proc_ctx->batch); hsw_veb_surface_state(ctx, proc_ctx, INPUT_SURFACE); hsw_veb_surface_state(ctx, proc_ctx, OUTPUT_SURFACE); hsw_veb_state_table_setup(ctx, proc_ctx); hsw_veb_state_command(ctx, proc_ctx); hsw_veb_dndi_iecp_command(ctx, proc_ctx); intel_batchbuffer_end_atomic(proc_ctx->batch); intel_batchbuffer_flush(proc_ctx->batch); } hsw_veb_post_format_convert(ctx, proc_ctx); // hsw_veb_surface_unreference(ctx, proc_ctx); proc_ctx->frame_order = (proc_ctx->frame_order + 1) % 2; return VA_STATUS_SUCCESS; error: return VA_STATUS_ERROR_INVALID_PARAMETER; } void gen75_vebox_context_destroy(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { int i; if(proc_ctx->surface_input_vebox != VA_INVALID_ID){ i965_DestroySurfaces(ctx, &proc_ctx->surface_input_vebox, 1); proc_ctx->surface_input_vebox = VA_INVALID_ID; proc_ctx->surface_input_vebox_object = NULL; } if(proc_ctx->surface_output_vebox != VA_INVALID_ID){ i965_DestroySurfaces(ctx, &proc_ctx->surface_output_vebox, 1); proc_ctx->surface_output_vebox = VA_INVALID_ID; proc_ctx->surface_output_vebox_object = NULL; } if(proc_ctx->surface_output_scaled != VA_INVALID_ID){ i965_DestroySurfaces(ctx, &proc_ctx->surface_output_scaled, 1); proc_ctx->surface_output_scaled = VA_INVALID_ID; proc_ctx->surface_output_scaled_object = NULL; } for(i = 0; i < FRAME_STORE_SUM; i ++) { if (proc_ctx->frame_store[i].is_internal_surface == 1) { assert(proc_ctx->frame_store[i].surface_id != VA_INVALID_ID); if (proc_ctx->frame_store[i].surface_id != VA_INVALID_ID) i965_DestroySurfaces(ctx, &proc_ctx->frame_store[i].surface_id, 1); } proc_ctx->frame_store[i].surface_id = VA_INVALID_ID; proc_ctx->frame_store[i].is_internal_surface = 0; proc_ctx->frame_store[i].obj_surface = NULL; } /* dndi state table */ dri_bo_unreference(proc_ctx->dndi_state_table.bo); proc_ctx->dndi_state_table.bo = NULL; /* iecp state table */ dri_bo_unreference(proc_ctx->iecp_state_table.bo); proc_ctx->dndi_state_table.bo = NULL; /* gamut statu table */ dri_bo_unreference(proc_ctx->gamut_state_table.bo); proc_ctx->gamut_state_table.bo = NULL; /* vertex state table */ dri_bo_unreference(proc_ctx->vertex_state_table.bo); proc_ctx->vertex_state_table.bo = NULL; intel_batchbuffer_free(proc_ctx->batch); free(proc_ctx); } struct intel_vebox_context * gen75_vebox_context_init(VADriverContextP ctx) { struct intel_driver_data *intel = intel_driver_data(ctx); struct intel_vebox_context *proc_context = calloc(1, sizeof(struct intel_vebox_context)); int i; proc_context->batch = intel_batchbuffer_new(intel, I915_EXEC_VEBOX, 0); memset(proc_context->frame_store, 0, sizeof(VEBFrameStore)*FRAME_STORE_SUM); for (i = 0; i < FRAME_STORE_SUM; i ++) { proc_context->frame_store[i].surface_id = VA_INVALID_ID; proc_context->frame_store[i].is_internal_surface = 0; proc_context->frame_store[i].obj_surface = NULL; } proc_context->filters_mask = 0; proc_context->frame_order = -1; /* the first frame */ proc_context->surface_output_object = NULL; proc_context->surface_input_object = NULL; proc_context->surface_input_vebox = VA_INVALID_ID; proc_context->surface_input_vebox_object = NULL; proc_context->surface_output_vebox = VA_INVALID_ID; proc_context->surface_output_vebox_object = NULL; proc_context->surface_output_scaled = VA_INVALID_ID; proc_context->surface_output_scaled_object = NULL; proc_context->filters_mask = 0; proc_context->format_convert_flags = 0; return proc_context; } void bdw_veb_state_command(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { struct intel_batchbuffer *batch = proc_ctx->batch; unsigned int is_dn_enabled = (proc_ctx->filters_mask & 0x01)? 1: 0; unsigned int is_di_enabled = (proc_ctx->filters_mask & 0x02)? 1: 0; unsigned int is_iecp_enabled = (proc_ctx->filters_mask & 0xff00)?1:0; unsigned int is_first_frame = !!((proc_ctx->frame_order == -1) && (is_di_enabled || is_dn_enabled)); unsigned int di_output_frames_flag = 2; /* Output Current Frame Only */ if(proc_ctx->fourcc_input != proc_ctx->fourcc_output || (is_dn_enabled == 0 && is_di_enabled == 0)){ is_iecp_enabled = 1; } if (is_di_enabled) { VAProcFilterParameterBufferDeinterlacing *di_param = (VAProcFilterParameterBufferDeinterlacing *)proc_ctx->filter_di; assert(di_param); if (di_param->algorithm == VAProcDeinterlacingBob) is_first_frame = 1; if ((di_param->algorithm == VAProcDeinterlacingMotionAdaptive || di_param->algorithm == VAProcDeinterlacingMotionCompensated) && proc_ctx->frame_order != -1) di_output_frames_flag = 0; /* Output both Current Frame and Previous Frame */ } BEGIN_VEB_BATCH(batch, 0xc); OUT_VEB_BATCH(batch, VEB_STATE | (0xc - 2)); OUT_VEB_BATCH(batch, 0 << 25 | // state surface control bits 0 << 23 | // reserved. 0 << 22 | // gamut expansion position 0 << 15 | // reserved. 0 << 14 | // single slice vebox enable 0 << 13 | // hot pixel filter enable 0 << 12 | // alpha plane enable 0 << 11 | // vignette enable 0 << 10 | // demosaic enable di_output_frames_flag << 8 | // DI output frame 1 << 7 | // 444->422 downsample method 1 << 6 | // 422->420 downsample method is_first_frame << 5 | // DN/DI first frame is_di_enabled << 4 | // DI enable is_dn_enabled << 3 | // DN enable is_iecp_enabled << 2 | // global IECP enabled 0 << 1 | // ColorGamutCompressionEnable 0 ) ; // ColorGamutExpansionEnable. OUT_RELOC(batch, proc_ctx->dndi_state_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_VEB_BATCH(batch, 0); OUT_RELOC(batch, proc_ctx->iecp_state_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_VEB_BATCH(batch, 0); OUT_RELOC(batch, proc_ctx->gamut_state_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_VEB_BATCH(batch, 0); OUT_RELOC(batch, proc_ctx->vertex_state_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_VEB_BATCH(batch, 0); OUT_VEB_BATCH(batch, 0);/*caputre pipe state pointer*/ OUT_VEB_BATCH(batch, 0); ADVANCE_VEB_BATCH(batch); } void bdw_veb_dndi_iecp_command(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { struct intel_batchbuffer *batch = proc_ctx->batch; unsigned char frame_ctrl_bits = 0; unsigned int startingX = 0; unsigned int endingX = (proc_ctx->width_input + 63 ) / 64 * 64; BEGIN_VEB_BATCH(batch, 0x14); OUT_VEB_BATCH(batch, VEB_DNDI_IECP_STATE | (0x14 - 2));//DWord 0 OUT_VEB_BATCH(batch, startingX << 16 | endingX -1);//DWord 1 OUT_RELOC(batch, proc_ctx->frame_store[FRAME_IN_CURRENT].obj_surface->bo, I915_GEM_DOMAIN_RENDER, 0, frame_ctrl_bits);//DWord 2 OUT_VEB_BATCH(batch,0);//DWord 3 OUT_RELOC(batch, proc_ctx->frame_store[FRAME_IN_PREVIOUS].obj_surface->bo, I915_GEM_DOMAIN_RENDER, 0, frame_ctrl_bits);//DWord 4 OUT_VEB_BATCH(batch,0);//DWord 5 OUT_RELOC(batch, proc_ctx->frame_store[FRAME_IN_STMM].obj_surface->bo, I915_GEM_DOMAIN_RENDER, 0, frame_ctrl_bits);//DWord 6 OUT_VEB_BATCH(batch,0);//DWord 7 OUT_RELOC(batch, proc_ctx->frame_store[FRAME_OUT_STMM].obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits);//DWord 8 OUT_VEB_BATCH(batch,0);//DWord 9 OUT_RELOC(batch, proc_ctx->frame_store[FRAME_OUT_CURRENT_DN].obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits);//DWord 10 OUT_VEB_BATCH(batch,0);//DWord 11 OUT_RELOC(batch, proc_ctx->frame_store[FRAME_OUT_CURRENT].obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits);//DWord 12 OUT_VEB_BATCH(batch,0);//DWord 13 OUT_RELOC(batch, proc_ctx->frame_store[FRAME_OUT_PREVIOUS].obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits);//DWord 14 OUT_VEB_BATCH(batch,0);//DWord 15 OUT_RELOC(batch, proc_ctx->frame_store[FRAME_OUT_STATISTIC].obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, frame_ctrl_bits);//DWord 16 OUT_VEB_BATCH(batch,0);//DWord 17 OUT_VEB_BATCH(batch,0);//DWord 18 OUT_VEB_BATCH(batch,0);//DWord 19 ADVANCE_VEB_BATCH(batch); } VAStatus gen8_vebox_process_picture(VADriverContextP ctx, struct intel_vebox_context *proc_ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAProcPipelineParameterBuffer *pipe = proc_ctx->pipeline_param; VAProcFilterParameterBuffer* filter = NULL; struct object_buffer *obj_buf = NULL; unsigned int i; for (i = 0; i < pipe->num_filters; i ++) { obj_buf = BUFFER(pipe->filters[i]); assert(obj_buf && obj_buf->buffer_store); if (!obj_buf || !obj_buf->buffer_store) goto error; filter = (VAProcFilterParameterBuffer*)obj_buf-> buffer_store->buffer; if (filter->type == VAProcFilterNoiseReduction) { proc_ctx->filters_mask |= VPP_DNDI_DN; proc_ctx->filter_dn = filter; } else if (filter->type == VAProcFilterDeinterlacing) { proc_ctx->filters_mask |= VPP_DNDI_DI; proc_ctx->filter_di = filter; } else if (filter->type == VAProcFilterColorBalance) { proc_ctx->filters_mask |= VPP_IECP_PRO_AMP; proc_ctx->filter_iecp_amp = filter; proc_ctx->filter_iecp_amp_num_elements = obj_buf->num_elements; } } hsw_veb_pre_format_convert(ctx, proc_ctx); hsw_veb_surface_reference(ctx, proc_ctx); if (proc_ctx->frame_order == -1) { hsw_veb_resource_prepare(ctx, proc_ctx); } if (proc_ctx->format_convert_flags & POST_COPY_CONVERT) { assert(proc_ctx->frame_order == 1); /* directly copy the saved frame in the second call */ } else { intel_batchbuffer_start_atomic_veb(proc_ctx->batch, 0x1000); intel_batchbuffer_emit_mi_flush(proc_ctx->batch); hsw_veb_surface_state(ctx, proc_ctx, INPUT_SURFACE); hsw_veb_surface_state(ctx, proc_ctx, OUTPUT_SURFACE); hsw_veb_state_table_setup(ctx, proc_ctx); bdw_veb_state_command(ctx, proc_ctx); bdw_veb_dndi_iecp_command(ctx, proc_ctx); intel_batchbuffer_end_atomic(proc_ctx->batch); intel_batchbuffer_flush(proc_ctx->batch); } hsw_veb_post_format_convert(ctx, proc_ctx); // hsw_veb_surface_unreference(ctx, proc_ctx); proc_ctx->frame_order = (proc_ctx->frame_order + 1) % 2; return VA_STATUS_SUCCESS; error: return VA_STATUS_ERROR_INVALID_PARAMETER; } intel-driver-1.3.0/src/gen75_vpp_vebox.h000066400000000000000000000104771231401140700200760ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Li Xiaowei * */ #ifndef _GEN75_VPP_VEBOX_H #define _GEN75_VPP_VEBOX_H #include #include #include #include #include #include "i965_drv_video.h" #include "i965_post_processing.h" #define INPUT_SURFACE 0 #define OUTPUT_SURFACE 1 #define VPP_DNDI_DN 0x00000001 #define VPP_DNDI_DI 0x00000002 #define VPP_IECP_STD_STE 0x00000100 #define VPP_IECP_ACE 0x00000200 #define VPP_IECP_TCC 0x00000400 #define VPP_IECP_PRO_AMP 0x00000800 #define VPP_IECP_CSC 0x00001000 #define VPP_IECP_AOI 0x00002000 #define MAX_FILTER_SUM 8 #define PRE_FORMAT_CONVERT 0x01 #define POST_FORMAT_CONVERT 0x02 #define POST_SCALING_CONVERT 0x04 #define POST_COPY_CONVERT 0x08 enum { FRAME_IN_CURRENT = 0, FRAME_IN_PREVIOUS, FRAME_IN_STMM, FRAME_OUT_STMM, FRAME_OUT_CURRENT_DN, FRAME_OUT_CURRENT, FRAME_OUT_PREVIOUS, FRAME_OUT_STATISTIC, FRAME_STORE_SUM, }; enum SURFACE_FORMAT{ YCRCB_NORMAL = 0, YCRCB_SWAPUVY, YCRCB_SWAPUV, YCRCB_SWAPY, PLANAR_420_8, //NV12 PACKED_444A_8, PACKED_422_16, R10G10B10A2_UNORM_SRGB, R8G8B8A8_UNORM_SRGB, PACKED_444_16, PLANAR_422_16, Y8_UNORM, PLANAR_420_16, R16G16B16A16, SURFACE_FORMAT_SUM }; typedef struct veb_frame_store { VASurfaceID surface_id; unsigned int is_internal_surface; struct object_surface *obj_surface; } VEBFrameStore; typedef struct veb_buffer { dri_bo *bo; void * ptr; unsigned char valid; } VEBBuffer; struct intel_vebox_context { struct intel_batchbuffer *batch; struct object_surface *surface_input_object; struct object_surface *surface_output_object; VASurfaceID surface_input_vebox; struct object_surface *surface_input_vebox_object; VASurfaceID surface_output_vebox; struct object_surface *surface_output_vebox_object; VASurfaceID surface_output_scaled; struct object_surface *surface_output_scaled_object; unsigned int fourcc_input; unsigned int fourcc_output; int width_input; int height_input; int width_output; int height_output; VEBFrameStore frame_store[FRAME_STORE_SUM]; VEBBuffer dndi_state_table; VEBBuffer iecp_state_table; VEBBuffer gamut_state_table; VEBBuffer vertex_state_table; unsigned int filters_mask; int frame_order; int current_output; VAProcPipelineParameterBuffer * pipeline_param; void * filter_dn; void * filter_di; void * filter_iecp_std; void * filter_iecp_ace; void * filter_iecp_tcc; void * filter_iecp_amp; unsigned int filter_iecp_amp_num_elements; unsigned char format_convert_flags; }; VAStatus gen75_vebox_process_picture(VADriverContextP ctx, struct intel_vebox_context *proc_ctx); void gen75_vebox_context_destroy(VADriverContextP ctx, struct intel_vebox_context *proc_ctx); struct intel_vebox_context * gen75_vebox_context_init(VADriverContextP ctx); VAStatus gen8_vebox_process_picture(VADriverContextP ctx, struct intel_vebox_context *proc_ctx); #endif intel-driver-1.3.0/src/gen7_mfc.c000066400000000000000000001412671231401140700165430ustar00rootroot00000000000000/* * Copyright © 2011 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Zhou Chang * Xiang, Haihao * */ #include #include #include #include #include "intel_batchbuffer.h" #include "i965_defines.h" #include "i965_structs.h" #include "i965_drv_video.h" #include "i965_encoder.h" #include "i965_encoder_utils.h" #include "gen6_mfc.h" #include "gen6_vme.h" #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7) #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index) extern void gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context); extern void gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context); extern void gen6_mfc_init(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context); extern VAStatus gen6_mfc_run(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context); extern VAStatus gen6_mfc_stop(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int *encoded_bits_size); extern VAStatus gen6_mfc_avc_encode_picture(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context); static const uint32_t gen7_mfc_batchbuffer_avc_intra[][4] = { #include "shaders/utils/mfc_batchbuffer_avc_intra.g7b" }; static const uint32_t gen7_mfc_batchbuffer_avc_inter[][4] = { #include "shaders/utils/mfc_batchbuffer_avc_inter.g7b" }; static struct i965_kernel gen7_mfc_kernels[] = { { "MFC AVC INTRA BATCHBUFFER ", MFC_BATCHBUFFER_AVC_INTRA, gen7_mfc_batchbuffer_avc_intra, sizeof(gen7_mfc_batchbuffer_avc_intra), NULL }, { "MFC AVC INTER BATCHBUFFER ", MFC_BATCHBUFFER_AVC_INTER, gen7_mfc_batchbuffer_avc_inter, sizeof(gen7_mfc_batchbuffer_avc_inter), NULL }, }; static void gen7_mfc_pipe_mode_select(VADriverContextP ctx, int standard_select, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; assert(standard_select == MFX_FORMAT_MPEG2 || standard_select == MFX_FORMAT_AVC); BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2)); OUT_BCS_BATCH(batch, (MFX_LONG_MODE << 17) | /* Must be long format for encoder */ (MFD_MODE_VLD << 15) | /* VLD mode */ (1 << 10) | /* Stream-Out Enable */ ((!!mfc_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */ ((!!mfc_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */ (0 << 8) | /* Pre Deblocking Output */ (0 << 5) | /* not in stitch mode */ (1 << 4) | /* encoding mode */ (standard_select << 0)); /* standard select: avc or mpeg2 */ OUT_BCS_BATCH(batch, (0 << 7) | /* expand NOA bus flag */ (0 << 6) | /* disable slice-level clock gating */ (0 << 5) | /* disable clock gating for NOA */ (0 << 4) | /* terminate if AVC motion and POC table error occurs */ (0 << 3) | /* terminate if AVC mbdata error occurs */ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ (0 << 1) | (0 << 0)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, ((mfc_context->surface_state.height - 1) << 18) | ((mfc_context->surface_state.width - 1) << 4)); OUT_BCS_BATCH(batch, (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */ (0 << 22) | /* surface object control state, FIXME??? */ ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */ (0 << 2) | /* must be 0 for interleave U/V */ (1 << 1) | /* must be tiled */ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */ OUT_BCS_BATCH(batch, (0 << 16) | /* must be 0 for interleave U/V */ (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* MFX Indirect MV Object Base Address */ OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /*MFC Indirect PAK-BSE Object Base Address for Encoder*/ OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, mfc_context->mfc_indirect_pak_bse_object.end_offset); ADVANCE_BCS_BATCH(batch); } static void gen7_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; BEGIN_BCS_BATCH(batch, 16); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2)); /*DW1 frame size */ OUT_BCS_BATCH(batch, ((width_in_mbs * height_in_mbs - 1) & 0xFFFF)); OUT_BCS_BATCH(batch, ((height_in_mbs - 1) << 16) | ((width_in_mbs - 1) << 0)); /*DW3 Qp setting */ OUT_BCS_BATCH(batch, (0 << 24) | /* Second Chroma QP Offset */ (0 << 16) | /* Chroma QP Offset */ (0 << 14) | /* Max-bit conformance Intra flag */ (0 << 13) | /* Max Macroblock size conformance Inter flag */ (pPicParameter->pic_fields.bits.weighted_pred_flag << 12) | /*Weighted_Pred_Flag */ (pPicParameter->pic_fields.bits.weighted_bipred_idc << 10) | /* Weighted_BiPred_Idc */ (0 << 8) | /* FIXME: Image Structure */ (0 << 0) ); /* Current Decoed Image Frame Store ID, reserved in Encode mode */ OUT_BCS_BATCH(batch, (0 << 16) | /* Mininum Frame size */ (0 << 15) | /* Disable reading of Macroblock Status Buffer */ (0 << 14) | /* Load BitStream Pointer only once, 1 slic 1 frame */ (0 << 13) | /* CABAC 0 word insertion test enable */ (1 << 12) | /* MVUnpackedEnable,compliant to DXVA */ (1 << 10) | /* Chroma Format IDC, 4:2:0 */ (0 << 9) | /* FIXME: MbMvFormatFlag */ (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/ (0 << 6) | /* Only valid for VLD decoding mode */ (0 << 5) | /* Constrained Intra Predition Flag, from PPS */ (0 << 4) | /* Direct 8x8 inference flag */ (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/ (1 << 2) | /* Frame MB only flag */ (0 << 1) | /* MBAFF mode is in active */ (0 << 0)); /* Field picture flag */ /*DW5 trequllis quantization */ OUT_BCS_BATCH(batch, 0); /* Mainly about MB rate control and debug, just ignoring */ OUT_BCS_BATCH(batch, /* Inter and Intra Conformance Max size limit */ (0xBB8 << 16) | /* InterMbMaxSz */ (0xEE8) ); /* IntraMbMaxSz */ /* DW7 */ OUT_BCS_BATCH(batch, 0); /* Reserved */ OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */ OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */ /* DW10 frame bit setting */ OUT_BCS_BATCH(batch, 0x8C000000); OUT_BCS_BATCH(batch, 0x00010000); OUT_BCS_BATCH(batch, 0); /* DW13 Ref setting */ OUT_BCS_BATCH(batch, 0x02010100); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_mfc_qm_state(VADriverContextP ctx, int qm_type, unsigned int *qm, int qm_length, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; unsigned int qm_buffer[16]; assert(qm_length <= 16); assert(sizeof(*qm) == 4); memcpy(qm_buffer, qm, qm_length * 4); BEGIN_BCS_BATCH(batch, 18); OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2)); OUT_BCS_BATCH(batch, qm_type << 0); intel_batchbuffer_data(batch, qm_buffer, 16 * 4); ADVANCE_BCS_BATCH(batch); } static void gen7_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned int qm[16] = { 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010 }; gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, encoder_context); gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, encoder_context); gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, encoder_context); gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, encoder_context); } static void gen7_mfc_fqm_state(VADriverContextP ctx, int fqm_type, unsigned int *fqm, int fqm_length, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; unsigned int fqm_buffer[32]; assert(fqm_length <= 32); assert(sizeof(*fqm) == 4); memcpy(fqm_buffer, fqm, fqm_length * 4); BEGIN_BCS_BATCH(batch, 34); OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2)); OUT_BCS_BATCH(batch, fqm_type << 0); intel_batchbuffer_data(batch, fqm_buffer, 32 * 4); ADVANCE_BCS_BATCH(batch); } static void gen7_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned int qm[32] = { 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000 }; gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, encoder_context); gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, encoder_context); gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, encoder_context); gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, encoder_context); } static void gen7_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context, unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw, int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag, struct intel_batchbuffer *batch) { if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, lenght_in_dws + 2); OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws + 2 - 2)); OUT_BCS_BATCH(batch, (0 << 16) | /* always start at offset 0 */ (data_bits_in_last_dw << 8) | (skip_emul_byte_count << 4) | (!!emulation_flag << 3) | ((!!is_last_header) << 2) | ((!!is_end_of_slice) << 1) | (0 << 0)); /* FIXME: ??? */ intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4); ADVANCE_BCS_BATCH(batch); } static const int va_to_gen7_mpeg2_picture_type[3] = { 1, /* I */ 2, /* P */ 3 /* B */ }; static void gen7_mfc_mpeg2_pic_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context, struct encode_state *encode_state) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncPictureParameterBufferMPEG2 *pic_param; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; VAEncSliceParameterBufferMPEG2 *slice_param = NULL; assert(encode_state->pic_param_ext && encode_state->pic_param_ext->buffer); pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer; BEGIN_BCS_BATCH(batch, 13); OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2)); OUT_BCS_BATCH(batch, (pic_param->f_code[1][1] & 0xf) << 28 | /* f_code[1][1] */ (pic_param->f_code[1][0] & 0xf) << 24 | /* f_code[1][0] */ (pic_param->f_code[0][1] & 0xf) << 20 | /* f_code[0][1] */ (pic_param->f_code[0][0] & 0xf) << 16 | /* f_code[0][0] */ pic_param->picture_coding_extension.bits.intra_dc_precision << 14 | pic_param->picture_coding_extension.bits.picture_structure << 12 | pic_param->picture_coding_extension.bits.top_field_first << 11 | pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 | pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 | pic_param->picture_coding_extension.bits.q_scale_type << 8 | pic_param->picture_coding_extension.bits.intra_vlc_format << 7 | pic_param->picture_coding_extension.bits.alternate_scan << 6); OUT_BCS_BATCH(batch, 0 << 14 | /* LoadSlicePointerFlag, 0 means only loading bitstream pointer once */ va_to_gen7_mpeg2_picture_type[pic_param->picture_type] << 9 | 0); OUT_BCS_BATCH(batch, 1 << 31 | /* slice concealment */ (height_in_mbs - 1) << 16 | (width_in_mbs - 1)); if (slice_param && slice_param->quantiser_scale_code >= 14) OUT_BCS_BATCH(batch, (3 << 1) | (1 << 4) | (5 << 8) | (1 << 12)); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0xFFF << 16 | /* InterMBMaxSize */ 0xFFF << 0 | /* IntraMBMaxSize */ 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_mfc_mpeg2_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned char intra_qm[64] = { 8, 16, 19, 22, 26, 27, 29, 34, 16, 16, 22, 24, 27, 29, 34, 37, 19, 22, 26, 27, 29, 34, 34, 38, 22, 22, 26, 27, 29, 34, 37, 40, 22, 26, 27, 29, 32, 35, 40, 48, 26, 27, 29, 32, 35, 40, 48, 58, 26, 27, 29, 34, 38, 46, 56, 69, 27, 29, 35, 38, 46, 56, 69, 83 }; unsigned char non_intra_qm[64] = { 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16 }; gen7_mfc_qm_state(ctx, MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX, (unsigned int *)intra_qm, 16, encoder_context); gen7_mfc_qm_state(ctx, MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX, (unsigned int *)non_intra_qm, 16,encoder_context); } static void gen7_mfc_mpeg2_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned short intra_fqm[64] = { 65536/0x8, 65536/0x10, 65536/0x13, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, 65536/0x10, 65536/0x10, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1b, 65536/0x1b, 65536/0x1d, 65536/0x13, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, 65536/0x1d, 65536/0x1d, 65536/0x23, 65536/0x16, 65536/0x18, 65536/0x1b, 65536/0x1b, 65536/0x13, 65536/0x20, 65536/0x22, 65536/0x26, 65536/0x1a, 65536/0x1b, 65536/0x13, 65536/0x13, 65536/0x20, 65536/0x23, 65536/0x26, 65536/0x2e, 65536/0x1b, 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x23, 65536/0x28, 65536/0x2e, 65536/0x38, 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x25, 65536/0x28, 65536/0x30, 65536/0x38, 65536/0x45, 65536/0x22, 65536/0x25, 65536/0x26, 65536/0x28, 65536/0x30, 65536/0x3a, 65536/0x45, 65536/0x53, }; unsigned short non_intra_fqm[64] = { 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, }; gen7_mfc_fqm_state(ctx, MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX, (unsigned int *)intra_fqm, 32, encoder_context); gen7_mfc_fqm_state(ctx, MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX, (unsigned int *)non_intra_fqm, 32, encoder_context); } static void gen7_mfc_mpeg2_slicegroup_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context, int x, int y, int next_x, int next_y, int is_fisrt_slice_group, int is_last_slice_group, int intra_slice, int qp, struct intel_batchbuffer *batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, 8); OUT_BCS_BATCH(batch, MFC_MPEG2_SLICEGROUP_STATE | (8 - 2)); OUT_BCS_BATCH(batch, 0 << 31 | /* MbRateCtrlFlag */ !!is_last_slice_group << 19 | /* IsLastSliceGrp */ 1 << 17 | /* Insert Header before the first slice group data */ 1 << 16 | /* SliceData PresentFlag: always 1 */ 1 << 15 | /* TailPresentFlag: always 1 */ 0 << 14 | /* FirstSliceHdrDisabled: slice header for each slice */ !!intra_slice << 13 | /* IntraSlice */ !!intra_slice << 12 | /* IntraSliceFlag */ 0); OUT_BCS_BATCH(batch, next_y << 24 | next_x << 16 | y << 8 | x << 0 | 0); OUT_BCS_BATCH(batch, qp); /* FIXME: SliceGroupQp */ /* bitstream pointer is only loaded once for the first slice of a frame when * LoadSlicePointerFlag is 0 */ OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset); OUT_BCS_BATCH(batch, 0); /* FIXME: */ OUT_BCS_BATCH(batch, 0); /* FIXME: CorrectPoints */ OUT_BCS_BATCH(batch, 0); /* FIXME: CVxxx */ ADVANCE_BCS_BATCH(batch); } static int gen7_mfc_mpeg2_pak_object_intra(VADriverContextP ctx, struct intel_encoder_context *encoder_context, int x, int y, int first_mb_in_slice, int last_mb_in_slice, int first_mb_in_slice_group, int last_mb_in_slice_group, int mb_type, int qp_scale_code, int coded_block_pattern, unsigned char target_size_in_word, unsigned char max_size_in_word, struct intel_batchbuffer *batch) { int len_in_dwords = 9; if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, len_in_dwords); OUT_BCS_BATCH(batch, MFC_MPEG2_PAK_OBJECT | (len_in_dwords - 2)); OUT_BCS_BATCH(batch, 0 << 24 | /* PackedMvNum */ 0 << 20 | /* MvFormat */ 7 << 17 | /* CbpDcY/CbpDcU/CbpDcV */ 0 << 15 | /* TransformFlag: frame DCT */ 0 << 14 | /* FieldMbFlag */ 1 << 13 | /* IntraMbFlag */ mb_type << 8 | /* MbType: Intra */ 0 << 2 | /* SkipMbFlag */ 0 << 0 | /* InterMbMode */ 0); OUT_BCS_BATCH(batch, y << 16 | x); OUT_BCS_BATCH(batch, max_size_in_word << 24 | target_size_in_word << 16 | coded_block_pattern << 6 | /* CBP */ 0); OUT_BCS_BATCH(batch, last_mb_in_slice << 31 | first_mb_in_slice << 30 | 0 << 27 | /* EnableCoeffClamp */ last_mb_in_slice_group << 26 | 0 << 25 | /* MbSkipConvDisable */ first_mb_in_slice_group << 24 | 0 << 16 | /* MvFieldSelect */ qp_scale_code << 0 | 0); OUT_BCS_BATCH(batch, 0); /* MV[0][0] */ OUT_BCS_BATCH(batch, 0); /* MV[1][0] */ OUT_BCS_BATCH(batch, 0); /* MV[0][1] */ OUT_BCS_BATCH(batch, 0); /* MV[1][1] */ ADVANCE_BCS_BATCH(batch); return len_in_dwords; } #define MV_OFFSET_IN_WORD 112 static struct _mv_ranges { int low; /* in the unit of 1/2 pixel */ int high; /* in the unit of 1/2 pixel */ } mv_ranges[] = { {0, 0}, {-16, 15}, {-32, 31}, {-64, 63}, {-128, 127}, {-256, 255}, {-512, 511}, {-1024, 1023}, {-2048, 2047}, {-4096, 4095} }; static int mpeg2_motion_vector(int mv, int pos, int display_max, int f_code) { if (mv + pos * 16 * 2 < 0 || mv + (pos + 1) * 16 * 2 > display_max * 2) mv = 0; if (f_code > 0 && f_code < 10) { if (mv < mv_ranges[f_code].low) mv = mv_ranges[f_code].low; if (mv > mv_ranges[f_code].high) mv = mv_ranges[f_code].high; } return mv; } static int gen7_mfc_mpeg2_pak_object_inter(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, unsigned int *msg, int width_in_mbs, int height_in_mbs, int x, int y, int first_mb_in_slice, int last_mb_in_slice, int first_mb_in_slice_group, int last_mb_in_slice_group, int qp_scale_code, unsigned char target_size_in_word, unsigned char max_size_in_word, struct intel_batchbuffer *batch) { VAEncPictureParameterBufferMPEG2 *pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; int len_in_dwords = 9; short *mvptr, mvx0, mvy0, mvx1, mvy1; if (batch == NULL) batch = encoder_context->base.batch; mvptr = (short *)msg; mvx0 = mpeg2_motion_vector(mvptr[0] / 2, x, width_in_mbs * 16, pic_param->f_code[0][0]); mvy0 = mpeg2_motion_vector(mvptr[1] / 2, y, height_in_mbs * 16, pic_param->f_code[0][0]); mvx1 = mpeg2_motion_vector(mvptr[2] / 2, x, width_in_mbs * 16, pic_param->f_code[1][0]); mvy1 = mpeg2_motion_vector(mvptr[3] / 2, y, height_in_mbs * 16, pic_param->f_code[1][0]); BEGIN_BCS_BATCH(batch, len_in_dwords); OUT_BCS_BATCH(batch, MFC_MPEG2_PAK_OBJECT | (len_in_dwords - 2)); OUT_BCS_BATCH(batch, 2 << 24 | /* PackedMvNum */ 7 << 20 | /* MvFormat */ 7 << 17 | /* CbpDcY/CbpDcU/CbpDcV */ 0 << 15 | /* TransformFlag: frame DCT */ 0 << 14 | /* FieldMbFlag */ 0 << 13 | /* IntraMbFlag */ 1 << 8 | /* MbType: Frame-based */ 0 << 2 | /* SkipMbFlag */ 0 << 0 | /* InterMbMode */ 0); OUT_BCS_BATCH(batch, y << 16 | x); OUT_BCS_BATCH(batch, max_size_in_word << 24 | target_size_in_word << 16 | 0x3f << 6 | /* CBP */ 0); OUT_BCS_BATCH(batch, last_mb_in_slice << 31 | first_mb_in_slice << 30 | 0 << 27 | /* EnableCoeffClamp */ last_mb_in_slice_group << 26 | 0 << 25 | /* MbSkipConvDisable */ first_mb_in_slice_group << 24 | 0 << 16 | /* MvFieldSelect */ qp_scale_code << 0 | 0); OUT_BCS_BATCH(batch, (mvx0 & 0xFFFF) | mvy0 << 16); /* MV[0][0] */ OUT_BCS_BATCH(batch, (mvx1 & 0xFFFF) | mvy1 << 16); /* MV[1][0] */ OUT_BCS_BATCH(batch, 0); /* MV[0][1] */ OUT_BCS_BATCH(batch, 0); /* MV[1][1] */ ADVANCE_BCS_BATCH(batch); return len_in_dwords; } static void gen7_mfc_mpeg2_pipeline_header_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, struct intel_batchbuffer *slice_batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderMPEG2_SPS); if (encode_state->packed_header_data[idx]) { VAEncPackedHeaderParameterBuffer *param = NULL; unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer; unsigned int length_in_bits; assert(encode_state->packed_header_param[idx]); param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer; length_in_bits = param->bit_length; mfc_context->insert_object(ctx, encoder_context, header_data, ALIGN(length_in_bits, 32) >> 5, length_in_bits & 0x1f, 5, /* FIXME: check it */ 0, 0, 0, /* Needn't insert emulation bytes for MPEG-2 */ slice_batch); } idx = va_enc_packed_type_to_idx(VAEncPackedHeaderMPEG2_PPS); if (encode_state->packed_header_data[idx]) { VAEncPackedHeaderParameterBuffer *param = NULL; unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer; unsigned int length_in_bits; assert(encode_state->packed_header_param[idx]); param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer; length_in_bits = param->bit_length; mfc_context->insert_object(ctx, encoder_context, header_data, ALIGN(length_in_bits, 32) >> 5, length_in_bits & 0x1f, 5, /* FIXME: check it */ 0, 0, 0, /* Needn't insert emulation bytes for MPEG-2 */ slice_batch); } } static void gen7_mfc_mpeg2_pipeline_slice_group(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int slice_index, VAEncSliceParameterBufferMPEG2 *next_slice_group_param, struct intel_batchbuffer *slice_batch) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; VAEncSliceParameterBufferMPEG2 *slice_param = NULL; unsigned char tail_delimiter[] = {MPEG2_DELIMITER0, MPEG2_DELIMITER1, MPEG2_DELIMITER2, MPEG2_DELIMITER3, MPEG2_DELIMITER4, 0, 0, 0}; unsigned char section_delimiter[] = {0x0, 0x0, 0x0, 0x0}; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; int i, j; int h_start_pos, v_start_pos, h_next_start_pos, v_next_start_pos; unsigned int *msg = NULL; unsigned char *msg_ptr = NULL; slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[slice_index]->buffer; h_start_pos = slice_param->macroblock_address % width_in_mbs; v_start_pos = slice_param->macroblock_address / width_in_mbs; assert(h_start_pos + slice_param->num_macroblocks <= width_in_mbs); dri_bo_map(vme_context->vme_output.bo , 0); msg_ptr = (unsigned char *)vme_context->vme_output.bo->virtual; if (next_slice_group_param) { h_next_start_pos = next_slice_group_param->macroblock_address % width_in_mbs; v_next_start_pos = next_slice_group_param->macroblock_address / width_in_mbs; } else { h_next_start_pos = 0; v_next_start_pos = height_in_mbs; } gen7_mfc_mpeg2_slicegroup_state(ctx, encoder_context, h_start_pos, v_start_pos, h_next_start_pos, v_next_start_pos, slice_index == 0, next_slice_group_param == NULL, slice_param->is_intra_slice, slice_param->quantiser_scale_code, slice_batch); if (slice_index == 0) gen7_mfc_mpeg2_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); /* Insert '00' to make sure the header is valid */ mfc_context->insert_object(ctx, encoder_context, (unsigned int*)section_delimiter, 1, 8, /* 8bits in the last DWORD */ 1, /* 1 byte */ 1, 0, 0, slice_batch); for (i = 0; i < encode_state->slice_params_ext[slice_index]->num_elements; i++) { /* PAK for each macroblocks */ for (j = 0; j < slice_param->num_macroblocks; j++) { int h_pos = (slice_param->macroblock_address + j) % width_in_mbs; int v_pos = (slice_param->macroblock_address + j) / width_in_mbs; int first_mb_in_slice = (j == 0); int last_mb_in_slice = (j == slice_param->num_macroblocks - 1); int first_mb_in_slice_group = (i == 0 && j == 0); int last_mb_in_slice_group = (i == encode_state->slice_params_ext[slice_index]->num_elements - 1 && j == slice_param->num_macroblocks - 1); if (slice_param->is_intra_slice) { gen7_mfc_mpeg2_pak_object_intra(ctx, encoder_context, h_pos, v_pos, first_mb_in_slice, last_mb_in_slice, first_mb_in_slice_group, last_mb_in_slice_group, 0x1a, slice_param->quantiser_scale_code, 0x3f, 0, 0xff, slice_batch); } else { msg = (unsigned int *)(msg_ptr + (slice_param->macroblock_address + j) * vme_context->vme_output.size_block); if(msg[32] & INTRA_MB_FLAG_MASK) { gen7_mfc_mpeg2_pak_object_intra(ctx, encoder_context, h_pos, v_pos, first_mb_in_slice, last_mb_in_slice, first_mb_in_slice_group, last_mb_in_slice_group, 0x1a, slice_param->quantiser_scale_code, 0x3f, 0, 0xff, slice_batch); } else { gen7_mfc_mpeg2_pak_object_inter(ctx, encode_state, encoder_context, msg, width_in_mbs, height_in_mbs, h_pos, v_pos, first_mb_in_slice, last_mb_in_slice, first_mb_in_slice_group, last_mb_in_slice_group, slice_param->quantiser_scale_code, 0, 0xff, slice_batch); } } } slice_param++; } dri_bo_unmap(vme_context->vme_output.bo); /* tail data */ if (next_slice_group_param == NULL) { /* end of a picture */ mfc_context->insert_object(ctx, encoder_context, (unsigned int *)tail_delimiter, 2, 8, /* 8bits in the last DWORD */ 5, /* 5 bytes */ 1, 1, 0, slice_batch); } else { /* end of a lsice group */ mfc_context->insert_object(ctx, encoder_context, (unsigned int *)section_delimiter, 1, 8, /* 8bits in the last DWORD */ 1, /* 1 byte */ 1, 1, 0, slice_batch); } } /* * A batch buffer for all slices, including slice state, * slice insert object and slice pak object commands * */ static dri_bo * gen7_mfc_mpeg2_software_slice_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct intel_batchbuffer *batch; VAEncSliceParameterBufferMPEG2 *next_slice_group_param = NULL; dri_bo *batch_bo; int i; batch = mfc_context->aux_batchbuffer; batch_bo = batch->buffer; for (i = 0; i < encode_state->num_slice_params_ext; i++) { if (i == encode_state->num_slice_params_ext - 1) next_slice_group_param = NULL; else next_slice_group_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[i + 1]->buffer; gen7_mfc_mpeg2_pipeline_slice_group(ctx, encode_state, encoder_context, i, next_slice_group_param, batch); } intel_batchbuffer_align(batch, 8); BEGIN_BCS_BATCH(batch, 2); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END); ADVANCE_BCS_BATCH(batch); dri_bo_reference(batch_bo); intel_batchbuffer_free(batch); mfc_context->aux_batchbuffer = NULL; return batch_bo; } static void gen7_mfc_mpeg2_pipeline_picture_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; mfc_context->pipe_mode_select(ctx, MFX_FORMAT_MPEG2, encoder_context); mfc_context->set_surface_state(ctx, encoder_context); mfc_context->ind_obj_base_addr_state(ctx, encoder_context); gen6_mfc_pipe_buf_addr_state(ctx, encoder_context); gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context); gen7_mfc_mpeg2_pic_state(ctx, encoder_context, encode_state); gen7_mfc_mpeg2_qm_state(ctx, encoder_context); gen7_mfc_mpeg2_fqm_state(ctx, encoder_context); } static void gen7_mfc_mpeg2_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; dri_bo *slice_batch_bo; slice_batch_bo = gen7_mfc_mpeg2_software_slice_batchbuffer(ctx, encode_state, encoder_context); // begin programing intel_batchbuffer_start_atomic_bcs(batch, 0x4000); intel_batchbuffer_emit_mi_flush(batch); // picture level programing gen7_mfc_mpeg2_pipeline_picture_programing(ctx, encode_state, encoder_context); BEGIN_BCS_BATCH(batch, 2); OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8)); OUT_BCS_RELOC(batch, slice_batch_bo, I915_GEM_DOMAIN_COMMAND, 0, 0); ADVANCE_BCS_BATCH(batch); // end programing intel_batchbuffer_end_atomic(batch); dri_bo_unreference(slice_batch_bo); } static VAStatus gen7_mfc_mpeg2_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct object_surface *obj_surface; struct object_buffer *obj_buffer; struct i965_coded_buffer_segment *coded_buffer_segment; VAStatus vaStatus = VA_STATUS_SUCCESS; dri_bo *bo; int i; /* reconstructed surface */ obj_surface = encode_state->reconstructed_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); mfc_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(mfc_context->pre_deblocking_output.bo); mfc_context->surface_state.width = obj_surface->orig_width; mfc_context->surface_state.height = obj_surface->orig_height; mfc_context->surface_state.w_pitch = obj_surface->width; mfc_context->surface_state.h_pitch = obj_surface->height; /* forward reference */ obj_surface = encode_state->reference_objects[0]; if (obj_surface && obj_surface->bo) { mfc_context->reference_surfaces[0].bo = obj_surface->bo; dri_bo_reference(mfc_context->reference_surfaces[0].bo); } else mfc_context->reference_surfaces[0].bo = NULL; /* backward reference */ obj_surface = encode_state->reference_objects[1]; if (obj_surface && obj_surface->bo) { mfc_context->reference_surfaces[1].bo = obj_surface->bo; dri_bo_reference(mfc_context->reference_surfaces[1].bo); } else { mfc_context->reference_surfaces[1].bo = mfc_context->reference_surfaces[0].bo; if (mfc_context->reference_surfaces[1].bo) dri_bo_reference(mfc_context->reference_surfaces[1].bo); } for (i = 2; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) { mfc_context->reference_surfaces[i].bo = mfc_context->reference_surfaces[i & 1].bo; if (mfc_context->reference_surfaces[i].bo) dri_bo_reference(mfc_context->reference_surfaces[i].bo); } /* input YUV surface */ obj_surface = encode_state->input_yuv_object; mfc_context->uncompressed_picture_source.bo = obj_surface->bo; dri_bo_reference(mfc_context->uncompressed_picture_source.bo); /* coded buffer */ obj_buffer = encode_state->coded_buf_object; bo = obj_buffer->buffer_store->bo; mfc_context->mfc_indirect_pak_bse_object.bo = bo; mfc_context->mfc_indirect_pak_bse_object.offset = I965_CODEDBUFFER_HEADER_SIZE; mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN(obj_buffer->size_element - 0x1000, 0x1000); dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo); /* set the internal flag to 0 to indicate the coded size is unknown */ dri_bo_map(bo, 1); coded_buffer_segment = (struct i965_coded_buffer_segment *)bo->virtual; coded_buffer_segment->mapped = 0; coded_buffer_segment->codec = encoder_context->codec; dri_bo_unmap(bo); return vaStatus; } static VAStatus gen7_mfc_mpeg2_encode_picture(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen6_mfc_init(ctx, encode_state, encoder_context); gen7_mfc_mpeg2_prepare(ctx, encode_state, encoder_context); /*Programing bcs pipeline*/ gen7_mfc_mpeg2_pipeline_programing(ctx, encode_state, encoder_context); gen6_mfc_run(ctx, encode_state, encoder_context); return VA_STATUS_SUCCESS; } VAStatus gen7_mfc_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { VAStatus vaStatus; switch (profile) { case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context); break; case VAProfileMPEG2Simple: case VAProfileMPEG2Main: vaStatus = gen7_mfc_mpeg2_encode_picture(ctx, encode_state, encoder_context); break; /* FIXME: add for other profile */ default: vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE; break; } return vaStatus; } Bool gen7_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context)); mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS; mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data); mfc_context->gpe_context.curbe.length = 32 * 4; mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1; mfc_context->gpe_context.vfe_state.num_urb_entries = 16; mfc_context->gpe_context.vfe_state.gpgpu_mode = 0; mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1; mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1; i965_gpe_load_kernels(ctx, &mfc_context->gpe_context, gen7_mfc_kernels, NUM_MFC_KERNEL); mfc_context->pipe_mode_select = gen7_mfc_pipe_mode_select; mfc_context->set_surface_state = gen7_mfc_surface_state; mfc_context->ind_obj_base_addr_state = gen7_mfc_ind_obj_base_addr_state; mfc_context->avc_img_state = gen7_mfc_avc_img_state; mfc_context->avc_qm_state = gen7_mfc_avc_qm_state; mfc_context->avc_fqm_state = gen7_mfc_avc_fqm_state; mfc_context->insert_object = gen7_mfc_avc_insert_object; mfc_context->buffer_suface_setup = gen7_gpe_buffer_suface_setup; encoder_context->mfc_context = mfc_context; encoder_context->mfc_context_destroy = gen6_mfc_context_destroy; encoder_context->mfc_pipeline = gen7_mfc_pipeline; encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare; return True; } intel-driver-1.3.0/src/gen7_mfd.c000077500000000000000000003252631231401140700165470ustar00rootroot00000000000000/* * Copyright © 2011 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #include "sysdeps.h" #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_decoder_utils.h" #include "gen7_mfd.h" #include "intel_media.h" static const uint32_t zigzag_direct[64] = { 0, 1, 8, 16, 9, 2, 3, 10, 17, 24, 32, 25, 18, 11, 4, 5, 12, 19, 26, 33, 40, 48, 41, 34, 27, 20, 13, 6, 7, 14, 21, 28, 35, 42, 49, 56, 57, 50, 43, 36, 29, 22, 15, 23, 30, 37, 44, 51, 58, 59, 52, 45, 38, 31, 39, 46, 53, 60, 61, 54, 47, 55, 62, 63 }; static void gen7_mfd_init_avc_surface(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, struct object_surface *obj_surface) { struct i965_driver_data *i965 = i965_driver_data(ctx); GenAvcSurface *gen7_avc_surface = obj_surface->private_data; int width_in_mbs, height_in_mbs; obj_surface->free_private_data = gen_free_avc_surface; width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */ if (!gen7_avc_surface) { gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1); assert((obj_surface->size & 0x3f) == 0); obj_surface->private_data = gen7_avc_surface; } gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag && !pic_param->seq_fields.bits.direct_8x8_inference_flag); if (gen7_avc_surface->dmv_top == NULL) { gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", width_in_mbs * (height_in_mbs + 1) * 64, 0x1000); assert(gen7_avc_surface->dmv_top); } if (gen7_avc_surface->dmv_bottom_flag && gen7_avc_surface->dmv_bottom == NULL) { gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", width_in_mbs * (height_in_mbs + 1) * 64, 0x1000); assert(gen7_avc_surface->dmv_bottom); } } static void gen7_mfd_pipe_mode_select(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; assert(standard_select == MFX_FORMAT_MPEG2 || standard_select == MFX_FORMAT_AVC || standard_select == MFX_FORMAT_VC1 || standard_select == MFX_FORMAT_JPEG); BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2)); OUT_BCS_BATCH(batch, (MFX_LONG_MODE << 17) | /* Currently only support long format */ (MFD_MODE_VLD << 15) | /* VLD mode */ (0 << 10) | /* disable Stream-Out */ (gen7_mfd_context->post_deblocking_output.valid << 9) | /* Post Deblocking Output */ (gen7_mfd_context->pre_deblocking_output.valid << 8) | /* Pre Deblocking Output */ (0 << 5) | /* not in stitch mode */ (MFX_CODEC_DECODE << 4) | /* decoding mode */ (standard_select << 0)); OUT_BCS_BATCH(batch, (0 << 4) | /* terminate if AVC motion and POC table error occurs */ (0 << 3) | /* terminate if AVC mbdata error occurs */ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ (0 << 1) | (0 << 0)); OUT_BCS_BATCH(batch, 0); /* pic status/error report id */ OUT_BCS_BATCH(batch, 0); /* reserved */ ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_surface_state(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct object_surface *obj_surface = decode_state->render_object; unsigned int y_cb_offset; unsigned int y_cr_offset; assert(obj_surface); y_cb_offset = obj_surface->y_cb_offset; y_cr_offset = obj_surface->y_cr_offset; BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, ((obj_surface->orig_height - 1) << 18) | ((obj_surface->orig_width - 1) << 4)); OUT_BCS_BATCH(batch, (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */ (0 << 22) | /* surface object control state, ignored */ ((obj_surface->width - 1) << 3) | /* pitch */ (0 << 2) | /* must be 0 */ (1 << 1) | /* must be tiled */ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */ OUT_BCS_BATCH(batch, (0 << 16) | /* X offset for U(Cb), must be 0 */ (y_cb_offset << 0)); /* Y offset for U(Cb) */ OUT_BCS_BATCH(batch, (0 << 16) | /* X offset for V(Cr), must be 0 */ (y_cr_offset << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */ ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_pipe_buf_addr_state(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int i; BEGIN_BCS_BATCH(batch, 24); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2)); if (gen7_mfd_context->pre_deblocking_output.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (gen7_mfd_context->post_deblocking_output.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ if (gen7_mfd_context->intra_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); /* DW 7..22 */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { struct object_surface *obj_surface; if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID && gen7_mfd_context->reference_surface[i].obj_surface && gen7_mfd_context->reference_surface[i].obj_surface->bo) { obj_surface = gen7_mfd_context->reference_surface[i].obj_surface; OUT_BCS_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } else { OUT_BCS_BATCH(batch, 0); } } OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */ ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_ind_obj_base_addr_state(VADriverContextP ctx, dri_bo *slice_data_bo, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */ OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_bsp_buf_base_addr_state(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2)); if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (gen7_mfd_context->bitplane_read_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_qm_state(VADriverContextP ctx, int qm_type, unsigned char *qm, int qm_length, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; unsigned int qm_buffer[16]; assert(qm_length <= 16 * 4); memcpy(qm_buffer, qm, qm_length); BEGIN_BCS_BATCH(batch, 18); OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2)); OUT_BCS_BATCH(batch, qm_type << 0); intel_batchbuffer_data(batch, qm_buffer, 16 * 4); ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_avc_img_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int img_struct; int mbaff_frame_flag; unsigned int width_in_mbs, height_in_mbs; VAPictureParameterBufferH264 *pic_param; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD) img_struct = 1; else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD) img_struct = 3; else img_struct = 0; if ((img_struct & 0x1) == 0x1) { assert(pic_param->pic_fields.bits.field_pic_flag == 0x1); } else { assert(pic_param->pic_fields.bits.field_pic_flag == 0x0); } if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */ assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0); assert(pic_param->pic_fields.bits.field_pic_flag == 0); } else { assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */ } mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag && !pic_param->pic_fields.bits.field_pic_flag); width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */ /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */ assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */ pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */ assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */ BEGIN_BCS_BATCH(batch, 16); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2)); OUT_BCS_BATCH(batch, (width_in_mbs * height_in_mbs - 1)); OUT_BCS_BATCH(batch, ((height_in_mbs - 1) << 16) | ((width_in_mbs - 1) << 0)); OUT_BCS_BATCH(batch, ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) | ((pic_param->chroma_qp_index_offset & 0x1f) << 16) | (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */ (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */ (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */ (pic_param->pic_fields.bits.weighted_bipred_idc << 10) | (img_struct << 8)); OUT_BCS_BATCH(batch, (pic_param->seq_fields.bits.chroma_format_idc << 10) | (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) | ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) | (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) | (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) | (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) | (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) | (mbaff_frame_flag << 1) | (pic_param->pic_fields.bits.field_pic_flag << 0)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_avc_qm_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAIQMatrixBufferH264 *iq_matrix; VAPictureParameterBufferH264 *pic_param; if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer; else iq_matrix = &gen7_mfd_context->iq_matrix.h264; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context); gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context); if (pic_param->pic_fields.bits.transform_8x8_mode_flag) { gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context); gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context); } } static void gen7_mfd_avc_directmode_state(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct object_surface *obj_surface; GenAvcSurface *gen7_avc_surface; VAPictureH264 *va_pic; int i, j; BEGIN_BCS_BATCH(batch, 69); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2)); /* reference surfaces 0..15 */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID && gen7_mfd_context->reference_surface[i].obj_surface && gen7_mfd_context->reference_surface[i].obj_surface->private_data) { obj_surface = gen7_mfd_context->reference_surface[i].obj_surface; gen7_avc_surface = obj_surface->private_data; OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); if (gen7_avc_surface->dmv_bottom_flag == 1) OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } /* the current decoding frame/field */ va_pic = &pic_param->CurrPic; obj_surface = decode_state->render_object; assert(obj_surface->bo && obj_surface->private_data); gen7_avc_surface = obj_surface->private_data; OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); if (gen7_avc_surface->dmv_bottom_flag == 1) OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* POC List */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) { int found = 0; assert(gen7_mfd_context->reference_surface[i].obj_surface != NULL); for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) { va_pic = &pic_param->ReferenceFrames[j]; if (va_pic->flags & VA_PICTURE_H264_INVALID) continue; if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) { found = 1; break; } } assert(found == 1); assert(!(va_pic->flags & VA_PICTURE_H264_INVALID)); OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt); OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } va_pic = &pic_param->CurrPic; OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt); OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt); ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_avc_slice_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, VASliceParameterBufferH264 *next_slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos; int num_ref_idx_l0, num_ref_idx_l1; int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag && pic_param->seq_fields.bits.mb_adaptive_frame_field_flag); int first_mb_in_slice = 0, first_mb_in_next_slice = 0; int slice_type; if (slice_param->slice_type == SLICE_TYPE_I || slice_param->slice_type == SLICE_TYPE_SI) { slice_type = SLICE_TYPE_I; } else if (slice_param->slice_type == SLICE_TYPE_P || slice_param->slice_type == SLICE_TYPE_SP) { slice_type = SLICE_TYPE_P; } else { assert(slice_param->slice_type == SLICE_TYPE_B); slice_type = SLICE_TYPE_B; } if (slice_type == SLICE_TYPE_I) { assert(slice_param->num_ref_idx_l0_active_minus1 == 0); assert(slice_param->num_ref_idx_l1_active_minus1 == 0); num_ref_idx_l0 = 0; num_ref_idx_l1 = 0; } else if (slice_type == SLICE_TYPE_P) { assert(slice_param->num_ref_idx_l1_active_minus1 == 0); num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = 0; } else { num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1; } first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture; slice_hor_pos = first_mb_in_slice % width_in_mbs; slice_ver_pos = first_mb_in_slice / width_in_mbs; if (next_slice_param) { first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture; next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs; next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs; } else { next_slice_hor_pos = 0; next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag); } BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */ OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2)); OUT_BCS_BATCH(batch, slice_type); OUT_BCS_BATCH(batch, (num_ref_idx_l1 << 24) | (num_ref_idx_l0 << 16) | (slice_param->chroma_log2_weight_denom << 8) | (slice_param->luma_log2_weight_denom << 0)); OUT_BCS_BATCH(batch, (slice_param->direct_spatial_mv_pred_flag << 29) | (slice_param->disable_deblocking_filter_idc << 27) | (slice_param->cabac_init_idc << 24) | ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) | ((slice_param->slice_beta_offset_div2 & 0xf) << 8) | ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0)); OUT_BCS_BATCH(batch, (slice_ver_pos << 24) | (slice_hor_pos << 16) | (first_mb_in_slice << 0)); OUT_BCS_BATCH(batch, (next_slice_ver_pos << 16) | (next_slice_hor_pos << 0)); OUT_BCS_BATCH(batch, (next_slice_param == NULL) << 19); /* last slice flag */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static inline void gen7_mfd_avc_ref_idx_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen7_mfd_context *gen7_mfd_context) { gen6_send_avc_ref_idx_state( gen7_mfd_context->base.batch, slice_param, gen7_mfd_context->reference_surface ); } static void gen7_mfd_avc_weightoffset_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int i, j, num_weight_offset_table = 0; short weightoffsets[32 * 6]; if ((slice_param->slice_type == SLICE_TYPE_P || slice_param->slice_type == SLICE_TYPE_SP) && (pic_param->pic_fields.bits.weighted_pred_flag == 1)) { num_weight_offset_table = 1; } if ((slice_param->slice_type == SLICE_TYPE_B) && (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) { num_weight_offset_table = 2; } for (i = 0; i < num_weight_offset_table; i++) { BEGIN_BCS_BATCH(batch, 98); OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2)); OUT_BCS_BATCH(batch, i); if (i == 0) { for (j = 0; j < 32; j++) { weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j]; weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j]; weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0]; weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0]; weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1]; weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1]; } } else { for (j = 0; j < 32; j++) { weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j]; weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j]; weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0]; weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0]; weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1]; weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1]; } } intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets)); ADVANCE_BCS_BATCH(batch); } } static void gen7_mfd_avc_bsd_object(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, dri_bo *slice_data_bo, VASliceParameterBufferH264 *next_slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; unsigned int slice_data_bit_offset; slice_data_bit_offset = avc_get_first_mb_bit_offset( slice_data_bo, slice_param, pic_param->pic_fields.bits.entropy_coding_mode_flag ); /* the input bitsteam format on GEN7 differs from GEN6 */ BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2)); OUT_BCS_BATCH(batch, (slice_param->slice_data_size - slice_param->slice_data_offset)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset); OUT_BCS_BATCH(batch, (0 << 31) | (0 << 14) | (0 << 12) | (0 << 10) | (0 << 8)); OUT_BCS_BATCH(batch, ((slice_data_bit_offset >> 3) << 16) | (1 << 7) | (0 << 5) | (0 << 4) | ((next_slice_param == NULL) << 3) | /* LastSlice Flag */ (slice_data_bit_offset & 0x7)); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static inline void gen7_mfd_avc_context_init( VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context ) { /* Initialize flat scaling lists */ avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264); } static void gen7_mfd_avc_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAPictureParameterBufferH264 *pic_param; VASliceParameterBufferH264 *slice_param; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *bo; int i, j, enable_avc_ildb = 0; unsigned int width_in_mbs, height_in_mbs; for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); assert((slice_param->slice_type == SLICE_TYPE_I) || (slice_param->slice_type == SLICE_TYPE_SI) || (slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP) || (slice_param->slice_type == SLICE_TYPE_B)); if (slice_param->disable_deblocking_filter_idc != 1) { enable_avc_ildb = 1; break; } slice_param++; } } assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; intel_update_avc_frame_store_index(ctx, decode_state, pic_param, gen7_mfd_context->reference_surface); width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */ assert(height_in_mbs > 0 && height_in_mbs <= 256); /* Current decoded picture */ obj_surface = decode_state->render_object; obj_surface->flags &= ~SURFACE_REF_DIS_MASK; obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0); i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); /* initial uv component for YUV400 case */ if (pic_param->seq_fields.bits.chroma_format_idc == 0) { unsigned int uv_offset = obj_surface->width * obj_surface->height; unsigned int uv_size = obj_surface->width * obj_surface->height / 2; drm_intel_gem_bo_map_gtt(obj_surface->bo); memset(obj_surface->bo->virtual + uv_offset, 0x80, uv_size); drm_intel_gem_bo_unmap_gtt(obj_surface->bo); } gen7_mfd_init_avc_surface(ctx, pic_param, obj_surface); dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb; dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb; dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", width_in_mbs * 64, 0x1000); assert(bo); gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "deblocking filter row store", width_in_mbs * 64 * 4, 0x1000); assert(bo); gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 64 * 2, 0x1000); assert(bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "mpr row store", width_in_mbs * 64 * 2, 0x1000); assert(bo); gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1; gen7_mfd_context->bitplane_read_buffer.valid = 0; } static void gen7_mfd_avc_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferH264 *pic_param; VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; gen7_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context); gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context); gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context); gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context); gen7_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context); gen7_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); assert((slice_param->slice_type == SLICE_TYPE_I) || (slice_param->slice_type == SLICE_TYPE_SI) || (slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP) || (slice_param->slice_type == SLICE_TYPE_B)); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen7_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen7_mfd_context); gen7_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context); gen7_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context); gen7_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context); gen7_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static void gen7_mfd_mpeg2_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAPictureParameterBufferMPEG2 *pic_param; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *bo; unsigned int width_in_mbs; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16; mpeg2_set_reference_surfaces( ctx, gen7_mfd_context->reference_surface, decode_state, pic_param ); /* Current decoded picture */ obj_surface = decode_state->render_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = 1; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 96, 0x1000); assert(bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; gen7_mfd_context->post_deblocking_output.valid = 0; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0; gen7_mfd_context->bitplane_read_buffer.valid = 0; } static void gen7_mfd_mpeg2_pic_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data * const i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferMPEG2 *pic_param; unsigned int slice_concealment_disable_bit = 0; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; if (IS_HASWELL(i965->intel.device_id)) { /* XXX: disable concealment for now */ slice_concealment_disable_bit = 1; } BEGIN_BCS_BATCH(batch, 13); OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2)); OUT_BCS_BATCH(batch, (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */ ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */ ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */ ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */ pic_param->picture_coding_extension.bits.intra_dc_precision << 14 | pic_param->picture_coding_extension.bits.picture_structure << 12 | pic_param->picture_coding_extension.bits.top_field_first << 11 | pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 | pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 | pic_param->picture_coding_extension.bits.q_scale_type << 8 | pic_param->picture_coding_extension.bits.intra_vlc_format << 7 | pic_param->picture_coding_extension.bits.alternate_scan << 6); OUT_BCS_BATCH(batch, pic_param->picture_coding_type << 9); OUT_BCS_BATCH(batch, (slice_concealment_disable_bit << 31) | ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 | ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_mpeg2_qm_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2; int i, j; /* Update internal QM state */ if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) { VAIQMatrixBufferMPEG2 * const iq_matrix = (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer; if (gen_iq_matrix->load_intra_quantiser_matrix == -1 || iq_matrix->load_intra_quantiser_matrix) { gen_iq_matrix->load_intra_quantiser_matrix = iq_matrix->load_intra_quantiser_matrix; if (iq_matrix->load_intra_quantiser_matrix) { for (j = 0; j < 64; j++) gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] = iq_matrix->intra_quantiser_matrix[j]; } } if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 || iq_matrix->load_non_intra_quantiser_matrix) { gen_iq_matrix->load_non_intra_quantiser_matrix = iq_matrix->load_non_intra_quantiser_matrix; if (iq_matrix->load_non_intra_quantiser_matrix) { for (j = 0; j < 64; j++) gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] = iq_matrix->non_intra_quantiser_matrix[j]; } } } /* Commit QM state to HW */ for (i = 0; i < 2; i++) { unsigned char *qm = NULL; int qm_type; if (i == 0) { if (gen_iq_matrix->load_intra_quantiser_matrix) { qm = gen_iq_matrix->intra_quantiser_matrix; qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX; } } else { if (gen_iq_matrix->load_non_intra_quantiser_matrix) { qm = gen_iq_matrix->non_intra_quantiser_matrix; qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX; } } if (!qm) continue; gen7_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context); } } static void gen7_mfd_mpeg2_bsd_object(VADriverContextP ctx, VAPictureParameterBufferMPEG2 *pic_param, VASliceParameterBufferMPEG2 *slice_param, VASliceParameterBufferMPEG2 *next_slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data * const i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16; int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0; if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD || pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD) is_field_pic = 1; is_field_pic_wa = is_field_pic && gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0; vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa); hpos0 = slice_param->slice_horizontal_position; if (next_slice_param == NULL) { vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic); hpos1 = 0; } else { vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa); hpos1 = next_slice_param->slice_horizontal_position; } mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0); BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2)); OUT_BCS_BATCH(batch, slice_param->slice_data_size - (slice_param->macroblock_offset >> 3)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3)); OUT_BCS_BATCH(batch, hpos0 << 24 | vpos0 << 16 | mb_count << 8 | (next_slice_param == NULL) << 5 | (next_slice_param == NULL) << 3 | (slice_param->macroblock_offset & 0x7)); OUT_BCS_BATCH(batch, (slice_param->quantiser_scale_code << 24) | (IS_HASWELL(i965->intel.device_id) ? (vpos1 << 8 | hpos1) : 0)); ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_mpeg2_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferMPEG2 *pic_param; VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; gen7_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context); gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context); gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context); gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context); gen7_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context); gen7_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context); if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0) gen7_mfd_context->wa_mpeg2_slice_vertical_position = mpeg2_wa_slice_vertical_position(decode_state, pic_param); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen7_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static const int va_to_gen7_vc1_pic_type[5] = { GEN7_VC1_I_PICTURE, GEN7_VC1_P_PICTURE, GEN7_VC1_B_PICTURE, GEN7_VC1_BI_PICTURE, GEN7_VC1_P_PICTURE, }; static const int va_to_gen7_vc1_mv[4] = { 1, /* 1-MV */ 2, /* 1-MV half-pel */ 3, /* 1-MV half-pef bilinear */ 0, /* Mixed MV */ }; static const int b_picture_scale_factor[21] = { 128, 85, 170, 64, 192, 51, 102, 153, 204, 43, 215, 37, 74, 111, 148, 185, 222, 32, 96, 160, 224, }; static const int va_to_gen7_vc1_condover[3] = { 0, 2, 3 }; static const int va_to_gen7_vc1_profile[4] = { GEN7_VC1_SIMPLE_PROFILE, GEN7_VC1_MAIN_PROFILE, GEN7_VC1_RESERVED_PROFILE, GEN7_VC1_ADVANCED_PROFILE }; static void gen7_mfd_free_vc1_surface(void **data) { struct gen7_vc1_surface *gen7_vc1_surface = *data; if (!gen7_vc1_surface) return; dri_bo_unreference(gen7_vc1_surface->dmv); free(gen7_vc1_surface); *data = NULL; } static void gen7_mfd_init_vc1_surface(VADriverContextP ctx, VAPictureParameterBufferVC1 *pic_param, struct object_surface *obj_surface) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data; int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16; obj_surface->free_private_data = gen7_mfd_free_vc1_surface; if (!gen7_vc1_surface) { gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1); assert((obj_surface->size & 0x3f) == 0); obj_surface->private_data = gen7_vc1_surface; } gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type; if (gen7_vc1_surface->dmv == NULL) { gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", width_in_mbs * height_in_mbs * 64, 0x1000); } } static void gen7_mfd_vc1_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAPictureParameterBufferVC1 *pic_param; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *bo; int width_in_mbs; int picture_type; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; picture_type = pic_param->picture_fields.bits.picture_type; intel_update_vc1_frame_store_index(ctx, decode_state, pic_param, gen7_mfd_context->reference_surface); /* Current decoded picture */ obj_surface = decode_state->render_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); gen7_mfd_init_vc1_surface(ctx, pic_param, obj_surface); dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter; dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter; dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", width_in_mbs * 64, 0x1000); assert(bo); gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "deblocking filter row store", width_in_mbs * 7 * 64, 0x1000); assert(bo); gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 96, 0x1000); assert(bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0; gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value; dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo); if (gen7_mfd_context->bitplane_read_buffer.valid) { int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16; int bitplane_width = ALIGN(width_in_mbs, 2) / 2; int src_w, src_h; uint8_t *src = NULL, *dst = NULL; assert(decode_state->bit_plane->buffer); src = decode_state->bit_plane->buffer; bo = dri_bo_alloc(i965->intel.bufmgr, "VC-1 Bitplane", bitplane_width * height_in_mbs, 0x1000); assert(bo); gen7_mfd_context->bitplane_read_buffer.bo = bo; dri_bo_map(bo, True); assert(bo->virtual); dst = bo->virtual; for (src_h = 0; src_h < height_in_mbs; src_h++) { for(src_w = 0; src_w < width_in_mbs; src_w++) { int src_index, dst_index; int src_shift; uint8_t src_value; src_index = (src_h * width_in_mbs + src_w) / 2; src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4; src_value = ((src[src_index] >> src_shift) & 0xf); if (picture_type == GEN7_VC1_SKIPPED_PICTURE){ src_value |= 0x2; } dst_index = src_w / 2; dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4)); } if (src_w & 1) dst[src_w / 2] >>= 4; dst += bitplane_width; } dri_bo_unmap(bo); } else gen7_mfd_context->bitplane_read_buffer.bo = NULL; } static void gen7_mfd_vc1_pic_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferVC1 *pic_param; struct object_surface *obj_surface; int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq; int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel; int unified_mv_mode; int ref_field_pic_polarity = 0; int scale_factor = 0; int trans_ac_y = 0; int dmv_surface_valid = 0; int brfd = 0; int fcm = 0; int picture_type; int profile; int overlap; int interpolation_mode = 0; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile]; dquant = pic_param->pic_quantizer_fields.bits.dquant; dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame; dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile; dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge; dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge; dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level; alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer; if (dquant == 0) { alt_pquant_config = 0; alt_pquant_edge_mask = 0; } else if (dquant == 2) { alt_pquant_config = 1; alt_pquant_edge_mask = 0xf; } else { assert(dquant == 1); if (dquantfrm == 0) { alt_pquant_config = 0; alt_pquant_edge_mask = 0; alt_pq = 0; } else { assert(dquantfrm == 1); alt_pquant_config = 1; switch (dqprofile) { case 3: if (dqbilevel == 0) { alt_pquant_config = 2; alt_pquant_edge_mask = 0; } else { assert(dqbilevel == 1); alt_pquant_config = 3; alt_pquant_edge_mask = 0; } break; case 0: alt_pquant_edge_mask = 0xf; break; case 1: if (dqdbedge == 3) alt_pquant_edge_mask = 0x9; else alt_pquant_edge_mask = (0x3 << dqdbedge); break; case 2: alt_pquant_edge_mask = (0x1 << dqsbedge); break; default: assert(0); } } } if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) { assert(pic_param->mv_fields.bits.mv_mode2 < 4); unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2]; } else { assert(pic_param->mv_fields.bits.mv_mode < 4); unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode]; } if (pic_param->sequence_fields.bits.interlace == 1 && pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */ /* FIXME: calculate reference field picture polarity */ assert(0); ref_field_pic_polarity = 0; } if (pic_param->b_picture_fraction < 21) scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction]; picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type]; if (profile == GEN7_VC1_ADVANCED_PROFILE && picture_type == GEN7_VC1_I_PICTURE) picture_type = GEN7_VC1_BI_PICTURE; if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */ trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2; else { trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1; /* * 8.3.6.2.1 Transform Type Selection * If variable-sized transform coding is not enabled, * then the 8x8 transform shall be used for all blocks. * it is also MFX_VC1_PIC_STATE requirement. */ if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) { pic_param->transform_fields.bits.mb_level_transform_type_flag = 1; pic_param->transform_fields.bits.frame_level_transform_type = 0; } } if (picture_type == GEN7_VC1_B_PICTURE) { struct gen7_vc1_surface *gen7_vc1_surface = NULL; obj_surface = decode_state->reference_objects[1]; if (obj_surface) gen7_vc1_surface = obj_surface->private_data; if (!gen7_vc1_surface || (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE || va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE)) dmv_surface_valid = 0; else dmv_surface_valid = 1; } assert(pic_param->picture_fields.bits.frame_coding_mode < 3); if (pic_param->picture_fields.bits.frame_coding_mode < 2) fcm = pic_param->picture_fields.bits.frame_coding_mode; else { if (pic_param->picture_fields.bits.top_field_first) fcm = 2; else fcm = 3; } if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */ brfd = pic_param->reference_fields.bits.reference_distance; brfd = (scale_factor * brfd) >> 8; brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1; if (brfd < 0) brfd = 0; } overlap = 0; if (profile != GEN7_VC1_ADVANCED_PROFILE){ if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 && pic_param->picture_fields.bits.picture_type != GEN7_VC1_B_PICTURE) { overlap = 1; } }else { if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_P_PICTURE && pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){ overlap = 1; } if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_I_PICTURE || pic_param->picture_fields.bits.picture_type == GEN7_VC1_BI_PICTURE){ if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){ overlap = 1; } else if (va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 2 || va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 3) { overlap = 1; } } } assert(pic_param->conditional_overlap_flag < 3); assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */ if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear || (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation && pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear)) interpolation_mode = 9; /* Half-pel bilinear */ else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel || (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation && pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel)) interpolation_mode = 1; /* Half-pel bicubic */ else interpolation_mode = 0; /* Quarter-pel bicubic */ BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2)); OUT_BCS_BATCH(batch, (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) | ((ALIGN(pic_param->coded_width, 16) / 16) - 1)); OUT_BCS_BATCH(batch, ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 | dmv_surface_valid << 15 | (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */ pic_param->rounding_control << 13 | pic_param->sequence_fields.bits.syncmarker << 12 | interpolation_mode << 8 | 0 << 7 | /* FIXME: scale up or down ??? */ pic_param->range_reduction_frame << 6 | pic_param->entrypoint_fields.bits.loopfilter << 5 | overlap << 4 | !pic_param->picture_fields.bits.is_first_field << 3 | (pic_param->sequence_fields.bits.profile == 3) << 0); OUT_BCS_BATCH(batch, va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 | picture_type << 26 | fcm << 24 | alt_pq << 16 | pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 | scale_factor << 0); OUT_BCS_BATCH(batch, unified_mv_mode << 28 | pic_param->mv_fields.bits.four_mv_switch << 27 | pic_param->fast_uvmc_flag << 26 | ref_field_pic_polarity << 25 | pic_param->reference_fields.bits.num_reference_pictures << 24 | pic_param->reference_fields.bits.reference_distance << 20 | pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */ pic_param->mv_fields.bits.extended_dmv_range << 10 | pic_param->mv_fields.bits.extended_mv_range << 8 | alt_pquant_edge_mask << 4 | alt_pquant_config << 2 | pic_param->pic_quantizer_fields.bits.half_qp << 1 | pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0); OUT_BCS_BATCH(batch, !!pic_param->bitplane_present.value << 31 | !pic_param->bitplane_present.flags.bp_forward_mb << 30 | !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 | !pic_param->bitplane_present.flags.bp_skip_mb << 28 | !pic_param->bitplane_present.flags.bp_direct_mb << 27 | !pic_param->bitplane_present.flags.bp_overflags << 26 | !pic_param->bitplane_present.flags.bp_ac_pred << 25 | !pic_param->bitplane_present.flags.bp_field_tx << 24 | pic_param->mv_fields.bits.mv_table << 20 | pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 | pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 | pic_param->transform_fields.bits.frame_level_transform_type << 12 | pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 | pic_param->mb_mode_table << 8 | trans_ac_y << 6 | pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 | pic_param->transform_fields.bits.intra_transform_dc_table << 3 | pic_param->cbp_table << 0); ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_vc1_pred_pipe_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferVC1 *pic_param; int intensitycomp_single; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation); BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0 << 14 | /* FIXME: double ??? */ 0 << 12 | intensitycomp_single << 10 | intensitycomp_single << 8 | 0 << 4 | /* FIXME: interlace mode */ 0); OUT_BCS_BATCH(batch, pic_param->luma_shift << 16 | pic_param->luma_scale << 0); /* FIXME: Luma Scaling */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_vc1_directmode_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct object_surface *obj_surface; dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL; obj_surface = decode_state->render_object; if (obj_surface && obj_surface->private_data) { dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv; } obj_surface = decode_state->reference_objects[1]; if (obj_surface && obj_surface->private_data) { dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv; } BEGIN_BCS_BATCH(batch, 3); OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2)); if (dmv_write_buffer) OUT_BCS_RELOC(batch, dmv_write_buffer, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); if (dmv_read_buffer) OUT_BCS_RELOC(batch, dmv_read_buffer, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static int gen7_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile) { int out_slice_data_bit_offset; int slice_header_size = in_slice_data_bit_offset / 8; int i, j; if (profile != 3) out_slice_data_bit_offset = in_slice_data_bit_offset; else { for (i = 0, j = 0; i < slice_header_size; i++, j++) { if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) { i++, j += 2; } } out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8; } return out_slice_data_bit_offset; } static void gen7_mfd_vc1_bsd_object(VADriverContextP ctx, VAPictureParameterBufferVC1 *pic_param, VASliceParameterBufferVC1 *slice_param, VASliceParameterBufferVC1 *next_slice_param, dri_bo *slice_data_bo, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int next_slice_start_vert_pos; int macroblock_offset; uint8_t *slice_data = NULL; dri_bo_map(slice_data_bo, 0); slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset); macroblock_offset = gen7_mfd_vc1_get_macroblock_bit_offset(slice_data, slice_param->macroblock_offset, pic_param->sequence_fields.bits.profile); dri_bo_unmap(slice_data_bo); if (next_slice_param) next_slice_start_vert_pos = next_slice_param->slice_vertical_position; else next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16; BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2)); OUT_BCS_BATCH(batch, slice_param->slice_data_size - (macroblock_offset >> 3)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset + (macroblock_offset >> 3)); OUT_BCS_BATCH(batch, slice_param->slice_vertical_position << 16 | next_slice_start_vert_pos << 0); OUT_BCS_BATCH(batch, (macroblock_offset & 0x7)); ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_vc1_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferVC1 *pic_param; VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; gen7_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context); gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context); gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context); gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context); gen7_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context); gen7_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context); gen7_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen7_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static void gen7_mfd_jpeg_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct object_surface *obj_surface; VAPictureParameterBufferJPEGBaseline *pic_param; int subsampling = SUBSAMPLE_YUV420; int fourcc = VA_FOURCC('I', 'M', 'C', '3'); pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer; if (pic_param->num_components == 1) { subsampling = SUBSAMPLE_YUV400; fourcc = VA_FOURCC('Y', '8', '0', '0'); } else if (pic_param->num_components == 3) { int h1 = pic_param->components[0].h_sampling_factor; int h2 = pic_param->components[1].h_sampling_factor; int h3 = pic_param->components[2].h_sampling_factor; int v1 = pic_param->components[0].v_sampling_factor; int v2 = pic_param->components[1].v_sampling_factor; int v3 = pic_param->components[2].v_sampling_factor; if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV420; fourcc = VA_FOURCC('I', 'M', 'C', '3'); } else if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV422H; fourcc = VA_FOURCC('4', '2', '2', 'H'); } else if (h1 == 1 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV444; fourcc = VA_FOURCC('4', '4', '4', 'P'); } else if (h1 == 4 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV411; fourcc = VA_FOURCC('4', '1', '1', 'P'); } else if (h1 == 1 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV422V; fourcc = VA_FOURCC('4', '2', '2', 'V'); } else if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 2 && v3 == 2) { subsampling = SUBSAMPLE_YUV422H; fourcc = VA_FOURCC('4', '2', '2', 'H'); } else if (h2 == 2 && h2 == 2 && h3 == 2 && v1 == 2 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV422V; fourcc = VA_FOURCC('4', '2', '2', 'V'); } else assert(0); } else { assert(0); } /* Current decoded picture */ obj_surface = decode_state->render_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, fourcc, subsampling); dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = 1; gen7_mfd_context->post_deblocking_output.bo = NULL; gen7_mfd_context->post_deblocking_output.valid = 0; gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0; gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0; gen7_mfd_context->bitplane_read_buffer.bo = NULL; gen7_mfd_context->bitplane_read_buffer.valid = 0; } static const int va_to_gen7_jpeg_rotation[4] = { GEN7_JPEG_ROTATION_0, GEN7_JPEG_ROTATION_90, GEN7_JPEG_ROTATION_180, GEN7_JPEG_ROTATION_270 }; static void gen7_mfd_jpeg_pic_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferJPEGBaseline *pic_param; int chroma_type = GEN7_YUV420; int frame_width_in_blks; int frame_height_in_blks; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer; if (pic_param->num_components == 1) chroma_type = GEN7_YUV400; else if (pic_param->num_components == 3) { int h1 = pic_param->components[0].h_sampling_factor; int h2 = pic_param->components[1].h_sampling_factor; int h3 = pic_param->components[2].h_sampling_factor; int v1 = pic_param->components[0].v_sampling_factor; int v2 = pic_param->components[1].v_sampling_factor; int v3 = pic_param->components[2].v_sampling_factor; if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV420; else if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV422H_2Y; else if (h1 == 1 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV444; else if (h1 == 4 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV411; else if (h1 == 1 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV422V_2Y; else if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 2 && v3 == 2) chroma_type = GEN7_YUV422H_4Y; else if (h2 == 2 && h2 == 2 && h3 == 2 && v1 == 2 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV422V_4Y; else assert(0); } if (chroma_type == GEN7_YUV400 || chroma_type == GEN7_YUV444 || chroma_type == GEN7_YUV422V_2Y) { frame_width_in_blks = ((pic_param->picture_width + 7) / 8); frame_height_in_blks = ((pic_param->picture_height + 7) / 8); } else if (chroma_type == GEN7_YUV411) { frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4; frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4; } else { frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2; frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2; } BEGIN_BCS_BATCH(batch, 3); OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2)); OUT_BCS_BATCH(batch, (va_to_gen7_jpeg_rotation[0] << 4) | /* without rotation */ (chroma_type << 0)); OUT_BCS_BATCH(batch, ((frame_height_in_blks - 1) << 16) | /* FrameHeightInBlks */ ((frame_width_in_blks - 1) << 0)); /* FrameWidthInBlks */ ADVANCE_BCS_BATCH(batch); } static const int va_to_gen7_jpeg_hufftable[2] = { MFX_HUFFTABLE_ID_Y, MFX_HUFFTABLE_ID_UV }; static void gen7_mfd_jpeg_huff_table_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context, int num_tables) { VAHuffmanTableBufferJPEGBaseline *huffman_table; struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int index; if (!decode_state->huffman_table || !decode_state->huffman_table->buffer) return; huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer; for (index = 0; index < num_tables; index++) { int id = va_to_gen7_jpeg_hufftable[index]; if (!huffman_table->load_huffman_table[index]) continue; BEGIN_BCS_BATCH(batch, 53); OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2)); OUT_BCS_BATCH(batch, id); intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12); intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12); intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16); intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164); ADVANCE_BCS_BATCH(batch); } } static const int va_to_gen7_jpeg_qm[5] = { -1, MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX, MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX, MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX, MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX }; static void gen7_mfd_jpeg_qm_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAPictureParameterBufferJPEGBaseline *pic_param; VAIQMatrixBufferJPEGBaseline *iq_matrix; int index; if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer) return; iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer; pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer; assert(pic_param->num_components <= 3); for (index = 0; index < pic_param->num_components; index++) { int id = pic_param->components[index].component_id - pic_param->components[0].component_id + 1; int qm_type; unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector]; unsigned char raster_qm[64]; int j; if (id > 4 || id < 1) continue; if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector]) continue; qm_type = va_to_gen7_jpeg_qm[id]; for (j = 0; j < 64; j++) raster_qm[zigzag_direct[j]] = qm[j]; gen7_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context); } } static void gen7_mfd_jpeg_bsd_object(VADriverContextP ctx, VAPictureParameterBufferJPEGBaseline *pic_param, VASliceParameterBufferJPEGBaseline *slice_param, VASliceParameterBufferJPEGBaseline *next_slice_param, dri_bo *slice_data_bo, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int scan_component_mask = 0; int i; assert(slice_param->num_components > 0); assert(slice_param->num_components < 4); assert(slice_param->num_components <= pic_param->num_components); for (i = 0; i < slice_param->num_components; i++) { switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) { case 1: scan_component_mask |= (1 << 0); break; case 2: scan_component_mask |= (1 << 1); break; case 3: scan_component_mask |= (1 << 2); break; default: assert(0); break; } } BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2)); OUT_BCS_BATCH(batch, slice_param->slice_data_size); OUT_BCS_BATCH(batch, slice_param->slice_data_offset); OUT_BCS_BATCH(batch, slice_param->slice_horizontal_position << 16 | slice_param->slice_vertical_position << 0); OUT_BCS_BATCH(batch, ((slice_param->num_components != 1) << 30) | /* interleaved */ (scan_component_mask << 27) | /* scan components */ (0 << 26) | /* disable interrupt allowed */ (slice_param->num_mcus << 0)); /* MCU count */ OUT_BCS_BATCH(batch, (slice_param->restart_interval << 0)); /* RestartInterval */ ADVANCE_BCS_BATCH(batch); } /* Workaround for JPEG decoding on Ivybridge */ VAStatus i965_DestroySurfaces(VADriverContextP ctx, VASurfaceID *surface_list, int num_surfaces); VAStatus i965_CreateSurfaces(VADriverContextP ctx, int width, int height, int format, int num_surfaces, VASurfaceID *surfaces); static struct { int width; int height; unsigned char data[32]; int data_size; int data_bit_offset; int qp; } gen7_jpeg_wa_clip = { 16, 16, { 0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c, 0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00 }, 14, 40, 28, }; static void gen7_jpeg_wa_init(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAStatus status; struct object_surface *obj_surface; if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE) i965_DestroySurfaces(ctx, &gen7_mfd_context->jpeg_wa_surface_id, 1); status = i965_CreateSurfaces(ctx, gen7_jpeg_wa_clip.width, gen7_jpeg_wa_clip.height, VA_RT_FORMAT_YUV420, 1, &gen7_mfd_context->jpeg_wa_surface_id); assert(status == VA_STATUS_SUCCESS); obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id); assert(obj_surface); i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420); gen7_mfd_context->jpeg_wa_surface_object = obj_surface; if (!gen7_mfd_context->jpeg_wa_slice_data_bo) { gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr, "JPEG WA data", 0x1000, 0x1000); dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo, 0, gen7_jpeg_wa_clip.data_size, gen7_jpeg_wa_clip.data); } } static void gen7_jpeg_wa_pipe_mode_select(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2)); OUT_BCS_BATCH(batch, (MFX_LONG_MODE << 17) | /* Currently only support long format */ (MFD_MODE_VLD << 15) | /* VLD mode */ (0 << 10) | /* disable Stream-Out */ (0 << 9) | /* Post Deblocking Output */ (1 << 8) | /* Pre Deblocking Output */ (0 << 5) | /* not in stitch mode */ (MFX_CODEC_DECODE << 4) | /* decoding mode */ (MFX_FORMAT_AVC << 0)); OUT_BCS_BATCH(batch, (0 << 4) | /* terminate if AVC motion and POC table error occurs */ (0 << 3) | /* terminate if AVC mbdata error occurs */ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ (0 << 1) | (0 << 0)); OUT_BCS_BATCH(batch, 0); /* pic status/error report id */ OUT_BCS_BATCH(batch, 0); /* reserved */ ADVANCE_BCS_BATCH(batch); } static void gen7_jpeg_wa_surface_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object; struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, ((obj_surface->orig_width - 1) << 18) | ((obj_surface->orig_height - 1) << 4)); OUT_BCS_BATCH(batch, (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ (1 << 27) | /* interleave chroma, set to 0 for JPEG */ (0 << 22) | /* surface object control state, ignored */ ((obj_surface->width - 1) << 3) | /* pitch */ (0 << 2) | /* must be 0 */ (1 << 1) | /* must be tiled */ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */ OUT_BCS_BATCH(batch, (0 << 16) | /* X offset for U(Cb), must be 0 */ (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */ OUT_BCS_BATCH(batch, (0 << 16) | /* X offset for V(Cr), must be 0 */ (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */ ADVANCE_BCS_BATCH(batch); } static void gen7_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object; struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; dri_bo *intra_bo; int i; intra_bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", 128 * 64, 0x1000); BEGIN_BCS_BATCH(batch, 24); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2)); OUT_BCS_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); /* post deblocking */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_RELOC(batch, intra_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); /* DW 7..22 */ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */ ADVANCE_BCS_BATCH(batch); dri_bo_unreference(intra_bo); } static void gen7_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; dri_bo *bsd_mpc_bo, *mpr_bo; bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", 11520, /* 1.5 * 120 * 64 */ 0x1000); mpr_bo = dri_bo_alloc(i965->intel.bufmgr, "mpr row store", 7680, /* 1. 0 * 120 * 64 */ 0x1000); BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2)); OUT_BCS_RELOC(batch, bsd_mpc_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_RELOC(batch, mpr_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); dri_bo_unreference(bsd_mpc_bo); dri_bo_unreference(mpr_bo); } static void gen7_jpeg_wa_avc_qm_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { } static void gen7_jpeg_wa_avc_img_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int img_struct = 0; int mbaff_frame_flag = 0; unsigned int width_in_mbs = 1, height_in_mbs = 1; BEGIN_BCS_BATCH(batch, 16); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2)); OUT_BCS_BATCH(batch, (width_in_mbs * height_in_mbs - 1)); OUT_BCS_BATCH(batch, ((height_in_mbs - 1) << 16) | ((width_in_mbs - 1) << 0)); OUT_BCS_BATCH(batch, (0 << 24) | (0 << 16) | (0 << 14) | (0 << 13) | (0 << 12) | /* differ from GEN6 */ (0 << 10) | (img_struct << 8)); OUT_BCS_BATCH(batch, (1 << 10) | /* 4:2:0 */ (1 << 7) | /* CABAC */ (0 << 6) | (0 << 5) | (0 << 4) | (0 << 3) | (1 << 2) | (mbaff_frame_flag << 1) | (0 << 0)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_jpeg_wa_avc_directmode_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int i; BEGIN_BCS_BATCH(batch, 69); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2)); /* reference surfaces 0..15 */ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { OUT_BCS_BATCH(batch, 0); /* top */ OUT_BCS_BATCH(batch, 0); /* bottom */ } /* the current decoding frame/field */ OUT_BCS_BATCH(batch, 0); /* top */ OUT_BCS_BATCH(batch, 0); /* bottom */ /* POC List */ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); OUT_BCS_RELOC(batch, gen7_mfd_context->jpeg_wa_slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_jpeg_wa_avc_bsd_object(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; /* the input bitsteam format on GEN7 differs from GEN6 */ BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2)); OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, (0 << 31) | (0 << 14) | (0 << 12) | (0 << 10) | (0 << 8)); OUT_BCS_BATCH(batch, ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) | (0 << 5) | (0 << 4) | (1 << 3) | /* LastSlice Flag */ (gen7_jpeg_wa_clip.data_bit_offset & 0x7)); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_jpeg_wa_avc_slice_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1; int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0; int first_mb_in_slice = 0; int slice_type = SLICE_TYPE_I; BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2)); OUT_BCS_BATCH(batch, slice_type); OUT_BCS_BATCH(batch, (num_ref_idx_l1 << 24) | (num_ref_idx_l0 << 16) | (0 << 8) | (0 << 0)); OUT_BCS_BATCH(batch, (0 << 29) | (1 << 27) | /* disable Deblocking */ (0 << 24) | (gen7_jpeg_wa_clip.qp << 16) | (0 << 8) | (0 << 0)); OUT_BCS_BATCH(batch, (slice_ver_pos << 24) | (slice_hor_pos << 16) | (first_mb_in_slice << 0)); OUT_BCS_BATCH(batch, (next_slice_ver_pos << 16) | (next_slice_hor_pos << 0)); OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen7_mfd_jpeg_wa(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; gen7_jpeg_wa_init(ctx, gen7_mfd_context); intel_batchbuffer_emit_mi_flush(batch); gen7_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context); gen7_jpeg_wa_surface_state(ctx, gen7_mfd_context); gen7_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context); gen7_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context); gen7_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context); gen7_jpeg_wa_avc_img_state(ctx, gen7_mfd_context); gen7_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context); gen7_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context); gen7_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context); gen7_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context); } void gen7_mfd_jpeg_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferJPEGBaseline *pic_param; VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j, max_selector = 0; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer; /* Currently only support Baseline DCT */ gen7_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); gen7_mfd_jpeg_wa(ctx, gen7_mfd_context); intel_batchbuffer_emit_mi_flush(batch); gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context); gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context); gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context); gen7_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context); gen7_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { int component; assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; for (component = 0; component < slice_param->num_components; component++) { if (max_selector < slice_param->components[component].dc_table_selector) max_selector = slice_param->components[component].dc_table_selector; if (max_selector < slice_param->components[component].ac_table_selector) max_selector = slice_param->components[component].ac_table_selector; } slice_param++; } } assert(max_selector < 2); gen7_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen7_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static VAStatus gen7_mfd_decode_picture(VADriverContextP ctx, VAProfile profile, union codec_state *codec_state, struct hw_context *hw_context) { struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context; struct decode_state *decode_state = &codec_state->decode; VAStatus vaStatus; assert(gen7_mfd_context); vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state); if (vaStatus != VA_STATUS_SUCCESS) goto out; gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1; switch (profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: gen7_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context); break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: gen7_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context); break; case VAProfileVC1Simple: case VAProfileVC1Main: case VAProfileVC1Advanced: gen7_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context); break; case VAProfileJPEGBaseline: gen7_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context); break; default: assert(0); break; } vaStatus = VA_STATUS_SUCCESS; out: return vaStatus; } static void gen7_mfd_context_destroy(void *hw_context) { struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context; dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.bo = NULL; dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = NULL; dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo); gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo); gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo); gen7_mfd_context->bitplane_read_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo); intel_batchbuffer_free(gen7_mfd_context->base.batch); free(gen7_mfd_context); } static void gen7_mfd_mpeg2_context_init(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1; gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1; gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1; gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1; } struct hw_context * gen7_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config) { struct intel_driver_data *intel = intel_driver_data(ctx); struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context)); int i; gen7_mfd_context->base.destroy = gen7_mfd_context_destroy; gen7_mfd_context->base.run = gen7_mfd_decode_picture; gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0); for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID; gen7_mfd_context->reference_surface[i].frame_store_id = -1; gen7_mfd_context->reference_surface[i].obj_surface = NULL; } gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE; gen7_mfd_context->jpeg_wa_surface_object = NULL; switch (obj_config->profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: gen7_mfd_mpeg2_context_init(ctx, gen7_mfd_context); break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: gen7_mfd_avc_context_init(ctx, gen7_mfd_context); break; default: break; } return (struct hw_context *)gen7_mfd_context; } intel-driver-1.3.0/src/gen7_mfd.h000066400000000000000000000062221231401140700165400ustar00rootroot00000000000000/* * Copyright © 2011 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #ifndef _GEN7_MFD_H_ #define _GEN7_MFD_H_ #include #include #include #include #include "i965_decoder.h" #define GEN7_VC1_I_PICTURE 0 #define GEN7_VC1_P_PICTURE 1 #define GEN7_VC1_B_PICTURE 2 #define GEN7_VC1_BI_PICTURE 3 #define GEN7_VC1_SKIPPED_PICTURE 4 #define GEN7_VC1_SIMPLE_PROFILE 0 #define GEN7_VC1_MAIN_PROFILE 1 #define GEN7_VC1_ADVANCED_PROFILE 2 #define GEN7_VC1_RESERVED_PROFILE 3 #define GEN7_JPEG_ROTATION_0 0 #define GEN7_JPEG_ROTATION_90 1 #define GEN7_JPEG_ROTATION_270 2 #define GEN7_JPEG_ROTATION_180 3 #define GEN7_YUV400 0 #define GEN7_YUV420 1 #define GEN7_YUV422H_2Y 2 #define GEN7_YUV444 3 #define GEN7_YUV411 4 #define GEN7_YUV422V_2Y 5 #define GEN7_YUV422H_4Y 6 #define GEN7_YUV422V_4Y 7 struct gen7_vc1_surface { dri_bo *dmv; int picture_type; }; struct hw_context; struct gen7_mfd_context { struct hw_context base; union { VAIQMatrixBufferMPEG2 mpeg2; VAIQMatrixBufferH264 h264; /* flat scaling lists (default) */ } iq_matrix; GenFrameStore reference_surface[MAX_GEN_REFERENCE_FRAMES]; GenBuffer post_deblocking_output; GenBuffer pre_deblocking_output; GenBuffer intra_row_store_scratch_buffer; GenBuffer deblocking_filter_row_store_scratch_buffer; GenBuffer bsd_mpc_row_store_scratch_buffer; GenBuffer mpr_row_store_scratch_buffer; GenBuffer bitplane_read_buffer; VASurfaceID jpeg_wa_surface_id; struct object_surface *jpeg_wa_surface_object; dri_bo *jpeg_wa_slice_data_bo; int wa_mpeg2_slice_vertical_position; }; #endif /* _GEN7_MFD_H_ */ intel-driver-1.3.0/src/gen7_vme.c000066400000000000000000001215321231401140700165560ustar00rootroot00000000000000/* * Copyright © 2010-2011 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Zhao Yakui * */ #include #include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_encoder.h" #include "gen6_vme.h" #include "gen6_mfc.h" #ifdef SURFACE_STATE_PADDED_SIZE #undef SURFACE_STATE_PADDED_SIZE #endif #define VME_MSG_LENGTH 32 #define SURFACE_STATE_PADDED_SIZE SURFACE_STATE_PADDED_SIZE_GEN7 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index) #define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */ #define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */ #define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */ enum VIDEO_CODING_TYPE{ VIDEO_CODING_AVC = 0, VIDEO_CODING_MPEG2, VIDEO_CODING_SUM }; enum AVC_VME_KERNEL_TYPE{ AVC_VME_INTRA_SHADER = 0, AVC_VME_INTER_SHADER, AVC_VME_BATCHBUFFER, AVC_VME_BINTER_SHADER, AVC_VME_KERNEL_SUM }; enum MPEG2_VME_KERNEL_TYPE{ MPEG2_VME_INTER_SHADER = 0, MPEG2_VME_BATCHBUFFER, MPEG2_VME_KERNEL_SUM }; static const uint32_t gen7_vme_intra_frame[][4] = { #include "shaders/vme/intra_frame_ivb.g7b" }; static const uint32_t gen7_vme_inter_frame[][4] = { #include "shaders/vme/inter_frame_ivb.g7b" }; static const uint32_t gen7_vme_batchbuffer[][4] = { #include "shaders/vme/batchbuffer.g7b" }; static const uint32_t gen7_vme_binter_frame[][4] = { #include "shaders/vme/inter_bframe_ivb.g7b" }; static struct i965_kernel gen7_vme_kernels[] = { { "AVC VME Intra Frame", AVC_VME_INTRA_SHADER, /*index*/ gen7_vme_intra_frame, sizeof(gen7_vme_intra_frame), NULL }, { "AVC VME inter Frame", AVC_VME_INTER_SHADER, gen7_vme_inter_frame, sizeof(gen7_vme_inter_frame), NULL }, { "AVC VME BATCHBUFFER", AVC_VME_BATCHBUFFER, gen7_vme_batchbuffer, sizeof(gen7_vme_batchbuffer), NULL }, { "AVC VME binter Frame", AVC_VME_BINTER_SHADER, gen7_vme_binter_frame, sizeof(gen7_vme_binter_frame), NULL } }; static const uint32_t gen7_vme_mpeg2_inter_frame[][4] = { #include "shaders/vme/mpeg2_inter_ivb.g7b" }; static const uint32_t gen7_vme_mpeg2_batchbuffer[][4] = { #include "shaders/vme/batchbuffer.g7b" }; static struct i965_kernel gen7_vme_mpeg2_kernels[] = { { "MPEG2 VME inter Frame", MPEG2_VME_INTER_SHADER, gen7_vme_mpeg2_inter_frame, sizeof(gen7_vme_mpeg2_inter_frame), NULL }, { "MPEG2 VME BATCHBUFFER", MPEG2_VME_BATCHBUFFER, gen7_vme_mpeg2_batchbuffer, sizeof(gen7_vme_mpeg2_batchbuffer), NULL }, }; /* only used for VME source surface state */ static void gen7_vme_source_surface_state(VADriverContextP ctx, int index, struct object_surface *obj_surface, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; vme_context->vme_surface2_setup(ctx, &vme_context->gpe_context, obj_surface, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen7_vme_media_source_surface_state(VADriverContextP ctx, int index, struct object_surface *obj_surface, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; vme_context->vme_media_rw_surface_setup(ctx, &vme_context->gpe_context, obj_surface, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen7_vme_output_buffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs; vme_context->vme_output.pitch = 16; /* in bytes, always 16 */ if (is_intra) vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES; else vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES; vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr, "VME output buffer", vme_context->vme_output.num_blocks * vme_context->vme_output.size_block, 0x1000); assert(vme_context->vme_output.bo); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_output, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen7_vme_output_vme_batchbuffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1; vme_context->vme_batchbuffer.size_block = 32; /* 2 OWORDs */ vme_context->vme_batchbuffer.pitch = 16; vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr, "VME batchbuffer", vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block, 0x1000); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_batchbuffer, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static VAStatus gen7_vme_surface_setup(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct object_surface *obj_surface; /*Setup surfaces state*/ /* current picture for encoding */ obj_surface = encode_state->input_yuv_object; gen7_vme_source_surface_state(ctx, 0, obj_surface, encoder_context); gen7_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context); if (!is_intra) { VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int slice_type; slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI); intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 0, 1, gen7_vme_source_surface_state); if (slice_type == SLICE_TYPE_B) intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 1, 2, gen7_vme_source_surface_state); } /* VME output */ gen7_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context); gen7_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context); return VA_STATUS_SUCCESS; } static VAStatus gen7_vme_interface_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct gen6_interface_descriptor_data *desc; int i; dri_bo *bo; bo = vme_context->gpe_context.idrt.bo; dri_bo_map(bo, 1); assert(bo->virtual); desc = bo->virtual; for (i = 0; i < vme_context->vme_kernel_sum; i++) { struct i965_kernel *kernel; kernel = &vme_context->gpe_context.kernels[i]; assert(sizeof(*desc) == 32); /*Setup the descritor table*/ memset(desc, 0, sizeof(*desc)); desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6); desc->desc2.sampler_count = 1; /* FIXME: */ desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5); desc->desc3.binding_table_entry_count = 1; /* FIXME: */ desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5); desc->desc4.constant_urb_entry_read_offset = 0; desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH; /*kernel start*/ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0), kernel->bo); /*Sampler State(VME state pointer)*/ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, (1 << 2), // i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2), vme_context->vme_state.bo); desc++; } dri_bo_unmap(bo); return VA_STATUS_SUCCESS; } static VAStatus gen7_vme_constant_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; unsigned char *constant_buffer; unsigned int *vme_state_message; int mv_num; vme_state_message = (unsigned int *)vme_context->vme_state_message; mv_num = 32; if (encoder_context->codec == CODEC_H264) { if (vme_context->h264_level >= 30) { mv_num = 16; if (vme_context->h264_level >= 31) mv_num = 8; } } else if (encoder_context->codec == CODEC_MPEG2) { mv_num = 2; } vme_state_message[31] = mv_num; dri_bo_map(vme_context->gpe_context.curbe.bo, 1); assert(vme_context->gpe_context.curbe.bo->virtual); constant_buffer = vme_context->gpe_context.curbe.bo->virtual; /* Pass the required constant info into the constant buffer */ memcpy(constant_buffer, (char *)vme_context->vme_state_message, 128); dri_bo_unmap( vme_context->gpe_context.curbe.bo); return VA_STATUS_SUCCESS; } static VAStatus gen7_vme_avc_state_setup(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; unsigned int *vme_state_message; unsigned int *mb_cost_table; int i; VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; mb_cost_table = (unsigned int *)vme_context->vme_state_message; //building VME state message dri_bo_map(vme_context->vme_state.bo, 1); assert(vme_context->vme_state.bo->virtual); vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual; if ((slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP)) { vme_state_message[0] = 0x01010101; vme_state_message[1] = 0x10010101; vme_state_message[2] = 0x0F0F0F0F; vme_state_message[3] = 0x100F0F0F; vme_state_message[4] = 0x01010101; vme_state_message[5] = 0x10010101; vme_state_message[6] = 0x0F0F0F0F; vme_state_message[7] = 0x100F0F0F; vme_state_message[8] = 0x01010101; vme_state_message[9] = 0x10010101; vme_state_message[10] = 0x0F0F0F0F; vme_state_message[11] = 0x000F0F0F; vme_state_message[12] = 0x00; vme_state_message[13] = 0x00; } else { vme_state_message[0] = 0x10010101; vme_state_message[1] = 0x100F0F0F; vme_state_message[2] = 0x10010101; vme_state_message[3] = 0x000F0F0F; vme_state_message[4] = 0; vme_state_message[5] = 0; vme_state_message[6] = 0; vme_state_message[7] = 0; vme_state_message[8] = 0; vme_state_message[9] = 0; vme_state_message[10] = 0; vme_state_message[11] = 0; vme_state_message[12] = 0; vme_state_message[13] = 0; } vme_state_message[14] = (mb_cost_table[2] & 0xFFFF); vme_state_message[15] = 0; vme_state_message[16] = mb_cost_table[0]; vme_state_message[17] = mb_cost_table[1]; vme_state_message[18] = mb_cost_table[3]; vme_state_message[19] = mb_cost_table[4]; for(i = 20; i < 32; i++) { vme_state_message[i] = 0; } dri_bo_unmap( vme_context->vme_state.bo); return VA_STATUS_SUCCESS; } static VAStatus gen7_vme_mpeg2_state_setup(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; unsigned int *vme_state_message; int i; unsigned int *mb_cost_table; mb_cost_table = (unsigned int *)vme_context->vme_state_message; //building VME state message dri_bo_map(vme_context->vme_state.bo, 1); assert(vme_context->vme_state.bo->virtual); vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual; vme_state_message[0] = 0x01010101; vme_state_message[1] = 0x10010101; vme_state_message[2] = 0x0F0F0F0F; vme_state_message[3] = 0x100F0F0F; vme_state_message[4] = 0x01010101; vme_state_message[5] = 0x10010101; vme_state_message[6] = 0x0F0F0F0F; vme_state_message[7] = 0x100F0F0F; vme_state_message[8] = 0x01010101; vme_state_message[9] = 0x10010101; vme_state_message[10] = 0x0F0F0F0F; vme_state_message[11] = 0x000F0F0F; vme_state_message[12] = 0x00; vme_state_message[13] = 0x00; vme_state_message[14] = (mb_cost_table[2] & 0xFFFF); vme_state_message[15] = 0; vme_state_message[16] = mb_cost_table[0]; vme_state_message[17] = 0; vme_state_message[18] = mb_cost_table[3]; vme_state_message[19] = mb_cost_table[4]; for(i = 20; i < 32; i++) { vme_state_message[i] = 0; } //vme_state_message[16] = 0x42424242; //cost function LUT set 0 for Intra dri_bo_unmap( vme_context->vme_state.bo); return VA_STATUS_SUCCESS; } static void gen7_vme_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, int transform_8x8_mode_flag, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int mb_x = 0, mb_y = 0; int i, s, j; unsigned int *command_ptr; dri_bo_map(vme_context->vme_batchbuffer.bo, 1); command_ptr = vme_context->vme_batchbuffer.bo->virtual; for (s = 0; s < encode_state->num_slice_params_ext; s++) { VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer; for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) { int slice_mb_begin = slice_param->macroblock_address; int slice_mb_number = slice_param->num_macroblocks; unsigned int mb_intra_ub; int slice_mb_x = slice_param->macroblock_address % mb_width; for (i = 0; i < slice_mb_number;) { int mb_count = i + slice_mb_begin; mb_x = mb_count % mb_width; mb_y = mb_count / mb_width; mb_intra_ub = 0; if (mb_x != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; } if (mb_y != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; if (mb_x != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (mb_x != (mb_width -1)) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; } if (i < mb_width) { if (i == 0) mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE); mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK); if ((i == (mb_width - 1)) && slice_mb_x) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; } } if ((i == mb_width) && slice_mb_x) { mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D); } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; /*inline data */ *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x); *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8)); i += 1; } slice_param++; } } *command_ptr++ = 0; *command_ptr++ = MI_BATCH_BUFFER_END; dri_bo_unmap(vme_context->vme_batchbuffer.bo); } static void gen7_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; dri_bo *bo; i965_gpe_context_init(ctx, &vme_context->gpe_context); /* VME output buffer */ dri_bo_unreference(vme_context->vme_output.bo); vme_context->vme_output.bo = NULL; dri_bo_unreference(vme_context->vme_batchbuffer.bo); vme_context->vme_batchbuffer.bo = NULL; /* VME state */ dri_bo_unreference(vme_context->vme_state.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", 1024*16, 64); assert(bo); vme_context->vme_state.bo = bo; } static void gen7_vme_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct intel_batchbuffer *batch = encoder_context->base.batch; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; int s; bool allow_hwscore = true; int kernel_shader; for (s = 0; s < encode_state->num_slice_params_ext; s++) { pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer; if ((pSliceParameter->macroblock_address % width_in_mbs)) { allow_hwscore = false; break; } } if ((pSliceParameter->slice_type == SLICE_TYPE_I) || (pSliceParameter->slice_type == SLICE_TYPE_I)) { kernel_shader = AVC_VME_INTRA_SHADER; } else if ((pSliceParameter->slice_type == SLICE_TYPE_P) || (pSliceParameter->slice_type == SLICE_TYPE_SP)) { kernel_shader = AVC_VME_INTER_SHADER; } else { kernel_shader = AVC_VME_BINTER_SHADER; if (!allow_hwscore) kernel_shader = AVC_VME_INTER_SHADER; } if (allow_hwscore) gen7_vme_walker_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, kernel_shader, pPicParameter->pic_fields.bits.transform_8x8_mode_flag, encoder_context); else gen7_vme_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, kernel_shader, pPicParameter->pic_fields.bits.transform_8x8_mode_flag, encoder_context); intel_batchbuffer_start_atomic(batch, 0x1000); gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8)); OUT_RELOC(batch, vme_context->vme_batchbuffer.bo, I915_GEM_DOMAIN_COMMAND, 0, 0); ADVANCE_BATCH(batch); intel_batchbuffer_end_atomic(batch); } static VAStatus gen7_vme_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { VAStatus vaStatus = VA_STATUS_SUCCESS; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; struct gen6_vme_context *vme_context = encoder_context->vme_context; if (!vme_context->h264_level || (vme_context->h264_level != pSequenceParameter->level_idc)) { vme_context->h264_level = pSequenceParameter->level_idc; } intel_vme_update_mbmv_cost(ctx, encode_state, encoder_context); /*Setup all the memory object*/ gen7_vme_surface_setup(ctx, encode_state, is_intra, encoder_context); gen7_vme_interface_setup(ctx, encode_state, encoder_context); gen7_vme_constant_setup(ctx, encode_state, encoder_context); gen7_vme_avc_state_setup(ctx, encode_state, is_intra, encoder_context); /*Programing media pipeline*/ gen7_vme_pipeline_programing(ctx, encode_state, encoder_context); return vaStatus; } static VAStatus gen7_vme_run(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; intel_batchbuffer_flush(batch); return VA_STATUS_SUCCESS; } static VAStatus gen7_vme_stop(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { return VA_STATUS_SUCCESS; } static VAStatus gen7_vme_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen7_vme_media_init(ctx, encoder_context); gen7_vme_prepare(ctx, encode_state, encoder_context); gen7_vme_run(ctx, encode_state, encoder_context); gen7_vme_stop(ctx, encode_state, encoder_context); return VA_STATUS_SUCCESS; } static void gen7_vme_mpeg2_output_buffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, int is_intra, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs; vme_context->vme_output.pitch = 16; /* in bytes, always 16 */ if (is_intra) vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES; else vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES; vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr, "VME output buffer", vme_context->vme_output.num_blocks * vme_context->vme_output.size_block, 0x1000); assert(vme_context->vme_output.bo); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_output, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen7_vme_mpeg2_output_vme_batchbuffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1; vme_context->vme_batchbuffer.size_block = 32; /* 4 OWORDs */ vme_context->vme_batchbuffer.pitch = 16; vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr, "VME batchbuffer", vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block, 0x1000); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_batchbuffer, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static VAStatus gen7_vme_mpeg2_surface_setup(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct object_surface *obj_surface; /*Setup surfaces state*/ /* current picture for encoding */ obj_surface = encode_state->input_yuv_object; gen7_vme_source_surface_state(ctx, 0, obj_surface, encoder_context); gen7_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context); if (!is_intra) { /* reference 0 */ obj_surface = encode_state->reference_objects[0]; if (obj_surface->bo != NULL) gen7_vme_source_surface_state(ctx, 1, obj_surface, encoder_context); /* reference 1 */ obj_surface = encode_state->reference_objects[1]; if (obj_surface && obj_surface->bo != NULL) gen7_vme_source_surface_state(ctx, 2, obj_surface, encoder_context); } /* VME output */ gen7_vme_mpeg2_output_buffer_setup(ctx, encode_state, 3, is_intra, encoder_context); gen7_vme_mpeg2_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context); return VA_STATUS_SUCCESS; } static void gen7_vme_mpeg2_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, int transform_8x8_mode_flag, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int mb_x = 0, mb_y = 0; int i, s, j; unsigned int *command_ptr; dri_bo_map(vme_context->vme_batchbuffer.bo, 1); command_ptr = vme_context->vme_batchbuffer.bo->virtual; for (s = 0; s < encode_state->num_slice_params_ext; s++) { VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer; for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) { int slice_mb_begin = slice_param->macroblock_address; int slice_mb_number = slice_param->num_macroblocks; unsigned int mb_intra_ub; for (i = 0; i < slice_mb_number;) { int mb_count = i + slice_mb_begin; mb_x = mb_count % mb_width; mb_y = mb_count / mb_width; mb_intra_ub = 0; if (mb_x != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; } if (mb_y != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; if (mb_x != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (mb_x != (mb_width -1)) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; /*inline data */ *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x); *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8)); i += 1; } slice_param++; } } *command_ptr++ = 0; *command_ptr++ = MI_BATCH_BUFFER_END; dri_bo_unmap(vme_context->vme_batchbuffer.bo); } static void gen7_vme_mpeg2_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct intel_batchbuffer *batch = encoder_context->base.batch; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; bool allow_hwscore = true; int s; for (s = 0; s < encode_state->num_slice_params_ext; s++) { int j; VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer; for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) { if (slice_param->macroblock_address % width_in_mbs) { allow_hwscore = false; break; } } } if (allow_hwscore) gen7_vme_mpeg2_walker_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, MPEG2_VME_INTER_SHADER, encoder_context); else gen7_vme_mpeg2_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, MPEG2_VME_INTER_SHADER, 0, encoder_context); intel_batchbuffer_start_atomic(batch, 0x1000); gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8)); OUT_RELOC(batch, vme_context->vme_batchbuffer.bo, I915_GEM_DOMAIN_COMMAND, 0, 0); ADVANCE_BATCH(batch); intel_batchbuffer_end_atomic(batch); } static VAStatus gen7_vme_mpeg2_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { VAStatus vaStatus = VA_STATUS_SUCCESS; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; struct gen6_vme_context *vme_context = encoder_context->vme_context; if ((!vme_context->mpeg2_level) || (vme_context->mpeg2_level != (seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK))) { vme_context->mpeg2_level = seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK; } /*Setup all the memory object*/ intel_vme_mpeg2_state_setup(ctx, encode_state, encoder_context); gen7_vme_mpeg2_surface_setup(ctx, encode_state, 0, encoder_context); gen7_vme_interface_setup(ctx, encode_state, encoder_context); gen7_vme_constant_setup(ctx, encode_state, encoder_context); gen7_vme_mpeg2_state_setup(ctx, encode_state, 0, encoder_context); /*Programing media pipeline*/ gen7_vme_mpeg2_pipeline_programing(ctx, encode_state, 0, encoder_context); return vaStatus; } static VAStatus gen7_vme_mpeg2_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; /*No need of to exec VME for Intra slice */ if (slice_param->is_intra_slice) { if(!vme_context->vme_output.bo) { int w_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int h_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; vme_context->vme_output.num_blocks = w_in_mbs * h_in_mbs; vme_context->vme_output.pitch = 16; /* in bytes, always 16 */ vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES; vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr, "MPEG2 VME output buffer", vme_context->vme_output.num_blocks * vme_context->vme_output.size_block, 0x1000); } return VA_STATUS_SUCCESS; } gen7_vme_media_init(ctx, encoder_context); gen7_vme_mpeg2_prepare(ctx, encode_state, encoder_context); gen7_vme_run(ctx, encode_state, encoder_context); gen7_vme_stop(ctx, encode_state, encoder_context); return VA_STATUS_SUCCESS; } static void gen7_vme_context_destroy(void *context) { struct gen6_vme_context *vme_context = context; i965_gpe_context_destroy(&vme_context->gpe_context); dri_bo_unreference(vme_context->vme_output.bo); vme_context->vme_output.bo = NULL; dri_bo_unreference(vme_context->vme_state.bo); vme_context->vme_state.bo = NULL; dri_bo_unreference(vme_context->vme_batchbuffer.bo); vme_context->vme_batchbuffer.bo = NULL; if (vme_context->vme_state_message) { free(vme_context->vme_state_message); vme_context->vme_state_message = NULL; } free(vme_context); } Bool gen7_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context)); struct i965_kernel *vme_kernel_list = NULL; vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6; vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data); vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH; vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1; vme_context->gpe_context.vfe_state.num_urb_entries = 16; vme_context->gpe_context.vfe_state.gpgpu_mode = 0; vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1; vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1; gen7_vme_scoreboard_init(ctx, vme_context); if (encoder_context->codec == CODEC_H264) { vme_kernel_list = gen7_vme_kernels; vme_context->video_coding_type = VIDEO_CODING_AVC; vme_context->vme_kernel_sum = AVC_VME_KERNEL_SUM; encoder_context->vme_pipeline = gen7_vme_pipeline; } else if (encoder_context->codec == CODEC_MPEG2) { vme_kernel_list = gen7_vme_mpeg2_kernels; vme_context->video_coding_type = VIDEO_CODING_MPEG2; vme_context->vme_kernel_sum = MPEG2_VME_KERNEL_SUM; encoder_context->vme_pipeline = gen7_vme_mpeg2_pipeline; } else { /* Unsupported codec */ assert(0); } i965_gpe_load_kernels(ctx, &vme_context->gpe_context, vme_kernel_list, vme_context->vme_kernel_sum); vme_context->vme_surface2_setup = gen7_gpe_surface2_setup; vme_context->vme_media_rw_surface_setup = gen7_gpe_media_rw_surface_setup; vme_context->vme_buffer_suface_setup = gen7_gpe_buffer_suface_setup; encoder_context->vme_context = vme_context; encoder_context->vme_context_destroy = gen7_vme_context_destroy; vme_context->vme_state_message = malloc(VME_MSG_LENGTH * sizeof(int)); return True; } intel-driver-1.3.0/src/gen8_mfc.c000066400000000000000000003103701231401140700165350ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Zhao Yakui * Xiang Haihao * */ #include #include #include #include #include #include "intel_batchbuffer.h" #include "i965_defines.h" #include "i965_structs.h" #include "i965_drv_video.h" #include "i965_encoder.h" #include "i965_encoder_utils.h" #include "gen6_mfc.h" #include "gen6_vme.h" #include "intel_media.h" #define SURFACE_STATE_PADDED_SIZE SURFACE_STATE_PADDED_SIZE_GEN8 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index) #define MFC_SOFTWARE_HASWELL 1 #define B0_STEP_REV 2 #define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV) static const uint32_t gen8_mfc_batchbuffer_avc_intra[][4] = { #include "shaders/utils/mfc_batchbuffer_avc_intra.g7b" }; static const uint32_t gen8_mfc_batchbuffer_avc_inter[][4] = { #include "shaders/utils/mfc_batchbuffer_avc_inter.g7b" }; static struct i965_kernel gen8_mfc_kernels[] = { { "MFC AVC INTRA BATCHBUFFER ", MFC_BATCHBUFFER_AVC_INTRA, gen8_mfc_batchbuffer_avc_intra, sizeof(gen8_mfc_batchbuffer_avc_intra), NULL }, { "MFC AVC INTER BATCHBUFFER ", MFC_BATCHBUFFER_AVC_INTER, gen8_mfc_batchbuffer_avc_inter, sizeof(gen8_mfc_batchbuffer_avc_inter), NULL }, }; #define INTER_MODE_MASK 0x03 #define INTER_8X8 0x03 #define INTER_16X8 0x01 #define INTER_8X16 0x02 #define SUBMB_SHAPE_MASK 0x00FF00 #define INTER_MV8 (4 << 20) #define INTER_MV32 (6 << 20) static void gen8_mfc_pipe_mode_select(VADriverContextP ctx, int standard_select, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; assert(standard_select == MFX_FORMAT_MPEG2 || standard_select == MFX_FORMAT_AVC); BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2)); OUT_BCS_BATCH(batch, (MFX_LONG_MODE << 17) | /* Must be long format for encoder */ (MFD_MODE_VLD << 15) | /* VLD mode */ (0 << 10) | /* Stream-Out Enable */ ((!!mfc_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */ ((!!mfc_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */ (0 << 5) | /* not in stitch mode */ (1 << 4) | /* encoding mode */ (standard_select << 0)); /* standard select: avc or mpeg2 */ OUT_BCS_BATCH(batch, (0 << 7) | /* expand NOA bus flag */ (0 << 6) | /* disable slice-level clock gating */ (0 << 5) | /* disable clock gating for NOA */ (0 << 4) | /* terminate if AVC motion and POC table error occurs */ (0 << 3) | /* terminate if AVC mbdata error occurs */ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ (0 << 1) | (0 << 0)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, ((mfc_context->surface_state.height - 1) << 18) | ((mfc_context->surface_state.width - 1) << 4)); OUT_BCS_BATCH(batch, (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */ (0 << 22) | /* surface object control state, FIXME??? */ ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */ (0 << 2) | /* must be 0 for interleave U/V */ (1 << 1) | /* must be tiled */ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */ OUT_BCS_BATCH(batch, (0 << 16) | /* must be 0 for interleave U/V */ (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; int vme_size; BEGIN_BCS_BATCH(batch, 26); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2)); /* the DW1-3 is for the MFX indirect bistream offset */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW4-5 is the MFX upper bound */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); vme_size = vme_context->vme_output.size_block * vme_context->vme_output.num_blocks; /* the DW6-10 is for MFX Indirect MV Object Base Address */ OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, vme_size); OUT_BCS_BATCH(batch, 0); /* the DW11-15 is for MFX IT-COFF. Not used on encoder */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW16-20 is for MFX indirect DBLK. Not used on encoder */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW21-25 is for MFC Indirect PAK-BSE Object Base Address for Encoder*/ OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, mfc_context->mfc_indirect_pak_bse_object.end_offset); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; BEGIN_BCS_BATCH(batch, 16); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2)); /*DW1. MB setting of frame */ OUT_BCS_BATCH(batch, ((width_in_mbs * height_in_mbs - 1) & 0xFFFF)); OUT_BCS_BATCH(batch, ((height_in_mbs - 1) << 16) | ((width_in_mbs - 1) << 0)); /* DW3 QP setting */ OUT_BCS_BATCH(batch, (0 << 24) | /* Second Chroma QP Offset */ (0 << 16) | /* Chroma QP Offset */ (0 << 14) | /* Max-bit conformance Intra flag */ (0 << 13) | /* Max Macroblock size conformance Inter flag */ (pPicParameter->pic_fields.bits.weighted_pred_flag << 12) | /*Weighted_Pred_Flag */ (pPicParameter->pic_fields.bits.weighted_bipred_idc << 10) | /* Weighted_BiPred_Idc */ (0 << 8) | /* FIXME: Image Structure */ (0 << 0) ); /* Current Decoed Image Frame Store ID, reserved in Encode mode */ OUT_BCS_BATCH(batch, (0 << 16) | /* Mininum Frame size */ (0 << 15) | /* Disable reading of Macroblock Status Buffer */ (0 << 14) | /* Load BitStream Pointer only once, 1 slic 1 frame */ (0 << 13) | /* CABAC 0 word insertion test enable */ (1 << 12) | /* MVUnpackedEnable,compliant to DXVA */ (1 << 10) | /* Chroma Format IDC, 4:2:0 */ (0 << 8) | /* FIXME: MbMvFormatFlag */ (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/ (0 << 6) | /* Only valid for VLD decoding mode */ (0 << 5) | /* Constrained Intra Predition Flag, from PPS */ (0 << 4) | /* Direct 8x8 inference flag */ (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/ (1 << 2) | /* Frame MB only flag */ (0 << 1) | /* MBAFF mode is in active */ (0 << 0)); /* Field picture flag */ /* DW5 Trellis quantization */ OUT_BCS_BATCH(batch, 0); /* Mainly about MB rate control and debug, just ignoring */ OUT_BCS_BATCH(batch, /* Inter and Intra Conformance Max size limit */ (0xBB8 << 16) | /* InterMbMaxSz */ (0xEE8) ); /* IntraMbMaxSz */ OUT_BCS_BATCH(batch, 0); /* Reserved */ /* DW8. QP delta */ OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */ OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */ /* DW10. Bit setting for MB */ OUT_BCS_BATCH(batch, 0x8C000000); OUT_BCS_BATCH(batch, 0x00010000); /* DW12. */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0x02010100); /* DW14. For short format */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfc_qm_state(VADriverContextP ctx, int qm_type, unsigned int *qm, int qm_length, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; unsigned int qm_buffer[16]; assert(qm_length <= 16); assert(sizeof(*qm) == 4); memcpy(qm_buffer, qm, qm_length * 4); BEGIN_BCS_BATCH(batch, 18); OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2)); OUT_BCS_BATCH(batch, qm_type << 0); intel_batchbuffer_data(batch, qm_buffer, 16 * 4); ADVANCE_BCS_BATCH(batch); } static void gen8_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned int qm[16] = { 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010 }; gen8_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, encoder_context); gen8_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, encoder_context); gen8_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, encoder_context); gen8_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, encoder_context); } static void gen8_mfc_fqm_state(VADriverContextP ctx, int fqm_type, unsigned int *fqm, int fqm_length, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; unsigned int fqm_buffer[32]; assert(fqm_length <= 32); assert(sizeof(*fqm) == 4); memcpy(fqm_buffer, fqm, fqm_length * 4); BEGIN_BCS_BATCH(batch, 34); OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2)); OUT_BCS_BATCH(batch, fqm_type << 0); intel_batchbuffer_data(batch, fqm_buffer, 32 * 4); ADVANCE_BCS_BATCH(batch); } static void gen8_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned int qm[32] = { 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000, 0x10001000 }; gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, encoder_context); gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, encoder_context); gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, encoder_context); gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, encoder_context); } static void gen8_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context, unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw, int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag, struct intel_batchbuffer *batch) { if (batch == NULL) batch = encoder_context->base.batch; if (data_bits_in_last_dw == 0) data_bits_in_last_dw = 32; BEGIN_BCS_BATCH(batch, lenght_in_dws + 2); OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws + 2 - 2)); OUT_BCS_BATCH(batch, (0 << 16) | /* always start at offset 0 */ (data_bits_in_last_dw << 8) | (skip_emul_byte_count << 4) | (!!emulation_flag << 3) | ((!!is_last_header) << 2) | ((!!is_end_of_slice) << 1) | (0 << 0)); /* FIXME: ??? */ intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4); ADVANCE_BCS_BATCH(batch); } static void gen8_mfc_init(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; dri_bo *bo; int i; int width_in_mbs = 0; int height_in_mbs = 0; int slice_batchbuffer_size; if (encoder_context->codec == CODEC_H264) { VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; width_in_mbs = pSequenceParameter->picture_width_in_mbs; height_in_mbs = pSequenceParameter->picture_height_in_mbs; } else { VAEncSequenceParameterBufferMPEG2 *pSequenceParameter = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; assert(encoder_context->codec == CODEC_MPEG2); width_in_mbs = ALIGN(pSequenceParameter->picture_width, 16) / 16; height_in_mbs = ALIGN(pSequenceParameter->picture_height, 16) / 16; } slice_batchbuffer_size = 64 * width_in_mbs * height_in_mbs + 4096 + (SLICE_HEADER + SLICE_TAIL) * encode_state->num_slice_params_ext; /*Encode common setup for MFC*/ dri_bo_unreference(mfc_context->post_deblocking_output.bo); mfc_context->post_deblocking_output.bo = NULL; dri_bo_unreference(mfc_context->pre_deblocking_output.bo); mfc_context->pre_deblocking_output.bo = NULL; dri_bo_unreference(mfc_context->uncompressed_picture_source.bo); mfc_context->uncompressed_picture_source.bo = NULL; dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo); mfc_context->mfc_indirect_pak_bse_object.bo = NULL; for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){ if ( mfc_context->direct_mv_buffers[i].bo != NULL); dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo); mfc_context->direct_mv_buffers[i].bo = NULL; } for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){ if (mfc_context->reference_surfaces[i].bo != NULL) dri_bo_unreference(mfc_context->reference_surfaces[i].bo); mfc_context->reference_surfaces[i].bo = NULL; } dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", width_in_mbs * 64, 64); assert(bo); mfc_context->intra_row_store_scratch_buffer.bo = bo; dri_bo_unreference(mfc_context->macroblock_status_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", width_in_mbs * height_in_mbs * 16, 64); assert(bo); mfc_context->macroblock_status_buffer.bo = bo; dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */ 64); assert(bo); mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo; dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", 2 * width_in_mbs * 64, /* 2 * width_in_mbs * 64 */ 0x1000); assert(bo); mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo; dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo); mfc_context->mfc_batchbuffer_surface.bo = NULL; dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo); mfc_context->aux_batchbuffer_surface.bo = NULL; if (mfc_context->aux_batchbuffer) intel_batchbuffer_free(mfc_context->aux_batchbuffer); mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, slice_batchbuffer_size); mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer; dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo); mfc_context->aux_batchbuffer_surface.pitch = 16; mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16; mfc_context->aux_batchbuffer_surface.size_block = 16; i965_gpe_context_init(ctx, &mfc_context->gpe_context); } static void gen8_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int i; BEGIN_BCS_BATCH(batch, 61); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2)); /* the DW1-3 is for pre_deblocking */ if (mfc_context->pre_deblocking_output.bo) OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); /* pre output addr */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW4-6 is for the post_deblocking */ if (mfc_context->post_deblocking_output.bo) OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* post output addr */ else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW7-9 is for the uncompressed_picture */ OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* uncompressed data */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW10-12 is for the mb status */ OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* StreamOut data*/ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW13-15 is for the intra_row_store_scratch */ OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW16-18 is for the deblocking filter */ OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW 19-50 is for Reference pictures*/ for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) { if ( mfc_context->reference_surfaces[i].bo != NULL) { OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); } else { OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); /* The DW 52-54 is for the MB status buffer */ OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* Macroblock status buffer*/ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW 55-57 is the ILDB buffer */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW 58-60 is the second ILDB buffer */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int i; BEGIN_BCS_BATCH(batch, 71); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2)); /* Reference frames and Current frames */ /* the DW1-32 is for the direct MV for reference */ for(i = 0; i < NUM_MFC_DMV_BUFFERS - 2; i += 2) { if ( mfc_context->direct_mv_buffers[i].bo != NULL) { OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } OUT_BCS_BATCH(batch, 0); /* the DW34-36 is the MV for the current reference */ OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* POL list */ for(i = 0; i < 32; i++) { OUT_BCS_BATCH(batch, i/2); } OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2)); OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW4-6 is for MPR Row Store Scratch Buffer Base Address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW7-9 is for Bitplane Read Buffer Base Address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfc_avc_pipeline_picture_programing( VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context); mfc_context->set_surface_state(ctx, encoder_context); mfc_context->ind_obj_base_addr_state(ctx, encoder_context); gen8_mfc_pipe_buf_addr_state(ctx, encoder_context); gen8_mfc_bsp_buf_base_addr_state(ctx, encoder_context); mfc_context->avc_img_state(ctx, encode_state, encoder_context); mfc_context->avc_qm_state(ctx, encoder_context); mfc_context->avc_fqm_state(ctx, encoder_context); gen8_mfc_avc_directmode_state(ctx, encoder_context); intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context); } static VAStatus gen8_mfc_run(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; intel_batchbuffer_flush(batch); //run the pipeline return VA_STATUS_SUCCESS; } static VAStatus gen8_mfc_stop(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int *encoded_bits_size) { VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VACodedBufferSegment *coded_buffer_segment; vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment); assert(vaStatus == VA_STATUS_SUCCESS); *encoded_bits_size = coded_buffer_segment->size * 8; i965_UnmapBuffer(ctx, pPicParameter->coded_buf); return VA_STATUS_SUCCESS; } static void gen8_mfc_avc_slice_state(VADriverContextP ctx, VAEncPictureParameterBufferH264 *pic_param, VAEncSliceParameterBufferH264 *slice_param, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int rate_control_enable, int qp, struct intel_batchbuffer *batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; int beginmb = slice_param->macroblock_address; int endmb = beginmb + slice_param->num_macroblocks; int beginx = beginmb % width_in_mbs; int beginy = beginmb / width_in_mbs; int nextx = endmb % width_in_mbs; int nexty = endmb / width_in_mbs; int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); int last_slice = (endmb == (width_in_mbs * height_in_mbs)); int maxQpN, maxQpP; unsigned char correct[6], grow, shrink; int i; int weighted_pred_idc = 0; unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom; unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom; int num_ref_l0 = 0, num_ref_l1 = 0; if (batch == NULL) batch = encoder_context->base.batch; if (slice_type == SLICE_TYPE_I) { luma_log2_weight_denom = 0; chroma_log2_weight_denom = 0; } else if (slice_type == SLICE_TYPE_P) { weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag; num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1; if (slice_param->num_ref_idx_active_override_flag) num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; } else if (slice_type == SLICE_TYPE_B) { weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc; num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1; num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1; if (slice_param->num_ref_idx_active_override_flag) { num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1; } if (weighted_pred_idc == 2) { /* 8.4.3 - Derivation process for prediction weights (8-279) */ luma_log2_weight_denom = 5; chroma_log2_weight_denom = 5; } } maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier; maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier; for (i = 0; i < 6; i++) correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i]; grow = mfc_context->bit_rate_control_context[slice_type].GrowInit + (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4); shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit + (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4); BEGIN_BCS_BATCH(batch, 11);; OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) ); OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/ OUT_BCS_BATCH(batch, (num_ref_l0 << 16) | (num_ref_l1 << 24) | (chroma_log2_weight_denom << 8) | (luma_log2_weight_denom << 0)); OUT_BCS_BATCH(batch, (weighted_pred_idc << 30) | (slice_param->direct_spatial_mv_pred_flag<<29) | /*Direct Prediction Type*/ (slice_param->disable_deblocking_filter_idc << 27) | (slice_param->cabac_init_idc << 24) | (qp<<16) | /*Slice Quantization Parameter*/ ((slice_param->slice_beta_offset_div2 & 0xf) << 8) | ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0)); OUT_BCS_BATCH(batch, (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/ (beginx << 16) | slice_param->macroblock_address ); OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/ OUT_BCS_BATCH(batch, (0/*rate_control_enable*/ << 31) | /*in CBR mode RateControlCounterEnable = enable*/ (1 << 30) | /*ResetRateControlCounter*/ (0 << 28) | /*RC Triggle Mode = Always Rate Control*/ (4 << 24) | /*RC Stable Tolerance, middle level*/ (0/*rate_control_enable*/ << 23) | /*RC Panic Enable*/ (0 << 22) | /*QP mode, don't modfiy CBP*/ (0 << 21) | /*MB Type Direct Conversion Enabled*/ (0 << 20) | /*MB Type Skip Conversion Enabled*/ (last_slice << 19) | /*IsLastSlice*/ (0 << 18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/ (1 << 17) | /*HeaderPresentFlag*/ (1 << 16) | /*SliceData PresentFlag*/ (1 << 15) | /*TailPresentFlag*/ (1 << 13) | /*RBSP NAL TYPE*/ (0 << 12) ); /*CabacZeroWordInsertionEnable*/ OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset); OUT_BCS_BATCH(batch, (maxQpN << 24) | /*Target QP - 24 is lowest QP*/ (maxQpP << 16) | /*Target QP + 20 is highest QP*/ (shrink << 8) | (grow << 0)); OUT_BCS_BATCH(batch, (correct[5] << 20) | (correct[4] << 16) | (correct[3] << 12) | (correct[2] << 8) | (correct[1] << 4) | (correct[0] << 0)); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } #ifdef MFC_SOFTWARE_HASWELL static int gen8_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg, struct intel_encoder_context *encoder_context, unsigned char target_mb_size, unsigned char max_mb_size, struct intel_batchbuffer *batch) { int len_in_dwords = 12; unsigned int intra_msg; #define INTRA_MSG_FLAG (1 << 13) #define INTRA_MBTYPE_MASK (0x1F0000) if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, len_in_dwords); intra_msg = msg[0] & 0xC0FF; intra_msg |= INTRA_MSG_FLAG; intra_msg |= ((msg[0] & INTRA_MBTYPE_MASK) >> 8); OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, (0 << 24) | /* PackedMvNum, Debug*/ (0 << 20) | /* No motion vector */ (1 << 19) | /* CbpDcY */ (1 << 18) | /* CbpDcU */ (1 << 17) | /* CbpDcV */ intra_msg); OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x); /* Code Block Pattern for Y*/ OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */ /*Stuff for Intra MB*/ OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/ OUT_BCS_BATCH(batch, msg[2]); OUT_BCS_BATCH(batch, msg[3]&0xFF); /*MaxSizeInWord and TargetSzieInWord*/ OUT_BCS_BATCH(batch, (max_mb_size << 24) | (target_mb_size << 16) ); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); return len_in_dwords; } static int gen8_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int *msg, unsigned int offset, struct intel_encoder_context *encoder_context, unsigned char target_mb_size,unsigned char max_mb_size, int slice_type, struct intel_batchbuffer *batch) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int len_in_dwords = 12; unsigned int inter_msg = 0; if (batch == NULL) batch = encoder_context->base.batch; { #define MSG_MV_OFFSET 4 unsigned int *mv_ptr; mv_ptr = msg + MSG_MV_OFFSET; /* MV of VME output is based on 16 sub-blocks. So it is necessary * to convert them to be compatible with the format of AVC_PAK * command. */ if ((msg[0] & INTER_MODE_MASK) == INTER_8X16) { /* MV[0] and MV[2] are replicated */ mv_ptr[4] = mv_ptr[0]; mv_ptr[5] = mv_ptr[1]; mv_ptr[2] = mv_ptr[8]; mv_ptr[3] = mv_ptr[9]; mv_ptr[6] = mv_ptr[8]; mv_ptr[7] = mv_ptr[9]; } else if ((msg[0] & INTER_MODE_MASK) == INTER_16X8) { /* MV[0] and MV[1] are replicated */ mv_ptr[2] = mv_ptr[0]; mv_ptr[3] = mv_ptr[1]; mv_ptr[4] = mv_ptr[16]; mv_ptr[5] = mv_ptr[17]; mv_ptr[6] = mv_ptr[24]; mv_ptr[7] = mv_ptr[25]; } else if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) && !(msg[1] & SUBMB_SHAPE_MASK)) { /* Don't touch MV[0] or MV[1] */ mv_ptr[2] = mv_ptr[8]; mv_ptr[3] = mv_ptr[9]; mv_ptr[4] = mv_ptr[16]; mv_ptr[5] = mv_ptr[17]; mv_ptr[6] = mv_ptr[24]; mv_ptr[7] = mv_ptr[25]; } } BEGIN_BCS_BATCH(batch, len_in_dwords); OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); inter_msg = 32; /* MV quantity */ if ((msg[0] & INTER_MODE_MASK) == INTER_8X8) { if (msg[1] & SUBMB_SHAPE_MASK) inter_msg = 128; } OUT_BCS_BATCH(batch, inter_msg); /* 32 MV*/ OUT_BCS_BATCH(batch, offset); inter_msg = msg[0] & (0x1F00FFFF); inter_msg |= INTER_MV8; inter_msg |= ((1 << 19) | (1 << 18) | (1 << 17)); if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) && (msg[1] & SUBMB_SHAPE_MASK)) { inter_msg |= INTER_MV32; } OUT_BCS_BATCH(batch, inter_msg); OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/ OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ #if 0 if ( slice_type == SLICE_TYPE_B) { OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */ } else { OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ } #else OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ #endif inter_msg = msg[1] >> 8; /*Stuff for Inter MB*/ OUT_BCS_BATCH(batch, inter_msg); OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[0]); OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[1]); /*MaxSizeInWord and TargetSzieInWord*/ OUT_BCS_BATCH(batch, (max_mb_size << 24) | (target_mb_size << 16) ); OUT_BCS_BATCH(batch, 0x0); ADVANCE_BCS_BATCH(batch); return len_in_dwords; } #define AVC_INTRA_RDO_OFFSET 4 #define AVC_INTER_RDO_OFFSET 10 #define AVC_INTER_MSG_OFFSET 8 #define AVC_INTER_MV_OFFSET 48 #define AVC_RDO_MASK 0xFFFF static void gen8_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int slice_index, struct intel_batchbuffer *slice_batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer; unsigned int *msg = NULL, offset = 0; unsigned char *msg_ptr = NULL; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs); int i,x,y; int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta; unsigned int rate_control_mode = encoder_context->rate_control_mode; unsigned char *slice_header = NULL; int slice_header_length_in_bits = 0; unsigned int tail_data[] = { 0x0, 0x0 }; int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type); int is_intra = slice_type == SLICE_TYPE_I; if (rate_control_mode == VA_RC_CBR) { qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY; pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp; } /* only support for 8-bit pixel bit-depth */ assert(pSequenceParameter->bit_depth_luma_minus8 == 0); assert(pSequenceParameter->bit_depth_chroma_minus8 == 0); assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52); assert(qp >= 0 && qp < 52); gen8_mfc_avc_slice_state(ctx, pPicParameter, pSliceParameter, encode_state, encoder_context, (rate_control_mode == VA_RC_CBR), qp, slice_batch); if ( slice_index == 0) intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header); // slice hander mfc_context->insert_object(ctx, encoder_context, (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f, 5, /* first 5 bytes are start code + nal unit type */ 1, 0, 1, slice_batch); dri_bo_map(vme_context->vme_output.bo , 1); msg_ptr = (unsigned char *)vme_context->vme_output.bo->virtual; if (is_intra) { msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block); } else { msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block); } for (i = pSliceParameter->macroblock_address; i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) { int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) ); x = i % width_in_mbs; y = i / width_in_mbs; msg = (unsigned int *) (msg_ptr + i * vme_context->vme_output.size_block); if (is_intra) { assert(msg); gen8_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch); } else { int inter_rdo, intra_rdo; inter_rdo = msg[AVC_INTER_RDO_OFFSET] & AVC_RDO_MASK; intra_rdo = msg[AVC_INTRA_RDO_OFFSET] & AVC_RDO_MASK; offset = i * vme_context->vme_output.size_block + AVC_INTER_MV_OFFSET; if (intra_rdo < inter_rdo) { gen8_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch); } else { msg += AVC_INTER_MSG_OFFSET; gen8_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch); } } } dri_bo_unmap(vme_context->vme_output.bo); if ( last_slice ) { mfc_context->insert_object(ctx, encoder_context, tail_data, 2, 8, 2, 1, 1, 0, slice_batch); } else { mfc_context->insert_object(ctx, encoder_context, tail_data, 1, 8, 1, 1, 1, 0, slice_batch); } free(slice_header); } static dri_bo * gen8_mfc_avc_software_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch; dri_bo *batch_bo; int i; batch = mfc_context->aux_batchbuffer; batch_bo = batch->buffer; for (i = 0; i < encode_state->num_slice_params_ext; i++) { gen8_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch); } intel_batchbuffer_align(batch, 8); BEGIN_BCS_BATCH(batch, 2); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END); ADVANCE_BCS_BATCH(batch); dri_bo_reference(batch_bo); intel_batchbuffer_free(batch); mfc_context->aux_batchbuffer = NULL; return batch_bo; } #else static void gen8_mfc_batchbuffer_surfaces_input(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; assert(vme_context->vme_output.bo); mfc_context->buffer_suface_setup(ctx, &mfc_context->gpe_context, &vme_context->vme_output, BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT), SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT)); assert(mfc_context->aux_batchbuffer_surface.bo); mfc_context->buffer_suface_setup(ctx, &mfc_context->gpe_context, &mfc_context->aux_batchbuffer_surface, BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER), SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER)); } static void gen8_mfc_batchbuffer_surfaces_output(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1; mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */ mfc_context->mfc_batchbuffer_surface.pitch = 16; mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr, "MFC batchbuffer", mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block, 0x1000); mfc_context->buffer_suface_setup(ctx, &mfc_context->gpe_context, &mfc_context->mfc_batchbuffer_surface, BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER), SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER)); } static void gen8_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen8_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context); gen8_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context); } static void gen8_mfc_batchbuffer_idrt_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_interface_descriptor_data *desc; int i; dri_bo *bo; bo = mfc_context->gpe_context.idrt.bo; dri_bo_map(bo, 1); assert(bo->virtual); desc = bo->virtual; for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) { struct i965_kernel *kernel; kernel = &mfc_context->gpe_context.kernels[i]; assert(sizeof(*desc) == 32); /*Setup the descritor table*/ memset(desc, 0, sizeof(*desc)); desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6); desc->desc2.sampler_count = 0; desc->desc2.sampler_state_pointer = 0; desc->desc3.binding_table_entry_count = 2; desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5); desc->desc4.constant_urb_entry_read_offset = 0; desc->desc4.constant_urb_entry_read_length = 4; /*kernel start*/ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0), kernel->bo); desc++; } dri_bo_unmap(bo); } static void gen8_mfc_batchbuffer_constant_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; (void)mfc_context; } static void gen8_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch, int index, int head_offset, int batchbuffer_offset, int head_size, int tail_size, int number_mb_cmds, int first_object, int last_object, int last_slice, int mb_x, int mb_y, int width_in_mbs, int qp) { BEGIN_BATCH(batch, 12); OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2)); OUT_BATCH(batch, index); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /*inline data */ OUT_BATCH(batch, head_offset); OUT_BATCH(batch, batchbuffer_offset); OUT_BATCH(batch, head_size << 16 | tail_size); OUT_BATCH(batch, number_mb_cmds << 16 | first_object << 2 | last_object << 1 | last_slice); OUT_BATCH(batch, mb_y << 8 | mb_x); OUT_BATCH(batch, qp << 16 | width_in_mbs); ADVANCE_BATCH(batch); } static void gen8_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx, struct intel_encoder_context *encoder_context, VAEncSliceParameterBufferH264 *slice_param, int head_offset, unsigned short head_size, unsigned short tail_size, int batchbuffer_offset, int qp, int last_slice) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int total_mbs = slice_param->num_macroblocks; int number_mb_cmds = 128; int starting_mb = 0; int last_object = 0; int first_object = 1; int i; int mb_x, mb_y; int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER; for (i = 0; i < total_mbs / number_mb_cmds; i++) { last_object = (total_mbs - starting_mb) == number_mb_cmds; mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs; mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs; assert(mb_x <= 255 && mb_y <= 255); starting_mb += number_mb_cmds; gen8_mfc_batchbuffer_emit_object_command(batch, index, head_offset, batchbuffer_offset, head_size, tail_size, number_mb_cmds, first_object, last_object, last_slice, mb_x, mb_y, width_in_mbs, qp); if (first_object) { head_offset += head_size; batchbuffer_offset += head_size; } if (last_object) { head_offset += tail_size; batchbuffer_offset += tail_size; } batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD; first_object = 0; } if (!last_object) { last_object = 1; number_mb_cmds = total_mbs % number_mb_cmds; mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs; mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs; assert(mb_x <= 255 && mb_y <= 255); starting_mb += number_mb_cmds; gen8_mfc_batchbuffer_emit_object_command(batch, index, head_offset, batchbuffer_offset, head_size, tail_size, number_mb_cmds, first_object, last_object, last_slice, mb_x, mb_y, width_in_mbs, qp); } } /* * return size in Owords (16bytes) */ static int gen8_mfc_avc_batchbuffer_slice(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int slice_index, int batchbuffer_offset) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs); int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta; unsigned int rate_control_mode = encoder_context->rate_control_mode; unsigned char *slice_header = NULL; int slice_header_length_in_bits = 0; unsigned int tail_data[] = { 0x0, 0x0 }; long head_offset; int old_used = intel_batchbuffer_used_size(slice_batch), used; unsigned short head_size, tail_size; int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type); if (rate_control_mode == VA_RC_CBR) { qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY; pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp; } /* only support for 8-bit pixel bit-depth */ assert(pSequenceParameter->bit_depth_luma_minus8 == 0); assert(pSequenceParameter->bit_depth_chroma_minus8 == 0); assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52); assert(qp >= 0 && qp < 52); head_offset = old_used / 16; gen8_mfc_avc_slice_state(ctx, pPicParameter, pSliceParameter, encode_state, encoder_context, (rate_control_mode == VA_RC_CBR), qp, slice_batch); if (slice_index == 0) intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header); // slice hander mfc_context->insert_object(ctx, encoder_context, (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f, 5, /* first 5 bytes are start code + nal unit type */ 1, 0, 1, slice_batch); free(slice_header); intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */ used = intel_batchbuffer_used_size(slice_batch); head_size = (used - old_used) / 16; old_used = used; /* tail */ if (last_slice) { mfc_context->insert_object(ctx, encoder_context, tail_data, 2, 8, 2, 1, 1, 0, slice_batch); } else { mfc_context->insert_object(ctx, encoder_context, tail_data, 1, 8, 1, 1, 1, 0, slice_batch); } intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */ used = intel_batchbuffer_used_size(slice_batch); tail_size = (used - old_used) / 16; gen8_mfc_avc_batchbuffer_slice_command(ctx, encoder_context, pSliceParameter, head_offset, head_size, tail_size, batchbuffer_offset, qp, last_slice); return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD; } static void gen8_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct intel_batchbuffer *batch = encoder_context->base.batch; int i, size, offset = 0; intel_batchbuffer_start_atomic(batch, 0x4000); gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch); for ( i = 0; i < encode_state->num_slice_params_ext; i++) { size = gen8_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset); offset += size; } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static void gen8_mfc_build_avc_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen8_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context); gen8_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context); gen8_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context); gen8_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context); } static dri_bo * gen8_mfc_avc_hardware_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; gen8_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context); dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo); return mfc_context->mfc_batchbuffer_surface.bo; } #endif static void gen8_mfc_avc_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; dri_bo *slice_batch_bo; if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) { fprintf(stderr, "Current VA driver don't support interlace mode!\n"); assert(0); return; } #ifdef MFC_SOFTWARE_HASWELL slice_batch_bo = gen8_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context); #else slice_batch_bo = gen8_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context); #endif // begin programing intel_batchbuffer_start_atomic_bcs(batch, 0x4000); intel_batchbuffer_emit_mi_flush(batch); // picture level programing gen8_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context); BEGIN_BCS_BATCH(batch, 3); OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0)); OUT_BCS_RELOC(batch, slice_batch_bo, I915_GEM_DOMAIN_COMMAND, 0, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); // end programing intel_batchbuffer_end_atomic(batch); dri_bo_unreference(slice_batch_bo); } static VAStatus gen8_mfc_avc_encode_picture(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; unsigned int rate_control_mode = encoder_context->rate_control_mode; int current_frame_bits_size; int sts; for (;;) { gen8_mfc_init(ctx, encode_state, encoder_context); intel_mfc_avc_prepare(ctx, encode_state, encoder_context); /*Programing bcs pipeline*/ gen8_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline gen8_mfc_run(ctx, encode_state, encoder_context); if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) { gen8_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size); sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size); if (sts == BRC_NO_HRD_VIOLATION) { intel_mfc_hrd_context_update(encode_state, mfc_context); break; } else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) { if (!mfc_context->hrd.violation_noted) { fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow"); mfc_context->hrd.violation_noted = 1; } return VA_STATUS_SUCCESS; } } else { break; } } return VA_STATUS_SUCCESS; } /* * MPEG-2 */ static const int va_to_gen8_mpeg2_picture_type[3] = { 1, /* I */ 2, /* P */ 3 /* B */ }; static void gen8_mfc_mpeg2_pic_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context, struct encode_state *encode_state) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncPictureParameterBufferMPEG2 *pic_param; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; VAEncSliceParameterBufferMPEG2 *slice_param = NULL; assert(encode_state->pic_param_ext && encode_state->pic_param_ext->buffer); pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer; BEGIN_BCS_BATCH(batch, 13); OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2)); OUT_BCS_BATCH(batch, (pic_param->f_code[1][1] & 0xf) << 28 | /* f_code[1][1] */ (pic_param->f_code[1][0] & 0xf) << 24 | /* f_code[1][0] */ (pic_param->f_code[0][1] & 0xf) << 20 | /* f_code[0][1] */ (pic_param->f_code[0][0] & 0xf) << 16 | /* f_code[0][0] */ pic_param->picture_coding_extension.bits.intra_dc_precision << 14 | pic_param->picture_coding_extension.bits.picture_structure << 12 | pic_param->picture_coding_extension.bits.top_field_first << 11 | pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 | pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 | pic_param->picture_coding_extension.bits.q_scale_type << 8 | pic_param->picture_coding_extension.bits.intra_vlc_format << 7 | pic_param->picture_coding_extension.bits.alternate_scan << 6); OUT_BCS_BATCH(batch, 0 << 14 | /* LoadSlicePointerFlag, 0 means only loading bitstream pointer once */ va_to_gen8_mpeg2_picture_type[pic_param->picture_type] << 9 | 0); OUT_BCS_BATCH(batch, 1 << 31 | /* slice concealment */ (height_in_mbs - 1) << 16 | (width_in_mbs - 1)); if (slice_param && slice_param->quantiser_scale_code >= 14) OUT_BCS_BATCH(batch, (3 << 1) | (1 << 4) | (5 << 8) | (1 << 12)); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0xFFF << 16 | /* InterMBMaxSize */ 0xFFF << 0 | /* IntraMBMaxSize */ 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfc_mpeg2_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned char intra_qm[64] = { 8, 16, 19, 22, 26, 27, 29, 34, 16, 16, 22, 24, 27, 29, 34, 37, 19, 22, 26, 27, 29, 34, 34, 38, 22, 22, 26, 27, 29, 34, 37, 40, 22, 26, 27, 29, 32, 35, 40, 48, 26, 27, 29, 32, 35, 40, 48, 58, 26, 27, 29, 34, 38, 46, 56, 69, 27, 29, 35, 38, 46, 56, 69, 83 }; unsigned char non_intra_qm[64] = { 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16 }; gen8_mfc_qm_state(ctx, MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX, (unsigned int *)intra_qm, 16, encoder_context); gen8_mfc_qm_state(ctx, MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX, (unsigned int *)non_intra_qm, 16,encoder_context); } static void gen8_mfc_mpeg2_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { unsigned short intra_fqm[64] = { 65536/0x8, 65536/0x10, 65536/0x13, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, 65536/0x10, 65536/0x10, 65536/0x16, 65536/0x16, 65536/0x1a, 65536/0x1b, 65536/0x1b, 65536/0x1d, 65536/0x13, 65536/0x16, 65536/0x1a, 65536/0x1a, 65536/0x1b, 65536/0x1d, 65536/0x1d, 65536/0x23, 65536/0x16, 65536/0x18, 65536/0x1b, 65536/0x1b, 65536/0x13, 65536/0x20, 65536/0x22, 65536/0x26, 65536/0x1a, 65536/0x1b, 65536/0x13, 65536/0x13, 65536/0x20, 65536/0x23, 65536/0x26, 65536/0x2e, 65536/0x1b, 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x23, 65536/0x28, 65536/0x2e, 65536/0x38, 65536/0x1d, 65536/0x22, 65536/0x22, 65536/0x25, 65536/0x28, 65536/0x30, 65536/0x38, 65536/0x45, 65536/0x22, 65536/0x25, 65536/0x26, 65536/0x28, 65536/0x30, 65536/0x3a, 65536/0x45, 65536/0x53, }; unsigned short non_intra_fqm[64] = { 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, }; gen8_mfc_fqm_state(ctx, MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX, (unsigned int *)intra_fqm, 32, encoder_context); gen8_mfc_fqm_state(ctx, MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX, (unsigned int *)non_intra_fqm, 32, encoder_context); } static void gen8_mfc_mpeg2_slicegroup_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context, int x, int y, int next_x, int next_y, int is_fisrt_slice_group, int is_last_slice_group, int intra_slice, int qp, struct intel_batchbuffer *batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, 8); OUT_BCS_BATCH(batch, MFC_MPEG2_SLICEGROUP_STATE | (8 - 2)); OUT_BCS_BATCH(batch, 0 << 31 | /* MbRateCtrlFlag */ !!is_last_slice_group << 19 | /* IsLastSliceGrp */ 1 << 17 | /* Insert Header before the first slice group data */ 1 << 16 | /* SliceData PresentFlag: always 1 */ 1 << 15 | /* TailPresentFlag: always 1 */ 0 << 14 | /* FirstSliceHdrDisabled: slice header for each slice */ !!intra_slice << 13 | /* IntraSlice */ !!intra_slice << 12 | /* IntraSliceFlag */ 0); OUT_BCS_BATCH(batch, next_y << 24 | next_x << 16 | y << 8 | x << 0 | 0); OUT_BCS_BATCH(batch, qp); /* FIXME: SliceGroupQp */ /* bitstream pointer is only loaded once for the first slice of a frame when * LoadSlicePointerFlag is 0 */ OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset); OUT_BCS_BATCH(batch, 0); /* FIXME: */ OUT_BCS_BATCH(batch, 0); /* FIXME: CorrectPoints */ OUT_BCS_BATCH(batch, 0); /* FIXME: CVxxx */ ADVANCE_BCS_BATCH(batch); } static int gen8_mfc_mpeg2_pak_object_intra(VADriverContextP ctx, struct intel_encoder_context *encoder_context, int x, int y, int first_mb_in_slice, int last_mb_in_slice, int first_mb_in_slice_group, int last_mb_in_slice_group, int mb_type, int qp_scale_code, int coded_block_pattern, unsigned char target_size_in_word, unsigned char max_size_in_word, struct intel_batchbuffer *batch) { int len_in_dwords = 9; if (batch == NULL) batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, len_in_dwords); OUT_BCS_BATCH(batch, MFC_MPEG2_PAK_OBJECT | (len_in_dwords - 2)); OUT_BCS_BATCH(batch, 0 << 24 | /* PackedMvNum */ 0 << 20 | /* MvFormat */ 7 << 17 | /* CbpDcY/CbpDcU/CbpDcV */ 0 << 15 | /* TransformFlag: frame DCT */ 0 << 14 | /* FieldMbFlag */ 1 << 13 | /* IntraMbFlag */ mb_type << 8 | /* MbType: Intra */ 0 << 2 | /* SkipMbFlag */ 0 << 0 | /* InterMbMode */ 0); OUT_BCS_BATCH(batch, y << 16 | x); OUT_BCS_BATCH(batch, max_size_in_word << 24 | target_size_in_word << 16 | coded_block_pattern << 6 | /* CBP */ 0); OUT_BCS_BATCH(batch, last_mb_in_slice << 31 | first_mb_in_slice << 30 | 0 << 27 | /* EnableCoeffClamp */ last_mb_in_slice_group << 26 | 0 << 25 | /* MbSkipConvDisable */ first_mb_in_slice_group << 24 | 0 << 16 | /* MvFieldSelect */ qp_scale_code << 0 | 0); OUT_BCS_BATCH(batch, 0); /* MV[0][0] */ OUT_BCS_BATCH(batch, 0); /* MV[1][0] */ OUT_BCS_BATCH(batch, 0); /* MV[0][1] */ OUT_BCS_BATCH(batch, 0); /* MV[1][1] */ ADVANCE_BCS_BATCH(batch); return len_in_dwords; } /* Byte offset */ #define MPEG2_INTER_MV_OFFSET 48 static struct _mv_ranges { int low; /* in the unit of 1/2 pixel */ int high; /* in the unit of 1/2 pixel */ } mv_ranges[] = { {0, 0}, {-16, 15}, {-32, 31}, {-64, 63}, {-128, 127}, {-256, 255}, {-512, 511}, {-1024, 1023}, {-2048, 2047}, {-4096, 4095} }; static int mpeg2_motion_vector(int mv, int pos, int display_max, int f_code) { if (mv + pos * 16 * 2 < 0 || mv + (pos + 1) * 16 * 2 > display_max * 2) mv = 0; if (f_code > 0 && f_code < 10) { if (mv < mv_ranges[f_code].low) mv = mv_ranges[f_code].low; if (mv > mv_ranges[f_code].high) mv = mv_ranges[f_code].high; } return mv; } static int gen8_mfc_mpeg2_pak_object_inter(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, unsigned int *msg, int width_in_mbs, int height_in_mbs, int x, int y, int first_mb_in_slice, int last_mb_in_slice, int first_mb_in_slice_group, int last_mb_in_slice_group, int qp_scale_code, unsigned char target_size_in_word, unsigned char max_size_in_word, struct intel_batchbuffer *batch) { VAEncPictureParameterBufferMPEG2 *pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; int len_in_dwords = 9; short *mvptr, mvx0, mvy0, mvx1, mvy1; if (batch == NULL) batch = encoder_context->base.batch; mvptr = (short *)((unsigned char *)msg + MPEG2_INTER_MV_OFFSET);; mvx0 = mpeg2_motion_vector(mvptr[0] / 2, x, width_in_mbs * 16, pic_param->f_code[0][0]); mvy0 = mpeg2_motion_vector(mvptr[1] / 2, y, height_in_mbs * 16, pic_param->f_code[0][0]); mvx1 = mpeg2_motion_vector(mvptr[2] / 2, x, width_in_mbs * 16, pic_param->f_code[1][0]); mvy1 = mpeg2_motion_vector(mvptr[3] / 2, y, height_in_mbs * 16, pic_param->f_code[1][0]); BEGIN_BCS_BATCH(batch, len_in_dwords); OUT_BCS_BATCH(batch, MFC_MPEG2_PAK_OBJECT | (len_in_dwords - 2)); OUT_BCS_BATCH(batch, 2 << 24 | /* PackedMvNum */ 7 << 20 | /* MvFormat */ 7 << 17 | /* CbpDcY/CbpDcU/CbpDcV */ 0 << 15 | /* TransformFlag: frame DCT */ 0 << 14 | /* FieldMbFlag */ 0 << 13 | /* IntraMbFlag */ 1 << 8 | /* MbType: Frame-based */ 0 << 2 | /* SkipMbFlag */ 0 << 0 | /* InterMbMode */ 0); OUT_BCS_BATCH(batch, y << 16 | x); OUT_BCS_BATCH(batch, max_size_in_word << 24 | target_size_in_word << 16 | 0x3f << 6 | /* CBP */ 0); OUT_BCS_BATCH(batch, last_mb_in_slice << 31 | first_mb_in_slice << 30 | 0 << 27 | /* EnableCoeffClamp */ last_mb_in_slice_group << 26 | 0 << 25 | /* MbSkipConvDisable */ first_mb_in_slice_group << 24 | 0 << 16 | /* MvFieldSelect */ qp_scale_code << 0 | 0); OUT_BCS_BATCH(batch, (mvx0 & 0xFFFF) | mvy0 << 16); /* MV[0][0] */ OUT_BCS_BATCH(batch, (mvx1 & 0xFFFF) | mvy1 << 16); /* MV[1][0] */ OUT_BCS_BATCH(batch, 0); /* MV[0][1] */ OUT_BCS_BATCH(batch, 0); /* MV[1][1] */ ADVANCE_BCS_BATCH(batch); return len_in_dwords; } static void intel_mfc_mpeg2_pipeline_header_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, struct intel_batchbuffer *slice_batch) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderMPEG2_SPS); if (encode_state->packed_header_data[idx]) { VAEncPackedHeaderParameterBuffer *param = NULL; unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer; unsigned int length_in_bits; assert(encode_state->packed_header_param[idx]); param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer; length_in_bits = param->bit_length; mfc_context->insert_object(ctx, encoder_context, header_data, ALIGN(length_in_bits, 32) >> 5, length_in_bits & 0x1f, 5, /* FIXME: check it */ 0, 0, 0, /* Needn't insert emulation bytes for MPEG-2 */ slice_batch); } idx = va_enc_packed_type_to_idx(VAEncPackedHeaderMPEG2_PPS); if (encode_state->packed_header_data[idx]) { VAEncPackedHeaderParameterBuffer *param = NULL; unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer; unsigned int length_in_bits; assert(encode_state->packed_header_param[idx]); param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer; length_in_bits = param->bit_length; mfc_context->insert_object(ctx, encoder_context, header_data, ALIGN(length_in_bits, 32) >> 5, length_in_bits & 0x1f, 5, /* FIXME: check it */ 0, 0, 0, /* Needn't insert emulation bytes for MPEG-2 */ slice_batch); } } static void gen8_mfc_mpeg2_pipeline_slice_group(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context, int slice_index, VAEncSliceParameterBufferMPEG2 *next_slice_group_param, struct intel_batchbuffer *slice_batch) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; VAEncSliceParameterBufferMPEG2 *slice_param = NULL; unsigned char tail_delimiter[] = {MPEG2_DELIMITER0, MPEG2_DELIMITER1, MPEG2_DELIMITER2, MPEG2_DELIMITER3, MPEG2_DELIMITER4, 0, 0, 0}; unsigned char section_delimiter[] = {0x0, 0x0, 0x0, 0x0}; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; int i, j; int h_start_pos, v_start_pos, h_next_start_pos, v_next_start_pos; unsigned int *msg = NULL; unsigned char *msg_ptr = NULL; slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[slice_index]->buffer; h_start_pos = slice_param->macroblock_address % width_in_mbs; v_start_pos = slice_param->macroblock_address / width_in_mbs; assert(h_start_pos + slice_param->num_macroblocks <= width_in_mbs); dri_bo_map(vme_context->vme_output.bo , 0); msg_ptr = (unsigned char *)vme_context->vme_output.bo->virtual; if (next_slice_group_param) { h_next_start_pos = next_slice_group_param->macroblock_address % width_in_mbs; v_next_start_pos = next_slice_group_param->macroblock_address / width_in_mbs; } else { h_next_start_pos = 0; v_next_start_pos = height_in_mbs; } gen8_mfc_mpeg2_slicegroup_state(ctx, encoder_context, h_start_pos, v_start_pos, h_next_start_pos, v_next_start_pos, slice_index == 0, next_slice_group_param == NULL, slice_param->is_intra_slice, slice_param->quantiser_scale_code, slice_batch); if (slice_index == 0) intel_mfc_mpeg2_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); /* Insert '00' to make sure the header is valid */ mfc_context->insert_object(ctx, encoder_context, (unsigned int*)section_delimiter, 1, 8, /* 8bits in the last DWORD */ 1, /* 1 byte */ 1, 0, 0, slice_batch); for (i = 0; i < encode_state->slice_params_ext[slice_index]->num_elements; i++) { /* PAK for each macroblocks */ for (j = 0; j < slice_param->num_macroblocks; j++) { int h_pos = (slice_param->macroblock_address + j) % width_in_mbs; int v_pos = (slice_param->macroblock_address + j) / width_in_mbs; int first_mb_in_slice = (j == 0); int last_mb_in_slice = (j == slice_param->num_macroblocks - 1); int first_mb_in_slice_group = (i == 0 && j == 0); int last_mb_in_slice_group = (i == encode_state->slice_params_ext[slice_index]->num_elements - 1 && j == slice_param->num_macroblocks - 1); msg = (unsigned int *)(msg_ptr + (slice_param->macroblock_address + j) * vme_context->vme_output.size_block); if (slice_param->is_intra_slice) { gen8_mfc_mpeg2_pak_object_intra(ctx, encoder_context, h_pos, v_pos, first_mb_in_slice, last_mb_in_slice, first_mb_in_slice_group, last_mb_in_slice_group, 0x1a, slice_param->quantiser_scale_code, 0x3f, 0, 0xff, slice_batch); } else { int inter_rdo, intra_rdo; inter_rdo = msg[AVC_INTER_RDO_OFFSET] & AVC_RDO_MASK; intra_rdo = msg[AVC_INTRA_RDO_OFFSET] & AVC_RDO_MASK; if (intra_rdo < inter_rdo) gen8_mfc_mpeg2_pak_object_intra(ctx, encoder_context, h_pos, v_pos, first_mb_in_slice, last_mb_in_slice, first_mb_in_slice_group, last_mb_in_slice_group, 0x1a, slice_param->quantiser_scale_code, 0x3f, 0, 0xff, slice_batch); else gen8_mfc_mpeg2_pak_object_inter(ctx, encode_state, encoder_context, msg, width_in_mbs, height_in_mbs, h_pos, v_pos, first_mb_in_slice, last_mb_in_slice, first_mb_in_slice_group, last_mb_in_slice_group, slice_param->quantiser_scale_code, 0, 0xff, slice_batch); } } slice_param++; } dri_bo_unmap(vme_context->vme_output.bo); /* tail data */ if (next_slice_group_param == NULL) { /* end of a picture */ mfc_context->insert_object(ctx, encoder_context, (unsigned int *)tail_delimiter, 2, 8, /* 8bits in the last DWORD */ 5, /* 5 bytes */ 1, 1, 0, slice_batch); } else { /* end of a lsice group */ mfc_context->insert_object(ctx, encoder_context, (unsigned int *)section_delimiter, 1, 8, /* 8bits in the last DWORD */ 1, /* 1 byte */ 1, 1, 0, slice_batch); } } /* * A batch buffer for all slices, including slice state, * slice insert object and slice pak object commands * */ static dri_bo * gen8_mfc_mpeg2_software_slice_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch; VAEncSliceParameterBufferMPEG2 *next_slice_group_param = NULL; dri_bo *batch_bo; int i; batch = mfc_context->aux_batchbuffer; batch_bo = batch->buffer; for (i = 0; i < encode_state->num_slice_params_ext; i++) { if (i == encode_state->num_slice_params_ext - 1) next_slice_group_param = NULL; else next_slice_group_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[i + 1]->buffer; gen8_mfc_mpeg2_pipeline_slice_group(ctx, encode_state, encoder_context, i, next_slice_group_param, batch); } intel_batchbuffer_align(batch, 8); BEGIN_BCS_BATCH(batch, 2); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END); ADVANCE_BCS_BATCH(batch); dri_bo_reference(batch_bo); intel_batchbuffer_free(batch); mfc_context->aux_batchbuffer = NULL; return batch_bo; } static void gen8_mfc_mpeg2_pipeline_picture_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; mfc_context->pipe_mode_select(ctx, MFX_FORMAT_MPEG2, encoder_context); mfc_context->set_surface_state(ctx, encoder_context); mfc_context->ind_obj_base_addr_state(ctx, encoder_context); gen8_mfc_pipe_buf_addr_state(ctx, encoder_context); gen8_mfc_bsp_buf_base_addr_state(ctx, encoder_context); gen8_mfc_mpeg2_pic_state(ctx, encoder_context, encode_state); gen8_mfc_mpeg2_qm_state(ctx, encoder_context); gen8_mfc_mpeg2_fqm_state(ctx, encoder_context); } static void gen8_mfc_mpeg2_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; dri_bo *slice_batch_bo; slice_batch_bo = gen8_mfc_mpeg2_software_slice_batchbuffer(ctx, encode_state, encoder_context); // begin programing intel_batchbuffer_start_atomic_bcs(batch, 0x4000); intel_batchbuffer_emit_mi_flush(batch); // picture level programing gen8_mfc_mpeg2_pipeline_picture_programing(ctx, encode_state, encoder_context); BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0)); OUT_BCS_RELOC(batch, slice_batch_bo, I915_GEM_DOMAIN_COMMAND, 0, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); // end programing intel_batchbuffer_end_atomic(batch); dri_bo_unreference(slice_batch_bo); } static VAStatus intel_mfc_mpeg2_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct object_surface *obj_surface; struct object_buffer *obj_buffer; struct i965_coded_buffer_segment *coded_buffer_segment; VAStatus vaStatus = VA_STATUS_SUCCESS; dri_bo *bo; int i; /* reconstructed surface */ obj_surface = encode_state->reconstructed_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); mfc_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(mfc_context->pre_deblocking_output.bo); mfc_context->surface_state.width = obj_surface->orig_width; mfc_context->surface_state.height = obj_surface->orig_height; mfc_context->surface_state.w_pitch = obj_surface->width; mfc_context->surface_state.h_pitch = obj_surface->height; /* forward reference */ obj_surface = encode_state->reference_objects[0]; if (obj_surface && obj_surface->bo) { mfc_context->reference_surfaces[0].bo = obj_surface->bo; dri_bo_reference(mfc_context->reference_surfaces[0].bo); } else mfc_context->reference_surfaces[0].bo = NULL; /* backward reference */ obj_surface = encode_state->reference_objects[1]; if (obj_surface && obj_surface->bo) { mfc_context->reference_surfaces[1].bo = obj_surface->bo; dri_bo_reference(mfc_context->reference_surfaces[1].bo); } else { mfc_context->reference_surfaces[1].bo = mfc_context->reference_surfaces[0].bo; if (mfc_context->reference_surfaces[1].bo) dri_bo_reference(mfc_context->reference_surfaces[1].bo); } for (i = 2; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) { mfc_context->reference_surfaces[i].bo = mfc_context->reference_surfaces[i & 1].bo; if (mfc_context->reference_surfaces[i].bo) dri_bo_reference(mfc_context->reference_surfaces[i].bo); } /* input YUV surface */ obj_surface = encode_state->input_yuv_object; mfc_context->uncompressed_picture_source.bo = obj_surface->bo; dri_bo_reference(mfc_context->uncompressed_picture_source.bo); /* coded buffer */ obj_buffer = encode_state->coded_buf_object; bo = obj_buffer->buffer_store->bo; mfc_context->mfc_indirect_pak_bse_object.bo = bo; mfc_context->mfc_indirect_pak_bse_object.offset = I965_CODEDBUFFER_HEADER_SIZE; mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN(obj_buffer->size_element - 0x1000, 0x1000); dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo); /* set the internal flag to 0 to indicate the coded size is unknown */ dri_bo_map(bo, 1); coded_buffer_segment = (struct i965_coded_buffer_segment *)bo->virtual; coded_buffer_segment->mapped = 0; coded_buffer_segment->codec = encoder_context->codec; dri_bo_unmap(bo); return vaStatus; } static VAStatus gen8_mfc_mpeg2_encode_picture(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen8_mfc_init(ctx, encode_state, encoder_context); intel_mfc_mpeg2_prepare(ctx, encode_state, encoder_context); /*Programing bcs pipeline*/ gen8_mfc_mpeg2_pipeline_programing(ctx, encode_state, encoder_context); gen8_mfc_run(ctx, encode_state, encoder_context); return VA_STATUS_SUCCESS; } static void gen8_mfc_context_destroy(void *context) { struct gen6_mfc_context *mfc_context = context; int i; dri_bo_unreference(mfc_context->post_deblocking_output.bo); mfc_context->post_deblocking_output.bo = NULL; dri_bo_unreference(mfc_context->pre_deblocking_output.bo); mfc_context->pre_deblocking_output.bo = NULL; dri_bo_unreference(mfc_context->uncompressed_picture_source.bo); mfc_context->uncompressed_picture_source.bo = NULL; dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo); mfc_context->mfc_indirect_pak_bse_object.bo = NULL; for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){ dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo); mfc_context->direct_mv_buffers[i].bo = NULL; } dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo); mfc_context->intra_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(mfc_context->macroblock_status_buffer.bo); mfc_context->macroblock_status_buffer.bo = NULL; dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo); mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo); mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){ dri_bo_unreference(mfc_context->reference_surfaces[i].bo); mfc_context->reference_surfaces[i].bo = NULL; } i965_gpe_context_destroy(&mfc_context->gpe_context); dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo); mfc_context->mfc_batchbuffer_surface.bo = NULL; dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo); mfc_context->aux_batchbuffer_surface.bo = NULL; if (mfc_context->aux_batchbuffer) intel_batchbuffer_free(mfc_context->aux_batchbuffer); mfc_context->aux_batchbuffer = NULL; free(mfc_context); } static VAStatus gen8_mfc_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { VAStatus vaStatus; switch (profile) { case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: vaStatus = gen8_mfc_avc_encode_picture(ctx, encode_state, encoder_context); break; /* FIXME: add for other profile */ case VAProfileMPEG2Simple: case VAProfileMPEG2Main: vaStatus = gen8_mfc_mpeg2_encode_picture(ctx, encode_state, encoder_context); break; default: vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE; break; } return vaStatus; } Bool gen8_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context)); mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS; mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data); mfc_context->gpe_context.curbe.length = 32 * 4; mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1; mfc_context->gpe_context.vfe_state.num_urb_entries = 16; mfc_context->gpe_context.vfe_state.gpgpu_mode = 0; mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1; mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1; i965_gpe_load_kernels(ctx, &mfc_context->gpe_context, gen8_mfc_kernels, NUM_MFC_KERNEL); mfc_context->pipe_mode_select = gen8_mfc_pipe_mode_select; mfc_context->set_surface_state = gen8_mfc_surface_state; mfc_context->ind_obj_base_addr_state = gen8_mfc_ind_obj_base_addr_state; mfc_context->avc_img_state = gen8_mfc_avc_img_state; mfc_context->avc_qm_state = gen8_mfc_avc_qm_state; mfc_context->avc_fqm_state = gen8_mfc_avc_fqm_state; mfc_context->insert_object = gen8_mfc_avc_insert_object; mfc_context->buffer_suface_setup = gen8_gpe_buffer_suface_setup; encoder_context->mfc_context = mfc_context; encoder_context->mfc_context_destroy = gen8_mfc_context_destroy; encoder_context->mfc_pipeline = gen8_mfc_pipeline; encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare; return True; } intel-driver-1.3.0/src/gen8_mfd.c000066400000000000000000003715241231401140700165460ustar00rootroot00000000000000/* * Copyright © 2011 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * Zhao Yakui * */ #include #include #include #include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_decoder_utils.h" #include "gen7_mfd.h" #include "intel_media.h" #define B0_STEP_REV 2 #define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV) static const uint32_t zigzag_direct[64] = { 0, 1, 8, 16, 9, 2, 3, 10, 17, 24, 32, 25, 18, 11, 4, 5, 12, 19, 26, 33, 40, 48, 41, 34, 27, 20, 13, 6, 7, 14, 21, 28, 35, 42, 49, 56, 57, 50, 43, 36, 29, 22, 15, 23, 30, 37, 44, 51, 58, 59, 52, 45, 38, 31, 39, 46, 53, 60, 61, 54, 47, 55, 62, 63 }; static void gen8_mfd_init_avc_surface(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, struct object_surface *obj_surface) { struct i965_driver_data *i965 = i965_driver_data(ctx); GenAvcSurface *gen7_avc_surface = obj_surface->private_data; int width_in_mbs, height_in_mbs; obj_surface->free_private_data = gen_free_avc_surface; width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */ if (!gen7_avc_surface) { gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1); assert((obj_surface->size & 0x3f) == 0); obj_surface->private_data = gen7_avc_surface; } gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag && !pic_param->seq_fields.bits.direct_8x8_inference_flag); if (gen7_avc_surface->dmv_top == NULL) { gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", width_in_mbs * height_in_mbs * 128, 0x1000); assert(gen7_avc_surface->dmv_top); } if (gen7_avc_surface->dmv_bottom_flag && gen7_avc_surface->dmv_bottom == NULL) { gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", width_in_mbs * height_in_mbs * 128, 0x1000); assert(gen7_avc_surface->dmv_bottom); } } static void gen8_mfd_pipe_mode_select(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; assert(standard_select == MFX_FORMAT_MPEG2 || standard_select == MFX_FORMAT_AVC || standard_select == MFX_FORMAT_VC1 || standard_select == MFX_FORMAT_JPEG || standard_select == MFX_FORMAT_VP8); BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2)); OUT_BCS_BATCH(batch, (MFX_LONG_MODE << 17) | /* Currently only support long format */ (MFD_MODE_VLD << 15) | /* VLD mode */ (0 << 10) | /* disable Stream-Out */ (gen7_mfd_context->post_deblocking_output.valid << 9) | /* Post Deblocking Output */ (gen7_mfd_context->pre_deblocking_output.valid << 8) | /* Pre Deblocking Output */ (0 << 5) | /* not in stitch mode */ (MFX_CODEC_DECODE << 4) | /* decoding mode */ (standard_select << 0)); OUT_BCS_BATCH(batch, (0 << 4) | /* terminate if AVC motion and POC table error occurs */ (0 << 3) | /* terminate if AVC mbdata error occurs */ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ (0 << 1) | (0 << 0)); OUT_BCS_BATCH(batch, 0); /* pic status/error report id */ OUT_BCS_BATCH(batch, 0); /* reserved */ ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_surface_state(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct object_surface *obj_surface = decode_state->render_object; unsigned int y_cb_offset; unsigned int y_cr_offset; assert(obj_surface); y_cb_offset = obj_surface->y_cb_offset; y_cr_offset = obj_surface->y_cr_offset; BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, ((obj_surface->orig_height - 1) << 18) | ((obj_surface->orig_width - 1) << 4)); OUT_BCS_BATCH(batch, (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */ (0 << 22) | /* surface object control state, ignored */ ((obj_surface->width - 1) << 3) | /* pitch */ (0 << 2) | /* must be 0 */ (1 << 1) | /* must be tiled */ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */ OUT_BCS_BATCH(batch, (0 << 16) | /* X offset for U(Cb), must be 0 */ (y_cb_offset << 0)); /* Y offset for U(Cb) */ OUT_BCS_BATCH(batch, (0 << 16) | /* X offset for V(Cr), must be 0 */ (y_cr_offset << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */ ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_pipe_buf_addr_state(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int i; BEGIN_BCS_BATCH(batch, 61); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2)); /* Pre-deblock 1-3 */ if (gen7_mfd_context->pre_deblocking_output.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* Post-debloing 4-6 */ if (gen7_mfd_context->post_deblocking_output.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* uncompressed-video & stream out 7-12 */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* intra row-store scratch 13-15 */ if (gen7_mfd_context->intra_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* deblocking-filter-row-store 16-18 */ if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* DW 19..50 */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { struct object_surface *obj_surface; if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID && gen7_mfd_context->reference_surface[i].obj_surface && gen7_mfd_context->reference_surface[i].obj_surface->bo) { obj_surface = gen7_mfd_context->reference_surface[i].obj_surface; OUT_BCS_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } else { OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); } /* reference property 51 */ OUT_BCS_BATCH(batch, 0); /* Macroblock status & ILDB 52-57 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the second Macroblock status 58-60 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_ind_obj_base_addr_state(VADriverContextP ctx, dri_bo *slice_data_bo, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 26); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2)); /* MFX In BS 1-5 */ OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* Upper bound 4-5 */ OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ OUT_BCS_BATCH(batch, 0); /* MFX indirect MV 6-10 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* MFX IT_COFF 11-15 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* MFX IT_DBLK 16-20 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* MFX PAK_BSE object for encoder 21-25 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_bsp_buf_base_addr_state(VADriverContextP ctx, struct decode_state *decode_state, int standard_select, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2)); if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* MPR Row Store Scratch buffer 4-6 */ if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* Bitplane 7-9 */ if (gen7_mfd_context->bitplane_read_buffer.valid) OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_qm_state(VADriverContextP ctx, int qm_type, unsigned char *qm, int qm_length, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; unsigned int qm_buffer[16]; assert(qm_length <= 16 * 4); memcpy(qm_buffer, qm, qm_length); BEGIN_BCS_BATCH(batch, 18); OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2)); OUT_BCS_BATCH(batch, qm_type << 0); intel_batchbuffer_data(batch, qm_buffer, 16 * 4); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_avc_img_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int img_struct; int mbaff_frame_flag; unsigned int width_in_mbs, height_in_mbs; VAPictureParameterBufferH264 *pic_param; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID)); if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD) img_struct = 1; else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD) img_struct = 3; else img_struct = 0; if ((img_struct & 0x1) == 0x1) { assert(pic_param->pic_fields.bits.field_pic_flag == 0x1); } else { assert(pic_param->pic_fields.bits.field_pic_flag == 0x0); } if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */ assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0); assert(pic_param->pic_fields.bits.field_pic_flag == 0); } else { assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */ } mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag && !pic_param->pic_fields.bits.field_pic_flag); width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */ /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */ assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */ pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */ assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */ BEGIN_BCS_BATCH(batch, 17); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (17 - 2)); OUT_BCS_BATCH(batch, (width_in_mbs * height_in_mbs - 1)); OUT_BCS_BATCH(batch, ((height_in_mbs - 1) << 16) | ((width_in_mbs - 1) << 0)); OUT_BCS_BATCH(batch, ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) | ((pic_param->chroma_qp_index_offset & 0x1f) << 16) | (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */ (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */ (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */ (pic_param->pic_fields.bits.weighted_bipred_idc << 10) | (img_struct << 8)); OUT_BCS_BATCH(batch, (pic_param->seq_fields.bits.chroma_format_idc << 10) | (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) | ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) | (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) | (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) | (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) | (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) | (mbaff_frame_flag << 1) | (pic_param->pic_fields.bits.field_pic_flag << 0)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_avc_qm_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAIQMatrixBufferH264 *iq_matrix; VAPictureParameterBufferH264 *pic_param; if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer; else iq_matrix = &gen7_mfd_context->iq_matrix.h264; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; gen8_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context); gen8_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context); if (pic_param->pic_fields.bits.transform_8x8_mode_flag) { gen8_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context); gen8_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context); } } static void gen8_mfd_avc_picid_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFD_AVC_PICID_STATE | (10 - 2)); OUT_BCS_BATCH(batch, 1); // disable Picture ID Remapping OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_avc_directmode_state(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct object_surface *obj_surface; GenAvcSurface *gen7_avc_surface; VAPictureH264 *va_pic; int i, j; BEGIN_BCS_BATCH(batch, 71); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2)); /* reference surfaces 0..15 */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID && gen7_mfd_context->reference_surface[i].obj_surface && gen7_mfd_context->reference_surface[i].obj_surface->private_data) { obj_surface = gen7_mfd_context->reference_surface[i].obj_surface; gen7_avc_surface = obj_surface->private_data; OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } OUT_BCS_BATCH(batch, 0); /* the current decoding frame/field */ va_pic = &pic_param->CurrPic; obj_surface = decode_state->render_object; assert(obj_surface->bo && obj_surface->private_data); gen7_avc_surface = obj_surface->private_data; OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* POC List */ for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) { int found = 0; assert(gen7_mfd_context->reference_surface[i].obj_surface != NULL); for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) { va_pic = &pic_param->ReferenceFrames[j]; if (va_pic->flags & VA_PICTURE_H264_INVALID) continue; if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) { found = 1; break; } } assert(found == 1); assert(!(va_pic->flags & VA_PICTURE_H264_INVALID)); OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt); OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } va_pic = &pic_param->CurrPic; OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt); OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_avc_slice_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, VASliceParameterBufferH264 *next_slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos; int num_ref_idx_l0, num_ref_idx_l1; int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag && pic_param->seq_fields.bits.mb_adaptive_frame_field_flag); int first_mb_in_slice = 0, first_mb_in_next_slice = 0; int slice_type; if (slice_param->slice_type == SLICE_TYPE_I || slice_param->slice_type == SLICE_TYPE_SI) { slice_type = SLICE_TYPE_I; } else if (slice_param->slice_type == SLICE_TYPE_P || slice_param->slice_type == SLICE_TYPE_SP) { slice_type = SLICE_TYPE_P; } else { assert(slice_param->slice_type == SLICE_TYPE_B); slice_type = SLICE_TYPE_B; } if (slice_type == SLICE_TYPE_I) { assert(slice_param->num_ref_idx_l0_active_minus1 == 0); assert(slice_param->num_ref_idx_l1_active_minus1 == 0); num_ref_idx_l0 = 0; num_ref_idx_l1 = 0; } else if (slice_type == SLICE_TYPE_P) { assert(slice_param->num_ref_idx_l1_active_minus1 == 0); num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = 0; } else { num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1; } first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture; slice_hor_pos = first_mb_in_slice % width_in_mbs; slice_ver_pos = first_mb_in_slice / width_in_mbs; if (next_slice_param) { first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture; next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs; next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs; } else { next_slice_hor_pos = 0; next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag); } BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */ OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2)); OUT_BCS_BATCH(batch, slice_type); OUT_BCS_BATCH(batch, (num_ref_idx_l1 << 24) | (num_ref_idx_l0 << 16) | (slice_param->chroma_log2_weight_denom << 8) | (slice_param->luma_log2_weight_denom << 0)); OUT_BCS_BATCH(batch, (slice_param->direct_spatial_mv_pred_flag << 29) | (slice_param->disable_deblocking_filter_idc << 27) | (slice_param->cabac_init_idc << 24) | ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) | ((slice_param->slice_beta_offset_div2 & 0xf) << 8) | ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0)); OUT_BCS_BATCH(batch, (slice_ver_pos << 24) | (slice_hor_pos << 16) | (first_mb_in_slice << 0)); OUT_BCS_BATCH(batch, (next_slice_ver_pos << 16) | (next_slice_hor_pos << 0)); OUT_BCS_BATCH(batch, (next_slice_param == NULL) << 19); /* last slice flag */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static inline void gen8_mfd_avc_ref_idx_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen7_mfd_context *gen7_mfd_context) { gen6_send_avc_ref_idx_state( gen7_mfd_context->base.batch, slice_param, gen7_mfd_context->reference_surface ); } static void gen8_mfd_avc_weightoffset_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int i, j, num_weight_offset_table = 0; short weightoffsets[32 * 6]; if ((slice_param->slice_type == SLICE_TYPE_P || slice_param->slice_type == SLICE_TYPE_SP) && (pic_param->pic_fields.bits.weighted_pred_flag == 1)) { num_weight_offset_table = 1; } if ((slice_param->slice_type == SLICE_TYPE_B) && (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) { num_weight_offset_table = 2; } for (i = 0; i < num_weight_offset_table; i++) { BEGIN_BCS_BATCH(batch, 98); OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2)); OUT_BCS_BATCH(batch, i); if (i == 0) { for (j = 0; j < 32; j++) { weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j]; weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j]; weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0]; weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0]; weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1]; weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1]; } } else { for (j = 0; j < 32; j++) { weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j]; weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j]; weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0]; weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0]; weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1]; weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1]; } } intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets)); ADVANCE_BCS_BATCH(batch); } } static void gen8_mfd_avc_bsd_object(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, dri_bo *slice_data_bo, VASliceParameterBufferH264 *next_slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int slice_data_bit_offset = avc_get_first_mb_bit_offset(slice_data_bo, slice_param, pic_param->pic_fields.bits.entropy_coding_mode_flag); /* the input bitsteam format on GEN7 differs from GEN6 */ BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2)); OUT_BCS_BATCH(batch, (slice_param->slice_data_size)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset); OUT_BCS_BATCH(batch, (0 << 31) | (0 << 14) | (0 << 12) | (0 << 10) | (0 << 8)); OUT_BCS_BATCH(batch, ((slice_data_bit_offset >> 3) << 16) | (1 << 7) | (0 << 5) | (0 << 4) | ((next_slice_param == NULL) << 3) | /* LastSlice Flag */ (slice_data_bit_offset & 0x7)); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static inline void gen8_mfd_avc_context_init( VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context ) { /* Initialize flat scaling lists */ avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264); } static void gen8_mfd_avc_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAPictureParameterBufferH264 *pic_param; VASliceParameterBufferH264 *slice_param; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *bo; int i, j, enable_avc_ildb = 0; unsigned int width_in_mbs, height_in_mbs; for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); assert((slice_param->slice_type == SLICE_TYPE_I) || (slice_param->slice_type == SLICE_TYPE_SI) || (slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP) || (slice_param->slice_type == SLICE_TYPE_B)); if (slice_param->disable_deblocking_filter_idc != 1) { enable_avc_ildb = 1; break; } slice_param++; } } assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; intel_update_avc_frame_store_index(ctx, decode_state, pic_param, gen7_mfd_context->reference_surface); width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */ assert(height_in_mbs > 0 && height_in_mbs <= 256); /* Current decoded picture */ obj_surface = decode_state->render_object; obj_surface->flags &= ~SURFACE_REF_DIS_MASK; obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0); i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); /* initial uv component for YUV400 case */ if (pic_param->seq_fields.bits.chroma_format_idc == 0) { unsigned int uv_offset = obj_surface->width * obj_surface->height; unsigned int uv_size = obj_surface->width * obj_surface->height / 2; drm_intel_gem_bo_map_gtt(obj_surface->bo); memset(obj_surface->bo->virtual + uv_offset, 0x80, uv_size); drm_intel_gem_bo_unmap_gtt(obj_surface->bo); } gen8_mfd_init_avc_surface(ctx, pic_param, obj_surface); dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb; dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb; dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", width_in_mbs * 64, 0x1000); assert(bo); gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "deblocking filter row store", width_in_mbs * 64 * 4, 0x1000); assert(bo); gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 64 * 2, 0x1000); assert(bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "mpr row store", width_in_mbs * 64 * 2, 0x1000); assert(bo); gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1; gen7_mfd_context->bitplane_read_buffer.valid = 0; } static void gen8_mfd_avc_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferH264 *pic_param; VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; gen8_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen8_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context); gen8_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context); gen8_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context); gen8_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context); gen8_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context); gen8_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context); gen8_mfd_avc_picid_state(ctx, decode_state, gen7_mfd_context); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen8_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); assert((slice_param->slice_type == SLICE_TYPE_I) || (slice_param->slice_type == SLICE_TYPE_SI) || (slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP) || (slice_param->slice_type == SLICE_TYPE_B)); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen8_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen7_mfd_context); gen8_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context); gen8_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context); gen8_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context); gen8_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static void gen8_mfd_mpeg2_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAPictureParameterBufferMPEG2 *pic_param; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *bo; unsigned int width_in_mbs; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16; mpeg2_set_reference_surfaces( ctx, gen7_mfd_context->reference_surface, decode_state, pic_param ); /* Current decoded picture */ obj_surface = decode_state->render_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = 1; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 96, 0x1000); assert(bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; gen7_mfd_context->post_deblocking_output.valid = 0; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0; gen7_mfd_context->bitplane_read_buffer.valid = 0; } static void gen8_mfd_mpeg2_pic_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferMPEG2 *pic_param; unsigned int slice_concealment_disable_bit = 0; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; slice_concealment_disable_bit = 1; BEGIN_BCS_BATCH(batch, 13); OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2)); OUT_BCS_BATCH(batch, (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */ ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */ ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */ ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */ pic_param->picture_coding_extension.bits.intra_dc_precision << 14 | pic_param->picture_coding_extension.bits.picture_structure << 12 | pic_param->picture_coding_extension.bits.top_field_first << 11 | pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 | pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 | pic_param->picture_coding_extension.bits.q_scale_type << 8 | pic_param->picture_coding_extension.bits.intra_vlc_format << 7 | pic_param->picture_coding_extension.bits.alternate_scan << 6); OUT_BCS_BATCH(batch, pic_param->picture_coding_type << 9); OUT_BCS_BATCH(batch, (slice_concealment_disable_bit << 31) | ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 | ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_mpeg2_qm_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2; int i, j; /* Update internal QM state */ if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) { VAIQMatrixBufferMPEG2 * const iq_matrix = (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer; if (gen_iq_matrix->load_intra_quantiser_matrix == -1 || iq_matrix->load_intra_quantiser_matrix) { gen_iq_matrix->load_intra_quantiser_matrix = iq_matrix->load_intra_quantiser_matrix; if (iq_matrix->load_intra_quantiser_matrix) { for (j = 0; j < 64; j++) gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] = iq_matrix->intra_quantiser_matrix[j]; } } if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 || iq_matrix->load_non_intra_quantiser_matrix) { gen_iq_matrix->load_non_intra_quantiser_matrix = iq_matrix->load_non_intra_quantiser_matrix; if (iq_matrix->load_non_intra_quantiser_matrix) { for (j = 0; j < 64; j++) gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] = iq_matrix->non_intra_quantiser_matrix[j]; } } } /* Commit QM state to HW */ for (i = 0; i < 2; i++) { unsigned char *qm = NULL; int qm_type; if (i == 0) { if (gen_iq_matrix->load_intra_quantiser_matrix) { qm = gen_iq_matrix->intra_quantiser_matrix; qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX; } } else { if (gen_iq_matrix->load_non_intra_quantiser_matrix) { qm = gen_iq_matrix->non_intra_quantiser_matrix; qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX; } } if (!qm) continue; gen8_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context); } } static void gen8_mfd_mpeg2_bsd_object(VADriverContextP ctx, VAPictureParameterBufferMPEG2 *pic_param, VASliceParameterBufferMPEG2 *slice_param, VASliceParameterBufferMPEG2 *next_slice_param, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16; int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0; if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD || pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD) is_field_pic = 1; is_field_pic_wa = is_field_pic && gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0; vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa); hpos0 = slice_param->slice_horizontal_position; if (next_slice_param == NULL) { vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic); hpos1 = 0; } else { vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa); hpos1 = next_slice_param->slice_horizontal_position; } mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0); BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2)); OUT_BCS_BATCH(batch, slice_param->slice_data_size - (slice_param->macroblock_offset >> 3)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3)); OUT_BCS_BATCH(batch, hpos0 << 24 | vpos0 << 16 | mb_count << 8 | (next_slice_param == NULL) << 5 | (next_slice_param == NULL) << 3 | (slice_param->macroblock_offset & 0x7)); OUT_BCS_BATCH(batch, (slice_param->quantiser_scale_code << 24) | (vpos1 << 8 | hpos1)); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_mpeg2_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferMPEG2 *pic_param; VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; gen8_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen8_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context); gen8_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context); gen8_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context); gen8_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context); gen8_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context); gen8_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context); if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0) gen7_mfd_context->wa_mpeg2_slice_vertical_position = mpeg2_wa_slice_vertical_position(decode_state, pic_param); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen8_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen8_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static const int va_to_gen7_vc1_pic_type[5] = { GEN7_VC1_I_PICTURE, GEN7_VC1_P_PICTURE, GEN7_VC1_B_PICTURE, GEN7_VC1_BI_PICTURE, GEN7_VC1_P_PICTURE, }; static const int va_to_gen7_vc1_mv[4] = { 1, /* 1-MV */ 2, /* 1-MV half-pel */ 3, /* 1-MV half-pef bilinear */ 0, /* Mixed MV */ }; static const int b_picture_scale_factor[21] = { 128, 85, 170, 64, 192, 51, 102, 153, 204, 43, 215, 37, 74, 111, 148, 185, 222, 32, 96, 160, 224, }; static const int va_to_gen7_vc1_condover[3] = { 0, 2, 3 }; static const int va_to_gen7_vc1_profile[4] = { GEN7_VC1_SIMPLE_PROFILE, GEN7_VC1_MAIN_PROFILE, GEN7_VC1_RESERVED_PROFILE, GEN7_VC1_ADVANCED_PROFILE }; static void gen8_mfd_free_vc1_surface(void **data) { struct gen7_vc1_surface *gen7_vc1_surface = *data; if (!gen7_vc1_surface) return; dri_bo_unreference(gen7_vc1_surface->dmv); free(gen7_vc1_surface); *data = NULL; } static void gen8_mfd_init_vc1_surface(VADriverContextP ctx, VAPictureParameterBufferVC1 *pic_param, struct object_surface *obj_surface) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data; int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16; obj_surface->free_private_data = gen8_mfd_free_vc1_surface; if (!gen7_vc1_surface) { gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1); assert((obj_surface->size & 0x3f) == 0); obj_surface->private_data = gen7_vc1_surface; } gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type; if (gen7_vc1_surface->dmv == NULL) { gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", width_in_mbs * height_in_mbs * 64, 0x1000); } } static void gen8_mfd_vc1_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAPictureParameterBufferVC1 *pic_param; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; dri_bo *bo; int width_in_mbs; int picture_type; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; picture_type = pic_param->picture_fields.bits.picture_type; intel_update_vc1_frame_store_index(ctx, decode_state, pic_param, gen7_mfd_context->reference_surface); /* Current decoded picture */ obj_surface = decode_state->render_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); gen8_mfd_init_vc1_surface(ctx, pic_param, obj_surface); dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter; dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter; dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", width_in_mbs * 64, 0x1000); assert(bo); gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "deblocking filter row store", width_in_mbs * 7 * 64, 0x1000); assert(bo); gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 96, 0x1000); assert(bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0; gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value; dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo); if (gen7_mfd_context->bitplane_read_buffer.valid) { int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16; int bitplane_width = ALIGN(width_in_mbs, 2) / 2; int src_w, src_h; uint8_t *src = NULL, *dst = NULL; assert(decode_state->bit_plane->buffer); src = decode_state->bit_plane->buffer; bo = dri_bo_alloc(i965->intel.bufmgr, "VC-1 Bitplane", bitplane_width * height_in_mbs, 0x1000); assert(bo); gen7_mfd_context->bitplane_read_buffer.bo = bo; dri_bo_map(bo, True); assert(bo->virtual); dst = bo->virtual; for (src_h = 0; src_h < height_in_mbs; src_h++) { for(src_w = 0; src_w < width_in_mbs; src_w++) { int src_index, dst_index; int src_shift; uint8_t src_value; src_index = (src_h * width_in_mbs + src_w) / 2; src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4; src_value = ((src[src_index] >> src_shift) & 0xf); if (picture_type == GEN7_VC1_SKIPPED_PICTURE){ src_value |= 0x2; } dst_index = src_w / 2; dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4)); } if (src_w & 1) dst[src_w / 2] >>= 4; dst += bitplane_width; } dri_bo_unmap(bo); } else gen7_mfd_context->bitplane_read_buffer.bo = NULL; } static void gen8_mfd_vc1_pic_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferVC1 *pic_param; struct object_surface *obj_surface; int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq; int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel; int unified_mv_mode; int ref_field_pic_polarity = 0; int scale_factor = 0; int trans_ac_y = 0; int dmv_surface_valid = 0; int brfd = 0; int fcm = 0; int picture_type; int profile; int overlap; int interpolation_mode = 0; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile]; dquant = pic_param->pic_quantizer_fields.bits.dquant; dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame; dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile; dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge; dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge; dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level; alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer; if (dquant == 0) { alt_pquant_config = 0; alt_pquant_edge_mask = 0; } else if (dquant == 2) { alt_pquant_config = 1; alt_pquant_edge_mask = 0xf; } else { assert(dquant == 1); if (dquantfrm == 0) { alt_pquant_config = 0; alt_pquant_edge_mask = 0; alt_pq = 0; } else { assert(dquantfrm == 1); alt_pquant_config = 1; switch (dqprofile) { case 3: if (dqbilevel == 0) { alt_pquant_config = 2; alt_pquant_edge_mask = 0; } else { assert(dqbilevel == 1); alt_pquant_config = 3; alt_pquant_edge_mask = 0; } break; case 0: alt_pquant_edge_mask = 0xf; break; case 1: if (dqdbedge == 3) alt_pquant_edge_mask = 0x9; else alt_pquant_edge_mask = (0x3 << dqdbedge); break; case 2: alt_pquant_edge_mask = (0x1 << dqsbedge); break; default: assert(0); } } } if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) { assert(pic_param->mv_fields.bits.mv_mode2 < 4); unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2]; } else { assert(pic_param->mv_fields.bits.mv_mode < 4); unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode]; } if (pic_param->sequence_fields.bits.interlace == 1 && pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */ /* FIXME: calculate reference field picture polarity */ assert(0); ref_field_pic_polarity = 0; } if (pic_param->b_picture_fraction < 21) scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction]; picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type]; if (profile == GEN7_VC1_ADVANCED_PROFILE && picture_type == GEN7_VC1_I_PICTURE) picture_type = GEN7_VC1_BI_PICTURE; if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */ trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2; else { trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1; /* * 8.3.6.2.1 Transform Type Selection * If variable-sized transform coding is not enabled, * then the 8x8 transform shall be used for all blocks. * it is also MFX_VC1_PIC_STATE requirement. */ if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) { pic_param->transform_fields.bits.mb_level_transform_type_flag = 1; pic_param->transform_fields.bits.frame_level_transform_type = 0; } } if (picture_type == GEN7_VC1_B_PICTURE) { struct gen7_vc1_surface *gen7_vc1_surface = NULL; obj_surface = decode_state->reference_objects[1]; if (obj_surface) gen7_vc1_surface = obj_surface->private_data; if (!gen7_vc1_surface || (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE || va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE)) dmv_surface_valid = 0; else dmv_surface_valid = 1; } assert(pic_param->picture_fields.bits.frame_coding_mode < 3); if (pic_param->picture_fields.bits.frame_coding_mode < 2) fcm = pic_param->picture_fields.bits.frame_coding_mode; else { if (pic_param->picture_fields.bits.top_field_first) fcm = 2; else fcm = 3; } if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */ brfd = pic_param->reference_fields.bits.reference_distance; brfd = (scale_factor * brfd) >> 8; brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1; if (brfd < 0) brfd = 0; } overlap = 0; if (profile != GEN7_VC1_ADVANCED_PROFILE){ if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 && pic_param->picture_fields.bits.picture_type != GEN7_VC1_B_PICTURE) { overlap = 1; } }else { if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_P_PICTURE && pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){ overlap = 1; } if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_I_PICTURE || pic_param->picture_fields.bits.picture_type == GEN7_VC1_BI_PICTURE){ if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){ overlap = 1; } else if (va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 2 || va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 3) { overlap = 1; } } } assert(pic_param->conditional_overlap_flag < 3); assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */ if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear || (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation && pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear)) interpolation_mode = 9; /* Half-pel bilinear */ else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel || (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation && pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel)) interpolation_mode = 1; /* Half-pel bicubic */ else interpolation_mode = 0; /* Quarter-pel bicubic */ BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2)); OUT_BCS_BATCH(batch, (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) | ((ALIGN(pic_param->coded_width, 16) / 16) - 1)); OUT_BCS_BATCH(batch, ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 | dmv_surface_valid << 15 | (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */ pic_param->rounding_control << 13 | pic_param->sequence_fields.bits.syncmarker << 12 | interpolation_mode << 8 | 0 << 7 | /* FIXME: scale up or down ??? */ pic_param->range_reduction_frame << 6 | pic_param->entrypoint_fields.bits.loopfilter << 5 | overlap << 4 | !pic_param->picture_fields.bits.is_first_field << 3 | (pic_param->sequence_fields.bits.profile == 3) << 0); OUT_BCS_BATCH(batch, va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 | picture_type << 26 | fcm << 24 | alt_pq << 16 | pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 | scale_factor << 0); OUT_BCS_BATCH(batch, unified_mv_mode << 28 | pic_param->mv_fields.bits.four_mv_switch << 27 | pic_param->fast_uvmc_flag << 26 | ref_field_pic_polarity << 25 | pic_param->reference_fields.bits.num_reference_pictures << 24 | pic_param->reference_fields.bits.reference_distance << 20 | pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */ pic_param->mv_fields.bits.extended_dmv_range << 10 | pic_param->mv_fields.bits.extended_mv_range << 8 | alt_pquant_edge_mask << 4 | alt_pquant_config << 2 | pic_param->pic_quantizer_fields.bits.half_qp << 1 | pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0); OUT_BCS_BATCH(batch, !!pic_param->bitplane_present.value << 31 | !pic_param->bitplane_present.flags.bp_forward_mb << 30 | !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 | !pic_param->bitplane_present.flags.bp_skip_mb << 28 | !pic_param->bitplane_present.flags.bp_direct_mb << 27 | !pic_param->bitplane_present.flags.bp_overflags << 26 | !pic_param->bitplane_present.flags.bp_ac_pred << 25 | !pic_param->bitplane_present.flags.bp_field_tx << 24 | pic_param->mv_fields.bits.mv_table << 20 | pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 | pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 | pic_param->transform_fields.bits.frame_level_transform_type << 12 | pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 | pic_param->mb_mode_table << 8 | trans_ac_y << 6 | pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 | pic_param->transform_fields.bits.intra_transform_dc_table << 3 | pic_param->cbp_table << 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_vc1_pred_pipe_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferVC1 *pic_param; int intensitycomp_single; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation); BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0 << 14 | /* FIXME: double ??? */ 0 << 12 | intensitycomp_single << 10 | intensitycomp_single << 8 | 0 << 4 | /* FIXME: interlace mode */ 0); OUT_BCS_BATCH(batch, pic_param->luma_shift << 16 | pic_param->luma_scale << 0); /* FIXME: Luma Scaling */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_vc1_directmode_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; struct object_surface *obj_surface; dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL; obj_surface = decode_state->render_object; if (obj_surface && obj_surface->private_data) { dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv; } obj_surface = decode_state->reference_objects[1]; if (obj_surface && obj_surface->private_data) { dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv; } BEGIN_BCS_BATCH(batch, 7); OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (7 - 2)); if (dmv_write_buffer) OUT_BCS_RELOC(batch, dmv_write_buffer, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); if (dmv_read_buffer) OUT_BCS_RELOC(batch, dmv_read_buffer, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static int gen8_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile) { int out_slice_data_bit_offset; int slice_header_size = in_slice_data_bit_offset / 8; int i, j; if (profile != 3) out_slice_data_bit_offset = in_slice_data_bit_offset; else { for (i = 0, j = 0; i < slice_header_size; i++, j++) { if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) { i++, j += 2; } } out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8; } return out_slice_data_bit_offset; } static void gen8_mfd_vc1_bsd_object(VADriverContextP ctx, VAPictureParameterBufferVC1 *pic_param, VASliceParameterBufferVC1 *slice_param, VASliceParameterBufferVC1 *next_slice_param, dri_bo *slice_data_bo, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int next_slice_start_vert_pos; int macroblock_offset; uint8_t *slice_data = NULL; dri_bo_map(slice_data_bo, 0); slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset); macroblock_offset = gen8_mfd_vc1_get_macroblock_bit_offset(slice_data, slice_param->macroblock_offset, pic_param->sequence_fields.bits.profile); dri_bo_unmap(slice_data_bo); if (next_slice_param) next_slice_start_vert_pos = next_slice_param->slice_vertical_position; else next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16; BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2)); OUT_BCS_BATCH(batch, slice_param->slice_data_size - (macroblock_offset >> 3)); OUT_BCS_BATCH(batch, slice_param->slice_data_offset + (macroblock_offset >> 3)); OUT_BCS_BATCH(batch, slice_param->slice_vertical_position << 16 | next_slice_start_vert_pos << 0); OUT_BCS_BATCH(batch, (macroblock_offset & 0x7)); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_vc1_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferVC1 *pic_param; VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; gen8_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen8_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context); gen8_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context); gen8_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context); gen8_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context); gen8_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context); gen8_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context); gen8_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen8_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen8_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static void gen8_mfd_jpeg_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct object_surface *obj_surface; VAPictureParameterBufferJPEGBaseline *pic_param; int subsampling = SUBSAMPLE_YUV420; int fourcc = VA_FOURCC('I', 'M', 'C', '3'); pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer; if (pic_param->num_components == 1) subsampling = SUBSAMPLE_YUV400; else if (pic_param->num_components == 3) { int h1 = pic_param->components[0].h_sampling_factor; int h2 = pic_param->components[1].h_sampling_factor; int h3 = pic_param->components[2].h_sampling_factor; int v1 = pic_param->components[0].v_sampling_factor; int v2 = pic_param->components[1].v_sampling_factor; int v3 = pic_param->components[2].v_sampling_factor; if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV420; fourcc = VA_FOURCC('I', 'M', 'C', '3'); } else if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV422H; fourcc = VA_FOURCC('4', '2', '2', 'H'); } else if (h1 == 1 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV444; fourcc = VA_FOURCC('4', '4', '4', 'P'); } else if (h1 == 4 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV411; fourcc = VA_FOURCC('4', '1', '1', 'P'); } else if (h1 == 1 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV422V; fourcc = VA_FOURCC('4', '2', '2', 'V'); } else if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 2 && v3 == 2) { subsampling = SUBSAMPLE_YUV422H; fourcc = VA_FOURCC('4', '2', '2', 'H'); } else if (h2 == 2 && h2 == 2 && h3 == 2 && v1 == 2 && v2 == 1 && v3 == 1) { subsampling = SUBSAMPLE_YUV422V; fourcc = VA_FOURCC('4', '2', '2', 'V'); } else assert(0); } else { assert(0); } /* Current decoded picture */ obj_surface = decode_state->render_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, fourcc, subsampling); dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = 1; gen7_mfd_context->post_deblocking_output.bo = NULL; gen7_mfd_context->post_deblocking_output.valid = 0; gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0; gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0; gen7_mfd_context->bitplane_read_buffer.bo = NULL; gen7_mfd_context->bitplane_read_buffer.valid = 0; } static const int va_to_gen7_jpeg_rotation[4] = { GEN7_JPEG_ROTATION_0, GEN7_JPEG_ROTATION_90, GEN7_JPEG_ROTATION_180, GEN7_JPEG_ROTATION_270 }; static void gen8_mfd_jpeg_pic_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferJPEGBaseline *pic_param; int chroma_type = GEN7_YUV420; int frame_width_in_blks; int frame_height_in_blks; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer; if (pic_param->num_components == 1) chroma_type = GEN7_YUV400; else if (pic_param->num_components == 3) { int h1 = pic_param->components[0].h_sampling_factor; int h2 = pic_param->components[1].h_sampling_factor; int h3 = pic_param->components[2].h_sampling_factor; int v1 = pic_param->components[0].v_sampling_factor; int v2 = pic_param->components[1].v_sampling_factor; int v3 = pic_param->components[2].v_sampling_factor; if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV420; else if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV422H_2Y; else if (h1 == 1 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV444; else if (h1 == 4 && h2 == 1 && h3 == 1 && v1 == 1 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV411; else if (h1 == 1 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV422V_2Y; else if (h1 == 2 && h2 == 1 && h3 == 1 && v1 == 2 && v2 == 2 && v3 == 2) chroma_type = GEN7_YUV422H_4Y; else if (h2 == 2 && h2 == 2 && h3 == 2 && v1 == 2 && v2 == 1 && v3 == 1) chroma_type = GEN7_YUV422V_4Y; else assert(0); } if (chroma_type == GEN7_YUV400 || chroma_type == GEN7_YUV444 || chroma_type == GEN7_YUV422V_2Y) { frame_width_in_blks = ((pic_param->picture_width + 7) / 8); frame_height_in_blks = ((pic_param->picture_height + 7) / 8); } else if (chroma_type == GEN7_YUV411) { frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4; frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4; } else { frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2; frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2; } BEGIN_BCS_BATCH(batch, 3); OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2)); OUT_BCS_BATCH(batch, (va_to_gen7_jpeg_rotation[0] << 4) | /* without rotation */ (chroma_type << 0)); OUT_BCS_BATCH(batch, ((frame_height_in_blks - 1) << 16) | /* FrameHeightInBlks */ ((frame_width_in_blks - 1) << 0)); /* FrameWidthInBlks */ ADVANCE_BCS_BATCH(batch); } static const int va_to_gen7_jpeg_hufftable[2] = { MFX_HUFFTABLE_ID_Y, MFX_HUFFTABLE_ID_UV }; static void gen8_mfd_jpeg_huff_table_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context, int num_tables) { VAHuffmanTableBufferJPEGBaseline *huffman_table; struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int index; if (!decode_state->huffman_table || !decode_state->huffman_table->buffer) return; huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer; for (index = 0; index < num_tables; index++) { int id = va_to_gen7_jpeg_hufftable[index]; if (!huffman_table->load_huffman_table[index]) continue; BEGIN_BCS_BATCH(batch, 53); OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2)); OUT_BCS_BATCH(batch, id); intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12); intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12); intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16); intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164); ADVANCE_BCS_BATCH(batch); } } static const int va_to_gen7_jpeg_qm[5] = { -1, MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX, MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX, MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX, MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX }; static void gen8_mfd_jpeg_qm_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { VAPictureParameterBufferJPEGBaseline *pic_param; VAIQMatrixBufferJPEGBaseline *iq_matrix; int index; if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer) return; iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer; pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer; assert(pic_param->num_components <= 3); for (index = 0; index < pic_param->num_components; index++) { int id = pic_param->components[index].component_id - pic_param->components[0].component_id + 1; int qm_type; unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector]; unsigned char raster_qm[64]; int j; if (id > 4 || id < 1) continue; if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector]) continue; qm_type = va_to_gen7_jpeg_qm[id]; for (j = 0; j < 64; j++) raster_qm[zigzag_direct[j]] = qm[j]; gen8_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context); } } static void gen8_mfd_jpeg_bsd_object(VADriverContextP ctx, VAPictureParameterBufferJPEGBaseline *pic_param, VASliceParameterBufferJPEGBaseline *slice_param, VASliceParameterBufferJPEGBaseline *next_slice_param, dri_bo *slice_data_bo, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int scan_component_mask = 0; int i; assert(slice_param->num_components > 0); assert(slice_param->num_components < 4); assert(slice_param->num_components <= pic_param->num_components); for (i = 0; i < slice_param->num_components; i++) { switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) { case 1: scan_component_mask |= (1 << 0); break; case 2: scan_component_mask |= (1 << 1); break; case 3: scan_component_mask |= (1 << 2); break; default: assert(0); break; } } BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2)); OUT_BCS_BATCH(batch, slice_param->slice_data_size); OUT_BCS_BATCH(batch, slice_param->slice_data_offset); OUT_BCS_BATCH(batch, slice_param->slice_horizontal_position << 16 | slice_param->slice_vertical_position << 0); OUT_BCS_BATCH(batch, ((slice_param->num_components != 1) << 30) | /* interleaved */ (scan_component_mask << 27) | /* scan components */ (0 << 26) | /* disable interrupt allowed */ (slice_param->num_mcus << 0)); /* MCU count */ OUT_BCS_BATCH(batch, (slice_param->restart_interval << 0)); /* RestartInterval */ ADVANCE_BCS_BATCH(batch); } /* Workaround for JPEG decoding on Ivybridge */ #ifdef JPEG_WA VAStatus i965_DestroySurfaces(VADriverContextP ctx, VASurfaceID *surface_list, int num_surfaces); VAStatus i965_CreateSurfaces(VADriverContextP ctx, int width, int height, int format, int num_surfaces, VASurfaceID *surfaces); static struct { int width; int height; unsigned char data[32]; int data_size; int data_bit_offset; int qp; } gen7_jpeg_wa_clip = { 16, 16, { 0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c, 0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00 }, 14, 40, 28, }; static void gen8_jpeg_wa_init(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAStatus status; struct object_surface *obj_surface; if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE) i965_DestroySurfaces(ctx, &gen7_mfd_context->jpeg_wa_surface_id, 1); status = i965_CreateSurfaces(ctx, gen7_jpeg_wa_clip.width, gen7_jpeg_wa_clip.height, VA_RT_FORMAT_YUV420, 1, &gen7_mfd_context->jpeg_wa_surface_id); assert(status == VA_STATUS_SUCCESS); obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id); assert(obj_surface); i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420); gen7_mfd_context->jpeg_wa_surface_object = obj_surface; if (!gen7_mfd_context->jpeg_wa_slice_data_bo) { gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr, "JPEG WA data", 0x1000, 0x1000); dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo, 0, gen7_jpeg_wa_clip.data_size, gen7_jpeg_wa_clip.data); } } static void gen8_jpeg_wa_pipe_mode_select(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 5); OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2)); OUT_BCS_BATCH(batch, (MFX_LONG_MODE << 17) | /* Currently only support long format */ (MFD_MODE_VLD << 15) | /* VLD mode */ (0 << 10) | /* disable Stream-Out */ (0 << 9) | /* Post Deblocking Output */ (1 << 8) | /* Pre Deblocking Output */ (0 << 5) | /* not in stitch mode */ (MFX_CODEC_DECODE << 4) | /* decoding mode */ (MFX_FORMAT_AVC << 0)); OUT_BCS_BATCH(batch, (0 << 4) | /* terminate if AVC motion and POC table error occurs */ (0 << 3) | /* terminate if AVC mbdata error occurs */ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */ (0 << 1) | (0 << 0)); OUT_BCS_BATCH(batch, 0); /* pic status/error report id */ OUT_BCS_BATCH(batch, 0); /* reserved */ ADVANCE_BCS_BATCH(batch); } static void gen8_jpeg_wa_surface_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object; struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, ((obj_surface->orig_width - 1) << 18) | ((obj_surface->orig_height - 1) << 4)); OUT_BCS_BATCH(batch, (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */ (1 << 27) | /* interleave chroma, set to 0 for JPEG */ (0 << 22) | /* surface object control state, ignored */ ((obj_surface->width - 1) << 3) | /* pitch */ (0 << 2) | /* must be 0 */ (1 << 1) | /* must be tiled */ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */ OUT_BCS_BATCH(batch, (0 << 16) | /* X offset for U(Cb), must be 0 */ (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */ OUT_BCS_BATCH(batch, (0 << 16) | /* X offset for V(Cr), must be 0 */ (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */ ADVANCE_BCS_BATCH(batch); } static void gen8_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object; struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; dri_bo *intra_bo; int i; intra_bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", 128 * 64, 0x1000); BEGIN_BCS_BATCH(batch, 61); OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2)); OUT_BCS_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* post deblocking */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* uncompressed-video & stream out 7-12 */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW 13-15 is for intra row store scratch */ OUT_BCS_RELOC(batch, intra_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW 16-18 is for deblocking filter */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* DW 19..50 */ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); /* the DW52-54 is for mb status address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* the DW56-60 is for ILDB & second ILDB address */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); dri_bo_unreference(intra_bo); } static void gen8_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; dri_bo *bsd_mpc_bo, *mpr_bo; bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", 11520, /* 1.5 * 120 * 64 */ 0x1000); mpr_bo = dri_bo_alloc(i965->intel.bufmgr, "mpr row store", 7680, /* 1. 0 * 120 * 64 */ 0x1000); BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2)); OUT_BCS_RELOC(batch, bsd_mpc_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_RELOC(batch, mpr_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); dri_bo_unreference(bsd_mpc_bo); dri_bo_unreference(mpr_bo); } static void gen8_jpeg_wa_avc_qm_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { } static void gen8_jpeg_wa_avc_img_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int img_struct = 0; int mbaff_frame_flag = 0; unsigned int width_in_mbs = 1, height_in_mbs = 1; BEGIN_BCS_BATCH(batch, 16); OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2)); OUT_BCS_BATCH(batch, width_in_mbs * height_in_mbs); OUT_BCS_BATCH(batch, ((height_in_mbs - 1) << 16) | ((width_in_mbs - 1) << 0)); OUT_BCS_BATCH(batch, (0 << 24) | (0 << 16) | (0 << 14) | (0 << 13) | (0 << 12) | /* differ from GEN6 */ (0 << 10) | (img_struct << 8)); OUT_BCS_BATCH(batch, (1 << 10) | /* 4:2:0 */ (1 << 7) | /* CABAC */ (0 << 6) | (0 << 5) | (0 << 4) | (0 << 3) | (1 << 2) | (mbaff_frame_flag << 1) | (0 << 0)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_jpeg_wa_avc_directmode_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int i; BEGIN_BCS_BATCH(batch, 71); OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2)); /* reference surfaces 0..15 */ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { OUT_BCS_BATCH(batch, 0); /* top */ OUT_BCS_BATCH(batch, 0); /* bottom */ } OUT_BCS_BATCH(batch, 0); /* the current decoding frame/field */ OUT_BCS_BATCH(batch, 0); /* top */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* POC List */ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2)); OUT_BCS_RELOC(batch, gen7_mfd_context->jpeg_wa_slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_jpeg_wa_avc_bsd_object(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; /* the input bitsteam format on GEN7 differs from GEN6 */ BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2)); OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, (0 << 31) | (0 << 14) | (0 << 12) | (0 << 10) | (0 << 8)); OUT_BCS_BATCH(batch, ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) | (0 << 5) | (0 << 4) | (1 << 3) | /* LastSlice Flag */ (gen7_jpeg_wa_clip.data_bit_offset & 0x7)); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_jpeg_wa_avc_slice_state(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1; int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0; int first_mb_in_slice = 0; int slice_type = SLICE_TYPE_I; BEGIN_BCS_BATCH(batch, 11); OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2)); OUT_BCS_BATCH(batch, slice_type); OUT_BCS_BATCH(batch, (num_ref_idx_l1 << 24) | (num_ref_idx_l0 << 16) | (0 << 8) | (0 << 0)); OUT_BCS_BATCH(batch, (0 << 29) | (1 << 27) | /* disable Deblocking */ (0 << 24) | (gen7_jpeg_wa_clip.qp << 16) | (0 << 8) | (0 << 0)); OUT_BCS_BATCH(batch, (slice_ver_pos << 24) | (slice_hor_pos << 16) | (first_mb_in_slice << 0)); OUT_BCS_BATCH(batch, (next_slice_ver_pos << 16) | (next_slice_hor_pos << 0)); OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_jpeg_wa(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; gen8_jpeg_wa_init(ctx, gen7_mfd_context); intel_batchbuffer_emit_mi_flush(batch); gen8_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context); gen8_jpeg_wa_surface_state(ctx, gen7_mfd_context); gen8_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context); gen8_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context); gen8_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context); gen8_jpeg_wa_avc_img_state(ctx, gen7_mfd_context); gen8_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context); gen8_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context); gen8_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context); gen8_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context); } #endif void gen8_mfd_jpeg_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferJPEGBaseline *pic_param; VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param; dri_bo *slice_data_bo; int i, j, max_selector = 0; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer; /* Currently only support Baseline DCT */ gen8_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); #ifdef JPEG_WA gen8_mfd_jpeg_wa(ctx, gen7_mfd_context); #endif intel_batchbuffer_emit_mi_flush(batch); gen8_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context); gen8_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context); gen8_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context); gen8_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context); gen8_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen8_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { int component; assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; for (component = 0; component < slice_param->num_components; component++) { if (max_selector < slice_param->components[component].dc_table_selector) max_selector = slice_param->components[component].dc_table_selector; if (max_selector < slice_param->components[component].ac_table_selector) max_selector = slice_param->components[component].ac_table_selector; } slice_param++; } } assert(max_selector < 2); gen8_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer; slice_data_bo = decode_state->slice_datas[j]->bo; gen8_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context); if (j == decode_state->num_slice_params - 1) next_slice_group_param = NULL; else next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); if (i < decode_state->slice_params[j]->num_elements - 1) next_slice_param = slice_param + 1; else next_slice_param = next_slice_group_param; gen8_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context); slice_param++; } } intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static const int vp8_dc_qlookup[128] = { 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 21, 22, 22, 23, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 91, 93, 95, 96, 98, 100, 101, 102, 104, 106, 108, 110, 112, 114, 116, 118, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 143, 145, 148, 151, 154, 157, }; static const int vp8_ac_qlookup[128] = { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116, 119, 122, 125, 128, 131, 134, 137, 140, 143, 146, 149, 152, 155, 158, 161, 164, 167, 170, 173, 177, 181, 185, 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 234, 239, 245, 249, 254, 259, 264, 269, 274, 279, 284, }; static inline unsigned int vp8_clip_quantization_index(int index) { if(index > 127) return 127; else if(index <0) return 0; return index; } static void gen8_mfd_vp8_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct object_surface *obj_surface; struct i965_driver_data *i965 = i965_driver_data(ctx); dri_bo *bo; VAPictureParameterBufferVP8 *pic_param = (VAPictureParameterBufferVP8 *)decode_state->pic_param->buffer; int width_in_mbs = (pic_param->frame_width + 15) / 16; int height_in_mbs = (pic_param->frame_height + 15) / 16; assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */ assert(height_in_mbs > 0 && height_in_mbs <= 256); intel_update_vp8_frame_store_index(ctx, decode_state, pic_param, gen7_mfd_context->reference_surface); /* Current decoded picture */ obj_surface = decode_state->render_object; i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.valid = !pic_param->pic_fields.bits.loop_filter_disable; dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo; dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.valid = pic_param->pic_fields.bits.loop_filter_disable; /* The same as AVC */ dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "intra row store", width_in_mbs * 64, 0x1000); assert(bo); gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo; gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "deblocking filter row store", width_in_mbs * 64 * 4, 0x1000); assert(bo); gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo; gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd mpc row store", width_in_mbs * 64 * 2, 0x1000); assert(bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo; gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1; dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "mpr row store", width_in_mbs * 64 * 2, 0x1000); assert(bo); gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo; gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1; gen7_mfd_context->bitplane_read_buffer.valid = 0; } static void gen8_mfd_vp8_pic_state(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferVP8 *pic_param = (VAPictureParameterBufferVP8 *)decode_state->pic_param->buffer; VAIQMatrixBufferVP8 *iq_matrix = (VAIQMatrixBufferVP8 *)decode_state->iq_matrix->buffer; VASliceParameterBufferVP8 *slice_param = (VASliceParameterBufferVP8 *)decode_state->slice_params[0]->buffer; /* one slice per frame */ dri_bo *probs_bo = decode_state->probability_data->bo; int i, j,log2num; unsigned int quantization_value[4][6]; log2num = (int)log2(slice_param->num_of_partitions - 1); BEGIN_BCS_BATCH(batch, 38); OUT_BCS_BATCH(batch, MFX_VP8_PIC_STATE | (38 - 2)); OUT_BCS_BATCH(batch, (ALIGN(pic_param->frame_height, 16) / 16 - 1) << 16 | (ALIGN(pic_param->frame_width, 16) / 16 - 1) << 0); OUT_BCS_BATCH(batch, log2num << 24 | pic_param->pic_fields.bits.sharpness_level << 16 | pic_param->pic_fields.bits.sign_bias_alternate << 13 | pic_param->pic_fields.bits.sign_bias_golden << 12 | pic_param->pic_fields.bits.loop_filter_adj_enable << 11 | pic_param->pic_fields.bits.mb_no_coeff_skip << 10 | pic_param->pic_fields.bits.update_mb_segmentation_map << 9 | pic_param->pic_fields.bits.segmentation_enabled << 8 | 0 << 7 | /* segmentation id streamin disabled */ 0 << 6 | /* segmentation id streamout disabled */ (pic_param->pic_fields.bits.key_frame == 0 ? 1 : 0) << 5 | /* 0 indicate an intra frame in VP8 stream/spec($9.1)*/ pic_param->pic_fields.bits.filter_type << 4 | (pic_param->pic_fields.bits.version == 3) << 1 | /* full pixel mode for version 3 */ !!pic_param->pic_fields.bits.version << 0); /* version 0: 6 tap */ OUT_BCS_BATCH(batch, pic_param->loop_filter_level[3] << 24 | pic_param->loop_filter_level[2] << 16 | pic_param->loop_filter_level[1] << 8 | pic_param->loop_filter_level[0] << 0); /* Quantizer Value for 4 segmetns, DW4-DW15 */ for (i = 0; i < 4; i++) { quantization_value[i][0] = vp8_ac_qlookup[vp8_clip_quantization_index(iq_matrix->quantization_index[i][0])];/*yac*/ quantization_value[i][1] = vp8_dc_qlookup[vp8_clip_quantization_index(iq_matrix->quantization_index[i][1])];/*ydc*/ quantization_value[i][2] = 2*vp8_dc_qlookup[vp8_clip_quantization_index(iq_matrix->quantization_index[i][2])];/*y2dc*/ /* 101581>>16 is equivalent to 155/100 */ quantization_value[i][3] = (101581*vp8_ac_qlookup[vp8_clip_quantization_index(iq_matrix->quantization_index[i][3])]) >> 16;/*y2ac*/ quantization_value[i][4] = vp8_dc_qlookup[vp8_clip_quantization_index(iq_matrix->quantization_index[i][4])];/*uvdc*/ quantization_value[i][5] = vp8_ac_qlookup[vp8_clip_quantization_index(iq_matrix->quantization_index[i][5])];/*uvac*/ quantization_value[i][3] = (quantization_value[i][3] > 8 ? quantization_value[i][3] : 8); quantization_value[i][4] = (quantization_value[i][4] < 132 ? quantization_value[i][4] : 132); OUT_BCS_BATCH(batch, quantization_value[i][0] << 16 | /* Y1AC */ quantization_value[i][1] << 0); /* Y1DC */ OUT_BCS_BATCH(batch, quantization_value[i][5] << 16 | /* UVAC */ quantization_value[i][4] << 0); /* UVDC */ OUT_BCS_BATCH(batch, quantization_value[i][3] << 16 | /* Y2AC */ quantization_value[i][2] << 0); /* Y2DC */ } /* CoeffProbability table for non-key frame, DW16-DW18 */ if (probs_bo) { OUT_BCS_RELOC(batch, probs_bo, 0, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } OUT_BCS_BATCH(batch, pic_param->mb_segment_tree_probs[2] << 16 | pic_param->mb_segment_tree_probs[1] << 8 | pic_param->mb_segment_tree_probs[0] << 0); OUT_BCS_BATCH(batch, pic_param->prob_skip_false << 24 | pic_param->prob_intra << 16 | pic_param->prob_last << 8 | pic_param->prob_gf << 0); OUT_BCS_BATCH(batch, pic_param->y_mode_probs[3] << 24 | pic_param->y_mode_probs[2] << 16 | pic_param->y_mode_probs[1] << 8 | pic_param->y_mode_probs[0] << 0); OUT_BCS_BATCH(batch, pic_param->uv_mode_probs[2] << 16 | pic_param->uv_mode_probs[1] << 8 | pic_param->uv_mode_probs[0] << 0); /* MV update value, DW23-DW32 */ for (i = 0; i < 2; i++) { for (j = 0; j < 20; j += 4) { OUT_BCS_BATCH(batch, (j + 3 == 19 ? 0 : pic_param->mv_probs[i][j + 3]) << 24 | pic_param->mv_probs[i][j + 2] << 16 | pic_param->mv_probs[i][j + 1] << 8 | pic_param->mv_probs[i][j + 0] << 0); } } OUT_BCS_BATCH(batch, pic_param->loop_filter_deltas_ref_frame[3] << 24 | pic_param->loop_filter_deltas_ref_frame[2] << 16 | pic_param->loop_filter_deltas_ref_frame[1] << 8 | pic_param->loop_filter_deltas_ref_frame[0] << 0); OUT_BCS_BATCH(batch, pic_param->loop_filter_deltas_mode[3] << 24 | pic_param->loop_filter_deltas_mode[2] << 16 | pic_param->loop_filter_deltas_mode[1] << 8 | pic_param->loop_filter_deltas_mode[0] << 0); /* segmentation id stream base address, DW35-DW37 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void gen8_mfd_vp8_bsd_object(VADriverContextP ctx, VAPictureParameterBufferVP8 *pic_param, VASliceParameterBufferVP8 *slice_param, dri_bo *slice_data_bo, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; int i, log2num; unsigned int offset = slice_param->slice_data_offset + ((slice_param->macroblock_offset + 7 ) >> 3); unsigned int used_bits = 8-pic_param->bool_coder_ctx.count; unsigned int partition_size_0 = slice_param->partition_size[0]; assert(pic_param->bool_coder_ctx.count >= 0 && pic_param->bool_coder_ctx.count <= 7); if (used_bits == 8) { used_bits = 0; offset += 1; partition_size_0 -= 1; } assert(slice_param->num_of_partitions >= 2); assert(slice_param->num_of_partitions <= 9); log2num = (int)log2(slice_param->num_of_partitions - 1); BEGIN_BCS_BATCH(batch, 22); OUT_BCS_BATCH(batch, MFD_VP8_BSD_OBJECT | (22 - 2)); OUT_BCS_BATCH(batch, used_bits << 16 | /* Partition 0 CPBAC Entropy Count */ pic_param->bool_coder_ctx.range << 8 | /* Partition 0 Count Entropy Range */ log2num << 4 | (slice_param->macroblock_offset & 0x7)); OUT_BCS_BATCH(batch, pic_param->bool_coder_ctx.value << 24 | /* Partition 0 Count Entropy Value */ 0); OUT_BCS_BATCH(batch, partition_size_0); OUT_BCS_BATCH(batch, offset); //partion sizes in bytes are present after the above first partition when there are more than one token partition offset += (partition_size_0 + 3 * (slice_param->num_of_partitions - 2)); for (i = 1; i < 9; i++) { if (i < slice_param->num_of_partitions) { OUT_BCS_BATCH(batch, slice_param->partition_size[i]); OUT_BCS_BATCH(batch, offset); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } offset += slice_param->partition_size[i]; } OUT_BCS_BATCH(batch, 1 << 31 | /* concealment method */ 0); ADVANCE_BCS_BATCH(batch); } void gen8_mfd_vp8_decode_picture(VADriverContextP ctx, struct decode_state *decode_state, struct gen7_mfd_context *gen7_mfd_context) { struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; VAPictureParameterBufferVP8 *pic_param; VASliceParameterBufferVP8 *slice_param; dri_bo *slice_data_bo; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferVP8 *)decode_state->pic_param->buffer; /* one slice per frame */ if (decode_state->num_slice_params != 1 || (!decode_state->slice_params || !decode_state->slice_params[0] || (decode_state->slice_params[0]->num_elements != 1 || decode_state->slice_params[0]->buffer == NULL)) || (!decode_state->slice_datas || !decode_state->slice_datas[0] || !decode_state->slice_datas[0]->bo) || !decode_state->probability_data) { WARN_ONCE("Wrong parameters for VP8 decoding\n"); return; } slice_param = (VASliceParameterBufferVP8 *)decode_state->slice_params[0]->buffer; slice_data_bo = decode_state->slice_datas[0]->bo; gen8_mfd_vp8_decode_init(ctx, decode_state, gen7_mfd_context); intel_batchbuffer_start_atomic_bcs(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen8_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VP8, gen7_mfd_context); gen8_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VP8, gen7_mfd_context); gen8_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VP8, gen7_mfd_context); gen8_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VP8, gen7_mfd_context); gen8_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VP8, gen7_mfd_context); gen8_mfd_vp8_pic_state(ctx, decode_state, gen7_mfd_context); gen8_mfd_vp8_bsd_object(ctx, pic_param, slice_param, slice_data_bo, gen7_mfd_context); intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } static VAStatus gen8_mfd_decode_picture(VADriverContextP ctx, VAProfile profile, union codec_state *codec_state, struct hw_context *hw_context) { struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context; struct decode_state *decode_state = &codec_state->decode; VAStatus vaStatus; assert(gen7_mfd_context); vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state); if (vaStatus != VA_STATUS_SUCCESS) goto out; gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1; switch (profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: gen8_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context); break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: gen8_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context); break; case VAProfileVC1Simple: case VAProfileVC1Main: case VAProfileVC1Advanced: gen8_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context); break; case VAProfileJPEGBaseline: gen8_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context); break; case VAProfileVP8Version0_3: gen8_mfd_vp8_decode_picture(ctx, decode_state, gen7_mfd_context); break; default: assert(0); break; } vaStatus = VA_STATUS_SUCCESS; out: return vaStatus; } static void gen8_mfd_context_destroy(void *hw_context) { struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context; dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo); gen7_mfd_context->post_deblocking_output.bo = NULL; dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo); gen7_mfd_context->pre_deblocking_output.bo = NULL; dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo); gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo); gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo); gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo); gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo); gen7_mfd_context->bitplane_read_buffer.bo = NULL; dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo); intel_batchbuffer_free(gen7_mfd_context->base.batch); free(gen7_mfd_context); } static void gen8_mfd_mpeg2_context_init(VADriverContextP ctx, struct gen7_mfd_context *gen7_mfd_context) { gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1; gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1; gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1; gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1; } struct hw_context * gen8_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config) { struct intel_driver_data *intel = intel_driver_data(ctx); struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context)); int i; gen7_mfd_context->base.destroy = gen8_mfd_context_destroy; gen7_mfd_context->base.run = gen8_mfd_decode_picture; gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0); for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) { gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID; gen7_mfd_context->reference_surface[i].frame_store_id = -1; } gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE; switch (obj_config->profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: gen8_mfd_mpeg2_context_init(ctx, gen7_mfd_context); break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: gen8_mfd_avc_context_init(ctx, gen7_mfd_context); break; default: break; } return (struct hw_context *)gen7_mfd_context; } intel-driver-1.3.0/src/gen8_vme.c000066400000000000000000001305231231401140700165570ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Zhao Yakui * Xiang Haihao */ #include #include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_encoder.h" #include "gen6_vme.h" #include "gen6_mfc.h" #ifdef SURFACE_STATE_PADDED_SIZE #undef SURFACE_STATE_PADDED_SIZE #endif #define SURFACE_STATE_PADDED_SIZE SURFACE_STATE_PADDED_SIZE_GEN8 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index) #define VME_INTRA_SHADER 0 #define VME_INTER_SHADER 1 #define VME_BINTER_SHADER 2 #define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */ #define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */ #define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */ #define VME_MSG_LENGTH 32 static const uint32_t gen8_vme_intra_frame[][4] = { #include "shaders/vme/intra_frame_gen8.g8b" }; static const uint32_t gen8_vme_inter_frame[][4] = { #include "shaders/vme/inter_frame_gen8.g8b" }; static const uint32_t gen8_vme_inter_bframe[][4] = { #include "shaders/vme/inter_bframe_gen8.g8b" }; static struct i965_kernel gen8_vme_kernels[] = { { "VME Intra Frame", VME_INTRA_SHADER, /*index*/ gen8_vme_intra_frame, sizeof(gen8_vme_intra_frame), NULL }, { "VME inter Frame", VME_INTER_SHADER, gen8_vme_inter_frame, sizeof(gen8_vme_inter_frame), NULL }, { "VME inter BFrame", VME_BINTER_SHADER, gen8_vme_inter_bframe, sizeof(gen8_vme_inter_bframe), NULL } }; static const uint32_t gen8_vme_mpeg2_intra_frame[][4] = { #include "shaders/vme/intra_frame_gen8.g8b" }; static const uint32_t gen8_vme_mpeg2_inter_frame[][4] = { #include "shaders/vme/mpeg2_inter_gen8.g8b" }; static struct i965_kernel gen8_vme_mpeg2_kernels[] = { { "VME Intra Frame", VME_INTRA_SHADER, /*index*/ gen8_vme_mpeg2_intra_frame, sizeof(gen8_vme_mpeg2_intra_frame), NULL }, { "VME inter Frame", VME_INTER_SHADER, gen8_vme_mpeg2_inter_frame, sizeof(gen8_vme_mpeg2_inter_frame), NULL }, }; /* only used for VME source surface state */ static void gen8_vme_source_surface_state(VADriverContextP ctx, int index, struct object_surface *obj_surface, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; vme_context->vme_surface2_setup(ctx, &vme_context->gpe_context, obj_surface, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen8_vme_media_source_surface_state(VADriverContextP ctx, int index, struct object_surface *obj_surface, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; vme_context->vme_media_rw_surface_setup(ctx, &vme_context->gpe_context, obj_surface, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen8_vme_media_chroma_source_surface_state(VADriverContextP ctx, int index, struct object_surface *obj_surface, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; vme_context->vme_media_chroma_surface_setup(ctx, &vme_context->gpe_context, obj_surface, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen8_vme_output_buffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs; vme_context->vme_output.pitch = 16; /* in bytes, always 16 */ if (is_intra) vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2; else vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24; /* * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref * + 16 FBR Info + 128 FBR MV + 32 FBR Ref. * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24. */ vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr, "VME output buffer", vme_context->vme_output.num_blocks * vme_context->vme_output.size_block, 0x1000); assert(vme_context->vme_output.bo); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_output, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen8_vme_output_vme_batchbuffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1; vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */ vme_context->vme_batchbuffer.pitch = 16; vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr, "VME batchbuffer", vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block, 0x1000); /* vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_batchbuffer, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); */ } static VAStatus gen8_vme_surface_setup(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct object_surface *obj_surface; /*Setup surfaces state*/ /* current picture for encoding */ obj_surface = encode_state->input_yuv_object; gen8_vme_source_surface_state(ctx, 0, obj_surface, encoder_context); gen8_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context); gen8_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context); if (!is_intra) { VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int slice_type; slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI); intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 0, 1, gen8_vme_source_surface_state); if (slice_type == SLICE_TYPE_B) intel_avc_vme_reference_state(ctx, encode_state, encoder_context, 1, 2, gen8_vme_source_surface_state); } /* VME output */ gen8_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context); gen8_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context); return VA_STATUS_SUCCESS; } static VAStatus gen8_vme_interface_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct gen8_interface_descriptor_data *desc; int i; dri_bo *bo; unsigned char *desc_ptr; bo = vme_context->gpe_context.dynamic_state.bo; dri_bo_map(bo, 1); assert(bo->virtual); desc_ptr = (unsigned char *)bo->virtual + vme_context->gpe_context.idrt_offset; desc = (struct gen8_interface_descriptor_data *)desc_ptr; for (i = 0; i < vme_context->vme_kernel_sum; i++) { struct i965_kernel *kernel; kernel = &vme_context->gpe_context.kernels[i]; assert(sizeof(*desc) == 32); /*Setup the descritor table*/ memset(desc, 0, sizeof(*desc)); desc->desc0.kernel_start_pointer = kernel->kernel_offset >> 6; desc->desc3.sampler_count = 0; /* FIXME: */ desc->desc3.sampler_state_pointer = 0; desc->desc4.binding_table_entry_count = 1; /* FIXME: */ desc->desc4.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5); desc->desc5.constant_urb_entry_read_offset = 0; desc->desc5.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH; desc++; } dri_bo_unmap(bo); return VA_STATUS_SUCCESS; } static VAStatus gen8_vme_constant_setup(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; unsigned char *constant_buffer; unsigned int *vme_state_message; int mv_num = 32; vme_state_message = (unsigned int *)vme_context->vme_state_message; if (encoder_context->codec == CODEC_H264) { if (vme_context->h264_level >= 30) { mv_num = 16; if (vme_context->h264_level >= 31) mv_num = 8; } } else if (encoder_context->codec == CODEC_MPEG2) { mv_num = 2; } vme_state_message[31] = mv_num; dri_bo_map(vme_context->gpe_context.dynamic_state.bo, 1); assert(vme_context->gpe_context.dynamic_state.bo->virtual); constant_buffer = (unsigned char *)vme_context->gpe_context.dynamic_state.bo->virtual + vme_context->gpe_context.curbe_offset; /* VME MV/Mb cost table is passed by using const buffer */ /* Now it uses the fixed search path. So it is constructed directly * in the GPU shader. */ memcpy(constant_buffer, (char *)vme_context->vme_state_message, 128); dri_bo_unmap(vme_context->gpe_context.dynamic_state.bo); return VA_STATUS_SUCCESS; } #define MB_SCOREBOARD_A (1 << 0) #define MB_SCOREBOARD_B (1 << 1) #define MB_SCOREBOARD_C (1 << 2) /* check whether the mb of (x_index, y_index) is out of bound */ static inline int loop_in_bounds(int x_index, int y_index, int first_mb, int num_mb, int mb_width, int mb_height) { int mb_index; if (x_index < 0 || x_index >= mb_width) return -1; if (y_index < 0 || y_index >= mb_height) return -1; mb_index = y_index * mb_width + x_index; if (mb_index < first_mb || mb_index > (first_mb + num_mb)) return -1; return 0; } static void gen8wa_vme_walker_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, int transform_8x8_mode_flag, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int mb_row; int s; unsigned int *command_ptr; #define USE_SCOREBOARD (1 << 21) dri_bo_map(vme_context->vme_batchbuffer.bo, 1); command_ptr = vme_context->vme_batchbuffer.bo->virtual; for (s = 0; s < encode_state->num_slice_params_ext; s++) { VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer; int first_mb = pSliceParameter->macroblock_address; int num_mb = pSliceParameter->num_macroblocks; unsigned int mb_intra_ub, score_dep; int x_outer, y_outer, x_inner, y_inner; int xtemp_outer = 0; x_outer = first_mb % mb_width; y_outer = first_mb / mb_width; mb_row = y_outer; for (; x_outer < (mb_width -2 ) && !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) { x_inner = x_outer; y_inner = y_outer; for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) { mb_intra_ub = 0; score_dep = 0; if (x_inner != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; score_dep |= MB_SCOREBOARD_A; } if (y_inner != mb_row) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; score_dep |= MB_SCOREBOARD_B; if (x_inner != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (x_inner != (mb_width -1)) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; score_dep |= MB_SCOREBOARD_C; } } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = USE_SCOREBOARD; /* Indirect data */ *command_ptr++ = 0; /* the (X, Y) term of scoreboard */ *command_ptr++ = ((y_inner << 16) | x_inner); *command_ptr++ = score_dep; /*inline data */ *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner); *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8)); *command_ptr++ = CMD_MEDIA_STATE_FLUSH; *command_ptr++ = 0; x_inner -= 2; y_inner += 1; } x_outer += 1; } xtemp_outer = mb_width - 2; if (xtemp_outer < 0) xtemp_outer = 0; x_outer = xtemp_outer; y_outer = first_mb / mb_width; for (;!loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) { y_inner = y_outer; x_inner = x_outer; for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) { mb_intra_ub = 0; score_dep = 0; if (x_inner != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; score_dep |= MB_SCOREBOARD_A; } if (y_inner != mb_row) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; score_dep |= MB_SCOREBOARD_B; if (x_inner != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (x_inner != (mb_width -1)) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; score_dep |= MB_SCOREBOARD_C; } } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = USE_SCOREBOARD; /* Indirect data */ *command_ptr++ = 0; /* the (X, Y) term of scoreboard */ *command_ptr++ = ((y_inner << 16) | x_inner); *command_ptr++ = score_dep; /*inline data */ *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner); *command_ptr++ = ((1 << 18) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8)); *command_ptr++ = CMD_MEDIA_STATE_FLUSH; *command_ptr++ = 0; x_inner -= 2; y_inner += 1; } x_outer++; if (x_outer >= mb_width) { y_outer += 1; x_outer = xtemp_outer; } } } *command_ptr++ = MI_BATCH_BUFFER_END; *command_ptr++ = 0; dri_bo_unmap(vme_context->vme_batchbuffer.bo); } static void gen8_vme_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, int transform_8x8_mode_flag, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int mb_x = 0, mb_y = 0; int i, s; unsigned int *command_ptr; dri_bo_map(vme_context->vme_batchbuffer.bo, 1); command_ptr = vme_context->vme_batchbuffer.bo->virtual; for (s = 0; s < encode_state->num_slice_params_ext; s++) { VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer; int slice_mb_begin = pSliceParameter->macroblock_address; int slice_mb_number = pSliceParameter->num_macroblocks; unsigned int mb_intra_ub; int slice_mb_x = pSliceParameter->macroblock_address % mb_width; for (i = 0; i < slice_mb_number; ) { int mb_count = i + slice_mb_begin; mb_x = mb_count % mb_width; mb_y = mb_count / mb_width; mb_intra_ub = 0; if (mb_x != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; } if (mb_y != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; if (mb_x != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (mb_x != (mb_width -1)) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; } if (i < mb_width) { if (i == 0) mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE); mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK); if ((i == (mb_width - 1)) && slice_mb_x) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; } } if ((i == mb_width) && slice_mb_x) { mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D); } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; /*inline data */ *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x); *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8)); *command_ptr++ = CMD_MEDIA_STATE_FLUSH; *command_ptr++ = 0; i += 1; } } *command_ptr++ = MI_BATCH_BUFFER_END; *command_ptr++ = 0; dri_bo_unmap(vme_context->vme_batchbuffer.bo); } static void gen8_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; gen8_gpe_context_init(ctx, &vme_context->gpe_context); /* VME output buffer */ dri_bo_unreference(vme_context->vme_output.bo); vme_context->vme_output.bo = NULL; dri_bo_unreference(vme_context->vme_batchbuffer.bo); vme_context->vme_batchbuffer.bo = NULL; /* VME state */ dri_bo_unreference(vme_context->vme_state.bo); vme_context->vme_state.bo = NULL; } static void gen8_vme_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct intel_batchbuffer *batch = encoder_context->base.batch; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int width_in_mbs = pSequenceParameter->picture_width_in_mbs; int height_in_mbs = pSequenceParameter->picture_height_in_mbs; int kernel_shader; bool allow_hwscore = true; int s; for (s = 0; s < encode_state->num_slice_params_ext; s++) { pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer; if ((pSliceParameter->macroblock_address % width_in_mbs)) { allow_hwscore = false; break; } } if ((pSliceParameter->slice_type == SLICE_TYPE_I) || (pSliceParameter->slice_type == SLICE_TYPE_I)) { kernel_shader = VME_INTRA_SHADER; } else if ((pSliceParameter->slice_type == SLICE_TYPE_P) || (pSliceParameter->slice_type == SLICE_TYPE_SP)) { kernel_shader = VME_INTER_SHADER; } else { kernel_shader = VME_BINTER_SHADER; if (!allow_hwscore) kernel_shader = VME_INTER_SHADER; } if (allow_hwscore) gen8wa_vme_walker_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, kernel_shader, pPicParameter->pic_fields.bits.transform_8x8_mode_flag, encoder_context); else gen8_vme_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, kernel_shader, pPicParameter->pic_fields.bits.transform_8x8_mode_flag, encoder_context); intel_batchbuffer_start_atomic(batch, 0x1000); gen8_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch); BEGIN_BATCH(batch, 3); OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0)); OUT_RELOC(batch, vme_context->vme_batchbuffer.bo, I915_GEM_DOMAIN_COMMAND, 0, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); intel_batchbuffer_end_atomic(batch); } static VAStatus gen8_vme_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { VAStatus vaStatus = VA_STATUS_SUCCESS; VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; struct gen6_vme_context *vme_context = encoder_context->vme_context; if (!vme_context->h264_level || (vme_context->h264_level != pSequenceParameter->level_idc)) { vme_context->h264_level = pSequenceParameter->level_idc; } intel_vme_update_mbmv_cost(ctx, encode_state, encoder_context); /*Setup all the memory object*/ gen8_vme_surface_setup(ctx, encode_state, is_intra, encoder_context); gen8_vme_interface_setup(ctx, encode_state, encoder_context); //gen8_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context); gen8_vme_constant_setup(ctx, encode_state, encoder_context); /*Programing media pipeline*/ gen8_vme_pipeline_programing(ctx, encode_state, encoder_context); return vaStatus; } static VAStatus gen8_vme_run(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; intel_batchbuffer_flush(batch); return VA_STATUS_SUCCESS; } static VAStatus gen8_vme_stop(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { return VA_STATUS_SUCCESS; } static VAStatus gen8_vme_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen8_vme_media_init(ctx, encoder_context); gen8_vme_prepare(ctx, encode_state, encoder_context); gen8_vme_run(ctx, encode_state, encoder_context); gen8_vme_stop(ctx, encode_state, encoder_context); return VA_STATUS_SUCCESS; } static void gen8_vme_mpeg2_output_buffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, int is_intra, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs; vme_context->vme_output.pitch = 16; /* in bytes, always 16 */ if (is_intra) vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2; else vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24; /* * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref * + 16 FBR Info + 128 FBR MV + 32 FBR Ref. * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24. */ vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr, "VME output buffer", vme_context->vme_output.num_blocks * vme_context->vme_output.size_block, 0x1000); assert(vme_context->vme_output.bo); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_output, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static void gen8_vme_mpeg2_output_vme_batchbuffer_setup(VADriverContextP ctx, struct encode_state *encode_state, int index, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_vme_context *vme_context = encoder_context->vme_context; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1; vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */ vme_context->vme_batchbuffer.pitch = 16; vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr, "VME batchbuffer", vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block, 0x1000); vme_context->vme_buffer_suface_setup(ctx, &vme_context->gpe_context, &vme_context->vme_batchbuffer, BINDING_TABLE_OFFSET(index), SURFACE_STATE_OFFSET(index)); } static VAStatus gen8_vme_mpeg2_surface_setup(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct object_surface *obj_surface; /*Setup surfaces state*/ /* current picture for encoding */ obj_surface = encode_state->input_yuv_object; gen8_vme_source_surface_state(ctx, 0, obj_surface, encoder_context); gen8_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context); gen8_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context); if (!is_intra) { /* reference 0 */ obj_surface = encode_state->reference_objects[0]; if (obj_surface->bo != NULL) gen8_vme_source_surface_state(ctx, 1, obj_surface, encoder_context); /* reference 1 */ obj_surface = encode_state->reference_objects[1]; if (obj_surface && obj_surface->bo != NULL) gen8_vme_source_surface_state(ctx, 2, obj_surface, encoder_context); } /* VME output */ gen8_vme_mpeg2_output_buffer_setup(ctx, encode_state, 3, is_intra, encoder_context); gen8_vme_mpeg2_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context); return VA_STATUS_SUCCESS; } static void gen8wa_vme_mpeg2_walker_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; unsigned int *command_ptr; #define MPEG2_SCOREBOARD (1 << 21) dri_bo_map(vme_context->vme_batchbuffer.bo, 1); command_ptr = vme_context->vme_batchbuffer.bo->virtual; { unsigned int mb_intra_ub, score_dep; int x_outer, y_outer, x_inner, y_inner; int xtemp_outer = 0; int first_mb = 0; int num_mb = mb_width * mb_height; x_outer = 0; y_outer = 0; for (; x_outer < (mb_width -2 ) && !loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) { x_inner = x_outer; y_inner = y_outer; for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) { mb_intra_ub = 0; score_dep = 0; if (x_inner != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; score_dep |= MB_SCOREBOARD_A; } if (y_inner != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; score_dep |= MB_SCOREBOARD_B; if (x_inner != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (x_inner != (mb_width -1)) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; score_dep |= MB_SCOREBOARD_C; } } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = MPEG2_SCOREBOARD; /* Indirect data */ *command_ptr++ = 0; /* the (X, Y) term of scoreboard */ *command_ptr++ = ((y_inner << 16) | x_inner); *command_ptr++ = score_dep; /*inline data */ *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner); *command_ptr++ = ((1 << 18) | (1 << 16) | (mb_intra_ub << 8)); *command_ptr++ = CMD_MEDIA_STATE_FLUSH; *command_ptr++ = 0; x_inner -= 2; y_inner += 1; } x_outer += 1; } xtemp_outer = mb_width - 2; if (xtemp_outer < 0) xtemp_outer = 0; x_outer = xtemp_outer; y_outer = 0; for (;!loop_in_bounds(x_outer, y_outer, first_mb, num_mb, mb_width, mb_height); ) { y_inner = y_outer; x_inner = x_outer; for (; !loop_in_bounds(x_inner, y_inner, first_mb, num_mb, mb_width, mb_height);) { mb_intra_ub = 0; score_dep = 0; if (x_inner != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; score_dep |= MB_SCOREBOARD_A; } if (y_inner != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; score_dep |= MB_SCOREBOARD_B; if (x_inner != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (x_inner != (mb_width -1)) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; score_dep |= MB_SCOREBOARD_C; } } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = MPEG2_SCOREBOARD; /* Indirect data */ *command_ptr++ = 0; /* the (X, Y) term of scoreboard */ *command_ptr++ = ((y_inner << 16) | x_inner); *command_ptr++ = score_dep; /*inline data */ *command_ptr++ = (mb_width << 16 | y_inner << 8 | x_inner); *command_ptr++ = ((1 << 18) | (1 << 16) | (mb_intra_ub << 8)); *command_ptr++ = CMD_MEDIA_STATE_FLUSH; *command_ptr++ = 0; x_inner -= 2; y_inner += 1; } x_outer++; if (x_outer >= mb_width) { y_outer += 1; x_outer = xtemp_outer; } } } *command_ptr++ = MI_BATCH_BUFFER_END; *command_ptr++ = 0; dri_bo_unmap(vme_context->vme_batchbuffer.bo); return; } static void gen8_vme_mpeg2_fill_vme_batchbuffer(VADriverContextP ctx, struct encode_state *encode_state, int mb_width, int mb_height, int kernel, int transform_8x8_mode_flag, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; int mb_x = 0, mb_y = 0; int i, s, j; unsigned int *command_ptr; dri_bo_map(vme_context->vme_batchbuffer.bo, 1); command_ptr = vme_context->vme_batchbuffer.bo->virtual; for (s = 0; s < encode_state->num_slice_params_ext; s++) { VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer; for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) { int slice_mb_begin = slice_param->macroblock_address; int slice_mb_number = slice_param->num_macroblocks; unsigned int mb_intra_ub; for (i = 0; i < slice_mb_number;) { int mb_count = i + slice_mb_begin; mb_x = mb_count % mb_width; mb_y = mb_count / mb_width; mb_intra_ub = 0; if (mb_x != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE; } if (mb_y != 0) { mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B; if (mb_x != 0) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D; if (mb_x != (mb_width -1)) mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C; } *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2)); *command_ptr++ = kernel; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; /*inline data */ *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x); *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8)); *command_ptr++ = CMD_MEDIA_STATE_FLUSH; *command_ptr++ = 0; i += 1; } slice_param++; } } *command_ptr++ = MI_BATCH_BUFFER_END; *command_ptr++ = 0; dri_bo_unmap(vme_context->vme_batchbuffer.bo); } static void gen8_vme_mpeg2_pipeline_programing(VADriverContextP ctx, struct encode_state *encode_state, int is_intra, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = encoder_context->vme_context; struct intel_batchbuffer *batch = encoder_context->base.batch; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16; int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16; bool allow_hwscore = true; int s; int kernel_shader; VAEncPictureParameterBufferMPEG2 *pic_param = NULL; for (s = 0; s < encode_state->num_slice_params_ext; s++) { int j; VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer; for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) { if (slice_param->macroblock_address % width_in_mbs) { allow_hwscore = false; break; } } } pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; if (pic_param->picture_type == VAEncPictureTypeIntra) { allow_hwscore = false; kernel_shader = VME_INTRA_SHADER; } else { kernel_shader = VME_INTER_SHADER; } if (allow_hwscore) gen8wa_vme_mpeg2_walker_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, kernel_shader, encoder_context); else gen8_vme_mpeg2_fill_vme_batchbuffer(ctx, encode_state, width_in_mbs, height_in_mbs, is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER, 0, encoder_context); intel_batchbuffer_start_atomic(batch, 0x1000); gen8_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch); BEGIN_BATCH(batch, 4); OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0)); OUT_RELOC(batch, vme_context->vme_batchbuffer.bo, I915_GEM_DOMAIN_COMMAND, 0, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); intel_batchbuffer_end_atomic(batch); } static VAStatus gen8_vme_mpeg2_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { VAStatus vaStatus = VA_STATUS_SUCCESS; VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer; VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer; struct gen6_vme_context *vme_context = encoder_context->vme_context; if ((!vme_context->mpeg2_level) || (vme_context->mpeg2_level != (seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK))) { vme_context->mpeg2_level = seq_param->sequence_extension.bits.profile_and_level_indication & MPEG2_LEVEL_MASK; } /*Setup all the memory object*/ gen8_vme_mpeg2_surface_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context); gen8_vme_interface_setup(ctx, encode_state, encoder_context); //gen8_vme_vme_state_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context); intel_vme_mpeg2_state_setup(ctx, encode_state, encoder_context); gen8_vme_constant_setup(ctx, encode_state, encoder_context); /*Programing media pipeline*/ gen8_vme_mpeg2_pipeline_programing(ctx, encode_state, slice_param->is_intra_slice, encoder_context); return vaStatus; } static VAStatus gen8_vme_mpeg2_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { gen8_vme_media_init(ctx, encoder_context); gen8_vme_mpeg2_prepare(ctx, encode_state, encoder_context); gen8_vme_run(ctx, encode_state, encoder_context); gen8_vme_stop(ctx, encode_state, encoder_context); return VA_STATUS_SUCCESS; } static void gen8_vme_context_destroy(void *context) { struct gen6_vme_context *vme_context = context; gen8_gpe_context_destroy(&vme_context->gpe_context); dri_bo_unreference(vme_context->vme_output.bo); vme_context->vme_output.bo = NULL; dri_bo_unreference(vme_context->vme_state.bo); vme_context->vme_state.bo = NULL; dri_bo_unreference(vme_context->vme_batchbuffer.bo); vme_context->vme_batchbuffer.bo = NULL; if (vme_context->vme_state_message) { free(vme_context->vme_state_message); vme_context->vme_state_message = NULL; } free(vme_context); } Bool gen8_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context)); struct i965_kernel *vme_kernel_list = NULL; int i965_kernel_num; switch (encoder_context->codec) { case CODEC_H264: vme_kernel_list = gen8_vme_kernels; encoder_context->vme_pipeline = gen8_vme_pipeline; i965_kernel_num = sizeof(gen8_vme_kernels) / sizeof(struct i965_kernel); break; case CODEC_MPEG2: vme_kernel_list = gen8_vme_mpeg2_kernels; encoder_context->vme_pipeline = gen8_vme_mpeg2_pipeline; i965_kernel_num = sizeof(gen8_vme_mpeg2_kernels) / sizeof(struct i965_kernel); break; default: /* never get here */ assert(0); break; } vme_context->vme_kernel_sum = i965_kernel_num; vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; vme_context->gpe_context.idrt_size = sizeof(struct gen8_interface_descriptor_data) * MAX_INTERFACE_DESC_GEN6; vme_context->gpe_context.curbe_size = CURBE_TOTAL_DATA_LENGTH; vme_context->gpe_context.sampler_size = 0; vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1; vme_context->gpe_context.vfe_state.num_urb_entries = 64; vme_context->gpe_context.vfe_state.gpgpu_mode = 0; vme_context->gpe_context.vfe_state.urb_entry_size = 16; vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1; gen7_vme_scoreboard_init(ctx, vme_context); gen8_gpe_load_kernels(ctx, &vme_context->gpe_context, vme_kernel_list, i965_kernel_num); vme_context->vme_surface2_setup = gen8_gpe_surface2_setup; vme_context->vme_media_rw_surface_setup = gen8_gpe_media_rw_surface_setup; vme_context->vme_buffer_suface_setup = gen8_gpe_buffer_suface_setup; vme_context->vme_media_chroma_surface_setup = gen8_gpe_media_chroma_surface_setup; encoder_context->vme_context = vme_context; encoder_context->vme_context_destroy = gen8_vme_context_destroy; vme_context->vme_state_message = malloc(VME_MSG_LENGTH * sizeof(int)); return True; } intel-driver-1.3.0/src/i965_avc_bsd.c000066400000000000000000001144271231401140700172310ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #include "sysdeps.h" #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_avc_bsd.h" #include "i965_media_h264.h" #include "i965_media.h" #include "i965_decoder_utils.h" #include "intel_media.h" static void i965_avc_bsd_init_avc_bsd_surface(VADriverContextP ctx, struct object_surface *obj_surface, VAPictureParameterBufferH264 *pic_param, struct i965_h264_context *i965_h264_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); GenAvcSurface *avc_bsd_surface = obj_surface->private_data; obj_surface->free_private_data = gen_free_avc_surface; if (!avc_bsd_surface) { avc_bsd_surface = calloc(sizeof(GenAvcSurface), 1); assert((obj_surface->size & 0x3f) == 0); obj_surface->private_data = avc_bsd_surface; } avc_bsd_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag && !pic_param->seq_fields.bits.direct_8x8_inference_flag); if (avc_bsd_surface->dmv_top == NULL) { avc_bsd_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", DMV_SIZE, 0x1000); } if (avc_bsd_surface->dmv_bottom_flag && avc_bsd_surface->dmv_bottom == NULL) { avc_bsd_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr, "direct mv w/r buffer", DMV_SIZE, 0x1000); } } static void i965_bsd_ind_obj_base_address(VADriverContextP ctx, struct decode_state *decode_state, int slice, struct i965_h264_context *i965_h264_context) { struct intel_batchbuffer *batch = i965_h264_context->batch; dri_bo *ind_bo = decode_state->slice_datas[slice]->bo; BEGIN_BCS_BATCH(batch, 3); OUT_BCS_BATCH(batch, CMD_BSD_IND_OBJ_BASE_ADDR | (3 - 2)); OUT_BCS_RELOC(batch, ind_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } static void i965_avc_bsd_img_state(VADriverContextP ctx, struct decode_state *decode_state, struct i965_h264_context *i965_h264_context) { struct intel_batchbuffer *batch = i965_h264_context->batch; int qm_present_flag; int img_struct; int mbaff_frame_flag; unsigned int avc_it_command_header; unsigned int width_in_mbs, height_in_mbs; VAPictureParameterBufferH264 *pic_param; if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) qm_present_flag = 1; else qm_present_flag = 0; /* built-in QM matrices */ assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD) img_struct = 1; else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD) img_struct = 3; else img_struct = 0; if ((img_struct & 0x1) == 0x1) { assert(pic_param->pic_fields.bits.field_pic_flag == 0x1); } else { assert(pic_param->pic_fields.bits.field_pic_flag == 0x0); } if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */ assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0); assert(pic_param->pic_fields.bits.field_pic_flag == 0); } else { assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */ } mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag && !pic_param->pic_fields.bits.field_pic_flag); width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff); height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */ assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */ /* BSD unit doesn't support 4:2:2 and 4:4:4 picture */ assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */ pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */ assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */ avc_it_command_header = (CMD_MEDIA_OBJECT_EX | (12 - 2)); BEGIN_BCS_BATCH(batch, 6); OUT_BCS_BATCH(batch, CMD_AVC_BSD_IMG_STATE | (6 - 2)); OUT_BCS_BATCH(batch, ((width_in_mbs * height_in_mbs) & 0x7fff)); OUT_BCS_BATCH(batch, (height_in_mbs << 16) | (width_in_mbs << 0)); OUT_BCS_BATCH(batch, ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) | ((pic_param->chroma_qp_index_offset & 0x1f) << 16) | (SCAN_RASTER_ORDER << 15) | /* AVC ILDB Data */ (SCAN_SPECIAL_ORDER << 14) | /* AVC IT Command */ (SCAN_RASTER_ORDER << 13) | /* AVC IT Data */ (1 << 12) | /* always 1, hardware requirement */ (qm_present_flag << 10) | (img_struct << 8) | (16 << 0)); /* FIXME: always support 16 reference frames ??? */ OUT_BCS_BATCH(batch, (RESIDUAL_DATA_OFFSET << 24) | /* residual data offset */ (0 << 17) | /* don't overwrite SRT */ (0 << 16) | /* Un-SRT (Unsynchronized Root Thread) */ (0 << 12) | /* FIXME: no 16MV ??? */ (pic_param->seq_fields.bits.chroma_format_idc << 10) | (i965_h264_context->enable_avc_ildb << 8) | /* Enable ILDB writing output */ (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) | ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) | (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) | (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) | (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) | (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) | (mbaff_frame_flag << 1) | (pic_param->pic_fields.bits.field_pic_flag << 0)); OUT_BCS_BATCH(batch, avc_it_command_header); ADVANCE_BCS_BATCH(batch); } static void i965_avc_bsd_qm_state(VADriverContextP ctx, struct decode_state *decode_state, struct i965_h264_context *i965_h264_context) { struct intel_batchbuffer *batch = i965_h264_context->batch; int cmd_len; VAIQMatrixBufferH264 *iq_matrix; VAPictureParameterBufferH264 *pic_param; if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer) return; iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */ if (pic_param->pic_fields.bits.transform_8x8_mode_flag) cmd_len += 2 * 16; /* load two 8x8 scaling matrices */ BEGIN_BCS_BATCH(batch, cmd_len); OUT_BCS_BATCH(batch, CMD_AVC_BSD_QM_STATE | (cmd_len - 2)); if (pic_param->pic_fields.bits.transform_8x8_mode_flag) OUT_BCS_BATCH(batch, (0x0 << 8) | /* don't use default built-in matrices */ (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */ else OUT_BCS_BATCH(batch, (0x0 << 8) | /* don't use default built-in matrices */ (0x3f << 0)); /* six 4x4 scaling matrices */ intel_batchbuffer_data(batch, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4); if (pic_param->pic_fields.bits.transform_8x8_mode_flag) intel_batchbuffer_data(batch, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4); ADVANCE_BCS_BATCH(batch); } static void i965_avc_bsd_slice_state(VADriverContextP ctx, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct i965_h264_context *i965_h264_context) { struct intel_batchbuffer *batch = i965_h264_context->batch; int present_flag, cmd_len, list, j; uint8_t ref_idx_state[32]; char weightoffsets[32 * 6]; /* don't issue SLICE_STATE for intra-prediction decoding */ if (slice_param->slice_type == SLICE_TYPE_I || slice_param->slice_type == SLICE_TYPE_SI) return; cmd_len = 2; if (slice_param->slice_type == SLICE_TYPE_P || slice_param->slice_type == SLICE_TYPE_SP) { present_flag = PRESENT_REF_LIST0; cmd_len += 8; } else { present_flag = PRESENT_REF_LIST0 | PRESENT_REF_LIST1; cmd_len += 16; } if ((slice_param->slice_type == SLICE_TYPE_P || slice_param->slice_type == SLICE_TYPE_SP) && (pic_param->pic_fields.bits.weighted_pred_flag == 1)) { present_flag |= PRESENT_WEIGHT_OFFSET_L0; cmd_len += 48; } if ((slice_param->slice_type == SLICE_TYPE_B) && (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) { present_flag |= PRESENT_WEIGHT_OFFSET_L0 | PRESENT_WEIGHT_OFFSET_L1; cmd_len += 96; } BEGIN_BCS_BATCH(batch, cmd_len); OUT_BCS_BATCH(batch, CMD_AVC_BSD_SLICE_STATE | (cmd_len - 2)); OUT_BCS_BATCH(batch, present_flag); for (list = 0; list < 2; list++) { int flag, num_va_pics; VAPictureH264 *va_pic; if (list == 0) { flag = PRESENT_REF_LIST0; va_pic = slice_param->RefPicList0; num_va_pics = slice_param->num_ref_idx_l0_active_minus1 + 1; } else { flag = PRESENT_REF_LIST1; va_pic = slice_param->RefPicList1; num_va_pics = slice_param->num_ref_idx_l1_active_minus1 + 1; } if (!(present_flag & flag)) continue; gen5_fill_avc_ref_idx_state( ref_idx_state, va_pic, num_va_pics, i965_h264_context->fsid_list ); intel_batchbuffer_data(batch, ref_idx_state, sizeof(ref_idx_state)); } i965_h264_context->weight128_luma_l0 = 0; i965_h264_context->weight128_luma_l1 = 0; i965_h264_context->weight128_chroma_l0 = 0; i965_h264_context->weight128_chroma_l1 = 0; i965_h264_context->weight128_offset0_flag = 0; i965_h264_context->weight128_offset0 = 0; if (present_flag & PRESENT_WEIGHT_OFFSET_L0) { for (j = 0; j < 32; j++) { weightoffsets[j * 6 + 0] = slice_param->luma_offset_l0[j]; weightoffsets[j * 6 + 1] = slice_param->luma_weight_l0[j]; weightoffsets[j * 6 + 2] = slice_param->chroma_offset_l0[j][0]; weightoffsets[j * 6 + 3] = slice_param->chroma_weight_l0[j][0]; weightoffsets[j * 6 + 4] = slice_param->chroma_offset_l0[j][1]; weightoffsets[j * 6 + 5] = slice_param->chroma_weight_l0[j][1]; if (pic_param->pic_fields.bits.weighted_pred_flag == 1 || pic_param->pic_fields.bits.weighted_bipred_idc == 1) { if (i965_h264_context->use_hw_w128) { if (slice_param->luma_weight_l0[j] == 128) i965_h264_context->weight128_luma_l0 |= (1 << j); if (slice_param->chroma_weight_l0[j][0] == 128 || slice_param->chroma_weight_l0[j][1] == 128) i965_h264_context->weight128_chroma_l0 |= (1 << j); } else { /* FIXME: workaround for weight 128 */ if (slice_param->luma_weight_l0[j] == 128 || slice_param->chroma_weight_l0[j][0] == 128 || slice_param->chroma_weight_l0[j][1] == 128) i965_h264_context->weight128_offset0_flag = 1; } } } intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets)); } if (present_flag & PRESENT_WEIGHT_OFFSET_L1) { for (j = 0; j < 32; j++) { weightoffsets[j * 6 + 0] = slice_param->luma_offset_l1[j]; weightoffsets[j * 6 + 1] = slice_param->luma_weight_l1[j]; weightoffsets[j * 6 + 2] = slice_param->chroma_offset_l1[j][0]; weightoffsets[j * 6 + 3] = slice_param->chroma_weight_l1[j][0]; weightoffsets[j * 6 + 4] = slice_param->chroma_offset_l1[j][1]; weightoffsets[j * 6 + 5] = slice_param->chroma_weight_l1[j][1]; if (pic_param->pic_fields.bits.weighted_bipred_idc == 1) { if (i965_h264_context->use_hw_w128) { if (slice_param->luma_weight_l1[j] == 128) i965_h264_context->weight128_luma_l1 |= (1 << j); if (slice_param->chroma_weight_l1[j][0] == 128 || slice_param->chroma_weight_l1[j][1] == 128) i965_h264_context->weight128_chroma_l1 |= (1 << j); } else { if (slice_param->luma_weight_l0[j] == 128 || slice_param->chroma_weight_l0[j][0] == 128 || slice_param->chroma_weight_l0[j][1] == 128) i965_h264_context->weight128_offset0_flag = 1; } } } intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets)); } ADVANCE_BCS_BATCH(batch); } static void i965_avc_bsd_buf_base_state(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, struct i965_h264_context *i965_h264_context) { struct intel_batchbuffer *batch = i965_h264_context->batch; struct i965_avc_bsd_context *i965_avc_bsd_context; int i, j; VAPictureH264 *va_pic; struct object_surface *obj_surface; GenAvcSurface *avc_bsd_surface; i965_avc_bsd_context = &i965_h264_context->i965_avc_bsd_context; BEGIN_BCS_BATCH(batch, 74); OUT_BCS_BATCH(batch, CMD_AVC_BSD_BUF_BASE_STATE | (74 - 2)); OUT_BCS_RELOC(batch, i965_avc_bsd_context->bsd_raw_store.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_RELOC(batch, i965_avc_bsd_context->mpr_row_store.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BCS_RELOC(batch, i965_h264_context->avc_it_command_mb_info.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, i965_h264_context->avc_it_command_mb_info.mbs * i965_h264_context->use_avc_hw_scoreboard * MB_CMD_IN_BYTES); OUT_BCS_RELOC(batch, i965_h264_context->avc_it_data.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, (i965_h264_context->avc_it_data.write_offset << 6)); if (i965_h264_context->enable_avc_ildb) OUT_BCS_RELOC(batch, i965_h264_context->avc_ildb_data.bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_BATCH(batch, 0); for (i = 0; i < ARRAY_ELEMS(i965_h264_context->fsid_list); i++) { if (i965_h264_context->fsid_list[i].surface_id != VA_INVALID_ID && i965_h264_context->fsid_list[i].obj_surface && i965_h264_context->fsid_list[i].obj_surface->private_data) { int found = 0; for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) { va_pic = &pic_param->ReferenceFrames[j]; if (va_pic->flags & VA_PICTURE_H264_INVALID) continue; if (va_pic->picture_id == i965_h264_context->fsid_list[i].surface_id) { found = 1; break; } } assert(found == 1); obj_surface = i965_h264_context->fsid_list[i].obj_surface; avc_bsd_surface = obj_surface->private_data; OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); if (avc_bsd_surface->dmv_bottom_flag == 1) OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_bottom, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); else OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } va_pic = &pic_param->CurrPic; obj_surface = decode_state->render_object; obj_surface->flags &= ~SURFACE_REF_DIS_MASK; obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0); i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); /* initial uv component for YUV400 case */ if (pic_param->seq_fields.bits.chroma_format_idc == 0) { unsigned int uv_offset = obj_surface->width * obj_surface->height; unsigned int uv_size = obj_surface->width * obj_surface->height / 2; dri_bo_map(obj_surface->bo, 1); memset(obj_surface->bo->virtual + uv_offset, 0x80, uv_size); dri_bo_unmap(obj_surface->bo); } i965_avc_bsd_init_avc_bsd_surface(ctx, obj_surface, pic_param, i965_h264_context); avc_bsd_surface = obj_surface->private_data; OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); if (avc_bsd_surface->dmv_bottom_flag == 1) OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_bottom, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); else OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_top, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); /* POC List */ for (i = 0; i < ARRAY_ELEMS(i965_h264_context->fsid_list); i++) { if (i965_h264_context->fsid_list[i].surface_id != VA_INVALID_ID) { int found = 0; for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) { va_pic = &pic_param->ReferenceFrames[j]; if (va_pic->flags & VA_PICTURE_H264_INVALID) continue; if (va_pic->picture_id == i965_h264_context->fsid_list[i].surface_id) { found = 1; break; } } assert(found == 1); if (!(va_pic->flags & VA_PICTURE_H264_INVALID)) { OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt); OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt); } } else { OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); } } va_pic = &pic_param->CurrPic; OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt); OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt); ADVANCE_BCS_BATCH(batch); } static void g4x_avc_bsd_object(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, int slice_index, struct i965_h264_context *i965_h264_context) { struct intel_batchbuffer *batch = i965_h264_context->batch; int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */ if (slice_param) { int encrypted, counter_value, cmd_len; int slice_hor_pos, slice_ver_pos; int num_ref_idx_l0, num_ref_idx_l1; int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag && pic_param->seq_fields.bits.mb_adaptive_frame_field_flag); unsigned int slice_data_bit_offset; int weighted_pred_idc = 0; int first_mb_in_slice = 0; int slice_type; encrypted = 0; /* FIXME: which flag in VAAPI is used for encryption? */ if (encrypted) { cmd_len = 9; counter_value = 0; /* FIXME: ??? */ } else cmd_len = 8; slice_data_bit_offset = avc_get_first_mb_bit_offset_with_epb( decode_state->slice_datas[slice_index]->bo, slice_param, pic_param->pic_fields.bits.entropy_coding_mode_flag ); if (slice_param->slice_type == SLICE_TYPE_I || slice_param->slice_type == SLICE_TYPE_SI) slice_type = SLICE_TYPE_I; else if (slice_param->slice_type == SLICE_TYPE_P || slice_param->slice_type == SLICE_TYPE_SP) slice_type = SLICE_TYPE_P; else { assert(slice_param->slice_type == SLICE_TYPE_B); slice_type = SLICE_TYPE_B; } if (slice_type == SLICE_TYPE_I) { assert(slice_param->num_ref_idx_l0_active_minus1 == 0); assert(slice_param->num_ref_idx_l1_active_minus1 == 0); num_ref_idx_l0 = 0; num_ref_idx_l1 = 0; } else if (slice_type == SLICE_TYPE_P) { assert(slice_param->num_ref_idx_l1_active_minus1 == 0); num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = 0; } else { num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1; } if (slice_type == SLICE_TYPE_P) weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag; else if (slice_type == SLICE_TYPE_B) weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc; first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture; slice_hor_pos = first_mb_in_slice % width_in_mbs; slice_ver_pos = first_mb_in_slice / width_in_mbs; BEGIN_BCS_BATCH(batch, cmd_len); OUT_BCS_BATCH(batch, CMD_AVC_BSD_OBJECT | (cmd_len - 2)); OUT_BCS_BATCH(batch, (encrypted << 31) | ((slice_param->slice_data_size - (slice_data_bit_offset >> 3)) << 0)); OUT_BCS_BATCH(batch, (slice_param->slice_data_offset + (slice_data_bit_offset >> 3))); OUT_BCS_BATCH(batch, (0 << 31) | /* concealment mode: 0->intra 16x16 prediction, 1->inter P Copy */ (0 << 14) | /* ignore BSDPrematureComplete Error handling */ (0 << 13) | /* FIXME: ??? */ (0 << 12) | /* ignore MPR Error handling */ (0 << 10) | /* ignore Entropy Error handling */ (0 << 8) | /* ignore MB Header Error handling */ (slice_type << 0)); OUT_BCS_BATCH(batch, (num_ref_idx_l1 << 24) | (num_ref_idx_l0 << 16) | (slice_param->chroma_log2_weight_denom << 8) | (slice_param->luma_log2_weight_denom << 0)); OUT_BCS_BATCH(batch, (weighted_pred_idc << 30) | (slice_param->direct_spatial_mv_pred_flag << 29) | (slice_param->disable_deblocking_filter_idc << 27) | (slice_param->cabac_init_idc << 24) | ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) | ((slice_param->slice_beta_offset_div2 & 0xf) << 8) | ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0)); OUT_BCS_BATCH(batch, (slice_ver_pos << 24) | (slice_hor_pos << 16) | (first_mb_in_slice << 0)); OUT_BCS_BATCH(batch, (1 << 7) | ((0x7 - (slice_data_bit_offset & 0x7)) << 0)); if (encrypted) { OUT_BCS_BATCH(batch, counter_value); } ADVANCE_BCS_BATCH(batch); } else { BEGIN_BCS_BATCH(batch, 8); OUT_BCS_BATCH(batch, CMD_AVC_BSD_OBJECT | (8 - 2)); OUT_BCS_BATCH(batch, 0); /* indirect data length for phantom slice is 0 */ OUT_BCS_BATCH(batch, 0); /* indirect data start address for phantom slice is 0 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag)); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } } static void ironlake_avc_bsd_object(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, int slice_index, struct i965_h264_context *i965_h264_context) { struct intel_batchbuffer *batch = i965_h264_context->batch; int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1; int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */ if (slice_param) { int encrypted, counter_value; int slice_hor_pos, slice_ver_pos; int num_ref_idx_l0, num_ref_idx_l1; int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag && pic_param->seq_fields.bits.mb_adaptive_frame_field_flag); unsigned int slice_data_bit_offset; int weighted_pred_idc = 0; int first_mb_in_slice; int slice_type; encrypted = 0; /* FIXME: which flag in VAAPI is used for encryption? */ if (encrypted) { counter_value = 0; /* FIXME: ??? */ } else counter_value = 0; slice_data_bit_offset = avc_get_first_mb_bit_offset_with_epb( decode_state->slice_datas[slice_index]->bo, slice_param, pic_param->pic_fields.bits.entropy_coding_mode_flag ); if (slice_param->slice_type == SLICE_TYPE_I || slice_param->slice_type == SLICE_TYPE_SI) slice_type = SLICE_TYPE_I; else if (slice_param->slice_type == SLICE_TYPE_P || slice_param->slice_type == SLICE_TYPE_SP) slice_type = SLICE_TYPE_P; else { assert(slice_param->slice_type == SLICE_TYPE_B); slice_type = SLICE_TYPE_B; } if (slice_type == SLICE_TYPE_I) { assert(slice_param->num_ref_idx_l0_active_minus1 == 0); assert(slice_param->num_ref_idx_l1_active_minus1 == 0); num_ref_idx_l0 = 0; num_ref_idx_l1 = 0; } else if (slice_type == SLICE_TYPE_P) { assert(slice_param->num_ref_idx_l1_active_minus1 == 0); num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = 0; } else { num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1; num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1; } if (slice_type == SLICE_TYPE_P) weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag; else if (slice_type == SLICE_TYPE_B) weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc; first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture; slice_hor_pos = first_mb_in_slice % width_in_mbs; slice_ver_pos = first_mb_in_slice / width_in_mbs; BEGIN_BCS_BATCH(batch, 16); OUT_BCS_BATCH(batch, CMD_AVC_BSD_OBJECT | (16 - 2)); OUT_BCS_BATCH(batch, (encrypted << 31) | (0 << 30) | /* FIXME: packet based bit stream */ (0 << 29) | /* FIXME: packet format */ ((slice_param->slice_data_size - (slice_data_bit_offset >> 3)) << 0)); OUT_BCS_BATCH(batch, (slice_param->slice_data_offset + (slice_data_bit_offset >> 3))); OUT_BCS_BATCH(batch, (0 << 31) | /* concealment mode: 0->intra 16x16 prediction, 1->inter P Copy */ (0 << 14) | /* ignore BSDPrematureComplete Error handling */ (0 << 13) | /* FIXME: ??? */ (0 << 12) | /* ignore MPR Error handling */ (0 << 10) | /* ignore Entropy Error handling */ (0 << 8) | /* ignore MB Header Error handling */ (slice_type << 0)); OUT_BCS_BATCH(batch, (num_ref_idx_l1 << 24) | (num_ref_idx_l0 << 16) | (slice_param->chroma_log2_weight_denom << 8) | (slice_param->luma_log2_weight_denom << 0)); OUT_BCS_BATCH(batch, (weighted_pred_idc << 30) | (slice_param->direct_spatial_mv_pred_flag << 29) | (slice_param->disable_deblocking_filter_idc << 27) | (slice_param->cabac_init_idc << 24) | ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) | ((slice_param->slice_beta_offset_div2 & 0xf) << 8) | ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0)); OUT_BCS_BATCH(batch, (slice_ver_pos << 24) | (slice_hor_pos << 16) | (first_mb_in_slice << 0)); OUT_BCS_BATCH(batch, (1 << 7) | ((0x7 - (slice_data_bit_offset & 0x7)) << 0)); OUT_BCS_BATCH(batch, counter_value); /* FIXME: dw9-dw11 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, i965_h264_context->weight128_luma_l0); OUT_BCS_BATCH(batch, i965_h264_context->weight128_luma_l1); OUT_BCS_BATCH(batch, i965_h264_context->weight128_chroma_l0); OUT_BCS_BATCH(batch, i965_h264_context->weight128_chroma_l1); ADVANCE_BCS_BATCH(batch); } else { BEGIN_BCS_BATCH(batch, 16); OUT_BCS_BATCH(batch, CMD_AVC_BSD_OBJECT | (16 - 2)); OUT_BCS_BATCH(batch, 0); /* indirect data length for phantom slice is 0 */ OUT_BCS_BATCH(batch, 0); /* indirect data start address for phantom slice is 0 */ OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag)); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } } static void i965_avc_bsd_object(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferH264 *pic_param, VASliceParameterBufferH264 *slice_param, int slice_index, struct i965_h264_context *i965_h264_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); if (IS_IRONLAKE(i965->intel.device_id)) ironlake_avc_bsd_object(ctx, decode_state, pic_param, slice_param, slice_index, i965_h264_context); else g4x_avc_bsd_object(ctx, decode_state, pic_param, slice_param, slice_index, i965_h264_context); } static void i965_avc_bsd_phantom_slice(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferH264 *pic_param, struct i965_h264_context *i965_h264_context) { i965_avc_bsd_object(ctx, decode_state, pic_param, NULL, 0, i965_h264_context); } void i965_avc_bsd_pipeline(VADriverContextP ctx, struct decode_state *decode_state, void *h264_context) { struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context; struct intel_batchbuffer *batch = i965_h264_context->batch; VAPictureParameterBufferH264 *pic_param; VASliceParameterBufferH264 *slice_param; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; intel_update_avc_frame_store_index(ctx, decode_state, pic_param, i965_h264_context->fsid_list); i965_h264_context->enable_avc_ildb = 0; i965_h264_context->picture.i_flag = 1; for (j = 0; j < decode_state->num_slice_params && i965_h264_context->enable_avc_ildb == 0; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); assert((slice_param->slice_type == SLICE_TYPE_I) || (slice_param->slice_type == SLICE_TYPE_SI) || (slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP) || (slice_param->slice_type == SLICE_TYPE_B)); if (slice_param->disable_deblocking_filter_idc != 1) { i965_h264_context->enable_avc_ildb = 1; break; } slice_param++; } } intel_batchbuffer_start_atomic_bcs(batch, 0x1000); i965_avc_bsd_img_state(ctx, decode_state, i965_h264_context); i965_avc_bsd_qm_state(ctx, decode_state, i965_h264_context); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params && decode_state->slice_params[j]->buffer); slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer; i965_bsd_ind_obj_base_address(ctx, decode_state, j, i965_h264_context); for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); assert((slice_param->slice_type == SLICE_TYPE_I) || (slice_param->slice_type == SLICE_TYPE_SI) || (slice_param->slice_type == SLICE_TYPE_P) || (slice_param->slice_type == SLICE_TYPE_SP) || (slice_param->slice_type == SLICE_TYPE_B)); if (i965_h264_context->picture.i_flag && (slice_param->slice_type != SLICE_TYPE_I || slice_param->slice_type != SLICE_TYPE_SI)) i965_h264_context->picture.i_flag = 0; i965_avc_bsd_slice_state(ctx, pic_param, slice_param, i965_h264_context); i965_avc_bsd_buf_base_state(ctx, decode_state, pic_param, slice_param, i965_h264_context); i965_avc_bsd_object(ctx, decode_state, pic_param, slice_param, j, i965_h264_context); slice_param++; } } i965_avc_bsd_phantom_slice(ctx, decode_state, pic_param, i965_h264_context); intel_batchbuffer_emit_mi_flush(batch); intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); } void i965_avc_bsd_decode_init(VADriverContextP ctx, void *h264_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context; struct i965_avc_bsd_context *i965_avc_bsd_context; dri_bo *bo; assert(i965_h264_context); i965_avc_bsd_context = &i965_h264_context->i965_avc_bsd_context; dri_bo_unreference(i965_avc_bsd_context->bsd_raw_store.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "bsd raw store", 0x3000, /* at least 11520 bytes to support 120 MBs per row */ 64); assert(bo); i965_avc_bsd_context->bsd_raw_store.bo = bo; dri_bo_unreference(i965_avc_bsd_context->mpr_row_store.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "mpr row store", 0x2000, /* at least 7680 bytes to support 120 MBs per row */ 64); assert(bo); i965_avc_bsd_context->mpr_row_store.bo = bo; } Bool i965_avc_bsd_ternimate(struct i965_avc_bsd_context *i965_avc_bsd_context) { dri_bo_unreference(i965_avc_bsd_context->bsd_raw_store.bo); dri_bo_unreference(i965_avc_bsd_context->mpr_row_store.bo); return True; } intel-driver-1.3.0/src/i965_avc_bsd.h000066400000000000000000000033171231401140700172310ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #ifndef __I965_AVC_BSD_H__ #define __I965_AVC_BSD_H__ #define DMV_SIZE 0x88000 /* 557056 bytes for a frame */ struct i965_avc_bsd_context { struct { dri_bo *bo; } bsd_raw_store; struct { dri_bo *bo; } mpr_row_store; }; void i965_avc_bsd_pipeline(VADriverContextP, struct decode_state *, void *h264_context); void i965_avc_bsd_decode_init(VADriverContextP, void *h264_context); Bool i965_avc_bsd_ternimate(struct i965_avc_bsd_context *); #endif /* __I965_AVC_BSD_H__ */ intel-driver-1.3.0/src/i965_avc_hw_scoreboard.c000066400000000000000000000451151231401140700212770ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_avc_hw_scoreboard.h" #include "i965_media_h264.h" #include "i965_media.h" /* On Ironlake */ #include "shaders/h264/mc/export.inc.gen5" enum { AVC_HW_SCOREBOARD = 0, AVC_HW_SCOREBOARD_MBAFF }; static unsigned long avc_hw_scoreboard_kernel_offset[] = { SETHWSCOREBOARD_IP_GEN5 * INST_UNIT_GEN5, SETHWSCOREBOARD_MBAFF_IP_GEN5 * INST_UNIT_GEN5 }; static unsigned int avc_hw_scoreboard_constants[] = { 0x08040201, 0x00000010, 0x08000210, 0x00000000, 0x08040201, 0x08040210, 0x01000010, 0x08040200 }; static void i965_avc_hw_scoreboard_surface_state(struct i965_h264_context *i965_h264_context) { struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; struct i965_surface_state *ss; dri_bo *bo; bo = avc_hw_scoreboard_context->surface.ss_bo; dri_bo_map(bo, 1); assert(bo->virtual); ss = bo->virtual; memset(ss, 0, sizeof(*ss)); ss->ss0.surface_type = I965_SURFACE_BUFFER; ss->ss1.base_addr = avc_hw_scoreboard_context->surface.s_bo->offset; ss->ss2.width = ((avc_hw_scoreboard_context->surface.total_mbs * MB_CMD_IN_OWS - 1) & 0x7f); ss->ss2.height = (((avc_hw_scoreboard_context->surface.total_mbs * MB_CMD_IN_OWS - 1) >> 7) & 0x1fff); ss->ss3.depth = (((avc_hw_scoreboard_context->surface.total_mbs * MB_CMD_IN_OWS - 1) >> 20) & 0x7f); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0, offsetof(struct i965_surface_state, ss1), avc_hw_scoreboard_context->surface.s_bo); dri_bo_unmap(bo); } static void i965_avc_hw_scoreboard_interface_descriptor_table(struct i965_h264_context *i965_h264_context) { struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; struct i965_interface_descriptor *desc; dri_bo *bo; bo = avc_hw_scoreboard_context->idrt.bo; dri_bo_map(bo, 1); assert(bo->virtual); desc = bo->virtual; memset(desc, 0, sizeof(*desc)); desc->desc0.grf_reg_blocks = 7; desc->desc0.kernel_start_pointer = (avc_hw_scoreboard_context->hw_kernel.bo->offset + avc_hw_scoreboard_context->hw_kernel.offset) >> 6; /* reloc */ desc->desc1.const_urb_entry_read_offset = 0; desc->desc1.const_urb_entry_read_len = 1; desc->desc3.binding_table_entry_count = 0; desc->desc3.binding_table_pointer = avc_hw_scoreboard_context->binding_table.bo->offset >> 5; /*reloc */ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, desc->desc0.grf_reg_blocks + avc_hw_scoreboard_context->hw_kernel.offset, offsetof(struct i965_interface_descriptor, desc0), avc_hw_scoreboard_context->hw_kernel.bo); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, desc->desc3.binding_table_entry_count, offsetof(struct i965_interface_descriptor, desc3), avc_hw_scoreboard_context->binding_table.bo); dri_bo_unmap(bo); } static void i965_avc_hw_scoreboard_binding_table(struct i965_h264_context *i965_h264_context) { struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; unsigned int *binding_table; dri_bo *bo = avc_hw_scoreboard_context->binding_table.bo; dri_bo_map(bo, 1); assert(bo->virtual); binding_table = bo->virtual; memset(binding_table, 0, bo->size); binding_table[0] = avc_hw_scoreboard_context->surface.ss_bo->offset; dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, 0, avc_hw_scoreboard_context->surface.ss_bo); dri_bo_unmap(bo); } static void i965_avc_hw_scoreboard_vfe_state(struct i965_h264_context *i965_h264_context) { struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; struct i965_vfe_state *vfe_state; dri_bo *bo; bo = avc_hw_scoreboard_context->vfe_state.bo; dri_bo_map(bo, 1); assert(bo->virtual); vfe_state = bo->virtual; memset(vfe_state, 0, sizeof(*vfe_state)); vfe_state->vfe1.max_threads = avc_hw_scoreboard_context->urb.num_vfe_entries - 1; vfe_state->vfe1.urb_entry_alloc_size = avc_hw_scoreboard_context->urb.size_vfe_entry - 1; vfe_state->vfe1.num_urb_entries = avc_hw_scoreboard_context->urb.num_vfe_entries; vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE; vfe_state->vfe1.children_present = 0; vfe_state->vfe2.interface_descriptor_base = avc_hw_scoreboard_context->idrt.bo->offset >> 4; /* reloc */ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, offsetof(struct i965_vfe_state, vfe2), avc_hw_scoreboard_context->idrt.bo); dri_bo_unmap(bo); } static void i965_avc_hw_scoreboard_upload_constants(struct i965_h264_context *i965_h264_context) { struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; unsigned char *constant_buffer; if (avc_hw_scoreboard_context->curbe.upload) return; dri_bo_map(avc_hw_scoreboard_context->curbe.bo, 1); assert(avc_hw_scoreboard_context->curbe.bo->virtual); constant_buffer = avc_hw_scoreboard_context->curbe.bo->virtual; memcpy(constant_buffer, avc_hw_scoreboard_constants, sizeof(avc_hw_scoreboard_constants)); dri_bo_unmap(avc_hw_scoreboard_context->curbe.bo); avc_hw_scoreboard_context->curbe.upload = 1; } static void i965_avc_hw_scoreboard_states_setup(struct i965_h264_context *i965_h264_context) { i965_avc_hw_scoreboard_surface_state(i965_h264_context); i965_avc_hw_scoreboard_binding_table(i965_h264_context); i965_avc_hw_scoreboard_interface_descriptor_table(i965_h264_context); i965_avc_hw_scoreboard_vfe_state(i965_h264_context); i965_avc_hw_scoreboard_upload_constants(i965_h264_context); } static void i965_avc_hw_scoreboard_pipeline_select(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct intel_batchbuffer *batch = i965_h264_context->batch; BEGIN_BATCH(batch, 1); OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); ADVANCE_BATCH(batch); } static void i965_avc_hw_scoreboard_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965_h264_context->batch; unsigned int vfe_fence, cs_fence; vfe_fence = avc_hw_scoreboard_context->urb.cs_start; cs_fence = URB_SIZE((&i965->intel)); BEGIN_BATCH(batch, 3); OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1); OUT_BATCH(batch, 0); OUT_BATCH(batch, (vfe_fence << UF2_VFE_FENCE_SHIFT) | /* VFE_SIZE */ (cs_fence << UF2_CS_FENCE_SHIFT)); /* CS_SIZE */ ADVANCE_BATCH(batch); } static void i965_avc_hw_scoreboard_state_base_address(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct intel_batchbuffer *batch = i965_h264_context->batch; BEGIN_BATCH(batch, 8); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); ADVANCE_BATCH(batch); } static void i965_avc_hw_scoreboard_state_pointers(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; struct intel_batchbuffer *batch = i965_h264_context->batch; BEGIN_BATCH(batch, 3); OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1); OUT_BATCH(batch, 0); OUT_RELOC(batch, avc_hw_scoreboard_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_BATCH(batch); } static void i965_avc_hw_scoreboard_cs_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; struct intel_batchbuffer *batch = i965_h264_context->batch; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, CMD_CS_URB_STATE | 0); OUT_BATCH(batch, ((avc_hw_scoreboard_context->urb.size_cs_entry - 1) << 4) | /* URB Entry Allocation Size */ (avc_hw_scoreboard_context->urb.num_cs_entries << 0)); /* Number of URB Entries */ ADVANCE_BATCH(batch); } static void i965_avc_hw_scoreboard_constant_buffer(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; struct intel_batchbuffer *batch = i965_h264_context->batch; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2)); OUT_RELOC(batch, avc_hw_scoreboard_context->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, avc_hw_scoreboard_context->urb.size_cs_entry - 1); ADVANCE_BATCH(batch); } static void i965_avc_hw_scoreboard_objects(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; struct intel_batchbuffer *batch = i965_h264_context->batch; int number_mb_cmds = 512; int starting_mb_number = avc_hw_scoreboard_context->inline_data.starting_mb_number; int i; for (i = 0; i < avc_hw_scoreboard_context->inline_data.num_mb_cmds / 512; i++) { BEGIN_BATCH(batch, 6); OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4); OUT_BATCH(batch, 0); /* interface descriptor offset: 0 */ OUT_BATCH(batch, 0); /* no indirect data */ OUT_BATCH(batch, 0); OUT_BATCH(batch, ((number_mb_cmds << 16) | (starting_mb_number << 0))); OUT_BATCH(batch, avc_hw_scoreboard_context->inline_data.pic_width_in_mbs); ADVANCE_BATCH(batch); starting_mb_number += 512; } number_mb_cmds = avc_hw_scoreboard_context->inline_data.num_mb_cmds % 512; if (number_mb_cmds) { BEGIN_BATCH(batch, 6); OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4); OUT_BATCH(batch, 0); /* interface descriptor offset: 0 */ OUT_BATCH(batch, 0); /* no indirect data */ OUT_BATCH(batch, 0); OUT_BATCH(batch, ((number_mb_cmds << 16) | (starting_mb_number << 0))); OUT_BATCH(batch, avc_hw_scoreboard_context->inline_data.pic_width_in_mbs); ADVANCE_BATCH(batch); } } static void i965_avc_hw_scoreboard_pipeline_setup(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct intel_batchbuffer *batch = i965_h264_context->batch; intel_batchbuffer_start_atomic(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); i965_avc_hw_scoreboard_pipeline_select(ctx, i965_h264_context); i965_avc_hw_scoreboard_state_base_address(ctx, i965_h264_context); i965_avc_hw_scoreboard_state_pointers(ctx, i965_h264_context); i965_avc_hw_scoreboard_urb_layout(ctx, i965_h264_context); i965_avc_hw_scoreboard_cs_urb_layout(ctx, i965_h264_context); i965_avc_hw_scoreboard_constant_buffer(ctx, i965_h264_context); i965_avc_hw_scoreboard_objects(ctx, i965_h264_context); intel_batchbuffer_end_atomic(batch); } void i965_avc_hw_scoreboard(VADriverContextP ctx, struct decode_state *decode_state, void *h264_context) { struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context; if (i965_h264_context->use_avc_hw_scoreboard) { struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; avc_hw_scoreboard_context->inline_data.num_mb_cmds = i965_h264_context->avc_it_command_mb_info.mbs; avc_hw_scoreboard_context->inline_data.starting_mb_number = i965_h264_context->avc_it_command_mb_info.mbs; avc_hw_scoreboard_context->inline_data.pic_width_in_mbs = i965_h264_context->picture.width_in_mbs; avc_hw_scoreboard_context->surface.total_mbs = i965_h264_context->avc_it_command_mb_info.mbs * 2; dri_bo_unreference(avc_hw_scoreboard_context->hw_kernel.bo); avc_hw_scoreboard_context->hw_kernel.bo = i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo; assert(avc_hw_scoreboard_context->hw_kernel.bo != NULL); dri_bo_reference(avc_hw_scoreboard_context->hw_kernel.bo); if (i965_h264_context->picture.mbaff_frame_flag) avc_hw_scoreboard_context->hw_kernel.offset = avc_hw_scoreboard_kernel_offset[AVC_HW_SCOREBOARD_MBAFF]; else avc_hw_scoreboard_context->hw_kernel.offset = avc_hw_scoreboard_kernel_offset[AVC_HW_SCOREBOARD]; i965_avc_hw_scoreboard_states_setup(i965_h264_context); i965_avc_hw_scoreboard_pipeline_setup(ctx, i965_h264_context); } } void i965_avc_hw_scoreboard_decode_init(VADriverContextP ctx, void *h264_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context; if (i965_h264_context->use_avc_hw_scoreboard) { struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context; dri_bo *bo; if (avc_hw_scoreboard_context->curbe.bo == NULL) { bo = dri_bo_alloc(i965->intel.bufmgr, "constant buffer", 4096, 64); assert(bo); avc_hw_scoreboard_context->curbe.bo = bo; avc_hw_scoreboard_context->curbe.upload = 0; } dri_bo_unreference(avc_hw_scoreboard_context->surface.s_bo); avc_hw_scoreboard_context->surface.s_bo = i965_h264_context->avc_it_command_mb_info.bo; assert(avc_hw_scoreboard_context->surface.s_bo != NULL); dri_bo_reference(avc_hw_scoreboard_context->surface.s_bo); dri_bo_unreference(avc_hw_scoreboard_context->surface.ss_bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state", sizeof(struct i965_surface_state), 32); assert(bo); avc_hw_scoreboard_context->surface.ss_bo = bo; dri_bo_unreference(avc_hw_scoreboard_context->binding_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "binding table", MAX_MEDIA_SURFACES * sizeof(unsigned int), 32); assert(bo); avc_hw_scoreboard_context->binding_table.bo = bo; dri_bo_unreference(avc_hw_scoreboard_context->idrt.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "interface discriptor", MAX_INTERFACE_DESC * sizeof(struct i965_interface_descriptor), 16); assert(bo); avc_hw_scoreboard_context->idrt.bo = bo; dri_bo_unreference(avc_hw_scoreboard_context->vfe_state.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vfe state", sizeof(struct i965_vfe_state), 32); assert(bo); avc_hw_scoreboard_context->vfe_state.bo = bo; avc_hw_scoreboard_context->urb.num_vfe_entries = 32; avc_hw_scoreboard_context->urb.size_vfe_entry = 2; avc_hw_scoreboard_context->urb.num_cs_entries = 1; avc_hw_scoreboard_context->urb.size_cs_entry = 1; avc_hw_scoreboard_context->urb.vfe_start = 0; avc_hw_scoreboard_context->urb.cs_start = avc_hw_scoreboard_context->urb.vfe_start + avc_hw_scoreboard_context->urb.num_vfe_entries * avc_hw_scoreboard_context->urb.size_vfe_entry; assert(avc_hw_scoreboard_context->urb.cs_start + avc_hw_scoreboard_context->urb.num_cs_entries * avc_hw_scoreboard_context->urb.size_cs_entry <= URB_SIZE((&i965->intel))); } } Bool i965_avc_hw_scoreboard_ternimate(struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context) { dri_bo_unreference(avc_hw_scoreboard_context->curbe.bo); avc_hw_scoreboard_context->curbe.bo = NULL; dri_bo_unreference(avc_hw_scoreboard_context->surface.ss_bo); avc_hw_scoreboard_context->surface.ss_bo = NULL; dri_bo_unreference(avc_hw_scoreboard_context->surface.s_bo); avc_hw_scoreboard_context->surface.s_bo = NULL; dri_bo_unreference(avc_hw_scoreboard_context->binding_table.bo); avc_hw_scoreboard_context->binding_table.bo = NULL; dri_bo_unreference(avc_hw_scoreboard_context->idrt.bo); avc_hw_scoreboard_context->idrt.bo = NULL; dri_bo_unreference(avc_hw_scoreboard_context->vfe_state.bo); avc_hw_scoreboard_context->vfe_state.bo = NULL; dri_bo_unreference(avc_hw_scoreboard_context->hw_kernel.bo); avc_hw_scoreboard_context->hw_kernel.bo = NULL; return True; } intel-driver-1.3.0/src/i965_avc_hw_scoreboard.h000066400000000000000000000045771231401140700213130ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #ifndef __I965_AVC_HW_SCOREBOARD_H__ #define __I965_AVC_HW_SCOREBOARD_H__ struct i965_avc_hw_scoreboard_context { struct { unsigned int num_mb_cmds; unsigned int starting_mb_number; unsigned int pic_width_in_mbs; } inline_data; struct { dri_bo *ss_bo; dri_bo *s_bo; unsigned int total_mbs; } surface; struct { dri_bo *bo; } binding_table; struct { dri_bo *bo; } idrt; struct { dri_bo *bo; } vfe_state; struct { dri_bo *bo; int upload; } curbe; struct { dri_bo *bo; unsigned long offset; } hw_kernel; struct { unsigned int vfe_start; unsigned int cs_start; unsigned int num_vfe_entries; unsigned int num_cs_entries; unsigned int size_vfe_entry; unsigned int size_cs_entry; } urb; }; void i965_avc_hw_scoreboard(VADriverContextP, struct decode_state *, void *h264_context); void i965_avc_hw_scoreboard_decode_init(VADriverContextP, void *h264_context); Bool i965_avc_hw_scoreboard_ternimate(struct i965_avc_hw_scoreboard_context *); #endif /* __I965_AVC_HW_SCOREBOARD_H__ */ intel-driver-1.3.0/src/i965_avc_ildb.c000066400000000000000000000646131231401140700173740ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_avc_ildb.h" #include "i965_media_h264.h" #include "i965_media.h" /* On Cantiga */ #include "shaders/h264/mc/export.inc" /* On Ironlake */ #include "shaders/h264/mc/export.inc.gen5" #define PICTURE_FRAME 0 #define PICTURE_FIELD 1 #define PICTURE_MBAFF 2 enum { AVC_ILDB_ROOT_Y_ILDB_FRAME, AVC_ILDB_CHILD_Y_ILDB_FRAME, AVC_ILDB_ROOT_UV_ILDB_FRAME, AVC_ILDB_CHILD_UV_ILDB_FRAME, AVC_ILDB_ROOT_Y_ILDB_FIELD, AVC_ILDB_CHILD_Y_ILDB_FIELD, AVC_ILDB_ROOT_UV_ILDB_FIELD, AVC_ILDB_CHILD_UV_ILDB_FIELD, AVC_ILDB_ROOT_Y_ILDB_MBAFF, AVC_ILDB_CHILD_Y_ILDB_MBAFF, AVC_ILDB_ROOT_UV_ILDB_MBAFF, AVC_ILDB_CHILD_UV_ILDB_MBAFF }; static unsigned long avc_ildb_kernel_offset_gen4[] = { AVC_ILDB_ROOT_Y_ILDB_FRAME_IP * INST_UNIT_GEN4, AVC_ILDB_CHILD_Y_ILDB_FRAME_IP * INST_UNIT_GEN4, AVC_ILDB_ROOT_UV_ILDB_FRAME_IP * INST_UNIT_GEN4, AVC_ILDB_CHILD_UV_ILDB_FRAME_IP * INST_UNIT_GEN4, AVC_ILDB_ROOT_Y_ILDB_FIELD_IP * INST_UNIT_GEN4, AVC_ILDB_CHILD_Y_ILDB_FIELD_IP * INST_UNIT_GEN4, AVC_ILDB_ROOT_UV_ILDB_FIELD_IP * INST_UNIT_GEN4, AVC_ILDB_CHILD_UV_ILDB_FIELD_IP * INST_UNIT_GEN4, AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP * INST_UNIT_GEN4, AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP * INST_UNIT_GEN4, AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP * INST_UNIT_GEN4, AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP * INST_UNIT_GEN4 }; static unsigned long avc_ildb_kernel_offset_gen5[] = { AVC_ILDB_ROOT_Y_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5, AVC_ILDB_CHILD_Y_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5, AVC_ILDB_ROOT_UV_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5, AVC_ILDB_CHILD_UV_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5, AVC_ILDB_ROOT_Y_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5, AVC_ILDB_CHILD_Y_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5, AVC_ILDB_ROOT_UV_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5, AVC_ILDB_CHILD_UV_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5, AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5, AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5, AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5, AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5 }; struct avc_ildb_root_input { unsigned int blocks_per_row : 16; unsigned int blocks_per_column : 16; unsigned int picture_type : 16; unsigned int max_concurrent_threads : 16; unsigned int debug_field : 16; unsigned int mbaff_frame_flag : 1; unsigned int bottom_field_flag : 1; unsigned int control_data_expansion_flag : 1; unsigned int chroma_format : 1; unsigned int pad0 : 12; unsigned int ramp_constant_0; unsigned int ramp_constant_1; int constant_0 : 8; int constant_1 : 8; int pad1 : 16; unsigned int pad2; unsigned int pad3; }; #define NUM_AVC_ILDB_INTERFACES ARRAY_ELEMS(avc_ildb_kernel_offset_gen4) static unsigned long *avc_ildb_kernel_offset = NULL; static void i965_avc_ildb_surface_state(VADriverContextP ctx, struct decode_state *decode_state, struct i965_h264_context *i965_h264_context) { struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context; struct i965_surface_state *ss; struct object_surface *obj_surface; VAPictureParameterBufferH264 *pic_param; VAPictureH264 *va_pic; dri_bo *bo; int i; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; va_pic = &pic_param->CurrPic; obj_surface = decode_state->render_object; avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].s_bo = i965_h264_context->avc_ildb_data.bo; dri_bo_reference(avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].s_bo); avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].offset = 0; avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].surface_type = I965_SURFACE_BUFFER; avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].width = ((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) & 0x7f); avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].height = (((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) >> 7) & 0x1fff); avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].depth = (((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) >> 20) & 0x7f); avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].pitch = EDGE_CONTROL_DATA_IN_BTYES - 1; avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].is_target = 0; avc_ildb_context->surface[SURFACE_SRC_Y].s_bo = obj_surface->bo; dri_bo_reference(avc_ildb_context->surface[SURFACE_SRC_Y].s_bo); avc_ildb_context->surface[SURFACE_SRC_Y].offset = 0; avc_ildb_context->surface[SURFACE_SRC_Y].surface_type = I965_SURFACE_2D; avc_ildb_context->surface[SURFACE_SRC_Y].format = I965_SURFACEFORMAT_R8_SINT; avc_ildb_context->surface[SURFACE_SRC_Y].width = obj_surface->width / 4 - 1; avc_ildb_context->surface[SURFACE_SRC_Y].height = obj_surface->height - 1; avc_ildb_context->surface[SURFACE_SRC_Y].depth = 0; avc_ildb_context->surface[SURFACE_SRC_Y].pitch = obj_surface->width - 1; avc_ildb_context->surface[SURFACE_SRC_Y].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD)); avc_ildb_context->surface[SURFACE_SRC_Y].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD); avc_ildb_context->surface[SURFACE_SRC_Y].is_target = 0; avc_ildb_context->surface[SURFACE_SRC_UV].s_bo = obj_surface->bo; dri_bo_reference(avc_ildb_context->surface[SURFACE_SRC_UV].s_bo); avc_ildb_context->surface[SURFACE_SRC_UV].offset = obj_surface->width * obj_surface->height; avc_ildb_context->surface[SURFACE_SRC_UV].surface_type = I965_SURFACE_2D; avc_ildb_context->surface[SURFACE_SRC_UV].format = I965_SURFACEFORMAT_R8G8_SINT; avc_ildb_context->surface[SURFACE_SRC_UV].width = obj_surface->width / 4 - 1; avc_ildb_context->surface[SURFACE_SRC_UV].height = obj_surface->height / 2 - 1; avc_ildb_context->surface[SURFACE_SRC_UV].depth = 0; avc_ildb_context->surface[SURFACE_SRC_UV].pitch = obj_surface->width - 1; avc_ildb_context->surface[SURFACE_SRC_UV].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD)); avc_ildb_context->surface[SURFACE_SRC_UV].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD); avc_ildb_context->surface[SURFACE_SRC_UV].is_target = 0; avc_ildb_context->surface[SURFACE_DEST_Y].s_bo = obj_surface->bo; dri_bo_reference(avc_ildb_context->surface[SURFACE_DEST_Y].s_bo); avc_ildb_context->surface[SURFACE_DEST_Y].offset = 0; avc_ildb_context->surface[SURFACE_DEST_Y].surface_type = I965_SURFACE_2D; avc_ildb_context->surface[SURFACE_DEST_Y].format = I965_SURFACEFORMAT_R8_SINT; avc_ildb_context->surface[SURFACE_DEST_Y].width = obj_surface->width / 4 - 1; avc_ildb_context->surface[SURFACE_DEST_Y].height = obj_surface->height - 1; avc_ildb_context->surface[SURFACE_DEST_Y].depth = 0; avc_ildb_context->surface[SURFACE_DEST_Y].pitch = obj_surface->width - 1; avc_ildb_context->surface[SURFACE_DEST_Y].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD)); avc_ildb_context->surface[SURFACE_DEST_Y].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD); avc_ildb_context->surface[SURFACE_DEST_Y].is_target = 1; avc_ildb_context->surface[SURFACE_DEST_UV].s_bo = obj_surface->bo; dri_bo_reference(avc_ildb_context->surface[SURFACE_DEST_UV].s_bo); avc_ildb_context->surface[SURFACE_DEST_UV].offset = obj_surface->width * obj_surface->height; avc_ildb_context->surface[SURFACE_DEST_UV].surface_type = I965_SURFACE_2D; avc_ildb_context->surface[SURFACE_DEST_UV].format = I965_SURFACEFORMAT_R8G8_SINT; avc_ildb_context->surface[SURFACE_DEST_UV].width = obj_surface->width / 4 - 1; avc_ildb_context->surface[SURFACE_DEST_UV].height = obj_surface->height / 2 - 1; avc_ildb_context->surface[SURFACE_DEST_UV].depth = 0; avc_ildb_context->surface[SURFACE_DEST_UV].pitch = obj_surface->width - 1; avc_ildb_context->surface[SURFACE_DEST_UV].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD)); avc_ildb_context->surface[SURFACE_DEST_UV].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD); avc_ildb_context->surface[SURFACE_DEST_UV].is_target = 1; for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) { bo = avc_ildb_context->surface[i].ss_bo; dri_bo_map(bo, 1); assert(bo->virtual); ss = bo->virtual; memset(ss, 0, sizeof(*ss)); ss->ss0.surface_type = avc_ildb_context->surface[i].surface_type; ss->ss0.surface_format = avc_ildb_context->surface[i].format; ss->ss0.vert_line_stride = avc_ildb_context->surface[i].vert_line_stride; ss->ss0.vert_line_stride_ofs = avc_ildb_context->surface[i].vert_line_stride_ofs; ss->ss1.base_addr = avc_ildb_context->surface[i].s_bo->offset + avc_ildb_context->surface[i].offset; ss->ss2.width = avc_ildb_context->surface[i].width; ss->ss2.height = avc_ildb_context->surface[i].height; ss->ss3.depth = avc_ildb_context->surface[i].depth; ss->ss3.pitch = avc_ildb_context->surface[i].pitch; dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, avc_ildb_context->surface[i].is_target ? I915_GEM_DOMAIN_RENDER : 0, avc_ildb_context->surface[i].offset, offsetof(struct i965_surface_state, ss1), avc_ildb_context->surface[i].s_bo); dri_bo_unmap(bo); } } static void i965_avc_ildb_binding_table(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context; unsigned int *binding_table; dri_bo *bo = avc_ildb_context->binding_table.bo; int i; dri_bo_map(bo, 1); assert(bo->virtual); binding_table = bo->virtual; memset(binding_table, 0, bo->size); for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) { binding_table[i] = avc_ildb_context->surface[i].ss_bo->offset; dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, i * sizeof(*binding_table), avc_ildb_context->surface[i].ss_bo); } dri_bo_unmap(bo); } static void i965_avc_ildb_interface_descriptor_table(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context; struct i965_interface_descriptor *desc; dri_bo *bo; int i; bo = avc_ildb_context->idrt.bo; dri_bo_map(bo, 1); assert(bo->virtual); desc = bo->virtual; for (i = 0; i < NUM_AVC_ILDB_INTERFACES; i++) { int kernel_offset = avc_ildb_kernel_offset[i]; memset(desc, 0, sizeof(*desc)); desc->desc0.grf_reg_blocks = 7; desc->desc0.kernel_start_pointer = (i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */ desc->desc1.const_urb_entry_read_offset = 0; desc->desc1.const_urb_entry_read_len = ((i == AVC_ILDB_ROOT_Y_ILDB_FRAME || i == AVC_ILDB_ROOT_Y_ILDB_FIELD || i == AVC_ILDB_ROOT_Y_ILDB_MBAFF) ? 1 : 0); desc->desc3.binding_table_entry_count = 0; desc->desc3.binding_table_pointer = avc_ildb_context->binding_table.bo->offset >> 5; /*reloc */ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, desc->desc0.grf_reg_blocks + kernel_offset, i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0), i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, desc->desc3.binding_table_entry_count, i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc3), avc_ildb_context->binding_table.bo); desc++; } dri_bo_unmap(bo); } static void i965_avc_ildb_vfe_state(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context; struct i965_vfe_state *vfe_state; dri_bo *bo; bo = avc_ildb_context->vfe_state.bo; dri_bo_map(bo, 1); assert(bo->virtual); vfe_state = bo->virtual; memset(vfe_state, 0, sizeof(*vfe_state)); vfe_state->vfe1.max_threads = 0; vfe_state->vfe1.urb_entry_alloc_size = avc_ildb_context->urb.size_vfe_entry - 1; vfe_state->vfe1.num_urb_entries = avc_ildb_context->urb.num_vfe_entries; vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE; vfe_state->vfe1.children_present = 1; vfe_state->vfe2.interface_descriptor_base = avc_ildb_context->idrt.bo->offset >> 4; /* reloc */ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, offsetof(struct i965_vfe_state, vfe2), avc_ildb_context->idrt.bo); dri_bo_unmap(bo); } static void i965_avc_ildb_upload_constants(VADriverContextP ctx, struct decode_state *decode_state, struct i965_h264_context *i965_h264_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context; VAPictureParameterBufferH264 *pic_param; struct avc_ildb_root_input *root_input; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; dri_bo_map(avc_ildb_context->curbe.bo, 1); assert(avc_ildb_context->curbe.bo->virtual); root_input = avc_ildb_context->curbe.bo->virtual; if (IS_IRONLAKE(i965->intel.device_id)) { root_input->max_concurrent_threads = 76; /* 72 - 2 + 8 - 2 */ } else { root_input->max_concurrent_threads = 54; /* 50 - 2 + 8 - 2 */ } if (pic_param->pic_fields.bits.field_pic_flag) root_input->picture_type = PICTURE_FIELD; else { if (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag) root_input->picture_type = PICTURE_MBAFF; else root_input->picture_type = PICTURE_FRAME; } avc_ildb_context->picture_type = root_input->picture_type; root_input->blocks_per_row = pic_param->picture_width_in_mbs_minus1 + 1; root_input->blocks_per_column = (pic_param->picture_height_in_mbs_minus1 + 1) / (1 + (root_input->picture_type != PICTURE_FRAME)); avc_ildb_context->mbs_per_picture = (pic_param->picture_width_in_mbs_minus1 + 1) * (pic_param->picture_height_in_mbs_minus1 + 1); root_input->mbaff_frame_flag = (root_input->picture_type == PICTURE_MBAFF); root_input->bottom_field_flag = !!(pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD); root_input->control_data_expansion_flag = 1; /* Always 1 on G4x+ */ root_input->chroma_format = (pic_param->seq_fields.bits.chroma_format_idc != 1); /* 0=4:0:0, 1=4:2:0 */ root_input->ramp_constant_0 = 0x03020100; root_input->ramp_constant_1 = 0x07060504; root_input->constant_0 = -2; root_input->constant_1 = 1; dri_bo_unmap(avc_ildb_context->curbe.bo); } static void i965_avc_ildb_states_setup(VADriverContextP ctx, struct decode_state *decode_state, struct i965_h264_context *i965_h264_context) { i965_avc_ildb_surface_state(ctx, decode_state, i965_h264_context); i965_avc_ildb_binding_table(ctx, i965_h264_context); i965_avc_ildb_interface_descriptor_table(ctx, i965_h264_context); i965_avc_ildb_vfe_state(ctx, i965_h264_context); i965_avc_ildb_upload_constants(ctx, decode_state, i965_h264_context); } static void i965_avc_ildb_pipeline_select(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct intel_batchbuffer *batch = i965_h264_context->batch; BEGIN_BATCH(batch, 1); OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); ADVANCE_BATCH(batch); } static void i965_avc_ildb_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context; struct intel_batchbuffer *batch = i965_h264_context->batch; unsigned int vfe_fence, cs_fence; vfe_fence = avc_ildb_context->urb.cs_start; cs_fence = URB_SIZE((&i965->intel)); BEGIN_BATCH(batch, 3); OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1); OUT_BATCH(batch, 0); OUT_BATCH(batch, (vfe_fence << UF2_VFE_FENCE_SHIFT) | /* VFE_SIZE */ (cs_fence << UF2_CS_FENCE_SHIFT)); /* CS_SIZE */ ADVANCE_BATCH(batch); } static void i965_avc_ildb_state_base_address(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965_h264_context->batch; if (IS_IRONLAKE(i965->intel.device_id)) { BEGIN_BATCH(batch, 8); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); ADVANCE_BATCH(batch); } else { BEGIN_BATCH(batch, 6); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); ADVANCE_BATCH(batch); } } static void i965_avc_ildb_state_pointers(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context; struct intel_batchbuffer *batch = i965_h264_context->batch; BEGIN_BATCH(batch, 3); OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1); OUT_BATCH(batch, 0); OUT_RELOC(batch, avc_ildb_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_BATCH(batch); } static void i965_avc_ildb_cs_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context; struct intel_batchbuffer *batch = i965_h264_context->batch; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, CMD_CS_URB_STATE | 0); OUT_BATCH(batch, ((avc_ildb_context->urb.size_cs_entry - 1) << 4) | /* URB Entry Allocation Size */ (avc_ildb_context->urb.num_cs_entries << 0)); /* Number of URB Entries */ ADVANCE_BATCH(batch); } static void i965_avc_ildb_constant_buffer(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context; struct intel_batchbuffer *batch = i965_h264_context->batch; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2)); OUT_RELOC(batch, avc_ildb_context->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, avc_ildb_context->urb.size_cs_entry - 1); ADVANCE_BATCH(batch); } static void i965_avc_ildb_objects(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context; struct intel_batchbuffer *batch = i965_h264_context->batch; BEGIN_BATCH(batch, 6); OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4); switch (avc_ildb_context->picture_type) { case PICTURE_FRAME: OUT_BATCH(batch, AVC_ILDB_ROOT_Y_ILDB_FRAME); break; case PICTURE_FIELD: OUT_BATCH(batch, AVC_ILDB_ROOT_Y_ILDB_FIELD); break; case PICTURE_MBAFF: OUT_BATCH(batch, AVC_ILDB_ROOT_Y_ILDB_MBAFF); break; default: assert(0); OUT_BATCH(batch, 0); break; } OUT_BATCH(batch, 0); /* no indirect data */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void i965_avc_ildb_pipeline_setup(VADriverContextP ctx, struct i965_h264_context *i965_h264_context) { struct intel_batchbuffer *batch = i965_h264_context->batch; intel_batchbuffer_emit_mi_flush(batch); i965_avc_ildb_pipeline_select(ctx, i965_h264_context); i965_avc_ildb_state_base_address(ctx, i965_h264_context); i965_avc_ildb_state_pointers(ctx, i965_h264_context); i965_avc_ildb_urb_layout(ctx, i965_h264_context); i965_avc_ildb_cs_urb_layout(ctx, i965_h264_context); i965_avc_ildb_constant_buffer(ctx, i965_h264_context); i965_avc_ildb_objects(ctx, i965_h264_context); } void i965_avc_ildb(VADriverContextP ctx, struct decode_state *decode_state, void *h264_context) { struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context; if (i965_h264_context->enable_avc_ildb) { i965_avc_ildb_states_setup(ctx, decode_state, i965_h264_context); i965_avc_ildb_pipeline_setup(ctx, i965_h264_context); } } void i965_avc_ildb_decode_init(VADriverContextP ctx, void *h264_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context; struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;; dri_bo *bo; int i; dri_bo_unreference(avc_ildb_context->curbe.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "constant buffer", 4096, 64); assert(bo); avc_ildb_context->curbe.bo = bo; dri_bo_unreference(avc_ildb_context->binding_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "binding table", NUM_AVC_ILDB_SURFACES * sizeof(unsigned int), 32); assert(bo); avc_ildb_context->binding_table.bo = bo; dri_bo_unreference(avc_ildb_context->idrt.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "interface discriptor", NUM_AVC_ILDB_INTERFACES * sizeof(struct i965_interface_descriptor), 16); assert(bo); avc_ildb_context->idrt.bo = bo; dri_bo_unreference(avc_ildb_context->vfe_state.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vfe state", sizeof(struct i965_vfe_state), 32); assert(bo); avc_ildb_context->vfe_state.bo = bo; avc_ildb_context->urb.num_vfe_entries = 1; avc_ildb_context->urb.size_vfe_entry = 640; avc_ildb_context->urb.num_cs_entries = 1; avc_ildb_context->urb.size_cs_entry = 1; avc_ildb_context->urb.vfe_start = 0; avc_ildb_context->urb.cs_start = avc_ildb_context->urb.vfe_start + avc_ildb_context->urb.num_vfe_entries * avc_ildb_context->urb.size_vfe_entry; assert(avc_ildb_context->urb.cs_start + avc_ildb_context->urb.num_cs_entries * avc_ildb_context->urb.size_cs_entry <= URB_SIZE((&i965->intel))); for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) { dri_bo_unreference(avc_ildb_context->surface[i].s_bo); avc_ildb_context->surface[i].s_bo = NULL; dri_bo_unreference(avc_ildb_context->surface[i].ss_bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state", sizeof(struct i965_surface_state), 32); assert(bo); avc_ildb_context->surface[i].ss_bo = bo; } /* kernel offset */ assert(NUM_AVC_ILDB_INTERFACES == ARRAY_ELEMS(avc_ildb_kernel_offset_gen5)); if (IS_IRONLAKE(i965->intel.device_id)) { avc_ildb_kernel_offset = avc_ildb_kernel_offset_gen5; } else { avc_ildb_kernel_offset = avc_ildb_kernel_offset_gen4; } } Bool i965_avc_ildb_ternimate(struct i965_avc_ildb_context *avc_ildb_context) { int i; dri_bo_unreference(avc_ildb_context->curbe.bo); avc_ildb_context->curbe.bo = NULL; dri_bo_unreference(avc_ildb_context->binding_table.bo); avc_ildb_context->binding_table.bo = NULL; dri_bo_unreference(avc_ildb_context->idrt.bo); avc_ildb_context->idrt.bo = NULL; dri_bo_unreference(avc_ildb_context->vfe_state.bo); avc_ildb_context->vfe_state.bo = NULL; for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) { dri_bo_unreference(avc_ildb_context->surface[i].ss_bo); avc_ildb_context->surface[i].ss_bo = NULL; dri_bo_unreference(avc_ildb_context->surface[i].s_bo); avc_ildb_context->surface[i].s_bo = NULL; } return True; } intel-driver-1.3.0/src/i965_avc_ildb.h000066400000000000000000000052531231401140700173740ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #ifndef __I965_AVC_ILDB_H__ #define __I965_AVC_ILDB_H__ #define SURFACE_EDGE_CONTROL_DATA 0 #define SURFACE_SRC_Y 1 #define SURFACE_SRC_UV 2 #define SURFACE_DEST_Y 3 #define SURFACE_DEST_UV 4 #define NUM_AVC_ILDB_SURFACES 5 #define EDGE_CONTROL_DATA_IN_DWS 16 #define EDGE_CONTROL_DATA_IN_BTYES 64 struct i965_avc_ildb_context { struct { dri_bo *bo; } curbe; struct { dri_bo *ss_bo; dri_bo *s_bo; unsigned long offset; int surface_type; int width; int height; int depth; int pitch; int format; int vert_line_stride; int vert_line_stride_ofs; int is_target; } surface[NUM_AVC_ILDB_SURFACES]; struct { dri_bo *bo; } binding_table; struct { dri_bo *bo; } idrt; struct { dri_bo *bo; } vfe_state; struct { unsigned int vfe_start; unsigned int cs_start; unsigned int num_vfe_entries; unsigned int num_cs_entries; unsigned int size_vfe_entry; unsigned int size_cs_entry; } urb; int picture_type; int mbs_per_picture; }; void i965_avc_ildb(VADriverContextP, struct decode_state *, void *h264_context); void i965_avc_ildb_decode_init(VADriverContextP, void *h264_context); Bool i965_avc_ildb_ternimate(struct i965_avc_ildb_context *); #endif /* __I965_AVC_ILDB_H__ */ intel-driver-1.3.0/src/i965_decoder.h000066400000000000000000000035431231401140700172360ustar00rootroot00000000000000/* * Copyright (C) 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef I965_DECODER_H #define I965_DECODER_H #include #include #include #include #include #define MAX_GEN_REFERENCE_FRAMES 16 typedef struct gen_frame_store GenFrameStore; struct gen_frame_store { VASurfaceID surface_id; int frame_store_id; struct object_surface *obj_surface; }; typedef struct gen_buffer GenBuffer; struct gen_buffer { dri_bo *bo; int valid; }; struct hw_context * gen75_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config); extern struct hw_context * gen8_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config); #endif /* I965_DECODER_H */ intel-driver-1.3.0/src/i965_decoder_utils.c000066400000000000000000000671571231401140700204640ustar00rootroot00000000000000/* * Copyright (C) 2006-2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "sysdeps.h" #include #include "intel_batchbuffer.h" #include "i965_drv_video.h" #include "i965_decoder_utils.h" #include "i965_defines.h" /* Set reference surface if backing store exists */ static inline int set_ref_frame( struct i965_driver_data *i965, GenFrameStore *ref_frame, VASurfaceID va_surface, struct object_surface *obj_surface ) { if (va_surface == VA_INVALID_ID) return 0; if (!obj_surface || !obj_surface->bo) return 0; ref_frame->surface_id = va_surface; ref_frame->obj_surface = obj_surface; return 1; } /* Check wether codec layer incorrectly fills in slice_vertical_position */ int mpeg2_wa_slice_vertical_position( struct decode_state *decode_state, VAPictureParameterBufferMPEG2 *pic_param ) { unsigned int i, j, mb_height, vpos, last_vpos = 0; /* Assume progressive sequence if we got a progressive frame */ if (pic_param->picture_coding_extension.bits.progressive_frame) return 0; /* Wait for a field coded picture */ if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_FRAME) return -1; assert(decode_state && decode_state->slice_params); mb_height = (pic_param->vertical_size + 31) / 32; for (j = 0; j < decode_state->num_slice_params; j++) { struct buffer_store * const buffer_store = decode_state->slice_params[j]; for (i = 0; i < buffer_store->num_elements; i++) { VASliceParameterBufferMPEG2 * const slice_param = ((VASliceParameterBufferMPEG2 *)buffer_store->buffer) + i; vpos = slice_param->slice_vertical_position; if (vpos >= mb_height || vpos == last_vpos + 2) { WARN_ONCE("codec layer incorrectly fills in MPEG-2 slice_vertical_position. Workaround applied\n"); return 1; } last_vpos = vpos; } } return 0; } /* Build MPEG-2 reference frames array */ void mpeg2_set_reference_surfaces( VADriverContextP ctx, GenFrameStore ref_frames[MAX_GEN_REFERENCE_FRAMES], struct decode_state *decode_state, VAPictureParameterBufferMPEG2 *pic_param ) { struct i965_driver_data * const i965 = i965_driver_data(ctx); VASurfaceID va_surface; unsigned pic_structure, is_second_field, n = 0; struct object_surface *obj_surface; pic_structure = pic_param->picture_coding_extension.bits.picture_structure; is_second_field = pic_structure != MPEG_FRAME && !pic_param->picture_coding_extension.bits.is_first_field; ref_frames[0].surface_id = VA_INVALID_ID; ref_frames[0].obj_surface = NULL; /* Reference frames are indexed by frame store ID (0:top, 1:bottom) */ switch (pic_param->picture_coding_type) { case MPEG_P_PICTURE: if (is_second_field && pic_structure == MPEG_BOTTOM_FIELD) { va_surface = decode_state->current_render_target; obj_surface = decode_state->render_object; n += set_ref_frame(i965, &ref_frames[n], va_surface, obj_surface); } va_surface = pic_param->forward_reference_picture; obj_surface = decode_state->reference_objects[0]; n += set_ref_frame(i965, &ref_frames[n], va_surface, obj_surface); break; case MPEG_B_PICTURE: va_surface = pic_param->forward_reference_picture; obj_surface = decode_state->reference_objects[0]; n += set_ref_frame(i965, &ref_frames[n], va_surface, obj_surface); va_surface = pic_param->backward_reference_picture; obj_surface = decode_state->reference_objects[1]; n += set_ref_frame(i965, &ref_frames[n], va_surface, obj_surface); break; } while (n != 2) { ref_frames[n].obj_surface = ref_frames[0].obj_surface; ref_frames[n++].surface_id = ref_frames[0].surface_id; } if (pic_param->picture_coding_extension.bits.progressive_frame) return; ref_frames[2].surface_id = VA_INVALID_ID; ref_frames[2].obj_surface = NULL; /* Bottom field pictures used as reference */ switch (pic_param->picture_coding_type) { case MPEG_P_PICTURE: if (is_second_field && pic_structure == MPEG_TOP_FIELD) { va_surface = decode_state->current_render_target; obj_surface = decode_state->render_object; n += set_ref_frame(i965, &ref_frames[n], va_surface, obj_surface); } va_surface = pic_param->forward_reference_picture; obj_surface = decode_state->reference_objects[0]; n += set_ref_frame(i965, &ref_frames[n], va_surface, obj_surface); break; case MPEG_B_PICTURE: va_surface = pic_param->forward_reference_picture; obj_surface = decode_state->reference_objects[0]; n += set_ref_frame(i965, &ref_frames[n], va_surface, obj_surface); va_surface = pic_param->backward_reference_picture; obj_surface = decode_state->reference_objects[1]; n += set_ref_frame(i965, &ref_frames[n], va_surface, obj_surface); break; } while (n != 4) { ref_frames[n].obj_surface = ref_frames[2].obj_surface; ref_frames[n++].surface_id = ref_frames[2].surface_id; } } /* Generate flat scaling matrices for H.264 decoding */ void avc_gen_default_iq_matrix(VAIQMatrixBufferH264 *iq_matrix) { /* Flat_4x4_16 */ memset(&iq_matrix->ScalingList4x4, 16, sizeof(iq_matrix->ScalingList4x4)); /* Flat_8x8_16 */ memset(&iq_matrix->ScalingList8x8, 16, sizeof(iq_matrix->ScalingList8x8)); } /* Get first macroblock bit offset for BSD, minus EPB count (AVC) */ /* XXX: slice_data_bit_offset does not account for EPB */ unsigned int avc_get_first_mb_bit_offset( dri_bo *slice_data_bo, VASliceParameterBufferH264 *slice_param, unsigned int mode_flag ) { unsigned int slice_data_bit_offset = slice_param->slice_data_bit_offset; if (mode_flag == ENTROPY_CABAC) slice_data_bit_offset = ALIGN(slice_data_bit_offset, 0x8); return slice_data_bit_offset; } /* Get first macroblock bit offset for BSD, with EPB count (AVC) */ /* XXX: slice_data_bit_offset does not account for EPB */ unsigned int avc_get_first_mb_bit_offset_with_epb( dri_bo *slice_data_bo, VASliceParameterBufferH264 *slice_param, unsigned int mode_flag ) { unsigned int in_slice_data_bit_offset = slice_param->slice_data_bit_offset; unsigned int out_slice_data_bit_offset; unsigned int i, j, n, buf_size, data_size, header_size; uint8_t *buf; int ret; header_size = slice_param->slice_data_bit_offset / 8; data_size = slice_param->slice_data_size - slice_param->slice_data_offset; buf_size = (header_size * 3 + 1) / 2; // Max possible header size (x1.5) if (buf_size > data_size) buf_size = data_size; buf = alloca(buf_size); ret = dri_bo_get_subdata( slice_data_bo, slice_param->slice_data_offset, buf_size, buf ); assert(ret == 0); for (i = 2, j = 2, n = 0; i < buf_size && j < header_size; i++, j++) { if (buf[i] == 0x03 && buf[i - 1] == 0x00 && buf[i - 2] == 0x00) i += 2, j++, n++; } out_slice_data_bit_offset = in_slice_data_bit_offset + n * 8; if (mode_flag == ENTROPY_CABAC) out_slice_data_bit_offset = ALIGN(out_slice_data_bit_offset, 0x8); return out_slice_data_bit_offset; } static inline uint8_t get_ref_idx_state_1(const VAPictureH264 *va_pic, unsigned int frame_store_id) { const unsigned int is_long_term = !!(va_pic->flags & VA_PICTURE_H264_LONG_TERM_REFERENCE); const unsigned int is_top_field = !!(va_pic->flags & VA_PICTURE_H264_TOP_FIELD); const unsigned int is_bottom_field = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD); return ((is_long_term << 6) | ((is_top_field ^ is_bottom_field ^ 1) << 5) | (frame_store_id << 1) | ((is_top_field ^ 1) & is_bottom_field)); } /* Fill in Reference List Entries (Gen5+: ILK, SNB, IVB) */ void gen5_fill_avc_ref_idx_state( uint8_t state[32], const VAPictureH264 ref_list[32], unsigned int ref_list_count, const GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES] ) { unsigned int i, n, frame_idx; int found; for (i = 0, n = 0; i < ref_list_count; i++) { const VAPictureH264 * const va_pic = &ref_list[i]; if (va_pic->flags & VA_PICTURE_H264_INVALID) continue; found = 0; for (frame_idx = 0; frame_idx < MAX_GEN_REFERENCE_FRAMES; frame_idx++) { const GenFrameStore * const fs = &frame_store[frame_idx]; if (fs->surface_id != VA_INVALID_ID && fs->surface_id == va_pic->picture_id) { found = 1; break; } } if (found) { state[n++] = get_ref_idx_state_1(va_pic, frame_idx); } else { WARN_ONCE("Invalid Slice reference frame list !!!. It is not included in DPB \n"); } } for (; n < 32; n++) state[n] = 0xff; } /* Emit Reference List Entries (Gen6+: SNB, IVB) */ static void gen6_send_avc_ref_idx_state_1( struct intel_batchbuffer *batch, unsigned int list, const VAPictureH264 *ref_list, unsigned int ref_list_count, const GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES] ) { uint8_t ref_idx_state[32]; BEGIN_BCS_BATCH(batch, 10); OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | (10 - 2)); OUT_BCS_BATCH(batch, list); gen5_fill_avc_ref_idx_state( ref_idx_state, ref_list, ref_list_count, frame_store ); intel_batchbuffer_data(batch, ref_idx_state, sizeof(ref_idx_state)); ADVANCE_BCS_BATCH(batch); } void gen6_send_avc_ref_idx_state( struct intel_batchbuffer *batch, const VASliceParameterBufferH264 *slice_param, const GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES] ) { if (slice_param->slice_type == SLICE_TYPE_I || slice_param->slice_type == SLICE_TYPE_SI) return; /* RefPicList0 */ gen6_send_avc_ref_idx_state_1( batch, 0, slice_param->RefPicList0, slice_param->num_ref_idx_l0_active_minus1 + 1, frame_store ); if (slice_param->slice_type != SLICE_TYPE_B) return; /* RefPicList1 */ gen6_send_avc_ref_idx_state_1( batch, 1, slice_param->RefPicList1, slice_param->num_ref_idx_l1_active_minus1 + 1, frame_store ); } void intel_update_avc_frame_store_index(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferH264 *pic_param, GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES]) { int i, j; assert(MAX_GEN_REFERENCE_FRAMES == ARRAY_ELEMS(pic_param->ReferenceFrames)); for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { int found = 0; if (frame_store[i].surface_id == VA_INVALID_ID || frame_store[i].obj_surface == NULL) continue; assert(frame_store[i].frame_store_id != -1); for (j = 0; j < MAX_GEN_REFERENCE_FRAMES; j++) { VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[j]; if (ref_pic->flags & VA_PICTURE_H264_INVALID) continue; if (frame_store[i].surface_id == ref_pic->picture_id) { found = 1; break; } } /* remove it from the internal DPB */ if (!found) { struct object_surface *obj_surface = frame_store[i].obj_surface; obj_surface->flags &= ~SURFACE_REFERENCED; if ((obj_surface->flags & SURFACE_ALL_MASK) == SURFACE_DISPLAYED) { dri_bo_unreference(obj_surface->bo); obj_surface->bo = NULL; obj_surface->flags &= ~SURFACE_REF_DIS_MASK; } if (obj_surface->free_private_data) obj_surface->free_private_data(&obj_surface->private_data); frame_store[i].surface_id = VA_INVALID_ID; frame_store[i].frame_store_id = -1; frame_store[i].obj_surface = NULL; } } for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) { VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[i]; int found = 0; if (ref_pic->flags & VA_PICTURE_H264_INVALID || ref_pic->picture_id == VA_INVALID_SURFACE || decode_state->reference_objects[i] == NULL) continue; for (j = 0; j < MAX_GEN_REFERENCE_FRAMES; j++) { if (frame_store[j].surface_id == ref_pic->picture_id) { found = 1; break; } } /* add the new reference frame into the internal DPB */ if (!found) { int frame_idx; int slot_found; struct object_surface *obj_surface = decode_state->reference_objects[i]; /* * Sometimes a dummy frame comes from the upper layer library, call i965_check_alloc_surface_bo() * to ake sure the store buffer is allocated for this reference frame */ i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420); slot_found = 0; frame_idx = -1; /* Find a free frame store index */ for (j = 0; j < MAX_GEN_REFERENCE_FRAMES; j++) { if (frame_store[j].surface_id == VA_INVALID_ID || frame_store[j].obj_surface == NULL) { frame_idx = j; slot_found = 1; break; } } if (slot_found) { frame_store[j].surface_id = ref_pic->picture_id; frame_store[j].frame_store_id = frame_idx; frame_store[j].obj_surface = obj_surface; } else { WARN_ONCE("Not free slot for DPB reference list!!!\n"); } } } } void intel_update_vc1_frame_store_index(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferVC1 *pic_param, GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES]) { struct object_surface *obj_surface; int i; obj_surface = decode_state->reference_objects[0]; if (pic_param->forward_reference_picture == VA_INVALID_ID || !obj_surface || !obj_surface->bo) { frame_store[0].surface_id = VA_INVALID_ID; frame_store[0].obj_surface = NULL; } else { frame_store[0].surface_id = pic_param->forward_reference_picture; frame_store[0].obj_surface = obj_surface; } obj_surface = decode_state->reference_objects[1]; if (pic_param->backward_reference_picture == VA_INVALID_ID || !obj_surface || !obj_surface->bo) { frame_store[1].surface_id = frame_store[0].surface_id; frame_store[1].obj_surface = frame_store[0].obj_surface; } else { frame_store[1].surface_id = pic_param->backward_reference_picture; frame_store[1].obj_surface = obj_surface; } for (i = 2; i < MAX_GEN_REFERENCE_FRAMES; i++) { frame_store[i].surface_id = frame_store[i % 2].surface_id; frame_store[i].obj_surface = frame_store[i % 2].obj_surface; } } void intel_update_vp8_frame_store_index(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferVP8 *pic_param, GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES]) { struct object_surface *obj_surface; int i; obj_surface = decode_state->reference_objects[0]; if (pic_param->last_ref_frame == VA_INVALID_ID || !obj_surface || !obj_surface->bo) { frame_store[0].surface_id = VA_INVALID_ID; frame_store[0].obj_surface = NULL; } else { frame_store[0].surface_id = pic_param->last_ref_frame; frame_store[0].obj_surface = obj_surface; } obj_surface = decode_state->reference_objects[1]; if (pic_param->golden_ref_frame == VA_INVALID_ID || !obj_surface || !obj_surface->bo) { frame_store[1].surface_id = frame_store[0].surface_id; frame_store[1].obj_surface = frame_store[0].obj_surface; } else { frame_store[1].surface_id = pic_param->golden_ref_frame; frame_store[1].obj_surface = obj_surface; } obj_surface = decode_state->reference_objects[2]; if (pic_param->alt_ref_frame == VA_INVALID_ID || !obj_surface || !obj_surface->bo) { frame_store[2].surface_id = frame_store[0].surface_id; frame_store[2].obj_surface = frame_store[0].obj_surface; } else { frame_store[2].surface_id = pic_param->alt_ref_frame; frame_store[2].obj_surface = obj_surface; } for (i = 3; i < MAX_GEN_REFERENCE_FRAMES; i++) { frame_store[i].surface_id = frame_store[i % 2].surface_id; frame_store[i].obj_surface = frame_store[i % 2].obj_surface; } } static VAStatus intel_decoder_check_avc_parameter(VADriverContextP ctx, VAProfile h264_profile, struct decode_state *decode_state) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAPictureParameterBufferH264 *pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; struct object_surface *obj_surface; int i; assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID)); assert(pic_param->CurrPic.picture_id != VA_INVALID_SURFACE); if (pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID || pic_param->CurrPic.picture_id == VA_INVALID_SURFACE) goto error; assert(pic_param->CurrPic.picture_id == decode_state->current_render_target); if (pic_param->CurrPic.picture_id != decode_state->current_render_target) goto error; if ((h264_profile != VAProfileH264Baseline)) { if (pic_param->num_slice_groups_minus1 || pic_param->pic_fields.bits.redundant_pic_cnt_present_flag) { WARN_ONCE("Unsupported the FMO/ASO constraints!!!\n"); goto error; } } for (i = 0; i < 16; i++) { if (pic_param->ReferenceFrames[i].flags & VA_PICTURE_H264_INVALID || pic_param->ReferenceFrames[i].picture_id == VA_INVALID_SURFACE) break; else { obj_surface = SURFACE(pic_param->ReferenceFrames[i].picture_id); assert(obj_surface); if (!obj_surface) goto error; if (!obj_surface->bo) { /* a reference frame without store buffer */ WARN_ONCE("Invalid reference frame!!!\n"); } decode_state->reference_objects[i] = obj_surface; } } for ( ; i < 16; i++) decode_state->reference_objects[i] = NULL; return VA_STATUS_SUCCESS; error: return VA_STATUS_ERROR_INVALID_PARAMETER; } static VAStatus intel_decoder_check_mpeg2_parameter(VADriverContextP ctx, struct decode_state *decode_state) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAPictureParameterBufferMPEG2 *pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; struct object_surface *obj_surface; int i = 0; if (pic_param->picture_coding_type == MPEG_I_PICTURE) { } else if (pic_param->picture_coding_type == MPEG_P_PICTURE) { obj_surface = SURFACE(pic_param->forward_reference_picture); if (!obj_surface || !obj_surface->bo) decode_state->reference_objects[i++] = NULL; else decode_state->reference_objects[i++] = obj_surface; } else if (pic_param->picture_coding_type == MPEG_B_PICTURE) { obj_surface = SURFACE(pic_param->forward_reference_picture); if (!obj_surface || !obj_surface->bo) decode_state->reference_objects[i++] = NULL; else decode_state->reference_objects[i++] = obj_surface; obj_surface = SURFACE(pic_param->backward_reference_picture); if (!obj_surface || !obj_surface->bo) decode_state->reference_objects[i++] = NULL; else decode_state->reference_objects[i++] = obj_surface; } else goto error; for ( ; i < 16; i++) decode_state->reference_objects[i] = NULL; return VA_STATUS_SUCCESS; error: return VA_STATUS_ERROR_INVALID_PARAMETER; } static VAStatus intel_decoder_check_vc1_parameter(VADriverContextP ctx, struct decode_state *decode_state) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAPictureParameterBufferVC1 *pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; struct object_surface *obj_surface; int i = 0; if (pic_param->picture_fields.bits.picture_type == 0 || pic_param->picture_fields.bits.picture_type == 3) { } else if (pic_param->picture_fields.bits.picture_type == 1 || pic_param->picture_fields.bits.picture_type == 4) { obj_surface = SURFACE(pic_param->forward_reference_picture); if (!obj_surface || !obj_surface->bo) decode_state->reference_objects[i++] = NULL; else decode_state->reference_objects[i++] = obj_surface; } else if (pic_param->picture_fields.bits.picture_type == 2) { obj_surface = SURFACE(pic_param->forward_reference_picture); if (!obj_surface || !obj_surface->bo) decode_state->reference_objects[i++] = NULL; else decode_state->reference_objects[i++] = obj_surface; obj_surface = SURFACE(pic_param->backward_reference_picture); if (!obj_surface || !obj_surface->bo) decode_state->reference_objects[i++] = NULL; else decode_state->reference_objects[i++] = obj_surface; } else goto error; for ( ; i < 16; i++) decode_state->reference_objects[i] = NULL; return VA_STATUS_SUCCESS; error: return VA_STATUS_ERROR_INVALID_PARAMETER; } static VAStatus intel_decoder_check_vp8_parameter(VADriverContextP ctx, struct decode_state *decode_state) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAPictureParameterBufferVP8 *pic_param = (VAPictureParameterBufferVP8 *)decode_state->pic_param->buffer; struct object_surface *obj_surface; int i = 0; if (pic_param->last_ref_frame != VA_INVALID_SURFACE) { obj_surface = SURFACE(pic_param->last_ref_frame); if (obj_surface && obj_surface->bo) decode_state->reference_objects[i++] = obj_surface; else decode_state->reference_objects[i++] = NULL; } if (pic_param->golden_ref_frame != VA_INVALID_SURFACE) { obj_surface = SURFACE(pic_param->golden_ref_frame); if (obj_surface && obj_surface->bo) decode_state->reference_objects[i++] = obj_surface; else decode_state->reference_objects[i++] = NULL; } if (pic_param->alt_ref_frame != VA_INVALID_SURFACE) { obj_surface = SURFACE(pic_param->alt_ref_frame); if (obj_surface && obj_surface->bo) decode_state->reference_objects[i++] = obj_surface; else decode_state->reference_objects[i++] = NULL; } for ( ; i < 16; i++) decode_state->reference_objects[i] = NULL; return VA_STATUS_SUCCESS; } VAStatus intel_decoder_sanity_check_input(VADriverContextP ctx, VAProfile profile, struct decode_state *decode_state) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; VAStatus vaStatus = VA_STATUS_ERROR_INVALID_PARAMETER; if (decode_state->current_render_target == VA_INVALID_SURFACE) goto out; obj_surface = SURFACE(decode_state->current_render_target); if (!obj_surface) goto out; decode_state->render_object = obj_surface; switch (profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: vaStatus = intel_decoder_check_mpeg2_parameter(ctx, decode_state); break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: vaStatus = intel_decoder_check_avc_parameter(ctx, profile, decode_state); break; case VAProfileVC1Simple: case VAProfileVC1Main: case VAProfileVC1Advanced: vaStatus = intel_decoder_check_vc1_parameter(ctx, decode_state); break; case VAProfileJPEGBaseline: vaStatus = VA_STATUS_SUCCESS; break; case VAProfileVP8Version0_3: vaStatus = intel_decoder_check_vp8_parameter(ctx, decode_state); break; default: vaStatus = VA_STATUS_ERROR_INVALID_PARAMETER; break; } out: return vaStatus; } /* * Return the next slice paramter * * Input: * slice_param: the current slice * *group_idx & *element_idx the current slice position in slice groups * Output: * Return the next slice parameter * *group_idx & *element_idx the next slice position in slice groups, * if the next slice is NULL, *group_idx & *element_idx will be ignored */ VASliceParameterBufferMPEG2 * intel_mpeg2_find_next_slice(struct decode_state *decode_state, VAPictureParameterBufferMPEG2 *pic_param, VASliceParameterBufferMPEG2 *slice_param, int *group_idx, int *element_idx) { VASliceParameterBufferMPEG2 *next_slice_param; unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16; int j = *group_idx, i = *element_idx + 1; for (; j < decode_state->num_slice_params; j++) { for (; i < decode_state->slice_params[j]->num_elements; i++) { next_slice_param = ((VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer) + i; if ((next_slice_param->slice_vertical_position * width_in_mbs + next_slice_param->slice_horizontal_position) >= (slice_param->slice_vertical_position * width_in_mbs + slice_param->slice_horizontal_position)) { *group_idx = j; *element_idx = i; return next_slice_param; } } i = 0; } return NULL; } intel-driver-1.3.0/src/i965_decoder_utils.h000066400000000000000000000076141231401140700204610ustar00rootroot00000000000000/* * Copyright (C) 2006-2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef I965_DECODER_UTILS_H #define I965_DECODER_UTILS_H #include "i965_decoder.h" #include "intel_batchbuffer.h" struct decode_state; int mpeg2_wa_slice_vertical_position( struct decode_state *decode_state, VAPictureParameterBufferMPEG2 *pic_param ); void mpeg2_set_reference_surfaces( VADriverContextP ctx, GenFrameStore ref_frames[MAX_GEN_REFERENCE_FRAMES], struct decode_state *decode_state, VAPictureParameterBufferMPEG2 *pic_param ); void avc_gen_default_iq_matrix(VAIQMatrixBufferH264 *iq_matrix); unsigned int avc_get_first_mb_bit_offset( dri_bo *slice_data_bo, VASliceParameterBufferH264 *slice_param, unsigned int mode_flag ); unsigned int avc_get_first_mb_bit_offset_with_epb( dri_bo *slice_data_bo, VASliceParameterBufferH264 *slice_param, unsigned int mode_flag ); void gen5_fill_avc_ref_idx_state( uint8_t state[32], const VAPictureH264 ref_list[32], unsigned int ref_list_count, const GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES] ); void gen6_send_avc_ref_idx_state( struct intel_batchbuffer *batch, const VASliceParameterBufferH264 *slice_param, const GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES] ); VAStatus intel_decoder_sanity_check_input(VADriverContextP ctx, VAProfile profile, struct decode_state *decode_state); void intel_update_avc_frame_store_index(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferH264 *pic_param, GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES]); void intel_update_vc1_frame_store_index(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferVC1 *pic_param, GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES]); VASliceParameterBufferMPEG2 * intel_mpeg2_find_next_slice(struct decode_state *decode_state, VAPictureParameterBufferMPEG2 *pic_param, VASliceParameterBufferMPEG2 *slice_param, int *group_idx, int *element_idx); void intel_update_vp8_frame_store_index(VADriverContextP ctx, struct decode_state *decode_state, VAPictureParameterBufferVP8 *pic_param, GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES]); #endif /* I965_DECODER_UTILS_H */ intel-driver-1.3.0/src/i965_defines.h000077500000000000000000001133551231401140700172540ustar00rootroot00000000000000#ifndef _I965_DEFINES_H_ #define _I965_DEFINES_H_ #define CMD(pipeline,op,sub_op) ((3 << 29) | \ ((pipeline) << 27) | \ ((op) << 24) | \ ((sub_op) << 16)) #define CMD_URB_FENCE CMD(0, 0, 0) #define CMD_CS_URB_STATE CMD(0, 0, 1) #define CMD_CONSTANT_BUFFER CMD(0, 0, 2) #define CMD_STATE_PREFETCH CMD(0, 0, 3) #define CMD_STATE_BASE_ADDRESS CMD(0, 1, 1) #define CMD_STATE_SIP CMD(0, 1, 2) #define CMD_PIPELINE_SELECT CMD(1, 1, 4) #define CMD_SAMPLER_PALETTE_LOAD CMD(3, 1, 2) #define CMD_MEDIA_STATE_POINTERS CMD(2, 0, 0) #define CMD_MEDIA_VFE_STATE CMD(2, 0, 0) #define CMD_MEDIA_CURBE_LOAD CMD(2, 0, 1) #define CMD_MEDIA_INTERFACE_LOAD CMD(2, 0, 2) #define CMD_MEDIA_OBJECT CMD(2, 1, 0) #define CMD_MEDIA_OBJECT_EX CMD(2, 1, 1) #define CMD_AVC_BSD_IMG_STATE CMD(2, 4, 0) #define CMD_AVC_BSD_QM_STATE CMD(2, 4, 1) #define CMD_AVC_BSD_SLICE_STATE CMD(2, 4, 2) #define CMD_AVC_BSD_BUF_BASE_STATE CMD(2, 4, 3) #define CMD_BSD_IND_OBJ_BASE_ADDR CMD(2, 4, 4) #define CMD_AVC_BSD_OBJECT CMD(2, 4, 8) #define CMD_MEDIA_VFE_STATE CMD(2, 0, 0) #define CMD_MEDIA_CURBE_LOAD CMD(2, 0, 1) #define CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD CMD(2, 0, 2) #define CMD_MEDIA_GATEWAY_STATE CMD(2, 0, 3) #define CMD_MEDIA_STATE_FLUSH CMD(2, 0, 4) #define CMD_MEDIA_OBJECT_WALKER CMD(2, 1, 3) #define CMD_PIPELINED_POINTERS CMD(3, 0, 0) #define CMD_BINDING_TABLE_POINTERS CMD(3, 0, 1) # define GEN6_BINDING_TABLE_MODIFY_PS (1 << 12)/* for GEN6 */ # define GEN6_BINDING_TABLE_MODIFY_GS (1 << 9) /* for GEN6 */ # define GEN6_BINDING_TABLE_MODIFY_VS (1 << 8) /* for GEN6 */ #define CMD_VERTEX_BUFFERS CMD(3, 0, 8) #define CMD_VERTEX_ELEMENTS CMD(3, 0, 9) #define CMD_DRAWING_RECTANGLE CMD(3, 1, 0) #define CMD_CONSTANT_COLOR CMD(3, 1, 1) #define CMD_3DPRIMITIVE CMD(3, 3, 0) #define CMD_DEPTH_BUFFER CMD(3, 1, 5) # define CMD_DEPTH_BUFFER_TYPE_SHIFT 29 # define CMD_DEPTH_BUFFER_FORMAT_SHIFT 18 #define CMD_CLEAR_PARAMS CMD(3, 1, 0x10) /* DW1 */ # define CMD_CLEAR_PARAMS_DEPTH_CLEAR_VALID (1 << 15) /* for GEN6+ */ #define GEN6_3DSTATE_SAMPLER_STATE_POINTERS CMD(3, 0, 0x02) # define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS (1 << 12) # define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_GS (1 << 9) # define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_VS (1 << 8) #define GEN6_3DSTATE_URB CMD(3, 0, 0x05) /* DW1 */ # define GEN6_3DSTATE_URB_VS_SIZE_SHIFT 16 # define GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT 0 /* DW2 */ # define GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT 8 # define GEN6_3DSTATE_URB_GS_SIZE_SHIFT 0 #define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS CMD(3, 0, 0x0d) # define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC (1 << 12) # define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_SF (1 << 11) # define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CLIP (1 << 10) #define GEN6_3DSTATE_CC_STATE_POINTERS CMD(3, 0, 0x0e) #define GEN6_3DSTATE_VS CMD(3, 0, 0x10) #define GEN6_3DSTATE_GS CMD(3, 0, 0x11) /* DW4 */ # define GEN6_3DSTATE_GS_DISPATCH_START_GRF_SHIFT 0 #define GEN6_3DSTATE_CLIP CMD(3, 0, 0x12) #define GEN6_3DSTATE_SF CMD(3, 0, 0x13) /* DW1 on GEN6 */ # define GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT 22 # define GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT 11 # define GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT 4 /* DW1 on GEN7 */ # define GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT 12 /* DW2 */ /* DW3 */ # define GEN6_3DSTATE_SF_CULL_BOTH (0 << 29) # define GEN6_3DSTATE_SF_CULL_NONE (1 << 29) # define GEN6_3DSTATE_SF_CULL_FRONT (2 << 29) # define GEN6_3DSTATE_SF_CULL_BACK (3 << 29) /* DW4 */ # define GEN6_3DSTATE_SF_TRI_PROVOKE_SHIFT 29 # define GEN6_3DSTATE_SF_LINE_PROVOKE_SHIFT 27 # define GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT 25 #define GEN8_3DSTATE_RASTER CMD(3, 0, 0x50) # define GEN8_3DSTATE_RASTER_CULL_BOTH (0 << 16) # define GEN8_3DSTATE_RASTER_CULL_NONE (1 << 16) # define GEN8_3DSTATE_RASTER_CULL_FRONT (2 << 16) # define GEN8_3DSTATE_RASTER_CULL_BACK (3 << 16) #define GEN6_3DSTATE_WM CMD(3, 0, 0x14) /* DW2 */ # define GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF 27 # define GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 /* DW4 */ # define GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT 16 /* DW5 */ # define GEN6_3DSTATE_WM_MAX_THREADS_SHIFT 25 # define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) # define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) # define GEN6_3DSTATE_WM_8_DISPATCH_ENABLE (1 << 0) /* DW6 */ # define GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT 20 # define GEN6_3DSTATE_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 15) # define GEN6_3DSTATE_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 14) # define GEN6_3DSTATE_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 13) # define GEN6_3DSTATE_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 12) # define GEN6_3DSTATE_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11) # define GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10) /* 3DSTATE_WM on GEN7 */ /* DW1 */ # define GEN7_WM_STATISTICS_ENABLE (1 << 31) # define GEN7_WM_DEPTH_CLEAR (1 << 30) # define GEN7_WM_DISPATCH_ENABLE (1 << 29) # define GEN6_WM_DEPTH_RESOLVE (1 << 28) # define GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27) # define GEN7_WM_KILL_ENABLE (1 << 25) # define GEN7_WM_PSCDEPTH_OFF (0 << 23) # define GEN7_WM_PSCDEPTH_ON (1 << 23) # define GEN7_WM_PSCDEPTH_ON_GE (2 << 23) # define GEN7_WM_PSCDEPTH_ON_LE (3 << 23) # define GEN7_WM_USES_SOURCE_DEPTH (1 << 20) # define GEN7_WM_USES_SOURCE_W (1 << 19) # define GEN7_WM_POSITION_ZW_PIXEL (0 << 17) # define GEN7_WM_POSITION_ZW_CENTROID (2 << 17) # define GEN7_WM_POSITION_ZW_SAMPLE (3 << 17) # define GEN7_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 16) # define GEN7_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 15) # define GEN7_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 14) # define GEN7_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 13) # define GEN7_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 12) # define GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 11) # define GEN7_WM_USES_INPUT_COVERAGE_MASK (1 << 10) # define GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 8) # define GEN7_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 8) # define GEN7_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 8) # define GEN7_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 8) # define GEN7_WM_LINE_AA_WIDTH_0_5 (0 << 6) # define GEN7_WM_LINE_AA_WIDTH_1_0 (1 << 6) # define GEN7_WM_LINE_AA_WIDTH_2_0 (2 << 6) # define GEN7_WM_LINE_AA_WIDTH_4_0 (3 << 6) # define GEN7_WM_POLYGON_STIPPLE_ENABLE (1 << 4) # define GEN7_WM_LINE_STIPPLE_ENABLE (1 << 3) # define GEN7_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 2) # define GEN7_WM_MSRAST_OFF_PIXEL (0 << 0) # define GEN7_WM_MSRAST_OFF_PATTERN (1 << 0) # define GEN7_WM_MSRAST_ON_PIXEL (2 << 0) # define GEN7_WM_MSRAST_ON_PATTERN (3 << 0) /* DW2 */ # define GEN7_WM_MSDISPMODE_PERPIXEL (1 << 31) #define GEN6_3DSTATE_CONSTANT_VS CMD(3, 0, 0x15) #define GEN6_3DSTATE_CONSTANT_GS CMD(3, 0, 0x16) #define GEN6_3DSTATE_CONSTANT_PS CMD(3, 0, 0x17) /* Gen8 WM_HZ_OP */ #define GEN8_3DSTATE_WM_HZ_OP CMD(3, 0, 0x52) # define GEN6_3DSTATE_CONSTANT_BUFFER_3_ENABLE (1 << 15) # define GEN6_3DSTATE_CONSTANT_BUFFER_2_ENABLE (1 << 14) # define GEN6_3DSTATE_CONSTANT_BUFFER_1_ENABLE (1 << 13) # define GEN6_3DSTATE_CONSTANT_BUFFER_0_ENABLE (1 << 12) #define GEN6_3DSTATE_SAMPLE_MASK CMD(3, 0, 0x18) #define GEN6_3DSTATE_MULTISAMPLE CMD(3, 1, 0x0d) /* DW1 */ # define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER (0 << 4) # define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_UPPER_LEFT (1 << 4) # define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1 (0 << 1) # define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_4 (2 << 1) # define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_8 (3 << 1) #define GEN8_3DSTATE_MULTISAMPLE CMD(3, 0, 0x0d) #define GEN8_3DSTATE_SAMPLE_PATTERN CMD(3, 1, 0x1C) /* GEN7 */ #define GEN7_3DSTATE_CLEAR_PARAMS CMD(3, 0, 0x04) #define GEN7_3DSTATE_DEPTH_BUFFER CMD(3, 0, 0x05) #define GEN7_3DSTATE_HIER_DEPTH_BUFFER CMD(3, 0, 0x07) #define GEN7_3DSTATE_URB_VS CMD(3, 0, 0x30) #define GEN7_3DSTATE_URB_HS CMD(3, 0, 0x31) #define GEN7_3DSTATE_URB_DS CMD(3, 0, 0x32) #define GEN7_3DSTATE_URB_GS CMD(3, 0, 0x33) /* DW1 */ # define GEN7_URB_ENTRY_NUMBER_SHIFT 0 # define GEN7_URB_ENTRY_SIZE_SHIFT 16 # define GEN7_URB_STARTING_ADDRESS_SHIFT 25 #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS CMD(3, 1, 0x12) #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS CMD(3, 1, 0x16) #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS CMD(3, 1, 0x14) #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS CMD(3, 1, 0x13) #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS CMD(3, 1, 0x15) /* DW1 */ # define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16 # define GEN8_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16 # define GEN8_PUSH_CONSTANT_BUFFER_SIZE_SHIFT 0 #define GEN7_3DSTATE_CONSTANT_HS CMD(3, 0, 0x19) #define GEN7_3DSTATE_CONSTANT_DS CMD(3, 0, 0x1a) #define GEN7_3DSTATE_HS CMD(3, 0, 0x1b) #define GEN7_3DSTATE_TE CMD(3, 0, 0x1c) #define GEN7_3DSTATE_DS CMD(3, 0, 0x1d) #define GEN7_3DSTATE_STREAMOUT CMD(3, 0, 0x1e) #define GEN7_3DSTATE_SBE CMD(3, 0, 0x1f) /* DW1 */ # define GEN7_SBE_SWIZZLE_CONTROL_MODE (1 << 28) # define GEN7_SBE_NUM_OUTPUTS_SHIFT 22 # define GEN7_SBE_SWIZZLE_ENABLE (1 << 21) # define GEN7_SBE_POINT_SPRITE_LOWERLEFT (1 << 20) # define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT 11 # define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT 4 # define GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH (1 << 29) # define GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET (1 << 28) # define GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT 5 #define GEN8_3DSTATE_SBE_SWIZ CMD(3, 0, 0x51) #define GEN7_3DSTATE_PS CMD(3, 0, 0x20) /* DW1: kernel pointer */ /* DW2 */ # define GEN7_PS_SPF_MODE (1 << 31) # define GEN7_PS_VECTOR_MASK_ENABLE (1 << 30) # define GEN7_PS_SAMPLER_COUNT_SHIFT 27 # define GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 # define GEN7_PS_FLOATING_POINT_MODE_IEEE_754 (0 << 16) # define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16) /* DW3: scratch space */ /* DW4 */ # define GEN7_PS_MAX_THREADS_SHIFT_IVB 24 # define GEN7_PS_MAX_THREADS_SHIFT_HSW 23 # define GEN7_PS_SAMPLE_MASK_SHIFT_HSW 12 # define GEN7_PS_PUSH_CONSTANT_ENABLE (1 << 11) # define GEN7_PS_ATTRIBUTE_ENABLE (1 << 10) # define GEN7_PS_OMASK_TO_RENDER_TARGET (1 << 9) # define GEN7_PS_DUAL_SOURCE_BLEND_ENABLE (1 << 7) # define GEN7_PS_POSOFFSET_NONE (0 << 3) # define GEN7_PS_POSOFFSET_CENTROID (2 << 3) # define GEN7_PS_POSOFFSET_SAMPLE (3 << 3) # define GEN7_PS_32_DISPATCH_ENABLE (1 << 2) # define GEN7_PS_16_DISPATCH_ENABLE (1 << 1) # define GEN7_PS_8_DISPATCH_ENABLE (1 << 0) /* DW5 */ # define GEN7_PS_DISPATCH_START_GRF_SHIFT_0 16 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_1 8 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_2 0 /* DW6: kernel 1 pointer */ /* DW7: kernel 2 pointer */ # define GEN8_PS_MAX_THREADS_SHIFT 23 #define GEN8_3DSTATE_PSEXTRA CMD(3, 0, 0x4f) /* DW1 */ # define GEN8_PSX_PIXEL_SHADER_VALID (1 << 31) # define GEN8_PSX_PSCDEPTH_OFF (0 << 26) # define GEN8_PSX_PSCDEPTH_ON (1 << 26) # define GEN8_PSX_PSCDEPTH_ON_GE (2 << 26) # define GEN8_PSX_PSCDEPTH_ON_LE (3 << 26) # define GEN8_PSX_ATTRIBUTE_ENABLE (1 << 8) #define GEN8_3DSTATE_PSBLEND CMD(3, 0, 0x4d) /* DW1 */ # define GEN8_PS_BLEND_ALPHA_TO_COVERAGE_ENABLE (1 << 31) # define GEN8_PS_BLEND_HAS_WRITEABLE_RT (1 << 30) # define GEN8_PS_BLEND_COLOR_BUFFER_BLEND_ENABLE (1 << 29) # define GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_MASK INTEL_MASK(28, 24) # define GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT 24 # define GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_MASK INTEL_MASK(23, 19) # define GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT 19 # define GEN8_PS_BLEND_SRC_BLEND_FACTOR_MASK INTEL_MASK(18, 14) # define GEN8_PS_BLEND_SRC_BLEND_FACTOR_SHIFT 14 # define GEN8_PS_BLEND_DST_BLEND_FACTOR_MASK INTEL_MASK(13, 9) # define GEN8_PS_BLEND_DST_BLEND_FACTOR_SHIFT 9 # define GEN8_PS_BLEND_ALPHA_TEST_ENABLE (1 << 8) # define GEN8_PS_BLEND_INDEPENDENT_ALPHA_BLEND_ENABLE (1 << 7) #define GEN7_3DSTATE_STENCIL_BUFFER CMD(3, 0, 0x06) #define GEN8_3DSTATE_WM_DEPTH_STENCIL CMD(3, 0, 0x4e) #define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL CMD(3, 0, 0x21) #define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC CMD(3, 0, 0x23) #define GEN7_3DSTATE_BLEND_STATE_POINTERS CMD(3, 0, 0x24) #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS CMD(3, 0, 0x25) #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS CMD(3, 0, 0x26) #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS CMD(3, 0, 0x27) #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS CMD(3, 0, 0x28) #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS CMD(3, 0, 0x29) #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS CMD(3, 0, 0x2a) #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS CMD(3, 0, 0x2b) #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS CMD(3, 0, 0x2e) #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS CMD(3, 0, 0x2f) #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS CMD(3, 0, 0x2c) #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS CMD(3, 0, 0x2d) #define MFX(pipeline, op, sub_opa, sub_opb) \ (3 << 29 | \ (pipeline) << 27 | \ (op) << 24 | \ (sub_opa) << 21 | \ (sub_opb) << 16) #define MFX_PIPE_MODE_SELECT MFX(2, 0, 0, 0) #define MFX_SURFACE_STATE MFX(2, 0, 0, 1) #define MFX_PIPE_BUF_ADDR_STATE MFX(2, 0, 0, 2) #define MFX_IND_OBJ_BASE_ADDR_STATE MFX(2, 0, 0, 3) #define MFX_BSP_BUF_BASE_ADDR_STATE MFX(2, 0, 0, 4) #define MFX_AES_STATE MFX(2, 0, 0, 5) #define MFX_STATE_POINTER MFX(2, 0, 0, 6) #define MFX_QM_STATE MFX(2, 0, 0, 7) #define MFX_FQM_STATE MFX(2, 0, 0, 8) #define MFX_INSERT_OBJECT MFX(2, 0, 2, 8) #define MFX_WAIT MFX(1, 0, 0, 0) #define MFX_AVC_IMG_STATE MFX(2, 1, 0, 0) #define MFX_AVC_QM_STATE MFX(2, 1, 0, 1) #define MFX_AVC_DIRECTMODE_STATE MFX(2, 1, 0, 2) #define MFX_AVC_SLICE_STATE MFX(2, 1, 0, 3) #define MFX_AVC_REF_IDX_STATE MFX(2, 1, 0, 4) #define MFX_AVC_WEIGHTOFFSET_STATE MFX(2, 1, 0, 5) #define MFD_AVC_PICID_STATE MFX(2, 1, 1, 5) #define MFD_AVC_BSD_OBJECT MFX(2, 1, 1, 8) #define MFC_AVC_FQM_STATE MFX(2, 1, 2, 2) #define MFC_AVC_INSERT_OBJECT MFX(2, 1, 2, 8) #define MFC_AVC_PAK_OBJECT MFX(2, 1, 2, 9) #define MFX_MPEG2_PIC_STATE MFX(2, 3, 0, 0) #define MFX_MPEG2_QM_STATE MFX(2, 3, 0, 1) #define MFD_MPEG2_BSD_OBJECT MFX(2, 3, 1, 8) #define MFC_MPEG2_SLICEGROUP_STATE MFX(2, 3, 2, 3) #define MFC_MPEG2_PAK_OBJECT MFX(2, 3, 2, 9) #define MFX_VC1_PIC_STATE MFX(2, 2, 0, 0) #define MFX_VC1_PRED_PIPE_STATE MFX(2, 2, 0, 1) #define MFX_VC1_DIRECTMODE_STATE MFX(2, 2, 0, 2) #define MFD_VC1_SHORT_PIC_STATE MFX(2, 2, 1, 0) #define MFD_VC1_LONG_PIC_STATE MFX(2, 2, 1, 1) #define MFD_VC1_BSD_OBJECT MFX(2, 2, 1, 8) #define MFX_JPEG_PIC_STATE MFX(2, 7, 0, 0) #define MFX_JPEG_HUFF_TABLE_STATE MFX(2, 7, 0, 2) #define MFD_JPEG_BSD_OBJECT MFX(2, 7, 1, 8) #define MFX_VP8_PIC_STATE MFX(2, 4, 0, 0) #define MFD_VP8_BSD_OBJECT MFX(2, 4, 1, 8) #define VEB(pipeline, op, sub_opa, sub_opb) \ (3 << 29 | \ (pipeline) << 27 | \ (op) << 24 | \ (sub_opa) << 21 | \ (sub_opb) << 16) #define VEB_SURFACE_STATE VEB(2, 4, 0, 0) #define VEB_STATE VEB(2, 4, 0, 2) #define VEB_DNDI_IECP_STATE VEB(2, 4, 0, 3) #define I965_DEPTHFORMAT_D32_FLOAT 1 #define BASE_ADDRESS_MODIFY (1 << 0) #define PIPELINE_SELECT_3D 0 #define PIPELINE_SELECT_MEDIA 1 #define UF0_CS_REALLOC (1 << 13) #define UF0_VFE_REALLOC (1 << 12) #define UF0_SF_REALLOC (1 << 11) #define UF0_CLIP_REALLOC (1 << 10) #define UF0_GS_REALLOC (1 << 9) #define UF0_VS_REALLOC (1 << 8) #define UF1_CLIP_FENCE_SHIFT 20 #define UF1_GS_FENCE_SHIFT 10 #define UF1_VS_FENCE_SHIFT 0 #define UF2_CS_FENCE_SHIFT 20 #define UF2_VFE_FENCE_SHIFT 10 #define UF2_SF_FENCE_SHIFT 0 #define VFE_GENERIC_MODE 0x0 #define VFE_VLD_MODE 0x1 #define VFE_IS_MODE 0x2 #define VFE_AVC_MC_MODE 0x4 #define VFE_AVC_IT_MODE 0x7 #define FLOATING_POINT_IEEE_754 0 #define FLOATING_POINT_NON_IEEE_754 1 #define I965_SURFACE_1D 0 #define I965_SURFACE_2D 1 #define I965_SURFACE_3D 2 #define I965_SURFACE_CUBE 3 #define I965_SURFACE_BUFFER 4 #define I965_SURFACE_NULL 7 #define I965_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 #define I965_SURFACEFORMAT_R32G32B32A32_SINT 0x001 #define I965_SURFACEFORMAT_R32G32B32A32_UINT 0x002 #define I965_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 #define I965_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 #define I965_SURFACEFORMAT_R64G64_FLOAT 0x005 #define I965_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 #define I965_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 #define I965_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 #define I965_SURFACEFORMAT_R32G32B32_FLOAT 0x040 #define I965_SURFACEFORMAT_R32G32B32_SINT 0x041 #define I965_SURFACEFORMAT_R32G32B32_UINT 0x042 #define I965_SURFACEFORMAT_R32G32B32_UNORM 0x043 #define I965_SURFACEFORMAT_R32G32B32_SNORM 0x044 #define I965_SURFACEFORMAT_R32G32B32_SSCALED 0x045 #define I965_SURFACEFORMAT_R32G32B32_USCALED 0x046 #define I965_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 #define I965_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 #define I965_SURFACEFORMAT_R16G16B16A16_SINT 0x082 #define I965_SURFACEFORMAT_R16G16B16A16_UINT 0x083 #define I965_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 #define I965_SURFACEFORMAT_R32G32_FLOAT 0x085 #define I965_SURFACEFORMAT_R32G32_SINT 0x086 #define I965_SURFACEFORMAT_R32G32_UINT 0x087 #define I965_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 #define I965_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089 #define I965_SURFACEFORMAT_L32A32_FLOAT 0x08A #define I965_SURFACEFORMAT_R32G32_UNORM 0x08B #define I965_SURFACEFORMAT_R32G32_SNORM 0x08C #define I965_SURFACEFORMAT_R64_FLOAT 0x08D #define I965_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E #define I965_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F #define I965_SURFACEFORMAT_A32X32_FLOAT 0x090 #define I965_SURFACEFORMAT_L32X32_FLOAT 0x091 #define I965_SURFACEFORMAT_I32X32_FLOAT 0x092 #define I965_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 #define I965_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 #define I965_SURFACEFORMAT_R32G32_SSCALED 0x095 #define I965_SURFACEFORMAT_R32G32_USCALED 0x096 #define I965_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 #define I965_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1 #define I965_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 #define I965_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 #define I965_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 #define I965_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 #define I965_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 #define I965_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8 #define I965_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 #define I965_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA #define I965_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB #define I965_SURFACEFORMAT_R16G16_UNORM 0x0CC #define I965_SURFACEFORMAT_R16G16_SNORM 0x0CD #define I965_SURFACEFORMAT_R16G16_SINT 0x0CE #define I965_SURFACEFORMAT_R16G16_UINT 0x0CF #define I965_SURFACEFORMAT_R16G16_FLOAT 0x0D0 #define I965_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 #define I965_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 #define I965_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3 #define I965_SURFACEFORMAT_R32_SINT 0x0D6 #define I965_SURFACEFORMAT_R32_UINT 0x0D7 #define I965_SURFACEFORMAT_R32_FLOAT 0x0D8 #define I965_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9 #define I965_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA #define I965_SURFACEFORMAT_L16A16_UNORM 0x0DF #define I965_SURFACEFORMAT_I24X8_UNORM 0x0E0 #define I965_SURFACEFORMAT_L24X8_UNORM 0x0E1 #define I965_SURFACEFORMAT_A24X8_UNORM 0x0E2 #define I965_SURFACEFORMAT_I32_FLOAT 0x0E3 #define I965_SURFACEFORMAT_L32_FLOAT 0x0E4 #define I965_SURFACEFORMAT_A32_FLOAT 0x0E5 #define I965_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9 #define I965_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA #define I965_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB #define I965_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC #define I965_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED #define I965_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE #define I965_SURFACEFORMAT_L16A16_FLOAT 0x0F0 #define I965_SURFACEFORMAT_R32_UNORM 0x0F1 #define I965_SURFACEFORMAT_R32_SNORM 0x0F2 #define I965_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3 #define I965_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4 #define I965_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5 #define I965_SURFACEFORMAT_R16G16_SSCALED 0x0F6 #define I965_SURFACEFORMAT_R16G16_USCALED 0x0F7 #define I965_SURFACEFORMAT_R32_SSCALED 0x0F8 #define I965_SURFACEFORMAT_R32_USCALED 0x0F9 #define I965_SURFACEFORMAT_B5G6R5_UNORM 0x100 #define I965_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101 #define I965_SURFACEFORMAT_B5G5R5A1_UNORM 0x102 #define I965_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103 #define I965_SURFACEFORMAT_B4G4R4A4_UNORM 0x104 #define I965_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105 #define I965_SURFACEFORMAT_R8G8_UNORM 0x106 #define I965_SURFACEFORMAT_R8G8_SNORM 0x107 #define I965_SURFACEFORMAT_R8G8_SINT 0x108 #define I965_SURFACEFORMAT_R8G8_UINT 0x109 #define I965_SURFACEFORMAT_R16_UNORM 0x10A #define I965_SURFACEFORMAT_R16_SNORM 0x10B #define I965_SURFACEFORMAT_R16_SINT 0x10C #define I965_SURFACEFORMAT_R16_UINT 0x10D #define I965_SURFACEFORMAT_R16_FLOAT 0x10E #define I965_SURFACEFORMAT_I16_UNORM 0x111 #define I965_SURFACEFORMAT_L16_UNORM 0x112 #define I965_SURFACEFORMAT_A16_UNORM 0x113 #define I965_SURFACEFORMAT_L8A8_UNORM 0x114 #define I965_SURFACEFORMAT_I16_FLOAT 0x115 #define I965_SURFACEFORMAT_L16_FLOAT 0x116 #define I965_SURFACEFORMAT_A16_FLOAT 0x117 #define I965_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 #define I965_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A #define I965_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B #define I965_SURFACEFORMAT_R8G8_SSCALED 0x11C #define I965_SURFACEFORMAT_R8G8_USCALED 0x11D #define I965_SURFACEFORMAT_R16_SSCALED 0x11E #define I965_SURFACEFORMAT_R16_USCALED 0x11F #define I965_SURFACEFORMAT_P8A8_UNORM 0x122 #define I965_SURFACEFORMAT_A8P8_UNORM 0x123 #define I965_SURFACEFORMAT_R8_UNORM 0x140 #define I965_SURFACEFORMAT_R8_SNORM 0x141 #define I965_SURFACEFORMAT_R8_SINT 0x142 #define I965_SURFACEFORMAT_R8_UINT 0x143 #define I965_SURFACEFORMAT_A8_UNORM 0x144 #define I965_SURFACEFORMAT_I8_UNORM 0x145 #define I965_SURFACEFORMAT_L8_UNORM 0x146 #define I965_SURFACEFORMAT_P4A4_UNORM 0x147 #define I965_SURFACEFORMAT_A4P4_UNORM 0x148 #define I965_SURFACEFORMAT_R8_SSCALED 0x149 #define I965_SURFACEFORMAT_R8_USCALED 0x14A #define I965_SURFACEFORMAT_R1_UINT 0x181 #define I965_SURFACEFORMAT_YCRCB_NORMAL 0x182 #define I965_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 #define I965_SURFACEFORMAT_BC1_UNORM 0x186 #define I965_SURFACEFORMAT_BC2_UNORM 0x187 #define I965_SURFACEFORMAT_BC3_UNORM 0x188 #define I965_SURFACEFORMAT_BC4_UNORM 0x189 #define I965_SURFACEFORMAT_BC5_UNORM 0x18A #define I965_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B #define I965_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C #define I965_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D #define I965_SURFACEFORMAT_MONO8 0x18E #define I965_SURFACEFORMAT_YCRCB_SWAPUV 0x18F #define I965_SURFACEFORMAT_YCRCB_SWAPY 0x190 #define I965_SURFACEFORMAT_DXT1_RGB 0x191 #define I965_SURFACEFORMAT_FXT1 0x192 #define I965_SURFACEFORMAT_R8G8B8_UNORM 0x193 #define I965_SURFACEFORMAT_R8G8B8_SNORM 0x194 #define I965_SURFACEFORMAT_R8G8B8_SSCALED 0x195 #define I965_SURFACEFORMAT_R8G8B8_USCALED 0x196 #define I965_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197 #define I965_SURFACEFORMAT_R64G64B64_FLOAT 0x198 #define I965_SURFACEFORMAT_BC4_SNORM 0x199 #define I965_SURFACEFORMAT_BC5_SNORM 0x19A #define I965_SURFACEFORMAT_R16G16B16_UNORM 0x19C #define I965_SURFACEFORMAT_R16G16B16_SNORM 0x19D #define I965_SURFACEFORMAT_R16G16B16_SSCALED 0x19E #define I965_SURFACEFORMAT_R16G16B16_USCALED 0x19F #define I965_CULLMODE_BOTH 0 #define I965_CULLMODE_NONE 1 #define I965_CULLMODE_FRONT 2 #define I965_CULLMODE_BACK 3 #define I965_MAPFILTER_NEAREST 0x0 #define I965_MAPFILTER_LINEAR 0x1 #define I965_MAPFILTER_ANISOTROPIC 0x2 #define I965_MIPFILTER_NONE 0 #define I965_MIPFILTER_NEAREST 1 #define I965_MIPFILTER_LINEAR 3 #define HSW_SCS_ZERO 0 #define HSW_SCS_ONE 1 #define HSW_SCS_RED 4 #define HSW_SCS_GREEN 5 #define HSW_SCS_BLUE 6 #define HSW_SCS_ALPHA 7 #define I965_TEXCOORDMODE_WRAP 0 #define I965_TEXCOORDMODE_MIRROR 1 #define I965_TEXCOORDMODE_CLAMP 2 #define I965_TEXCOORDMODE_CUBE 3 #define I965_TEXCOORDMODE_CLAMP_BORDER 4 #define I965_TEXCOORDMODE_MIRROR_ONCE 5 #define I965_BLENDFACTOR_ONE 0x1 #define I965_BLENDFACTOR_SRC_COLOR 0x2 #define I965_BLENDFACTOR_SRC_ALPHA 0x3 #define I965_BLENDFACTOR_DST_ALPHA 0x4 #define I965_BLENDFACTOR_DST_COLOR 0x5 #define I965_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 #define I965_BLENDFACTOR_CONST_COLOR 0x7 #define I965_BLENDFACTOR_CONST_ALPHA 0x8 #define I965_BLENDFACTOR_SRC1_COLOR 0x9 #define I965_BLENDFACTOR_SRC1_ALPHA 0x0A #define I965_BLENDFACTOR_ZERO 0x11 #define I965_BLENDFACTOR_INV_SRC_COLOR 0x12 #define I965_BLENDFACTOR_INV_SRC_ALPHA 0x13 #define I965_BLENDFACTOR_INV_DST_ALPHA 0x14 #define I965_BLENDFACTOR_INV_DST_COLOR 0x15 #define I965_BLENDFACTOR_INV_CONST_COLOR 0x17 #define I965_BLENDFACTOR_INV_CONST_ALPHA 0x18 #define I965_BLENDFACTOR_INV_SRC1_COLOR 0x19 #define I965_BLENDFACTOR_INV_SRC1_ALPHA 0x1A #define I965_BLENDFUNCTION_ADD 0 #define I965_BLENDFUNCTION_SUBTRACT 1 #define I965_BLENDFUNCTION_REVERSE_SUBTRACT 2 #define I965_BLENDFUNCTION_MIN 3 #define I965_BLENDFUNCTION_MAX 4 #define I965_SURFACERETURNFORMAT_FLOAT32 0 #define I965_SURFACERETURNFORMAT_S1 1 #define I965_VFCOMPONENT_NOSTORE 0 #define I965_VFCOMPONENT_STORE_SRC 1 #define I965_VFCOMPONENT_STORE_0 2 #define I965_VFCOMPONENT_STORE_1_FLT 3 #define I965_VFCOMPONENT_STORE_1_INT 4 #define I965_VFCOMPONENT_STORE_VID 5 #define I965_VFCOMPONENT_STORE_IID 6 #define I965_VFCOMPONENT_STORE_PID 7 #define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 #define GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN6 */ #define VE0_VALID (1 << 26) #define GEN6_VE0_VALID (1 << 25) /* for GEN6 */ #define VE0_FORMAT_SHIFT 16 #define VE0_OFFSET_SHIFT 0 #define VE1_VFCOMPONENT_0_SHIFT 28 #define VE1_VFCOMPONENT_1_SHIFT 24 #define VE1_VFCOMPONENT_2_SHIFT 20 #define VE1_VFCOMPONENT_3_SHIFT 16 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 #define GEN8_VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN8 */ #define GEN8_VE0_VALID (1 << 25) /* for GEN8 */ #define VB0_BUFFER_INDEX_SHIFT 27 #define GEN6_VB0_BUFFER_INDEX_SHIFT 26 #define VB0_VERTEXDATA (0 << 26) #define VB0_INSTANCEDATA (1 << 26) #define GEN6_VB0_VERTEXDATA (0 << 20) #define GEN6_VB0_INSTANCEDATA (1 << 20) #define GEN7_VB0_ADDRESS_MODIFYENABLE (1 << 14) #define VB0_BUFFER_PITCH_SHIFT 0 #define GEN8_VB0_BUFFER_INDEX_SHIFT 26 #define GEN8_VB0_MOCS_SHIFT 16 #define _3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15) #define _3DPRIMITIVE_VERTEX_RANDOM (1 << 15) #define _3DPRIMITIVE_TOPOLOGY_SHIFT 10 /* DW1 on GEN7*/ # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8) # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 8) #define _3DPRIM_POINTLIST 0x01 #define _3DPRIM_LINELIST 0x02 #define _3DPRIM_LINESTRIP 0x03 #define _3DPRIM_TRILIST 0x04 #define _3DPRIM_TRISTRIP 0x05 #define _3DPRIM_TRIFAN 0x06 #define _3DPRIM_QUADLIST 0x07 #define _3DPRIM_QUADSTRIP 0x08 #define _3DPRIM_LINELIST_ADJ 0x09 #define _3DPRIM_LINESTRIP_ADJ 0x0A #define _3DPRIM_TRILIST_ADJ 0x0B #define _3DPRIM_TRISTRIP_ADJ 0x0C #define _3DPRIM_TRISTRIP_REVERSE 0x0D #define _3DPRIM_POLYGON 0x0E #define _3DPRIM_RECTLIST 0x0F #define _3DPRIM_LINELOOP 0x10 #define _3DPRIM_POINTLIST_BF 0x11 #define _3DPRIM_LINESTRIP_CONT 0x12 #define _3DPRIM_LINESTRIP_BF 0x13 #define _3DPRIM_LINESTRIP_CONT_BF 0x14 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 #define GEN8_3DSTATE_VF_TOPOLOGY CMD(3, 0, 0x4b) #define I965_TILEWALK_XMAJOR 0 #define I965_TILEWALK_YMAJOR 1 #define SCAN_RASTER_ORDER 0 #define SCAN_SPECIAL_ORDER 1 #define ENTROPY_CAVLD 0 #define ENTROPY_CABAC 1 #define SLICE_TYPE_P 0 #define SLICE_TYPE_B 1 #define SLICE_TYPE_I 2 #define SLICE_TYPE_SP 3 #define SLICE_TYPE_SI 4 #define PRESENT_REF_LIST0 (1 << 0) #define PRESENT_REF_LIST1 (1 << 1) #define PRESENT_WEIGHT_OFFSET_L0 (1 << 2) #define PRESENT_WEIGHT_OFFSET_L1 (1 << 3) #define RESIDUAL_DATA_OFFSET 48 #define PRESENT_NOMV 0 #define PRESENT_NOWO 1 #define PRESENT_MV_WO 3 #define SCOREBOARD_STALLING 0 #define SCOREBOARD_NON_STALLING 1 #define SURFACE_FORMAT_YCRCB_NORMAL 0 #define SURFACE_FORMAT_YCRCB_SWAPUVY 1 #define SURFACE_FORMAT_YCRCB_SWAPUV 2 #define SURFACE_FORMAT_YCRCB_SWAPY 3 #define SURFACE_FORMAT_PLANAR_420_8 4 #define SURFACE_FORMAT_PLANAR_411_8 5 #define SURFACE_FORMAT_PLANAR_422_8 6 #define SURFACE_FORMAT_STMM_DN_STATISTICS 7 #define SURFACE_FORMAT_R10G10B10A2_UNORM 8 #define SURFACE_FORMAT_R8G8B8A8_UNORM 9 #define SURFACE_FORMAT_R8B8_UNORM 10 #define SURFACE_FORMAT_R8_UNORM 11 #define SURFACE_FORMAT_Y8_UNORM 12 #define AVS_FILTER_ADAPTIVE_8_TAP 0 #define AVS_FILTER_NEAREST 1 #define IEF_FILTER_COMBO 0 #define IEF_FILTER_DETAIL 1 #define IEF_FILTER_SIZE_3X3 0 #define IEF_FILTER_SIZE_5X5 1 #define MFX_FORMAT_MPEG2 0 #define MFX_FORMAT_VC1 1 #define MFX_FORMAT_AVC 2 #define MFX_FORMAT_JPEG 3 #define MFX_FORMAT_SVC 4 #define MFX_FORMAT_VP8 5 #define MFX_SHORT_MODE 0 #define MFX_LONG_MODE 1 #define MFX_CODEC_DECODE 0 #define MFX_CODEC_ENCODE 1 #define MFX_QM_AVC_4X4_INTRA_MATRIX 0 #define MFX_QM_AVC_4X4_INTER_MATRIX 1 #define MFX_QM_AVC_8x8_INTRA_MATRIX 2 #define MFX_QM_AVC_8x8_INTER_MATRIX 3 #define MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX 0 #define MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX 1 #define MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX 0 #define MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX 1 #define MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX 2 #define MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX 3 /* for new device */ #define MFX_HUFFTABLE_ID_Y 0 #define MFX_HUFFTABLE_ID_UV 1 /* UV on Ivybridge */ #define MFD_MODE_VLD 0 #define MFD_MODE_IT 1 #define MFX_SURFACE_PLANAR_420_8 4 #define MFX_SURFACE_PLANAR_411_8 5 #define MFX_SURFACE_PLANAR_422_8 6 #define MFX_SURFACE_MONOCHROME 12 #define MPEG_I_PICTURE 1 #define MPEG_P_PICTURE 2 #define MPEG_B_PICTURE 3 #define MPEG_TOP_FIELD 1 #define MPEG_BOTTOM_FIELD 2 #define MPEG_FRAME 3 #define SUBSAMPLE_YUV400 0 #define SUBSAMPLE_YUV420 1 #define SUBSAMPLE_YUV422H 2 #define SUBSAMPLE_YUV422V 3 #define SUBSAMPLE_YUV444 4 #define SUBSAMPLE_YUV411 5 #define SUBSAMPLE_RGBX 6 #define URB_SIZE(intel) (IS_GEN7(intel->device_id) ? 4096 : \ IS_GEN8(intel->device_id) ? 4096 : \ IS_GEN6(intel->device_id) ? 1024 : \ IS_IRONLAKE(intel->device_id) ? 1024 : \ IS_G4X(intel->device_id) ? 384 : 256) #endif /* _I965_DEFINES_H_ */ intel-driver-1.3.0/src/i965_drv_video.c000077500000000000000000005575561231401140700176320ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * Zou Nan hai * */ #include "sysdeps.h" #ifdef HAVE_VA_X11 # include "i965_output_dri.h" #endif #ifdef HAVE_VA_WAYLAND # include "i965_output_wayland.h" #endif #include "intel_driver.h" #include "intel_memman.h" #include "intel_batchbuffer.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_decoder.h" #include "i965_encoder.h" #define CONFIG_ID_OFFSET 0x01000000 #define CONTEXT_ID_OFFSET 0x02000000 #define SURFACE_ID_OFFSET 0x04000000 #define BUFFER_ID_OFFSET 0x08000000 #define IMAGE_ID_OFFSET 0x0a000000 #define SUBPIC_ID_OFFSET 0x10000000 #define HAS_MPEG2_DECODING(ctx) ((ctx)->codec_info->has_mpeg2_decoding && \ (ctx)->intel.has_bsd) #define HAS_MPEG2_ENCODING(ctx) ((ctx)->codec_info->has_mpeg2_encoding && \ (ctx)->intel.has_bsd) #define HAS_H264_DECODING(ctx) ((ctx)->codec_info->has_h264_decoding && \ (ctx)->intel.has_bsd) #define HAS_H264_ENCODING(ctx) ((ctx)->codec_info->has_h264_encoding && \ (ctx)->intel.has_bsd) #define HAS_VC1_DECODING(ctx) ((ctx)->codec_info->has_vc1_decoding && \ (ctx)->intel.has_bsd) #define HAS_JPEG_DECODING(ctx) ((ctx)->codec_info->has_jpeg_decoding && \ (ctx)->intel.has_bsd) #define HAS_VPP(ctx) ((ctx)->codec_info->has_vpp) #define HAS_ACCELERATED_GETIMAGE(ctx) ((ctx)->codec_info->has_accelerated_getimage) #define HAS_ACCELERATED_PUTIMAGE(ctx) ((ctx)->codec_info->has_accelerated_putimage) #define HAS_TILED_SURFACE(ctx) ((ctx)->codec_info->has_tiled_surface) #define HAS_VP8_DECODING(ctx) ((ctx)->codec_info->has_vp8_decoding && \ (ctx)->intel.has_bsd) #define HAS_VP8_ENCODING(ctx) ((ctx)->codec_info->has_vp8_encoding && \ (ctx)->intel.has_bsd) static int get_sampling_from_fourcc(unsigned int fourcc); /* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */ #define IS_VA_X11(ctx) \ (((ctx)->display_type & VA_DISPLAY_MAJOR_MASK) == VA_DISPLAY_X11) /* Check whether we are rendering to Wayland */ #define IS_VA_WAYLAND(ctx) \ (((ctx)->display_type & VA_DISPLAY_MAJOR_MASK) == VA_DISPLAY_WAYLAND) enum { I965_SURFACETYPE_RGBA = 1, I965_SURFACETYPE_YUV, I965_SURFACETYPE_INDEXED }; /* List of supported display attributes */ static const VADisplayAttribute i965_display_attributes[] = { { VADisplayAttribBrightness, -100, 100, DEFAULT_BRIGHTNESS, VA_DISPLAY_ATTRIB_GETTABLE | VA_DISPLAY_ATTRIB_SETTABLE }, { VADisplayAttribContrast, 0, 100, DEFAULT_CONTRAST, VA_DISPLAY_ATTRIB_GETTABLE | VA_DISPLAY_ATTRIB_SETTABLE }, { VADisplayAttribHue, -180, 180, DEFAULT_HUE, VA_DISPLAY_ATTRIB_GETTABLE | VA_DISPLAY_ATTRIB_SETTABLE }, { VADisplayAttribSaturation, 0, 100, DEFAULT_SATURATION, VA_DISPLAY_ATTRIB_GETTABLE | VA_DISPLAY_ATTRIB_SETTABLE }, { VADisplayAttribRotation, 0, 3, VA_ROTATION_NONE, VA_DISPLAY_ATTRIB_GETTABLE|VA_DISPLAY_ATTRIB_SETTABLE }, }; /* List of supported image formats */ typedef struct { unsigned int type; VAImageFormat va_format; } i965_image_format_map_t; static const i965_image_format_map_t i965_image_formats_map[I965_MAX_IMAGE_FORMATS + 1] = { { I965_SURFACETYPE_YUV, { VA_FOURCC('Y','V','1','2'), VA_LSB_FIRST, 12, } }, { I965_SURFACETYPE_YUV, { VA_FOURCC('I','4','2','0'), VA_LSB_FIRST, 12, } }, { I965_SURFACETYPE_YUV, { VA_FOURCC('N','V','1','2'), VA_LSB_FIRST, 12, } }, { I965_SURFACETYPE_YUV, { VA_FOURCC('Y','U','Y','2'), VA_LSB_FIRST, 16, } }, { I965_SURFACETYPE_YUV, { VA_FOURCC('U','Y','V','Y'), VA_LSB_FIRST, 16, } }, { I965_SURFACETYPE_RGBA, { VA_FOURCC('R','G','B','X'), VA_LSB_FIRST, 32, 24, 0x000000ff, 0x0000ff00, 0x00ff0000 } }, { I965_SURFACETYPE_RGBA, { VA_FOURCC('B','G','R','X'), VA_LSB_FIRST, 32, 24, 0x00ff0000, 0x0000ff00, 0x000000ff } }, }; /* List of supported subpicture formats */ typedef struct { unsigned int type; unsigned int format; VAImageFormat va_format; unsigned int va_flags; } i965_subpic_format_map_t; #define COMMON_SUBPICTURE_FLAGS \ (VA_SUBPICTURE_DESTINATION_IS_SCREEN_COORD| \ VA_SUBPICTURE_GLOBAL_ALPHA) static const i965_subpic_format_map_t i965_subpic_formats_map[I965_MAX_SUBPIC_FORMATS + 1] = { { I965_SURFACETYPE_INDEXED, I965_SURFACEFORMAT_P4A4_UNORM, { VA_FOURCC('I','A','4','4'), VA_MSB_FIRST, 8, }, COMMON_SUBPICTURE_FLAGS }, { I965_SURFACETYPE_INDEXED, I965_SURFACEFORMAT_A4P4_UNORM, { VA_FOURCC('A','I','4','4'), VA_MSB_FIRST, 8, }, COMMON_SUBPICTURE_FLAGS }, { I965_SURFACETYPE_INDEXED, I965_SURFACEFORMAT_P8A8_UNORM, { VA_FOURCC('I','A','8','8'), VA_MSB_FIRST, 16, }, COMMON_SUBPICTURE_FLAGS }, { I965_SURFACETYPE_INDEXED, I965_SURFACEFORMAT_A8P8_UNORM, { VA_FOURCC('A','I','8','8'), VA_MSB_FIRST, 16, }, COMMON_SUBPICTURE_FLAGS }, { I965_SURFACETYPE_RGBA, I965_SURFACEFORMAT_B8G8R8A8_UNORM, { VA_FOURCC('B','G','R','A'), VA_LSB_FIRST, 32, 32, 0x00ff0000, 0x0000ff00, 0x000000ff, 0xff000000 }, COMMON_SUBPICTURE_FLAGS }, { I965_SURFACETYPE_RGBA, I965_SURFACEFORMAT_R8G8B8A8_UNORM, { VA_FOURCC('R','G','B','A'), VA_LSB_FIRST, 32, 32, 0x000000ff, 0x0000ff00, 0x00ff0000, 0xff000000 }, COMMON_SUBPICTURE_FLAGS }, }; static const i965_subpic_format_map_t * get_subpic_format(const VAImageFormat *va_format) { unsigned int i; for (i = 0; i965_subpic_formats_map[i].type != 0; i++) { const i965_subpic_format_map_t * const m = &i965_subpic_formats_map[i]; if (m->va_format.fourcc == va_format->fourcc && (m->type == I965_SURFACETYPE_RGBA ? (m->va_format.byte_order == va_format->byte_order && m->va_format.red_mask == va_format->red_mask && m->va_format.green_mask == va_format->green_mask && m->va_format.blue_mask == va_format->blue_mask && m->va_format.alpha_mask == va_format->alpha_mask) : 1)) return m; } return NULL; } extern struct hw_context *i965_proc_context_init(VADriverContextP, struct object_config *); extern struct hw_context *g4x_dec_hw_context_init(VADriverContextP, struct object_config *); static struct hw_codec_info g4x_hw_codec_info = { .dec_hw_context_init = g4x_dec_hw_context_init, .enc_hw_context_init = NULL, .proc_hw_context_init = NULL, .max_width = 2048, .max_height = 2048, .has_mpeg2_decoding = 1, .num_filters = 0, }; extern struct hw_context *ironlake_dec_hw_context_init(VADriverContextP, struct object_config *); static struct hw_codec_info ironlake_hw_codec_info = { .dec_hw_context_init = ironlake_dec_hw_context_init, .enc_hw_context_init = NULL, .proc_hw_context_init = i965_proc_context_init, .max_width = 2048, .max_height = 2048, .has_mpeg2_decoding = 1, .has_h264_decoding = 1, .has_vpp = 1, .has_accelerated_putimage = 1, .num_filters = 0, }; extern struct hw_context *gen6_dec_hw_context_init(VADriverContextP, struct object_config *); extern struct hw_context *gen6_enc_hw_context_init(VADriverContextP, struct object_config *); static struct hw_codec_info gen6_hw_codec_info = { .dec_hw_context_init = gen6_dec_hw_context_init, .enc_hw_context_init = gen6_enc_hw_context_init, .proc_hw_context_init = i965_proc_context_init, .max_width = 2048, .max_height = 2048, .has_mpeg2_decoding = 1, .has_h264_decoding = 1, .has_h264_encoding = 1, .has_vc1_decoding = 1, .has_vpp = 1, .has_accelerated_getimage = 1, .has_accelerated_putimage = 1, .has_tiled_surface = 1, .num_filters = 2, .filters = { { VAProcFilterNoiseReduction, I965_RING_NULL }, { VAProcFilterDeinterlacing, I965_RING_NULL }, }, }; extern struct hw_context *gen7_dec_hw_context_init(VADriverContextP, struct object_config *); extern struct hw_context *gen7_enc_hw_context_init(VADriverContextP, struct object_config *); static struct hw_codec_info gen7_hw_codec_info = { .dec_hw_context_init = gen7_dec_hw_context_init, .enc_hw_context_init = gen7_enc_hw_context_init, .proc_hw_context_init = i965_proc_context_init, .max_width = 4096, .max_height = 4096, .has_mpeg2_decoding = 1, .has_mpeg2_encoding = 1, .has_h264_decoding = 1, .has_h264_encoding = 1, .has_vc1_decoding = 1, .has_jpeg_decoding = 1, .has_vpp = 1, .has_accelerated_getimage = 1, .has_accelerated_putimage = 1, .has_tiled_surface = 1, .has_di_motion_adptive = 1, .num_filters = 2, .filters = { { VAProcFilterNoiseReduction, I965_RING_NULL }, { VAProcFilterDeinterlacing, I965_RING_NULL }, }, }; extern struct hw_context *gen75_proc_context_init(VADriverContextP, struct object_config *); static struct hw_codec_info gen75_hw_codec_info = { .dec_hw_context_init = gen75_dec_hw_context_init, .enc_hw_context_init = gen75_enc_hw_context_init, .proc_hw_context_init = gen75_proc_context_init, .max_width = 4096, .max_height = 4096, .has_mpeg2_decoding = 1, .has_mpeg2_encoding = 1, .has_h264_decoding = 1, .has_h264_encoding = 1, .has_vc1_decoding = 1, .has_jpeg_decoding = 1, .has_vpp = 1, .has_accelerated_getimage = 1, .has_accelerated_putimage = 1, .has_tiled_surface = 1, .has_di_motion_adptive = 1, .has_di_motion_compensated = 1, .num_filters = 4, .filters = { { VAProcFilterNoiseReduction, I965_RING_VEBOX }, { VAProcFilterDeinterlacing, I965_RING_VEBOX }, { VAProcFilterSharpening, I965_RING_NULL }, { VAProcFilterColorBalance, I965_RING_VEBOX}, }, }; /* TODO: Add the separate call back function for Gen8 */ static struct hw_codec_info gen8_hw_codec_info = { .dec_hw_context_init = gen8_dec_hw_context_init, .enc_hw_context_init = gen8_enc_hw_context_init, .proc_hw_context_init = gen75_proc_context_init, .max_width = 4096, .max_height = 4096, .has_mpeg2_decoding = 1, .has_mpeg2_encoding = 1, .has_h264_decoding = 1, .has_h264_encoding = 1, .has_vc1_decoding = 1, .has_jpeg_decoding = 1, .has_vpp = 1, .has_accelerated_getimage = 1, .has_accelerated_putimage = 1, .has_tiled_surface = 1, .has_di_motion_adptive = 1, .has_di_motion_compensated = 1, .has_vp8_decoding = 1, .num_filters = 4, .filters = { { VAProcFilterNoiseReduction, I965_RING_VEBOX }, { VAProcFilterDeinterlacing, I965_RING_VEBOX }, { VAProcFilterSharpening, I965_RING_NULL }, /* need to rebuild the shader for BDW */ { VAProcFilterColorBalance, I965_RING_VEBOX}, }, }; #define I965_PACKED_HEADER_BASE 0 #define I965_PACKED_MISC_HEADER_BASE 3 int va_enc_packed_type_to_idx(int packed_type) { int idx = 0; if (packed_type & VAEncPackedHeaderMiscMask) { idx = I965_PACKED_MISC_HEADER_BASE; packed_type = (~VAEncPackedHeaderMiscMask & packed_type); assert(packed_type > 0); idx += (packed_type - 1); } else { idx = I965_PACKED_HEADER_BASE; switch (packed_type) { case VAEncPackedHeaderSequence: idx = I965_PACKED_HEADER_BASE + 0; break; case VAEncPackedHeaderPicture: idx = I965_PACKED_HEADER_BASE + 1; break; case VAEncPackedHeaderSlice: idx = I965_PACKED_HEADER_BASE + 2; break; default: /* Should not get here */ assert(0); break; } } assert(idx < 4); return idx; } VAStatus i965_QueryConfigProfiles(VADriverContextP ctx, VAProfile *profile_list, /* out */ int *num_profiles) /* out */ { struct i965_driver_data * const i965 = i965_driver_data(ctx); int i = 0; if (HAS_MPEG2_DECODING(i965) || HAS_MPEG2_ENCODING(i965)) { profile_list[i++] = VAProfileMPEG2Simple; profile_list[i++] = VAProfileMPEG2Main; } if (HAS_H264_DECODING(i965) || HAS_H264_ENCODING(i965)) { profile_list[i++] = VAProfileH264ConstrainedBaseline; profile_list[i++] = VAProfileH264Main; profile_list[i++] = VAProfileH264High; } if (HAS_VC1_DECODING(i965)) { profile_list[i++] = VAProfileVC1Simple; profile_list[i++] = VAProfileVC1Main; profile_list[i++] = VAProfileVC1Advanced; } if (HAS_VPP(i965)) { profile_list[i++] = VAProfileNone; } if (HAS_JPEG_DECODING(i965)) { profile_list[i++] = VAProfileJPEGBaseline; } if (HAS_VP8_DECODING(i965) || HAS_VP8_ENCODING(i965)) { profile_list[i++] = VAProfileVP8Version0_3; } /* If the assert fails then I965_MAX_PROFILES needs to be bigger */ assert(i <= I965_MAX_PROFILES); *num_profiles = i; return VA_STATUS_SUCCESS; } VAStatus i965_QueryConfigEntrypoints(VADriverContextP ctx, VAProfile profile, VAEntrypoint *entrypoint_list, /* out */ int *num_entrypoints) /* out */ { struct i965_driver_data * const i965 = i965_driver_data(ctx); int n = 0; switch (profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: if (HAS_MPEG2_DECODING(i965)) entrypoint_list[n++] = VAEntrypointVLD; if (HAS_MPEG2_ENCODING(i965)) entrypoint_list[n++] = VAEntrypointEncSlice; break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: if (HAS_H264_DECODING(i965)) entrypoint_list[n++] = VAEntrypointVLD; if (HAS_H264_ENCODING(i965)) entrypoint_list[n++] = VAEntrypointEncSlice; break; case VAProfileVC1Simple: case VAProfileVC1Main: case VAProfileVC1Advanced: if (HAS_VC1_DECODING(i965)) entrypoint_list[n++] = VAEntrypointVLD; break; case VAProfileNone: if (HAS_VPP(i965)) entrypoint_list[n++] = VAEntrypointVideoProc; break; case VAProfileJPEGBaseline: if (HAS_JPEG_DECODING(i965)) entrypoint_list[n++] = VAEntrypointVLD; break; case VAProfileVP8Version0_3: if (HAS_VP8_DECODING(i965)) entrypoint_list[n++] = VAEntrypointVLD; if (HAS_VP8_ENCODING(i965)) entrypoint_list[n++] = VAEntrypointEncSlice; default: break; } /* If the assert fails then I965_MAX_ENTRYPOINTS needs to be bigger */ assert(n <= I965_MAX_ENTRYPOINTS); *num_entrypoints = n; return n > 0 ? VA_STATUS_SUCCESS : VA_STATUS_ERROR_UNSUPPORTED_PROFILE; } VAStatus i965_GetConfigAttributes(VADriverContextP ctx, VAProfile profile, VAEntrypoint entrypoint, VAConfigAttrib *attrib_list, /* in/out */ int num_attribs) { int i; /* Other attributes don't seem to be defined */ /* What to do if we don't know the attribute? */ for (i = 0; i < num_attribs; i++) { switch (attrib_list[i].type) { case VAConfigAttribRTFormat: attrib_list[i].value = VA_RT_FORMAT_YUV420; break; case VAConfigAttribRateControl: if (entrypoint == VAEntrypointEncSlice) { attrib_list[i].value = VA_RC_CQP; if (profile != VAProfileMPEG2Main && profile != VAProfileMPEG2Simple) attrib_list[i].value |= VA_RC_CBR; break; } case VAConfigAttribEncPackedHeaders: if (entrypoint == VAEntrypointEncSlice) { attrib_list[i].value = VA_ENC_PACKED_HEADER_SEQUENCE | VA_ENC_PACKED_HEADER_PICTURE | VA_ENC_PACKED_HEADER_MISC; break; } case VAConfigAttribEncMaxRefFrames: if (entrypoint == VAEntrypointEncSlice) { attrib_list[i].value = (1 << 16) | (1 << 0); break; } default: /* Do nothing */ attrib_list[i].value = VA_ATTRIB_NOT_SUPPORTED; break; } } return VA_STATUS_SUCCESS; } static void i965_destroy_config(struct object_heap *heap, struct object_base *obj) { object_heap_free(heap, obj); } static VAStatus i965_update_attribute(struct object_config *obj_config, VAConfigAttrib *attrib) { int i; /* Check existing attrbiutes */ for (i = 0; i < obj_config->num_attribs; i++) { if (obj_config->attrib_list[i].type == attrib->type) { /* Update existing attribute */ obj_config->attrib_list[i].value = attrib->value; return VA_STATUS_SUCCESS; } } if (obj_config->num_attribs < I965_MAX_CONFIG_ATTRIBUTES) { i = obj_config->num_attribs; obj_config->attrib_list[i].type = attrib->type; obj_config->attrib_list[i].value = attrib->value; obj_config->num_attribs++; return VA_STATUS_SUCCESS; } return VA_STATUS_ERROR_MAX_NUM_EXCEEDED; } VAStatus i965_CreateConfig(VADriverContextP ctx, VAProfile profile, VAEntrypoint entrypoint, VAConfigAttrib *attrib_list, int num_attribs, VAConfigID *config_id) /* out */ { struct i965_driver_data * const i965 = i965_driver_data(ctx); struct object_config *obj_config; int configID; int i; VAStatus vaStatus; /* Validate profile & entrypoint */ switch (profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: if ((HAS_MPEG2_DECODING(i965) && VAEntrypointVLD == entrypoint) || (HAS_MPEG2_ENCODING(i965) && VAEntrypointEncSlice == entrypoint)) { vaStatus = VA_STATUS_SUCCESS; } else { vaStatus = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT; } break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: if ((HAS_H264_DECODING(i965) && VAEntrypointVLD == entrypoint) || (HAS_H264_ENCODING(i965) && VAEntrypointEncSlice == entrypoint)) { vaStatus = VA_STATUS_SUCCESS; } else { vaStatus = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT; } break; case VAProfileVC1Simple: case VAProfileVC1Main: case VAProfileVC1Advanced: if (HAS_VC1_DECODING(i965) && VAEntrypointVLD == entrypoint) { vaStatus = VA_STATUS_SUCCESS; } else { vaStatus = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT; } break; case VAProfileNone: if (HAS_VPP(i965) && VAEntrypointVideoProc == entrypoint) { vaStatus = VA_STATUS_SUCCESS; } else { vaStatus = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT; } break; case VAProfileJPEGBaseline: if (HAS_JPEG_DECODING(i965) && VAEntrypointVLD == entrypoint) { vaStatus = VA_STATUS_SUCCESS; } else { vaStatus = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT; } break; case VAProfileVP8Version0_3: if ((HAS_VP8_DECODING(i965) && VAEntrypointVLD == entrypoint) || (HAS_VP8_ENCODING(i965) && VAEntrypointEncSlice == entrypoint)) vaStatus = VA_STATUS_SUCCESS; else vaStatus = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT; break; default: vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE; break; } if (VA_STATUS_SUCCESS != vaStatus) { return vaStatus; } configID = NEW_CONFIG_ID(); obj_config = CONFIG(configID); if (NULL == obj_config) { vaStatus = VA_STATUS_ERROR_ALLOCATION_FAILED; return vaStatus; } obj_config->profile = profile; obj_config->entrypoint = entrypoint; obj_config->attrib_list[0].type = VAConfigAttribRTFormat; obj_config->attrib_list[0].value = VA_RT_FORMAT_YUV420; obj_config->num_attribs = 1; for(i = 0; i < num_attribs; i++) { vaStatus = i965_update_attribute(obj_config, &(attrib_list[i])); if (VA_STATUS_SUCCESS != vaStatus) { break; } } /* Error recovery */ if (VA_STATUS_SUCCESS != vaStatus) { i965_destroy_config(&i965->config_heap, (struct object_base *)obj_config); } else { *config_id = configID; } return vaStatus; } VAStatus i965_DestroyConfig(VADriverContextP ctx, VAConfigID config_id) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_config *obj_config = CONFIG(config_id); VAStatus vaStatus; if (NULL == obj_config) { vaStatus = VA_STATUS_ERROR_INVALID_CONFIG; return vaStatus; } i965_destroy_config(&i965->config_heap, (struct object_base *)obj_config); return VA_STATUS_SUCCESS; } VAStatus i965_QueryConfigAttributes(VADriverContextP ctx, VAConfigID config_id, VAProfile *profile, /* out */ VAEntrypoint *entrypoint, /* out */ VAConfigAttrib *attrib_list, /* out */ int *num_attribs) /* out */ { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_config *obj_config = CONFIG(config_id); VAStatus vaStatus = VA_STATUS_SUCCESS; int i; assert(obj_config); *profile = obj_config->profile; *entrypoint = obj_config->entrypoint; *num_attribs = obj_config->num_attribs; for(i = 0; i < obj_config->num_attribs; i++) { attrib_list[i] = obj_config->attrib_list[i]; } return vaStatus; } static void i965_destroy_surface(struct object_heap *heap, struct object_base *obj) { struct object_surface *obj_surface = (struct object_surface *)obj; dri_bo_unreference(obj_surface->bo); obj_surface->bo = NULL; if (obj_surface->free_private_data != NULL) { obj_surface->free_private_data(&obj_surface->private_data); obj_surface->private_data = NULL; } object_heap_free(heap, obj); } static VAStatus i965_surface_native_memory(VADriverContextP ctx, struct object_surface *obj_surface, int format, int expected_fourcc) { struct i965_driver_data *i965 = i965_driver_data(ctx); int tiling = HAS_TILED_SURFACE(i965); if (!expected_fourcc) return VA_STATUS_SUCCESS; // todo, should we disable tiling for 422 format? if (expected_fourcc == VA_FOURCC('I', '4', '2', '0') || expected_fourcc == VA_FOURCC('I', 'Y', 'U', 'V') || expected_fourcc == VA_FOURCC('Y', 'V', '1', '2')) tiling = 0; i965_check_alloc_surface_bo(ctx, obj_surface, tiling, expected_fourcc, get_sampling_from_fourcc(expected_fourcc)); return VA_STATUS_SUCCESS; } static VAStatus i965_suface_external_memory(VADriverContextP ctx, struct object_surface *obj_surface, int external_memory_type, VASurfaceAttribExternalBuffers *memory_attibute, int index) { struct i965_driver_data *i965 = i965_driver_data(ctx); if (!memory_attibute || !memory_attibute->buffers || index > memory_attibute->num_buffers) return VA_STATUS_ERROR_INVALID_PARAMETER; assert(obj_surface->orig_width == memory_attibute->width); assert(obj_surface->orig_height == memory_attibute->height); assert(memory_attibute->num_planes >= 1); obj_surface->fourcc = memory_attibute->pixel_format; obj_surface->width = memory_attibute->pitches[0]; obj_surface->size = memory_attibute->data_size; if (memory_attibute->num_planes == 1) obj_surface->height = memory_attibute->data_size / obj_surface->width; else obj_surface->height = memory_attibute->offsets[1] / obj_surface->width; obj_surface->x_cb_offset = 0; /* X offset is always 0 */ obj_surface->x_cr_offset = 0; switch (obj_surface->fourcc) { case VA_FOURCC('N', 'V', '1', '2'): assert(memory_attibute->num_planes == 2); assert(memory_attibute->pitches[0] == memory_attibute->pitches[1]); obj_surface->subsampling = SUBSAMPLE_YUV420; obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = obj_surface->height; obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height / 2; obj_surface->cb_cr_pitch = memory_attibute->pitches[1]; break; case VA_FOURCC('Y', 'V', '1', '2'): case VA_FOURCC('I', 'M', 'C', '1'): assert(memory_attibute->num_planes == 3); assert(memory_attibute->pitches[1] == memory_attibute->pitches[2]); obj_surface->subsampling = SUBSAMPLE_YUV420; obj_surface->y_cr_offset = obj_surface->height; obj_surface->y_cb_offset = memory_attibute->offsets[2] / obj_surface->width; obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height / 2; obj_surface->cb_cr_pitch = memory_attibute->pitches[1]; break; case VA_FOURCC('I', '4', '2', '0'): case VA_FOURCC('I', 'Y', 'U', 'V'): case VA_FOURCC('I', 'M', 'C', '3'): assert(memory_attibute->num_planes == 3); assert(memory_attibute->pitches[1] == memory_attibute->pitches[2]); obj_surface->subsampling = SUBSAMPLE_YUV420; obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = memory_attibute->offsets[2] / obj_surface->width; obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height / 2; obj_surface->cb_cr_pitch = memory_attibute->pitches[1]; break; case VA_FOURCC('Y', 'U', 'Y', '2'): case VA_FOURCC('U', 'Y', 'V', 'Y'): assert(memory_attibute->num_planes == 1); obj_surface->subsampling = SUBSAMPLE_YUV422H; obj_surface->y_cb_offset = 0; obj_surface->y_cr_offset = 0; obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height; obj_surface->cb_cr_pitch = memory_attibute->pitches[0]; break; case VA_FOURCC('R', 'G', 'B', 'A'): case VA_FOURCC('R', 'G', 'B', 'X'): case VA_FOURCC('B', 'G', 'R', 'A'): case VA_FOURCC('B', 'G', 'R', 'X'): assert(memory_attibute->num_planes == 1); obj_surface->subsampling = SUBSAMPLE_RGBX; obj_surface->y_cb_offset = 0; obj_surface->y_cr_offset = 0; obj_surface->cb_cr_width = 0; obj_surface->cb_cr_height = 0; obj_surface->cb_cr_pitch = 0; break; case VA_FOURCC('Y', '8', '0', '0'): /* monochrome surface */ assert(memory_attibute->num_planes == 1); obj_surface->subsampling = SUBSAMPLE_YUV400; obj_surface->y_cb_offset = 0; obj_surface->y_cr_offset = 0; obj_surface->cb_cr_width = 0; obj_surface->cb_cr_height = 0; obj_surface->cb_cr_pitch = 0; break; case VA_FOURCC('4', '1', '1', 'P'): assert(memory_attibute->num_planes == 3); assert(memory_attibute->pitches[1] == memory_attibute->pitches[2]); obj_surface->subsampling = SUBSAMPLE_YUV411; obj_surface->y_cb_offset = 0; obj_surface->y_cr_offset = 0; obj_surface->cb_cr_width = obj_surface->orig_width / 4; obj_surface->cb_cr_height = obj_surface->orig_height; obj_surface->cb_cr_pitch = memory_attibute->pitches[1]; break; case VA_FOURCC('4', '2', '2', 'H'): assert(memory_attibute->num_planes == 3); assert(memory_attibute->pitches[1] == memory_attibute->pitches[2]); obj_surface->subsampling = SUBSAMPLE_YUV422H; obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = memory_attibute->offsets[2] / obj_surface->width; obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height; obj_surface->cb_cr_pitch = memory_attibute->pitches[1]; break; case VA_FOURCC('4', '2', '2', 'V'): assert(memory_attibute->num_planes == 3); assert(memory_attibute->pitches[1] == memory_attibute->pitches[2]); obj_surface->subsampling = SUBSAMPLE_YUV422H; obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = memory_attibute->offsets[2] / obj_surface->width; obj_surface->cb_cr_width = obj_surface->orig_width; obj_surface->cb_cr_height = obj_surface->orig_height / 2; obj_surface->cb_cr_pitch = memory_attibute->pitches[1]; break; case VA_FOURCC('4', '4', '4', 'P'): assert(memory_attibute->num_planes == 3); assert(memory_attibute->pitches[1] == memory_attibute->pitches[2]); obj_surface->subsampling = SUBSAMPLE_YUV444; obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = memory_attibute->offsets[2] / obj_surface->width; obj_surface->cb_cr_width = obj_surface->orig_width; obj_surface->cb_cr_height = obj_surface->orig_height; obj_surface->cb_cr_pitch = memory_attibute->pitches[1]; break; default: return VA_STATUS_ERROR_INVALID_PARAMETER; } if (external_memory_type == I965_SURFACE_MEM_GEM_FLINK) obj_surface->bo = drm_intel_bo_gem_create_from_name(i965->intel.bufmgr, "gem flinked vaapi surface", memory_attibute->buffers[index]); else if (external_memory_type == I965_SURFACE_MEM_DRM_PRIME) obj_surface->bo = drm_intel_bo_gem_create_from_prime(i965->intel.bufmgr, memory_attibute->buffers[index], obj_surface->size); if (!obj_surface->bo) return VA_STATUS_ERROR_INVALID_PARAMETER; return VA_STATUS_SUCCESS; } static VAStatus i965_CreateSurfaces2( VADriverContextP ctx, unsigned int format, unsigned int width, unsigned int height, VASurfaceID *surfaces, unsigned int num_surfaces, VASurfaceAttrib *attrib_list, unsigned int num_attribs ) { struct i965_driver_data *i965 = i965_driver_data(ctx); int i,j; VAStatus vaStatus = VA_STATUS_SUCCESS; int expected_fourcc = 0; int memory_type = I965_SURFACE_MEM_NATIVE; /* native */ VASurfaceAttribExternalBuffers *memory_attibute = NULL; for (i = 0; i < num_attribs && attrib_list; i++) { if ((attrib_list[i].type == VASurfaceAttribPixelFormat) && (attrib_list[i].flags & VA_SURFACE_ATTRIB_SETTABLE)) { assert(attrib_list[i].value.type == VAGenericValueTypeInteger); expected_fourcc = attrib_list[i].value.value.i; } if ((attrib_list[i].type == VASurfaceAttribMemoryType) && (attrib_list[i].flags & VA_SURFACE_ATTRIB_SETTABLE)) { assert(attrib_list[i].value.type == VAGenericValueTypeInteger); if (attrib_list[i].value.value.i == VA_SURFACE_ATTRIB_MEM_TYPE_KERNEL_DRM) memory_type = I965_SURFACE_MEM_GEM_FLINK; /* flinked GEM handle */ else if (attrib_list[i].value.value.i == VA_SURFACE_ATTRIB_MEM_TYPE_DRM_PRIME) memory_type = I965_SURFACE_MEM_DRM_PRIME; /* drm prime fd */ } if ((attrib_list[i].type == VASurfaceAttribExternalBufferDescriptor) && (attrib_list[i].flags == VA_SURFACE_ATTRIB_SETTABLE)) { assert(attrib_list[i].value.type == VAGenericValueTypePointer); memory_attibute = (VASurfaceAttribExternalBuffers *)attrib_list[i].value.value.p; } } /* support 420 & 422 & RGB32 format, 422 and RGB32 are only used * for post-processing (including color conversion) */ if (VA_RT_FORMAT_YUV420 != format && VA_RT_FORMAT_YUV422 != format && VA_RT_FORMAT_YUV444 != format && VA_RT_FORMAT_YUV411 != format && VA_RT_FORMAT_YUV400 != format && VA_RT_FORMAT_RGB32 != format) { return VA_STATUS_ERROR_UNSUPPORTED_RT_FORMAT; } for (i = 0; i < num_surfaces; i++) { int surfaceID = NEW_SURFACE_ID(); struct object_surface *obj_surface = SURFACE(surfaceID); if (NULL == obj_surface) { vaStatus = VA_STATUS_ERROR_ALLOCATION_FAILED; break; } surfaces[i] = surfaceID; obj_surface->status = VASurfaceReady; obj_surface->orig_width = width; obj_surface->orig_height = height; obj_surface->subpic_render_idx = 0; for(j = 0; j < I965_MAX_SUBPIC_SUM; j++){ obj_surface->subpic[j] = VA_INVALID_ID; obj_surface->obj_subpic[j] = NULL; } obj_surface->width = ALIGN(width, 16); obj_surface->height = ALIGN(height, 16); obj_surface->flags = SURFACE_REFERENCED; obj_surface->fourcc = 0; obj_surface->bo = NULL; obj_surface->locked_image_id = VA_INVALID_ID; obj_surface->private_data = NULL; obj_surface->free_private_data = NULL; obj_surface->subsampling = SUBSAMPLE_YUV420; switch (memory_type) { case I965_SURFACE_MEM_NATIVE: i965_surface_native_memory(ctx, obj_surface, format, expected_fourcc); break; case I965_SURFACE_MEM_GEM_FLINK: case I965_SURFACE_MEM_DRM_PRIME: i965_suface_external_memory(ctx, obj_surface, memory_type, memory_attibute, i); break; } } /* Error recovery */ if (VA_STATUS_SUCCESS != vaStatus) { /* surfaces[i-1] was the last successful allocation */ for (; i--; ) { struct object_surface *obj_surface = SURFACE(surfaces[i]); surfaces[i] = VA_INVALID_SURFACE; assert(obj_surface); i965_destroy_surface(&i965->surface_heap, (struct object_base *)obj_surface); } } return vaStatus; } VAStatus i965_CreateSurfaces(VADriverContextP ctx, int width, int height, int format, int num_surfaces, VASurfaceID *surfaces) /* out */ { return i965_CreateSurfaces2(ctx, format, width, height, surfaces, num_surfaces, NULL, 0); } VAStatus i965_DestroySurfaces(VADriverContextP ctx, VASurfaceID *surface_list, int num_surfaces) { struct i965_driver_data *i965 = i965_driver_data(ctx); int i; for (i = num_surfaces; i--; ) { struct object_surface *obj_surface = SURFACE(surface_list[i]); assert(obj_surface); i965_destroy_surface(&i965->surface_heap, (struct object_base *)obj_surface); } return VA_STATUS_SUCCESS; } VAStatus i965_QueryImageFormats(VADriverContextP ctx, VAImageFormat *format_list, /* out */ int *num_formats) /* out */ { int n; for (n = 0; i965_image_formats_map[n].va_format.fourcc != 0; n++) { const i965_image_format_map_t * const m = &i965_image_formats_map[n]; if (format_list) format_list[n] = m->va_format; } if (num_formats) *num_formats = n; return VA_STATUS_SUCCESS; } /* * Guess the format when the usage of a VA surface is unknown * 1. Without a valid context: YV12 * 2. The current context is valid: * a) always NV12 on GEN6 and later * b) I420 for MPEG-2 and NV12 for other codec on GEN4 & GEN5 */ static void i965_guess_surface_format(VADriverContextP ctx, VASurfaceID surface, unsigned int *fourcc, unsigned int *is_tiled) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_context *obj_context = NULL; struct object_config *obj_config = NULL; *fourcc = VA_FOURCC('Y', 'V', '1', '2'); *is_tiled = 0; if (i965->current_context_id == VA_INVALID_ID) return; obj_context = CONTEXT(i965->current_context_id); if (!obj_context) return; obj_config = obj_context->obj_config; assert(obj_config); if (!obj_config) return; if (IS_GEN6(i965->intel.device_id) || IS_GEN7(i965->intel.device_id) || IS_GEN8(i965->intel.device_id)) { *fourcc = VA_FOURCC('N', 'V', '1', '2'); *is_tiled = 1; return; } switch (obj_config->profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: *fourcc = VA_FOURCC('I', '4', '2', '0'); *is_tiled = 0; break; default: *fourcc = VA_FOURCC('N', 'V', '1', '2'); *is_tiled = 0; break; } } VAStatus i965_QuerySubpictureFormats(VADriverContextP ctx, VAImageFormat *format_list, /* out */ unsigned int *flags, /* out */ unsigned int *num_formats) /* out */ { int n; for (n = 0; i965_subpic_formats_map[n].va_format.fourcc != 0; n++) { const i965_subpic_format_map_t * const m = &i965_subpic_formats_map[n]; if (format_list) format_list[n] = m->va_format; if (flags) flags[n] = m->va_flags; } if (num_formats) *num_formats = n; return VA_STATUS_SUCCESS; } static void i965_destroy_subpic(struct object_heap *heap, struct object_base *obj) { // struct object_subpic *obj_subpic = (struct object_subpic *)obj; object_heap_free(heap, obj); } VAStatus i965_CreateSubpicture(VADriverContextP ctx, VAImageID image, VASubpictureID *subpicture) /* out */ { struct i965_driver_data *i965 = i965_driver_data(ctx); VASubpictureID subpicID = NEW_SUBPIC_ID() struct object_subpic *obj_subpic = SUBPIC(subpicID); if (!obj_subpic) return VA_STATUS_ERROR_ALLOCATION_FAILED; struct object_image *obj_image = IMAGE(image); if (!obj_image) return VA_STATUS_ERROR_INVALID_IMAGE; const i965_subpic_format_map_t * const m = get_subpic_format(&obj_image->image.format); if (!m) return VA_STATUS_ERROR_UNKNOWN; /* XXX: VA_STATUS_ERROR_UNSUPPORTED_FORMAT? */ *subpicture = subpicID; obj_subpic->image = image; obj_subpic->obj_image = obj_image; obj_subpic->format = m->format; obj_subpic->width = obj_image->image.width; obj_subpic->height = obj_image->image.height; obj_subpic->pitch = obj_image->image.pitches[0]; obj_subpic->bo = obj_image->bo; obj_subpic->global_alpha = 1.0; return VA_STATUS_SUCCESS; } VAStatus i965_DestroySubpicture(VADriverContextP ctx, VASubpictureID subpicture) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_subpic *obj_subpic = SUBPIC(subpicture); if (!obj_subpic) return VA_STATUS_ERROR_INVALID_SUBPICTURE; assert(obj_subpic->obj_image); i965_destroy_subpic(&i965->subpic_heap, (struct object_base *)obj_subpic); return VA_STATUS_SUCCESS; } VAStatus i965_SetSubpictureImage(VADriverContextP ctx, VASubpictureID subpicture, VAImageID image) { /* TODO */ return VA_STATUS_ERROR_UNIMPLEMENTED; } VAStatus i965_SetSubpictureChromakey(VADriverContextP ctx, VASubpictureID subpicture, unsigned int chromakey_min, unsigned int chromakey_max, unsigned int chromakey_mask) { /* TODO */ return VA_STATUS_ERROR_UNIMPLEMENTED; } VAStatus i965_SetSubpictureGlobalAlpha(VADriverContextP ctx, VASubpictureID subpicture, float global_alpha) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_subpic *obj_subpic = SUBPIC(subpicture); if(global_alpha > 1.0 || global_alpha < 0.0){ return VA_STATUS_ERROR_INVALID_PARAMETER; } if (!obj_subpic) return VA_STATUS_ERROR_INVALID_SUBPICTURE; obj_subpic->global_alpha = global_alpha; return VA_STATUS_SUCCESS; } VAStatus i965_AssociateSubpicture(VADriverContextP ctx, VASubpictureID subpicture, VASurfaceID *target_surfaces, int num_surfaces, short src_x, /* upper left offset in subpicture */ short src_y, unsigned short src_width, unsigned short src_height, short dest_x, /* upper left offset in surface */ short dest_y, unsigned short dest_width, unsigned short dest_height, /* * whether to enable chroma-keying or global-alpha * see VA_SUBPICTURE_XXX values */ unsigned int flags) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_subpic *obj_subpic = SUBPIC(subpicture); int i, j; if (!obj_subpic) return VA_STATUS_ERROR_INVALID_SUBPICTURE; assert(obj_subpic->obj_image); obj_subpic->src_rect.x = src_x; obj_subpic->src_rect.y = src_y; obj_subpic->src_rect.width = src_width; obj_subpic->src_rect.height = src_height; obj_subpic->dst_rect.x = dest_x; obj_subpic->dst_rect.y = dest_y; obj_subpic->dst_rect.width = dest_width; obj_subpic->dst_rect.height = dest_height; obj_subpic->flags = flags; for (i = 0; i < num_surfaces; i++) { struct object_surface *obj_surface = SURFACE(target_surfaces[i]); if (!obj_surface) return VA_STATUS_ERROR_INVALID_SURFACE; for(j = 0; j < I965_MAX_SUBPIC_SUM; j ++){ if(obj_surface->subpic[j] == VA_INVALID_ID){ assert(obj_surface->obj_subpic[j] == NULL); obj_surface->subpic[j] = subpicture; obj_surface->obj_subpic[j] = obj_subpic; break; } } if(j == I965_MAX_SUBPIC_SUM){ return VA_STATUS_ERROR_MAX_NUM_EXCEEDED; } } return VA_STATUS_SUCCESS; } VAStatus i965_DeassociateSubpicture(VADriverContextP ctx, VASubpictureID subpicture, VASurfaceID *target_surfaces, int num_surfaces) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_subpic *obj_subpic = SUBPIC(subpicture); int i, j; if (!obj_subpic) return VA_STATUS_ERROR_INVALID_SUBPICTURE; for (i = 0; i < num_surfaces; i++) { struct object_surface *obj_surface = SURFACE(target_surfaces[i]); if (!obj_surface) return VA_STATUS_ERROR_INVALID_SURFACE; for(j = 0; j < I965_MAX_SUBPIC_SUM; j ++){ if (obj_surface->subpic[j] == subpicture) { assert(obj_surface->obj_subpic[j] == obj_subpic); obj_surface->subpic[j] = VA_INVALID_ID; obj_surface->obj_subpic[j] = NULL; break; } } if(j == I965_MAX_SUBPIC_SUM){ return VA_STATUS_ERROR_MAX_NUM_EXCEEDED; } } return VA_STATUS_SUCCESS; } void i965_reference_buffer_store(struct buffer_store **ptr, struct buffer_store *buffer_store) { assert(*ptr == NULL); if (buffer_store) { buffer_store->ref_count++; *ptr = buffer_store; } } void i965_release_buffer_store(struct buffer_store **ptr) { struct buffer_store *buffer_store = *ptr; if (buffer_store == NULL) return; assert(buffer_store->bo || buffer_store->buffer); assert(!(buffer_store->bo && buffer_store->buffer)); buffer_store->ref_count--; if (buffer_store->ref_count == 0) { dri_bo_unreference(buffer_store->bo); free(buffer_store->buffer); buffer_store->bo = NULL; buffer_store->buffer = NULL; free(buffer_store); } *ptr = NULL; } static void i965_destroy_context(struct object_heap *heap, struct object_base *obj) { struct object_context *obj_context = (struct object_context *)obj; int i; if (obj_context->hw_context) { obj_context->hw_context->destroy(obj_context->hw_context); obj_context->hw_context = NULL; } if (obj_context->codec_type == CODEC_PROC) { i965_release_buffer_store(&obj_context->codec_state.proc.pipeline_param); } else if (obj_context->codec_type == CODEC_ENC) { assert(obj_context->codec_state.encode.num_slice_params <= obj_context->codec_state.encode.max_slice_params); i965_release_buffer_store(&obj_context->codec_state.encode.pic_param); i965_release_buffer_store(&obj_context->codec_state.encode.seq_param); for (i = 0; i < obj_context->codec_state.encode.num_slice_params; i++) i965_release_buffer_store(&obj_context->codec_state.encode.slice_params[i]); free(obj_context->codec_state.encode.slice_params); assert(obj_context->codec_state.encode.num_slice_params_ext <= obj_context->codec_state.encode.max_slice_params_ext); i965_release_buffer_store(&obj_context->codec_state.encode.pic_param_ext); i965_release_buffer_store(&obj_context->codec_state.encode.seq_param_ext); for (i = 0; i < ARRAY_ELEMS(obj_context->codec_state.encode.packed_header_param); i++) i965_release_buffer_store(&obj_context->codec_state.encode.packed_header_param[i]); for (i = 0; i < ARRAY_ELEMS(obj_context->codec_state.encode.packed_header_data); i++) i965_release_buffer_store(&obj_context->codec_state.encode.packed_header_data[i]); for (i = 0; i < ARRAY_ELEMS(obj_context->codec_state.encode.misc_param); i++) i965_release_buffer_store(&obj_context->codec_state.encode.misc_param[i]); for (i = 0; i < obj_context->codec_state.encode.num_slice_params_ext; i++) i965_release_buffer_store(&obj_context->codec_state.encode.slice_params_ext[i]); free(obj_context->codec_state.encode.slice_params_ext); } else { assert(obj_context->codec_state.decode.num_slice_params <= obj_context->codec_state.decode.max_slice_params); assert(obj_context->codec_state.decode.num_slice_datas <= obj_context->codec_state.decode.max_slice_datas); i965_release_buffer_store(&obj_context->codec_state.decode.pic_param); i965_release_buffer_store(&obj_context->codec_state.decode.iq_matrix); i965_release_buffer_store(&obj_context->codec_state.decode.bit_plane); for (i = 0; i < obj_context->codec_state.decode.num_slice_params; i++) i965_release_buffer_store(&obj_context->codec_state.decode.slice_params[i]); for (i = 0; i < obj_context->codec_state.decode.num_slice_datas; i++) i965_release_buffer_store(&obj_context->codec_state.decode.slice_datas[i]); free(obj_context->codec_state.decode.slice_params); free(obj_context->codec_state.decode.slice_datas); } free(obj_context->render_targets); object_heap_free(heap, obj); } VAStatus i965_CreateContext(VADriverContextP ctx, VAConfigID config_id, int picture_width, int picture_height, int flag, VASurfaceID *render_targets, int num_render_targets, VAContextID *context) /* out */ { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct object_config *obj_config = CONFIG(config_id); struct object_context *obj_context = NULL; VAStatus vaStatus = VA_STATUS_SUCCESS; int contextID; int i; if (NULL == obj_config) { vaStatus = VA_STATUS_ERROR_INVALID_CONFIG; return vaStatus; } if (picture_width > i965->codec_info->max_width || picture_height > i965->codec_info->max_height) { vaStatus = VA_STATUS_ERROR_RESOLUTION_NOT_SUPPORTED; return vaStatus; } /* Validate flag */ /* Validate picture dimensions */ contextID = NEW_CONTEXT_ID(); obj_context = CONTEXT(contextID); if (NULL == obj_context) { vaStatus = VA_STATUS_ERROR_ALLOCATION_FAILED; return vaStatus; } render_state->inited = 1; switch (obj_config->profile) { case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: if (!HAS_H264_DECODING(i965) && !HAS_H264_ENCODING(i965)) return VA_STATUS_ERROR_UNSUPPORTED_PROFILE; render_state->interleaved_uv = 1; break; default: render_state->interleaved_uv = !!(IS_GEN6(i965->intel.device_id) || IS_GEN7(i965->intel.device_id) || IS_GEN8(i965->intel.device_id)); break; } *context = contextID; obj_context->flags = flag; obj_context->context_id = contextID; obj_context->obj_config = obj_config; obj_context->picture_width = picture_width; obj_context->picture_height = picture_height; obj_context->num_render_targets = num_render_targets; obj_context->render_targets = (VASurfaceID *)calloc(num_render_targets, sizeof(VASurfaceID)); obj_context->hw_context = NULL; for(i = 0; i < num_render_targets; i++) { if (NULL == SURFACE(render_targets[i])) { vaStatus = VA_STATUS_ERROR_INVALID_SURFACE; break; } obj_context->render_targets[i] = render_targets[i]; } if (VA_STATUS_SUCCESS == vaStatus) { if (VAEntrypointVideoProc == obj_config->entrypoint) { obj_context->codec_type = CODEC_PROC; memset(&obj_context->codec_state.proc, 0, sizeof(obj_context->codec_state.proc)); obj_context->codec_state.proc.current_render_target = VA_INVALID_ID; assert(i965->codec_info->proc_hw_context_init); obj_context->hw_context = i965->codec_info->proc_hw_context_init(ctx, obj_config); } else if (VAEntrypointEncSlice == obj_config->entrypoint) { /*encode routin only*/ obj_context->codec_type = CODEC_ENC; memset(&obj_context->codec_state.encode, 0, sizeof(obj_context->codec_state.encode)); obj_context->codec_state.encode.current_render_target = VA_INVALID_ID; obj_context->codec_state.encode.max_slice_params = NUM_SLICES; obj_context->codec_state.encode.slice_params = calloc(obj_context->codec_state.encode.max_slice_params, sizeof(*obj_context->codec_state.encode.slice_params)); assert(i965->codec_info->enc_hw_context_init); obj_context->hw_context = i965->codec_info->enc_hw_context_init(ctx, obj_config); } else { obj_context->codec_type = CODEC_DEC; memset(&obj_context->codec_state.decode, 0, sizeof(obj_context->codec_state.decode)); obj_context->codec_state.decode.current_render_target = -1; obj_context->codec_state.decode.max_slice_params = NUM_SLICES; obj_context->codec_state.decode.max_slice_datas = NUM_SLICES; obj_context->codec_state.decode.slice_params = calloc(obj_context->codec_state.decode.max_slice_params, sizeof(*obj_context->codec_state.decode.slice_params)); obj_context->codec_state.decode.slice_datas = calloc(obj_context->codec_state.decode.max_slice_datas, sizeof(*obj_context->codec_state.decode.slice_datas)); assert(i965->codec_info->dec_hw_context_init); obj_context->hw_context = i965->codec_info->dec_hw_context_init(ctx, obj_config); } } /* Error recovery */ if (VA_STATUS_SUCCESS != vaStatus) { i965_destroy_context(&i965->context_heap, (struct object_base *)obj_context); } i965->current_context_id = contextID; return vaStatus; } VAStatus i965_DestroyContext(VADriverContextP ctx, VAContextID context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_context *obj_context = CONTEXT(context); assert(obj_context); if (i965->current_context_id == context) i965->current_context_id = VA_INVALID_ID; i965_destroy_context(&i965->context_heap, (struct object_base *)obj_context); return VA_STATUS_SUCCESS; } static void i965_destroy_buffer(struct object_heap *heap, struct object_base *obj) { struct object_buffer *obj_buffer = (struct object_buffer *)obj; assert(obj_buffer->buffer_store); i965_release_buffer_store(&obj_buffer->buffer_store); object_heap_free(heap, obj); } static VAStatus i965_create_buffer_internal(VADriverContextP ctx, VAContextID context, VABufferType type, unsigned int size, unsigned int num_elements, void *data, dri_bo *store_bo, VABufferID *buf_id) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_buffer *obj_buffer = NULL; struct buffer_store *buffer_store = NULL; int bufferID; /* Validate type */ switch (type) { case VAPictureParameterBufferType: case VAIQMatrixBufferType: case VAQMatrixBufferType: case VABitPlaneBufferType: case VASliceGroupMapBufferType: case VASliceParameterBufferType: case VASliceDataBufferType: case VAMacroblockParameterBufferType: case VAResidualDataBufferType: case VADeblockingParameterBufferType: case VAImageBufferType: case VAEncCodedBufferType: case VAEncSequenceParameterBufferType: case VAEncPictureParameterBufferType: case VAEncSliceParameterBufferType: case VAEncPackedHeaderParameterBufferType: case VAEncPackedHeaderDataBufferType: case VAEncMiscParameterBufferType: case VAProcPipelineParameterBufferType: case VAProcFilterParameterBufferType: case VAHuffmanTableBufferType: case VAProbabilityBufferType: /* Ok */ break; default: return VA_STATUS_ERROR_UNSUPPORTED_BUFFERTYPE; } bufferID = NEW_BUFFER_ID(); obj_buffer = BUFFER(bufferID); if (NULL == obj_buffer) { return VA_STATUS_ERROR_ALLOCATION_FAILED; } if (type == VAEncCodedBufferType) { size += I965_CODEDBUFFER_HEADER_SIZE; size += 0x1000; /* for upper bound check */ } obj_buffer->max_num_elements = num_elements; obj_buffer->num_elements = num_elements; obj_buffer->size_element = size; obj_buffer->type = type; obj_buffer->buffer_store = NULL; buffer_store = calloc(1, sizeof(struct buffer_store)); assert(buffer_store); buffer_store->ref_count = 1; if (store_bo != NULL) { buffer_store->bo = store_bo; dri_bo_reference(buffer_store->bo); if (data) dri_bo_subdata(buffer_store->bo, 0, size * num_elements, data); } else if (type == VASliceDataBufferType || type == VAImageBufferType || type == VAEncCodedBufferType || type == VAProbabilityBufferType) { buffer_store->bo = dri_bo_alloc(i965->intel.bufmgr, "Buffer", size * num_elements, 64); assert(buffer_store->bo); if (type == VAEncCodedBufferType) { struct i965_coded_buffer_segment *coded_buffer_segment; dri_bo_map(buffer_store->bo, 1); coded_buffer_segment = (struct i965_coded_buffer_segment *)buffer_store->bo->virtual; coded_buffer_segment->base.size = size - I965_CODEDBUFFER_HEADER_SIZE; coded_buffer_segment->base.bit_offset = 0; coded_buffer_segment->base.status = 0; coded_buffer_segment->base.buf = NULL; coded_buffer_segment->base.next = NULL; coded_buffer_segment->mapped = 0; coded_buffer_segment->codec = 0; dri_bo_unmap(buffer_store->bo); } else if (data) { dri_bo_subdata(buffer_store->bo, 0, size * num_elements, data); } } else { int msize = size; if (type == VAEncPackedHeaderDataBufferType) { msize = ALIGN(size, 4); } buffer_store->buffer = malloc(msize * num_elements); assert(buffer_store->buffer); if (data) memcpy(buffer_store->buffer, data, size * num_elements); } buffer_store->num_elements = obj_buffer->num_elements; i965_reference_buffer_store(&obj_buffer->buffer_store, buffer_store); i965_release_buffer_store(&buffer_store); *buf_id = bufferID; return VA_STATUS_SUCCESS; } VAStatus i965_CreateBuffer(VADriverContextP ctx, VAContextID context, /* in */ VABufferType type, /* in */ unsigned int size, /* in */ unsigned int num_elements, /* in */ void *data, /* in */ VABufferID *buf_id) /* out */ { return i965_create_buffer_internal(ctx, context, type, size, num_elements, data, NULL, buf_id); } VAStatus i965_BufferSetNumElements(VADriverContextP ctx, VABufferID buf_id, /* in */ unsigned int num_elements) /* in */ { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_buffer *obj_buffer = BUFFER(buf_id); VAStatus vaStatus = VA_STATUS_SUCCESS; assert(obj_buffer); if (!obj_buffer) return VA_STATUS_ERROR_INVALID_BUFFER; if ((num_elements < 0) || (num_elements > obj_buffer->max_num_elements)) { vaStatus = VA_STATUS_ERROR_MAX_NUM_EXCEEDED; } else { obj_buffer->num_elements = num_elements; if (obj_buffer->buffer_store != NULL) { obj_buffer->buffer_store->num_elements = num_elements; } } return vaStatus; } VAStatus i965_MapBuffer(VADriverContextP ctx, VABufferID buf_id, /* in */ void **pbuf) /* out */ { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_buffer *obj_buffer = BUFFER(buf_id); VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN; assert(obj_buffer && obj_buffer->buffer_store); assert(obj_buffer->buffer_store->bo || obj_buffer->buffer_store->buffer); assert(!(obj_buffer->buffer_store->bo && obj_buffer->buffer_store->buffer)); if (!obj_buffer || !obj_buffer->buffer_store) return VA_STATUS_ERROR_INVALID_BUFFER; if (NULL != obj_buffer->buffer_store->bo) { unsigned int tiling, swizzle; dri_bo_get_tiling(obj_buffer->buffer_store->bo, &tiling, &swizzle); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_map_gtt(obj_buffer->buffer_store->bo); else dri_bo_map(obj_buffer->buffer_store->bo, 1); assert(obj_buffer->buffer_store->bo->virtual); *pbuf = obj_buffer->buffer_store->bo->virtual; if (obj_buffer->type == VAEncCodedBufferType) { int i; unsigned char *buffer = NULL; struct i965_coded_buffer_segment *coded_buffer_segment = (struct i965_coded_buffer_segment *)(obj_buffer->buffer_store->bo->virtual); if (!coded_buffer_segment->mapped) { unsigned char delimiter0, delimiter1, delimiter2, delimiter3, delimiter4; coded_buffer_segment->base.buf = buffer = (unsigned char *)(obj_buffer->buffer_store->bo->virtual) + I965_CODEDBUFFER_HEADER_SIZE; if (coded_buffer_segment->codec == CODEC_H264) { delimiter0 = H264_DELIMITER0; delimiter1 = H264_DELIMITER1; delimiter2 = H264_DELIMITER2; delimiter3 = H264_DELIMITER3; delimiter4 = H264_DELIMITER4; } else if (coded_buffer_segment->codec == CODEC_MPEG2) { delimiter0 = MPEG2_DELIMITER0; delimiter1 = MPEG2_DELIMITER1; delimiter2 = MPEG2_DELIMITER2; delimiter3 = MPEG2_DELIMITER3; delimiter4 = MPEG2_DELIMITER4; } else { assert(0); } for (i = 0; i < obj_buffer->size_element - I965_CODEDBUFFER_HEADER_SIZE - 3 - 0x1000; i++) { if ((buffer[i] == delimiter0) && (buffer[i + 1] == delimiter1) && (buffer[i + 2] == delimiter2) && (buffer[i + 3] == delimiter3) && (buffer[i + 4] == delimiter4)) break; } if (i == obj_buffer->size_element - I965_CODEDBUFFER_HEADER_SIZE - 3 - 0x1000) { coded_buffer_segment->base.status |= VA_CODED_BUF_STATUS_SLICE_OVERFLOW_MASK; } coded_buffer_segment->base.size = i; coded_buffer_segment->mapped = 1; } else { assert(coded_buffer_segment->base.buf); } } vaStatus = VA_STATUS_SUCCESS; } else if (NULL != obj_buffer->buffer_store->buffer) { *pbuf = obj_buffer->buffer_store->buffer; vaStatus = VA_STATUS_SUCCESS; } return vaStatus; } VAStatus i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_buffer *obj_buffer = BUFFER(buf_id); VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN; if ((buf_id & OBJECT_HEAP_OFFSET_MASK) != BUFFER_ID_OFFSET) return VA_STATUS_ERROR_INVALID_BUFFER; assert(obj_buffer && obj_buffer->buffer_store); assert(obj_buffer->buffer_store->bo || obj_buffer->buffer_store->buffer); assert(!(obj_buffer->buffer_store->bo && obj_buffer->buffer_store->buffer)); if (!obj_buffer || !obj_buffer->buffer_store) return VA_STATUS_ERROR_INVALID_BUFFER; if (NULL != obj_buffer->buffer_store->bo) { unsigned int tiling, swizzle; dri_bo_get_tiling(obj_buffer->buffer_store->bo, &tiling, &swizzle); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_unmap_gtt(obj_buffer->buffer_store->bo); else dri_bo_unmap(obj_buffer->buffer_store->bo); vaStatus = VA_STATUS_SUCCESS; } else if (NULL != obj_buffer->buffer_store->buffer) { /* Do nothing */ vaStatus = VA_STATUS_SUCCESS; } return vaStatus; } VAStatus i965_DestroyBuffer(VADriverContextP ctx, VABufferID buffer_id) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_buffer *obj_buffer = BUFFER(buffer_id); assert(obj_buffer); if (!obj_buffer) return VA_STATUS_ERROR_INVALID_BUFFER; i965_destroy_buffer(&i965->buffer_heap, (struct object_base *)obj_buffer); return VA_STATUS_SUCCESS; } VAStatus i965_BeginPicture(VADriverContextP ctx, VAContextID context, VASurfaceID render_target) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_context *obj_context = CONTEXT(context); struct object_surface *obj_surface = SURFACE(render_target); struct object_config *obj_config; VAStatus vaStatus; int i; assert(obj_context); if (!obj_context) return VA_STATUS_ERROR_INVALID_CONTEXT; assert(obj_surface); if (!obj_surface) return VA_STATUS_ERROR_INVALID_SURFACE; obj_config = obj_context->obj_config; assert(obj_config); switch (obj_config->profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: vaStatus = VA_STATUS_SUCCESS; break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: vaStatus = VA_STATUS_SUCCESS; break; case VAProfileVC1Simple: case VAProfileVC1Main: case VAProfileVC1Advanced: vaStatus = VA_STATUS_SUCCESS; break; case VAProfileJPEGBaseline: vaStatus = VA_STATUS_SUCCESS; break; case VAProfileNone: vaStatus = VA_STATUS_SUCCESS; break; case VAProfileVP8Version0_3: vaStatus = VA_STATUS_SUCCESS; break; default: assert(0); vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE; break; } if (obj_context->codec_type == CODEC_PROC) { obj_context->codec_state.proc.current_render_target = render_target; } else if (obj_context->codec_type == CODEC_ENC) { i965_release_buffer_store(&obj_context->codec_state.encode.pic_param); for (i = 0; i < obj_context->codec_state.encode.num_slice_params; i++) { i965_release_buffer_store(&obj_context->codec_state.encode.slice_params[i]); } obj_context->codec_state.encode.num_slice_params = 0; /* ext */ i965_release_buffer_store(&obj_context->codec_state.encode.pic_param_ext); for (i = 0; i < ARRAY_ELEMS(obj_context->codec_state.encode.packed_header_param); i++) i965_release_buffer_store(&obj_context->codec_state.encode.packed_header_param[i]); for (i = 0; i < ARRAY_ELEMS(obj_context->codec_state.encode.packed_header_data); i++) i965_release_buffer_store(&obj_context->codec_state.encode.packed_header_data[i]); for (i = 0; i < obj_context->codec_state.encode.num_slice_params_ext; i++) i965_release_buffer_store(&obj_context->codec_state.encode.slice_params_ext[i]); obj_context->codec_state.encode.num_slice_params_ext = 0; obj_context->codec_state.encode.current_render_target = render_target; /*This is input new frame*/ obj_context->codec_state.encode.last_packed_header_type = 0; } else { obj_context->codec_state.decode.current_render_target = render_target; i965_release_buffer_store(&obj_context->codec_state.decode.pic_param); i965_release_buffer_store(&obj_context->codec_state.decode.iq_matrix); i965_release_buffer_store(&obj_context->codec_state.decode.bit_plane); i965_release_buffer_store(&obj_context->codec_state.decode.huffman_table); for (i = 0; i < obj_context->codec_state.decode.num_slice_params; i++) { i965_release_buffer_store(&obj_context->codec_state.decode.slice_params[i]); i965_release_buffer_store(&obj_context->codec_state.decode.slice_datas[i]); } obj_context->codec_state.decode.num_slice_params = 0; obj_context->codec_state.decode.num_slice_datas = 0; } return vaStatus; } #define I965_RENDER_BUFFER(category, name) i965_render_##category##_##name##_buffer(ctx, obj_context, obj_buffer) #define DEF_RENDER_SINGLE_BUFFER_FUNC(category, name, member) \ static VAStatus \ i965_render_##category##_##name##_buffer(VADriverContextP ctx, \ struct object_context *obj_context, \ struct object_buffer *obj_buffer) \ { \ struct category##_state *category = &obj_context->codec_state.category; \ i965_release_buffer_store(&category->member); \ i965_reference_buffer_store(&category->member, obj_buffer->buffer_store); \ return VA_STATUS_SUCCESS; \ } #define DEF_RENDER_MULTI_BUFFER_FUNC(category, name, member) \ static VAStatus \ i965_render_##category##_##name##_buffer(VADriverContextP ctx, \ struct object_context *obj_context, \ struct object_buffer *obj_buffer) \ { \ struct category##_state *category = &obj_context->codec_state.category; \ if (category->num_##member == category->max_##member) { \ category->member = realloc(category->member, (category->max_##member + NUM_SLICES) * sizeof(*category->member)); \ memset(category->member + category->max_##member, 0, NUM_SLICES * sizeof(*category->member)); \ category->max_##member += NUM_SLICES; \ } \ i965_release_buffer_store(&category->member[category->num_##member]); \ i965_reference_buffer_store(&category->member[category->num_##member], obj_buffer->buffer_store); \ category->num_##member++; \ return VA_STATUS_SUCCESS; \ } #define I965_RENDER_DECODE_BUFFER(name) I965_RENDER_BUFFER(decode, name) #define DEF_RENDER_DECODE_SINGLE_BUFFER_FUNC(name, member) DEF_RENDER_SINGLE_BUFFER_FUNC(decode, name, member) DEF_RENDER_DECODE_SINGLE_BUFFER_FUNC(picture_parameter, pic_param) DEF_RENDER_DECODE_SINGLE_BUFFER_FUNC(iq_matrix, iq_matrix) DEF_RENDER_DECODE_SINGLE_BUFFER_FUNC(bit_plane, bit_plane) DEF_RENDER_DECODE_SINGLE_BUFFER_FUNC(huffman_table, huffman_table) DEF_RENDER_DECODE_SINGLE_BUFFER_FUNC(probability_data, probability_data) #define DEF_RENDER_DECODE_MULTI_BUFFER_FUNC(name, member) DEF_RENDER_MULTI_BUFFER_FUNC(decode, name, member) DEF_RENDER_DECODE_MULTI_BUFFER_FUNC(slice_parameter, slice_params) DEF_RENDER_DECODE_MULTI_BUFFER_FUNC(slice_data, slice_datas) static VAStatus i965_decoder_render_picture(VADriverContextP ctx, VAContextID context, VABufferID *buffers, int num_buffers) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_context *obj_context = CONTEXT(context); VAStatus vaStatus = VA_STATUS_SUCCESS; int i; assert(obj_context); if (!obj_context) return VA_STATUS_ERROR_INVALID_CONTEXT; for (i = 0; i < num_buffers && vaStatus == VA_STATUS_SUCCESS; i++) { struct object_buffer *obj_buffer = BUFFER(buffers[i]); if (!obj_buffer) return VA_STATUS_ERROR_INVALID_BUFFER; switch (obj_buffer->type) { case VAPictureParameterBufferType: vaStatus = I965_RENDER_DECODE_BUFFER(picture_parameter); break; case VAIQMatrixBufferType: vaStatus = I965_RENDER_DECODE_BUFFER(iq_matrix); break; case VABitPlaneBufferType: vaStatus = I965_RENDER_DECODE_BUFFER(bit_plane); break; case VASliceParameterBufferType: vaStatus = I965_RENDER_DECODE_BUFFER(slice_parameter); break; case VASliceDataBufferType: vaStatus = I965_RENDER_DECODE_BUFFER(slice_data); break; case VAHuffmanTableBufferType: vaStatus = I965_RENDER_DECODE_BUFFER(huffman_table); break; case VAProbabilityBufferType: vaStatus = I965_RENDER_DECODE_BUFFER(probability_data); break; default: vaStatus = VA_STATUS_ERROR_UNSUPPORTED_BUFFERTYPE; break; } } return vaStatus; } #define I965_RENDER_ENCODE_BUFFER(name) I965_RENDER_BUFFER(encode, name) #define DEF_RENDER_ENCODE_SINGLE_BUFFER_FUNC(name, member) DEF_RENDER_SINGLE_BUFFER_FUNC(encode, name, member) // DEF_RENDER_ENCODE_SINGLE_BUFFER_FUNC(sequence_parameter, seq_param) // DEF_RENDER_ENCODE_SINGLE_BUFFER_FUNC(picture_parameter, pic_param) // DEF_RENDER_ENCODE_SINGLE_BUFFER_FUNC(picture_control, pic_control) DEF_RENDER_ENCODE_SINGLE_BUFFER_FUNC(qmatrix, q_matrix) DEF_RENDER_ENCODE_SINGLE_BUFFER_FUNC(iqmatrix, iq_matrix) /* extended buffer */ DEF_RENDER_ENCODE_SINGLE_BUFFER_FUNC(sequence_parameter_ext, seq_param_ext) DEF_RENDER_ENCODE_SINGLE_BUFFER_FUNC(picture_parameter_ext, pic_param_ext) #define DEF_RENDER_ENCODE_MULTI_BUFFER_FUNC(name, member) DEF_RENDER_MULTI_BUFFER_FUNC(encode, name, member) // DEF_RENDER_ENCODE_MULTI_BUFFER_FUNC(slice_parameter, slice_params) DEF_RENDER_ENCODE_MULTI_BUFFER_FUNC(slice_parameter_ext, slice_params_ext) static VAStatus i965_encoder_render_packed_header_parameter_buffer(VADriverContextP ctx, struct object_context *obj_context, struct object_buffer *obj_buffer, int type_index) { struct encode_state *encode = &obj_context->codec_state.encode; assert(obj_buffer->buffer_store->bo == NULL); assert(obj_buffer->buffer_store->buffer); i965_release_buffer_store(&encode->packed_header_param[type_index]); i965_reference_buffer_store(&encode->packed_header_param[type_index], obj_buffer->buffer_store); return VA_STATUS_SUCCESS; } static VAStatus i965_encoder_render_packed_header_data_buffer(VADriverContextP ctx, struct object_context *obj_context, struct object_buffer *obj_buffer, int type_index) { struct encode_state *encode = &obj_context->codec_state.encode; assert(obj_buffer->buffer_store->bo == NULL); assert(obj_buffer->buffer_store->buffer); i965_release_buffer_store(&encode->packed_header_data[type_index]); i965_reference_buffer_store(&encode->packed_header_data[type_index], obj_buffer->buffer_store); return VA_STATUS_SUCCESS; } static VAStatus i965_encoder_render_misc_parameter_buffer(VADriverContextP ctx, struct object_context *obj_context, struct object_buffer *obj_buffer) { struct encode_state *encode = &obj_context->codec_state.encode; VAEncMiscParameterBuffer *param = NULL; assert(obj_buffer->buffer_store->bo == NULL); assert(obj_buffer->buffer_store->buffer); param = (VAEncMiscParameterBuffer *)obj_buffer->buffer_store->buffer; if (param->type > ARRAY_ELEMS(encode->misc_param)) return VA_STATUS_ERROR_INVALID_PARAMETER; i965_release_buffer_store(&encode->misc_param[param->type]); i965_reference_buffer_store(&encode->misc_param[param->type], obj_buffer->buffer_store); return VA_STATUS_SUCCESS; } static VAStatus i965_encoder_render_picture(VADriverContextP ctx, VAContextID context, VABufferID *buffers, int num_buffers) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_context *obj_context = CONTEXT(context); VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN; int i; assert(obj_context); if (!obj_context) return VA_STATUS_ERROR_INVALID_CONTEXT; for (i = 0; i < num_buffers; i++) { struct object_buffer *obj_buffer = BUFFER(buffers[i]); if (!obj_buffer) return VA_STATUS_ERROR_INVALID_BUFFER; switch (obj_buffer->type) { case VAQMatrixBufferType: vaStatus = I965_RENDER_ENCODE_BUFFER(qmatrix); break; case VAIQMatrixBufferType: vaStatus = I965_RENDER_ENCODE_BUFFER(iqmatrix); break; case VAEncSequenceParameterBufferType: vaStatus = I965_RENDER_ENCODE_BUFFER(sequence_parameter_ext); break; case VAEncPictureParameterBufferType: vaStatus = I965_RENDER_ENCODE_BUFFER(picture_parameter_ext); break; case VAEncSliceParameterBufferType: vaStatus = I965_RENDER_ENCODE_BUFFER(slice_parameter_ext); break; case VAEncPackedHeaderParameterBufferType: { struct encode_state *encode = &obj_context->codec_state.encode; VAEncPackedHeaderParameterBuffer *param = (VAEncPackedHeaderParameterBuffer *)obj_buffer->buffer_store->buffer; encode->last_packed_header_type = param->type; vaStatus = i965_encoder_render_packed_header_parameter_buffer(ctx, obj_context, obj_buffer, va_enc_packed_type_to_idx(encode->last_packed_header_type)); break; } case VAEncPackedHeaderDataBufferType: { struct encode_state *encode = &obj_context->codec_state.encode; assert(encode->last_packed_header_type == VAEncPackedHeaderSequence || encode->last_packed_header_type == VAEncPackedHeaderPicture || encode->last_packed_header_type == VAEncPackedHeaderSlice || (((encode->last_packed_header_type & VAEncPackedHeaderMiscMask) == VAEncPackedHeaderMiscMask) && ((encode->last_packed_header_type & (~VAEncPackedHeaderMiscMask)) != 0))); vaStatus = i965_encoder_render_packed_header_data_buffer(ctx, obj_context, obj_buffer, va_enc_packed_type_to_idx(encode->last_packed_header_type)); break; } case VAEncMiscParameterBufferType: vaStatus = i965_encoder_render_misc_parameter_buffer(ctx, obj_context, obj_buffer); break; default: vaStatus = VA_STATUS_ERROR_UNSUPPORTED_BUFFERTYPE; break; } } return vaStatus; } #define I965_RENDER_PROC_BUFFER(name) I965_RENDER_BUFFER(proc, name) #define DEF_RENDER_PROC_SINGLE_BUFFER_FUNC(name, member) DEF_RENDER_SINGLE_BUFFER_FUNC(proc, name, member) DEF_RENDER_PROC_SINGLE_BUFFER_FUNC(pipeline_parameter, pipeline_param) static VAStatus i965_proc_render_picture(VADriverContextP ctx, VAContextID context, VABufferID *buffers, int num_buffers) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_context *obj_context = CONTEXT(context); VAStatus vaStatus = VA_STATUS_SUCCESS; int i; assert(obj_context); if (!obj_context) return VA_STATUS_ERROR_INVALID_CONTEXT; for (i = 0; i < num_buffers && vaStatus == VA_STATUS_SUCCESS; i++) { struct object_buffer *obj_buffer = BUFFER(buffers[i]); if (!obj_buffer) return VA_STATUS_ERROR_INVALID_BUFFER; switch (obj_buffer->type) { case VAProcPipelineParameterBufferType: vaStatus = I965_RENDER_PROC_BUFFER(pipeline_parameter); break; default: vaStatus = VA_STATUS_ERROR_UNSUPPORTED_BUFFERTYPE; break; } } return vaStatus; } VAStatus i965_RenderPicture(VADriverContextP ctx, VAContextID context, VABufferID *buffers, int num_buffers) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_context *obj_context; struct object_config *obj_config; VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN; obj_context = CONTEXT(context); assert(obj_context); if (!obj_context) return VA_STATUS_ERROR_INVALID_CONTEXT; if (num_buffers <= 0) return VA_STATUS_ERROR_INVALID_PARAMETER; obj_config = obj_context->obj_config; assert(obj_config); if (VAEntrypointVideoProc == obj_config->entrypoint) { vaStatus = i965_proc_render_picture(ctx, context, buffers, num_buffers); } else if (VAEntrypointEncSlice == obj_config->entrypoint ) { vaStatus = i965_encoder_render_picture(ctx, context, buffers, num_buffers); } else { vaStatus = i965_decoder_render_picture(ctx, context, buffers, num_buffers); } return vaStatus; } VAStatus i965_EndPicture(VADriverContextP ctx, VAContextID context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_context *obj_context = CONTEXT(context); struct object_config *obj_config; assert(obj_context); if (!obj_context) return VA_STATUS_ERROR_INVALID_CONTEXT; obj_config = obj_context->obj_config; assert(obj_config); if (obj_context->codec_type == CODEC_PROC) { assert(VAEntrypointVideoProc == obj_config->entrypoint); } else if (obj_context->codec_type == CODEC_ENC) { assert(VAEntrypointEncSlice == obj_config->entrypoint); if (!(obj_context->codec_state.encode.pic_param || obj_context->codec_state.encode.pic_param_ext)) { return VA_STATUS_ERROR_INVALID_PARAMETER; } if (!(obj_context->codec_state.encode.seq_param || obj_context->codec_state.encode.seq_param_ext)) { return VA_STATUS_ERROR_INVALID_PARAMETER; } if ((obj_context->codec_state.encode.num_slice_params <=0) && (obj_context->codec_state.encode.num_slice_params_ext <=0)) { return VA_STATUS_ERROR_INVALID_PARAMETER; } } else { if (obj_context->codec_state.decode.pic_param == NULL) { return VA_STATUS_ERROR_INVALID_PARAMETER; } if (obj_context->codec_state.decode.num_slice_params <=0) { return VA_STATUS_ERROR_INVALID_PARAMETER; } if (obj_context->codec_state.decode.num_slice_datas <=0) { return VA_STATUS_ERROR_INVALID_PARAMETER; } if (obj_context->codec_state.decode.num_slice_params != obj_context->codec_state.decode.num_slice_datas) { return VA_STATUS_ERROR_INVALID_PARAMETER; } } assert(obj_context->hw_context->run); return obj_context->hw_context->run(ctx, obj_config->profile, &obj_context->codec_state, obj_context->hw_context); } VAStatus i965_SyncSurface(VADriverContextP ctx, VASurfaceID render_target) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface = SURFACE(render_target); assert(obj_surface); if(obj_surface->bo) drm_intel_bo_wait_rendering(obj_surface->bo); return VA_STATUS_SUCCESS; } VAStatus i965_QuerySurfaceStatus(VADriverContextP ctx, VASurfaceID render_target, VASurfaceStatus *status) /* out */ { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface = SURFACE(render_target); assert(obj_surface); if (obj_surface->bo) { if (drm_intel_bo_busy(obj_surface->bo)){ *status = VASurfaceRendering; } else { *status = VASurfaceReady; } } else { *status = VASurfaceReady; } return VA_STATUS_SUCCESS; } static VADisplayAttribute * get_display_attribute(VADriverContextP ctx, VADisplayAttribType type) { struct i965_driver_data * const i965 = i965_driver_data(ctx); unsigned int i; if (!i965->display_attributes) return NULL; for (i = 0; i < i965->num_display_attributes; i++) { if (i965->display_attributes[i].type == type) return &i965->display_attributes[i]; } return NULL; } static void i965_display_attributes_terminate(VADriverContextP ctx) { struct i965_driver_data * const i965 = i965_driver_data(ctx); if (i965->display_attributes) { free(i965->display_attributes); i965->display_attributes = NULL; i965->num_display_attributes = 0; } } static bool i965_display_attributes_init(VADriverContextP ctx) { struct i965_driver_data * const i965 = i965_driver_data(ctx); i965->num_display_attributes = ARRAY_ELEMS(i965_display_attributes); i965->display_attributes = malloc( i965->num_display_attributes * sizeof(i965->display_attributes[0])); if (!i965->display_attributes) goto error; memcpy( i965->display_attributes, i965_display_attributes, sizeof(i965_display_attributes) ); i965->rotation_attrib = get_display_attribute(ctx, VADisplayAttribRotation); i965->brightness_attrib = get_display_attribute(ctx, VADisplayAttribBrightness); i965->contrast_attrib = get_display_attribute(ctx, VADisplayAttribContrast); i965->hue_attrib = get_display_attribute(ctx, VADisplayAttribHue); i965->saturation_attrib = get_display_attribute(ctx, VADisplayAttribSaturation); if (!i965->rotation_attrib || !i965->brightness_attrib || !i965->contrast_attrib || !i965->hue_attrib || !i965->saturation_attrib) { goto error; } return true; error: i965_display_attributes_terminate(ctx); return false; } /* * Query display attributes * The caller must provide a "attr_list" array that can hold at * least vaMaxNumDisplayAttributes() entries. The actual number of attributes * returned in "attr_list" is returned in "num_attributes". */ VAStatus i965_QueryDisplayAttributes( VADriverContextP ctx, VADisplayAttribute *attribs, /* out */ int *num_attribs_ptr /* out */ ) { const int num_attribs = ARRAY_ELEMS(i965_display_attributes); if (attribs && num_attribs > 0) memcpy(attribs, i965_display_attributes, sizeof(i965_display_attributes)); if (num_attribs_ptr) *num_attribs_ptr = num_attribs; return VA_STATUS_SUCCESS; } /* * Get display attributes * This function returns the current attribute values in "attr_list". * Only attributes returned with VA_DISPLAY_ATTRIB_GETTABLE set in the "flags" field * from vaQueryDisplayAttributes() can have their values retrieved. */ VAStatus i965_GetDisplayAttributes( VADriverContextP ctx, VADisplayAttribute *attribs, /* inout */ int num_attribs /* in */ ) { int i; for (i = 0; i < num_attribs; i++) { VADisplayAttribute *src_attrib, * const dst_attrib = &attribs[i]; src_attrib = get_display_attribute(ctx, dst_attrib->type); if (src_attrib && (src_attrib->flags & VA_DISPLAY_ATTRIB_GETTABLE)) { dst_attrib->min_value = src_attrib->min_value; dst_attrib->max_value = src_attrib->max_value; dst_attrib->value = src_attrib->value; } else dst_attrib->flags = VA_DISPLAY_ATTRIB_NOT_SUPPORTED; } return VA_STATUS_SUCCESS; } /* * Set display attributes * Only attributes returned with VA_DISPLAY_ATTRIB_SETTABLE set in the "flags" field * from vaQueryDisplayAttributes() can be set. If the attribute is not settable or * the value is out of range, the function returns VA_STATUS_ERROR_ATTR_NOT_SUPPORTED */ VAStatus i965_SetDisplayAttributes( VADriverContextP ctx, VADisplayAttribute *attribs, /* in */ int num_attribs /* in */ ) { int i; for (i = 0; i < num_attribs; i++) { VADisplayAttribute *dst_attrib, * const src_attrib = &attribs[i]; dst_attrib = get_display_attribute(ctx, src_attrib->type); if (!dst_attrib) return VA_STATUS_ERROR_ATTR_NOT_SUPPORTED; if (!(dst_attrib->flags & VA_DISPLAY_ATTRIB_SETTABLE)) continue; if (src_attrib->value < dst_attrib->min_value || src_attrib->value > dst_attrib->max_value) return VA_STATUS_ERROR_INVALID_PARAMETER; dst_attrib->value = src_attrib->value; /* XXX: track modified attributes through timestamps */ } return VA_STATUS_SUCCESS; } VAStatus i965_DbgCopySurfaceToBuffer(VADriverContextP ctx, VASurfaceID surface, void **buffer, /* out */ unsigned int *stride) /* out */ { /* TODO */ return VA_STATUS_ERROR_UNIMPLEMENTED; } static void i965_destroy_heap(struct object_heap *heap, void (*func)(struct object_heap *heap, struct object_base *object)) { struct object_base *object; object_heap_iterator iter; object = object_heap_first(heap, &iter); while (object) { if (func) func(heap, object); object = object_heap_next(heap, &iter); } object_heap_destroy(heap); } VAStatus i965_DestroyImage(VADriverContextP ctx, VAImageID image); VAStatus i965_CreateImage(VADriverContextP ctx, VAImageFormat *format, int width, int height, VAImage *out_image) /* out */ { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_image *obj_image; VAStatus va_status = VA_STATUS_ERROR_OPERATION_FAILED; VAImageID image_id; unsigned int size2, size, awidth, aheight; out_image->image_id = VA_INVALID_ID; out_image->buf = VA_INVALID_ID; image_id = NEW_IMAGE_ID(); if (image_id == VA_INVALID_ID) return VA_STATUS_ERROR_ALLOCATION_FAILED; obj_image = IMAGE(image_id); if (!obj_image) return VA_STATUS_ERROR_ALLOCATION_FAILED; obj_image->bo = NULL; obj_image->palette = NULL; obj_image->derived_surface = VA_INVALID_ID; VAImage * const image = &obj_image->image; image->image_id = image_id; image->buf = VA_INVALID_ID; awidth = ALIGN(width, 64); if ((format->fourcc == VA_FOURCC('Y','V','1','2')) || (format->fourcc == VA_FOURCC('I','4','2','0'))) { if (awidth % 128 != 0) { awidth = ALIGN(width, 128); } } aheight = ALIGN(height, 16); size = awidth * aheight; size2 = (awidth / 2) * (aheight / 2); image->num_palette_entries = 0; image->entry_bytes = 0; memset(image->component_order, 0, sizeof(image->component_order)); switch (format->fourcc) { case VA_FOURCC('I','A','4','4'): case VA_FOURCC('A','I','4','4'): image->num_planes = 1; image->pitches[0] = awidth; image->offsets[0] = 0; image->data_size = image->offsets[0] + image->pitches[0] * aheight; image->num_palette_entries = 16; image->entry_bytes = 3; image->component_order[0] = 'R'; image->component_order[1] = 'G'; image->component_order[2] = 'B'; break; case VA_FOURCC('I','A','8','8'): case VA_FOURCC('A','I','8','8'): image->num_planes = 1; image->pitches[0] = awidth * 2; image->offsets[0] = 0; image->data_size = image->offsets[0] + image->pitches[0] * aheight; image->num_palette_entries = 256; image->entry_bytes = 3; image->component_order[0] = 'R'; image->component_order[1] = 'G'; image->component_order[2] = 'B'; break; case VA_FOURCC('A','R','G','B'): case VA_FOURCC('A','B','G','R'): case VA_FOURCC('B','G','R','A'): case VA_FOURCC('R','G','B','A'): case VA_FOURCC('B','G','R','X'): case VA_FOURCC('R','G','B','X'): image->num_planes = 1; image->pitches[0] = awidth * 4; image->offsets[0] = 0; image->data_size = image->offsets[0] + image->pitches[0] * aheight; break; case VA_FOURCC('Y','V','1','2'): image->num_planes = 3; image->pitches[0] = awidth; image->offsets[0] = 0; image->pitches[1] = awidth / 2; image->offsets[1] = size; image->pitches[2] = awidth / 2; image->offsets[2] = size + size2; image->data_size = size + 2 * size2; break; case VA_FOURCC('I','4','2','0'): image->num_planes = 3; image->pitches[0] = awidth; image->offsets[0] = 0; image->pitches[1] = awidth / 2; image->offsets[1] = size; image->pitches[2] = awidth / 2; image->offsets[2] = size + size2; image->data_size = size + 2 * size2; break; case VA_FOURCC('N','V','1','2'): image->num_planes = 2; image->pitches[0] = awidth; image->offsets[0] = 0; image->pitches[1] = awidth; image->offsets[1] = size; image->data_size = size + 2 * size2; break; case VA_FOURCC('Y','U','Y','2'): case VA_FOURCC('U','Y','V','Y'): image->num_planes = 1; image->pitches[0] = awidth * 2; image->offsets[0] = 0; image->data_size = size * 2; break; default: goto error; } va_status = i965_CreateBuffer(ctx, 0, VAImageBufferType, image->data_size, 1, NULL, &image->buf); if (va_status != VA_STATUS_SUCCESS) goto error; struct object_buffer *obj_buffer = BUFFER(image->buf); if (!obj_buffer || !obj_buffer->buffer_store || !obj_buffer->buffer_store->bo) return VA_STATUS_ERROR_ALLOCATION_FAILED; obj_image->bo = obj_buffer->buffer_store->bo; dri_bo_reference(obj_image->bo); if (image->num_palette_entries > 0 && image->entry_bytes > 0) { obj_image->palette = malloc(image->num_palette_entries * sizeof(*obj_image->palette)); if (!obj_image->palette) goto error; } image->image_id = image_id; image->format = *format; image->width = width; image->height = height; *out_image = *image; return VA_STATUS_SUCCESS; error: i965_DestroyImage(ctx, image_id); return va_status; } void i965_check_alloc_surface_bo(VADriverContextP ctx, struct object_surface *obj_surface, int tiled, unsigned int fourcc, unsigned int subsampling) { struct i965_driver_data *i965 = i965_driver_data(ctx); int region_width, region_height; if (obj_surface->bo) { assert(obj_surface->fourcc); assert(obj_surface->fourcc == fourcc); assert(obj_surface->subsampling == subsampling); return; } obj_surface->x_cb_offset = 0; /* X offset is always 0 */ obj_surface->x_cr_offset = 0; if (tiled) { assert(fourcc != VA_FOURCC('I', '4', '2', '0') && fourcc != VA_FOURCC('I', 'Y', 'U', 'V') && fourcc != VA_FOURCC('Y', 'V', '1', '2')); obj_surface->width = ALIGN(obj_surface->orig_width, 128); obj_surface->height = ALIGN(obj_surface->orig_height, 32); region_height = obj_surface->height; switch (fourcc) { case VA_FOURCC('N', 'V', '1', '2'): assert(subsampling == SUBSAMPLE_YUV420); obj_surface->cb_cr_pitch = obj_surface->width; obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height / 2; obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = obj_surface->height; region_width = obj_surface->width; region_height = obj_surface->height + ALIGN(obj_surface->cb_cr_height, 32); break; case VA_FOURCC('I', 'M', 'C', '1'): assert(subsampling == SUBSAMPLE_YUV420); obj_surface->cb_cr_pitch = obj_surface->width; obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height / 2; obj_surface->y_cr_offset = obj_surface->height; obj_surface->y_cb_offset = obj_surface->y_cr_offset + ALIGN(obj_surface->cb_cr_height, 32); region_width = obj_surface->width; region_height = obj_surface->height + ALIGN(obj_surface->cb_cr_height, 32) * 2; break; case VA_FOURCC('I', 'M', 'C', '3'): assert(subsampling == SUBSAMPLE_YUV420); obj_surface->cb_cr_pitch = obj_surface->width; obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height / 2; obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = obj_surface->y_cb_offset + ALIGN(obj_surface->cb_cr_height, 32); region_width = obj_surface->width; region_height = obj_surface->height + ALIGN(obj_surface->cb_cr_height, 32) * 2; break; case VA_FOURCC('4', '2', '2', 'H'): assert(subsampling == SUBSAMPLE_YUV422H); obj_surface->cb_cr_pitch = obj_surface->width; obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height; obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = obj_surface->y_cb_offset + ALIGN(obj_surface->cb_cr_height, 32); region_width = obj_surface->width; region_height = obj_surface->height + ALIGN(obj_surface->cb_cr_height, 32) * 2; break; case VA_FOURCC('4', '2', '2', 'V'): assert(subsampling == SUBSAMPLE_YUV422V); obj_surface->cb_cr_pitch = obj_surface->width; obj_surface->cb_cr_width = obj_surface->orig_width; obj_surface->cb_cr_height = obj_surface->orig_height / 2; obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = obj_surface->y_cb_offset + ALIGN(obj_surface->cb_cr_height, 32); region_width = obj_surface->width; region_height = obj_surface->height + ALIGN(obj_surface->cb_cr_height, 32) * 2; break; case VA_FOURCC('4', '1', '1', 'P'): assert(subsampling == SUBSAMPLE_YUV411); obj_surface->cb_cr_pitch = obj_surface->width; obj_surface->cb_cr_width = obj_surface->orig_width / 4; obj_surface->cb_cr_height = obj_surface->orig_height; obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = obj_surface->y_cb_offset + ALIGN(obj_surface->cb_cr_height, 32); region_width = obj_surface->width; region_height = obj_surface->height + ALIGN(obj_surface->cb_cr_height, 32) * 2; break; case VA_FOURCC('4', '4', '4', 'P'): assert(subsampling == SUBSAMPLE_YUV444); obj_surface->cb_cr_pitch = obj_surface->width; obj_surface->cb_cr_width = obj_surface->orig_width; obj_surface->cb_cr_height = obj_surface->orig_height; obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = obj_surface->y_cb_offset + ALIGN(obj_surface->cb_cr_height, 32); region_width = obj_surface->width; region_height = obj_surface->height + ALIGN(obj_surface->cb_cr_height, 32) * 2; break; case VA_FOURCC('Y', '8', '0', '0'): assert(subsampling == SUBSAMPLE_YUV400); obj_surface->cb_cr_pitch = obj_surface->width; obj_surface->cb_cr_width = 0; obj_surface->cb_cr_height = 0; obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = obj_surface->y_cb_offset + ALIGN(obj_surface->cb_cr_height, 32); region_width = obj_surface->width; region_height = obj_surface->height + ALIGN(obj_surface->cb_cr_height, 32) * 2; break; case VA_FOURCC('Y', 'U', 'Y', '2'): case VA_FOURCC('U', 'Y', 'V', 'Y'): assert(subsampling == SUBSAMPLE_YUV422H); obj_surface->width = ALIGN(obj_surface->orig_width * 2, 128); obj_surface->cb_cr_pitch = obj_surface->width; obj_surface->y_cb_offset = 0; obj_surface->y_cr_offset = 0; obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height / 2; region_width = obj_surface->width; region_height = obj_surface->height; break; case VA_FOURCC('R', 'G', 'B', 'A'): case VA_FOURCC('R', 'G', 'B', 'X'): case VA_FOURCC('B', 'G', 'R', 'A'): case VA_FOURCC('B', 'G', 'R', 'X'): assert(subsampling == SUBSAMPLE_RGBX); obj_surface->width = ALIGN(obj_surface->orig_width * 4, 128); region_width = obj_surface->width; region_height = obj_surface->height; break; default: /* Never get here */ assert(0); break; } } else { assert(subsampling == SUBSAMPLE_YUV420 || subsampling == SUBSAMPLE_YUV422H || subsampling == SUBSAMPLE_YUV422V || subsampling == SUBSAMPLE_RGBX); region_width = obj_surface->width; region_height = obj_surface->height; switch (fourcc) { case VA_FOURCC('N', 'V', '1', '2'): obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = obj_surface->height; obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height / 2; obj_surface->cb_cr_pitch = obj_surface->width; region_height = obj_surface->height + obj_surface->height / 2; break; case VA_FOURCC('Y', 'V', '1', '2'): case VA_FOURCC('I', '4', '2', '0'): if (fourcc == VA_FOURCC('Y', 'V', '1', '2')) { obj_surface->y_cr_offset = obj_surface->height; obj_surface->y_cb_offset = obj_surface->height + obj_surface->height / 4; } else { obj_surface->y_cb_offset = obj_surface->height; obj_surface->y_cr_offset = obj_surface->height + obj_surface->height / 4; } obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height / 2; obj_surface->cb_cr_pitch = obj_surface->width / 2; region_height = obj_surface->height + obj_surface->height / 2; break; case VA_FOURCC('Y', 'U', 'Y', '2'): case VA_FOURCC('U', 'Y', 'V', 'Y'): obj_surface->width = ALIGN(obj_surface->orig_width * 2, 16); obj_surface->y_cb_offset = 0; obj_surface->y_cr_offset = 0; obj_surface->cb_cr_width = obj_surface->orig_width / 2; obj_surface->cb_cr_height = obj_surface->orig_height; obj_surface->cb_cr_pitch = obj_surface->width; region_width = obj_surface->width; region_height = obj_surface->height; break; case VA_FOURCC('R', 'G', 'B', 'A'): case VA_FOURCC('R', 'G', 'B', 'X'): case VA_FOURCC('B', 'G', 'R', 'A'): case VA_FOURCC('B', 'G', 'R', 'X'): obj_surface->width = ALIGN(obj_surface->orig_width * 4, 16); region_width = obj_surface->width; region_height = obj_surface->height; break; default: /* Never get here */ assert(0); break; } } obj_surface->size = ALIGN(region_width * region_height, 0x1000); if (tiled) { uint32_t tiling_mode = I915_TILING_Y; /* always uses Y-tiled format */ unsigned long pitch; obj_surface->bo = drm_intel_bo_alloc_tiled(i965->intel.bufmgr, "vaapi surface", region_width, region_height, 1, &tiling_mode, &pitch, 0); assert(tiling_mode == I915_TILING_Y); assert(pitch == obj_surface->width); } else { obj_surface->bo = dri_bo_alloc(i965->intel.bufmgr, "vaapi surface", obj_surface->size, 0x1000); } obj_surface->fourcc = fourcc; obj_surface->subsampling = subsampling; assert(obj_surface->bo); } VAStatus i965_DeriveImage(VADriverContextP ctx, VASurfaceID surface, VAImage *out_image) /* out */ { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_image *obj_image; struct object_surface *obj_surface; VAImageID image_id; unsigned int w_pitch; VAStatus va_status = VA_STATUS_ERROR_OPERATION_FAILED; out_image->image_id = VA_INVALID_ID; obj_surface = SURFACE(surface); if (!obj_surface) return VA_STATUS_ERROR_INVALID_SURFACE; if (!obj_surface->bo) { unsigned int is_tiled = 0; unsigned int fourcc = VA_FOURCC('Y', 'V', '1', '2'); i965_guess_surface_format(ctx, surface, &fourcc, &is_tiled); int sampling = get_sampling_from_fourcc(fourcc); i965_check_alloc_surface_bo(ctx, obj_surface, is_tiled, fourcc, sampling); } assert(obj_surface->fourcc); w_pitch = obj_surface->width; image_id = NEW_IMAGE_ID(); if (image_id == VA_INVALID_ID) return VA_STATUS_ERROR_ALLOCATION_FAILED; obj_image = IMAGE(image_id); if (!obj_image) return VA_STATUS_ERROR_ALLOCATION_FAILED; obj_image->bo = NULL; obj_image->palette = NULL; obj_image->derived_surface = VA_INVALID_ID; VAImage * const image = &obj_image->image; memset(image, 0, sizeof(*image)); image->image_id = image_id; image->buf = VA_INVALID_ID; image->num_palette_entries = 0; image->entry_bytes = 0; image->width = obj_surface->orig_width; image->height = obj_surface->orig_height; image->data_size = obj_surface->size; image->format.fourcc = obj_surface->fourcc; image->format.byte_order = VA_LSB_FIRST; image->format.bits_per_pixel = 12; switch (image->format.fourcc) { case VA_FOURCC('Y', 'V', '1', '2'): image->num_planes = 3; image->pitches[0] = w_pitch; /* Y */ image->offsets[0] = 0; image->pitches[1] = obj_surface->cb_cr_pitch; /* V */ image->offsets[1] = w_pitch * obj_surface->y_cr_offset; image->pitches[2] = obj_surface->cb_cr_pitch; /* U */ image->offsets[2] = w_pitch * obj_surface->y_cb_offset; break; case VA_FOURCC('N', 'V', '1', '2'): image->num_planes = 2; image->pitches[0] = w_pitch; /* Y */ image->offsets[0] = 0; image->pitches[1] = obj_surface->cb_cr_pitch; /* UV */ image->offsets[1] = w_pitch * obj_surface->y_cb_offset; break; case VA_FOURCC('I', '4', '2', '0'): image->num_planes = 3; image->pitches[0] = w_pitch; /* Y */ image->offsets[0] = 0; image->pitches[1] = obj_surface->cb_cr_pitch; /* U */ image->offsets[1] = w_pitch * obj_surface->y_cb_offset; image->pitches[2] = obj_surface->cb_cr_pitch; /* V */ image->offsets[2] = w_pitch * obj_surface->y_cr_offset; break; case VA_FOURCC('Y', 'U', 'Y', '2'): case VA_FOURCC('U', 'Y', 'V', 'Y'): image->num_planes = 1; image->pitches[0] = obj_surface->width; /* Y, width is aligned already */ image->offsets[0] = 0; break; case VA_FOURCC('R', 'G', 'B', 'A'): case VA_FOURCC('R', 'G', 'B', 'X'): case VA_FOURCC('B', 'G', 'R', 'A'): case VA_FOURCC('B', 'G', 'R', 'X'): image->num_planes = 1; image->pitches[0] = obj_surface->width; break; default: goto error; } va_status = i965_create_buffer_internal(ctx, 0, VAImageBufferType, obj_surface->size, 1, NULL, obj_surface->bo, &image->buf); if (va_status != VA_STATUS_SUCCESS) goto error; struct object_buffer *obj_buffer = BUFFER(image->buf); if (!obj_buffer || !obj_buffer->buffer_store || !obj_buffer->buffer_store->bo) return VA_STATUS_ERROR_ALLOCATION_FAILED; obj_image->bo = obj_buffer->buffer_store->bo; dri_bo_reference(obj_image->bo); if (image->num_palette_entries > 0 && image->entry_bytes > 0) { obj_image->palette = malloc(image->num_palette_entries * sizeof(*obj_image->palette)); if (!obj_image->palette) { va_status = VA_STATUS_ERROR_ALLOCATION_FAILED; goto error; } } *out_image = *image; obj_surface->flags |= SURFACE_DERIVED; obj_image->derived_surface = surface; return VA_STATUS_SUCCESS; error: i965_DestroyImage(ctx, image_id); return va_status; } static void i965_destroy_image(struct object_heap *heap, struct object_base *obj) { object_heap_free(heap, obj); } VAStatus i965_DestroyImage(VADriverContextP ctx, VAImageID image) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_image *obj_image = IMAGE(image); struct object_surface *obj_surface; if (!obj_image) return VA_STATUS_SUCCESS; dri_bo_unreference(obj_image->bo); obj_image->bo = NULL; if (obj_image->image.buf != VA_INVALID_ID) { i965_DestroyBuffer(ctx, obj_image->image.buf); obj_image->image.buf = VA_INVALID_ID; } if (obj_image->palette) { free(obj_image->palette); obj_image->palette = NULL; } obj_surface = SURFACE(obj_image->derived_surface); if (obj_surface) { obj_surface->flags &= ~SURFACE_DERIVED; } i965_destroy_image(&i965->image_heap, (struct object_base *)obj_image); return VA_STATUS_SUCCESS; } /* * pointer to an array holding the palette data. The size of the array is * num_palette_entries * entry_bytes in size. The order of the components * in the palette is described by the component_order in VASubpicture struct */ VAStatus i965_SetImagePalette(VADriverContextP ctx, VAImageID image, unsigned char *palette) { struct i965_driver_data *i965 = i965_driver_data(ctx); unsigned int i; struct object_image *obj_image = IMAGE(image); if (!obj_image) return VA_STATUS_ERROR_INVALID_IMAGE; if (!obj_image->palette) return VA_STATUS_ERROR_ALLOCATION_FAILED; /* XXX: unpaletted/error */ for (i = 0; i < obj_image->image.num_palette_entries; i++) obj_image->palette[i] = (((unsigned int)palette[3*i + 0] << 16) | ((unsigned int)palette[3*i + 1] << 8) | (unsigned int)palette[3*i + 2]); return VA_STATUS_SUCCESS; } static int get_sampling_from_fourcc(unsigned int fourcc) { int surface_sampling = -1; switch (fourcc) { case VA_FOURCC('N', 'V', '1', '2'): case VA_FOURCC('Y', 'V', '1', '2'): case VA_FOURCC('I', '4', '2', '0'): case VA_FOURCC('I', 'Y', 'U', 'V'): case VA_FOURCC('I', 'M', 'C', '1'): case VA_FOURCC('I', 'M', 'C', '3'): surface_sampling = SUBSAMPLE_YUV420; break; case VA_FOURCC('Y', 'U', 'Y', '2'): case VA_FOURCC('U', 'Y', 'V', 'Y'): case VA_FOURCC('4', '2', '2', 'H'): surface_sampling = SUBSAMPLE_YUV422H; break; case VA_FOURCC('4', '2', '2', 'V'): surface_sampling = SUBSAMPLE_YUV422V; break; case VA_FOURCC('4', '4', '4', 'P'): surface_sampling = SUBSAMPLE_YUV444; break; case VA_FOURCC('4', '1', '1', 'P'): surface_sampling = SUBSAMPLE_YUV411; break; case VA_FOURCC('Y', '8', '0', '0'): surface_sampling = SUBSAMPLE_YUV400; break; case VA_FOURCC('R','G','B','A'): case VA_FOURCC('R','G','B','X'): case VA_FOURCC('B','G','R','A'): case VA_FOURCC('B','G','R','X'): surface_sampling = SUBSAMPLE_RGBX; break; default: /* Never get here */ assert(0); break; } return surface_sampling; } static inline void memcpy_pic(uint8_t *dst, unsigned int dst_stride, const uint8_t *src, unsigned int src_stride, unsigned int len, unsigned int height) { unsigned int i; for (i = 0; i < height; i++) { memcpy(dst, src, len); dst += dst_stride; src += src_stride; } } static void get_image_i420(struct object_image *obj_image, uint8_t *image_data, struct object_surface *obj_surface, const VARectangle *rect) { uint8_t *dst[3], *src[3]; const int Y = 0; const int U = obj_image->image.format.fourcc == obj_surface->fourcc ? 1 : 2; const int V = obj_image->image.format.fourcc == obj_surface->fourcc ? 2 : 1; unsigned int tiling, swizzle; if (!obj_surface->bo) return; assert(obj_surface->fourcc); dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_map_gtt(obj_surface->bo); else dri_bo_map(obj_surface->bo, 0); if (!obj_surface->bo->virtual) return; /* Dest VA image has either I420 or YV12 format. Source VA surface alway has I420 format */ dst[Y] = image_data + obj_image->image.offsets[Y]; src[0] = (uint8_t *)obj_surface->bo->virtual; dst[U] = image_data + obj_image->image.offsets[U]; src[1] = src[0] + obj_surface->width * obj_surface->height; dst[V] = image_data + obj_image->image.offsets[V]; src[2] = src[1] + (obj_surface->width / 2) * (obj_surface->height / 2); /* Y plane */ dst[Y] += rect->y * obj_image->image.pitches[Y] + rect->x; src[0] += rect->y * obj_surface->width + rect->x; memcpy_pic(dst[Y], obj_image->image.pitches[Y], src[0], obj_surface->width, rect->width, rect->height); /* U plane */ dst[U] += (rect->y / 2) * obj_image->image.pitches[U] + rect->x / 2; src[1] += (rect->y / 2) * obj_surface->width / 2 + rect->x / 2; memcpy_pic(dst[U], obj_image->image.pitches[U], src[1], obj_surface->width / 2, rect->width / 2, rect->height / 2); /* V plane */ dst[V] += (rect->y / 2) * obj_image->image.pitches[V] + rect->x / 2; src[2] += (rect->y / 2) * obj_surface->width / 2 + rect->x / 2; memcpy_pic(dst[V], obj_image->image.pitches[V], src[2], obj_surface->width / 2, rect->width / 2, rect->height / 2); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_unmap_gtt(obj_surface->bo); else dri_bo_unmap(obj_surface->bo); } static void get_image_nv12(struct object_image *obj_image, uint8_t *image_data, struct object_surface *obj_surface, const VARectangle *rect) { uint8_t *dst[2], *src[2]; unsigned int tiling, swizzle; if (!obj_surface->bo) return; assert(obj_surface->fourcc); dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_map_gtt(obj_surface->bo); else dri_bo_map(obj_surface->bo, 0); if (!obj_surface->bo->virtual) return; /* Both dest VA image and source surface have NV12 format */ dst[0] = image_data + obj_image->image.offsets[0]; src[0] = (uint8_t *)obj_surface->bo->virtual; dst[1] = image_data + obj_image->image.offsets[1]; src[1] = src[0] + obj_surface->width * obj_surface->height; /* Y plane */ dst[0] += rect->y * obj_image->image.pitches[0] + rect->x; src[0] += rect->y * obj_surface->width + rect->x; memcpy_pic(dst[0], obj_image->image.pitches[0], src[0], obj_surface->width, rect->width, rect->height); /* UV plane */ dst[1] += (rect->y / 2) * obj_image->image.pitches[1] + (rect->x & -2); src[1] += (rect->y / 2) * obj_surface->width + (rect->x & -2); memcpy_pic(dst[1], obj_image->image.pitches[1], src[1], obj_surface->width, rect->width, rect->height / 2); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_unmap_gtt(obj_surface->bo); else dri_bo_unmap(obj_surface->bo); } static void get_image_yuy2(struct object_image *obj_image, uint8_t *image_data, struct object_surface *obj_surface, const VARectangle *rect) { uint8_t *dst, *src; unsigned int tiling, swizzle; if (!obj_surface->bo) return; assert(obj_surface->fourcc); dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_map_gtt(obj_surface->bo); else dri_bo_map(obj_surface->bo, 0); if (!obj_surface->bo->virtual) return; /* Both dest VA image and source surface have YUYV format */ dst = image_data + obj_image->image.offsets[0]; src = (uint8_t *)obj_surface->bo->virtual; /* Y plane */ dst += rect->y * obj_image->image.pitches[0] + rect->x*2; src += rect->y * obj_surface->width + rect->x*2; memcpy_pic(dst, obj_image->image.pitches[0], src, obj_surface->width*2, rect->width*2, rect->height); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_unmap_gtt(obj_surface->bo); else dri_bo_unmap(obj_surface->bo); } static VAStatus i965_sw_getimage(VADriverContextP ctx, VASurfaceID surface, int x, /* coordinates of the upper left source pixel */ int y, unsigned int width, /* width and height of the region */ unsigned int height, VAImageID image) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct object_surface *obj_surface = SURFACE(surface); if (!obj_surface) return VA_STATUS_ERROR_INVALID_SURFACE; struct object_image *obj_image = IMAGE(image); if (!obj_image) return VA_STATUS_ERROR_INVALID_IMAGE; if (x < 0 || y < 0) return VA_STATUS_ERROR_INVALID_PARAMETER; if (x + width > obj_surface->orig_width || y + height > obj_surface->orig_height) return VA_STATUS_ERROR_INVALID_PARAMETER; if (x + width > obj_image->image.width || y + height > obj_image->image.height) return VA_STATUS_ERROR_INVALID_PARAMETER; if (obj_surface->fourcc != obj_image->image.format.fourcc) return VA_STATUS_ERROR_INVALID_IMAGE_FORMAT; VAStatus va_status; void *image_data = NULL; va_status = i965_MapBuffer(ctx, obj_image->image.buf, &image_data); if (va_status != VA_STATUS_SUCCESS) return va_status; VARectangle rect; rect.x = x; rect.y = y; rect.width = width; rect.height = height; switch (obj_image->image.format.fourcc) { case VA_FOURCC('Y','V','1','2'): case VA_FOURCC('I','4','2','0'): /* I420 is native format for MPEG-2 decoded surfaces */ if (render_state->interleaved_uv) goto operation_failed; get_image_i420(obj_image, image_data, obj_surface, &rect); break; case VA_FOURCC('N','V','1','2'): /* NV12 is native format for H.264 decoded surfaces */ if (!render_state->interleaved_uv) goto operation_failed; get_image_nv12(obj_image, image_data, obj_surface, &rect); break; case VA_FOURCC('Y','U','Y','2'): /* YUY2 is the format supported by overlay plane */ get_image_yuy2(obj_image, image_data, obj_surface, &rect); break; default: operation_failed: va_status = VA_STATUS_ERROR_OPERATION_FAILED; break; } i965_UnmapBuffer(ctx, obj_image->image.buf); return va_status; } static VAStatus i965_hw_getimage(VADriverContextP ctx, VASurfaceID surface, int x, /* coordinates of the upper left source pixel */ int y, unsigned int width, /* width and height of the region */ unsigned int height, VAImageID image) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_surface src_surface; struct i965_surface dst_surface; VAStatus va_status; VARectangle rect; struct object_surface *obj_surface = SURFACE(surface); struct object_image *obj_image = IMAGE(image); if (!obj_surface) return VA_STATUS_ERROR_INVALID_SURFACE; if (!obj_image) return VA_STATUS_ERROR_INVALID_IMAGE; if (x < 0 || y < 0) return VA_STATUS_ERROR_INVALID_PARAMETER; if (x + width > obj_surface->orig_width || y + height > obj_surface->orig_height) return VA_STATUS_ERROR_INVALID_PARAMETER; if (x + width > obj_image->image.width || y + height > obj_image->image.height) return VA_STATUS_ERROR_INVALID_PARAMETER; if (!obj_surface->bo) return VA_STATUS_SUCCESS; assert(obj_image->bo); // image bo is always created, see i965_CreateImage() rect.x = x; rect.y = y; rect.width = width; rect.height = height; src_surface.base = (struct object_base *)obj_surface; src_surface.type = I965_SURFACE_TYPE_SURFACE; src_surface.flags = I965_SURFACE_FLAG_FRAME; dst_surface.base = (struct object_base *)obj_image; dst_surface.type = I965_SURFACE_TYPE_IMAGE; dst_surface.flags = I965_SURFACE_FLAG_FRAME; va_status = i965_image_processing(ctx, &src_surface, &rect, &dst_surface, &rect); return va_status; } VAStatus i965_GetImage(VADriverContextP ctx, VASurfaceID surface, int x, /* coordinates of the upper left source pixel */ int y, unsigned int width, /* width and height of the region */ unsigned int height, VAImageID image) { struct i965_driver_data * const i965 = i965_driver_data(ctx); VAStatus va_status; if (HAS_ACCELERATED_GETIMAGE(i965)) va_status = i965_hw_getimage(ctx, surface, x, y, width, height, image); else va_status = i965_sw_getimage(ctx, surface, x, y, width, height, image); return va_status; } static void put_image_i420(struct object_surface *obj_surface, const VARectangle *dst_rect, struct object_image *obj_image, uint8_t *image_data, const VARectangle *src_rect) { uint8_t *dst[3], *src[3]; const int Y = 0; const int U = obj_image->image.format.fourcc == obj_surface->fourcc ? 1 : 2; const int V = obj_image->image.format.fourcc == obj_surface->fourcc ? 2 : 1; unsigned int tiling, swizzle; if (!obj_surface->bo) return; assert(obj_surface->fourcc); assert(dst_rect->width == src_rect->width); assert(dst_rect->height == src_rect->height); dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_map_gtt(obj_surface->bo); else dri_bo_map(obj_surface->bo, 0); if (!obj_surface->bo->virtual) return; /* Dest VA image has either I420 or YV12 format. Source VA surface alway has I420 format */ dst[0] = (uint8_t *)obj_surface->bo->virtual; src[Y] = image_data + obj_image->image.offsets[Y]; dst[1] = dst[0] + obj_surface->width * obj_surface->height; src[U] = image_data + obj_image->image.offsets[U]; dst[2] = dst[1] + (obj_surface->width / 2) * (obj_surface->height / 2); src[V] = image_data + obj_image->image.offsets[V]; /* Y plane */ dst[0] += dst_rect->y * obj_surface->width + dst_rect->x; src[Y] += src_rect->y * obj_image->image.pitches[Y] + src_rect->x; memcpy_pic(dst[0], obj_surface->width, src[Y], obj_image->image.pitches[Y], src_rect->width, src_rect->height); /* U plane */ dst[1] += (dst_rect->y / 2) * obj_surface->width / 2 + dst_rect->x / 2; src[U] += (src_rect->y / 2) * obj_image->image.pitches[U] + src_rect->x / 2; memcpy_pic(dst[1], obj_surface->width / 2, src[U], obj_image->image.pitches[U], src_rect->width / 2, src_rect->height / 2); /* V plane */ dst[2] += (dst_rect->y / 2) * obj_surface->width / 2 + dst_rect->x / 2; src[V] += (src_rect->y / 2) * obj_image->image.pitches[V] + src_rect->x / 2; memcpy_pic(dst[2], obj_surface->width / 2, src[V], obj_image->image.pitches[V], src_rect->width / 2, src_rect->height / 2); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_unmap_gtt(obj_surface->bo); else dri_bo_unmap(obj_surface->bo); } static void put_image_nv12(struct object_surface *obj_surface, const VARectangle *dst_rect, struct object_image *obj_image, uint8_t *image_data, const VARectangle *src_rect) { uint8_t *dst[2], *src[2]; unsigned int tiling, swizzle; if (!obj_surface->bo) return; assert(obj_surface->fourcc); assert(dst_rect->width == src_rect->width); assert(dst_rect->height == src_rect->height); dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_map_gtt(obj_surface->bo); else dri_bo_map(obj_surface->bo, 0); if (!obj_surface->bo->virtual) return; /* Both dest VA image and source surface have NV12 format */ dst[0] = (uint8_t *)obj_surface->bo->virtual; src[0] = image_data + obj_image->image.offsets[0]; dst[1] = dst[0] + obj_surface->width * obj_surface->height; src[1] = image_data + obj_image->image.offsets[1]; /* Y plane */ dst[0] += dst_rect->y * obj_surface->width + dst_rect->x; src[0] += src_rect->y * obj_image->image.pitches[0] + src_rect->x; memcpy_pic(dst[0], obj_surface->width, src[0], obj_image->image.pitches[0], src_rect->width, src_rect->height); /* UV plane */ dst[1] += (dst_rect->y / 2) * obj_surface->width + (dst_rect->x & -2); src[1] += (src_rect->y / 2) * obj_image->image.pitches[1] + (src_rect->x & -2); memcpy_pic(dst[1], obj_surface->width, src[1], obj_image->image.pitches[1], src_rect->width, src_rect->height / 2); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_unmap_gtt(obj_surface->bo); else dri_bo_unmap(obj_surface->bo); } static void put_image_yuy2(struct object_surface *obj_surface, const VARectangle *dst_rect, struct object_image *obj_image, uint8_t *image_data, const VARectangle *src_rect) { uint8_t *dst, *src; unsigned int tiling, swizzle; if (!obj_surface->bo) return; assert(obj_surface->fourcc); assert(dst_rect->width == src_rect->width); assert(dst_rect->height == src_rect->height); dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_map_gtt(obj_surface->bo); else dri_bo_map(obj_surface->bo, 0); if (!obj_surface->bo->virtual) return; /* Both dest VA image and source surface have YUY2 format */ dst = (uint8_t *)obj_surface->bo->virtual; src = image_data + obj_image->image.offsets[0]; /* YUYV packed plane */ dst += dst_rect->y * obj_surface->width + dst_rect->x*2; src += src_rect->y * obj_image->image.pitches[0] + src_rect->x*2; memcpy_pic(dst, obj_surface->width*2, src, obj_image->image.pitches[0], src_rect->width*2, src_rect->height); if (tiling != I915_TILING_NONE) drm_intel_gem_bo_unmap_gtt(obj_surface->bo); else dri_bo_unmap(obj_surface->bo); } static VAStatus i965_sw_putimage(VADriverContextP ctx, VASurfaceID surface, VAImageID image, int src_x, int src_y, unsigned int src_width, unsigned int src_height, int dest_x, int dest_y, unsigned int dest_width, unsigned int dest_height) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface = SURFACE(surface); if (!obj_surface) return VA_STATUS_ERROR_INVALID_SURFACE; struct object_image *obj_image = IMAGE(image); if (!obj_image) return VA_STATUS_ERROR_INVALID_IMAGE; if (src_x < 0 || src_y < 0) return VA_STATUS_ERROR_INVALID_PARAMETER; if (src_x + src_width > obj_image->image.width || src_y + src_height > obj_image->image.height) return VA_STATUS_ERROR_INVALID_PARAMETER; if (dest_x < 0 || dest_y < 0) return VA_STATUS_ERROR_INVALID_PARAMETER; if (dest_x + dest_width > obj_surface->orig_width || dest_y + dest_height > obj_surface->orig_height) return VA_STATUS_ERROR_INVALID_PARAMETER; /* XXX: don't allow scaling */ if (src_width != dest_width || src_height != dest_height) return VA_STATUS_ERROR_INVALID_PARAMETER; if (obj_surface->fourcc) { /* Don't allow format mismatch */ if (obj_surface->fourcc != obj_image->image.format.fourcc) return VA_STATUS_ERROR_INVALID_IMAGE_FORMAT; } else { /* VA is surface not used for decoding, use same VA image format */ i965_check_alloc_surface_bo( ctx, obj_surface, 0, /* XXX: don't use tiled surface */ obj_image->image.format.fourcc, get_sampling_from_fourcc (obj_image->image.format.fourcc)); } VAStatus va_status; void *image_data = NULL; va_status = i965_MapBuffer(ctx, obj_image->image.buf, &image_data); if (va_status != VA_STATUS_SUCCESS) return va_status; VARectangle src_rect, dest_rect; src_rect.x = src_x; src_rect.y = src_y; src_rect.width = src_width; src_rect.height = src_height; dest_rect.x = dest_x; dest_rect.y = dest_y; dest_rect.width = dest_width; dest_rect.height = dest_height; switch (obj_image->image.format.fourcc) { case VA_FOURCC('Y','V','1','2'): case VA_FOURCC('I','4','2','0'): put_image_i420(obj_surface, &dest_rect, obj_image, image_data, &src_rect); break; case VA_FOURCC('N','V','1','2'): put_image_nv12(obj_surface, &dest_rect, obj_image, image_data, &src_rect); break; case VA_FOURCC('Y','U','Y','2'): put_image_yuy2(obj_surface, &dest_rect, obj_image, image_data, &src_rect); break; default: va_status = VA_STATUS_ERROR_OPERATION_FAILED; break; } i965_UnmapBuffer(ctx, obj_image->image.buf); return va_status; } static VAStatus i965_hw_putimage(VADriverContextP ctx, VASurfaceID surface, VAImageID image, int src_x, int src_y, unsigned int src_width, unsigned int src_height, int dest_x, int dest_y, unsigned int dest_width, unsigned int dest_height) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface = SURFACE(surface); struct object_image *obj_image = IMAGE(image); struct i965_surface src_surface, dst_surface; VAStatus va_status = VA_STATUS_SUCCESS; VARectangle src_rect, dst_rect; if (!obj_surface) return VA_STATUS_ERROR_INVALID_SURFACE; if (!obj_image || !obj_image->bo) return VA_STATUS_ERROR_INVALID_IMAGE; if (src_x < 0 || src_y < 0 || src_x + src_width > obj_image->image.width || src_y + src_height > obj_image->image.height) return VA_STATUS_ERROR_INVALID_PARAMETER; if (dest_x < 0 || dest_y < 0 || dest_x + dest_width > obj_surface->orig_width || dest_y + dest_height > obj_surface->orig_height) return VA_STATUS_ERROR_INVALID_PARAMETER; if (!obj_surface->bo) { unsigned int tiling, swizzle; int surface_sampling = get_sampling_from_fourcc (obj_image->image.format.fourcc);; dri_bo_get_tiling(obj_image->bo, &tiling, &swizzle); i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, obj_image->image.format.fourcc, surface_sampling); } assert(obj_surface->fourcc); src_surface.base = (struct object_base *)obj_image; src_surface.type = I965_SURFACE_TYPE_IMAGE; src_surface.flags = I965_SURFACE_FLAG_FRAME; src_rect.x = src_x; src_rect.y = src_y; src_rect.width = src_width; src_rect.height = src_height; dst_surface.base = (struct object_base *)obj_surface; dst_surface.type = I965_SURFACE_TYPE_SURFACE; dst_surface.flags = I965_SURFACE_FLAG_FRAME; dst_rect.x = dest_x; dst_rect.y = dest_y; dst_rect.width = dest_width; dst_rect.height = dest_height; va_status = i965_image_processing(ctx, &src_surface, &src_rect, &dst_surface, &dst_rect); return va_status; } static VAStatus i965_PutImage(VADriverContextP ctx, VASurfaceID surface, VAImageID image, int src_x, int src_y, unsigned int src_width, unsigned int src_height, int dest_x, int dest_y, unsigned int dest_width, unsigned int dest_height) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAStatus va_status = VA_STATUS_SUCCESS; if (HAS_ACCELERATED_PUTIMAGE(i965)) va_status = i965_hw_putimage(ctx, surface, image, src_x, src_y, src_width, src_height, dest_x, dest_y, dest_width, dest_height); else va_status = i965_sw_putimage(ctx, surface, image, src_x, src_y, src_width, src_height, dest_x, dest_y, dest_width, dest_height); return va_status; } VAStatus i965_PutSurface(VADriverContextP ctx, VASurfaceID surface, void *draw, /* X Drawable */ short srcx, short srcy, unsigned short srcw, unsigned short srch, short destx, short desty, unsigned short destw, unsigned short desth, VARectangle *cliprects, /* client supplied clip list */ unsigned int number_cliprects, /* number of clip rects in the clip list */ unsigned int flags) /* de-interlacing flags */ { #ifdef HAVE_VA_X11 if (IS_VA_X11(ctx)) { VARectangle src_rect, dst_rect; src_rect.x = srcx; src_rect.y = srcy; src_rect.width = srcw; src_rect.height = srch; dst_rect.x = destx; dst_rect.y = desty; dst_rect.width = destw; dst_rect.height = desth; return i965_put_surface_dri(ctx, surface, draw, &src_rect, &dst_rect, cliprects, number_cliprects, flags); } #endif return VA_STATUS_ERROR_UNIMPLEMENTED; } static VAStatus i965_BufferInfo( VADriverContextP ctx, /* in */ VABufferID buf_id, /* in */ VABufferType *type, /* out */ unsigned int *size, /* out */ unsigned int *num_elements /* out */ ) { struct i965_driver_data *i965 = NULL; struct object_buffer *obj_buffer = NULL; i965 = i965_driver_data(ctx); obj_buffer = BUFFER(buf_id); assert(obj_buffer); if (!obj_buffer) return VA_STATUS_ERROR_INVALID_BUFFER; *type = obj_buffer->type; *size = obj_buffer->size_element; *num_elements = obj_buffer->num_elements; return VA_STATUS_SUCCESS; } static VAStatus i965_LockSurface( VADriverContextP ctx, /* in */ VASurfaceID surface, /* in */ unsigned int *fourcc, /* out */ unsigned int *luma_stride, /* out */ unsigned int *chroma_u_stride, /* out */ unsigned int *chroma_v_stride, /* out */ unsigned int *luma_offset, /* out */ unsigned int *chroma_u_offset, /* out */ unsigned int *chroma_v_offset, /* out */ unsigned int *buffer_name, /* out */ void **buffer /* out */ ) { VAStatus vaStatus = VA_STATUS_SUCCESS; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface = NULL; VAImage tmpImage; assert(fourcc); assert(luma_stride); assert(chroma_u_stride); assert(chroma_v_stride); assert(luma_offset); assert(chroma_u_offset); assert(chroma_v_offset); assert(buffer_name); assert(buffer); tmpImage.image_id = VA_INVALID_ID; obj_surface = SURFACE(surface); if (obj_surface == NULL) { // Surface is absent. vaStatus = VA_STATUS_ERROR_INVALID_PARAMETER; goto error; } // Lock functionality is absent now. if (obj_surface->locked_image_id != VA_INVALID_ID) { // Surface is locked already. vaStatus = VA_STATUS_ERROR_INVALID_PARAMETER; goto error; } vaStatus = i965_DeriveImage( ctx, surface, &tmpImage); if (vaStatus != VA_STATUS_SUCCESS) { goto error; } obj_surface->locked_image_id = tmpImage.image_id; vaStatus = i965_MapBuffer( ctx, tmpImage.buf, buffer); if (vaStatus != VA_STATUS_SUCCESS) { goto error; } *fourcc = tmpImage.format.fourcc; *luma_offset = tmpImage.offsets[0]; *luma_stride = tmpImage.pitches[0]; *chroma_u_offset = tmpImage.offsets[1]; *chroma_u_stride = tmpImage.pitches[1]; *chroma_v_offset = tmpImage.offsets[2]; *chroma_v_stride = tmpImage.pitches[2]; *buffer_name = tmpImage.buf; error: if (vaStatus != VA_STATUS_SUCCESS) { buffer = NULL; } return vaStatus; } static VAStatus i965_UnlockSurface( VADriverContextP ctx, /* in */ VASurfaceID surface /* in */ ) { VAStatus vaStatus = VA_STATUS_SUCCESS; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_image *locked_img = NULL; struct object_surface *obj_surface = NULL; obj_surface = SURFACE(surface); if (obj_surface == NULL) { vaStatus = VA_STATUS_ERROR_INVALID_PARAMETER; // Surface is absent return vaStatus; } if (obj_surface->locked_image_id == VA_INVALID_ID) { vaStatus = VA_STATUS_ERROR_INVALID_PARAMETER; // Surface is not locked return vaStatus; } locked_img = IMAGE(obj_surface->locked_image_id); if (locked_img == NULL || (locked_img->image.image_id == VA_INVALID_ID)) { // Work image was deallocated before i965_UnlockSurface() vaStatus = VA_STATUS_ERROR_INVALID_PARAMETER; goto error; } vaStatus = i965_UnmapBuffer( ctx, locked_img->image.buf); if (vaStatus != VA_STATUS_SUCCESS) { goto error; } vaStatus = i965_DestroyImage( ctx, locked_img->image.image_id); if (vaStatus != VA_STATUS_SUCCESS) { goto error; } locked_img->image.image_id = VA_INVALID_ID; error: obj_surface->locked_image_id = VA_INVALID_ID; return vaStatus; } static VAStatus i965_GetSurfaceAttributes( VADriverContextP ctx, VAConfigID config, VASurfaceAttrib *attrib_list, unsigned int num_attribs ) { VAStatus vaStatus = VA_STATUS_SUCCESS; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_config *obj_config; int i; if (config == VA_INVALID_ID) return VA_STATUS_ERROR_INVALID_CONFIG; obj_config = CONFIG(config); if (obj_config == NULL) return VA_STATUS_ERROR_INVALID_CONFIG; if (attrib_list == NULL || num_attribs == 0) return VA_STATUS_ERROR_INVALID_PARAMETER; for (i = 0; i < num_attribs; i++) { switch (attrib_list[i].type) { case VASurfaceAttribPixelFormat: attrib_list[i].value.type = VAGenericValueTypeInteger; attrib_list[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; if (attrib_list[i].value.value.i == 0) { if (IS_G4X(i965->intel.device_id)) { if (obj_config->profile == VAProfileMPEG2Simple || obj_config->profile == VAProfileMPEG2Main) { attrib_list[i].value.value.i = VA_FOURCC('I', '4', '2', '0'); } else { assert(0); attrib_list[i].flags = VA_SURFACE_ATTRIB_NOT_SUPPORTED; } } else if (IS_IRONLAKE(i965->intel.device_id)) { if (obj_config->profile == VAProfileMPEG2Simple || obj_config->profile == VAProfileMPEG2Main) { attrib_list[i].value.value.i = VA_FOURCC('I', '4', '2', '0'); } else if (obj_config->profile == VAProfileH264ConstrainedBaseline || obj_config->profile == VAProfileH264Main || obj_config->profile == VAProfileH264High) { attrib_list[i].value.value.i = VA_FOURCC('N', 'V', '1', '2'); } else if (obj_config->profile == VAProfileNone) { attrib_list[i].value.value.i = VA_FOURCC('N', 'V', '1', '2'); } else { assert(0); attrib_list[i].flags = VA_SURFACE_ATTRIB_NOT_SUPPORTED; } } else if (IS_GEN6(i965->intel.device_id)) { attrib_list[i].value.value.i = VA_FOURCC('N', 'V', '1', '2'); } else if (IS_GEN7(i965->intel.device_id) || IS_GEN8(i965->intel.device_id)) { if (obj_config->profile == VAProfileJPEGBaseline) attrib_list[i].value.value.i = 0; /* internal format */ else attrib_list[i].value.value.i = VA_FOURCC('N', 'V', '1', '2'); } } else { if (IS_G4X(i965->intel.device_id)) { if (obj_config->profile == VAProfileMPEG2Simple || obj_config->profile == VAProfileMPEG2Main) { if (attrib_list[i].value.value.i != VA_FOURCC('I', '4', '2', '0')) { attrib_list[i].value.value.i = 0; attrib_list[i].flags &= ~VA_SURFACE_ATTRIB_SETTABLE; } } else { assert(0); attrib_list[i].flags = VA_SURFACE_ATTRIB_NOT_SUPPORTED; } } else if (IS_IRONLAKE(i965->intel.device_id)) { if (obj_config->profile == VAProfileMPEG2Simple || obj_config->profile == VAProfileMPEG2Main) { if (attrib_list[i].value.value.i != VA_FOURCC('I', '4', '2', '0')) { attrib_list[i].value.value.i = 0; attrib_list[i].flags &= ~VA_SURFACE_ATTRIB_SETTABLE; } } else if (obj_config->profile == VAProfileH264ConstrainedBaseline || obj_config->profile == VAProfileH264Main || obj_config->profile == VAProfileH264High) { if (attrib_list[i].value.value.i != VA_FOURCC('N', 'V', '1', '2')) { attrib_list[i].value.value.i = 0; attrib_list[i].flags &= ~VA_SURFACE_ATTRIB_SETTABLE; } } else if (obj_config->profile == VAProfileNone) { switch (attrib_list[i].value.value.i) { case VA_FOURCC('N', 'V', '1', '2'): case VA_FOURCC('I', '4', '2', '0'): case VA_FOURCC('Y', 'V', '1', '2'): case VA_FOURCC('Y', 'U', 'Y', '2'): case VA_FOURCC('B', 'G', 'R', 'A'): case VA_FOURCC('B', 'G', 'R', 'X'): case VA_FOURCC('R', 'G', 'B', 'X'): case VA_FOURCC('R', 'G', 'B', 'A'): break; default: attrib_list[i].value.value.i = 0; attrib_list[i].flags &= ~VA_SURFACE_ATTRIB_SETTABLE; break; } } else { assert(0); attrib_list[i].flags = VA_SURFACE_ATTRIB_NOT_SUPPORTED; } } else if (IS_GEN6(i965->intel.device_id)) { if (obj_config->entrypoint == VAEntrypointEncSlice || obj_config->entrypoint == VAEntrypointVideoProc) { switch (attrib_list[i].value.value.i) { case VA_FOURCC('N', 'V', '1', '2'): case VA_FOURCC('I', '4', '2', '0'): case VA_FOURCC('Y', 'V', '1', '2'): case VA_FOURCC('Y', 'U', 'Y', '2'): case VA_FOURCC('B', 'G', 'R', 'A'): case VA_FOURCC('B', 'G', 'R', 'X'): case VA_FOURCC('R', 'G', 'B', 'X'): case VA_FOURCC('R', 'G', 'B', 'A'): break; default: attrib_list[i].value.value.i = 0; attrib_list[i].flags &= ~VA_SURFACE_ATTRIB_SETTABLE; break; } } else { if (attrib_list[i].value.value.i != VA_FOURCC('N', 'V', '1', '2')) { attrib_list[i].value.value.i = 0; attrib_list[i].flags &= ~VA_SURFACE_ATTRIB_SETTABLE; } } } else if (IS_GEN7(i965->intel.device_id) || IS_GEN8(i965->intel.device_id)) { if (obj_config->entrypoint == VAEntrypointEncSlice || obj_config->entrypoint == VAEntrypointVideoProc) { switch (attrib_list[i].value.value.i) { case VA_FOURCC('N', 'V', '1', '2'): case VA_FOURCC('I', '4', '2', '0'): case VA_FOURCC('Y', 'V', '1', '2'): break; default: attrib_list[i].value.value.i = 0; attrib_list[i].flags &= ~VA_SURFACE_ATTRIB_SETTABLE; break; } } else { if (obj_config->profile == VAProfileJPEGBaseline) { attrib_list[i].value.value.i = 0; /* JPEG decoding always uses an internal format */ attrib_list[i].flags &= ~VA_SURFACE_ATTRIB_SETTABLE; } else { if (attrib_list[i].value.value.i != VA_FOURCC('N', 'V', '1', '2')) { attrib_list[i].value.value.i = 0; attrib_list[i].flags &= ~VA_SURFACE_ATTRIB_SETTABLE; } } } } } break; case VASurfaceAttribMinWidth: /* FIXME: add support for it later */ attrib_list[i].flags = VA_SURFACE_ATTRIB_NOT_SUPPORTED; break; case VASurfaceAttribMaxWidth: attrib_list[i].flags = VA_SURFACE_ATTRIB_NOT_SUPPORTED; break; case VASurfaceAttribMinHeight: attrib_list[i].flags = VA_SURFACE_ATTRIB_NOT_SUPPORTED; break; case VASurfaceAttribMaxHeight: attrib_list[i].flags = VA_SURFACE_ATTRIB_NOT_SUPPORTED; break; default: attrib_list[i].flags = VA_SURFACE_ATTRIB_NOT_SUPPORTED; break; } } return vaStatus; } static VAStatus i965_QuerySurfaceAttributes(VADriverContextP ctx, VAConfigID config, VASurfaceAttrib *attrib_list, unsigned int *num_attribs) { VAStatus vaStatus = VA_STATUS_SUCCESS; struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_config *obj_config; int i = 0; VASurfaceAttrib *attribs = NULL; if (config == VA_INVALID_ID) return VA_STATUS_ERROR_INVALID_CONFIG; obj_config = CONFIG(config); if (obj_config == NULL) return VA_STATUS_ERROR_INVALID_CONFIG; if (!attrib_list && !num_attribs) return VA_STATUS_ERROR_INVALID_PARAMETER; if (attrib_list == NULL) { *num_attribs = I965_MAX_SURFACE_ATTRIBUTES; return VA_STATUS_SUCCESS; } attribs = malloc(I965_MAX_SURFACE_ATTRIBUTES *sizeof(*attribs)); if (attribs == NULL) return VA_STATUS_ERROR_ALLOCATION_FAILED; if (IS_G4X(i965->intel.device_id)) { if (obj_config->profile == VAProfileMPEG2Simple || obj_config->profile == VAProfileMPEG2Main) { attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('I', '4', '2', '0'); i++; } } else if (IS_IRONLAKE(i965->intel.device_id)) { switch (obj_config->profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('I', '4', '2', '0'); i++; break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('N', 'V', '1', '2'); i++; case VAProfileNone: attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('N', 'V', '1', '2'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('I', '4', '2', '0'); i++; break; default: break; } } else if (IS_GEN6(i965->intel.device_id)) { if (obj_config->entrypoint == VAEntrypointVLD) { /* decode */ attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('N', 'V', '1', '2'); i++; } else if (obj_config->entrypoint == VAEntrypointEncSlice || /* encode */ obj_config->entrypoint == VAEntrypointVideoProc) { /* vpp */ attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('N', 'V', '1', '2'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('I', '4', '2', '0'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('Y', 'V', '1', '2'); i++; if (obj_config->entrypoint == VAEntrypointVideoProc) { attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('Y', 'U', 'Y', '2'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('R', 'G', 'B', 'A'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('R', 'G', 'B', 'X'); i++; } } } else if (IS_GEN7(i965->intel.device_id)) { if (obj_config->entrypoint == VAEntrypointVLD) { /* decode */ if (obj_config->profile == VAProfileJPEGBaseline) { attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('I', 'M', 'C', '3'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('I', 'M', 'C', '1'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('Y', '8', '0', '0'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('4', '1', '1', 'P'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('4', '2', '2', 'H'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('4', '2', '2', 'V'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('4', '4', '4', 'P'); i++; } else { attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('N', 'V', '1', '2'); i++; } } else if (obj_config->entrypoint == VAEntrypointEncSlice || /* encode */ obj_config->entrypoint == VAEntrypointVideoProc) { /* vpp */ attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('N', 'V', '1', '2'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('I', '4', '2', '0'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('Y', 'V', '1', '2'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('I', 'M', 'C', '3'); i++; if (obj_config->entrypoint == VAEntrypointVideoProc) { attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('Y', 'U', 'Y', '2'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('R', 'G', 'B', 'A'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('R', 'G', 'B', 'X'); i++; } } } else if (IS_GEN8(i965->intel.device_id)) { if (obj_config->entrypoint == VAEntrypointVLD) { /* decode */ if (obj_config->profile == VAProfileJPEGBaseline) { attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('I', 'M', 'C', '3'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('I', 'M', 'C', '1'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('Y', '8', '0', '0'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('4', '1', '1', 'P'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('4', '2', '2', 'H'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('4', '2', '2', 'V'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('4', '4', '4', 'P'); i++; } else { attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('N', 'V', '1', '2'); i++; } } else if (obj_config->entrypoint == VAEntrypointEncSlice || /* encode */ obj_config->entrypoint == VAEntrypointVideoProc) { /* vpp */ attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('N', 'V', '1', '2'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('I', '4', '2', '0'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('Y', 'V', '1', '2'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('I', 'M', 'C', '3'); i++; if (obj_config->entrypoint == VAEntrypointVideoProc) { attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('Y', 'U', 'Y', '2'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('R', 'G', 'B', 'A'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('R', 'G', 'B', 'X'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('B', 'G', 'R', 'A'); i++; attribs[i].type = VASurfaceAttribPixelFormat; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_FOURCC('B', 'G', 'R', 'X'); i++; } } } attribs[i].type = VASurfaceAttribMemoryType; attribs[i].value.type = VAGenericValueTypeInteger; attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.i = VA_SURFACE_ATTRIB_MEM_TYPE_VA | VA_SURFACE_ATTRIB_MEM_TYPE_KERNEL_DRM | VA_SURFACE_ATTRIB_MEM_TYPE_DRM_PRIME; i++; attribs[i].type = VASurfaceAttribExternalBufferDescriptor; attribs[i].value.type = VAGenericValueTypePointer; attribs[i].flags = VA_SURFACE_ATTRIB_SETTABLE; attribs[i].value.value.p = NULL; /* ignore */ i++; if (i > *num_attribs) { *num_attribs = i; free(attribs); return VA_STATUS_ERROR_MAX_NUM_EXCEEDED; } *num_attribs = i; memcpy(attrib_list, attribs, i * sizeof(*attribs)); free(attribs); return vaStatus; } static int i965_os_has_ring_support(VADriverContextP ctx, int ring) { struct i965_driver_data *const i965 = i965_driver_data(ctx); switch (ring) { case I965_RING_BSD: return i965->intel.has_bsd; case I965_RING_BLT: return i965->intel.has_blt; case I965_RING_VEBOX: return i965->intel.has_vebox; case I965_RING_NULL: return 1; /* Always support */ default: /* should never get here */ assert(0); break; } return 0; } /* * Query video processing pipeline */ VAStatus i965_QueryVideoProcFilters( VADriverContextP ctx, VAContextID context, VAProcFilterType *filters, unsigned int *num_filters ) { struct i965_driver_data *const i965 = i965_driver_data(ctx); unsigned int i = 0, num = 0; if (!num_filters || !filters) return VA_STATUS_ERROR_INVALID_PARAMETER; for (i = 0; i < i965->codec_info->num_filters; i++) { if (i965_os_has_ring_support(ctx, i965->codec_info->filters[i].ring)) { if (num == *num_filters) { *num_filters = i965->codec_info->num_filters; return VA_STATUS_ERROR_MAX_NUM_EXCEEDED; } filters[num++] = i965->codec_info->filters[i].type; } } *num_filters = num; return VA_STATUS_SUCCESS; } VAStatus i965_QueryVideoProcFilterCaps( VADriverContextP ctx, VAContextID context, VAProcFilterType type, void *filter_caps, unsigned int *num_filter_caps ) { unsigned int i = 0; struct i965_driver_data *const i965 = i965_driver_data(ctx); if (!filter_caps || !num_filter_caps) return VA_STATUS_ERROR_INVALID_PARAMETER; for (i = 0; i < i965->codec_info->num_filters; i++) { if (type == i965->codec_info->filters[i].type && i965_os_has_ring_support(ctx, i965->codec_info->filters[i].ring)) break; } if (i == i965->codec_info->num_filters) return VA_STATUS_ERROR_UNSUPPORTED_FILTER; i = 0; switch (type) { case VAProcFilterNoiseReduction: case VAProcFilterSharpening: { VAProcFilterCap *cap = filter_caps; if (*num_filter_caps < 1) { *num_filter_caps = 1; return VA_STATUS_ERROR_MAX_NUM_EXCEEDED; } cap->range.min_value = 0.0; cap->range.max_value = 1.0; cap->range.default_value = 0.5; cap->range.step = 0.03125; /* 1.0 / 32 */ i++; } break; case VAProcFilterDeinterlacing: { VAProcFilterCapDeinterlacing *cap = filter_caps; if (*num_filter_caps < VAProcDeinterlacingCount) { *num_filter_caps = VAProcDeinterlacingCount; return VA_STATUS_ERROR_MAX_NUM_EXCEEDED; } cap->type = VAProcDeinterlacingBob; i++; cap++; if (i965->codec_info->has_di_motion_adptive) { cap->type = VAProcDeinterlacingMotionAdaptive; i++; cap++; } if (i965->codec_info->has_di_motion_compensated) { cap->type = VAProcDeinterlacingMotionCompensated; i++; cap++; } } break; case VAProcFilterColorBalance: { VAProcFilterCapColorBalance *cap = filter_caps; if (*num_filter_caps < VAProcColorBalanceCount) { *num_filter_caps = VAProcColorBalanceCount; return VA_STATUS_ERROR_MAX_NUM_EXCEEDED; } cap->type = VAProcColorBalanceHue; cap->range.min_value = -180.0; cap->range.max_value = 180.0; cap->range.default_value = 0.0; cap->range.step = 1.0; i++; cap++; cap->type = VAProcColorBalanceSaturation; cap->range.min_value = 0.0; cap->range.max_value = 10.0; cap->range.default_value = 1.0; cap->range.step = 0.1; i++; cap++; cap->type = VAProcColorBalanceBrightness; cap->range.min_value = -100.0; cap->range.max_value = 100.0; cap->range.default_value = 0.0; cap->range.step = 1.0; i++; cap++; cap->type = VAProcColorBalanceContrast; cap->range.min_value = 0.0; cap->range.max_value = 10.0; cap->range.default_value = 1.0; cap->range.step = 0.1; i++; cap++; } break; default: break; } *num_filter_caps = i; return VA_STATUS_SUCCESS; } static VAProcColorStandardType vpp_input_color_standards[VAProcColorStandardCount] = { VAProcColorStandardBT601, }; static VAProcColorStandardType vpp_output_color_standards[VAProcColorStandardCount] = { VAProcColorStandardBT601, }; VAStatus i965_QueryVideoProcPipelineCaps( VADriverContextP ctx, VAContextID context, VABufferID *filters, unsigned int num_filters, VAProcPipelineCaps *pipeline_cap /* out */ ) { struct i965_driver_data * const i965 = i965_driver_data(ctx); unsigned int i = 0; pipeline_cap->pipeline_flags = 0; pipeline_cap->filter_flags = 0; pipeline_cap->num_forward_references = 0; pipeline_cap->num_backward_references = 0; pipeline_cap->num_input_color_standards = 1; pipeline_cap->input_color_standards = vpp_input_color_standards; pipeline_cap->num_output_color_standards = 1; pipeline_cap->output_color_standards = vpp_output_color_standards; for (i = 0; i < num_filters; i++) { struct object_buffer *obj_buffer = BUFFER(filters[i]); if (!obj_buffer || !obj_buffer->buffer_store || !obj_buffer->buffer_store->buffer) return VA_STATUS_ERROR_INVALID_BUFFER; VAProcFilterParameterBufferBase *base = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer; if (base->type == VAProcFilterNoiseReduction) { VAProcFilterParameterBuffer *denoise = (VAProcFilterParameterBuffer *)base; (void)denoise; } else if (base->type == VAProcFilterDeinterlacing) { VAProcFilterParameterBufferDeinterlacing *deint = (VAProcFilterParameterBufferDeinterlacing *)base; assert(deint->algorithm == VAProcDeinterlacingBob || deint->algorithm == VAProcDeinterlacingMotionAdaptive || deint->algorithm == VAProcDeinterlacingMotionCompensated); if (deint->algorithm == VAProcDeinterlacingMotionAdaptive || deint->algorithm == VAProcDeinterlacingMotionCompensated); pipeline_cap->num_forward_references++; } } return VA_STATUS_SUCCESS; } static bool i965_driver_data_init(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); if (IS_GEN8(i965->intel.device_id)) i965->codec_info = &gen8_hw_codec_info; else if (IS_HASWELL(i965->intel.device_id)) i965->codec_info = &gen75_hw_codec_info; else if (IS_G4X(i965->intel.device_id)) i965->codec_info = &g4x_hw_codec_info; else if (IS_IRONLAKE(i965->intel.device_id)) i965->codec_info = &ironlake_hw_codec_info; else if (IS_GEN6(i965->intel.device_id)) i965->codec_info = &gen6_hw_codec_info; else if (IS_GEN7(i965->intel.device_id)) i965->codec_info = &gen7_hw_codec_info; else return false; if (object_heap_init(&i965->config_heap, sizeof(struct object_config), CONFIG_ID_OFFSET)) goto err_config_heap; if (object_heap_init(&i965->context_heap, sizeof(struct object_context), CONTEXT_ID_OFFSET)) goto err_context_heap; if (object_heap_init(&i965->surface_heap, sizeof(struct object_surface), SURFACE_ID_OFFSET)) goto err_surface_heap; if (object_heap_init(&i965->buffer_heap, sizeof(struct object_buffer), BUFFER_ID_OFFSET)) goto err_buffer_heap; if (object_heap_init(&i965->image_heap, sizeof(struct object_image), IMAGE_ID_OFFSET)) goto err_image_heap; if (object_heap_init(&i965->subpic_heap, sizeof(struct object_subpic), SUBPIC_ID_OFFSET)) goto err_subpic_heap; i965->batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_RENDER, 0); i965->pp_batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_RENDER, 0); _i965InitMutex(&i965->render_mutex); _i965InitMutex(&i965->pp_mutex); return true; err_subpic_heap: object_heap_destroy(&i965->image_heap); err_image_heap: object_heap_destroy(&i965->buffer_heap); err_buffer_heap: object_heap_destroy(&i965->surface_heap); err_surface_heap: object_heap_destroy(&i965->context_heap); err_context_heap: object_heap_destroy(&i965->config_heap); err_config_heap: return false; } static void i965_driver_data_terminate(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); _i965DestroyMutex(&i965->pp_mutex); _i965DestroyMutex(&i965->render_mutex); if (i965->batch) intel_batchbuffer_free(i965->batch); if (i965->pp_batch) intel_batchbuffer_free(i965->pp_batch); i965_destroy_heap(&i965->subpic_heap, i965_destroy_subpic); i965_destroy_heap(&i965->image_heap, i965_destroy_image); i965_destroy_heap(&i965->buffer_heap, i965_destroy_buffer); i965_destroy_heap(&i965->surface_heap, i965_destroy_surface); i965_destroy_heap(&i965->context_heap, i965_destroy_context); i965_destroy_heap(&i965->config_heap, i965_destroy_config); } struct { bool (*init)(VADriverContextP ctx); void (*terminate)(VADriverContextP ctx); int display_type; } i965_sub_ops[] = { { intel_driver_init, intel_driver_terminate, 0, }, { i965_driver_data_init, i965_driver_data_terminate, 0, }, { i965_display_attributes_init, i965_display_attributes_terminate, 0, }, { i965_post_processing_init, i965_post_processing_terminate, 0, }, { i965_render_init, i965_render_terminate, 0, }, #ifdef HAVE_VA_WAYLAND { i965_output_wayland_init, i965_output_wayland_terminate, VA_DISPLAY_WAYLAND, }, #endif #ifdef HAVE_VA_X11 { i965_output_dri_init, i965_output_dri_terminate, VA_DISPLAY_X11, }, #endif }; static VAStatus i965_Init(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); int i; for (i = 0; i < ARRAY_ELEMS(i965_sub_ops); i++) { if ((i965_sub_ops[i].display_type == 0 || i965_sub_ops[i].display_type == (ctx->display_type & VA_DISPLAY_MAJOR_MASK)) && !i965_sub_ops[i].init(ctx)) break; } if (i == ARRAY_ELEMS(i965_sub_ops)) { sprintf(i965->va_vendor, "%s %s driver - %d.%d.%d", INTEL_STR_DRIVER_VENDOR, INTEL_STR_DRIVER_NAME, INTEL_DRIVER_MAJOR_VERSION, INTEL_DRIVER_MINOR_VERSION, INTEL_DRIVER_MICRO_VERSION); if (INTEL_DRIVER_PRE_VERSION > 0) { const int len = strlen(i965->va_vendor); sprintf(&i965->va_vendor[len], ".pre%d", INTEL_DRIVER_PRE_VERSION); } i965->current_context_id = VA_INVALID_ID; return VA_STATUS_SUCCESS; } else { i--; for (; i >= 0; i--) { if (i965_sub_ops[i].display_type == 0 || i965_sub_ops[i].display_type == (ctx->display_type & VA_DISPLAY_MAJOR_MASK)) { i965_sub_ops[i].terminate(ctx); } } return VA_STATUS_ERROR_UNKNOWN; } } VAStatus i965_Terminate(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); int i; if (i965) { for (i = ARRAY_ELEMS(i965_sub_ops); i > 0; i--) if (i965_sub_ops[i - 1].display_type == 0 || i965_sub_ops[i - 1].display_type == (ctx->display_type & VA_DISPLAY_MAJOR_MASK)) { i965_sub_ops[i - 1].terminate(ctx); } free(i965); ctx->pDriverData = NULL; } return VA_STATUS_SUCCESS; } VAStatus DLL_EXPORT VA_DRIVER_INIT_FUNC(VADriverContextP ctx); VAStatus VA_DRIVER_INIT_FUNC( VADriverContextP ctx ) { struct VADriverVTable * const vtable = ctx->vtable; struct VADriverVTableVPP * const vtable_vpp = ctx->vtable_vpp; struct i965_driver_data *i965; VAStatus ret = VA_STATUS_ERROR_UNKNOWN; ctx->version_major = VA_MAJOR_VERSION; ctx->version_minor = VA_MINOR_VERSION; ctx->max_profiles = I965_MAX_PROFILES; ctx->max_entrypoints = I965_MAX_ENTRYPOINTS; ctx->max_attributes = I965_MAX_CONFIG_ATTRIBUTES; ctx->max_image_formats = I965_MAX_IMAGE_FORMATS; ctx->max_subpic_formats = I965_MAX_SUBPIC_FORMATS; ctx->max_display_attributes = 1 + ARRAY_ELEMS(i965_display_attributes); vtable->vaTerminate = i965_Terminate; vtable->vaQueryConfigEntrypoints = i965_QueryConfigEntrypoints; vtable->vaQueryConfigProfiles = i965_QueryConfigProfiles; vtable->vaQueryConfigEntrypoints = i965_QueryConfigEntrypoints; vtable->vaQueryConfigAttributes = i965_QueryConfigAttributes; vtable->vaCreateConfig = i965_CreateConfig; vtable->vaDestroyConfig = i965_DestroyConfig; vtable->vaGetConfigAttributes = i965_GetConfigAttributes; vtable->vaCreateSurfaces = i965_CreateSurfaces; vtable->vaDestroySurfaces = i965_DestroySurfaces; vtable->vaCreateContext = i965_CreateContext; vtable->vaDestroyContext = i965_DestroyContext; vtable->vaCreateBuffer = i965_CreateBuffer; vtable->vaBufferSetNumElements = i965_BufferSetNumElements; vtable->vaMapBuffer = i965_MapBuffer; vtable->vaUnmapBuffer = i965_UnmapBuffer; vtable->vaDestroyBuffer = i965_DestroyBuffer; vtable->vaBeginPicture = i965_BeginPicture; vtable->vaRenderPicture = i965_RenderPicture; vtable->vaEndPicture = i965_EndPicture; vtable->vaSyncSurface = i965_SyncSurface; vtable->vaQuerySurfaceStatus = i965_QuerySurfaceStatus; vtable->vaPutSurface = i965_PutSurface; vtable->vaQueryImageFormats = i965_QueryImageFormats; vtable->vaCreateImage = i965_CreateImage; vtable->vaDeriveImage = i965_DeriveImage; vtable->vaDestroyImage = i965_DestroyImage; vtable->vaSetImagePalette = i965_SetImagePalette; vtable->vaGetImage = i965_GetImage; vtable->vaPutImage = i965_PutImage; vtable->vaQuerySubpictureFormats = i965_QuerySubpictureFormats; vtable->vaCreateSubpicture = i965_CreateSubpicture; vtable->vaDestroySubpicture = i965_DestroySubpicture; vtable->vaSetSubpictureImage = i965_SetSubpictureImage; vtable->vaSetSubpictureChromakey = i965_SetSubpictureChromakey; vtable->vaSetSubpictureGlobalAlpha = i965_SetSubpictureGlobalAlpha; vtable->vaAssociateSubpicture = i965_AssociateSubpicture; vtable->vaDeassociateSubpicture = i965_DeassociateSubpicture; vtable->vaQueryDisplayAttributes = i965_QueryDisplayAttributes; vtable->vaGetDisplayAttributes = i965_GetDisplayAttributes; vtable->vaSetDisplayAttributes = i965_SetDisplayAttributes; vtable->vaBufferInfo = i965_BufferInfo; vtable->vaLockSurface = i965_LockSurface; vtable->vaUnlockSurface = i965_UnlockSurface; vtable->vaGetSurfaceAttributes = i965_GetSurfaceAttributes; vtable->vaQuerySurfaceAttributes = i965_QuerySurfaceAttributes; vtable->vaCreateSurfaces2 = i965_CreateSurfaces2; vtable_vpp->vaQueryVideoProcFilters = i965_QueryVideoProcFilters; vtable_vpp->vaQueryVideoProcFilterCaps = i965_QueryVideoProcFilterCaps; vtable_vpp->vaQueryVideoProcPipelineCaps = i965_QueryVideoProcPipelineCaps; i965 = (struct i965_driver_data *)calloc(1, sizeof(*i965)); if (i965 == NULL) { ctx->pDriverData = NULL; return VA_STATUS_ERROR_ALLOCATION_FAILED; } ctx->pDriverData = (void *)i965; ret = i965_Init(ctx); if (ret == VA_STATUS_SUCCESS) { ctx->str_vendor = i965->va_vendor; } else { free(i965); ctx->pDriverData = NULL; } return ret; } intel-driver-1.3.0/src/i965_drv_video.h000066400000000000000000000277351231401140700176230ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * Zou Nan hai * */ #ifndef _I965_DRV_VIDEO_H_ #define _I965_DRV_VIDEO_H_ #include #include #include #include #include #include #include "i965_mutext.h" #include "object_heap.h" #include "intel_driver.h" #define I965_MAX_PROFILES 20 #define I965_MAX_ENTRYPOINTS 5 #define I965_MAX_CONFIG_ATTRIBUTES 10 #define I965_MAX_IMAGE_FORMATS 10 #define I965_MAX_SUBPIC_FORMATS 6 #define I965_MAX_SUBPIC_SUM 4 #define I965_MAX_SURFACE_ATTRIBUTES 16 #define INTEL_STR_DRIVER_VENDOR "Intel" #define INTEL_STR_DRIVER_NAME "i965" #define I965_SURFACE_TYPE_IMAGE 0 #define I965_SURFACE_TYPE_SURFACE 1 #define I965_SURFACE_FLAG_FRAME 0x00000000 #define I965_SURFACE_FLAG_TOP_FIELD_FIRST 0x00000001 #define I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST 0x00000002 #define DEFAULT_BRIGHTNESS 0 #define DEFAULT_CONTRAST 50 #define DEFAULT_HUE 0 #define DEFAULT_SATURATION 50 struct i965_surface { struct object_base *base; int type; int flags; }; struct i965_kernel { char *name; int interface; const uint32_t (*bin)[4]; int size; dri_bo *bo; unsigned int kernel_offset; }; struct buffer_store { unsigned char *buffer; dri_bo *bo; int ref_count; int num_elements; }; struct object_config { struct object_base base; VAProfile profile; VAEntrypoint entrypoint; VAConfigAttrib attrib_list[I965_MAX_CONFIG_ATTRIBUTES]; int num_attribs; }; #define NUM_SLICES 10 struct decode_state { struct buffer_store *pic_param; struct buffer_store **slice_params; struct buffer_store *iq_matrix; struct buffer_store *bit_plane; struct buffer_store *huffman_table; struct buffer_store **slice_datas; struct buffer_store *probability_data; VASurfaceID current_render_target; int max_slice_params; int max_slice_datas; int num_slice_params; int num_slice_datas; struct object_surface *render_object; struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/ }; struct encode_state { struct buffer_store *seq_param; struct buffer_store *pic_param; struct buffer_store *pic_control; struct buffer_store *iq_matrix; struct buffer_store *q_matrix; struct buffer_store **slice_params; int max_slice_params; int num_slice_params; /* for ext */ struct buffer_store *seq_param_ext; struct buffer_store *pic_param_ext; struct buffer_store *packed_header_param[4]; struct buffer_store *packed_header_data[4]; struct buffer_store **slice_params_ext; int max_slice_params_ext; int num_slice_params_ext; int last_packed_header_type; struct buffer_store *misc_param[16]; VASurfaceID current_render_target; struct object_surface *input_yuv_object; struct object_surface *reconstructed_object; struct object_buffer *coded_buf_object; struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/ }; struct proc_state { struct buffer_store *pipeline_param; VASurfaceID current_render_target; }; #define CODEC_DEC 0 #define CODEC_ENC 1 #define CODEC_PROC 2 union codec_state { struct decode_state decode; struct encode_state encode; struct proc_state proc; }; struct hw_context { VAStatus (*run)(VADriverContextP ctx, VAProfile profile, union codec_state *codec_state, struct hw_context *hw_context); void (*destroy)(void *); struct intel_batchbuffer *batch; }; struct object_context { struct object_base base; VAContextID context_id; struct object_config *obj_config; VASurfaceID *render_targets; //input->encode, output->decode int num_render_targets; int picture_width; int picture_height; int flags; int codec_type; union codec_state codec_state; struct hw_context *hw_context; }; #define SURFACE_REFERENCED (1 << 0) #define SURFACE_DISPLAYED (1 << 1) #define SURFACE_DERIVED (1 << 2) #define SURFACE_REF_DIS_MASK ((SURFACE_REFERENCED) | \ (SURFACE_DISPLAYED)) #define SURFACE_ALL_MASK ((SURFACE_REFERENCED) | \ (SURFACE_DISPLAYED) | \ (SURFACE_DERIVED)) struct object_surface { struct object_base base; VASurfaceStatus status; VASubpictureID subpic[I965_MAX_SUBPIC_SUM]; struct object_subpic *obj_subpic[I965_MAX_SUBPIC_SUM]; unsigned int subpic_render_idx; int width; /* the pitch of plane 0 in bytes in horizontal direction */ int height; /* the pitch of plane 0 in bytes in vertical direction */ int size; int orig_width; /* the width of plane 0 in pixels */ int orig_height; /* the height of plane 0 in pixels */ int flags; unsigned int fourcc; dri_bo *bo; VAImageID locked_image_id; void (*free_private_data)(void **data); void *private_data; unsigned int subsampling; int x_cb_offset; int y_cb_offset; int x_cr_offset; int y_cr_offset; int cb_cr_width; int cb_cr_height; int cb_cr_pitch; }; struct object_buffer { struct object_base base; struct buffer_store *buffer_store; int max_num_elements; int num_elements; int size_element; VABufferType type; }; struct object_image { struct object_base base; VAImage image; dri_bo *bo; unsigned int *palette; VASurfaceID derived_surface; }; struct object_subpic { struct object_base base; VAImageID image; struct object_image *obj_image; VARectangle src_rect; VARectangle dst_rect; unsigned int format; int width; int height; int pitch; float global_alpha; dri_bo *bo; unsigned int flags; }; #define I965_RING_NULL 0 #define I965_RING_BSD 1 #define I965_RING_BLT 2 #define I965_RING_VEBOX 3 struct i965_filter { VAProcFilterType type; int ring; }; struct hw_codec_info { struct hw_context *(*dec_hw_context_init)(VADriverContextP, struct object_config *); struct hw_context *(*enc_hw_context_init)(VADriverContextP, struct object_config *); struct hw_context *(*proc_hw_context_init)(VADriverContextP, struct object_config *); int max_width; int max_height; unsigned int has_mpeg2_decoding:1; unsigned int has_mpeg2_encoding:1; unsigned int has_h264_decoding:1; unsigned int has_h264_encoding:1; unsigned int has_vc1_decoding:1; unsigned int has_vc1_encoding:1; unsigned int has_jpeg_decoding:1; unsigned int has_jpeg_encoding:1; unsigned int has_vpp:1; unsigned int has_accelerated_getimage:1; unsigned int has_accelerated_putimage:1; unsigned int has_tiled_surface:1; unsigned int has_di_motion_adptive:1; unsigned int has_di_motion_compensated:1; unsigned int has_vp8_decoding:1; unsigned int has_vp8_encoding:1; unsigned int num_filters; struct i965_filter filters[VAProcFilterCount]; }; #include "i965_render.h" struct i965_driver_data { struct intel_driver_data intel; struct object_heap config_heap; struct object_heap context_heap; struct object_heap surface_heap; struct object_heap buffer_heap; struct object_heap image_heap; struct object_heap subpic_heap; struct hw_codec_info *codec_info; _I965Mutex render_mutex; _I965Mutex pp_mutex; struct intel_batchbuffer *batch; struct intel_batchbuffer *pp_batch; struct i965_render_state render_state; void *pp_context; char va_vendor[256]; VADisplayAttribute *display_attributes; unsigned int num_display_attributes; VADisplayAttribute *rotation_attrib; VADisplayAttribute *brightness_attrib; VADisplayAttribute *contrast_attrib; VADisplayAttribute *hue_attrib; VADisplayAttribute *saturation_attrib; VAContextID current_context_id; /* VA/DRI (X11) specific data */ struct va_dri_output *dri_output; /* VA/Wayland specific data */ struct va_wl_output *wl_output; }; #define NEW_CONFIG_ID() object_heap_allocate(&i965->config_heap); #define NEW_CONTEXT_ID() object_heap_allocate(&i965->context_heap); #define NEW_SURFACE_ID() object_heap_allocate(&i965->surface_heap); #define NEW_BUFFER_ID() object_heap_allocate(&i965->buffer_heap); #define NEW_IMAGE_ID() object_heap_allocate(&i965->image_heap); #define NEW_SUBPIC_ID() object_heap_allocate(&i965->subpic_heap); #define CONFIG(id) ((struct object_config *)object_heap_lookup(&i965->config_heap, id)) #define CONTEXT(id) ((struct object_context *)object_heap_lookup(&i965->context_heap, id)) #define SURFACE(id) ((struct object_surface *)object_heap_lookup(&i965->surface_heap, id)) #define BUFFER(id) ((struct object_buffer *)object_heap_lookup(&i965->buffer_heap, id)) #define IMAGE(id) ((struct object_image *)object_heap_lookup(&i965->image_heap, id)) #define SUBPIC(id) ((struct object_subpic *)object_heap_lookup(&i965->subpic_heap, id)) #define FOURCC_IA44 0x34344149 #define FOURCC_AI44 0x34344941 #define STRIDE(w) (((w) + 0xf) & ~0xf) #define SIZE_YUV420(w, h) (h * (STRIDE(w) + STRIDE(w >> 1))) static INLINE struct i965_driver_data * i965_driver_data(VADriverContextP ctx) { return (struct i965_driver_data *)(ctx->pDriverData); } void i965_check_alloc_surface_bo(VADriverContextP ctx, struct object_surface *obj_surface, int tiled, unsigned int fourcc, unsigned int subsampling); int va_enc_packed_type_to_idx(int packed_type); /* reserve 2 byte for internal using */ #define CODEC_H264 0 #define CODEC_MPEG2 1 #define H264_DELIMITER0 0x00 #define H264_DELIMITER1 0x00 #define H264_DELIMITER2 0x00 #define H264_DELIMITER3 0x00 #define H264_DELIMITER4 0x00 #define MPEG2_DELIMITER0 0x00 #define MPEG2_DELIMITER1 0x00 #define MPEG2_DELIMITER2 0x00 #define MPEG2_DELIMITER3 0x00 #define MPEG2_DELIMITER4 0xb0 struct i965_coded_buffer_segment { VACodedBufferSegment base; unsigned char mapped; unsigned char codec; }; #define I965_CODEDBUFFER_HEADER_SIZE ALIGN(sizeof(struct i965_coded_buffer_segment), 64) extern VAStatus i965_MapBuffer(VADriverContextP ctx, VABufferID buf_id, /* in */ void **pbuf); /* out */ extern VAStatus i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id); #define I965_SURFACE_MEM_NATIVE 0 #define I965_SURFACE_MEM_GEM_FLINK 1 #define I965_SURFACE_MEM_DRM_PRIME 2 #endif /* _I965_DRV_VIDEO_H_ */ intel-driver-1.3.0/src/i965_encoder.c000066400000000000000000000344251231401140700172460ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Zhou Chang * */ #include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_encoder.h" #include "gen6_vme.h" #include "gen6_mfc.h" extern Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context); extern Bool gen6_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context); extern Bool gen7_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context); VAStatus i965_DestroySurfaces(VADriverContextP ctx, VASurfaceID *surface_list, int num_surfaces); VAStatus i965_CreateSurfaces(VADriverContextP ctx, int width, int height, int format, int num_surfaces, VASurfaceID *surfaces); static VAStatus intel_encoder_check_yuv_surface(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_surface src_surface, dst_surface; struct object_surface *obj_surface; VAStatus status; VARectangle rect; /* releae the temporary surface */ if (encoder_context->is_tmp_id) { i965_DestroySurfaces(ctx, &encoder_context->input_yuv_surface, 1); encode_state->input_yuv_object = NULL; } encoder_context->is_tmp_id = 0; obj_surface = SURFACE(encode_state->current_render_target); assert(obj_surface && obj_surface->bo); if (!obj_surface || !obj_surface->bo) return VA_STATUS_ERROR_INVALID_PARAMETER; if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')) { unsigned int tiling = 0, swizzle = 0; dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); if (tiling == I915_TILING_Y) { encoder_context->input_yuv_surface = encode_state->current_render_target; encode_state->input_yuv_object = obj_surface; return VA_STATUS_SUCCESS; } } rect.x = 0; rect.y = 0; rect.width = obj_surface->orig_width; rect.height = obj_surface->orig_height; src_surface.base = (struct object_base *)obj_surface; src_surface.type = I965_SURFACE_TYPE_SURFACE; src_surface.flags = I965_SURFACE_FLAG_FRAME; status = i965_CreateSurfaces(ctx, obj_surface->orig_width, obj_surface->orig_height, VA_RT_FORMAT_YUV420, 1, &encoder_context->input_yuv_surface); assert(status == VA_STATUS_SUCCESS); if (status != VA_STATUS_SUCCESS) return status; obj_surface = SURFACE(encoder_context->input_yuv_surface); encode_state->input_yuv_object = obj_surface; assert(obj_surface); i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420); dst_surface.base = (struct object_base *)obj_surface; dst_surface.type = I965_SURFACE_TYPE_SURFACE; dst_surface.flags = I965_SURFACE_FLAG_FRAME; status = i965_image_processing(ctx, &src_surface, &rect, &dst_surface, &rect); assert(status == VA_STATUS_SUCCESS); encoder_context->is_tmp_id = 1; return VA_STATUS_SUCCESS; } static VAStatus intel_encoder_check_avc_parameter(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct object_surface *obj_surface; struct object_buffer *obj_buffer; VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; int i; assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID)); if (pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID) goto error; obj_surface = SURFACE(pic_param->CurrPic.picture_id); assert(obj_surface); /* It is possible the store buffer isn't allocated yet */ if (!obj_surface) goto error; encode_state->reconstructed_object = obj_surface; obj_buffer = BUFFER(pic_param->coded_buf); assert(obj_buffer && obj_buffer->buffer_store && obj_buffer->buffer_store->bo); if (!obj_buffer || !obj_buffer->buffer_store || !obj_buffer->buffer_store->bo) goto error; encode_state->coded_buf_object = obj_buffer; for (i = 0; i < 16; i++) { if (pic_param->ReferenceFrames[i].flags & VA_PICTURE_H264_INVALID || pic_param->ReferenceFrames[i].picture_id == VA_INVALID_SURFACE) break; else { obj_surface = SURFACE(pic_param->ReferenceFrames[i].picture_id); assert(obj_surface); if (!obj_surface) goto error; if (obj_surface->bo) encode_state->reference_objects[i] = obj_surface; else encode_state->reference_objects[i] = NULL; /* FIXME: Warning or Error ??? */ } } for ( ; i < 16; i++) encode_state->reference_objects[i] = NULL; return VA_STATUS_SUCCESS; error: return VA_STATUS_ERROR_INVALID_PARAMETER; } static VAStatus intel_encoder_check_mpeg2_parameter(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAEncPictureParameterBufferMPEG2 *pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer; struct object_surface *obj_surface; struct object_buffer *obj_buffer; int i = 0; obj_surface = SURFACE(pic_param->reconstructed_picture); assert(obj_surface); /* It is possible the store buffer isn't allocated yet */ if (!obj_surface) goto error; encode_state->reconstructed_object = obj_surface; obj_buffer = BUFFER(pic_param->coded_buf); assert(obj_buffer && obj_buffer->buffer_store && obj_buffer->buffer_store->bo); if (!obj_buffer || !obj_buffer->buffer_store || !obj_buffer->buffer_store->bo) goto error; encode_state->coded_buf_object = obj_buffer; if (pic_param->picture_type == VAEncPictureTypeIntra) { } else if (pic_param->picture_type == VAEncPictureTypePredictive) { assert(pic_param->forward_reference_picture != VA_INVALID_SURFACE); obj_surface = SURFACE(pic_param->forward_reference_picture); assert(obj_surface && obj_surface->bo); if (!obj_surface || !obj_surface->bo) goto error; encode_state->reference_objects[i++] = obj_surface; } else if (pic_param->picture_type == VAEncPictureTypeBidirectional) { assert(pic_param->forward_reference_picture != VA_INVALID_SURFACE); obj_surface = SURFACE(pic_param->forward_reference_picture); assert(obj_surface && obj_surface->bo); if (!obj_surface || !obj_surface->bo) goto error; encode_state->reference_objects[i++] = obj_surface; assert(pic_param->backward_reference_picture != VA_INVALID_SURFACE); obj_surface = SURFACE(pic_param->backward_reference_picture); assert(obj_surface && obj_surface->bo); if (!obj_surface || !obj_surface->bo) goto error; encode_state->reference_objects[i++] = obj_surface; } else goto error; for ( ; i < 16; i++) encode_state->reference_objects[i] = NULL; return VA_STATUS_SUCCESS; error: return VA_STATUS_ERROR_INVALID_PARAMETER; } static VAStatus intel_encoder_sanity_check_input(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { VAStatus vaStatus; switch (profile) { case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: vaStatus = intel_encoder_check_avc_parameter(ctx, encode_state, encoder_context); break; case VAProfileMPEG2Simple: case VAProfileMPEG2Main: vaStatus = intel_encoder_check_mpeg2_parameter(ctx, encode_state, encoder_context); break; default: vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE; break; } if (vaStatus != VA_STATUS_SUCCESS) goto out; vaStatus = intel_encoder_check_yuv_surface(ctx, profile, encode_state, encoder_context); out: return vaStatus; } static VAStatus intel_encoder_end_picture(VADriverContextP ctx, VAProfile profile, union codec_state *codec_state, struct hw_context *hw_context) { struct intel_encoder_context *encoder_context = (struct intel_encoder_context *)hw_context; struct encode_state *encode_state = &codec_state->encode; VAStatus vaStatus; vaStatus = intel_encoder_sanity_check_input(ctx, profile, encode_state, encoder_context); if (vaStatus != VA_STATUS_SUCCESS) return vaStatus; encoder_context->mfc_brc_prepare(encode_state, encoder_context); vaStatus = encoder_context->vme_pipeline(ctx, profile, encode_state, encoder_context); if (vaStatus == VA_STATUS_SUCCESS) encoder_context->mfc_pipeline(ctx, profile, encode_state, encoder_context); return VA_STATUS_SUCCESS; } static void intel_encoder_context_destroy(void *hw_context) { struct intel_encoder_context *encoder_context = (struct intel_encoder_context *)hw_context; encoder_context->mfc_context_destroy(encoder_context->mfc_context); encoder_context->vme_context_destroy(encoder_context->vme_context); intel_batchbuffer_free(encoder_context->base.batch); free(encoder_context); } typedef Bool (* hw_init_func)(VADriverContextP, struct intel_encoder_context *); static struct hw_context * intel_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config, hw_init_func vme_context_init, hw_init_func mfc_context_init) { struct intel_driver_data *intel = intel_driver_data(ctx); struct intel_encoder_context *encoder_context = calloc(1, sizeof(struct intel_encoder_context)); int i; encoder_context->base.destroy = intel_encoder_context_destroy; encoder_context->base.run = intel_encoder_end_picture; encoder_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0); encoder_context->input_yuv_surface = VA_INVALID_SURFACE; encoder_context->is_tmp_id = 0; encoder_context->rate_control_mode = VA_RC_NONE; switch (obj_config->profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: encoder_context->codec = CODEC_MPEG2; break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: encoder_context->codec = CODEC_H264; break; default: /* Never get here */ assert(0); break; } for (i = 0; i < obj_config->num_attribs; i++) { if (obj_config->attrib_list[i].type == VAConfigAttribRateControl) { encoder_context->rate_control_mode = obj_config->attrib_list[i].value; if (encoder_context->codec == CODEC_MPEG2 && encoder_context->rate_control_mode & VA_RC_CBR) { WARN_ONCE("Don't support CBR for MPEG-2 encoding\n"); encoder_context->rate_control_mode &= ~VA_RC_CBR; } break; } } vme_context_init(ctx, encoder_context); assert(encoder_context->vme_context); assert(encoder_context->vme_context_destroy); assert(encoder_context->vme_pipeline); mfc_context_init(ctx, encoder_context); assert(encoder_context->mfc_context); assert(encoder_context->mfc_context_destroy); assert(encoder_context->mfc_pipeline); return (struct hw_context *)encoder_context; } struct hw_context * gen6_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config) { return intel_enc_hw_context_init(ctx, obj_config, gen6_vme_context_init, gen6_mfc_context_init); } struct hw_context * gen7_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config) { return intel_enc_hw_context_init(ctx, obj_config, gen7_vme_context_init, gen7_mfc_context_init); } struct hw_context * gen75_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config) { return intel_enc_hw_context_init(ctx, obj_config, gen75_vme_context_init, gen75_mfc_context_init); } struct hw_context * gen8_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config) { return intel_enc_hw_context_init(ctx, obj_config, gen8_vme_context_init, gen8_mfc_context_init); } intel-driver-1.3.0/src/i965_encoder.h000066400000000000000000000050321231401140700172430ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Zhou chang * */ #ifndef _I965_ENCODER_H_ #define _I965_ENCODER_H_ #include #include #include #include "i965_structs.h" #include "i965_drv_video.h" struct intel_encoder_context { struct hw_context base; int codec; VASurfaceID input_yuv_surface; int is_tmp_id; unsigned int rate_control_mode; void *vme_context; void *mfc_context; void (*vme_context_destroy)(void *vme_context); VAStatus (*vme_pipeline)(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context); void (*mfc_context_destroy)(void *mfc_context); VAStatus (*mfc_pipeline)(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, struct intel_encoder_context *encoder_context); void (*mfc_brc_prepare)(struct encode_state *encode_state, struct intel_encoder_context *encoder_context); }; extern struct hw_context * gen75_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config); extern struct hw_context * gen8_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config); #endif /* _I965_ENCODER_H_ */ intel-driver-1.3.0/src/i965_encoder_utils.c000066400000000000000000000377571231401140700205010ustar00rootroot00000000000000/* * Copyright © 2011 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include #include #include #include #include #include "i965_encoder_utils.h" #define BITSTREAM_ALLOCATE_STEPPING 4096 #define NAL_REF_IDC_NONE 0 #define NAL_REF_IDC_LOW 1 #define NAL_REF_IDC_MEDIUM 2 #define NAL_REF_IDC_HIGH 3 #define NAL_NON_IDR 1 #define NAL_IDR 5 #define NAL_SPS 7 #define NAL_PPS 8 #define NAL_SEI 6 #define SLICE_TYPE_P 0 #define SLICE_TYPE_B 1 #define SLICE_TYPE_I 2 #define IS_I_SLICE(type) (SLICE_TYPE_I == (type) || SLICE_TYPE_I == (type - 5)) #define IS_P_SLICE(type) (SLICE_TYPE_P == (type) || SLICE_TYPE_P == (type - 5)) #define IS_B_SLICE(type) (SLICE_TYPE_B == (type) || SLICE_TYPE_B == (type - 5)) #define ENTROPY_MODE_CAVLC 0 #define ENTROPY_MODE_CABAC 1 #define PROFILE_IDC_BASELINE 66 #define PROFILE_IDC_MAIN 77 #define PROFILE_IDC_HIGH 100 struct __avc_bitstream { unsigned int *buffer; int bit_offset; int max_size_in_dword; }; typedef struct __avc_bitstream avc_bitstream; static unsigned int swap32(unsigned int val) { unsigned char *pval = (unsigned char *)&val; return ((pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | (pval[3] << 0)); } static void avc_bitstream_start(avc_bitstream *bs) { bs->max_size_in_dword = BITSTREAM_ALLOCATE_STEPPING; bs->buffer = calloc(bs->max_size_in_dword * sizeof(int), 1); bs->bit_offset = 0; } static void avc_bitstream_end(avc_bitstream *bs) { int pos = (bs->bit_offset >> 5); int bit_offset = (bs->bit_offset & 0x1f); int bit_left = 32 - bit_offset; if (bit_offset) { bs->buffer[pos] = swap32((bs->buffer[pos] << bit_left)); } // free(bs->buffer); } static void avc_bitstream_put_ui(avc_bitstream *bs, unsigned int val, int size_in_bits) { int pos = (bs->bit_offset >> 5); int bit_offset = (bs->bit_offset & 0x1f); int bit_left = 32 - bit_offset; if (!size_in_bits) return; if (size_in_bits < 32) val &= (( 1 << size_in_bits) - 1); bs->bit_offset += size_in_bits; if (bit_left > size_in_bits) { bs->buffer[pos] = (bs->buffer[pos] << size_in_bits | val); } else { size_in_bits -= bit_left; bs->buffer[pos] = (bs->buffer[pos] << bit_left) | (val >> size_in_bits); bs->buffer[pos] = swap32(bs->buffer[pos]); if (pos + 1 == bs->max_size_in_dword) { bs->max_size_in_dword += BITSTREAM_ALLOCATE_STEPPING; bs->buffer = realloc(bs->buffer, bs->max_size_in_dword * sizeof(unsigned int)); if (!bs->buffer) return; } bs->buffer[pos + 1] = val; } } static void avc_bitstream_put_ue(avc_bitstream *bs, unsigned int val) { int size_in_bits = 0; int tmp_val = ++val; while (tmp_val) { tmp_val >>= 1; size_in_bits++; } avc_bitstream_put_ui(bs, 0, size_in_bits - 1); // leading zero avc_bitstream_put_ui(bs, val, size_in_bits); } static void avc_bitstream_put_se(avc_bitstream *bs, int val) { unsigned int new_val; if (val <= 0) new_val = -2 * val; else new_val = 2 * val - 1; avc_bitstream_put_ue(bs, new_val); } static void avc_bitstream_byte_aligning(avc_bitstream *bs, int bit) { int bit_offset = (bs->bit_offset & 0x7); int bit_left = 8 - bit_offset; int new_val; if (!bit_offset) return; assert(bit == 0 || bit == 1); if (bit) new_val = (1 << bit_left) - 1; else new_val = 0; avc_bitstream_put_ui(bs, new_val, bit_left); } static void avc_rbsp_trailing_bits(avc_bitstream *bs) { avc_bitstream_put_ui(bs, 1, 1); avc_bitstream_byte_aligning(bs, 0); } static void nal_start_code_prefix(avc_bitstream *bs) { avc_bitstream_put_ui(bs, 0x00000001, 32); } static void nal_header(avc_bitstream *bs, int nal_ref_idc, int nal_unit_type) { avc_bitstream_put_ui(bs, 0, 1); /* forbidden_zero_bit: 0 */ avc_bitstream_put_ui(bs, nal_ref_idc, 2); avc_bitstream_put_ui(bs, nal_unit_type, 5); } static void slice_header(avc_bitstream *bs, VAEncSequenceParameterBufferH264 *sps_param, VAEncPictureParameterBufferH264 *pic_param, VAEncSliceParameterBufferH264 *slice_param) { int first_mb_in_slice = slice_param->macroblock_address; avc_bitstream_put_ue(bs, first_mb_in_slice); /* first_mb_in_slice: 0 */ avc_bitstream_put_ue(bs, slice_param->slice_type); /* slice_type */ avc_bitstream_put_ue(bs, slice_param->pic_parameter_set_id); /* pic_parameter_set_id: 0 */ avc_bitstream_put_ui(bs, pic_param->frame_num, sps_param->seq_fields.bits.log2_max_frame_num_minus4 + 4); /* frame_num */ /* frame_mbs_only_flag == 1 */ if (!sps_param->seq_fields.bits.frame_mbs_only_flag) { /* FIXME: */ assert(0); } if (pic_param->pic_fields.bits.idr_pic_flag) avc_bitstream_put_ue(bs, slice_param->idr_pic_id); /* idr_pic_id: 0 */ if (sps_param->seq_fields.bits.pic_order_cnt_type == 0) { avc_bitstream_put_ui(bs, pic_param->CurrPic.TopFieldOrderCnt, sps_param->seq_fields.bits.log2_max_pic_order_cnt_lsb_minus4 + 4); /* pic_order_present_flag == 0 */ } else { /* FIXME: */ assert(0); } /* redundant_pic_cnt_present_flag == 0 */ /* slice type */ if (IS_P_SLICE(slice_param->slice_type)) { avc_bitstream_put_ui(bs, slice_param->num_ref_idx_active_override_flag, 1); /* num_ref_idx_active_override_flag: */ if (slice_param->num_ref_idx_active_override_flag) avc_bitstream_put_ue(bs, slice_param->num_ref_idx_l0_active_minus1); /* ref_pic_list_reordering */ avc_bitstream_put_ui(bs, 0, 1); /* ref_pic_list_reordering_flag_l0: 0 */ } else if (IS_B_SLICE(slice_param->slice_type)) { avc_bitstream_put_ui(bs, slice_param->direct_spatial_mv_pred_flag, 1); /* direct_spatial_mv_pred: 1 */ avc_bitstream_put_ui(bs, slice_param->num_ref_idx_active_override_flag, 1); /* num_ref_idx_active_override_flag: */ if (slice_param->num_ref_idx_active_override_flag) { avc_bitstream_put_ue(bs, slice_param->num_ref_idx_l0_active_minus1); avc_bitstream_put_ue(bs, slice_param->num_ref_idx_l1_active_minus1); } /* ref_pic_list_reordering */ avc_bitstream_put_ui(bs, 0, 1); /* ref_pic_list_reordering_flag_l0: 0 */ avc_bitstream_put_ui(bs, 0, 1); /* ref_pic_list_reordering_flag_l1: 0 */ } if ((pic_param->pic_fields.bits.weighted_pred_flag && IS_P_SLICE(slice_param->slice_type)) || ((pic_param->pic_fields.bits.weighted_bipred_idc == 1) && IS_B_SLICE(slice_param->slice_type))) { /* FIXME: fill weight/offset table */ assert(0); } /* dec_ref_pic_marking */ if (pic_param->pic_fields.bits.reference_pic_flag) { /* nal_ref_idc != 0 */ unsigned char no_output_of_prior_pics_flag = 0; unsigned char long_term_reference_flag = 0; unsigned char adaptive_ref_pic_marking_mode_flag = 0; if (pic_param->pic_fields.bits.idr_pic_flag) { avc_bitstream_put_ui(bs, no_output_of_prior_pics_flag, 1); /* no_output_of_prior_pics_flag: 0 */ avc_bitstream_put_ui(bs, long_term_reference_flag, 1); /* long_term_reference_flag: 0 */ } else { avc_bitstream_put_ui(bs, adaptive_ref_pic_marking_mode_flag, 1); /* adaptive_ref_pic_marking_mode_flag: 0 */ } } if (pic_param->pic_fields.bits.entropy_coding_mode_flag && !IS_I_SLICE(slice_param->slice_type)) avc_bitstream_put_ue(bs, slice_param->cabac_init_idc); /* cabac_init_idc: 0 */ avc_bitstream_put_se(bs, slice_param->slice_qp_delta); /* slice_qp_delta: 0 */ /* ignore for SP/SI */ if (pic_param->pic_fields.bits.deblocking_filter_control_present_flag) { avc_bitstream_put_ue(bs, slice_param->disable_deblocking_filter_idc); /* disable_deblocking_filter_idc: 0 */ if (slice_param->disable_deblocking_filter_idc != 1) { avc_bitstream_put_se(bs, slice_param->slice_alpha_c0_offset_div2); /* slice_alpha_c0_offset_div2: 2 */ avc_bitstream_put_se(bs, slice_param->slice_beta_offset_div2); /* slice_beta_offset_div2: 2 */ } } if (pic_param->pic_fields.bits.entropy_coding_mode_flag) { avc_bitstream_byte_aligning(bs, 1); } } int build_avc_slice_header(VAEncSequenceParameterBufferH264 *sps_param, VAEncPictureParameterBufferH264 *pic_param, VAEncSliceParameterBufferH264 *slice_param, unsigned char **slice_header_buffer) { avc_bitstream bs; int is_idr = !!pic_param->pic_fields.bits.idr_pic_flag; int is_ref = !!pic_param->pic_fields.bits.reference_pic_flag; avc_bitstream_start(&bs); nal_start_code_prefix(&bs); if (IS_I_SLICE(slice_param->slice_type)) { nal_header(&bs, NAL_REF_IDC_HIGH, is_idr ? NAL_IDR : NAL_NON_IDR); } else if (IS_P_SLICE(slice_param->slice_type)) { assert(!is_idr); nal_header(&bs, NAL_REF_IDC_MEDIUM, NAL_NON_IDR); } else { assert(IS_B_SLICE(slice_param->slice_type)); assert(!is_idr); nal_header(&bs, is_ref ? NAL_REF_IDC_LOW : NAL_REF_IDC_NONE, NAL_NON_IDR); } slice_header(&bs, sps_param, pic_param, slice_param); avc_bitstream_end(&bs); *slice_header_buffer = (unsigned char *)bs.buffer; return bs.bit_offset; } int build_avc_sei_buffering_period(int cpb_removal_length, unsigned int init_cpb_removal_delay, unsigned int init_cpb_removal_delay_offset, unsigned char **sei_buffer) { unsigned char *byte_buf; int byte_size, i; avc_bitstream nal_bs; avc_bitstream sei_bs; avc_bitstream_start(&sei_bs); avc_bitstream_put_ue(&sei_bs, 0); /*seq_parameter_set_id*/ avc_bitstream_put_ui(&sei_bs, init_cpb_removal_delay, cpb_removal_length); avc_bitstream_put_ui(&sei_bs, init_cpb_removal_delay_offset, cpb_removal_length); if ( sei_bs.bit_offset & 0x7) { avc_bitstream_put_ui(&sei_bs, 1, 1); } avc_bitstream_end(&sei_bs); byte_size = (sei_bs.bit_offset + 7) / 8; avc_bitstream_start(&nal_bs); nal_start_code_prefix(&nal_bs); nal_header(&nal_bs, NAL_REF_IDC_NONE, NAL_SEI); avc_bitstream_put_ui(&nal_bs, 0, 8); avc_bitstream_put_ui(&nal_bs, byte_size, 8); byte_buf = (unsigned char *)sei_bs.buffer; for(i = 0; i < byte_size; i++) { avc_bitstream_put_ui(&nal_bs, byte_buf[i], 8); } free(byte_buf); avc_rbsp_trailing_bits(&nal_bs); avc_bitstream_end(&nal_bs); *sei_buffer = (unsigned char *)nal_bs.buffer; return nal_bs.bit_offset; } int build_avc_sei_pic_timing(unsigned int cpb_removal_length, unsigned int cpb_removal_delay, unsigned int dpb_output_length, unsigned int dpb_output_delay, unsigned char **sei_buffer) { unsigned char *byte_buf; int byte_size, i; avc_bitstream nal_bs; avc_bitstream sei_bs; avc_bitstream_start(&sei_bs); avc_bitstream_put_ui(&sei_bs, cpb_removal_delay, cpb_removal_length); avc_bitstream_put_ui(&sei_bs, dpb_output_delay, dpb_output_length); if ( sei_bs.bit_offset & 0x7) { avc_bitstream_put_ui(&sei_bs, 1, 1); } avc_bitstream_end(&sei_bs); byte_size = (sei_bs.bit_offset + 7) / 8; avc_bitstream_start(&nal_bs); nal_start_code_prefix(&nal_bs); nal_header(&nal_bs, NAL_REF_IDC_NONE, NAL_SEI); avc_bitstream_put_ui(&nal_bs, 0x01, 8); avc_bitstream_put_ui(&nal_bs, byte_size, 8); byte_buf = (unsigned char *)sei_bs.buffer; for(i = 0; i < byte_size; i++) { avc_bitstream_put_ui(&nal_bs, byte_buf[i], 8); } free(byte_buf); avc_rbsp_trailing_bits(&nal_bs); avc_bitstream_end(&nal_bs); *sei_buffer = (unsigned char *)nal_bs.buffer; return nal_bs.bit_offset; } int build_avc_sei_buffer_timing(unsigned int init_cpb_removal_length, unsigned int init_cpb_removal_delay, unsigned int init_cpb_removal_delay_offset, unsigned int cpb_removal_length, unsigned int cpb_removal_delay, unsigned int dpb_output_length, unsigned int dpb_output_delay, unsigned char **sei_buffer) { unsigned char *byte_buf; int bp_byte_size, i, pic_byte_size; avc_bitstream nal_bs; avc_bitstream sei_bp_bs, sei_pic_bs; avc_bitstream_start(&sei_bp_bs); avc_bitstream_put_ue(&sei_bp_bs, 0); /*seq_parameter_set_id*/ avc_bitstream_put_ui(&sei_bp_bs, init_cpb_removal_delay, cpb_removal_length); avc_bitstream_put_ui(&sei_bp_bs, init_cpb_removal_delay_offset, cpb_removal_length); if ( sei_bp_bs.bit_offset & 0x7) { avc_bitstream_put_ui(&sei_bp_bs, 1, 1); } avc_bitstream_end(&sei_bp_bs); bp_byte_size = (sei_bp_bs.bit_offset + 7) / 8; avc_bitstream_start(&sei_pic_bs); avc_bitstream_put_ui(&sei_pic_bs, cpb_removal_delay, cpb_removal_length); avc_bitstream_put_ui(&sei_pic_bs, dpb_output_delay, dpb_output_length); if ( sei_pic_bs.bit_offset & 0x7) { avc_bitstream_put_ui(&sei_pic_bs, 1, 1); } avc_bitstream_end(&sei_pic_bs); pic_byte_size = (sei_pic_bs.bit_offset + 7) / 8; avc_bitstream_start(&nal_bs); nal_start_code_prefix(&nal_bs); nal_header(&nal_bs, NAL_REF_IDC_NONE, NAL_SEI); /* Write the SEI buffer period data */ avc_bitstream_put_ui(&nal_bs, 0, 8); avc_bitstream_put_ui(&nal_bs, bp_byte_size, 8); byte_buf = (unsigned char *)sei_bp_bs.buffer; for(i = 0; i < bp_byte_size; i++) { avc_bitstream_put_ui(&nal_bs, byte_buf[i], 8); } free(byte_buf); /* write the SEI timing data */ avc_bitstream_put_ui(&nal_bs, 0x01, 8); avc_bitstream_put_ui(&nal_bs, pic_byte_size, 8); byte_buf = (unsigned char *)sei_pic_bs.buffer; for(i = 0; i < pic_byte_size; i++) { avc_bitstream_put_ui(&nal_bs, byte_buf[i], 8); } free(byte_buf); avc_rbsp_trailing_bits(&nal_bs); avc_bitstream_end(&nal_bs); *sei_buffer = (unsigned char *)nal_bs.buffer; return nal_bs.bit_offset; } int build_mpeg2_slice_header(VAEncSequenceParameterBufferMPEG2 *sps_param, VAEncPictureParameterBufferMPEG2 *pic_param, VAEncSliceParameterBufferMPEG2 *slice_param, unsigned char **slice_header_buffer) { avc_bitstream bs; avc_bitstream_start(&bs); avc_bitstream_end(&bs); *slice_header_buffer = (unsigned char *)bs.buffer; return bs.bit_offset; } intel-driver-1.3.0/src/i965_encoder_utils.h000066400000000000000000000027271231401140700204730ustar00rootroot00000000000000#ifndef __I965_ENCODER_UTILS_H__ #define __I965_ENCODER_UTILS_H__ int build_avc_slice_header(VAEncSequenceParameterBufferH264 *sps_param, VAEncPictureParameterBufferH264 *pic_param, VAEncSliceParameterBufferH264 *slice_param, unsigned char **slice_header_buffer); int build_avc_sei_buffering_period(int cpb_removal_length, unsigned int init_cpb_removal_delay, unsigned int init_cpb_removal_delay_offset, unsigned char **sei_buffer); int build_avc_sei_pic_timing(unsigned int cpb_removal_length, unsigned int cpb_removal_delay, unsigned int dpb_output_length, unsigned int dpb_output_delay, unsigned char **sei_buffer); int build_avc_sei_buffer_timing(unsigned int init_cpb_removal_length, unsigned int init_cpb_removal_delay, unsigned int init_cpb_removal_delay_offset, unsigned int cpb_removal_length, unsigned int cpb_removal_delay, unsigned int dpb_output_length, unsigned int dpb_output_delay, unsigned char **sei_buffer); int build_mpeg2_slice_header(VAEncSequenceParameterBufferMPEG2 *sps_param, VAEncPictureParameterBufferMPEG2 *pic_param, VAEncSliceParameterBufferMPEG2 *slice_param, unsigned char **slice_header_buffer); #endif /* __I965_ENCODER_UTILS_H__ */ intel-driver-1.3.0/src/i965_gpe_utils.c000066400000000000000000001202111231401140700176070ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ #include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_gpe_utils.h" static void i965_gpe_select(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch) { BEGIN_BATCH(batch, 1); OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); ADVANCE_BATCH(batch); } static void gen6_gpe_state_base_address(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch) { BEGIN_BATCH(batch, 10); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2)); OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General State Base Address */ OUT_RELOC(batch, gpe_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic State Base Address */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect Object Base Address */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction Base Address */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General State Access Upper Bound */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic State Access Upper Bound */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect Object Access Upper Bound */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction Access Upper Bound */ ADVANCE_BATCH(batch); } static void gen6_gpe_vfe_state(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch) { BEGIN_BATCH(batch, 8); OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2)); OUT_BATCH(batch, 0); /* Scratch Space Base Pointer and Space */ OUT_BATCH(batch, gpe_context->vfe_state.max_num_threads << 16 | /* Maximum Number of Threads */ gpe_context->vfe_state.num_urb_entries << 8 | /* Number of URB Entries */ gpe_context->vfe_state.gpgpu_mode << 2); /* MEDIA Mode */ OUT_BATCH(batch, 0); /* Debug: Object ID */ OUT_BATCH(batch, gpe_context->vfe_state.urb_entry_size << 16 | /* URB Entry Allocation Size */ gpe_context->vfe_state.curbe_allocation_size); /* CURBE Allocation Size */ /* the vfe_desc5/6/7 will decide whether the scoreboard is used. */ OUT_BATCH(batch, gpe_context->vfe_desc5.dword); OUT_BATCH(batch, gpe_context->vfe_desc6.dword); OUT_BATCH(batch, gpe_context->vfe_desc7.dword); ADVANCE_BATCH(batch); } static void gen6_gpe_curbe_load(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch) { BEGIN_BATCH(batch, 4); OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, gpe_context->curbe.length); OUT_RELOC(batch, gpe_context->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_BATCH(batch); } static void gen6_gpe_idrt(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch) { BEGIN_BATCH(batch, 4); OUT_BATCH(batch, CMD_MEDIA_INTERFACE_LOAD | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, gpe_context->idrt.max_entries * gpe_context->idrt.entry_size); OUT_RELOC(batch, gpe_context->idrt.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_BATCH(batch); } void i965_gpe_load_kernels(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_kernel *kernel_list, unsigned int num_kernels) { struct i965_driver_data *i965 = i965_driver_data(ctx); int i; assert(num_kernels <= MAX_GPE_KERNELS); memcpy(gpe_context->kernels, kernel_list, sizeof(*kernel_list) * num_kernels); gpe_context->num_kernels = num_kernels; for (i = 0; i < num_kernels; i++) { struct i965_kernel *kernel = &gpe_context->kernels[i]; kernel->bo = dri_bo_alloc(i965->intel.bufmgr, kernel->name, kernel->size, 0x1000); assert(kernel->bo); dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin); } } void i965_gpe_context_destroy(struct i965_gpe_context *gpe_context) { int i; dri_bo_unreference(gpe_context->surface_state_binding_table.bo); gpe_context->surface_state_binding_table.bo = NULL; dri_bo_unreference(gpe_context->idrt.bo); gpe_context->idrt.bo = NULL; dri_bo_unreference(gpe_context->curbe.bo); gpe_context->curbe.bo = NULL; for (i = 0; i < gpe_context->num_kernels; i++) { struct i965_kernel *kernel = &gpe_context->kernels[i]; dri_bo_unreference(kernel->bo); kernel->bo = NULL; } } void i965_gpe_context_init(VADriverContextP ctx, struct i965_gpe_context *gpe_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); dri_bo *bo; dri_bo_unreference(gpe_context->surface_state_binding_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state & binding table", gpe_context->surface_state_binding_table.length, 4096); assert(bo); gpe_context->surface_state_binding_table.bo = bo; dri_bo_unreference(gpe_context->idrt.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "interface descriptor table", gpe_context->idrt.entry_size * gpe_context->idrt.max_entries, 4096); assert(bo); gpe_context->idrt.bo = bo; dri_bo_unreference(gpe_context->curbe.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "curbe buffer", gpe_context->curbe.length, 4096); assert(bo); gpe_context->curbe.bo = bo; } void gen6_gpe_pipeline_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch) { intel_batchbuffer_emit_mi_flush(batch); i965_gpe_select(ctx, gpe_context, batch); gen6_gpe_state_base_address(ctx, gpe_context, batch); gen6_gpe_vfe_state(ctx, gpe_context, batch); gen6_gpe_curbe_load(ctx, gpe_context, batch); gen6_gpe_idrt(ctx, gpe_context, batch); } static void i965_gpe_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss3.tiled_surface = 0; ss->ss3.tile_walk = 0; break; case I915_TILING_X: ss->ss3.tiled_surface = 1; ss->ss3.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss3.tiled_surface = 1; ss->ss3.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void i965_gpe_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss2.tiled_surface = 0; ss->ss2.tile_walk = 0; break; case I915_TILING_X: ss->ss2.tiled_surface = 1; ss->ss2.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss2.tiled_surface = 1; ss->ss2.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void gen7_gpe_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss0.tiled_surface = 0; ss->ss0.tile_walk = 0; break; case I915_TILING_X: ss->ss0.tiled_surface = 1; ss->ss0.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss0.tiled_surface = 1; ss->ss0.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void gen7_gpe_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss2.tiled_surface = 0; ss->ss2.tile_walk = 0; break; case I915_TILING_X: ss->ss2.tiled_surface = 1; ss->ss2.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss2.tiled_surface = 1; ss->ss2.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void gen8_gpe_set_surface_tiling(struct gen8_surface_state *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss0.tiled_surface = 0; ss->ss0.tile_walk = 0; break; case I915_TILING_X: ss->ss0.tiled_surface = 1; ss->ss0.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss0.tiled_surface = 1; ss->ss0.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void gen8_gpe_set_surface2_tiling(struct gen8_surface_state2 *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss2.tiled_surface = 0; ss->ss2.tile_walk = 0; break; case I915_TILING_X: ss->ss2.tiled_surface = 1; ss->ss2.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss2.tiled_surface = 1; ss->ss2.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void i965_gpe_set_surface2_state(VADriverContextP ctx, struct object_surface *obj_surface, struct i965_surface_state2 *ss) { int w, h, w_pitch; unsigned int tiling, swizzle; assert(obj_surface->bo); assert(obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')); dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); w = obj_surface->orig_width; h = obj_surface->orig_height; w_pitch = obj_surface->width; memset(ss, 0, sizeof(*ss)); /* ss0 */ ss->ss0.surface_base_address = obj_surface->bo->offset; /* ss1 */ ss->ss1.cbcr_pixel_offset_v_direction = 2; ss->ss1.width = w - 1; ss->ss1.height = h - 1; /* ss2 */ ss->ss2.surface_format = MFX_SURFACE_PLANAR_420_8; ss->ss2.interleave_chroma = 1; ss->ss2.pitch = w_pitch - 1; ss->ss2.half_pitch_for_chroma = 0; i965_gpe_set_surface2_tiling(ss, tiling); /* ss3: UV offset for interleave mode */ ss->ss3.x_offset_for_cb = obj_surface->x_cb_offset; ss->ss3.y_offset_for_cb = obj_surface->y_cb_offset; } void i965_gpe_surface2_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset) { struct i965_surface_state2 *ss; dri_bo *bo; bo = gpe_context->surface_state_binding_table.bo; dri_bo_map(bo, 1); assert(bo->virtual); ss = (struct i965_surface_state2 *)((char *)bo->virtual + surface_state_offset); i965_gpe_set_surface2_state(ctx, obj_surface, ss); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, 0, 0, surface_state_offset + offsetof(struct i965_surface_state2, ss0), obj_surface->bo); *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset; dri_bo_unmap(bo); } static void i965_gpe_set_media_rw_surface_state(VADriverContextP ctx, struct object_surface *obj_surface, struct i965_surface_state *ss) { int w, h, w_pitch; unsigned int tiling, swizzle; dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); w = obj_surface->orig_width; h = obj_surface->orig_height; w_pitch = obj_surface->width; memset(ss, 0, sizeof(*ss)); /* ss0 */ ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM; /* ss1 */ ss->ss1.base_addr = obj_surface->bo->offset; /* ss2 */ ss->ss2.width = w / 4 - 1; /* in DWORDs for media read & write message */ ss->ss2.height = h - 1; /* ss3 */ ss->ss3.pitch = w_pitch - 1; i965_gpe_set_surface_tiling(ss, tiling); } void i965_gpe_media_rw_surface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset) { struct i965_surface_state *ss; dri_bo *bo; bo = gpe_context->surface_state_binding_table.bo; dri_bo_map(bo, True); assert(bo->virtual); ss = (struct i965_surface_state *)((char *)bo->virtual + surface_state_offset); i965_gpe_set_media_rw_surface_state(ctx, obj_surface, ss); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, 0, 0, surface_state_offset + offsetof(struct i965_surface_state, ss1), obj_surface->bo); *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset; dri_bo_unmap(bo); } static void i965_gpe_set_buffer_surface_state(VADriverContextP ctx, struct i965_buffer_surface *buffer_surface, struct i965_surface_state *ss) { int num_entries; assert(buffer_surface->bo); num_entries = buffer_surface->num_blocks * buffer_surface->size_block / buffer_surface->pitch; memset(ss, 0, sizeof(*ss)); /* ss0 */ ss->ss0.render_cache_read_mode = 1; ss->ss0.surface_type = I965_SURFACE_BUFFER; /* ss1 */ ss->ss1.base_addr = buffer_surface->bo->offset; /* ss2 */ ss->ss2.width = ((num_entries - 1) & 0x7f); ss->ss2.height = (((num_entries - 1) >> 7) & 0x1fff); /* ss3 */ ss->ss3.depth = (((num_entries - 1) >> 20) & 0x7f); ss->ss3.pitch = buffer_surface->pitch - 1; } void i965_gpe_buffer_suface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_buffer_surface *buffer_surface, unsigned long binding_table_offset, unsigned long surface_state_offset) { struct i965_surface_state *ss; dri_bo *bo; bo = gpe_context->surface_state_binding_table.bo; dri_bo_map(bo, 1); assert(bo->virtual); ss = (struct i965_surface_state *)((char *)bo->virtual + surface_state_offset); i965_gpe_set_buffer_surface_state(ctx, buffer_surface, ss); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0, surface_state_offset + offsetof(struct i965_surface_state, ss1), buffer_surface->bo); *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset; dri_bo_unmap(bo); } static void gen7_gpe_set_surface2_state(VADriverContextP ctx, struct object_surface *obj_surface, struct gen7_surface_state2 *ss) { int w, h, w_pitch; unsigned int tiling, swizzle; assert(obj_surface->bo); assert(obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')); dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); w = obj_surface->orig_width; h = obj_surface->orig_height; w_pitch = obj_surface->width; memset(ss, 0, sizeof(*ss)); /* ss0 */ ss->ss0.surface_base_address = obj_surface->bo->offset; /* ss1 */ ss->ss1.cbcr_pixel_offset_v_direction = 2; ss->ss1.width = w - 1; ss->ss1.height = h - 1; /* ss2 */ ss->ss2.surface_format = MFX_SURFACE_PLANAR_420_8; ss->ss2.interleave_chroma = 1; ss->ss2.pitch = w_pitch - 1; ss->ss2.half_pitch_for_chroma = 0; gen7_gpe_set_surface2_tiling(ss, tiling); /* ss3: UV offset for interleave mode */ ss->ss3.x_offset_for_cb = obj_surface->x_cb_offset; ss->ss3.y_offset_for_cb = obj_surface->y_cb_offset; } void gen7_gpe_surface2_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset) { struct gen7_surface_state2 *ss; dri_bo *bo; bo = gpe_context->surface_state_binding_table.bo; dri_bo_map(bo, 1); assert(bo->virtual); ss = (struct gen7_surface_state2 *)((char *)bo->virtual + surface_state_offset); gen7_gpe_set_surface2_state(ctx, obj_surface, ss); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, 0, 0, surface_state_offset + offsetof(struct gen7_surface_state2, ss0), obj_surface->bo); *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset; dri_bo_unmap(bo); } static void gen7_gpe_set_media_rw_surface_state(VADriverContextP ctx, struct object_surface *obj_surface, struct gen7_surface_state *ss) { int w, h, w_pitch; unsigned int tiling, swizzle; dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); w = obj_surface->orig_width; h = obj_surface->orig_height; w_pitch = obj_surface->width; memset(ss, 0, sizeof(*ss)); /* ss0 */ ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM; /* ss1 */ ss->ss1.base_addr = obj_surface->bo->offset; /* ss2 */ ss->ss2.width = w / 4 - 1; /* in DWORDs for media read & write message */ ss->ss2.height = h - 1; /* ss3 */ ss->ss3.pitch = w_pitch - 1; gen7_gpe_set_surface_tiling(ss, tiling); } static void gen75_gpe_set_media_chroma_surface_state(VADriverContextP ctx, struct object_surface *obj_surface, struct gen7_surface_state *ss) { int w, w_pitch; unsigned int tiling, swizzle; int cbcr_offset; dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); w = obj_surface->orig_width; w_pitch = obj_surface->width; cbcr_offset = obj_surface->height * obj_surface->width; memset(ss, 0, sizeof(*ss)); /* ss0 */ ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM; /* ss1 */ ss->ss1.base_addr = obj_surface->bo->offset + cbcr_offset; /* ss2 */ ss->ss2.width = w / 4 - 1; /* in DWORDs for media read & write message */ ss->ss2.height = (obj_surface->height / 2) -1; /* ss3 */ ss->ss3.pitch = w_pitch - 1; gen7_gpe_set_surface_tiling(ss, tiling); } void gen7_gpe_media_rw_surface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset) { struct gen7_surface_state *ss; dri_bo *bo; bo = gpe_context->surface_state_binding_table.bo; dri_bo_map(bo, True); assert(bo->virtual); ss = (struct gen7_surface_state *)((char *)bo->virtual + surface_state_offset); gen7_gpe_set_media_rw_surface_state(ctx, obj_surface, ss); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, 0, 0, surface_state_offset + offsetof(struct gen7_surface_state, ss1), obj_surface->bo); *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset; dri_bo_unmap(bo); } void gen75_gpe_media_chroma_surface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset) { struct gen7_surface_state *ss; dri_bo *bo; int cbcr_offset; assert(obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')); bo = gpe_context->surface_state_binding_table.bo; dri_bo_map(bo, True); assert(bo->virtual); cbcr_offset = obj_surface->height * obj_surface->width; ss = (struct gen7_surface_state *)((char *)bo->virtual + surface_state_offset); gen75_gpe_set_media_chroma_surface_state(ctx, obj_surface, ss); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, 0, cbcr_offset, surface_state_offset + offsetof(struct gen7_surface_state, ss1), obj_surface->bo); *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset; dri_bo_unmap(bo); } static void gen7_gpe_set_buffer_surface_state(VADriverContextP ctx, struct i965_buffer_surface *buffer_surface, struct gen7_surface_state *ss) { int num_entries; assert(buffer_surface->bo); num_entries = buffer_surface->num_blocks * buffer_surface->size_block / buffer_surface->pitch; memset(ss, 0, sizeof(*ss)); /* ss0 */ ss->ss0.surface_type = I965_SURFACE_BUFFER; /* ss1 */ ss->ss1.base_addr = buffer_surface->bo->offset; /* ss2 */ ss->ss2.width = ((num_entries - 1) & 0x7f); ss->ss2.height = (((num_entries - 1) >> 7) & 0x3fff); /* ss3 */ ss->ss3.depth = (((num_entries - 1) >> 21) & 0x3f); ss->ss3.pitch = buffer_surface->pitch - 1; } void gen7_gpe_buffer_suface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_buffer_surface *buffer_surface, unsigned long binding_table_offset, unsigned long surface_state_offset) { struct gen7_surface_state *ss; dri_bo *bo; bo = gpe_context->surface_state_binding_table.bo; dri_bo_map(bo, 1); assert(bo->virtual); ss = (struct gen7_surface_state *)((char *)bo->virtual + surface_state_offset); gen7_gpe_set_buffer_surface_state(ctx, buffer_surface, ss); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0, surface_state_offset + offsetof(struct gen7_surface_state, ss1), buffer_surface->bo); *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset; dri_bo_unmap(bo); } static void gen8_gpe_set_surface2_state(VADriverContextP ctx, struct object_surface *obj_surface, struct gen8_surface_state2 *ss) { int w, h, w_pitch; unsigned int tiling, swizzle; assert(obj_surface->bo); assert(obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')); dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); w = obj_surface->orig_width; h = obj_surface->orig_height; w_pitch = obj_surface->width; memset(ss, 0, sizeof(*ss)); /* ss0 */ ss->ss6.base_addr = obj_surface->bo->offset; /* ss1 */ ss->ss1.cbcr_pixel_offset_v_direction = 2; ss->ss1.width = w - 1; ss->ss1.height = h - 1; /* ss2 */ ss->ss2.surface_format = MFX_SURFACE_PLANAR_420_8; ss->ss2.interleave_chroma = 1; ss->ss2.pitch = w_pitch - 1; ss->ss2.half_pitch_for_chroma = 0; gen8_gpe_set_surface2_tiling(ss, tiling); /* ss3: UV offset for interleave mode */ ss->ss3.x_offset_for_cb = obj_surface->x_cb_offset; ss->ss3.y_offset_for_cb = obj_surface->y_cb_offset; } void gen8_gpe_surface2_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset) { struct gen8_surface_state2 *ss; dri_bo *bo; bo = gpe_context->surface_state_binding_table.bo; dri_bo_map(bo, 1); assert(bo->virtual); ss = (struct gen8_surface_state2 *)((char *)bo->virtual + surface_state_offset); gen8_gpe_set_surface2_state(ctx, obj_surface, ss); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, 0, 0, surface_state_offset + offsetof(struct gen8_surface_state2, ss6), obj_surface->bo); *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset; dri_bo_unmap(bo); } static void gen8_gpe_set_media_rw_surface_state(VADriverContextP ctx, struct object_surface *obj_surface, struct gen8_surface_state *ss) { int w, h, w_pitch; unsigned int tiling, swizzle; dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); w = obj_surface->orig_width; h = obj_surface->orig_height; w_pitch = obj_surface->width; memset(ss, 0, sizeof(*ss)); /* ss0 */ ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM; /* ss1 */ ss->ss8.base_addr = obj_surface->bo->offset; /* ss2 */ ss->ss2.width = w / 4 - 1; /* in DWORDs for media read & write message */ ss->ss2.height = h - 1; /* ss3 */ ss->ss3.pitch = w_pitch - 1; gen8_gpe_set_surface_tiling(ss, tiling); } static void gen8_gpe_set_media_chroma_surface_state(VADriverContextP ctx, struct object_surface *obj_surface, struct gen8_surface_state *ss) { int w, h, w_pitch; unsigned int tiling, swizzle; int cbcr_offset; dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); w = obj_surface->orig_width; h = obj_surface->orig_height; w_pitch = obj_surface->width; cbcr_offset = obj_surface->height * obj_surface->width; memset(ss, 0, sizeof(*ss)); /* ss0 */ ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM; /* ss1 */ ss->ss8.base_addr = obj_surface->bo->offset + cbcr_offset; /* ss2 */ ss->ss2.width = w / 4 - 1; /* in DWORDs for media read & write message */ ss->ss2.height = (obj_surface->height / 2) -1; /* ss3 */ ss->ss3.pitch = w_pitch - 1; gen8_gpe_set_surface_tiling(ss, tiling); } void gen8_gpe_media_rw_surface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset) { struct gen8_surface_state *ss; dri_bo *bo; bo = gpe_context->surface_state_binding_table.bo; dri_bo_map(bo, True); assert(bo->virtual); ss = (struct gen8_surface_state *)((char *)bo->virtual + surface_state_offset); gen8_gpe_set_media_rw_surface_state(ctx, obj_surface, ss); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, 0, 0, surface_state_offset + offsetof(struct gen8_surface_state, ss8), obj_surface->bo); *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset; dri_bo_unmap(bo); } void gen8_gpe_media_chroma_surface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset) { struct gen8_surface_state *ss; dri_bo *bo; int cbcr_offset; assert(obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')); bo = gpe_context->surface_state_binding_table.bo; dri_bo_map(bo, True); assert(bo->virtual); cbcr_offset = obj_surface->height * obj_surface->width; ss = (struct gen8_surface_state *)((char *)bo->virtual + surface_state_offset); gen8_gpe_set_media_chroma_surface_state(ctx, obj_surface, ss); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, 0, cbcr_offset, surface_state_offset + offsetof(struct gen8_surface_state, ss8), obj_surface->bo); *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset; dri_bo_unmap(bo); } static void gen8_gpe_set_buffer_surface_state(VADriverContextP ctx, struct i965_buffer_surface *buffer_surface, struct gen8_surface_state *ss) { int num_entries; assert(buffer_surface->bo); num_entries = buffer_surface->num_blocks * buffer_surface->size_block / buffer_surface->pitch; memset(ss, 0, sizeof(*ss)); /* ss0 */ ss->ss0.surface_type = I965_SURFACE_BUFFER; /* ss1 */ ss->ss8.base_addr = buffer_surface->bo->offset; /* ss2 */ ss->ss2.width = ((num_entries - 1) & 0x7f); ss->ss2.height = (((num_entries - 1) >> 7) & 0x3fff); /* ss3 */ ss->ss3.depth = (((num_entries - 1) >> 21) & 0x3f); ss->ss3.pitch = buffer_surface->pitch - 1; } void gen8_gpe_buffer_suface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_buffer_surface *buffer_surface, unsigned long binding_table_offset, unsigned long surface_state_offset) { struct gen8_surface_state *ss; dri_bo *bo; bo = gpe_context->surface_state_binding_table.bo; dri_bo_map(bo, 1); assert(bo->virtual); ss = (struct gen8_surface_state *)((char *)bo->virtual + surface_state_offset); gen8_gpe_set_buffer_surface_state(ctx, buffer_surface, ss); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0, surface_state_offset + offsetof(struct gen8_surface_state, ss8), buffer_surface->bo); *((unsigned int *)((char *)bo->virtual + binding_table_offset)) = surface_state_offset; dri_bo_unmap(bo); } static void gen8_gpe_state_base_address(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch) { BEGIN_BATCH(batch, 16); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 14); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); //General State Base Address OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /*DW4 Surface state base address */ OUT_RELOC(batch, gpe_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */ OUT_BATCH(batch, 0); /*DW6. Dynamic state base address */ if (gpe_context->dynamic_state.bo) OUT_RELOC(batch, gpe_context->dynamic_state.bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY); else OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0); /*DW8. Indirect Object base address */ if (gpe_context->indirect_state.bo) OUT_RELOC(batch, gpe_context->indirect_state.bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY); else OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0); /*DW10. Instruct base address */ if (gpe_context->instruction_state.bo) OUT_RELOC(batch, gpe_context->instruction_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); else OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0); /* DW12. Size limitation */ OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY); //General State Access Upper Bound OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY); //Dynamic State Access Upper Bound OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY); //Indirect Object Access Upper Bound OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY); //Instruction Access Upper Bound /* OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); //LLC Coherent Base Address OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY ); //LLC Coherent Upper Bound */ ADVANCE_BATCH(batch); } static void gen8_gpe_vfe_state(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch) { BEGIN_BATCH(batch, 9); OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (9 - 2)); /* Scratch Space Base Pointer and Space */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, gpe_context->vfe_state.max_num_threads << 16 | /* Maximum Number of Threads */ gpe_context->vfe_state.num_urb_entries << 8 | /* Number of URB Entries */ gpe_context->vfe_state.gpgpu_mode << 2); /* MEDIA Mode */ OUT_BATCH(batch, 0); /* Debug: Object ID */ OUT_BATCH(batch, gpe_context->vfe_state.urb_entry_size << 16 | /* URB Entry Allocation Size */ gpe_context->vfe_state.curbe_allocation_size); /* CURBE Allocation Size */ /* the vfe_desc5/6/7 will decide whether the scoreboard is used. */ OUT_BATCH(batch, gpe_context->vfe_desc5.dword); OUT_BATCH(batch, gpe_context->vfe_desc6.dword); OUT_BATCH(batch, gpe_context->vfe_desc7.dword); ADVANCE_BATCH(batch); } static void gen8_gpe_curbe_load(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch) { BEGIN_BATCH(batch, 4); OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, gpe_context->curbe_size); OUT_BATCH(batch, gpe_context->curbe_offset); ADVANCE_BATCH(batch); } static void gen8_gpe_idrt(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch) { BEGIN_BATCH(batch, 4); OUT_BATCH(batch, CMD_MEDIA_INTERFACE_LOAD | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, gpe_context->idrt_size); OUT_BATCH(batch, gpe_context->idrt_offset); ADVANCE_BATCH(batch); } void gen8_gpe_pipeline_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch) { intel_batchbuffer_emit_mi_flush(batch); i965_gpe_select(ctx, gpe_context, batch); gen8_gpe_state_base_address(ctx, gpe_context, batch); gen8_gpe_vfe_state(ctx, gpe_context, batch); gen8_gpe_curbe_load(ctx, gpe_context, batch); gen8_gpe_idrt(ctx, gpe_context, batch); } void gen8_gpe_context_init(VADriverContextP ctx, struct i965_gpe_context *gpe_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); dri_bo *bo; int bo_size; unsigned int start_offset, end_offset; dri_bo_unreference(gpe_context->surface_state_binding_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state & binding table", gpe_context->surface_state_binding_table.length, 4096); assert(bo); gpe_context->surface_state_binding_table.bo = bo; bo_size = gpe_context->idrt_size + gpe_context->curbe_size + gpe_context->sampler_size + 192; dri_bo_unreference(gpe_context->dynamic_state.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state & binding table", bo_size, 4096); assert(bo); gpe_context->dynamic_state.bo = bo; gpe_context->dynamic_state.bo_size = bo_size; end_offset = 0; gpe_context->dynamic_state.end_offset = 0; /* Constant buffer offset */ start_offset = ALIGN(end_offset, 64); gpe_context->curbe_offset = start_offset; end_offset = start_offset + gpe_context->curbe_size; /* Interface descriptor offset */ start_offset = ALIGN(end_offset, 64); gpe_context->idrt_offset = start_offset; end_offset = start_offset + gpe_context->idrt_size; /* Sampler state offset */ start_offset = ALIGN(end_offset, 64); gpe_context->sampler_offset = start_offset; end_offset = start_offset + gpe_context->sampler_size; /* update the end offset of dynamic_state */ gpe_context->dynamic_state.end_offset = end_offset; } void gen8_gpe_context_destroy(struct i965_gpe_context *gpe_context) { int i; dri_bo_unreference(gpe_context->surface_state_binding_table.bo); gpe_context->surface_state_binding_table.bo = NULL; dri_bo_unreference(gpe_context->instruction_state.bo); gpe_context->instruction_state.bo = NULL; dri_bo_unreference(gpe_context->dynamic_state.bo); gpe_context->dynamic_state.bo = NULL; dri_bo_unreference(gpe_context->indirect_state.bo); gpe_context->indirect_state.bo = NULL; } void gen8_gpe_load_kernels(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_kernel *kernel_list, unsigned int num_kernels) { struct i965_driver_data *i965 = i965_driver_data(ctx); int i, kernel_size; unsigned int kernel_offset, end_offset; unsigned char *kernel_ptr; struct i965_kernel *kernel; assert(num_kernels <= MAX_GPE_KERNELS); memcpy(gpe_context->kernels, kernel_list, sizeof(*kernel_list) * num_kernels); gpe_context->num_kernels = num_kernels; kernel_size = num_kernels * 64; for (i = 0; i < num_kernels; i++) { kernel = &gpe_context->kernels[i]; kernel_size += kernel->size; } gpe_context->instruction_state.bo = dri_bo_alloc(i965->intel.bufmgr, "kernel shader", kernel_size, 0x1000); if (gpe_context->instruction_state.bo == NULL) { WARN_ONCE("failure to allocate the buffer space for kernel shader\n"); return; } assert(gpe_context->instruction_state.bo); gpe_context->instruction_state.bo_size = kernel_size; gpe_context->instruction_state.end_offset = 0; end_offset = 0; dri_bo_map(gpe_context->instruction_state.bo, 1); kernel_ptr = (unsigned char *)(gpe_context->instruction_state.bo->virtual); for (i = 0; i < num_kernels; i++) { kernel_offset = ALIGN(end_offset, 64); kernel = &gpe_context->kernels[i]; kernel->kernel_offset = kernel_offset; if (kernel->size) { memcpy(kernel_ptr + kernel_offset, kernel->bin, kernel->size); end_offset = kernel_offset + kernel->size; } } gpe_context->instruction_state.end_offset = end_offset; dri_bo_unmap(gpe_context->instruction_state.bo); return; } intel-driver-1.3.0/src/i965_gpe_utils.h000066400000000000000000000206661231401140700176310ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ #ifndef _I965_GPE_UTILS_H_ #define _I965_GPE_UTILS_H_ #include #include #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_structs.h" #define MAX_GPE_KERNELS 32 struct i965_buffer_surface { dri_bo *bo; unsigned int num_blocks; unsigned int size_block; unsigned int pitch; }; struct i965_gpe_context { struct { dri_bo *bo; unsigned int length; /* in bytes */ } surface_state_binding_table; struct { dri_bo *bo; unsigned int max_entries; unsigned int entry_size; /* in bytes */ } idrt; struct { dri_bo *bo; unsigned int length; /* in bytes */ } curbe; struct { unsigned int gpgpu_mode : 1; unsigned int pad0 : 7; unsigned int max_num_threads : 16; unsigned int num_urb_entries : 8; unsigned int urb_entry_size : 16; unsigned int curbe_allocation_size : 16; } vfe_state; /* vfe_desc5/6/7 is used to determine whether the HW scoreboard is used. * If scoreboard is not used, don't touch them */ union { unsigned int dword; struct { unsigned int mask:8; unsigned int pad:22; unsigned int type:1; unsigned int enable:1; } scoreboard0; }vfe_desc5; union { unsigned int dword; struct { int delta_x0:4; int delta_y0:4; int delta_x1:4; int delta_y1:4; int delta_x2:4; int delta_y2:4; int delta_x3:4; int delta_y3:4; } scoreboard1; } vfe_desc6; union { unsigned int dword; struct { int delta_x4:4; int delta_y4:4; int delta_x5:4; int delta_y5:4; int delta_x6:4; int delta_y6:4; int delta_x7:4; int delta_y7:4; } scoreboard2; } vfe_desc7; unsigned int num_kernels; struct i965_kernel kernels[MAX_GPE_KERNELS]; struct { dri_bo *bo; int bo_size; unsigned int end_offset; } instruction_state; struct { dri_bo *bo; } indirect_state; struct { dri_bo *bo; int bo_size; unsigned int end_offset; } dynamic_state; unsigned int sampler_offset; int sampler_size; unsigned int idrt_offset; int idrt_size; unsigned int curbe_offset; int curbe_size; }; void i965_gpe_context_destroy(struct i965_gpe_context *gpe_context); void i965_gpe_context_init(VADriverContextP ctx, struct i965_gpe_context *gpe_context); void i965_gpe_load_kernels(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_kernel *kernel_list, unsigned int num_kernels); void gen6_gpe_pipeline_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch); void i965_gpe_surface2_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); void i965_gpe_media_rw_surface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); void i965_gpe_buffer_suface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_buffer_surface *buffer_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); void gen7_gpe_surface2_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); void gen7_gpe_media_rw_surface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); void gen7_gpe_buffer_suface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_buffer_surface *buffer_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); void gen75_gpe_media_chroma_surface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); extern void gen8_gpe_surface2_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); extern void gen8_gpe_media_rw_surface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); extern void gen8_gpe_buffer_suface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_buffer_surface *buffer_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); extern void gen8_gpe_media_chroma_surface_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct object_surface *obj_surface, unsigned long binding_table_offset, unsigned long surface_state_offset); void gen8_gpe_pipeline_setup(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct intel_batchbuffer *batch); void gen8_gpe_context_destroy(struct i965_gpe_context *gpe_context); void gen8_gpe_context_init(VADriverContextP ctx, struct i965_gpe_context *gpe_context); void gen8_gpe_load_kernels(VADriverContextP ctx, struct i965_gpe_context *gpe_context, struct i965_kernel *kernel_list, unsigned int num_kernels); #endif /* _I965_GPE_UTILS_H_ */ intel-driver-1.3.0/src/i965_media.c000066400000000000000000000322641231401140700167050ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * Zou Nan hai * */ #include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_media.h" #include "i965_media_mpeg2.h" #include "i965_media_h264.h" #include "i965_decoder_utils.h" static void i965_media_pipeline_select(VADriverContextP ctx, struct i965_media_context *media_context) { struct intel_batchbuffer *batch = media_context->base.batch; BEGIN_BATCH(batch, 1); OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); ADVANCE_BATCH(batch); } static void i965_media_urb_layout(VADriverContextP ctx, struct i965_media_context *media_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = media_context->base.batch; unsigned int vfe_fence, cs_fence; vfe_fence = media_context->urb.cs_start; cs_fence = URB_SIZE((&i965->intel)); BEGIN_BATCH(batch, 3); OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1); OUT_BATCH(batch, 0); OUT_BATCH(batch, (vfe_fence << UF2_VFE_FENCE_SHIFT) | /* VFE_SIZE */ (cs_fence << UF2_CS_FENCE_SHIFT)); /* CS_SIZE */ ADVANCE_BATCH(batch); } static void i965_media_state_base_address(VADriverContextP ctx, struct i965_media_context *media_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = media_context->base.batch; if (IS_IRONLAKE(i965->intel.device_id)) { BEGIN_BATCH(batch, 8); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); if (media_context->indirect_object.bo) { OUT_RELOC(batch, media_context->indirect_object.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, media_context->indirect_object.offset | BASE_ADDRESS_MODIFY); } else { OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); } OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); ADVANCE_BATCH(batch); } else { BEGIN_BATCH(batch, 6); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); if (media_context->indirect_object.bo) { OUT_RELOC(batch, media_context->indirect_object.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, media_context->indirect_object.offset | BASE_ADDRESS_MODIFY); } else { OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); } OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); ADVANCE_BATCH(batch); } } static void i965_media_state_pointers(VADriverContextP ctx, struct i965_media_context *media_context) { struct intel_batchbuffer *batch = media_context->base.batch; BEGIN_BATCH(batch, 3); OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1); if (media_context->extended_state.enabled) OUT_RELOC(batch, media_context->extended_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); else OUT_BATCH(batch, 0); OUT_RELOC(batch, media_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_BATCH(batch); } static void i965_media_cs_urb_layout(VADriverContextP ctx, struct i965_media_context *media_context) { struct intel_batchbuffer *batch = media_context->base.batch; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, CMD_CS_URB_STATE | 0); OUT_BATCH(batch, ((media_context->urb.size_cs_entry - 1) << 4) | /* URB Entry Allocation Size */ (media_context->urb.num_cs_entries << 0)); /* Number of URB Entries */ ADVANCE_BATCH(batch); } static void i965_media_pipeline_state(VADriverContextP ctx, struct i965_media_context *media_context) { i965_media_state_base_address(ctx, media_context); i965_media_state_pointers(ctx, media_context); i965_media_cs_urb_layout(ctx, media_context); } static void i965_media_constant_buffer(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct intel_batchbuffer *batch = media_context->base.batch; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2)); OUT_RELOC(batch, media_context->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, media_context->urb.size_cs_entry - 1); ADVANCE_BATCH(batch); } static void i965_media_depth_buffer(VADriverContextP ctx, struct i965_media_context *media_context) { struct intel_batchbuffer *batch = media_context->base.batch; BEGIN_BATCH(batch, 6); OUT_BATCH(batch, CMD_DEPTH_BUFFER | 4); OUT_BATCH(batch, (I965_DEPTHFORMAT_D32_FLOAT << 18) | (I965_SURFACE_NULL << 29)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void i965_media_pipeline_setup(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct intel_batchbuffer *batch = media_context->base.batch; intel_batchbuffer_start_atomic(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); /* step 1 */ i965_media_depth_buffer(ctx, media_context); i965_media_pipeline_select(ctx, media_context); /* step 2 */ i965_media_urb_layout(ctx, media_context); /* step 3 */ i965_media_pipeline_state(ctx, media_context); /* step 4 */ i965_media_constant_buffer(ctx, decode_state, media_context); /* step 5 */ assert(media_context->media_objects); media_context->media_objects(ctx, decode_state, media_context); /* step 6 */ intel_batchbuffer_end_atomic(batch); } static void i965_media_decode_init(VADriverContextP ctx, VAProfile profile, struct decode_state *decode_state, struct i965_media_context *media_context) { int i; struct i965_driver_data *i965 = i965_driver_data(ctx); dri_bo *bo; /* constant buffer */ dri_bo_unreference(media_context->curbe.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "constant buffer", 4096, 64); assert(bo); media_context->curbe.bo = bo; /* surface state */ for (i = 0; i < MAX_MEDIA_SURFACES; i++) { dri_bo_unreference(media_context->surface_state[i].bo); media_context->surface_state[i].bo = NULL; } /* binding table */ dri_bo_unreference(media_context->binding_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "binding table", MAX_MEDIA_SURFACES * sizeof(unsigned int), 32); assert(bo); media_context->binding_table.bo = bo; /* interface descriptor remapping table */ dri_bo_unreference(media_context->idrt.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "interface discriptor", MAX_INTERFACE_DESC * sizeof(struct i965_interface_descriptor), 16); assert(bo); media_context->idrt.bo = bo; /* vfe state */ dri_bo_unreference(media_context->vfe_state.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vfe state", sizeof(struct i965_vfe_state), 32); assert(bo); media_context->vfe_state.bo = bo; /* extended state */ media_context->extended_state.enabled = 0; switch (profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: i965_media_mpeg2_decode_init(ctx, decode_state, media_context); break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: i965_media_h264_decode_init(ctx, decode_state, media_context); break; default: assert(0); break; } } static VAStatus i965_media_decode_picture(VADriverContextP ctx, VAProfile profile, union codec_state *codec_state, struct hw_context *hw_context) { struct i965_media_context *media_context = (struct i965_media_context *)hw_context; struct decode_state *decode_state = &codec_state->decode; VAStatus vaStatus; vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state); if (vaStatus != VA_STATUS_SUCCESS) goto out; i965_media_decode_init(ctx, profile, decode_state, media_context); assert(media_context->media_states_setup); media_context->media_states_setup(ctx, decode_state, media_context); i965_media_pipeline_setup(ctx, decode_state, media_context); intel_batchbuffer_flush(hw_context->batch); vaStatus = VA_STATUS_SUCCESS; out: return vaStatus; } static void i965_media_context_destroy(void *hw_context) { struct i965_media_context *media_context = (struct i965_media_context *)hw_context; int i; if (media_context->free_private_context) media_context->free_private_context(&media_context->private_context); for (i = 0; i < MAX_MEDIA_SURFACES; i++) { dri_bo_unreference(media_context->surface_state[i].bo); media_context->surface_state[i].bo = NULL; } dri_bo_unreference(media_context->extended_state.bo); media_context->extended_state.bo = NULL; dri_bo_unreference(media_context->vfe_state.bo); media_context->vfe_state.bo = NULL; dri_bo_unreference(media_context->idrt.bo); media_context->idrt.bo = NULL; dri_bo_unreference(media_context->binding_table.bo); media_context->binding_table.bo = NULL; dri_bo_unreference(media_context->curbe.bo); media_context->curbe.bo = NULL; dri_bo_unreference(media_context->indirect_object.bo); media_context->indirect_object.bo = NULL; intel_batchbuffer_free(media_context->base.batch); free(media_context); } struct hw_context * g4x_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config) { struct intel_driver_data *intel = intel_driver_data(ctx); struct i965_media_context *media_context = calloc(1, sizeof(struct i965_media_context)); media_context->base.destroy = i965_media_context_destroy; media_context->base.run = i965_media_decode_picture; media_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0); switch (obj_config->profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: i965_media_mpeg2_dec_context_init(ctx, media_context); break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: case VAProfileVC1Simple: case VAProfileVC1Main: case VAProfileVC1Advanced: default: assert(0); break; } return (struct hw_context *)media_context; } struct hw_context * ironlake_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config) { struct intel_driver_data *intel = intel_driver_data(ctx); struct i965_media_context *media_context = calloc(1, sizeof(struct i965_media_context)); media_context->base.destroy = i965_media_context_destroy; media_context->base.run = i965_media_decode_picture; media_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0); switch (obj_config->profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: i965_media_mpeg2_dec_context_init(ctx, media_context); break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: i965_media_h264_dec_context_init(ctx, media_context); break; case VAProfileVC1Simple: case VAProfileVC1Main: case VAProfileVC1Advanced: default: assert(0); break; } return (struct hw_context *)media_context; } intel-driver-1.3.0/src/i965_media.h000066400000000000000000000051431231401140700167060ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * Zou Nan hai * */ #ifndef _I965_MEDIA_H_ #define _I965_MEDIA_H_ #include #include #include #include #include "i965_structs.h" #define MAX_INTERFACE_DESC 16 #define MAX_MEDIA_SURFACES 34 struct decode_state; struct i965_media_context { struct hw_context base; struct { dri_bo *bo; } surface_state[MAX_MEDIA_SURFACES]; struct { dri_bo *bo; } binding_table; struct { dri_bo *bo; } idrt; /* interface descriptor remap table */ struct { dri_bo *bo; int enabled; } extended_state; struct { dri_bo *bo; } vfe_state; struct { dri_bo *bo; } curbe; struct { dri_bo *bo; unsigned long offset; } indirect_object; struct { unsigned int vfe_start; unsigned int cs_start; unsigned int num_vfe_entries; unsigned int num_cs_entries; unsigned int size_vfe_entry; unsigned int size_cs_entry; } urb; void *private_context; void (*media_states_setup)(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context); void (*media_objects)(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context); void (*free_private_context)(void **data); }; #endif /* _I965_MEDIA_H_ */ intel-driver-1.3.0/src/i965_media_h264.c000066400000000000000000001044151231401140700174460ustar00rootroot00000000000000#include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_media.h" #include "i965_media_h264.h" enum { INTRA_16X16 = 0, INTRA_8X8, INTRA_4X4, INTRA_PCM, FRAMEMB_MOTION, FIELDMB_MOTION, MBAFF_MOTION, }; struct intra_kernel_header { /* R1.0 */ unsigned char intra_4x4_luma_mode_0_offset; unsigned char intra_4x4_luma_mode_1_offset; unsigned char intra_4x4_luma_mode_2_offset; unsigned char intra_4x4_luma_mode_3_offset; /* R1.1 */ unsigned char intra_4x4_luma_mode_4_offset; unsigned char intra_4x4_luma_mode_5_offset; unsigned char intra_4x4_luma_mode_6_offset; unsigned char intra_4x4_luma_mode_7_offset; /* R1.2 */ unsigned char intra_4x4_luma_mode_8_offset; unsigned char pad0; unsigned short top_reference_offset; /* R1.3 */ unsigned char intra_8x8_luma_mode_0_offset; unsigned char intra_8x8_luma_mode_1_offset; unsigned char intra_8x8_luma_mode_2_offset; unsigned char intra_8x8_luma_mode_3_offset; /* R1.4 */ unsigned char intra_8x8_luma_mode_4_offset; unsigned char intra_8x8_luma_mode_5_offset; unsigned char intra_8x8_luma_mode_6_offset; unsigned char intra_8x8_luma_mode_7_offset; /* R1.5 */ unsigned char intra_8x8_luma_mode_8_offset; unsigned char pad1; unsigned short const_reverse_data_transfer_intra_8x8; /* R1.6 */ unsigned char intra_16x16_luma_mode_0_offset; unsigned char intra_16x16_luma_mode_1_offset; unsigned char intra_16x16_luma_mode_2_offset; unsigned char intra_16x16_luma_mode_3_offset; /* R1.7 */ unsigned char intra_chroma_mode_0_offset; unsigned char intra_chroma_mode_1_offset; unsigned char intra_chroma_mode_2_offset; unsigned char intra_chroma_mode_3_offset; /* R2.0 */ unsigned int const_intra_16x16_plane_0; /* R2.1 */ unsigned int const_intra_16x16_chroma_plane_0; /* R2.2 */ unsigned int const_intra_16x16_chroma_plane_1; /* R2.3 */ unsigned int const_intra_16x16_plane_1; /* R2.4 */ unsigned int left_shift_count_reverse_dw_ordering; /* R2.5 */ unsigned int const_reverse_data_transfer_intra_4x4; /* R2.6 */ unsigned int intra_4x4_pred_mode_offset; }; struct inter_kernel_header { unsigned short weight_offset; unsigned char weight_offset_flag; unsigned char pad0; }; #include "shaders/h264/mc/export.inc" static unsigned long avc_mc_kernel_offset_gen4[] = { INTRA_16x16_IP * INST_UNIT_GEN4, INTRA_8x8_IP * INST_UNIT_GEN4, INTRA_4x4_IP * INST_UNIT_GEN4, INTRA_PCM_IP * INST_UNIT_GEN4, FRAME_MB_IP * INST_UNIT_GEN4, FIELD_MB_IP * INST_UNIT_GEN4, MBAFF_MB_IP * INST_UNIT_GEN4 }; struct intra_kernel_header intra_kernel_header_gen4 = { 0, (INTRA_4X4_HORIZONTAL_IP - INTRA_4X4_VERTICAL_IP), (INTRA_4X4_DC_IP - INTRA_4X4_VERTICAL_IP), (INTRA_4X4_DIAG_DOWN_LEFT_IP - INTRA_4X4_VERTICAL_IP), (INTRA_4X4_DIAG_DOWN_RIGHT_IP - INTRA_4X4_VERTICAL_IP), (INTRA_4X4_VERT_RIGHT_IP - INTRA_4X4_VERTICAL_IP), (INTRA_4X4_HOR_DOWN_IP - INTRA_4X4_VERTICAL_IP), (INTRA_4X4_VERT_LEFT_IP - INTRA_4X4_VERTICAL_IP), (INTRA_4X4_HOR_UP_IP - INTRA_4X4_VERTICAL_IP), 0, 0xFFFC, 0, (INTRA_8X8_HORIZONTAL_IP - INTRA_8X8_VERTICAL_IP), (INTRA_8X8_DC_IP - INTRA_8X8_VERTICAL_IP), (INTRA_8X8_DIAG_DOWN_LEFT_IP - INTRA_8X8_VERTICAL_IP), (INTRA_8X8_DIAG_DOWN_RIGHT_IP - INTRA_8X8_VERTICAL_IP), (INTRA_8X8_VERT_RIGHT_IP - INTRA_8X8_VERTICAL_IP), (INTRA_8X8_HOR_DOWN_IP - INTRA_8X8_VERTICAL_IP), (INTRA_8X8_VERT_LEFT_IP - INTRA_8X8_VERTICAL_IP), (INTRA_8X8_HOR_UP_IP - INTRA_8X8_VERTICAL_IP), 0, 0x0001, 0, (INTRA_16x16_HORIZONTAL_IP - INTRA_16x16_VERTICAL_IP), (INTRA_16x16_DC_IP - INTRA_16x16_VERTICAL_IP), (INTRA_16x16_PLANE_IP - INTRA_16x16_VERTICAL_IP), 0, (INTRA_CHROMA_HORIZONTAL_IP - INTRA_CHROMA_DC_IP), (INTRA_CHROMA_VERTICAL_IP - INTRA_CHROMA_DC_IP), (INTRA_Chroma_PLANE_IP - INTRA_CHROMA_DC_IP), 0xFCFBFAF9, 0x00FFFEFD, 0x04030201, 0x08070605, 0x18100800, 0x00020406, (intra_Pred_4x4_Y_IP - ADD_ERROR_SB3_IP) * 0x1000000 + (intra_Pred_4x4_Y_IP - ADD_ERROR_SB2_IP) * 0x10000 + (intra_Pred_4x4_Y_IP - ADD_ERROR_SB1_IP) * 0x100 + (intra_Pred_4x4_Y_IP - ADD_ERROR_SB0_IP) }; static const uint32_t h264_avc_combined_gen4[][4] = { #include "shaders/h264/mc/avc_mc.g4b" }; static const uint32_t h264_avc_null_gen4[][4] = { #include "shaders/h264/mc/null.g4b" }; static struct i965_kernel h264_avc_kernels_gen4[] = { { "AVC combined kernel", H264_AVC_COMBINED, h264_avc_combined_gen4, sizeof(h264_avc_combined_gen4), NULL }, { "NULL kernel", H264_AVC_NULL, h264_avc_null_gen4, sizeof(h264_avc_null_gen4), NULL } }; /* On Ironlake */ #include "shaders/h264/mc/export.inc.gen5" static unsigned long avc_mc_kernel_offset_gen5[] = { INTRA_16x16_IP_GEN5 * INST_UNIT_GEN5, INTRA_8x8_IP_GEN5 * INST_UNIT_GEN5, INTRA_4x4_IP_GEN5 * INST_UNIT_GEN5, INTRA_PCM_IP_GEN5 * INST_UNIT_GEN5, FRAME_MB_IP_GEN5 * INST_UNIT_GEN5, FIELD_MB_IP_GEN5 * INST_UNIT_GEN5, MBAFF_MB_IP_GEN5 * INST_UNIT_GEN5 }; struct intra_kernel_header intra_kernel_header_gen5 = { 0, (INTRA_4X4_HORIZONTAL_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5), (INTRA_4X4_DC_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5), (INTRA_4X4_DIAG_DOWN_LEFT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5), (INTRA_4X4_DIAG_DOWN_RIGHT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5), (INTRA_4X4_VERT_RIGHT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5), (INTRA_4X4_HOR_DOWN_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5), (INTRA_4X4_VERT_LEFT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5), (INTRA_4X4_HOR_UP_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5), 0, 0xFFFC, 0, (INTRA_8X8_HORIZONTAL_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5), (INTRA_8X8_DC_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5), (INTRA_8X8_DIAG_DOWN_LEFT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5), (INTRA_8X8_DIAG_DOWN_RIGHT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5), (INTRA_8X8_VERT_RIGHT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5), (INTRA_8X8_HOR_DOWN_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5), (INTRA_8X8_VERT_LEFT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5), (INTRA_8X8_HOR_UP_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5), 0, 0x0001, 0, (INTRA_16x16_HORIZONTAL_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5), (INTRA_16x16_DC_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5), (INTRA_16x16_PLANE_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5), 0, (INTRA_CHROMA_HORIZONTAL_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5), (INTRA_CHROMA_VERTICAL_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5), (INTRA_Chroma_PLANE_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5), 0xFCFBFAF9, 0x00FFFEFD, 0x04030201, 0x08070605, 0x18100800, 0x00020406, (intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB3_IP_GEN5) * 0x1000000 + (intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB2_IP_GEN5) * 0x10000 + (intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB1_IP_GEN5) * 0x100 + (intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB0_IP_GEN5) }; static const uint32_t h264_avc_combined_gen5[][4] = { #include "shaders/h264/mc/avc_mc.g4b.gen5" }; static const uint32_t h264_avc_null_gen5[][4] = { #include "shaders/h264/mc/null.g4b.gen5" }; static struct i965_kernel h264_avc_kernels_gen5[] = { { "AVC combined kernel", H264_AVC_COMBINED, h264_avc_combined_gen5, sizeof(h264_avc_combined_gen5), NULL }, { "NULL kernel", H264_AVC_NULL, h264_avc_null_gen5, sizeof(h264_avc_null_gen5), NULL } }; #define NUM_AVC_MC_INTERFACES (sizeof(avc_mc_kernel_offset_gen4) / sizeof(avc_mc_kernel_offset_gen4[0])) static unsigned long *avc_mc_kernel_offset = NULL; static struct intra_kernel_header *intra_kernel_header = NULL; static void i965_media_h264_surface_state(VADriverContextP ctx, int index, struct object_surface *obj_surface, unsigned long offset, int w, int h, int pitch, Bool is_dst, int vert_line_stride, int vert_line_stride_ofs, int format, struct i965_media_context *media_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_surface_state *ss; dri_bo *bo; uint32_t write_domain, read_domain; assert(obj_surface->bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state", sizeof(struct i965_surface_state), 32); assert(bo); dri_bo_map(bo, 1); assert(bo->virtual); ss = bo->virtual; memset(ss, 0, sizeof(*ss)); ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = format; ss->ss0.vert_line_stride = vert_line_stride; ss->ss0.vert_line_stride_ofs = vert_line_stride_ofs; ss->ss1.base_addr = obj_surface->bo->offset + offset; ss->ss2.width = w - 1; ss->ss2.height = h - 1; ss->ss3.pitch = pitch - 1; if (is_dst) { write_domain = I915_GEM_DOMAIN_RENDER; read_domain = I915_GEM_DOMAIN_RENDER; } else { write_domain = 0; read_domain = I915_GEM_DOMAIN_SAMPLER; } dri_bo_emit_reloc(bo, read_domain, write_domain, offset, offsetof(struct i965_surface_state, ss1), obj_surface->bo); dri_bo_unmap(bo); assert(index < MAX_MEDIA_SURFACES); media_context->surface_state[index].bo = bo; } static void i965_media_h264_surfaces_setup(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct i965_h264_context *i965_h264_context; struct object_surface *obj_surface; VAPictureParameterBufferH264 *pic_param; VAPictureH264 *va_pic; int i, j, w, h; int field_picture; assert(media_context->private_context); i965_h264_context = (struct i965_h264_context *)media_context->private_context; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; /* Target Picture */ va_pic = &pic_param->CurrPic; obj_surface = decode_state->render_object; w = obj_surface->width; h = obj_surface->height; field_picture = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD)); i965_media_h264_surface_state(ctx, 0, obj_surface, 0, w / 4, h / (1 + field_picture), w, 1, field_picture, !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD), I965_SURFACEFORMAT_R8_SINT, /* Y */ media_context); i965_media_h264_surface_state(ctx, 1, obj_surface, w * h, w / 4, h / 2 / (1 + field_picture), w, 1, field_picture, !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD), I965_SURFACEFORMAT_R8G8_SINT, /* INTERLEAVED U/V */ media_context); /* Reference Pictures */ for (i = 0; i < ARRAY_ELEMS(i965_h264_context->fsid_list); i++) { if (i965_h264_context->fsid_list[i].surface_id != VA_INVALID_ID && i965_h264_context->fsid_list[i].obj_surface != NULL) { int found = 0; for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) { va_pic = &pic_param->ReferenceFrames[j]; if (va_pic->flags & VA_PICTURE_H264_INVALID) continue; if (va_pic->picture_id == i965_h264_context->fsid_list[i].surface_id) { found = 1; break; } } assert(found == 1); obj_surface = i965_h264_context->fsid_list[i].obj_surface; w = obj_surface->width; h = obj_surface->height; field_picture = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD)); i965_media_h264_surface_state(ctx, 2 + i, obj_surface, 0, w / 4, h / (1 + field_picture), w, 0, field_picture, !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD), I965_SURFACEFORMAT_R8_SINT, /* Y */ media_context); i965_media_h264_surface_state(ctx, 18 + i, obj_surface, w * h, w / 4, h / 2 / (1 + field_picture), w, 0, field_picture, !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD), I965_SURFACEFORMAT_R8G8_SINT, /* INTERLEAVED U/V */ media_context); } } } static void i965_media_h264_binding_table(VADriverContextP ctx, struct i965_media_context *media_context) { int i; unsigned int *binding_table; dri_bo *bo = media_context->binding_table.bo; dri_bo_map(bo, 1); assert(bo->virtual); binding_table = bo->virtual; memset(binding_table, 0, bo->size); for (i = 0; i < MAX_MEDIA_SURFACES; i++) { if (media_context->surface_state[i].bo) { binding_table[i] = media_context->surface_state[i].bo->offset; dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, i * sizeof(*binding_table), media_context->surface_state[i].bo); } } dri_bo_unmap(media_context->binding_table.bo); } static void i965_media_h264_interface_descriptor_remap_table(VADriverContextP ctx, struct i965_media_context *media_context) { struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_context->private_context; struct i965_interface_descriptor *desc; int i; dri_bo *bo; bo = media_context->idrt.bo; dri_bo_map(bo, 1); assert(bo->virtual); desc = bo->virtual; for (i = 0; i < NUM_AVC_MC_INTERFACES; i++) { int kernel_offset = avc_mc_kernel_offset[i]; memset(desc, 0, sizeof(*desc)); desc->desc0.grf_reg_blocks = 7; desc->desc0.kernel_start_pointer = (i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */ desc->desc1.const_urb_entry_read_offset = 0; desc->desc1.const_urb_entry_read_len = 2; desc->desc3.binding_table_entry_count = 0; desc->desc3.binding_table_pointer = media_context->binding_table.bo->offset >> 5; /*reloc */ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, desc->desc0.grf_reg_blocks + kernel_offset, i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0), i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, desc->desc3.binding_table_entry_count, i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc3), media_context->binding_table.bo); desc++; } dri_bo_unmap(bo); } static void i965_media_h264_vfe_state(VADriverContextP ctx, struct i965_media_context *media_context) { struct i965_vfe_state *vfe_state; dri_bo *bo; bo = media_context->vfe_state.bo; dri_bo_map(bo, 1); assert(bo->virtual); vfe_state = bo->virtual; memset(vfe_state, 0, sizeof(*vfe_state)); vfe_state->vfe0.extend_vfe_state_present = 1; vfe_state->vfe1.max_threads = media_context->urb.num_vfe_entries - 1; vfe_state->vfe1.urb_entry_alloc_size = media_context->urb.size_vfe_entry - 1; vfe_state->vfe1.num_urb_entries = media_context->urb.num_vfe_entries; vfe_state->vfe1.vfe_mode = VFE_AVC_IT_MODE; vfe_state->vfe1.children_present = 0; vfe_state->vfe2.interface_descriptor_base = media_context->idrt.bo->offset >> 4; /* reloc */ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, offsetof(struct i965_vfe_state, vfe2), media_context->idrt.bo); dri_bo_unmap(bo); } static void i965_media_h264_vfe_state_extension(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct i965_h264_context *i965_h264_context; struct i965_vfe_state_ex *vfe_state_ex; VAPictureParameterBufferH264 *pic_param; int mbaff_frame_flag; assert(media_context->private_context); i965_h264_context = (struct i965_h264_context *)media_context->private_context; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag && !pic_param->pic_fields.bits.field_pic_flag); assert(media_context->extended_state.bo); dri_bo_map(media_context->extended_state.bo, 1); assert(media_context->extended_state.bo->virtual); vfe_state_ex = media_context->extended_state.bo->virtual; memset(vfe_state_ex, 0, sizeof(*vfe_state_ex)); /* * Indirect data buffer: * -------------------------------------------------------- * | Motion Vectors | Weight/Offset data | Residual data | * -------------------------------------------------------- * R4-R7: Motion Vectors * R8-R9: Weight/Offset * R10-R33: Residual data */ vfe_state_ex->vfex1.avc.residual_data_fix_offset_flag = !!RESIDUAL_DATA_OFFSET; vfe_state_ex->vfex1.avc.residual_data_offset = RESIDUAL_DATA_OFFSET; if (i965_h264_context->picture.i_flag) { vfe_state_ex->vfex1.avc.sub_field_present_flag = PRESENT_NOMV; /* NoMV */ vfe_state_ex->vfex1.avc.weight_grf_offset = 0; vfe_state_ex->vfex1.avc.residual_grf_offset = 0; } else { vfe_state_ex->vfex1.avc.sub_field_present_flag = PRESENT_MV_WO; /* Both MV and W/O */ vfe_state_ex->vfex1.avc.weight_grf_offset = 4; vfe_state_ex->vfex1.avc.residual_grf_offset = 6; } if (!pic_param->pic_fields.bits.field_pic_flag) { if (mbaff_frame_flag) { vfe_state_ex->remap_table0.remap_index_0 = INTRA_16X16; vfe_state_ex->remap_table0.remap_index_1 = INTRA_8X8; vfe_state_ex->remap_table0.remap_index_2 = INTRA_4X4; vfe_state_ex->remap_table0.remap_index_3 = INTRA_PCM; vfe_state_ex->remap_table0.remap_index_4 = MBAFF_MOTION; vfe_state_ex->remap_table0.remap_index_5 = MBAFF_MOTION; vfe_state_ex->remap_table0.remap_index_6 = MBAFF_MOTION; vfe_state_ex->remap_table0.remap_index_7 = MBAFF_MOTION; vfe_state_ex->remap_table1.remap_index_8 = MBAFF_MOTION; vfe_state_ex->remap_table1.remap_index_9 = MBAFF_MOTION; vfe_state_ex->remap_table1.remap_index_10 = MBAFF_MOTION; vfe_state_ex->remap_table1.remap_index_11 = MBAFF_MOTION; vfe_state_ex->remap_table1.remap_index_12 = MBAFF_MOTION; vfe_state_ex->remap_table1.remap_index_13 = MBAFF_MOTION; vfe_state_ex->remap_table1.remap_index_14 = MBAFF_MOTION; vfe_state_ex->remap_table1.remap_index_15 = MBAFF_MOTION; } else { vfe_state_ex->remap_table0.remap_index_0 = INTRA_16X16; vfe_state_ex->remap_table0.remap_index_1 = INTRA_8X8; vfe_state_ex->remap_table0.remap_index_2 = INTRA_4X4; vfe_state_ex->remap_table0.remap_index_3 = INTRA_PCM; vfe_state_ex->remap_table0.remap_index_4 = FRAMEMB_MOTION; vfe_state_ex->remap_table0.remap_index_5 = FRAMEMB_MOTION; vfe_state_ex->remap_table0.remap_index_6 = FRAMEMB_MOTION; vfe_state_ex->remap_table0.remap_index_7 = FRAMEMB_MOTION; vfe_state_ex->remap_table1.remap_index_8 = FRAMEMB_MOTION; vfe_state_ex->remap_table1.remap_index_9 = FRAMEMB_MOTION; vfe_state_ex->remap_table1.remap_index_10 = FRAMEMB_MOTION; vfe_state_ex->remap_table1.remap_index_11 = FRAMEMB_MOTION; vfe_state_ex->remap_table1.remap_index_12 = FRAMEMB_MOTION; vfe_state_ex->remap_table1.remap_index_13 = FRAMEMB_MOTION; vfe_state_ex->remap_table1.remap_index_14 = FRAMEMB_MOTION; vfe_state_ex->remap_table1.remap_index_15 = FRAMEMB_MOTION; } } else { vfe_state_ex->remap_table0.remap_index_0 = INTRA_16X16; vfe_state_ex->remap_table0.remap_index_1 = INTRA_8X8; vfe_state_ex->remap_table0.remap_index_2 = INTRA_4X4; vfe_state_ex->remap_table0.remap_index_3 = INTRA_PCM; vfe_state_ex->remap_table0.remap_index_4 = FIELDMB_MOTION; vfe_state_ex->remap_table0.remap_index_5 = FIELDMB_MOTION; vfe_state_ex->remap_table0.remap_index_6 = FIELDMB_MOTION; vfe_state_ex->remap_table0.remap_index_7 = FIELDMB_MOTION; vfe_state_ex->remap_table1.remap_index_8 = FIELDMB_MOTION; vfe_state_ex->remap_table1.remap_index_9 = FIELDMB_MOTION; vfe_state_ex->remap_table1.remap_index_10 = FIELDMB_MOTION; vfe_state_ex->remap_table1.remap_index_11 = FIELDMB_MOTION; vfe_state_ex->remap_table1.remap_index_12 = FIELDMB_MOTION; vfe_state_ex->remap_table1.remap_index_13 = FIELDMB_MOTION; vfe_state_ex->remap_table1.remap_index_14 = FIELDMB_MOTION; vfe_state_ex->remap_table1.remap_index_15 = FIELDMB_MOTION; } if (i965_h264_context->use_avc_hw_scoreboard) { vfe_state_ex->scoreboard0.enable = 1; vfe_state_ex->scoreboard0.type = SCOREBOARD_STALLING; vfe_state_ex->scoreboard0.mask = 0xff; vfe_state_ex->scoreboard1.delta_x0 = -1; vfe_state_ex->scoreboard1.delta_y0 = 0; vfe_state_ex->scoreboard1.delta_x1 = 0; vfe_state_ex->scoreboard1.delta_y1 = -1; vfe_state_ex->scoreboard1.delta_x2 = 1; vfe_state_ex->scoreboard1.delta_y2 = -1; vfe_state_ex->scoreboard1.delta_x3 = -1; vfe_state_ex->scoreboard1.delta_y3 = -1; vfe_state_ex->scoreboard2.delta_x4 = -1; vfe_state_ex->scoreboard2.delta_y4 = 1; vfe_state_ex->scoreboard2.delta_x5 = 0; vfe_state_ex->scoreboard2.delta_y5 = -2; vfe_state_ex->scoreboard2.delta_x6 = 1; vfe_state_ex->scoreboard2.delta_y6 = -2; vfe_state_ex->scoreboard2.delta_x7 = -1; vfe_state_ex->scoreboard2.delta_y7 = -2; } dri_bo_unmap(media_context->extended_state.bo); } static void i965_media_h264_upload_constants(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct i965_h264_context *i965_h264_context; unsigned char *constant_buffer; VASliceParameterBufferH264 *slice_param; assert(media_context->private_context); i965_h264_context = (struct i965_h264_context *)media_context->private_context; assert(decode_state->slice_params[0] && decode_state->slice_params[0]->buffer); slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[0]->buffer; dri_bo_map(media_context->curbe.bo, 1); assert(media_context->curbe.bo->virtual); constant_buffer = media_context->curbe.bo->virtual; /* HW solution for W=128 */ if (i965_h264_context->use_hw_w128) { memcpy(constant_buffer, intra_kernel_header, sizeof(*intra_kernel_header)); } else { if (slice_param->slice_type == SLICE_TYPE_I || slice_param->slice_type == SLICE_TYPE_SI) { memcpy(constant_buffer, intra_kernel_header, sizeof(*intra_kernel_header)); } else { /* FIXME: Need to upload CURBE data to inter kernel interface * to support weighted prediction work-around */ *(short *)constant_buffer = i965_h264_context->weight128_offset0; constant_buffer += 2; *(char *)constant_buffer = i965_h264_context->weight128_offset0_flag; constant_buffer++; *constant_buffer = 0; } } dri_bo_unmap(media_context->curbe.bo); } static void i965_media_h264_states_setup(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct i965_h264_context *i965_h264_context; assert(media_context->private_context); i965_h264_context = (struct i965_h264_context *)media_context->private_context; i965_avc_bsd_pipeline(ctx, decode_state, i965_h264_context); if (i965_h264_context->use_avc_hw_scoreboard) i965_avc_hw_scoreboard(ctx, decode_state, i965_h264_context); i965_media_h264_surfaces_setup(ctx, decode_state, media_context); i965_media_h264_binding_table(ctx, media_context); i965_media_h264_interface_descriptor_remap_table(ctx, media_context); i965_media_h264_vfe_state_extension(ctx, decode_state, media_context); i965_media_h264_vfe_state(ctx, media_context); i965_media_h264_upload_constants(ctx, decode_state, media_context); } static void i965_media_h264_objects(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct intel_batchbuffer *batch = media_context->base.batch; struct i965_h264_context *i965_h264_context; unsigned int *object_command; assert(media_context->private_context); i965_h264_context = (struct i965_h264_context *)media_context->private_context; dri_bo_map(i965_h264_context->avc_it_command_mb_info.bo, True); assert(i965_h264_context->avc_it_command_mb_info.bo->virtual); object_command = i965_h264_context->avc_it_command_mb_info.bo->virtual; memset(object_command, 0, i965_h264_context->avc_it_command_mb_info.mbs * i965_h264_context->use_avc_hw_scoreboard * MB_CMD_IN_BYTES); object_command += i965_h264_context->avc_it_command_mb_info.mbs * (1 + i965_h264_context->use_avc_hw_scoreboard) * MB_CMD_IN_DWS; *object_command++ = 0; *object_command = MI_BATCH_BUFFER_END; dri_bo_unmap(i965_h264_context->avc_it_command_mb_info.bo); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6)); OUT_RELOC(batch, i965_h264_context->avc_it_command_mb_info.bo, I915_GEM_DOMAIN_COMMAND, 0, 0); ADVANCE_BATCH(batch); /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END * will cause control to pass back to ring buffer */ intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); intel_batchbuffer_start_atomic(batch, 0x1000); i965_avc_ildb(ctx, decode_state, i965_h264_context); } static void i965_media_h264_free_private_context(void **data) { struct i965_h264_context *i965_h264_context = *data; int i; if (i965_h264_context == NULL) return; i965_avc_ildb_ternimate(&i965_h264_context->avc_ildb_context); i965_avc_hw_scoreboard_ternimate(&i965_h264_context->avc_hw_scoreboard_context); i965_avc_bsd_ternimate(&i965_h264_context->i965_avc_bsd_context); dri_bo_unreference(i965_h264_context->avc_it_command_mb_info.bo); dri_bo_unreference(i965_h264_context->avc_it_data.bo); dri_bo_unreference(i965_h264_context->avc_ildb_data.bo); for (i = 0; i < NUM_H264_AVC_KERNELS; i++) { struct i965_kernel *kernel = &i965_h264_context->avc_kernels[i]; dri_bo_unreference(kernel->bo); kernel->bo = NULL; } free(i965_h264_context); *data = NULL; } void i965_media_h264_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_h264_context *i965_h264_context = media_context->private_context; dri_bo *bo; VAPictureParameterBufferH264 *pic_param; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer; i965_h264_context->picture.width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff); i965_h264_context->picture.height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff) / (1 + !!pic_param->pic_fields.bits.field_pic_flag); /* picture height */ i965_h264_context->picture.mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag && !pic_param->pic_fields.bits.field_pic_flag); i965_h264_context->avc_it_command_mb_info.mbs = (i965_h264_context->picture.width_in_mbs * i965_h264_context->picture.height_in_mbs); dri_bo_unreference(i965_h264_context->avc_it_command_mb_info.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "avc it command mb info", i965_h264_context->avc_it_command_mb_info.mbs * MB_CMD_IN_BYTES * (1 + i965_h264_context->use_avc_hw_scoreboard) + 8, 0x1000); assert(bo); i965_h264_context->avc_it_command_mb_info.bo = bo; dri_bo_unreference(i965_h264_context->avc_it_data.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "avc it data", i965_h264_context->avc_it_command_mb_info.mbs * 0x800 * (1 + !!pic_param->pic_fields.bits.field_pic_flag), 0x1000); assert(bo); i965_h264_context->avc_it_data.bo = bo; i965_h264_context->avc_it_data.write_offset = 0; dri_bo_unreference(media_context->indirect_object.bo); media_context->indirect_object.bo = bo; dri_bo_reference(media_context->indirect_object.bo); media_context->indirect_object.offset = i965_h264_context->avc_it_data.write_offset; dri_bo_unreference(i965_h264_context->avc_ildb_data.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "AVC-ILDB Data Buffer", i965_h264_context->avc_it_command_mb_info.mbs * 64 * 2, 0x1000); assert(bo); i965_h264_context->avc_ildb_data.bo = bo; /* bsd pipeline */ i965_avc_bsd_decode_init(ctx, i965_h264_context); /* HW scoreboard */ if (i965_h264_context->use_avc_hw_scoreboard) i965_avc_hw_scoreboard_decode_init(ctx, i965_h264_context); /* ILDB */ i965_avc_ildb_decode_init(ctx, i965_h264_context); /* for Media pipeline */ media_context->extended_state.enabled = 1; dri_bo_unreference(media_context->extended_state.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "extened vfe state", sizeof(struct i965_vfe_state_ex), 32); assert(bo); media_context->extended_state.bo = bo; } void i965_media_h264_dec_context_init(VADriverContextP ctx, struct i965_media_context *media_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_h264_context *i965_h264_context; int i; i965_h264_context = calloc(1, sizeof(struct i965_h264_context)); /* kernel */ assert(NUM_H264_AVC_KERNELS == (sizeof(h264_avc_kernels_gen5) / sizeof(h264_avc_kernels_gen5[0]))); assert(NUM_AVC_MC_INTERFACES == (sizeof(avc_mc_kernel_offset_gen5) / sizeof(avc_mc_kernel_offset_gen5[0]))); if (IS_IRONLAKE(i965->intel.device_id)) { memcpy(i965_h264_context->avc_kernels, h264_avc_kernels_gen5, sizeof(i965_h264_context->avc_kernels)); avc_mc_kernel_offset = avc_mc_kernel_offset_gen5; intra_kernel_header = &intra_kernel_header_gen5; i965_h264_context->use_avc_hw_scoreboard = 1; i965_h264_context->use_hw_w128 = 1; } else { memcpy(i965_h264_context->avc_kernels, h264_avc_kernels_gen4, sizeof(i965_h264_context->avc_kernels)); avc_mc_kernel_offset = avc_mc_kernel_offset_gen4; intra_kernel_header = &intra_kernel_header_gen4; i965_h264_context->use_avc_hw_scoreboard = 0; i965_h264_context->use_hw_w128 = 0; } for (i = 0; i < NUM_H264_AVC_KERNELS; i++) { struct i965_kernel *kernel = &i965_h264_context->avc_kernels[i]; kernel->bo = dri_bo_alloc(i965->intel.bufmgr, kernel->name, kernel->size, 0x1000); assert(kernel->bo); dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin); } for (i = 0; i < 16; i++) { i965_h264_context->fsid_list[i].surface_id = VA_INVALID_ID; i965_h264_context->fsid_list[i].frame_store_id = -1; } i965_h264_context->batch = media_context->base.batch; media_context->private_context = i965_h264_context; media_context->free_private_context = i965_media_h264_free_private_context; /* URB */ if (IS_IRONLAKE(i965->intel.device_id)) { media_context->urb.num_vfe_entries = 63; } else { media_context->urb.num_vfe_entries = 23; } media_context->urb.size_vfe_entry = 16; media_context->urb.num_cs_entries = 1; media_context->urb.size_cs_entry = 1; media_context->urb.vfe_start = 0; media_context->urb.cs_start = media_context->urb.vfe_start + media_context->urb.num_vfe_entries * media_context->urb.size_vfe_entry; assert(media_context->urb.cs_start + media_context->urb.num_cs_entries * media_context->urb.size_cs_entry <= URB_SIZE((&i965->intel))); /* hook functions */ media_context->media_states_setup = i965_media_h264_states_setup; media_context->media_objects = i965_media_h264_objects; } intel-driver-1.3.0/src/i965_media_h264.h000066400000000000000000000033431231401140700174510ustar00rootroot00000000000000#ifndef _I965_MEDIA_H264_H_ #define _I965_MEDIA_H264_H_ #include "i965_avc_bsd.h" #include "i965_avc_hw_scoreboard.h" #include "i965_avc_ildb.h" #include "i965_decoder.h" struct decode_state; struct i965_media_context; #define INST_UNIT_GEN4 16 #define INST_UNIT_GEN5 8 #define MB_CMD_IN_BYTES 64 #define MB_CMD_IN_DWS 16 #define MB_CMD_IN_OWS 4 enum { H264_AVC_COMBINED = 0, H264_AVC_NULL }; #define NUM_H264_AVC_KERNELS 2 struct i965_h264_context { struct { dri_bo *bo; unsigned int mbs; } avc_it_command_mb_info; struct { dri_bo *bo; long write_offset; } avc_it_data; struct { dri_bo *bo; } avc_ildb_data; struct { unsigned int width_in_mbs; unsigned int height_in_mbs; int mbaff_frame_flag; int i_flag; } picture; int enable_avc_ildb; int use_avc_hw_scoreboard; int use_hw_w128; unsigned int weight128_luma_l0; unsigned int weight128_luma_l1; unsigned int weight128_chroma_l0; unsigned int weight128_chroma_l1; char weight128_offset0_flag; short weight128_offset0; struct i965_avc_bsd_context i965_avc_bsd_context; struct i965_avc_hw_scoreboard_context avc_hw_scoreboard_context; struct i965_avc_ildb_context avc_ildb_context; GenFrameStore fsid_list[MAX_GEN_REFERENCE_FRAMES]; struct i965_kernel avc_kernels[NUM_H264_AVC_KERNELS]; struct intel_batchbuffer *batch; }; void i965_media_h264_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context); void i965_media_h264_dec_context_init(VADriverContextP ctx, struct i965_media_context *media_context); #endif /* _I965_MEDIA_H264_H_ */ intel-driver-1.3.0/src/i965_media_mpeg2.c000066400000000000000000001074301231401140700177750ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * Zou Nan hai * */ #include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_decoder_utils.h" #include "i965_media.h" #include "i965_media_mpeg2.h" #define SURFACE_TARGET 0 #define SURFACE_FORWARD 1 #define SURFACE_BACKWARD 2 #define SURFACE_BIDIRECT 3 enum interface { FRAME_INTRA = 0, FRAME_FRAME_PRED_FORWARD, FRAME_FRAME_PRED_BACKWARD, FRAME_FRAME_PRED_BIDIRECT, FRAME_FIELD_PRED_FORWARD, FRAME_FIELD_PRED_BACKWARD, FRAME_FIELD_PRED_BIDIRECT, LIB_INTERFACE, FIELD_INTRA, FIELD_FORWARD, FIELD_FORWARD_16X8, FIELD_BACKWARD, FIELD_BACKWARD_16X8, FIELD_BIDIRECT, FIELD_BIDIRECT_16X8 }; /* idct table */ #define C0 23170 #define C1 22725 #define C2 21407 #define C3 19266 #define C4 16383 #define C5 12873 #define C6 8867 #define C7 4520 const uint32_t idct_table[] = { C4, C1, C2, C3, C4, C5, C6, C7, //g5 C4, C1, C2, C3, C4, C5, C6, C7, C4, C3, C6,-C7,-C4,-C1,-C2,-C5, C4, C3, C6,-C7,-C4,-C1,-C2,-C5, C4, C5,-C6,-C1,-C4, C7, C2, C3, C4, C5,-C6,-C1,-C4, C7, C2, C3, C4, C7,-C2,-C5, C4, C3,-C6,-C1, C4, C7,-C2,-C5, C4, C3,-C6,-C1, C4,-C7,-C2, C5, C4,-C3,-C6, C1, C4,-C7,-C2, C5, C4,-C3,-C6, C1, C4,-C5,-C6, C1,-C4,-C7, C2,-C3, C4,-C5,-C6, C1,-C4,-C7, C2,-C3, C4,-C3, C6, C7,-C4, C1,-C2, C5, C4,-C3, C6, C7,-C4, C1,-C2, C5, C4,-C1, C2,-C3, C4,-C5, C6,-C7, C4,-C1, C2,-C3, C4,-C5, C6,-C7 //g20 }; #undef C0 #undef C1 #undef C2 #undef C3 #undef C4 #undef C5 #undef C6 #undef C7 const uint32_t zigzag_direct[64] = { 0, 1, 8, 16, 9, 2, 3, 10, 17, 24, 32, 25, 18, 11, 4, 5, 12, 19, 26, 33, 40, 48, 41, 34, 27, 20, 13, 6, 7, 14, 21, 28, 35, 42, 49, 56, 57, 50, 43, 36, 29, 22, 15, 23, 30, 37, 44, 51, 58, 59, 52, 45, 38, 31, 39, 46, 53, 60, 61, 54, 47, 55, 62, 63 }; static const uint32_t frame_intra_kernel[][4] = { #include "shaders/mpeg2/vld/frame_intra.g4b" }; static const uint32_t frame_frame_pred_forward_kernel[][4] = { #include "shaders/mpeg2/vld/frame_frame_pred_forward.g4b" }; static const uint32_t frame_frame_pred_backward_kernel[][4] = { #include "shaders/mpeg2/vld/frame_frame_pred_backward.g4b" }; static const uint32_t frame_frame_pred_bidirect_kernel[][4] = { #include "shaders/mpeg2/vld/frame_frame_pred_bidirect.g4b" }; static const uint32_t frame_field_pred_forward_kernel[][4] = { #include "shaders/mpeg2/vld/frame_field_pred_forward.g4b" }; static const uint32_t frame_field_pred_backward_kernel[][4] = { #include "shaders/mpeg2/vld/frame_field_pred_backward.g4b" }; static const uint32_t frame_field_pred_bidirect_kernel[][4] = { #include "shaders/mpeg2/vld/frame_field_pred_bidirect.g4b" }; static const uint32_t lib_kernel[][4] = { #include "shaders/mpeg2/vld/lib.g4b" }; /*field picture*/ static const uint32_t field_intra_kernel[][4] = { #include "shaders/mpeg2/vld/field_intra.g4b" }; static const uint32_t field_forward_kernel[][4] = { #include "shaders/mpeg2/vld/field_forward.g4b" }; static const uint32_t field_forward_16x8_kernel[][4] = { #include "shaders/mpeg2/vld/field_forward_16x8.g4b" }; static const uint32_t field_backward_kernel[][4] = { #include "shaders/mpeg2/vld/field_backward.g4b" }; static const uint32_t field_backward_16x8_kernel[][4] = { #include "shaders/mpeg2/vld/field_backward_16x8.g4b" }; static const uint32_t field_bidirect_kernel[][4] = { #include "shaders/mpeg2/vld/field_bidirect.g4b" }; static const uint32_t field_bidirect_16x8_kernel[][4] = { #include "shaders/mpeg2/vld/field_bidirect_16x8.g4b" }; static struct i965_kernel mpeg2_vld_kernels_gen4[] = { { "FRAME_INTRA", FRAME_INTRA, frame_intra_kernel, sizeof(frame_intra_kernel), NULL }, { "FRAME_FRAME_PRED_FORWARD", FRAME_FRAME_PRED_FORWARD, frame_frame_pred_forward_kernel, sizeof(frame_frame_pred_forward_kernel), NULL }, { "FRAME_FRAME_PRED_BACKWARD", FRAME_FRAME_PRED_BACKWARD, frame_frame_pred_backward_kernel, sizeof(frame_frame_pred_backward_kernel), NULL }, { "FRAME_FRAME_PRED_BIDIRECT", FRAME_FRAME_PRED_BIDIRECT, frame_frame_pred_bidirect_kernel, sizeof(frame_frame_pred_bidirect_kernel), NULL }, { "FRAME_FIELD_PRED_FORWARD", FRAME_FIELD_PRED_FORWARD, frame_field_pred_forward_kernel, sizeof(frame_field_pred_forward_kernel), NULL }, { "FRAME_FIELD_PRED_BACKWARD", FRAME_FIELD_PRED_BACKWARD, frame_field_pred_backward_kernel, sizeof(frame_field_pred_backward_kernel), NULL }, { "FRAME_FIELD_PRED_BIDIRECT", FRAME_FIELD_PRED_BIDIRECT, frame_field_pred_bidirect_kernel, sizeof(frame_field_pred_bidirect_kernel), NULL }, { "LIB", LIB_INTERFACE, lib_kernel, sizeof(lib_kernel), NULL }, { "FIELD_INTRA", FIELD_INTRA, field_intra_kernel, sizeof(field_intra_kernel), NULL }, { "FIELD_FORWARD", FIELD_FORWARD, field_forward_kernel, sizeof(field_forward_kernel), NULL }, { "FIELD_FORWARD_16X8", FIELD_FORWARD_16X8, field_forward_16x8_kernel, sizeof(field_forward_16x8_kernel), NULL }, { "FIELD_BACKWARD", FIELD_BACKWARD, field_backward_kernel, sizeof(field_backward_kernel), NULL }, { "FIELD_BACKWARD_16X8", FIELD_BACKWARD_16X8, field_backward_16x8_kernel, sizeof(field_backward_16x8_kernel), NULL }, { "FIELD_BIDIRECT", FIELD_BIDIRECT, field_bidirect_kernel, sizeof(field_bidirect_kernel), NULL }, { "FIELD_BIDIRECT_16X8", FIELD_BIDIRECT_16X8, field_bidirect_16x8_kernel, sizeof(field_bidirect_16x8_kernel), NULL } }; /* On IRONLAKE */ static const uint32_t frame_intra_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/frame_intra.g4b.gen5" }; static const uint32_t frame_frame_pred_forward_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/frame_frame_pred_forward.g4b.gen5" }; static const uint32_t frame_frame_pred_backward_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/frame_frame_pred_backward.g4b.gen5" }; static const uint32_t frame_frame_pred_bidirect_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/frame_frame_pred_bidirect.g4b.gen5" }; static const uint32_t frame_field_pred_forward_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/frame_field_pred_forward.g4b.gen5" }; static const uint32_t frame_field_pred_backward_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/frame_field_pred_backward.g4b.gen5" }; static const uint32_t frame_field_pred_bidirect_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/frame_field_pred_bidirect.g4b.gen5" }; static const uint32_t lib_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/lib.g4b.gen5" }; /*field picture*/ static const uint32_t field_intra_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/field_intra.g4b.gen5" }; static const uint32_t field_forward_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/field_forward.g4b.gen5" }; static const uint32_t field_forward_16x8_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/field_forward_16x8.g4b.gen5" }; static const uint32_t field_backward_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/field_backward.g4b.gen5" }; static const uint32_t field_backward_16x8_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/field_backward_16x8.g4b.gen5" }; static const uint32_t field_bidirect_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/field_bidirect.g4b.gen5" }; static const uint32_t field_bidirect_16x8_kernel_gen5[][4] = { #include "shaders/mpeg2/vld/field_bidirect_16x8.g4b.gen5" }; static struct i965_kernel mpeg2_vld_kernels_gen5[] = { { "FRAME_INTRA", FRAME_INTRA, frame_intra_kernel_gen5, sizeof(frame_intra_kernel_gen5), NULL }, { "FRAME_FRAME_PRED_FORWARD", FRAME_FRAME_PRED_FORWARD, frame_frame_pred_forward_kernel_gen5, sizeof(frame_frame_pred_forward_kernel_gen5), NULL }, { "FRAME_FRAME_PRED_BACKWARD", FRAME_FRAME_PRED_BACKWARD, frame_frame_pred_backward_kernel_gen5, sizeof(frame_frame_pred_backward_kernel_gen5), NULL }, { "FRAME_FRAME_PRED_BIDIRECT", FRAME_FRAME_PRED_BIDIRECT, frame_frame_pred_bidirect_kernel_gen5, sizeof(frame_frame_pred_bidirect_kernel_gen5), NULL }, { "FRAME_FIELD_PRED_FORWARD", FRAME_FIELD_PRED_FORWARD, frame_field_pred_forward_kernel_gen5, sizeof(frame_field_pred_forward_kernel_gen5), NULL }, { "FRAME_FIELD_PRED_BACKWARD", FRAME_FIELD_PRED_BACKWARD, frame_field_pred_backward_kernel_gen5, sizeof(frame_field_pred_backward_kernel_gen5), NULL }, { "FRAME_FIELD_PRED_BIDIRECT", FRAME_FIELD_PRED_BIDIRECT, frame_field_pred_bidirect_kernel_gen5, sizeof(frame_field_pred_bidirect_kernel_gen5), NULL }, { "LIB", LIB_INTERFACE, lib_kernel_gen5, sizeof(lib_kernel_gen5), NULL }, { "FIELD_INTRA", FIELD_INTRA, field_intra_kernel_gen5, sizeof(field_intra_kernel_gen5), NULL }, { "FIELD_FORWARD", FIELD_FORWARD, field_forward_kernel_gen5, sizeof(field_forward_kernel_gen5), NULL }, { "FIELD_FORWARD_16X8", FIELD_FORWARD_16X8, field_forward_16x8_kernel_gen5, sizeof(field_forward_16x8_kernel_gen5), NULL }, { "FIELD_BACKWARD", FIELD_BACKWARD, field_backward_kernel_gen5, sizeof(field_backward_kernel_gen5), NULL }, { "FIELD_BACKWARD_16X8", FIELD_BACKWARD_16X8, field_backward_16x8_kernel_gen5, sizeof(field_backward_16x8_kernel_gen5), NULL }, { "FIELD_BIDIRECT", FIELD_BIDIRECT, field_bidirect_kernel_gen5, sizeof(field_bidirect_kernel_gen5), NULL }, { "FIELD_BIDIRECT_16X8", FIELD_BIDIRECT_16X8, field_bidirect_16x8_kernel_gen5, sizeof(field_bidirect_16x8_kernel_gen5), NULL } }; static void i965_media_mpeg2_surface_state(VADriverContextP ctx, int index, struct object_surface *obj_surface, unsigned long offset, int w, int h, Bool is_dst, int vert_line_stride, int vert_line_stride_ofs, struct i965_media_context *media_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_surface_state *ss; dri_bo *bo; uint32_t write_domain, read_domain; bo = dri_bo_alloc(i965->intel.bufmgr, "surface state", sizeof(struct i965_surface_state), 32); assert(bo); dri_bo_map(bo, 1); assert(bo->virtual); ss = bo->virtual; memset(ss, 0, sizeof(*ss)); ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = I965_SURFACEFORMAT_R8_SINT; ss->ss0.vert_line_stride = vert_line_stride; ss->ss0.vert_line_stride_ofs = vert_line_stride_ofs; ss->ss1.base_addr = obj_surface->bo->offset + offset; ss->ss2.width = w - 1; ss->ss2.height = h - 1; ss->ss3.pitch = w - 1; if (is_dst) { write_domain = I915_GEM_DOMAIN_RENDER; read_domain = I915_GEM_DOMAIN_RENDER; } else { write_domain = 0; read_domain = I915_GEM_DOMAIN_SAMPLER; } dri_bo_emit_reloc(bo, read_domain, write_domain, offset, offsetof(struct i965_surface_state, ss1), obj_surface->bo); dri_bo_unmap(bo); assert(index < MAX_MEDIA_SURFACES); // assert(media_context->surface_state[index].bo == NULL); media_context->surface_state[index].bo = bo; } static void i965_media_mpeg2_surface_setup(VADriverContextP ctx, int base_index, struct object_surface *obj_surface, Bool is_dst, int picture_structure, int surface, struct i965_media_context *media_context) { int w = obj_surface->width; int h = obj_surface->height; i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('I','4','2','0'), SUBSAMPLE_YUV420); if (picture_structure == MPEG_FRAME) { i965_media_mpeg2_surface_state(ctx, base_index + 0, obj_surface, 0, w, h, is_dst, 0, 0, media_context); i965_media_mpeg2_surface_state(ctx, base_index + 1, obj_surface, w * h, w / 2, h / 2, is_dst, 0, 0, media_context); i965_media_mpeg2_surface_state(ctx, base_index + 2, obj_surface, w * h + w * h / 4, w / 2, h / 2, is_dst, 0, 0, media_context); } else { if (surface == SURFACE_TARGET) { i965_media_mpeg2_surface_state(ctx, 3, obj_surface, 0, w, h, False, 0, 0, media_context); i965_media_mpeg2_surface_state(ctx, 10, obj_surface, w * h, w / 2, h / 2, False, 0, 0, media_context); i965_media_mpeg2_surface_state(ctx, 11, obj_surface, w * h + w * h / 4, w / 2, h / 2, False, 0, 0, media_context); if (picture_structure == MPEG_TOP_FIELD) { i965_media_mpeg2_surface_state(ctx, base_index + 0, obj_surface, 0, w, h, True, 1, 0, media_context); i965_media_mpeg2_surface_state(ctx, base_index + 1, obj_surface, w * h, w / 2, h / 2, True, 1, 0, media_context); i965_media_mpeg2_surface_state(ctx, base_index + 2, obj_surface, w * h + w * h / 4, w / 2, h / 2, True, 1, 0, media_context); } else { assert(picture_structure == MPEG_BOTTOM_FIELD); i965_media_mpeg2_surface_state(ctx, base_index + 0, obj_surface, 0, w, h, True, 1, 1, media_context); i965_media_mpeg2_surface_state(ctx, base_index + 1, obj_surface, w * h, w / 2, h / 2, True, 1, 1, media_context); i965_media_mpeg2_surface_state(ctx, base_index + 2, obj_surface, w * h + w * h / 4, w / 2, h / 2, True, 1, 1, media_context); } } else { i965_media_mpeg2_surface_state(ctx, base_index + 0, obj_surface, 0, w, h, is_dst, 0, 0, media_context); i965_media_mpeg2_surface_state(ctx, base_index + 1, obj_surface, w * h, w / 2, h / 2, is_dst, 0, 0, media_context); i965_media_mpeg2_surface_state(ctx, base_index + 2, obj_surface, w * h + w * h / 4, w / 2, h / 2, is_dst, 0, 0, media_context); } } } void i965_media_mpeg2_surfaces_setup(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct object_surface *obj_surface; VAPictureParameterBufferMPEG2 *param; assert(decode_state->pic_param && decode_state->pic_param->buffer); param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; obj_surface = decode_state->render_object; i965_media_mpeg2_surface_setup(ctx, 0, obj_surface, True, param->picture_coding_extension.bits.picture_structure, SURFACE_TARGET, media_context); obj_surface = decode_state->reference_objects[0]; if (!obj_surface) { // assert(param->picture_coding_type == 1); /* I-picture */ } else { i965_media_mpeg2_surface_setup(ctx, 4, obj_surface, False, param->picture_coding_extension.bits.picture_structure, SURFACE_FORWARD, media_context); obj_surface = decode_state->reference_objects[1]; if (!obj_surface) { assert(param->picture_coding_type == 2); /* P-picture */ obj_surface = decode_state->reference_objects[0]; i965_media_mpeg2_surface_setup(ctx, 7, obj_surface, False, param->picture_coding_extension.bits.picture_structure, SURFACE_BACKWARD, media_context); } else { assert(param->picture_coding_type == 3); /* B-picture */ i965_media_mpeg2_surface_setup(ctx, 7, obj_surface, False, param->picture_coding_extension.bits.picture_structure, SURFACE_BIDIRECT, media_context); } } } static void i965_media_mpeg2_binding_table(VADriverContextP ctx, struct i965_media_context *media_context) { int i; unsigned int *binding_table; dri_bo *bo = media_context->binding_table.bo; dri_bo_map(bo, 1); assert(bo->virtual); binding_table = bo->virtual; memset(binding_table, 0, bo->size); for (i = 0; i < MAX_MEDIA_SURFACES; i++) { if (media_context->surface_state[i].bo) { binding_table[i] = media_context->surface_state[i].bo->offset; dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, i * sizeof(*binding_table), media_context->surface_state[i].bo); } } dri_bo_unmap(media_context->binding_table.bo); } static void i965_media_mpeg2_vfe_state(VADriverContextP ctx, struct i965_media_context *media_context) { struct i965_vfe_state *vfe_state; dri_bo *bo; bo = media_context->vfe_state.bo; dri_bo_map(bo, 1); assert(bo->virtual); vfe_state = bo->virtual; memset(vfe_state, 0, sizeof(*vfe_state)); vfe_state->vfe0.extend_vfe_state_present = 1; vfe_state->vfe1.vfe_mode = VFE_VLD_MODE; vfe_state->vfe1.num_urb_entries = media_context->urb.num_vfe_entries; vfe_state->vfe1.children_present = 0; vfe_state->vfe1.urb_entry_alloc_size = media_context->urb.size_vfe_entry - 1; vfe_state->vfe1.max_threads = media_context->urb.num_vfe_entries - 1; vfe_state->vfe2.interface_descriptor_base = media_context->idrt.bo->offset >> 4; /* reloc */ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, offsetof(struct i965_vfe_state, vfe2), media_context->idrt.bo); dri_bo_unmap(bo); } static void i965_media_mpeg2_interface_descriptor_remap_table(VADriverContextP ctx, struct i965_media_context *media_context) { struct i965_mpeg2_context *i965_mpeg2_context = (struct i965_mpeg2_context *)media_context->private_context; struct i965_interface_descriptor *desc; int i; dri_bo *bo; bo = media_context->idrt.bo; dri_bo_map(bo, 1); assert(bo->virtual); desc = bo->virtual; for (i = 0; i < NUM_MPEG2_VLD_KERNELS; i++) { memset(desc, 0, sizeof(*desc)); desc->desc0.grf_reg_blocks = 15; desc->desc0.kernel_start_pointer = i965_mpeg2_context->vld_kernels[i].bo->offset >> 6; /* reloc */ desc->desc1.const_urb_entry_read_offset = 0; desc->desc1.const_urb_entry_read_len = 30; desc->desc3.binding_table_entry_count = 0; desc->desc3.binding_table_pointer = media_context->binding_table.bo->offset >> 5; /*reloc */ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, desc->desc0.grf_reg_blocks, i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0), i965_mpeg2_context->vld_kernels[i].bo); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, desc->desc3.binding_table_entry_count, i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc3), media_context->binding_table.bo); desc++; } dri_bo_unmap(bo); } void i965_media_mpeg2_vld_state(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct i965_vld_state *vld_state; VAPictureParameterBufferMPEG2 *param; assert(decode_state->pic_param && decode_state->pic_param->buffer); param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; assert(media_context->extended_state.bo); dri_bo_map(media_context->extended_state.bo, 1); assert(media_context->extended_state.bo->virtual); vld_state = media_context->extended_state.bo->virtual; memset(vld_state, 0, sizeof(*vld_state)); vld_state->vld0.f_code_0_0 = ((param->f_code >> 12) & 0xf); vld_state->vld0.f_code_0_1 = ((param->f_code >> 8) & 0xf); vld_state->vld0.f_code_1_0 = ((param->f_code >> 4) & 0xf); vld_state->vld0.f_code_1_1 = (param->f_code & 0xf); vld_state->vld0.intra_dc_precision = param->picture_coding_extension.bits.intra_dc_precision; vld_state->vld0.picture_structure = param->picture_coding_extension.bits.picture_structure; vld_state->vld0.top_field_first = param->picture_coding_extension.bits.top_field_first; vld_state->vld0.frame_predict_frame_dct = param->picture_coding_extension.bits.frame_pred_frame_dct; vld_state->vld0.concealment_motion_vector = param->picture_coding_extension.bits.concealment_motion_vectors; vld_state->vld0.quantizer_scale_type = param->picture_coding_extension.bits.q_scale_type; vld_state->vld0.intra_vlc_format = param->picture_coding_extension.bits.intra_vlc_format; vld_state->vld0.scan_order = param->picture_coding_extension.bits.alternate_scan; vld_state->vld1.picture_coding_type = param->picture_coding_type; if (vld_state->vld0.picture_structure == MPEG_FRAME) { /*frame picture*/ vld_state->desc_remap_table0.index_0 = FRAME_INTRA; vld_state->desc_remap_table0.index_1 = FRAME_FRAME_PRED_FORWARD; vld_state->desc_remap_table0.index_2 = FRAME_FIELD_PRED_FORWARD; vld_state->desc_remap_table0.index_3 = FRAME_FIELD_PRED_BIDIRECT; /* dual prime */ vld_state->desc_remap_table0.index_4 = FRAME_FRAME_PRED_BACKWARD; vld_state->desc_remap_table0.index_5 = FRAME_FIELD_PRED_BACKWARD; vld_state->desc_remap_table0.index_6 = FRAME_FRAME_PRED_BIDIRECT; vld_state->desc_remap_table0.index_7 = FRAME_FIELD_PRED_BIDIRECT; vld_state->desc_remap_table1.index_8 = FRAME_INTRA; vld_state->desc_remap_table1.index_9 = FRAME_FRAME_PRED_FORWARD; vld_state->desc_remap_table1.index_10 = FRAME_FIELD_PRED_FORWARD; vld_state->desc_remap_table1.index_11 = FRAME_FIELD_PRED_BIDIRECT; vld_state->desc_remap_table1.index_12 = FRAME_FRAME_PRED_BACKWARD; vld_state->desc_remap_table1.index_13 = FRAME_FIELD_PRED_BACKWARD; vld_state->desc_remap_table1.index_14 = FRAME_FRAME_PRED_BIDIRECT; vld_state->desc_remap_table1.index_15 = FRAME_FIELD_PRED_BIDIRECT; } else { /*field picture*/ vld_state->desc_remap_table0.index_0 = FIELD_INTRA; vld_state->desc_remap_table0.index_1 = FIELD_FORWARD; vld_state->desc_remap_table0.index_2 = FIELD_FORWARD_16X8; vld_state->desc_remap_table0.index_3 = FIELD_BIDIRECT; /* dual prime */ vld_state->desc_remap_table0.index_4 = FIELD_BACKWARD; vld_state->desc_remap_table0.index_5 = FIELD_BACKWARD_16X8; vld_state->desc_remap_table0.index_6 = FIELD_BIDIRECT; vld_state->desc_remap_table0.index_7 = FIELD_BIDIRECT_16X8; } dri_bo_unmap(media_context->extended_state.bo); } static void i965_media_mpeg2_upload_constants(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct i965_mpeg2_context *i965_mpeg2_context = (struct i965_mpeg2_context *)media_context->private_context; VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &i965_mpeg2_context->iq_matrix; int i; unsigned char *constant_buffer; unsigned int *lib_reloc; int lib_reloc_offset = 0; dri_bo_map(media_context->curbe.bo, 1); assert(media_context->curbe.bo->virtual); constant_buffer = media_context->curbe.bo->virtual; /* iq_matrix */ if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) { VAIQMatrixBufferMPEG2 * const iq_matrix = (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer; gen_iq_matrix->load_intra_quantiser_matrix = iq_matrix->load_intra_quantiser_matrix; if (iq_matrix->load_intra_quantiser_matrix) { for (i = 0; i < 64; i++) gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[i]] = iq_matrix->intra_quantiser_matrix[i]; } gen_iq_matrix->load_non_intra_quantiser_matrix = iq_matrix->load_non_intra_quantiser_matrix; if (iq_matrix->load_non_intra_quantiser_matrix) { for (i = 0; i < 64; i++) gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[i]] = iq_matrix->non_intra_quantiser_matrix[i]; } /* no chroma quantisation matrices for 4:2:0 data */ } if (gen_iq_matrix->load_intra_quantiser_matrix) { unsigned char * const qm = constant_buffer; memcpy(qm, gen_iq_matrix->intra_quantiser_matrix, 64); } if (gen_iq_matrix->load_non_intra_quantiser_matrix) { unsigned char * const qm = constant_buffer + 64; memcpy(qm, gen_iq_matrix->non_intra_quantiser_matrix, 64); } /* idct table */ memcpy(constant_buffer + 128, idct_table, sizeof(idct_table)); /* idct lib reloc */ lib_reloc_offset = 128 + sizeof(idct_table); lib_reloc = (unsigned int *)(constant_buffer + lib_reloc_offset); for (i = 0; i < 8; i++) { lib_reloc[i] = i965_mpeg2_context->vld_kernels[LIB_INTERFACE].bo->offset; dri_bo_emit_reloc(media_context->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, lib_reloc_offset + i * sizeof(unsigned int), i965_mpeg2_context->vld_kernels[LIB_INTERFACE].bo); } dri_bo_unmap(media_context->curbe.bo); } static void i965_media_mpeg2_states_setup(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { i965_media_mpeg2_surfaces_setup(ctx, decode_state, media_context); i965_media_mpeg2_binding_table(ctx, media_context); i965_media_mpeg2_interface_descriptor_remap_table(ctx, media_context); i965_media_mpeg2_vld_state(ctx, decode_state, media_context); i965_media_mpeg2_vfe_state(ctx, media_context); i965_media_mpeg2_upload_constants(ctx, decode_state, media_context); } static void i965_media_mpeg2_objects(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct i965_mpeg2_context * const i965_mpeg2_context = media_context->private_context; struct intel_batchbuffer *batch = media_context->base.batch; VASliceParameterBufferMPEG2 *slice_param; VAPictureParameterBufferMPEG2 *pic_param; int i, j; assert(decode_state->pic_param && decode_state->pic_param->buffer); pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer; if (i965_mpeg2_context->wa_slice_vertical_position < 0) i965_mpeg2_context->wa_slice_vertical_position = mpeg2_wa_slice_vertical_position(decode_state, pic_param); for (j = 0; j < decode_state->num_slice_params; j++) { assert(decode_state->slice_params[j] && decode_state->slice_params[j]->buffer); assert(decode_state->slice_datas[j] && decode_state->slice_datas[j]->bo); slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer; for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) { int vpos, hpos, is_field_pic = 0; if (i965_mpeg2_context->wa_slice_vertical_position > 0 && (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD || pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)) is_field_pic = 1; assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL); vpos = slice_param->slice_vertical_position / (1 + is_field_pic); hpos = slice_param->slice_horizontal_position; BEGIN_BATCH(batch, 6); OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4); OUT_BATCH(batch, 0); OUT_BATCH(batch, slice_param->slice_data_size - (slice_param->macroblock_offset >> 3)); OUT_RELOC(batch, decode_state->slice_datas[j]->bo, I915_GEM_DOMAIN_SAMPLER, 0, slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3)); OUT_BATCH(batch, ((hpos << 24) | (vpos << 16) | (127 << 8) | (slice_param->macroblock_offset & 0x7))); OUT_BATCH(batch, slice_param->quantiser_scale_code << 24); ADVANCE_BATCH(batch); slice_param++; } } } static void i965_media_mpeg2_free_private_context(void **data) { struct i965_mpeg2_context *i965_mpeg2_context = *data; int i; if (i965_mpeg2_context == NULL) return; for (i = 0; i < NUM_MPEG2_VLD_KERNELS; i++) { struct i965_kernel *kernel = &i965_mpeg2_context->vld_kernels[i]; dri_bo_unreference(kernel->bo); kernel->bo = NULL; } free(i965_mpeg2_context); *data = NULL; } void i965_media_mpeg2_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); dri_bo *bo; dri_bo_unreference(media_context->indirect_object.bo); media_context->indirect_object.bo = NULL; media_context->extended_state.enabled = 1; dri_bo_unreference(media_context->extended_state.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vld state", sizeof(struct i965_vld_state), 32); assert(bo); media_context->extended_state.bo = bo; } void i965_media_mpeg2_dec_context_init(VADriverContextP ctx, struct i965_media_context *media_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_mpeg2_context *i965_mpeg2_context; int i; i965_mpeg2_context = calloc(1, sizeof(struct i965_mpeg2_context)); i965_mpeg2_context->wa_slice_vertical_position = -1; /* kernel */ assert(NUM_MPEG2_VLD_KERNELS == (sizeof(mpeg2_vld_kernels_gen4) / sizeof(mpeg2_vld_kernels_gen4[0]))); assert(NUM_MPEG2_VLD_KERNELS == (sizeof(mpeg2_vld_kernels_gen5) / sizeof(mpeg2_vld_kernels_gen5[0]))); assert(NUM_MPEG2_VLD_KERNELS <= MAX_INTERFACE_DESC); if (IS_IRONLAKE(i965->intel.device_id)) memcpy(i965_mpeg2_context->vld_kernels, mpeg2_vld_kernels_gen5, sizeof(i965_mpeg2_context->vld_kernels)); else memcpy(i965_mpeg2_context->vld_kernels, mpeg2_vld_kernels_gen4, sizeof(i965_mpeg2_context->vld_kernels)); for (i = 0; i < NUM_MPEG2_VLD_KERNELS; i++) { struct i965_kernel *kernel = &i965_mpeg2_context->vld_kernels[i]; kernel->bo = dri_bo_alloc(i965->intel.bufmgr, kernel->name, kernel->size, 64); assert(kernel->bo); dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin); } /* URB */ media_context->urb.num_vfe_entries = 28; media_context->urb.size_vfe_entry = 13; media_context->urb.num_cs_entries = 1; media_context->urb.size_cs_entry = 16; media_context->urb.vfe_start = 0; media_context->urb.cs_start = media_context->urb.vfe_start + media_context->urb.num_vfe_entries * media_context->urb.size_vfe_entry; assert(media_context->urb.cs_start + media_context->urb.num_cs_entries * media_context->urb.size_cs_entry <= URB_SIZE((&i965->intel))); /* hook functions */ media_context->media_states_setup = i965_media_mpeg2_states_setup; media_context->media_objects = i965_media_mpeg2_objects; media_context->private_context = i965_mpeg2_context; media_context->free_private_context = i965_media_mpeg2_free_private_context; } intel-driver-1.3.0/src/i965_media_mpeg2.h000066400000000000000000000036321231401140700200010ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * Zou Nan hai * */ #ifndef _I965_MEDIA_MPEG2_H_ #define _I965_MEDIA_MPEG2_H_ #include #include #include #include struct decode_state; struct i965_media_context; #define NUM_MPEG2_VLD_KERNELS 15 struct i965_mpeg2_context { struct i965_kernel vld_kernels[NUM_MPEG2_VLD_KERNELS]; VAIQMatrixBufferMPEG2 iq_matrix; int wa_slice_vertical_position; }; void i965_media_mpeg2_decode_init(VADriverContextP ctx, struct decode_state * decode_state, struct i965_media_context *media_context); void i965_media_mpeg2_dec_context_init(VADriverContextP ctx, struct i965_media_context *media_context); #endif /* _I965_MEDIA_MPEG2_H_ */ intel-driver-1.3.0/src/i965_mutext.h000066400000000000000000000021211231401140700171460ustar00rootroot00000000000000#ifndef _I965_MUTEX_H_ #define _I965_MUTEX_H_ #include "intel_compiler.h" #if defined PTHREADS #include typedef pthread_mutex_t _I965Mutex; static INLINE void _i965InitMutex(_I965Mutex *m) { pthread_mutex_init(m, NULL); } static INLINE void _i965DestroyMutex(_I965Mutex *m) { pthread_mutex_destroy(m); } static INLINE void _i965LockMutex(_I965Mutex *m) { pthread_mutex_lock(m); } static INLINE void _i965UnlockMutex(_I965Mutex *m) { pthread_mutex_unlock(m); } #define _I965_MUTEX_INITIALIZER PTHREAD_MUTEX_INITIALIZER #define _I965_DECLARE_MUTEX(m) \ _I965Mutex m = _I965_MUTEX_INITIALIZER #else typedef int _I965Mutex; static INLINE void _i965InitMutex(_I965Mutex *m) { (void) m; } static INLINE void _i965DestroyMutex(_I965Mutex *m) { (void) m; } static INLINE void _i965LockMutex(_I965Mutex *m) { (void) m; } static INLINE void _i965UnlockMutex(_I965Mutex *m) { (void) m; } #define _I965_MUTEX_INITIALIZER 0 #define _I965_DECLARE_MUTEX(m) \ _I965Mutex m = _I965_MUTEX_INITIALIZER #endif #endif /* _I965_MUTEX_H_ */ intel-driver-1.3.0/src/i965_output_dri.c000066400000000000000000000157201231401140700200220ustar00rootroot00000000000000/* * Copyright (C) 2012 Intel Corporation. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "sysdeps.h" #include #include "i965_drv_video.h" #include "i965_output_dri.h" #include "dso_utils.h" #define LIBVA_X11_NAME "libva-x11.so.1" typedef struct dri_drawable *(*dri_get_drawable_func)( VADriverContextP ctx, XID drawable); typedef union dri_buffer *(*dri_get_rendering_buffer_func)( VADriverContextP ctx, struct dri_drawable *d); typedef void (*dri_swap_buffer_func)( VADriverContextP ctx, struct dri_drawable *d); struct dri_vtable { dri_get_drawable_func get_drawable; dri_get_rendering_buffer_func get_rendering_buffer; dri_swap_buffer_func swap_buffer; }; struct va_dri_output { struct dso_handle *handle; struct dri_vtable vtable; }; bool i965_output_dri_init(VADriverContextP ctx) { struct i965_driver_data * const i965 = i965_driver_data(ctx); struct dso_handle *dso_handle; struct dri_vtable *dri_vtable; static const struct dso_symbol symbols[] = { { "dri_get_drawable", offsetof(struct dri_vtable, get_drawable) }, { "dri_get_rendering_buffer", offsetof(struct dri_vtable, get_rendering_buffer) }, { "dri_swap_buffer", offsetof(struct dri_vtable, swap_buffer) }, { NULL, } }; i965->dri_output = calloc(1, sizeof(struct va_dri_output)); if (!i965->dri_output) goto error; i965->dri_output->handle = dso_open(LIBVA_X11_NAME); if (!i965->dri_output->handle) goto error; dso_handle = i965->dri_output->handle; dri_vtable = &i965->dri_output->vtable; if (!dso_get_symbols(dso_handle, dri_vtable, sizeof(*dri_vtable), symbols)) goto error; return true; error: i965_output_dri_terminate(ctx); return false; } void i965_output_dri_terminate(VADriverContextP ctx) { struct i965_driver_data * const i965 = i965_driver_data(ctx); struct va_dri_output * const dri_output = i965->dri_output; if (!dri_output) return; if (dri_output->handle) { dso_close(dri_output->handle); dri_output->handle = NULL; } free(dri_output); i965->dri_output = NULL; } VAStatus i965_put_surface_dri( VADriverContextP ctx, VASurfaceID surface, void *draw, const VARectangle *src_rect, const VARectangle *dst_rect, const VARectangle *cliprects, unsigned int num_cliprects, unsigned int flags ) { struct i965_driver_data * const i965 = i965_driver_data(ctx); struct dri_vtable * const dri_vtable = &i965->dri_output->vtable; struct i965_render_state * const render_state = &i965->render_state; struct dri_drawable *dri_drawable; union dri_buffer *buffer; struct intel_region *dest_region; struct object_surface *obj_surface; unsigned int pp_flag = 0; bool new_region = false; uint32_t name; int i, ret; unsigned int color_flag = 0; /* Currently don't support DRI1 */ if (!VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_DRI2)) return VA_STATUS_ERROR_UNKNOWN; /* Some broken sources such as H.264 conformance case FM2_SVA_C * will get here */ obj_surface = SURFACE(surface); if (!obj_surface || !obj_surface->bo) return VA_STATUS_SUCCESS; _i965LockMutex(&i965->render_mutex); dri_drawable = dri_vtable->get_drawable(ctx, (Drawable)draw); assert(dri_drawable); buffer = dri_vtable->get_rendering_buffer(ctx, dri_drawable); assert(buffer); dest_region = render_state->draw_region; if (dest_region) { assert(dest_region->bo); dri_bo_flink(dest_region->bo, &name); if (buffer->dri2.name != name) { new_region = True; dri_bo_unreference(dest_region->bo); } } else { dest_region = (struct intel_region *)calloc(1, sizeof(*dest_region)); assert(dest_region); render_state->draw_region = dest_region; new_region = True; } if (new_region) { dest_region->x = dri_drawable->x; dest_region->y = dri_drawable->y; dest_region->width = dri_drawable->width; dest_region->height = dri_drawable->height; dest_region->cpp = buffer->dri2.cpp; dest_region->pitch = buffer->dri2.pitch; dest_region->bo = intel_bo_gem_create_from_name(i965->intel.bufmgr, "rendering buffer", buffer->dri2.name); assert(dest_region->bo); ret = dri_bo_get_tiling(dest_region->bo, &(dest_region->tiling), &(dest_region->swizzle)); assert(ret == 0); } color_flag = flags & VA_SRC_COLOR_MASK; if (color_flag == 0) color_flag = VA_SRC_BT601; pp_flag = color_flag; if ((flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC) pp_flag |= I965_PP_FLAG_AVS; if (flags & VA_TOP_FIELD) pp_flag |= I965_PP_FLAG_TOP_FIELD; else if (flags & VA_BOTTOM_FIELD) pp_flag |= I965_PP_FLAG_BOTTOM_FIELD; intel_render_put_surface(ctx, obj_surface, src_rect, dst_rect, pp_flag); for (i = 0; i < I965_MAX_SUBPIC_SUM; i++) { if (obj_surface->obj_subpic[i] != NULL) { assert(obj_surface->subpic[i] != VA_INVALID_ID); obj_surface->subpic_render_idx = i; intel_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect); } } if (!getenv("INTEL_DEBUG_BENCH")) dri_vtable->swap_buffer(ctx, dri_drawable); obj_surface->flags |= SURFACE_DISPLAYED; if ((obj_surface->flags & SURFACE_ALL_MASK) == SURFACE_DISPLAYED) { dri_bo_unreference(obj_surface->bo); obj_surface->bo = NULL; obj_surface->flags &= ~SURFACE_REF_DIS_MASK; if (obj_surface->free_private_data) obj_surface->free_private_data(&obj_surface->private_data); } _i965UnlockMutex(&i965->render_mutex); return VA_STATUS_SUCCESS; } intel-driver-1.3.0/src/i965_output_dri.h000066400000000000000000000033011231401140700200170ustar00rootroot00000000000000/* * Copyright (C) 2012 Intel Corporation. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef I965_OUTPUT_DRI_H #define I965_OUTPUT_DRI_H #include #include bool i965_output_dri_init(VADriverContextP ctx); void i965_output_dri_terminate(VADriverContextP ctx); VAStatus i965_put_surface_dri( VADriverContextP ctx, VASurfaceID surface, void *draw, const VARectangle *src_rect, const VARectangle *dst_rect, const VARectangle *cliprects, unsigned int num_cliprects, unsigned int flags ); #endif /* I965_OUTPUT_DRI_H */ intel-driver-1.3.0/src/i965_output_wayland.c000066400000000000000000000314161231401140700207030ustar00rootroot00000000000000/* * Copyright (C) 2012 Intel Corporation. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include "intel_driver.h" #include "i965_output_wayland.h" #include "i965_drv_video.h" #include "i965_defines.h" #include "dso_utils.h" #define LIBEGL_NAME "libEGL.so.1" #define LIBWAYLAND_CLIENT_NAME "libwayland-client.so.0" typedef uint32_t (*wl_display_get_global_func)(struct wl_display *display, const char *interface, uint32_t version); typedef void (*wl_display_roundtrip_func)(struct wl_display *display); typedef struct wl_proxy *(*wl_proxy_create_func)(struct wl_proxy *factory, const struct wl_interface *interface); typedef void (*wl_proxy_destroy_func)(struct wl_proxy *proxy); typedef void (*wl_proxy_marshal_func)(struct wl_proxy *p, uint32_t opcode, ...); typedef int (*wl_proxy_add_listener_func) (struct wl_proxy *proxy, void (**implementation)(void), void *data); struct wl_vtable { const struct wl_interface *buffer_interface; const struct wl_interface *drm_interface; const struct wl_interface *registry_interface; wl_display_roundtrip_func display_roundtrip; wl_proxy_create_func proxy_create; wl_proxy_destroy_func proxy_destroy; wl_proxy_marshal_func proxy_marshal; wl_proxy_add_listener_func proxy_add_listener; }; struct va_wl_output { struct dso_handle *libegl_handle; struct dso_handle *libwl_client_handle; struct wl_vtable vtable; struct wl_drm *wl_drm; struct wl_registry *wl_registry; }; /* These function are copied and adapted from the version inside * wayland-client-protocol.h */ static void * registry_bind( struct wl_vtable *wl_vtable, struct wl_registry *wl_registry, uint32_t name, const struct wl_interface *interface, uint32_t version ) { struct wl_proxy *id; id = wl_vtable->proxy_create((struct wl_proxy *) wl_registry, interface); if (!id) return NULL; wl_vtable->proxy_marshal((struct wl_proxy *) wl_registry, WL_REGISTRY_BIND, name, interface->name, version, id); return (void *) id; } static struct wl_registry * display_get_registry( struct wl_vtable *wl_vtable, struct wl_display *wl_display ) { struct wl_proxy *callback; callback = wl_vtable->proxy_create((struct wl_proxy *) wl_display, wl_vtable->registry_interface); if (!callback) return NULL; wl_vtable->proxy_marshal((struct wl_proxy *) wl_display, WL_DISPLAY_GET_REGISTRY, callback); return (struct wl_registry *) callback; } static int registry_add_listener( struct wl_vtable *wl_vtable, struct wl_registry *wl_registry, const struct wl_registry_listener *listener, void *data ) { return wl_vtable->proxy_add_listener((struct wl_proxy *) wl_registry, (void (**)(void)) listener, data); } static void registry_handle_global( void *data, struct wl_registry *registry, uint32_t id, const char *interface, uint32_t version ) { VADriverContextP ctx = data; struct i965_driver_data * const i965 = i965_driver_data(ctx); struct va_wl_output * const wl_output = i965->wl_output; struct wl_vtable * const wl_vtable = &wl_output->vtable; if (strcmp(interface, "wl_drm") == 0) { wl_output->wl_drm = registry_bind(wl_vtable, wl_output->wl_registry, id, wl_vtable->drm_interface, 1); } } static const struct wl_registry_listener registry_listener = { registry_handle_global, NULL }; /* Ensure wl_drm instance is created */ static bool ensure_wl_output(VADriverContextP ctx) { struct i965_driver_data * const i965 = i965_driver_data(ctx); struct va_wl_output * const wl_output = i965->wl_output; struct wl_vtable * const wl_vtable = &wl_output->vtable; if (wl_output->wl_drm) return true; wl_output->wl_registry = display_get_registry(wl_vtable, ctx->native_dpy); registry_add_listener(wl_vtable, wl_output->wl_registry, ®istry_listener, ctx); wl_vtable->display_roundtrip(ctx->native_dpy); if (!wl_output->wl_drm) return false; return true; } /* Create planar YUV buffer */ static struct wl_buffer * create_planar_buffer( struct va_wl_output *wl_output, uint32_t name, int32_t width, int32_t height, uint32_t format, int32_t offsets[3], int32_t pitches[3] ) { struct wl_vtable * const wl_vtable = &wl_output->vtable; struct wl_proxy *id; id = wl_vtable->proxy_create( (struct wl_proxy *)wl_output->wl_drm, wl_vtable->buffer_interface ); if (!id) return NULL; wl_vtable->proxy_marshal( (struct wl_proxy *)wl_output->wl_drm, WL_DRM_CREATE_PLANAR_BUFFER, id, name, width, height, format, offsets[0], pitches[0], offsets[1], pitches[1], offsets[2], pitches[2] ); return (struct wl_buffer *)id; } /* Hook to return Wayland buffer associated with the VA surface */ static VAStatus va_GetSurfaceBufferWl( struct VADriverContext *ctx, VASurfaceID surface, unsigned int flags, struct wl_buffer **out_buffer ) { struct i965_driver_data * const i965 = i965_driver_data(ctx); struct object_surface *obj_surface; struct wl_buffer *buffer; uint32_t name, drm_format; int offsets[3], pitches[3]; obj_surface = SURFACE(surface); if (!obj_surface) return VA_STATUS_ERROR_INVALID_SURFACE; if (flags != VA_FRAME_PICTURE) return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED; if (!out_buffer) return VA_STATUS_ERROR_INVALID_PARAMETER; if (!ensure_wl_output(ctx)) return VA_STATUS_ERROR_INVALID_DISPLAY; if (drm_intel_bo_flink(obj_surface->bo, &name) != 0) return VA_STATUS_ERROR_INVALID_SURFACE; switch (obj_surface->fourcc) { case VA_FOURCC('N','V','1','2'): drm_format = WL_DRM_FORMAT_NV12; offsets[0] = 0; pitches[0] = obj_surface->width; offsets[1] = obj_surface->width * obj_surface->y_cb_offset; pitches[1] = obj_surface->cb_cr_pitch; offsets[2] = 0; pitches[2] = 0; break; case VA_FOURCC('Y','V','1','2'): case VA_FOURCC('I','4','2','0'): case VA_FOURCC('I','M','C','1'): case VA_FOURCC('I','M','C','3'): case VA_FOURCC('4','2','2','H'): case VA_FOURCC('4','2','2','V'): case VA_FOURCC('4','1','1','P'): case VA_FOURCC('4','4','4','P'): switch (obj_surface->subsampling) { case SUBSAMPLE_YUV411: drm_format = WL_DRM_FORMAT_YUV411; break; case SUBSAMPLE_YUV420: drm_format = WL_DRM_FORMAT_YUV420; break; case SUBSAMPLE_YUV422H: case SUBSAMPLE_YUV422V: drm_format = WL_DRM_FORMAT_YUV422; break; case SUBSAMPLE_YUV444: drm_format = WL_DRM_FORMAT_YUV444; break; default: assert(0 && "unsupported subsampling"); return VA_STATUS_ERROR_INVALID_IMAGE_FORMAT; } offsets[0] = 0; pitches[0] = obj_surface->width; offsets[1] = obj_surface->width * obj_surface->y_cb_offset; pitches[1] = obj_surface->cb_cr_pitch; offsets[2] = obj_surface->width * obj_surface->y_cr_offset; pitches[2] = obj_surface->cb_cr_pitch; break; default: assert(0 && "unsupported format"); return VA_STATUS_ERROR_INVALID_IMAGE_FORMAT; } buffer = create_planar_buffer( i965->wl_output, name, obj_surface->orig_width, obj_surface->orig_height, drm_format, offsets, pitches ); if (!buffer) return VA_STATUS_ERROR_ALLOCATION_FAILED; *out_buffer = buffer; return VA_STATUS_SUCCESS; } /* Hook to return Wayland buffer associated with the VA image */ static VAStatus va_GetImageBufferWl( struct VADriverContext *ctx, VAImageID image, unsigned int flags, struct wl_buffer **out_buffer ) { return VA_STATUS_ERROR_UNIMPLEMENTED; } bool ensure_driver_vtable(VADriverContextP ctx) { struct VADriverVTableWayland * const vtable = ctx->vtable_wayland; if (!vtable) return false; vtable->vaGetSurfaceBufferWl = va_GetSurfaceBufferWl; vtable->vaGetImageBufferWl = va_GetImageBufferWl; return true; } bool i965_output_wayland_init(VADriverContextP ctx) { struct i965_driver_data * const i965 = i965_driver_data(ctx); struct dso_handle *dso_handle; struct wl_vtable *wl_vtable; static const struct dso_symbol libegl_symbols[] = { { "wl_drm_interface", offsetof(struct wl_vtable, drm_interface) }, { NULL, } }; static const struct dso_symbol libwl_client_symbols[] = { { "wl_buffer_interface", offsetof(struct wl_vtable, buffer_interface) }, { "wl_registry_interface", offsetof(struct wl_vtable, registry_interface) }, { "wl_display_roundtrip", offsetof(struct wl_vtable, display_roundtrip) }, { "wl_proxy_create", offsetof(struct wl_vtable, proxy_create) }, { "wl_proxy_destroy", offsetof(struct wl_vtable, proxy_destroy) }, { "wl_proxy_marshal", offsetof(struct wl_vtable, proxy_marshal) }, { "wl_proxy_add_listener", offsetof(struct wl_vtable, proxy_add_listener) }, { NULL, } }; if (ctx->display_type != VA_DISPLAY_WAYLAND) return false; i965->wl_output = calloc(1, sizeof(struct va_wl_output)); if (!i965->wl_output) goto error; i965->wl_output->libegl_handle = dso_open(LIBEGL_NAME); if (!i965->wl_output->libegl_handle) goto error; dso_handle = i965->wl_output->libegl_handle; wl_vtable = &i965->wl_output->vtable; if (!dso_get_symbols(dso_handle, wl_vtable, sizeof(*wl_vtable), libegl_symbols)) goto error; i965->wl_output->libwl_client_handle = dso_open(LIBWAYLAND_CLIENT_NAME); if (!i965->wl_output->libwl_client_handle) goto error; dso_handle = i965->wl_output->libwl_client_handle; wl_vtable = &i965->wl_output->vtable; if (!dso_get_symbols(dso_handle, wl_vtable, sizeof(*wl_vtable), libwl_client_symbols)) goto error; if (!ensure_driver_vtable(ctx)) goto error; return true; error: i965_output_wayland_terminate(ctx); return false; } void i965_output_wayland_terminate(VADriverContextP ctx) { struct i965_driver_data * const i965 = i965_driver_data(ctx); struct va_wl_output *wl_output; if (ctx->display_type != VA_DISPLAY_WAYLAND) return; wl_output = i965->wl_output; if (!wl_output) return; if (wl_output->wl_drm) { wl_output->vtable.proxy_destroy((struct wl_proxy *)wl_output->wl_drm); wl_output->wl_drm = NULL; } if (wl_output->libegl_handle) { dso_close(wl_output->libegl_handle); wl_output->libegl_handle = NULL; } if (wl_output->libwl_client_handle) { dso_close(wl_output->libwl_client_handle); wl_output->libwl_client_handle = NULL; } free(wl_output); i965->wl_output = NULL; } intel-driver-1.3.0/src/i965_output_wayland.h000066400000000000000000000026171231401140700207110ustar00rootroot00000000000000/* * Copyright (C) 2012 Intel Corporation. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef I965_OUTPUT_WAYLAND_H #define I965_OUTPUT_WAYLAND_H #include bool i965_output_wayland_init(VADriverContextP ctx); void i965_output_wayland_terminate(VADriverContextP ctx); #endif /* I965_OUTPUT_WAYLAND_H */ intel-driver-1.3.0/src/i965_post_processing.c000077500000000000000000007613301231401140700210550ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_structs.h" #include "i965_drv_video.h" #include "i965_post_processing.h" #include "i965_render.h" #include "intel_media.h" #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) || \ IS_GEN6((ctx)->intel.device_id) || \ IS_GEN7((ctx)->intel.device_id) || \ IS_GEN8((ctx)->intel.device_id)) #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN8,\ MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)) #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) #define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_PP_SURFACES) #define GPU_ASM_BLOCK_WIDTH 16 #define GPU_ASM_BLOCK_HEIGHT 8 #define GPU_ASM_X_OFFSET_ALIGNMENT 4 #define VA_STATUS_SUCCESS_1 0xFFFFFFFE extern VAStatus i965_DestroySurfaces(VADriverContextP ctx, VASurfaceID *surface_list, int num_surfaces); extern VAStatus i965_CreateSurfaces(VADriverContextP ctx, int width, int height, int format, int num_surfaces, VASurfaceID *surfaces); static const uint32_t pp_null_gen5[][4] = { #include "shaders/post_processing/gen5_6/null.g4b.gen5" }; static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = { #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5" }; static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = { #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5" }; static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = { #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5" }; static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = { #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5" }; static const uint32_t pp_nv12_scaling_gen5[][4] = { #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5" }; static const uint32_t pp_nv12_avs_gen5[][4] = { #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5" }; static const uint32_t pp_nv12_dndi_gen5[][4] = { #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5" }; static const uint32_t pp_nv12_dn_gen5[][4] = { #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5" }; static const uint32_t pp_nv12_load_save_pa_gen5[][4] = { #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5" }; static const uint32_t pp_pl3_load_save_pa_gen5[][4] = { #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5" }; static const uint32_t pp_pa_load_save_nv12_gen5[][4] = { #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5" }; static const uint32_t pp_pa_load_save_pl3_gen5[][4] = { #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5" }; static const uint32_t pp_pa_load_save_pa_gen5[][4] = { #include "shaders/post_processing/gen5_6/pa_load_save_pa.g4b.gen5" }; static const uint32_t pp_rgbx_load_save_nv12_gen5[][4] = { #include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g4b.gen5" }; static const uint32_t pp_nv12_load_save_rgbx_gen5[][4] = { #include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g4b.gen5" }; static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); static struct pp_module pp_modules_gen5[] = { { { "NULL module (for testing)", PP_NULL, pp_null_gen5, sizeof(pp_null_gen5), NULL, }, pp_null_initialize, }, { { "NV12_NV12", PP_NV12_LOAD_SAVE_N12, pp_nv12_load_save_nv12_gen5, sizeof(pp_nv12_load_save_nv12_gen5), NULL, }, pp_plx_load_save_plx_initialize, }, { { "NV12_PL3", PP_NV12_LOAD_SAVE_PL3, pp_nv12_load_save_pl3_gen5, sizeof(pp_nv12_load_save_pl3_gen5), NULL, }, pp_plx_load_save_plx_initialize, }, { { "PL3_NV12", PP_PL3_LOAD_SAVE_N12, pp_pl3_load_save_nv12_gen5, sizeof(pp_pl3_load_save_nv12_gen5), NULL, }, pp_plx_load_save_plx_initialize, }, { { "PL3_PL3", PP_PL3_LOAD_SAVE_PL3, pp_pl3_load_save_pl3_gen5, sizeof(pp_pl3_load_save_pl3_gen5), NULL, }, pp_plx_load_save_plx_initialize }, { { "NV12 Scaling module", PP_NV12_SCALING, pp_nv12_scaling_gen5, sizeof(pp_nv12_scaling_gen5), NULL, }, pp_nv12_scaling_initialize, }, { { "NV12 AVS module", PP_NV12_AVS, pp_nv12_avs_gen5, sizeof(pp_nv12_avs_gen5), NULL, }, pp_nv12_avs_initialize_nlas, }, { { "NV12 DNDI module", PP_NV12_DNDI, pp_nv12_dndi_gen5, sizeof(pp_nv12_dndi_gen5), NULL, }, pp_nv12_dndi_initialize, }, { { "NV12 DN module", PP_NV12_DN, pp_nv12_dn_gen5, sizeof(pp_nv12_dn_gen5), NULL, }, pp_nv12_dn_initialize, }, { { "NV12_PA module", PP_NV12_LOAD_SAVE_PA, pp_nv12_load_save_pa_gen5, sizeof(pp_nv12_load_save_pa_gen5), NULL, }, pp_plx_load_save_plx_initialize, }, { { "PL3_PA module", PP_PL3_LOAD_SAVE_PA, pp_pl3_load_save_pa_gen5, sizeof(pp_pl3_load_save_pa_gen5), NULL, }, pp_plx_load_save_plx_initialize, }, { { "PA_NV12 module", PP_PA_LOAD_SAVE_NV12, pp_pa_load_save_nv12_gen5, sizeof(pp_pa_load_save_nv12_gen5), NULL, }, pp_plx_load_save_plx_initialize, }, { { "PA_PL3 module", PP_PA_LOAD_SAVE_PL3, pp_pa_load_save_pl3_gen5, sizeof(pp_pa_load_save_pl3_gen5), NULL, }, pp_plx_load_save_plx_initialize, }, { { "PA_PA module", PP_PA_LOAD_SAVE_PA, pp_pa_load_save_pa_gen5, sizeof(pp_pa_load_save_pa_gen5), NULL, }, pp_plx_load_save_plx_initialize, }, { { "RGBX_NV12 module", PP_RGBX_LOAD_SAVE_NV12, pp_rgbx_load_save_nv12_gen5, sizeof(pp_rgbx_load_save_nv12_gen5), NULL, }, pp_plx_load_save_plx_initialize, }, { { "NV12_RGBX module", PP_NV12_LOAD_SAVE_RGBX, pp_nv12_load_save_rgbx_gen5, sizeof(pp_nv12_load_save_rgbx_gen5), NULL, }, pp_plx_load_save_plx_initialize, }, }; static const uint32_t pp_null_gen6[][4] = { #include "shaders/post_processing/gen5_6/null.g6b" }; static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = { #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b" }; static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = { #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b" }; static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = { #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b" }; static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = { #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b" }; static const uint32_t pp_nv12_scaling_gen6[][4] = { #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b" }; static const uint32_t pp_nv12_avs_gen6[][4] = { #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b" }; static const uint32_t pp_nv12_dndi_gen6[][4] = { #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b" }; static const uint32_t pp_nv12_dn_gen6[][4] = { #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b" }; static const uint32_t pp_nv12_load_save_pa_gen6[][4] = { #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b" }; static const uint32_t pp_pl3_load_save_pa_gen6[][4] = { #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b" }; static const uint32_t pp_pa_load_save_nv12_gen6[][4] = { #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b" }; static const uint32_t pp_pa_load_save_pl3_gen6[][4] = { #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b" }; static const uint32_t pp_pa_load_save_pa_gen6[][4] = { #include "shaders/post_processing/gen5_6/pa_load_save_pa.g6b" }; static const uint32_t pp_rgbx_load_save_nv12_gen6[][4] = { #include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g6b" }; static const uint32_t pp_nv12_load_save_rgbx_gen6[][4] = { #include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g6b" }; static struct pp_module pp_modules_gen6[] = { { { "NULL module (for testing)", PP_NULL, pp_null_gen6, sizeof(pp_null_gen6), NULL, }, pp_null_initialize, }, { { "NV12_NV12", PP_NV12_LOAD_SAVE_N12, pp_nv12_load_save_nv12_gen6, sizeof(pp_nv12_load_save_nv12_gen6), NULL, }, pp_plx_load_save_plx_initialize, }, { { "NV12_PL3", PP_NV12_LOAD_SAVE_PL3, pp_nv12_load_save_pl3_gen6, sizeof(pp_nv12_load_save_pl3_gen6), NULL, }, pp_plx_load_save_plx_initialize, }, { { "PL3_NV12", PP_PL3_LOAD_SAVE_N12, pp_pl3_load_save_nv12_gen6, sizeof(pp_pl3_load_save_nv12_gen6), NULL, }, pp_plx_load_save_plx_initialize, }, { { "PL3_PL3", PP_PL3_LOAD_SAVE_PL3, pp_pl3_load_save_pl3_gen6, sizeof(pp_pl3_load_save_pl3_gen6), NULL, }, pp_plx_load_save_plx_initialize, }, { { "NV12 Scaling module", PP_NV12_SCALING, pp_nv12_scaling_gen6, sizeof(pp_nv12_scaling_gen6), NULL, }, gen6_nv12_scaling_initialize, }, { { "NV12 AVS module", PP_NV12_AVS, pp_nv12_avs_gen6, sizeof(pp_nv12_avs_gen6), NULL, }, pp_nv12_avs_initialize_nlas, }, { { "NV12 DNDI module", PP_NV12_DNDI, pp_nv12_dndi_gen6, sizeof(pp_nv12_dndi_gen6), NULL, }, pp_nv12_dndi_initialize, }, { { "NV12 DN module", PP_NV12_DN, pp_nv12_dn_gen6, sizeof(pp_nv12_dn_gen6), NULL, }, pp_nv12_dn_initialize, }, { { "NV12_PA module", PP_NV12_LOAD_SAVE_PA, pp_nv12_load_save_pa_gen6, sizeof(pp_nv12_load_save_pa_gen6), NULL, }, pp_plx_load_save_plx_initialize, }, { { "PL3_PA module", PP_PL3_LOAD_SAVE_PA, pp_pl3_load_save_pa_gen6, sizeof(pp_pl3_load_save_pa_gen6), NULL, }, pp_plx_load_save_plx_initialize, }, { { "PA_NV12 module", PP_PA_LOAD_SAVE_NV12, pp_pa_load_save_nv12_gen6, sizeof(pp_pa_load_save_nv12_gen6), NULL, }, pp_plx_load_save_plx_initialize, }, { { "PA_PL3 module", PP_PA_LOAD_SAVE_PL3, pp_pa_load_save_pl3_gen6, sizeof(pp_pa_load_save_pl3_gen6), NULL, }, pp_plx_load_save_plx_initialize, }, { { "PA_PA module", PP_PA_LOAD_SAVE_PA, pp_pa_load_save_pa_gen6, sizeof(pp_pa_load_save_pa_gen6), NULL, }, pp_plx_load_save_plx_initialize, }, { { "RGBX_NV12 module", PP_RGBX_LOAD_SAVE_NV12, pp_rgbx_load_save_nv12_gen6, sizeof(pp_rgbx_load_save_nv12_gen6), NULL, }, pp_plx_load_save_plx_initialize, }, { { "NV12_RGBX module", PP_NV12_LOAD_SAVE_RGBX, pp_nv12_load_save_rgbx_gen6, sizeof(pp_nv12_load_save_rgbx_gen6), NULL, }, pp_plx_load_save_plx_initialize, }, }; static const uint32_t pp_null_gen7[][4] = { }; static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = { #include "shaders/post_processing/gen7/pl2_to_pl2.g7b" }; static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = { #include "shaders/post_processing/gen7/pl2_to_pl3.g7b" }; static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = { #include "shaders/post_processing/gen7/pl3_to_pl2.g7b" }; static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = { #include "shaders/post_processing/gen7/pl3_to_pl3.g7b" }; static const uint32_t pp_nv12_scaling_gen7[][4] = { #include "shaders/post_processing/gen7/avs.g7b" }; static const uint32_t pp_nv12_avs_gen7[][4] = { #include "shaders/post_processing/gen7/avs.g7b" }; static const uint32_t pp_nv12_dndi_gen7[][4] = { #include "shaders/post_processing/gen7/dndi.g7b" }; static const uint32_t pp_nv12_dn_gen7[][4] = { #include "shaders/post_processing/gen7/nv12_dn_nv12.g7b" }; static const uint32_t pp_nv12_load_save_pa_gen7[][4] = { #include "shaders/post_processing/gen7/pl2_to_pa.g7b" }; static const uint32_t pp_pl3_load_save_pa_gen7[][4] = { #include "shaders/post_processing/gen7/pl3_to_pa.g7b" }; static const uint32_t pp_pa_load_save_nv12_gen7[][4] = { #include "shaders/post_processing/gen7/pa_to_pl2.g7b" }; static const uint32_t pp_pa_load_save_pl3_gen7[][4] = { #include "shaders/post_processing/gen7/pa_to_pl3.g7b" }; static const uint32_t pp_pa_load_save_pa_gen7[][4] = { #include "shaders/post_processing/gen7/pa_to_pa.g7b" }; static const uint32_t pp_rgbx_load_save_nv12_gen7[][4] = { #include "shaders/post_processing/gen7/rgbx_to_nv12.g7b" }; static const uint32_t pp_nv12_load_save_rgbx_gen7[][4] = { #include "shaders/post_processing/gen7/pl2_to_rgbx.g7b" }; static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); static VAStatus gen8_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); static struct pp_module pp_modules_gen7[] = { { { "NULL module (for testing)", PP_NULL, pp_null_gen7, sizeof(pp_null_gen7), NULL, }, pp_null_initialize, }, { { "NV12_NV12", PP_NV12_LOAD_SAVE_N12, pp_nv12_load_save_nv12_gen7, sizeof(pp_nv12_load_save_nv12_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, { { "NV12_PL3", PP_NV12_LOAD_SAVE_PL3, pp_nv12_load_save_pl3_gen7, sizeof(pp_nv12_load_save_pl3_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, { { "PL3_NV12", PP_PL3_LOAD_SAVE_N12, pp_pl3_load_save_nv12_gen7, sizeof(pp_pl3_load_save_nv12_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, { { "PL3_PL3", PP_PL3_LOAD_SAVE_PL3, pp_pl3_load_save_pl3_gen7, sizeof(pp_pl3_load_save_pl3_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, { { "NV12 Scaling module", PP_NV12_SCALING, pp_nv12_scaling_gen7, sizeof(pp_nv12_scaling_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, { { "NV12 AVS module", PP_NV12_AVS, pp_nv12_avs_gen7, sizeof(pp_nv12_avs_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, { { "NV12 DNDI module", PP_NV12_DNDI, pp_nv12_dndi_gen7, sizeof(pp_nv12_dndi_gen7), NULL, }, gen7_pp_nv12_dndi_initialize, }, { { "NV12 DN module", PP_NV12_DN, pp_nv12_dn_gen7, sizeof(pp_nv12_dn_gen7), NULL, }, gen7_pp_nv12_dn_initialize, }, { { "NV12_PA module", PP_NV12_LOAD_SAVE_PA, pp_nv12_load_save_pa_gen7, sizeof(pp_nv12_load_save_pa_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, { { "PL3_PA module", PP_PL3_LOAD_SAVE_PA, pp_pl3_load_save_pa_gen7, sizeof(pp_pl3_load_save_pa_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, { { "PA_NV12 module", PP_PA_LOAD_SAVE_NV12, pp_pa_load_save_nv12_gen7, sizeof(pp_pa_load_save_nv12_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, { { "PA_PL3 module", PP_PA_LOAD_SAVE_PL3, pp_pa_load_save_pl3_gen7, sizeof(pp_pa_load_save_pl3_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, { { "PA_PA module", PP_PA_LOAD_SAVE_PA, pp_pa_load_save_pa_gen7, sizeof(pp_pa_load_save_pa_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, { { "RGBX_NV12 module", PP_RGBX_LOAD_SAVE_NV12, pp_rgbx_load_save_nv12_gen7, sizeof(pp_rgbx_load_save_nv12_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, { { "NV12_RGBX module", PP_NV12_LOAD_SAVE_RGBX, pp_nv12_load_save_rgbx_gen7, sizeof(pp_nv12_load_save_rgbx_gen7), NULL, }, gen7_pp_plx_avs_initialize, }, }; static const uint32_t pp_null_gen75[][4] = { }; static const uint32_t pp_nv12_load_save_nv12_gen75[][4] = { #include "shaders/post_processing/gen7/pl2_to_pl2.g75b" }; static const uint32_t pp_nv12_load_save_pl3_gen75[][4] = { #include "shaders/post_processing/gen7/pl2_to_pl3.g75b" }; static const uint32_t pp_pl3_load_save_nv12_gen75[][4] = { #include "shaders/post_processing/gen7/pl3_to_pl2.g75b" }; static const uint32_t pp_pl3_load_save_pl3_gen75[][4] = { #include "shaders/post_processing/gen7/pl3_to_pl3.g75b" }; static const uint32_t pp_nv12_scaling_gen75[][4] = { #include "shaders/post_processing/gen7/avs.g75b" }; static const uint32_t pp_nv12_avs_gen75[][4] = { #include "shaders/post_processing/gen7/avs.g75b" }; static const uint32_t pp_nv12_dndi_gen75[][4] = { // #include "shaders/post_processing/gen7/dndi.g75b" }; static const uint32_t pp_nv12_dn_gen75[][4] = { // #include "shaders/post_processing/gen7/nv12_dn_nv12.g75b" }; static const uint32_t pp_nv12_load_save_pa_gen75[][4] = { #include "shaders/post_processing/gen7/pl2_to_pa.g75b" }; static const uint32_t pp_pl3_load_save_pa_gen75[][4] = { #include "shaders/post_processing/gen7/pl3_to_pa.g75b" }; static const uint32_t pp_pa_load_save_nv12_gen75[][4] = { #include "shaders/post_processing/gen7/pa_to_pl2.g75b" }; static const uint32_t pp_pa_load_save_pl3_gen75[][4] = { #include "shaders/post_processing/gen7/pa_to_pl3.g75b" }; static const uint32_t pp_pa_load_save_pa_gen75[][4] = { #include "shaders/post_processing/gen7/pa_to_pa.g75b" }; static const uint32_t pp_rgbx_load_save_nv12_gen75[][4] = { #include "shaders/post_processing/gen7/rgbx_to_nv12.g75b" }; static const uint32_t pp_nv12_load_save_rgbx_gen75[][4] = { #include "shaders/post_processing/gen7/pl2_to_rgbx.g75b" }; static struct pp_module pp_modules_gen75[] = { { { "NULL module (for testing)", PP_NULL, pp_null_gen75, sizeof(pp_null_gen75), NULL, }, pp_null_initialize, }, { { "NV12_NV12", PP_NV12_LOAD_SAVE_N12, pp_nv12_load_save_nv12_gen75, sizeof(pp_nv12_load_save_nv12_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, { { "NV12_PL3", PP_NV12_LOAD_SAVE_PL3, pp_nv12_load_save_pl3_gen75, sizeof(pp_nv12_load_save_pl3_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, { { "PL3_NV12", PP_PL3_LOAD_SAVE_N12, pp_pl3_load_save_nv12_gen75, sizeof(pp_pl3_load_save_nv12_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, { { "PL3_PL3", PP_PL3_LOAD_SAVE_PL3, pp_pl3_load_save_pl3_gen75, sizeof(pp_pl3_load_save_pl3_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, { { "NV12 Scaling module", PP_NV12_SCALING, pp_nv12_scaling_gen75, sizeof(pp_nv12_scaling_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, { { "NV12 AVS module", PP_NV12_AVS, pp_nv12_avs_gen75, sizeof(pp_nv12_avs_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, { { "NV12 DNDI module", PP_NV12_DNDI, pp_nv12_dndi_gen75, sizeof(pp_nv12_dndi_gen75), NULL, }, gen7_pp_nv12_dn_initialize, }, { { "NV12 DN module", PP_NV12_DN, pp_nv12_dn_gen75, sizeof(pp_nv12_dn_gen75), NULL, }, gen7_pp_nv12_dn_initialize, }, { { "NV12_PA module", PP_NV12_LOAD_SAVE_PA, pp_nv12_load_save_pa_gen75, sizeof(pp_nv12_load_save_pa_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, { { "PL3_PA module", PP_PL3_LOAD_SAVE_PA, pp_pl3_load_save_pa_gen75, sizeof(pp_pl3_load_save_pa_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, { { "PA_NV12 module", PP_PA_LOAD_SAVE_NV12, pp_pa_load_save_nv12_gen75, sizeof(pp_pa_load_save_nv12_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, { { "PA_PL3 module", PP_PA_LOAD_SAVE_PL3, pp_pa_load_save_pl3_gen75, sizeof(pp_pa_load_save_pl3_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, { { "PA_PA module", PP_PA_LOAD_SAVE_PA, pp_pa_load_save_pa_gen75, sizeof(pp_pa_load_save_pa_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, { { "RGBX_NV12 module", PP_RGBX_LOAD_SAVE_NV12, pp_rgbx_load_save_nv12_gen75, sizeof(pp_rgbx_load_save_nv12_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, { { "NV12_RGBX module", PP_NV12_LOAD_SAVE_RGBX, pp_nv12_load_save_rgbx_gen75, sizeof(pp_nv12_load_save_rgbx_gen75), NULL, }, gen7_pp_plx_avs_initialize, }, }; /* TODO: Modify the shader and then compile it again. * Currently it is derived from Haswell*/ static const uint32_t pp_null_gen8[][4] = { }; static const uint32_t pp_nv12_load_save_nv12_gen8[][4] = { #include "shaders/post_processing/gen8/pl2_to_pl2.g8b" }; static const uint32_t pp_nv12_load_save_pl3_gen8[][4] = { #include "shaders/post_processing/gen8/pl2_to_pl3.g8b" }; static const uint32_t pp_pl3_load_save_nv12_gen8[][4] = { #include "shaders/post_processing/gen8/pl3_to_pl2.g8b" }; static const uint32_t pp_pl3_load_save_pl3_gen8[][4] = { #include "shaders/post_processing/gen8/pl3_to_pl3.g8b" }; static const uint32_t pp_nv12_scaling_gen8[][4] = { #include "shaders/post_processing/gen8/pl2_to_pl2.g8b" }; static const uint32_t pp_nv12_avs_gen8[][4] = { #include "shaders/post_processing/gen8/pl2_to_pl2.g8b" }; static const uint32_t pp_nv12_dndi_gen8[][4] = { // #include "shaders/post_processing/gen7/dndi.g75b" }; static const uint32_t pp_nv12_dn_gen8[][4] = { // #include "shaders/post_processing/gen7/nv12_dn_nv12.g75b" }; static const uint32_t pp_nv12_load_save_pa_gen8[][4] = { #include "shaders/post_processing/gen8/pl2_to_pa.g8b" }; static const uint32_t pp_pl3_load_save_pa_gen8[][4] = { #include "shaders/post_processing/gen8/pl3_to_pa.g8b" }; static const uint32_t pp_pa_load_save_nv12_gen8[][4] = { #include "shaders/post_processing/gen8/pa_to_pl2.g8b" }; static const uint32_t pp_pa_load_save_pl3_gen8[][4] = { #include "shaders/post_processing/gen8/pa_to_pl3.g8b" }; static const uint32_t pp_pa_load_save_pa_gen8[][4] = { #include "shaders/post_processing/gen8/pa_to_pa.g8b" }; static const uint32_t pp_rgbx_load_save_nv12_gen8[][4] = { #include "shaders/post_processing/gen8/rgbx_to_nv12.g8b" }; static const uint32_t pp_nv12_load_save_rgbx_gen8[][4] = { #include "shaders/post_processing/gen8/pl2_to_rgbx.g8b" }; static struct pp_module pp_modules_gen8[] = { { { "NULL module (for testing)", PP_NULL, pp_null_gen8, sizeof(pp_null_gen8), NULL, }, pp_null_initialize, }, { { "NV12_NV12", PP_NV12_LOAD_SAVE_N12, pp_nv12_load_save_nv12_gen8, sizeof(pp_nv12_load_save_nv12_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, { { "NV12_PL3", PP_NV12_LOAD_SAVE_PL3, pp_nv12_load_save_pl3_gen8, sizeof(pp_nv12_load_save_pl3_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, { { "PL3_NV12", PP_PL3_LOAD_SAVE_N12, pp_pl3_load_save_nv12_gen8, sizeof(pp_pl3_load_save_nv12_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, { { "PL3_PL3", PP_PL3_LOAD_SAVE_N12, pp_pl3_load_save_pl3_gen8, sizeof(pp_pl3_load_save_pl3_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, { { "NV12 Scaling module", PP_NV12_SCALING, pp_nv12_scaling_gen8, sizeof(pp_nv12_scaling_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, { { "NV12 AVS module", PP_NV12_AVS, pp_nv12_avs_gen8, sizeof(pp_nv12_avs_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, { { "NV12 DNDI module", PP_NV12_DNDI, pp_nv12_dndi_gen8, sizeof(pp_nv12_dndi_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, { { "NV12 DN module", PP_NV12_DN, pp_nv12_dn_gen8, sizeof(pp_nv12_dn_gen8), NULL, }, pp_null_initialize, }, { { "NV12_PA module", PP_NV12_LOAD_SAVE_PA, pp_nv12_load_save_pa_gen8, sizeof(pp_nv12_load_save_pa_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, { { "PL3_PA module", PP_PL3_LOAD_SAVE_PA, pp_pl3_load_save_pa_gen8, sizeof(pp_pl3_load_save_pa_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, { { "PA_NV12 module", PP_PA_LOAD_SAVE_NV12, pp_pa_load_save_nv12_gen8, sizeof(pp_pa_load_save_nv12_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, { { "PA_PL3 module", PP_PA_LOAD_SAVE_PL3, pp_pa_load_save_pl3_gen8, sizeof(pp_pa_load_save_pl3_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, { { "PA_PA module", PP_PA_LOAD_SAVE_PA, pp_pa_load_save_pa_gen8, sizeof(pp_pa_load_save_pa_gen8), NULL, }, pp_null_initialize, }, { { "RGBX_NV12 module", PP_RGBX_LOAD_SAVE_NV12, pp_rgbx_load_save_nv12_gen8, sizeof(pp_rgbx_load_save_nv12_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, { { "NV12_RGBX module", PP_NV12_LOAD_SAVE_RGBX, pp_nv12_load_save_rgbx_gen8, sizeof(pp_nv12_load_save_rgbx_gen8), NULL, }, gen8_pp_plx_avs_initialize, }, }; static int pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface) { int fourcc; if (surface->type == I965_SURFACE_TYPE_IMAGE) { struct object_image *obj_image = (struct object_image *)surface->base; fourcc = obj_image->image.format.fourcc; } else { struct object_surface *obj_surface = (struct object_surface *)surface->base; fourcc = obj_surface->fourcc; } return fourcc; } static void pp_get_surface_size(VADriverContextP ctx, const struct i965_surface *surface, int *width, int *height) { if (surface->type == I965_SURFACE_TYPE_IMAGE) { struct object_image *obj_image = (struct object_image *)surface->base; *width = obj_image->image.width; *height = obj_image->image.height; } else { struct object_surface *obj_surface = (struct object_surface *)surface->base; *width = obj_surface->orig_width; *height = obj_surface->orig_height; } } static void pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss3.tiled_surface = 0; ss->ss3.tile_walk = 0; break; case I915_TILING_X: ss->ss3.tiled_surface = 1; ss->ss3.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss3.tiled_surface = 1; ss->ss3.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss2.tiled_surface = 0; ss->ss2.tile_walk = 0; break; case I915_TILING_X: ss->ss2.tiled_surface = 1; ss->ss2.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss2.tiled_surface = 1; ss->ss2.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss0.tiled_surface = 0; ss->ss0.tile_walk = 0; break; case I915_TILING_X: ss->ss0.tiled_surface = 1; ss->ss0.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss0.tiled_surface = 1; ss->ss0.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void gen8_pp_set_surface_tiling(struct gen8_surface_state *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss0.tiled_surface = 0; ss->ss0.tile_walk = 0; break; case I915_TILING_X: ss->ss0.tiled_surface = 1; ss->ss0.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss0.tiled_surface = 1; ss->ss0.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss2.tiled_surface = 0; ss->ss2.tile_walk = 0; break; case I915_TILING_X: ss->ss2.tiled_surface = 1; ss->ss2.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss2.tiled_surface = 1; ss->ss2.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void gen8_pp_set_surface2_tiling(struct gen8_surface_state2 *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss2.tiled_surface = 0; ss->ss2.tile_walk = 0; break; case I915_TILING_X: ss->ss2.tiled_surface = 1; ss->ss2.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss2.tiled_surface = 1; ss->ss2.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context) { struct i965_interface_descriptor *desc; dri_bo *bo; int pp_index = pp_context->current_pp; bo = pp_context->idrt.bo; dri_bo_map(bo, 1); assert(bo->virtual); desc = bo->virtual; memset(desc, 0, sizeof(*desc)); desc->desc0.grf_reg_blocks = 10; desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */ desc->desc1.const_urb_entry_read_offset = 0; desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */ desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5; desc->desc2.sampler_count = 0; desc->desc3.binding_table_entry_count = 0; desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, desc->desc0.grf_reg_blocks, offsetof(struct i965_interface_descriptor, desc0), pp_context->pp_modules[pp_index].kernel.bo); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, desc->desc2.sampler_count << 2, offsetof(struct i965_interface_descriptor, desc2), pp_context->sampler_state_table.bo); dri_bo_unmap(bo); pp_context->idrt.num_interface_descriptors++; } static void ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context) { struct i965_vfe_state *vfe_state; dri_bo *bo; bo = pp_context->vfe_state.bo; dri_bo_map(bo, 1); assert(bo->virtual); vfe_state = bo->virtual; memset(vfe_state, 0, sizeof(*vfe_state)); vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1; vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1; vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries; vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE; vfe_state->vfe1.children_present = 0; vfe_state->vfe2.interface_descriptor_base = pp_context->idrt.bo->offset >> 4; /* reloc */ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, offsetof(struct i965_vfe_state, vfe2), pp_context->idrt.bo); dri_bo_unmap(bo); } static void ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context) { unsigned char *constant_buffer; struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; assert(sizeof(*pp_static_parameter) == 128); dri_bo_map(pp_context->curbe.bo, 1); assert(pp_context->curbe.bo->virtual); constant_buffer = pp_context->curbe.bo->virtual; memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter)); dri_bo_unmap(pp_context->curbe.bo); } static void ironlake_pp_states_setup(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { ironlake_pp_interface_descriptor_table(pp_context); ironlake_pp_vfe_state(pp_context); ironlake_pp_upload_constants(pp_context); } static void ironlake_pp_pipeline_select(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; BEGIN_BATCH(batch, 1); OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); ADVANCE_BATCH(batch); } static void ironlake_pp_urb_layout(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; unsigned int vfe_fence, cs_fence; vfe_fence = pp_context->urb.cs_start; cs_fence = pp_context->urb.size; BEGIN_BATCH(batch, 3); OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1); OUT_BATCH(batch, 0); OUT_BATCH(batch, (vfe_fence << UF2_VFE_FENCE_SHIFT) | /* VFE_SIZE */ (cs_fence << UF2_CS_FENCE_SHIFT)); /* CS_SIZE */ ADVANCE_BATCH(batch); } static void ironlake_pp_state_base_address(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; BEGIN_BATCH(batch, 8); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); ADVANCE_BATCH(batch); } static void ironlake_pp_state_pointers(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; BEGIN_BATCH(batch, 3); OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1); OUT_BATCH(batch, 0); OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_BATCH(batch); } static void ironlake_pp_cs_urb_layout(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, CMD_CS_URB_STATE | 0); OUT_BATCH(batch, ((pp_context->urb.size_cs_entry - 1) << 4) | /* URB Entry Allocation Size */ (pp_context->urb.num_cs_entries << 0)); /* Number of URB Entries */ ADVANCE_BATCH(batch); } static void ironlake_pp_constant_buffer(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2)); OUT_RELOC(batch, pp_context->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, pp_context->urb.size_cs_entry - 1); ADVANCE_BATCH(batch); } static void ironlake_pp_object_walker(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; int x, x_steps, y, y_steps; struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; x_steps = pp_context->pp_x_steps(pp_context->private_context); y_steps = pp_context->pp_y_steps(pp_context->private_context); for (y = 0; y < y_steps; y++) { for (x = 0; x < x_steps; x++) { if (!pp_context->pp_set_block_parameter(pp_context, x, y)) { BEGIN_BATCH(batch, 20); OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* no indirect data */ OUT_BATCH(batch, 0); /* inline data grf 5-6 */ assert(sizeof(*pp_inline_parameter) == 64); intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter)); ADVANCE_BATCH(batch); } } } } static void ironlake_pp_pipeline_setup(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; intel_batchbuffer_start_atomic(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); ironlake_pp_pipeline_select(ctx, pp_context); ironlake_pp_state_base_address(ctx, pp_context); ironlake_pp_state_pointers(ctx, pp_context); ironlake_pp_urb_layout(ctx, pp_context); ironlake_pp_cs_urb_layout(ctx, pp_context); ironlake_pp_constant_buffer(ctx, pp_context); ironlake_pp_object_walker(ctx, pp_context); intel_batchbuffer_end_atomic(batch); } // update u/v offset when the surface format are packed yuv static void i965_update_src_surface_static_parameter( VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *surface) { struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; int fourcc = pp_get_surface_fourcc(ctx, surface); switch (fourcc) { case VA_FOURCC('Y', 'U', 'Y', '2'): pp_static_parameter->grf1.source_packed_u_offset = 1; pp_static_parameter->grf1.source_packed_v_offset = 3; break; case VA_FOURCC('U', 'Y', 'V', 'Y'): pp_static_parameter->grf1.source_packed_y_offset = 1; pp_static_parameter->grf1.source_packed_v_offset = 2; break; case VA_FOURCC('B', 'G', 'R', 'X'): case VA_FOURCC('B', 'G', 'R', 'A'): pp_static_parameter->grf1.source_rgb_layout = 0; break; case VA_FOURCC('R', 'G', 'B', 'X'): case VA_FOURCC('R', 'G', 'B', 'A'): pp_static_parameter->grf1.source_rgb_layout = 1; break; default: break; } } static void i965_update_dst_surface_static_parameter( VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *surface) { struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; int fourcc = pp_get_surface_fourcc(ctx, surface); switch (fourcc) { case VA_FOURCC('Y', 'U', 'Y', '2'): pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1; pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3; break; case VA_FOURCC('U', 'Y', 'V', 'Y'): pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1; pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2; break; case VA_FOURCC('B', 'G', 'R', 'X'): case VA_FOURCC('B', 'G', 'R', 'A'): pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 0; break; case VA_FOURCC('R', 'G', 'B', 'X'): case VA_FOURCC('R', 'G', 'B', 'A'): pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 1; break; default: break; } } static void i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context, dri_bo *surf_bo, unsigned long surf_bo_offset, int width, int height, int pitch, int format, int index, int is_target) { struct i965_surface_state *ss; dri_bo *ss_bo; unsigned int tiling; unsigned int swizzle; dri_bo_get_tiling(surf_bo, &tiling, &swizzle); ss_bo = pp_context->surface_state_binding_table.bo; assert(ss_bo); dri_bo_map(ss_bo, True); assert(ss_bo->virtual); ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index)); memset(ss, 0, sizeof(*ss)); ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = format; ss->ss1.base_addr = surf_bo->offset + surf_bo_offset; ss->ss2.width = width - 1; ss->ss2.height = height - 1; ss->ss3.pitch = pitch - 1; pp_set_surface_tiling(ss, tiling); dri_bo_emit_reloc(ss_bo, I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0, surf_bo_offset, SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1), surf_bo); ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index); dri_bo_unmap(ss_bo); } static void i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context, dri_bo *surf_bo, unsigned long surf_bo_offset, int width, int height, int wpitch, int xoffset, int yoffset, int format, int interleave_chroma, int index) { struct i965_surface_state2 *ss2; dri_bo *ss2_bo; unsigned int tiling; unsigned int swizzle; dri_bo_get_tiling(surf_bo, &tiling, &swizzle); ss2_bo = pp_context->surface_state_binding_table.bo; assert(ss2_bo); dri_bo_map(ss2_bo, True); assert(ss2_bo->virtual); ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index)); memset(ss2, 0, sizeof(*ss2)); ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset; ss2->ss1.cbcr_pixel_offset_v_direction = 0; ss2->ss1.width = width - 1; ss2->ss1.height = height - 1; ss2->ss2.pitch = wpitch - 1; ss2->ss2.interleave_chroma = interleave_chroma; ss2->ss2.surface_format = format; ss2->ss3.x_offset_for_cb = xoffset; ss2->ss3.y_offset_for_cb = yoffset; pp_set_surface2_tiling(ss2, tiling); dri_bo_emit_reloc(ss2_bo, I915_GEM_DOMAIN_RENDER, 0, surf_bo_offset, SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0), surf_bo); ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index); dri_bo_unmap(ss2_bo); } static void gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context, dri_bo *surf_bo, unsigned long surf_bo_offset, int width, int height, int pitch, int format, int index, int is_target) { struct i965_driver_data * const i965 = i965_driver_data(ctx); struct gen7_surface_state *ss; dri_bo *ss_bo; unsigned int tiling; unsigned int swizzle; dri_bo_get_tiling(surf_bo, &tiling, &swizzle); ss_bo = pp_context->surface_state_binding_table.bo; assert(ss_bo); dri_bo_map(ss_bo, True); assert(ss_bo->virtual); ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index)); memset(ss, 0, sizeof(*ss)); ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = format; ss->ss1.base_addr = surf_bo->offset + surf_bo_offset; ss->ss2.width = width - 1; ss->ss2.height = height - 1; ss->ss3.pitch = pitch - 1; gen7_pp_set_surface_tiling(ss, tiling); if (IS_HASWELL(i965->intel.device_id)) gen7_render_set_surface_scs(ss); dri_bo_emit_reloc(ss_bo, I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0, surf_bo_offset, SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1), surf_bo); ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index); dri_bo_unmap(ss_bo); } static void gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context, dri_bo *surf_bo, unsigned long surf_bo_offset, int width, int height, int wpitch, int xoffset, int yoffset, int format, int interleave_chroma, int index) { struct gen7_surface_state2 *ss2; dri_bo *ss2_bo; unsigned int tiling; unsigned int swizzle; dri_bo_get_tiling(surf_bo, &tiling, &swizzle); ss2_bo = pp_context->surface_state_binding_table.bo; assert(ss2_bo); dri_bo_map(ss2_bo, True); assert(ss2_bo->virtual); ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index)); memset(ss2, 0, sizeof(*ss2)); ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset; ss2->ss1.cbcr_pixel_offset_v_direction = 0; ss2->ss1.width = width - 1; ss2->ss1.height = height - 1; ss2->ss2.pitch = wpitch - 1; ss2->ss2.interleave_chroma = interleave_chroma; ss2->ss2.surface_format = format; ss2->ss3.x_offset_for_cb = xoffset; ss2->ss3.y_offset_for_cb = yoffset; gen7_pp_set_surface2_tiling(ss2, tiling); dri_bo_emit_reloc(ss2_bo, I915_GEM_DOMAIN_RENDER, 0, surf_bo_offset, SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0), surf_bo); ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index); dri_bo_unmap(ss2_bo); } static void gen8_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context, dri_bo *surf_bo, unsigned long surf_bo_offset, int width, int height, int pitch, int format, int index, int is_target) { struct gen8_surface_state *ss; dri_bo *ss_bo; unsigned int tiling; unsigned int swizzle; dri_bo_get_tiling(surf_bo, &tiling, &swizzle); ss_bo = pp_context->surface_state_binding_table.bo; assert(ss_bo); dri_bo_map(ss_bo, True); assert(ss_bo->virtual); ss = (struct gen8_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index)); memset(ss, 0, sizeof(*ss)); ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = format; ss->ss8.base_addr = surf_bo->offset + surf_bo_offset; ss->ss2.width = width - 1; ss->ss2.height = height - 1; ss->ss3.pitch = pitch - 1; /* Always set 1(align 4 mode) per B-spec */ ss->ss0.vertical_alignment = 1; ss->ss0.horizontal_alignment = 1; gen8_pp_set_surface_tiling(ss, tiling); gen8_render_set_surface_scs(ss); dri_bo_emit_reloc(ss_bo, I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0, surf_bo_offset, SURFACE_STATE_OFFSET(index) + offsetof(struct gen8_surface_state, ss8), surf_bo); ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index); dri_bo_unmap(ss_bo); } static void gen8_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context, dri_bo *surf_bo, unsigned long surf_bo_offset, int width, int height, int wpitch, int xoffset, int yoffset, int format, int interleave_chroma, int index) { struct gen8_surface_state2 *ss2; dri_bo *ss2_bo; unsigned int tiling; unsigned int swizzle; dri_bo_get_tiling(surf_bo, &tiling, &swizzle); ss2_bo = pp_context->surface_state_binding_table.bo; assert(ss2_bo); dri_bo_map(ss2_bo, True); assert(ss2_bo->virtual); ss2 = (struct gen8_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index)); memset(ss2, 0, sizeof(*ss2)); ss2->ss6.base_addr = surf_bo->offset + surf_bo_offset; ss2->ss1.cbcr_pixel_offset_v_direction = 0; ss2->ss1.width = width - 1; ss2->ss1.height = height - 1; ss2->ss2.pitch = wpitch - 1; ss2->ss2.interleave_chroma = interleave_chroma; ss2->ss2.surface_format = format; ss2->ss3.x_offset_for_cb = xoffset; ss2->ss3.y_offset_for_cb = yoffset; gen8_pp_set_surface2_tiling(ss2, tiling); dri_bo_emit_reloc(ss2_bo, I915_GEM_DOMAIN_RENDER, 0, surf_bo_offset, SURFACE_STATE_OFFSET(index) + offsetof(struct gen8_surface_state2, ss6), surf_bo); ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index); dri_bo_unmap(ss2_bo); } static void pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *surface, int base_index, int is_target, int *width, int *height, int *pitch, int *offset) { struct object_surface *obj_surface; struct object_image *obj_image; dri_bo *bo; int fourcc = pp_get_surface_fourcc(ctx, surface); const int Y = 0; const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1; const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2; const int UV = 1; int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2'); int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')); int full_packed_format = (fourcc == VA_FOURCC('R', 'G', 'B', 'A') || fourcc == VA_FOURCC('R', 'G', 'B', 'X') || fourcc == VA_FOURCC('B', 'G', 'R', 'A') || fourcc == VA_FOURCC('B', 'G', 'R', 'X')); int scale_factor_of_1st_plane_width_in_byte = 1; if (surface->type == I965_SURFACE_TYPE_SURFACE) { obj_surface = (struct object_surface *)surface->base; bo = obj_surface->bo; width[0] = obj_surface->orig_width; height[0] = obj_surface->orig_height; pitch[0] = obj_surface->width; offset[0] = 0; if (full_packed_format) { scale_factor_of_1st_plane_width_in_byte = 4; } else if (packed_yuv ) { scale_factor_of_1st_plane_width_in_byte = 2; } else if (interleaved_uv) { width[1] = obj_surface->orig_width; height[1] = obj_surface->orig_height / 2; pitch[1] = obj_surface->width; offset[1] = offset[0] + obj_surface->width * obj_surface->height; } else { width[1] = obj_surface->orig_width / 2; height[1] = obj_surface->orig_height / 2; pitch[1] = obj_surface->width / 2; offset[1] = offset[0] + obj_surface->width * obj_surface->height; width[2] = obj_surface->orig_width / 2; height[2] = obj_surface->orig_height / 2; pitch[2] = obj_surface->width / 2; offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2); } } else { obj_image = (struct object_image *)surface->base; bo = obj_image->bo; width[0] = obj_image->image.width; height[0] = obj_image->image.height; pitch[0] = obj_image->image.pitches[0]; offset[0] = obj_image->image.offsets[0]; if (full_packed_format) { scale_factor_of_1st_plane_width_in_byte = 4; } else if (packed_yuv ) { scale_factor_of_1st_plane_width_in_byte = 2; } else if (interleaved_uv) { width[1] = obj_image->image.width; height[1] = obj_image->image.height / 2; pitch[1] = obj_image->image.pitches[1]; offset[1] = obj_image->image.offsets[1]; } else { width[1] = obj_image->image.width / 2; height[1] = obj_image->image.height / 2; pitch[1] = obj_image->image.pitches[1]; offset[1] = obj_image->image.offsets[1]; width[2] = obj_image->image.width / 2; height[2] = obj_image->image.height / 2; pitch[2] = obj_image->image.pitches[2]; offset[2] = obj_image->image.offsets[2]; } } /* Y surface */ i965_pp_set_surface_state(ctx, pp_context, bo, offset[Y], width[Y] *scale_factor_of_1st_plane_width_in_byte / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM, base_index, is_target); if (!packed_yuv && !full_packed_format) { if (interleaved_uv) { i965_pp_set_surface_state(ctx, pp_context, bo, offset[UV], width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM, base_index + 1, is_target); } else { /* U surface */ i965_pp_set_surface_state(ctx, pp_context, bo, offset[U], width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM, base_index + 1, is_target); /* V surface */ i965_pp_set_surface_state(ctx, pp_context, bo, offset[V], width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM, base_index + 2, is_target); } } } static void gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *surface, int base_index, int is_target, int *width, int *height, int *pitch, int *offset) { struct object_surface *obj_surface; struct object_image *obj_image; dri_bo *bo; int fourcc = pp_get_surface_fourcc(ctx, surface); const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') || fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1; const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') || fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2; int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2'); int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')); int rgbx_format = (fourcc == VA_FOURCC('R', 'G', 'B', 'A') || fourcc == VA_FOURCC('R', 'G', 'B', 'X') || fourcc == VA_FOURCC('B', 'G', 'R', 'A') || fourcc == VA_FOURCC('B', 'G', 'R', 'X')); if (surface->type == I965_SURFACE_TYPE_SURFACE) { obj_surface = (struct object_surface *)surface->base; bo = obj_surface->bo; width[0] = obj_surface->orig_width; height[0] = obj_surface->orig_height; pitch[0] = obj_surface->width; offset[0] = 0; if (packed_yuv) { if (is_target) width[0] = obj_surface->orig_width * 2; /* surface format is R8, so double the width */ else width[0] = obj_surface->orig_width; /* surface foramt is YCBCR, width is specified in units of pixels */ } else if (rgbx_format) { if (is_target) width[0] = obj_surface->orig_width * 4; /* surface format is R8, so quad the width */ } width[1] = obj_surface->cb_cr_width; height[1] = obj_surface->cb_cr_height; pitch[1] = obj_surface->cb_cr_pitch; offset[1] = obj_surface->y_cb_offset * obj_surface->width; width[2] = obj_surface->cb_cr_width; height[2] = obj_surface->cb_cr_height; pitch[2] = obj_surface->cb_cr_pitch; offset[2] = obj_surface->y_cr_offset * obj_surface->width; } else { obj_image = (struct object_image *)surface->base; bo = obj_image->bo; width[0] = obj_image->image.width; height[0] = obj_image->image.height; pitch[0] = obj_image->image.pitches[0]; offset[0] = obj_image->image.offsets[0]; if (rgbx_format) { if (is_target) width[0] = obj_image->image.width * 4; /* surface format is R8, so quad the width */ } else if (packed_yuv) { if (is_target) width[0] = obj_image->image.width * 2; /* surface format is R8, so double the width */ else width[0] = obj_image->image.width; /* surface foramt is YCBCR, width is specified in units of pixels */ } else if (interleaved_uv) { width[1] = obj_image->image.width / 2; height[1] = obj_image->image.height / 2; pitch[1] = obj_image->image.pitches[1]; offset[1] = obj_image->image.offsets[1]; } else { width[1] = obj_image->image.width / 2; height[1] = obj_image->image.height / 2; pitch[1] = obj_image->image.pitches[U]; offset[1] = obj_image->image.offsets[U]; width[2] = obj_image->image.width / 2; height[2] = obj_image->image.height / 2; pitch[2] = obj_image->image.pitches[V]; offset[2] = obj_image->image.offsets[V]; } } if (is_target) { gen7_pp_set_surface_state(ctx, pp_context, bo, 0, width[0] / 4, height[0], pitch[0], I965_SURFACEFORMAT_R8_UINT, base_index, 1); if (rgbx_format) { struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; /* the format is MSB: X-B-G-R */ pp_static_parameter->grf2.save_avs_rgb_swap = 0; if ((fourcc == VA_FOURCC('B', 'G', 'R', 'A')) || (fourcc == VA_FOURCC('B', 'G', 'R', 'X'))) { /* It is stored as MSB: X-R-G-B */ pp_static_parameter->grf2.save_avs_rgb_swap = 1; } } if (!packed_yuv && !rgbx_format) { if (interleaved_uv) { gen7_pp_set_surface_state(ctx, pp_context, bo, offset[1], width[1] / 2, height[1], pitch[1], I965_SURFACEFORMAT_R8G8_SINT, base_index + 1, 1); } else { gen7_pp_set_surface_state(ctx, pp_context, bo, offset[1], width[1] / 4, height[1], pitch[1], I965_SURFACEFORMAT_R8_SINT, base_index + 1, 1); gen7_pp_set_surface_state(ctx, pp_context, bo, offset[2], width[2] / 4, height[2], pitch[2], I965_SURFACEFORMAT_R8_SINT, base_index + 2, 1); } } } else { int format0 = SURFACE_FORMAT_Y8_UNORM; switch (fourcc) { case VA_FOURCC('Y', 'U', 'Y', '2'): format0 = SURFACE_FORMAT_YCRCB_NORMAL; break; case VA_FOURCC('U', 'Y', 'V', 'Y'): format0 = SURFACE_FORMAT_YCRCB_SWAPY; break; default: break; } if (rgbx_format) { struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; /* Only R8G8B8A8_UNORM is supported for BGRX or RGBX */ format0 = SURFACE_FORMAT_R8G8B8A8_UNORM; pp_static_parameter->grf2.src_avs_rgb_swap = 0; if ((fourcc == VA_FOURCC('B', 'G', 'R', 'A')) || (fourcc == VA_FOURCC('B', 'G', 'R', 'X'))) { pp_static_parameter->grf2.src_avs_rgb_swap = 1; } } gen7_pp_set_surface2_state(ctx, pp_context, bo, offset[0], width[0], height[0], pitch[0], 0, 0, format0, 0, base_index); if (!packed_yuv && !rgbx_format) { if (interleaved_uv) { gen7_pp_set_surface2_state(ctx, pp_context, bo, offset[1], width[1], height[1], pitch[1], 0, 0, SURFACE_FORMAT_R8B8_UNORM, 0, base_index + 1); } else { gen7_pp_set_surface2_state(ctx, pp_context, bo, offset[1], width[1], height[1], pitch[1], 0, 0, SURFACE_FORMAT_R8_UNORM, 0, base_index + 1); gen7_pp_set_surface2_state(ctx, pp_context, bo, offset[2], width[2], height[2], pitch[2], 0, 0, SURFACE_FORMAT_R8_UNORM, 0, base_index + 2); } } } } static void gen8_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *surface, int base_index, int is_target, int *width, int *height, int *pitch, int *offset) { struct object_surface *obj_surface; struct object_image *obj_image; dri_bo *bo; int fourcc = pp_get_surface_fourcc(ctx, surface); const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') || fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1; const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') || fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2; int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2'); int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')); int rgbx_format = (fourcc == VA_FOURCC('R', 'G', 'B', 'A') || fourcc == VA_FOURCC('R', 'G', 'B', 'X') || fourcc == VA_FOURCC('B', 'G', 'R', 'A') || fourcc == VA_FOURCC('B', 'G', 'R', 'X')); if (surface->type == I965_SURFACE_TYPE_SURFACE) { obj_surface = (struct object_surface *)surface->base; bo = obj_surface->bo; width[0] = obj_surface->orig_width; height[0] = obj_surface->orig_height; pitch[0] = obj_surface->width; offset[0] = 0; if (packed_yuv) { if (is_target) width[0] = obj_surface->orig_width * 2; /* surface format is R8, so double the width */ else width[0] = obj_surface->orig_width; /* surface foramt is YCBCR, width is specified in units of pixels */ } else if (rgbx_format) { if (is_target) width[0] = obj_surface->orig_width * 4; /* surface format is R8, so quad the width */ } width[1] = obj_surface->cb_cr_width; height[1] = obj_surface->cb_cr_height; pitch[1] = obj_surface->cb_cr_pitch; offset[1] = obj_surface->y_cb_offset * obj_surface->width; width[2] = obj_surface->cb_cr_width; height[2] = obj_surface->cb_cr_height; pitch[2] = obj_surface->cb_cr_pitch; offset[2] = obj_surface->y_cr_offset * obj_surface->width; } else { obj_image = (struct object_image *)surface->base; bo = obj_image->bo; width[0] = obj_image->image.width; height[0] = obj_image->image.height; pitch[0] = obj_image->image.pitches[0]; offset[0] = obj_image->image.offsets[0]; if (rgbx_format) { if (is_target) width[0] = obj_image->image.width * 4; /* surface format is R8, so quad the width */ } else if (packed_yuv) { if (is_target) width[0] = obj_image->image.width * 2; /* surface format is R8, so double the width */ else width[0] = obj_image->image.width; /* surface foramt is YCBCR, width is specified in units of pixels */ } else if (interleaved_uv) { width[1] = obj_image->image.width / 2; height[1] = obj_image->image.height / 2; pitch[1] = obj_image->image.pitches[1]; offset[1] = obj_image->image.offsets[1]; } else { width[1] = obj_image->image.width / 2; height[1] = obj_image->image.height / 2; pitch[1] = obj_image->image.pitches[U]; offset[1] = obj_image->image.offsets[U]; width[2] = obj_image->image.width / 2; height[2] = obj_image->image.height / 2; pitch[2] = obj_image->image.pitches[V]; offset[2] = obj_image->image.offsets[V]; } } if (is_target) { gen8_pp_set_surface_state(ctx, pp_context, bo, 0, width[0] / 4, height[0], pitch[0], I965_SURFACEFORMAT_R8_UINT, base_index, 1); if (rgbx_format) { struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; /* the format is MSB: X-B-G-R */ pp_static_parameter->grf2.save_avs_rgb_swap = 0; if ((fourcc == VA_FOURCC('B', 'G', 'R', 'A')) || (fourcc == VA_FOURCC('B', 'G', 'R', 'X'))) { /* It is stored as MSB: X-R-G-B */ pp_static_parameter->grf2.save_avs_rgb_swap = 1; } } if (!packed_yuv && !rgbx_format) { if (interleaved_uv) { gen8_pp_set_surface_state(ctx, pp_context, bo, offset[1], width[1] / 2, height[1], pitch[1], I965_SURFACEFORMAT_R8G8_SINT, base_index + 1, 1); } else { gen8_pp_set_surface_state(ctx, pp_context, bo, offset[1], width[1] / 4, height[1], pitch[1], I965_SURFACEFORMAT_R8_SINT, base_index + 1, 1); gen8_pp_set_surface_state(ctx, pp_context, bo, offset[2], width[2] / 4, height[2], pitch[2], I965_SURFACEFORMAT_R8_SINT, base_index + 2, 1); } } } else { int format0 = SURFACE_FORMAT_Y8_UNORM; switch (fourcc) { case VA_FOURCC('Y', 'U', 'Y', '2'): format0 = SURFACE_FORMAT_YCRCB_NORMAL; break; case VA_FOURCC('U', 'Y', 'V', 'Y'): format0 = SURFACE_FORMAT_YCRCB_SWAPY; break; default: break; } if (rgbx_format) { struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; /* Only R8G8B8A8_UNORM is supported for BGRX or RGBX */ format0 = SURFACE_FORMAT_R8G8B8A8_UNORM; pp_static_parameter->grf2.src_avs_rgb_swap = 0; if ((fourcc == VA_FOURCC('B', 'G', 'R', 'A')) || (fourcc == VA_FOURCC('B', 'G', 'R', 'X'))) { pp_static_parameter->grf2.src_avs_rgb_swap = 1; } } gen8_pp_set_surface2_state(ctx, pp_context, bo, offset[0], width[0], height[0], pitch[0], 0, 0, format0, 0, base_index); if (!packed_yuv && !rgbx_format) { if (interleaved_uv) { gen8_pp_set_surface2_state(ctx, pp_context, bo, offset[1], width[1], height[1], pitch[1], 0, 0, SURFACE_FORMAT_R8B8_UNORM, 0, base_index + 1); } else { gen8_pp_set_surface2_state(ctx, pp_context, bo, offset[1], width[1], height[1], pitch[1], 0, 0, SURFACE_FORMAT_R8_UNORM, 0, base_index + 1); gen8_pp_set_surface2_state(ctx, pp_context, bo, offset[2], width[2], height[2], pitch[2], 0, 0, SURFACE_FORMAT_R8_UNORM, 0, base_index + 2); } } } } static int pp_null_x_steps(void *private_context) { return 1; } static int pp_null_y_steps(void *private_context) { return 1; } static int pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y) { return 0; } static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param) { /* private function & data */ pp_context->pp_x_steps = pp_null_x_steps; pp_context->pp_y_steps = pp_null_y_steps; pp_context->private_context = NULL; pp_context->pp_set_block_parameter = pp_null_set_block_parameter; dst_surface->flags = src_surface->flags; return VA_STATUS_SUCCESS; } static int pp_load_save_x_steps(void *private_context) { return 1; } static int pp_load_save_y_steps(void *private_context) { struct pp_load_save_context *pp_load_save_context = private_context; return pp_load_save_context->dest_h / 8; } static int pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y) { struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)pp_context->private_context; pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_load_save_context->dest_x; pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_load_save_context->dest_y; return 0; } static void calculate_boundary_block_mask(struct i965_post_processing_context *pp_context, const VARectangle *dst_rect) { int i; /* x offset of dest surface must be dword aligned. * so we have to extend dst surface on left edge, and mask out pixels not interested */ if (dst_rect->x%GPU_ASM_X_OFFSET_ALIGNMENT) { pp_context->block_horizontal_mask_left = 0; for (i=dst_rect->x%GPU_ASM_X_OFFSET_ALIGNMENT; iblock_horizontal_mask_left |= 1<block_horizontal_mask_left = 0xffff; } int dst_width_adjust = dst_rect->width + dst_rect->x%GPU_ASM_X_OFFSET_ALIGNMENT; if (dst_width_adjust%GPU_ASM_BLOCK_WIDTH){ pp_context->block_horizontal_mask_right = (1 << (dst_width_adjust%GPU_ASM_BLOCK_WIDTH)) - 1; } else { pp_context->block_horizontal_mask_right = 0xffff; } if (dst_rect->height%GPU_ASM_BLOCK_HEIGHT){ pp_context->block_vertical_mask_bottom = (1 << (dst_rect->height%GPU_ASM_BLOCK_HEIGHT)) - 1; } else { pp_context->block_vertical_mask_bottom = 0xff; } } static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param) { struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->pp_load_save_context; struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; int width[3], height[3], pitch[3], offset[3]; /* source surface */ pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0, width, height, pitch, offset); /* destination surface */ pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1, width, height, pitch, offset); /* private function & data */ pp_context->pp_x_steps = pp_load_save_x_steps; pp_context->pp_y_steps = pp_load_save_y_steps; pp_context->private_context = &pp_context->pp_load_save_context; pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter; int dst_left_edge_extend = dst_rect->x%GPU_ASM_X_OFFSET_ALIGNMENT;; pp_load_save_context->dest_x = dst_rect->x - dst_left_edge_extend; pp_load_save_context->dest_y = dst_rect->y; pp_load_save_context->dest_h = ALIGN(dst_rect->height, 8); pp_load_save_context->dest_w = ALIGN(dst_rect->width+dst_left_edge_extend, 16); pp_inline_parameter->grf5.block_count_x = pp_load_save_context->dest_w / 16; /* 1 x N */ pp_inline_parameter->grf5.number_blocks = pp_load_save_context->dest_w / 16; pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x; pp_static_parameter->grf3.vertical_origin_offset = src_rect->y; // update u/v offset for packed yuv i965_update_src_surface_static_parameter (ctx, pp_context, src_surface); i965_update_dst_surface_static_parameter (ctx, pp_context, dst_surface); dst_surface->flags = src_surface->flags; return VA_STATUS_SUCCESS; } static int pp_scaling_x_steps(void *private_context) { return 1; } static int pp_scaling_y_steps(void *private_context) { struct pp_scaling_context *pp_scaling_context = private_context; return pp_scaling_context->dest_h / 8; } static int pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y) { struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)pp_context->private_context; struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step; float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step; pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x; pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y; pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x; pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y; return 0; } static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param) { struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->pp_scaling_context; struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; struct object_surface *obj_surface; struct i965_sampler_state *sampler_state; int in_w, in_h, in_wpitch, in_hpitch; int out_w, out_h, out_wpitch, out_hpitch; /* source surface */ obj_surface = (struct object_surface *)src_surface->base; in_w = obj_surface->orig_width; in_h = obj_surface->orig_height; in_wpitch = obj_surface->width; in_hpitch = obj_surface->height; /* source Y surface index 1 */ i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, 0, in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM, 1, 0); /* source UV surface index 2 */ i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, in_wpitch * in_hpitch, in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM, 2, 0); /* destination surface */ obj_surface = (struct object_surface *)dst_surface->base; out_w = obj_surface->orig_width; out_h = obj_surface->orig_height; out_wpitch = obj_surface->width; out_hpitch = obj_surface->height; /* destination Y surface index 7 */ i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, 0, out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM, 7, 1); /* destination UV surface index 8 */ i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, out_wpitch * out_hpitch, out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM, 8, 1); /* sampler state */ dri_bo_map(pp_context->sampler_state_table.bo, True); assert(pp_context->sampler_state_table.bo->virtual); sampler_state = pp_context->sampler_state_table.bo->virtual; /* SIMD16 Y index 1 */ sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR; sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR; sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP; /* SIMD16 UV index 2 */ sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR; sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR; sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP; dri_bo_unmap(pp_context->sampler_state_table.bo); /* private function & data */ pp_context->pp_x_steps = pp_scaling_x_steps; pp_context->pp_y_steps = pp_scaling_y_steps; pp_context->private_context = &pp_context->pp_scaling_context; pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter; int dst_left_edge_extend = dst_rect->x%GPU_ASM_X_OFFSET_ALIGNMENT; float src_left_edge_extend = (float)dst_left_edge_extend*src_rect->width/dst_rect->width; pp_scaling_context->dest_x = dst_rect->x - dst_left_edge_extend; pp_scaling_context->dest_y = dst_rect->y; pp_scaling_context->dest_w = ALIGN(dst_rect->width + dst_left_edge_extend, 16); pp_scaling_context->dest_h = ALIGN(dst_rect->height, 8); pp_scaling_context->src_normalized_x = (float)(src_rect->x - src_left_edge_extend)/ in_w; pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h; pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height; pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) (src_rect->width + src_left_edge_extend)/ in_w / (dst_rect->width + dst_left_edge_extend); pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16; /* 1 x N */ pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16; dst_surface->flags = src_surface->flags; return VA_STATUS_SUCCESS; } static int pp_avs_x_steps(void *private_context) { struct pp_avs_context *pp_avs_context = private_context; return pp_avs_context->dest_w / 16; } static int pp_avs_y_steps(void *private_context) { return 1; } static int pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y) { struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)pp_context->private_context; struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; float src_x_steping, src_y_steping, video_step_delta; int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16); if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) { src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step; pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x; } else if (tmp_w >= pp_avs_context->dest_w) { pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w; pp_inline_parameter->grf6.video_step_delta = 0; if (x == 0) { pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 + pp_avs_context->src_normalized_x; } else { src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step; video_step_delta = pp_inline_parameter->grf6.video_step_delta; pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 + 16 * 15 * video_step_delta / 2; } } else { int n0, n1, n2, nls_left, nls_right; int factor_a = 5, factor_b = 4; float f; n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2); n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0; n2 = tmp_w / (16 * factor_a); nls_left = n0 + n2; nls_right = n1 + n2; f = (float) n2 * 16 / tmp_w; if (n0 < 5) { pp_inline_parameter->grf6.video_step_delta = 0.0; if (x == 0) { pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w; pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x; } else { src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step; video_step_delta = pp_inline_parameter->grf6.video_step_delta; pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 + 16 * 15 * video_step_delta / 2; } } else { if (x < nls_left) { /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */ float a = f / (nls_left * 16 * factor_b); float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1)); pp_inline_parameter->grf6.video_step_delta = b; if (x == 0) { pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x; pp_inline_parameter->grf5.normalized_video_x_scaling_step = a; } else { src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step; video_step_delta = pp_inline_parameter->grf6.video_step_delta; pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 + 16 * 15 * video_step_delta / 2; pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b; } } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) { /* scale the center linearly */ src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step; video_step_delta = pp_inline_parameter->grf6.video_step_delta; pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 + 16 * 15 * video_step_delta / 2; pp_inline_parameter->grf6.video_step_delta = 0.0; pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w; } else { float a = f / (nls_right * 16 * factor_b); float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1)); src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step; video_step_delta = pp_inline_parameter->grf6.video_step_delta; pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 + 16 * 15 * video_step_delta / 2; pp_inline_parameter->grf6.video_step_delta = -b; if (x == (pp_avs_context->dest_w / 16 - nls_right)) pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16 - 1) * b; else pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16; } } } src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step; pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y; pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x; pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y; return 0; } static VAStatus pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param, int nlas) { struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->pp_avs_context; struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; struct object_surface *obj_surface; struct i965_sampler_8x8 *sampler_8x8; struct i965_sampler_8x8_state *sampler_8x8_state; int index; int in_w, in_h, in_wpitch, in_hpitch; int out_w, out_h, out_wpitch, out_hpitch; int i; /* surface */ obj_surface = (struct object_surface *)src_surface->base; in_w = obj_surface->orig_width; in_h = obj_surface->orig_height; in_wpitch = obj_surface->width; in_hpitch = obj_surface->height; /* source Y surface index 1 */ i965_pp_set_surface2_state(ctx, pp_context, obj_surface->bo, 0, in_w, in_h, in_wpitch, 0, 0, SURFACE_FORMAT_Y8_UNORM, 0, 1); /* source UV surface index 2 */ i965_pp_set_surface2_state(ctx, pp_context, obj_surface->bo, in_wpitch * in_hpitch, in_w / 2, in_h / 2, in_wpitch, 0, 0, SURFACE_FORMAT_R8B8_UNORM, 0, 2); /* destination surface */ obj_surface = (struct object_surface *)dst_surface->base; out_w = obj_surface->orig_width; out_h = obj_surface->orig_height; out_wpitch = obj_surface->width; out_hpitch = obj_surface->height; assert(out_w <= out_wpitch && out_h <= out_hpitch); /* destination Y surface index 7 */ i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, 0, out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM, 7, 1); /* destination UV surface index 8 */ i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, out_wpitch * out_hpitch, out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM, 8, 1); /* sampler 8x8 state */ dri_bo_map(pp_context->sampler_state_table.bo_8x8, True); assert(pp_context->sampler_state_table.bo_8x8->virtual); assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138); sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual; memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state)); for (i = 0; i < 17; i++) { /* for Y channel, currently ignore */ sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00; sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00; sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08; sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18; sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18; sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08; sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00; sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00; sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00; sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00; sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10; sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10; sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10; sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10; sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00; sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00; /* for U/V channel, 0.25 */ sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0; sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0; sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10; sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10; sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10; sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10; sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0; sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0; sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0; sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0; sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10; sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10; sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10; sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10; sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0; sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0; } sampler_8x8_state->dw136.default_sharpness_level = 0; sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1; sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1; sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1; dri_bo_unmap(pp_context->sampler_state_table.bo_8x8); /* sampler 8x8 */ dri_bo_map(pp_context->sampler_state_table.bo, True); assert(pp_context->sampler_state_table.bo->virtual); assert(sizeof(*sampler_8x8) == sizeof(int) * 16); sampler_8x8 = pp_context->sampler_state_table.bo->virtual; /* sample_8x8 Y index 1 */ index = 1; memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8)); sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP; sampler_8x8[index].dw0.ief_bypass = 1; sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL; sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5; sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5; sampler_8x8[index].dw2.global_noise_estimation = 22; sampler_8x8[index].dw2.strong_edge_threshold = 8; sampler_8x8[index].dw2.weak_edge_threshold = 1; sampler_8x8[index].dw3.strong_edge_weight = 7; sampler_8x8[index].dw3.regular_weight = 2; sampler_8x8[index].dw3.non_edge_weight = 0; sampler_8x8[index].dw3.gain_factor = 40; sampler_8x8[index].dw4.steepness_boost = 0; sampler_8x8[index].dw4.steepness_threshold = 0; sampler_8x8[index].dw4.mr_boost = 0; sampler_8x8[index].dw4.mr_threshold = 5; sampler_8x8[index].dw5.pwl1_point_1 = 4; sampler_8x8[index].dw5.pwl1_point_2 = 12; sampler_8x8[index].dw5.pwl1_point_3 = 16; sampler_8x8[index].dw5.pwl1_point_4 = 26; sampler_8x8[index].dw6.pwl1_point_5 = 40; sampler_8x8[index].dw6.pwl1_point_6 = 160; sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127; sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98; sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88; sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64; sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44; sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0; sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0; sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3; sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32; sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32; sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58; sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100; sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108; sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88; sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116; sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20; sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96; sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32; sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50; sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0; sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0; sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116; sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0; sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114; sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67; sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9; sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3; sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15; sampler_8x8[index].dw13.limiter_boost = 0; sampler_8x8[index].dw13.minimum_limiter = 10; sampler_8x8[index].dw13.maximum_limiter = 11; sampler_8x8[index].dw14.clip_limiter = 130; dri_bo_emit_reloc(pp_context->sampler_state_table.bo, I915_GEM_DOMAIN_RENDER, 0, 0, sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1), pp_context->sampler_state_table.bo_8x8); /* sample_8x8 UV index 2 */ index = 2; memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8)); sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP; sampler_8x8[index].dw0.ief_bypass = 1; sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL; sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5; sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5; sampler_8x8[index].dw2.global_noise_estimation = 22; sampler_8x8[index].dw2.strong_edge_threshold = 8; sampler_8x8[index].dw2.weak_edge_threshold = 1; sampler_8x8[index].dw3.strong_edge_weight = 7; sampler_8x8[index].dw3.regular_weight = 2; sampler_8x8[index].dw3.non_edge_weight = 0; sampler_8x8[index].dw3.gain_factor = 40; sampler_8x8[index].dw4.steepness_boost = 0; sampler_8x8[index].dw4.steepness_threshold = 0; sampler_8x8[index].dw4.mr_boost = 0; sampler_8x8[index].dw4.mr_threshold = 5; sampler_8x8[index].dw5.pwl1_point_1 = 4; sampler_8x8[index].dw5.pwl1_point_2 = 12; sampler_8x8[index].dw5.pwl1_point_3 = 16; sampler_8x8[index].dw5.pwl1_point_4 = 26; sampler_8x8[index].dw6.pwl1_point_5 = 40; sampler_8x8[index].dw6.pwl1_point_6 = 160; sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127; sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98; sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88; sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64; sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44; sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0; sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0; sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3; sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32; sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32; sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58; sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100; sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108; sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88; sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116; sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20; sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96; sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32; sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50; sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0; sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0; sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116; sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0; sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114; sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67; sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9; sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3; sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15; sampler_8x8[index].dw13.limiter_boost = 0; sampler_8x8[index].dw13.minimum_limiter = 10; sampler_8x8[index].dw13.maximum_limiter = 11; sampler_8x8[index].dw14.clip_limiter = 130; dri_bo_emit_reloc(pp_context->sampler_state_table.bo, I915_GEM_DOMAIN_RENDER, 0, 0, sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1), pp_context->sampler_state_table.bo_8x8); dri_bo_unmap(pp_context->sampler_state_table.bo); /* private function & data */ pp_context->pp_x_steps = pp_avs_x_steps; pp_context->pp_y_steps = pp_avs_y_steps; pp_context->private_context = &pp_context->pp_avs_context; pp_context->pp_set_block_parameter = pp_avs_set_block_parameter; int dst_left_edge_extend = dst_rect->x%GPU_ASM_X_OFFSET_ALIGNMENT; float src_left_edge_extend = (float)dst_left_edge_extend*src_rect->width/dst_rect->width; pp_avs_context->dest_x = dst_rect->x - dst_left_edge_extend; pp_avs_context->dest_y = dst_rect->y; pp_avs_context->dest_w = ALIGN(dst_rect->width + dst_left_edge_extend, 16); pp_avs_context->dest_h = ALIGN(dst_rect->height, 8); pp_avs_context->src_normalized_x = (float)(src_rect->x - src_left_edge_extend)/ in_w; pp_avs_context->src_normalized_y = (float)src_rect->y / in_h; pp_avs_context->src_w = src_rect->width + src_left_edge_extend; pp_avs_context->src_h = src_rect->height; pp_static_parameter->grf4.r4_2.avs.nlas = nlas; pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height; pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) (src_rect->width + src_left_edge_extend)/ in_w / (dst_rect->width + dst_left_edge_extend); pp_inline_parameter->grf5.block_count_x = 1; /* M x 1 */ pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8; pp_inline_parameter->grf6.video_step_delta = 0.0; dst_surface->flags = src_surface->flags; return VA_STATUS_SUCCESS; } static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param) { return pp_nv12_avs_initialize(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, filter_param, 1); } static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param) { return pp_nv12_avs_initialize(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, filter_param, 0); } static int gen7_pp_avs_x_steps(void *private_context) { struct pp_avs_context *pp_avs_context = private_context; return pp_avs_context->dest_w / 16; } static int gen7_pp_avs_y_steps(void *private_context) { struct pp_avs_context *pp_avs_context = private_context; return pp_avs_context->dest_h / 16; } static int gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y) { struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)pp_context->private_context; struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x; pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y; pp_inline_parameter->grf7.constant_0 = 0xffffffff; pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = pp_avs_context->horiz_range / pp_avs_context->src_w; return 0; } static void gen7_update_src_surface_uv_offset(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *surface) { struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; int fourcc = pp_get_surface_fourcc(ctx, surface); if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) { pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0; pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1; pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3; } else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) { pp_static_parameter->grf2.di_destination_packed_y_component_offset = 1; pp_static_parameter->grf2.di_destination_packed_u_component_offset = 0; pp_static_parameter->grf2.di_destination_packed_v_component_offset = 2; } } static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param) { struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->pp_avs_context; struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; struct gen7_sampler_8x8 *sampler_8x8; struct i965_sampler_8x8_state *sampler_8x8_state; int index, i; int width[3], height[3], pitch[3], offset[3]; int src_width, src_height; /* source surface */ gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0, width, height, pitch, offset); src_width = width[0]; src_height = height[0]; /* destination surface */ gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1, width, height, pitch, offset); /* sampler 8x8 state */ dri_bo_map(pp_context->sampler_state_table.bo_8x8, True); assert(pp_context->sampler_state_table.bo_8x8->virtual); assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138); sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual; memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state)); for (i = 0; i < 17; i++) { float coff; coff = i; coff = coff / 16; /* for Y channel, currently ignore */ sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0; sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0; sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0; sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = intel_format_convert(1 - coff, 1, 6,0); sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = intel_format_convert(coff, 1, 6, 0); sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0; sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0; sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0; sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0; sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0; sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0; sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = intel_format_convert(1 - coff, 1, 6, 0); sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = intel_format_convert(coff, 1, 6, 0); sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0; sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0; sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0; /* for U/V channel, 0.25 */ sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0; sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0; sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x0; sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = intel_format_convert(1 - coff, 1, 6, 0); sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = intel_format_convert(coff, 1, 6, 0); sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0; sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0; sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0; sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0; sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0; sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x0; sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = intel_format_convert(1 - coff, 1, 6, 0); sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = intel_format_convert(coff, 1, 6, 0); sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x0; sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0; sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0; } sampler_8x8_state->dw136.default_sharpness_level = 0; sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1; sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1; sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1; dri_bo_unmap(pp_context->sampler_state_table.bo_8x8); /* sampler 8x8 */ dri_bo_map(pp_context->sampler_state_table.bo, True); assert(pp_context->sampler_state_table.bo->virtual); assert(sizeof(*sampler_8x8) == sizeof(int) * 4); sampler_8x8 = pp_context->sampler_state_table.bo->virtual; /* sample_8x8 Y index 4 */ index = 4; memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8)); sampler_8x8[index].dw0.global_noise_estimation = 255; sampler_8x8[index].dw0.ief_bypass = 1; sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5; sampler_8x8[index].dw2.weak_edge_threshold = 1; sampler_8x8[index].dw2.strong_edge_threshold = 8; sampler_8x8[index].dw2.r5x_coefficient = 9; sampler_8x8[index].dw2.r5cx_coefficient = 8; sampler_8x8[index].dw2.r5c_coefficient = 3; sampler_8x8[index].dw3.r3x_coefficient = 27; sampler_8x8[index].dw3.r3c_coefficient = 5; sampler_8x8[index].dw3.gain_factor = 40; sampler_8x8[index].dw3.non_edge_weight = 1; sampler_8x8[index].dw3.regular_weight = 2; sampler_8x8[index].dw3.strong_edge_weight = 7; sampler_8x8[index].dw3.ief4_smooth_enable = 0; dri_bo_emit_reloc(pp_context->sampler_state_table.bo, I915_GEM_DOMAIN_RENDER, 0, 0, sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1), pp_context->sampler_state_table.bo_8x8); /* sample_8x8 UV index 8 */ index = 8; memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8)); sampler_8x8[index].dw0.disable_8x8_filter = 0; sampler_8x8[index].dw0.global_noise_estimation = 255; sampler_8x8[index].dw0.ief_bypass = 1; sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5; sampler_8x8[index].dw2.weak_edge_threshold = 1; sampler_8x8[index].dw2.strong_edge_threshold = 8; sampler_8x8[index].dw2.r5x_coefficient = 9; sampler_8x8[index].dw2.r5cx_coefficient = 8; sampler_8x8[index].dw2.r5c_coefficient = 3; sampler_8x8[index].dw3.r3x_coefficient = 27; sampler_8x8[index].dw3.r3c_coefficient = 5; sampler_8x8[index].dw3.gain_factor = 40; sampler_8x8[index].dw3.non_edge_weight = 1; sampler_8x8[index].dw3.regular_weight = 2; sampler_8x8[index].dw3.strong_edge_weight = 7; sampler_8x8[index].dw3.ief4_smooth_enable = 0; dri_bo_emit_reloc(pp_context->sampler_state_table.bo, I915_GEM_DOMAIN_RENDER, 0, 0, sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1), pp_context->sampler_state_table.bo_8x8); /* sampler_8x8 V, index 12 */ index = 12; memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8)); sampler_8x8[index].dw0.disable_8x8_filter = 0; sampler_8x8[index].dw0.global_noise_estimation = 255; sampler_8x8[index].dw0.ief_bypass = 1; sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5; sampler_8x8[index].dw2.weak_edge_threshold = 1; sampler_8x8[index].dw2.strong_edge_threshold = 8; sampler_8x8[index].dw2.r5x_coefficient = 9; sampler_8x8[index].dw2.r5cx_coefficient = 8; sampler_8x8[index].dw2.r5c_coefficient = 3; sampler_8x8[index].dw3.r3x_coefficient = 27; sampler_8x8[index].dw3.r3c_coefficient = 5; sampler_8x8[index].dw3.gain_factor = 40; sampler_8x8[index].dw3.non_edge_weight = 1; sampler_8x8[index].dw3.regular_weight = 2; sampler_8x8[index].dw3.strong_edge_weight = 7; sampler_8x8[index].dw3.ief4_smooth_enable = 0; dri_bo_emit_reloc(pp_context->sampler_state_table.bo, I915_GEM_DOMAIN_RENDER, 0, 0, sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1), pp_context->sampler_state_table.bo_8x8); dri_bo_unmap(pp_context->sampler_state_table.bo); /* private function & data */ pp_context->pp_x_steps = gen7_pp_avs_x_steps; pp_context->pp_y_steps = gen7_pp_avs_y_steps; pp_context->private_context = &pp_context->pp_avs_context; pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter; pp_avs_context->dest_x = dst_rect->x; pp_avs_context->dest_y = dst_rect->y; pp_avs_context->dest_w = ALIGN(dst_rect->width, 16); pp_avs_context->dest_h = ALIGN(dst_rect->height, 16); pp_avs_context->src_w = src_rect->width; pp_avs_context->src_h = src_rect->height; pp_avs_context->horiz_range = (float)src_rect->width / src_width; int dw = (pp_avs_context->src_w - 1) / 16 + 1; dw = MAX(dw, dst_rect->width); pp_static_parameter->grf1.pointer_to_inline_parameter = 7; pp_static_parameter->grf2.avs_wa_enable = 1; /* must be set for GEN7 */ if (IS_HASWELL(i965->intel.device_id)) pp_static_parameter->grf2.avs_wa_enable = 0; /* HSW don't use the WA */ if (pp_static_parameter->grf2.avs_wa_enable) { int src_fourcc = pp_get_surface_fourcc(ctx, src_surface); if ((src_fourcc == VA_FOURCC('R', 'G', 'B', 'A')) || (src_fourcc == VA_FOURCC('R', 'G', 'B', 'X')) || (src_fourcc == VA_FOURCC('B', 'G', 'R', 'A')) || (src_fourcc == VA_FOURCC('B', 'G', 'R', 'X'))) { pp_static_parameter->grf2.avs_wa_enable = 0; } } pp_static_parameter->grf2.avs_wa_width = dw; pp_static_parameter->grf2.avs_wa_one_div_256_width = (float) 1.0 / (256 * dw); pp_static_parameter->grf2.avs_wa_five_div_256_width = (float) 5.0 / (256 * dw); pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw; pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) src_rect->height / src_height / dst_rect->height; pp_static_parameter->grf5.sampler_load_vertical_frame_origin = (float) src_rect->y / src_height - (float) pp_avs_context->dest_y * pp_static_parameter->grf4.sampler_load_vertical_scaling_step; pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = (float) src_rect->x / src_width - (float) pp_avs_context->dest_x * pp_avs_context->horiz_range / dw; gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface); dst_surface->flags = src_surface->flags; return VA_STATUS_SUCCESS; } static VAStatus gen8_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param) { /* TODO: Add the sampler_8x8 state */ struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->pp_avs_context; struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; struct gen8_sampler_8x8_avs *sampler_8x8; struct i965_sampler_8x8_coefficient *sampler_8x8_state; int i; int width[3], height[3], pitch[3], offset[3]; int src_width, src_height; unsigned char *cc_ptr; memset(pp_static_parameter, 0, sizeof(struct gen7_pp_static_parameter)); /* source surface */ gen8_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0, width, height, pitch, offset); src_height = height[0]; src_width = width[0]; /* destination surface */ gen8_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1, width, height, pitch, offset); /* sampler 8x8 state */ dri_bo_map(pp_context->dynamic_state.bo, True); assert(pp_context->dynamic_state.bo->virtual); cc_ptr = (unsigned char *) pp_context->dynamic_state.bo->virtual + pp_context->sampler_offset; /* Currently only one gen8 sampler_8x8 is initialized */ sampler_8x8 = (struct gen8_sampler_8x8_avs *)cc_ptr; memset(sampler_8x8, 0, sizeof(*sampler_8x8)); sampler_8x8->dw0.gain_factor = 44; sampler_8x8->dw0.weak_edge_threshold = 1; sampler_8x8->dw0.strong_edge_threshold = 8; /* Use the value like that on Ivy instead of default * sampler_8x8->dw0.r3x_coefficient = 5; */ sampler_8x8->dw0.r3x_coefficient = 27; sampler_8x8->dw0.r3c_coefficient = 5; sampler_8x8->dw2.global_noise_estimation = 255; sampler_8x8->dw2.non_edge_weight = 1; sampler_8x8->dw2.regular_weight = 2; sampler_8x8->dw2.strong_edge_weight = 7; /* Use the value like that on Ivy instead of default * sampler_8x8->dw2.r5x_coefficient = 7; * sampler_8x8->dw2.r5cx_coefficient = 7; * sampler_8x8->dw2.r5c_coefficient = 7; */ sampler_8x8->dw2.r5x_coefficient = 9; sampler_8x8->dw2.r5cx_coefficient = 8; sampler_8x8->dw2.r5c_coefficient = 3; sampler_8x8->dw3.sin_alpha = 101; /* sin_alpha = 0 */ sampler_8x8->dw3.cos_alpha = 79; /* cos_alpha = 0 */ sampler_8x8->dw3.sat_max = 0x1f; sampler_8x8->dw3.hue_max = 14; /* The 8tap filter will determine whether the adaptive Filter is * applied for all channels(dw153). * If the 8tap filter is disabled, the adaptive filter should be disabled. * Only when 8tap filter is enabled, it can be enabled or not */ sampler_8x8->dw3.enable_8tap_filter = 3; sampler_8x8->dw3.ief4_smooth_enable = 0; sampler_8x8->dw4.s3u = 0; sampler_8x8->dw4.diamond_margin = 4; sampler_8x8->dw4.vy_std_enable = 0; sampler_8x8->dw4.umid = 110; sampler_8x8->dw4.vmid = 154; sampler_8x8->dw5.diamond_dv = 0; sampler_8x8->dw5.diamond_th = 35; sampler_8x8->dw5.diamond_alpha = 100; /* diamond_alpha = 0 */ sampler_8x8->dw5.hs_margin = 3; sampler_8x8->dw5.diamond_du = 2; sampler_8x8->dw6.y_point1 = 46; sampler_8x8->dw6.y_point2 = 47; sampler_8x8->dw6.y_point3 = 254; sampler_8x8->dw6.y_point4 = 255; sampler_8x8->dw7.inv_margin_vyl = 3300; /* inv_margin_vyl = 0 */ sampler_8x8->dw8.inv_margin_vyu = 1600; /* inv_margin_vyu = 0 */ sampler_8x8->dw8.p0l = 46; sampler_8x8->dw8.p1l = 216; sampler_8x8->dw9.p2l = 236; sampler_8x8->dw9.p3l = 236; sampler_8x8->dw9.b0l = 133; sampler_8x8->dw9.b1l = 130; sampler_8x8->dw10.b2l = 130; sampler_8x8->dw10.b3l = 130; /* s0l = -5 / 256. s2.8 */ sampler_8x8->dw10.s0l = 1029; /* s0l = 0 */ sampler_8x8->dw10.y_slope2 = 31; /* y_slop2 = 0 */ sampler_8x8->dw11.s1l = 0; sampler_8x8->dw11.s2l = 0; sampler_8x8->dw12.s3l = 0; sampler_8x8->dw12.p0u = 46; sampler_8x8->dw12.p1u = 66; sampler_8x8->dw12.y_slope1 = 31; /* y_slope1 = 0 */ sampler_8x8->dw13.p2u = 130; sampler_8x8->dw13.p3u = 236; sampler_8x8->dw13.b0u = 143; sampler_8x8->dw13.b1u = 163; sampler_8x8->dw14.b2u = 200; sampler_8x8->dw14.b3u = 140; sampler_8x8->dw14.s0u = 256; /* s0u = 0 */ sampler_8x8->dw15.s1u = 113; /* s1u = 0 */ sampler_8x8->dw15.s2u = 1203; /* s2u = 0 */ sampler_8x8_state = sampler_8x8->coefficients; for (i = 0; i < 17; i++) { float coff; coff = i; coff = coff / 16; memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state)); /* for Y channel, currently ignore */ sampler_8x8_state->dw0.table_0x_filter_c0 = 0x0; sampler_8x8_state->dw0.table_0x_filter_c1 = 0x0; sampler_8x8_state->dw0.table_0x_filter_c2 = 0x0; sampler_8x8_state->dw0.table_0x_filter_c3 = intel_format_convert(1 - coff, 1, 6, 0); sampler_8x8_state->dw1.table_0x_filter_c4 = intel_format_convert(coff, 1, 6, 0); sampler_8x8_state->dw1.table_0x_filter_c5 = 0x0; sampler_8x8_state->dw1.table_0x_filter_c6 = 0x0; sampler_8x8_state->dw1.table_0x_filter_c7 = 0x0; sampler_8x8_state->dw2.table_0y_filter_c0 = 0x0; sampler_8x8_state->dw2.table_0y_filter_c1 = 0x0; sampler_8x8_state->dw2.table_0y_filter_c2 = 0x0; sampler_8x8_state->dw2.table_0y_filter_c3 = intel_format_convert(1 - coff, 1, 6, 0); sampler_8x8_state->dw3.table_0y_filter_c4 = intel_format_convert(coff, 1, 6, 0); sampler_8x8_state->dw3.table_0y_filter_c5 = 0x0; sampler_8x8_state->dw3.table_0y_filter_c6 = 0x0; sampler_8x8_state->dw3.table_0y_filter_c7 = 0x0; /* for U/V channel, 0.25 */ sampler_8x8_state->dw4.table_1x_filter_c0 = 0x0; sampler_8x8_state->dw4.table_1x_filter_c1 = 0x0; sampler_8x8_state->dw4.table_1x_filter_c2 = 0x0; sampler_8x8_state->dw4.table_1x_filter_c3 = intel_format_convert(1 - coff, 1, 6, 0); sampler_8x8_state->dw5.table_1x_filter_c4 = intel_format_convert(coff, 1, 6, 0); sampler_8x8_state->dw5.table_1x_filter_c5 = 0x00; sampler_8x8_state->dw5.table_1x_filter_c6 = 0x0; sampler_8x8_state->dw5.table_1x_filter_c7 = 0x0; sampler_8x8_state->dw6.table_1y_filter_c0 = 0x0; sampler_8x8_state->dw6.table_1y_filter_c1 = 0x0; sampler_8x8_state->dw6.table_1y_filter_c2 = 0x0; sampler_8x8_state->dw6.table_1y_filter_c3 = intel_format_convert(1 - coff, 1, 6, 0); sampler_8x8_state->dw7.table_1y_filter_c4 = intel_format_convert(coff, 1, 6,0); sampler_8x8_state->dw7.table_1y_filter_c5 = 0x0; sampler_8x8_state->dw7.table_1y_filter_c6 = 0x0; sampler_8x8_state->dw7.table_1y_filter_c7 = 0x0; sampler_8x8_state++; } sampler_8x8->dw152.default_sharpness_level = 0; sampler_8x8->dw153.adaptive_filter_for_all_channel = 1; sampler_8x8->dw153.bypass_y_adaptive_filtering = 1; sampler_8x8->dw153.bypass_x_adaptive_filtering = 1; dri_bo_unmap(pp_context->dynamic_state.bo); /* private function & data */ pp_context->pp_x_steps = gen7_pp_avs_x_steps; pp_context->pp_y_steps = gen7_pp_avs_y_steps; pp_context->private_context = &pp_context->pp_avs_context; pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter; pp_avs_context->dest_x = dst_rect->x; pp_avs_context->dest_y = dst_rect->y; pp_avs_context->dest_w = ALIGN(dst_rect->width, 16); pp_avs_context->dest_h = ALIGN(dst_rect->height, 16); pp_avs_context->src_w = src_rect->width; pp_avs_context->src_h = src_rect->height; pp_avs_context->horiz_range = (float)src_rect->width / src_width; int dw = (pp_avs_context->src_w - 1) / 16 + 1; dw = MAX(dw, dst_rect->width); pp_static_parameter->grf1.pointer_to_inline_parameter = 7; pp_static_parameter->grf2.avs_wa_enable = 0; /* It is not required on GEN8+ */ pp_static_parameter->grf2.avs_wa_width = src_width; pp_static_parameter->grf2.avs_wa_one_div_256_width = (float) 1.0 / (256 * src_width); pp_static_parameter->grf2.avs_wa_five_div_256_width = (float) 5.0 / (256 * src_width); pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw; pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) src_rect->height / src_height / dst_rect->height; pp_static_parameter->grf5.sampler_load_vertical_frame_origin = (float) src_rect->y / src_height - (float) pp_avs_context->dest_y * pp_static_parameter->grf4.sampler_load_vertical_scaling_step; pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = (float) src_rect->x / src_width - (float) pp_avs_context->dest_x * pp_avs_context->horiz_range / dw; gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface); dst_surface->flags = src_surface->flags; return VA_STATUS_SUCCESS; } static int pp_dndi_x_steps(void *private_context) { return 1; } static int pp_dndi_y_steps(void *private_context) { struct pp_dndi_context *pp_dndi_context = private_context; return pp_dndi_context->dest_h / 4; } static int pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y) { struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16; pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4; return 0; } static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->pp_dndi_context; struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; struct object_surface *obj_surface; struct i965_sampler_dndi *sampler_dndi; int index; int w, h; int orig_w, orig_h; int dndi_top_first = 1; VAProcFilterParameterBufferDeinterlacing *di_filter_param = (VAProcFilterParameterBufferDeinterlacing *)filter_param; if (di_filter_param->flags & VA_DEINTERLACING_BOTTOM_FIELD) dndi_top_first = 0; else dndi_top_first = 1; /* surface */ obj_surface = (struct object_surface *)src_surface->base; orig_w = obj_surface->orig_width; orig_h = obj_surface->orig_height; w = obj_surface->width; h = obj_surface->height; if (pp_dndi_context->stmm_bo == NULL) { pp_dndi_context->stmm_bo = dri_bo_alloc(i965->intel.bufmgr, "STMM surface", w * h, 4096); assert(pp_dndi_context->stmm_bo); } /* source UV surface index 2 */ i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, w * h, orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 2, 0); /* source YUV surface index 4 */ i965_pp_set_surface2_state(ctx, pp_context, obj_surface->bo, 0, orig_w, orig_h, w, 0, h, SURFACE_FORMAT_PLANAR_420_8, 1, 4); /* source STMM surface index 20 */ i965_pp_set_surface_state(ctx, pp_context, pp_dndi_context->stmm_bo, 0, orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 20, 1); /* destination surface */ obj_surface = (struct object_surface *)dst_surface->base; orig_w = obj_surface->orig_width; orig_h = obj_surface->orig_height; w = obj_surface->width; h = obj_surface->height; /* destination Y surface index 7 */ i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, 0, orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 7, 1); /* destination UV surface index 8 */ i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, w * h, orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 8, 1); /* sampler dndi */ dri_bo_map(pp_context->sampler_state_table.bo, True); assert(pp_context->sampler_state_table.bo->virtual); assert(sizeof(*sampler_dndi) == sizeof(int) * 8); sampler_dndi = pp_context->sampler_state_table.bo->virtual; /* sample dndi index 1 */ index = 0; sampler_dndi[index].dw0.denoise_asd_threshold = 38; sampler_dndi[index].dw0.denoise_history_delta = 7; // 0-15, default is 8 sampler_dndi[index].dw0.denoise_maximum_history = 192; // 128-240 sampler_dndi[index].dw0.denoise_stad_threshold = 140; sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 38; sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 1; sampler_dndi[index].dw1.stmm_c2 = 1; sampler_dndi[index].dw1.low_temporal_difference_threshold = 0; sampler_dndi[index].dw1.temporal_difference_threshold = 0; sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 20; // 0-31 sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 1; // 0-15 sampler_dndi[index].dw2.denoise_edge_threshold = 7; // 0-15 sampler_dndi[index].dw2.good_neighbor_threshold = 12; // 0-63 sampler_dndi[index].dw3.maximum_stmm = 150; sampler_dndi[index].dw3.multipler_for_vecm = 30; sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 125; sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64; sampler_dndi[index].dw3.stmm_blending_constant_select = 0; sampler_dndi[index].dw4.sdi_delta = 5; sampler_dndi[index].dw4.sdi_threshold = 100; sampler_dndi[index].dw4.stmm_output_shift = 5; // stmm_max - stmm_min = 2 ^ stmm_output_shift sampler_dndi[index].dw4.stmm_shift_up = 1; sampler_dndi[index].dw4.stmm_shift_down = 0; sampler_dndi[index].dw4.minimum_stmm = 118; sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 175; sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 37; sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 100; sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 50; sampler_dndi[index].dw6.dn_enable = 1; sampler_dndi[index].dw6.di_enable = 1; sampler_dndi[index].dw6.di_partial = 0; sampler_dndi[index].dw6.dndi_top_first = dndi_top_first; sampler_dndi[index].dw6.dndi_stream_id = 0; sampler_dndi[index].dw6.dndi_first_frame = 1; sampler_dndi[index].dw6.progressive_dn = 0; sampler_dndi[index].dw6.fmd_tear_threshold = 2; sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 100; sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 16; sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0; sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0; sampler_dndi[index].dw7.vdi_walker_enable = 0; sampler_dndi[index].dw7.column_width_minus1 = w / 16; dri_bo_unmap(pp_context->sampler_state_table.bo); /* private function & data */ pp_context->pp_x_steps = pp_dndi_x_steps; pp_context->pp_y_steps = pp_dndi_y_steps; pp_context->private_context = &pp_context->pp_dndi_context; pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter; pp_static_parameter->grf1.statistics_surface_picth = w / 2; pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first; pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0; pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0; pp_inline_parameter->grf5.block_count_x = w / 16; /* 1 x N */ pp_inline_parameter->grf5.number_blocks = w / 16; pp_inline_parameter->grf5.block_vertical_mask = 0xff; pp_inline_parameter->grf5.block_horizontal_mask = 0xffff; pp_dndi_context->dest_w = w; pp_dndi_context->dest_h = h; dst_surface->flags = I965_SURFACE_FLAG_FRAME; return VA_STATUS_SUCCESS; } static int pp_dn_x_steps(void *private_context) { return 1; } static int pp_dn_y_steps(void *private_context) { struct pp_dn_context *pp_dn_context = private_context; return pp_dn_context->dest_h / 8; } static int pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y) { struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16; pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8; return 0; } static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->pp_dn_context; struct object_surface *obj_surface; struct i965_sampler_dndi *sampler_dndi; struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */ int index; int w, h; int orig_w, orig_h; int dn_strength = 15; int dndi_top_first = 1; int dn_progressive = 0; if (src_surface->flags == I965_SURFACE_FLAG_FRAME) { dndi_top_first = 1; dn_progressive = 1; } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) { dndi_top_first = 1; dn_progressive = 0; } else { dndi_top_first = 0; dn_progressive = 0; } if (dn_filter_param) { float value = dn_filter_param->value; if (value > 1.0) value = 1.0; if (value < 0.0) value = 0.0; dn_strength = (int)(value * 31.0F); } /* surface */ obj_surface = (struct object_surface *)src_surface->base; orig_w = obj_surface->orig_width; orig_h = obj_surface->orig_height; w = obj_surface->width; h = obj_surface->height; if (pp_dn_context->stmm_bo == NULL) { pp_dn_context->stmm_bo = dri_bo_alloc(i965->intel.bufmgr, "STMM surface", w * h, 4096); assert(pp_dn_context->stmm_bo); } /* source UV surface index 2 */ i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, w * h, orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 2, 0); /* source YUV surface index 4 */ i965_pp_set_surface2_state(ctx, pp_context, obj_surface->bo, 0, orig_w, orig_h, w, 0, h, SURFACE_FORMAT_PLANAR_420_8, 1, 4); /* source STMM surface index 20 */ i965_pp_set_surface_state(ctx, pp_context, pp_dn_context->stmm_bo, 0, orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 20, 1); /* destination surface */ obj_surface = (struct object_surface *)dst_surface->base; orig_w = obj_surface->orig_width; orig_h = obj_surface->orig_height; w = obj_surface->width; h = obj_surface->height; /* destination Y surface index 7 */ i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, 0, orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 7, 1); /* destination UV surface index 8 */ i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, w * h, orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 8, 1); /* sampler dn */ dri_bo_map(pp_context->sampler_state_table.bo, True); assert(pp_context->sampler_state_table.bo->virtual); assert(sizeof(*sampler_dndi) == sizeof(int) * 8); sampler_dndi = pp_context->sampler_state_table.bo->virtual; /* sample dndi index 1 */ index = 0; sampler_dndi[index].dw0.denoise_asd_threshold = 0; sampler_dndi[index].dw0.denoise_history_delta = 8; // 0-15, default is 8 sampler_dndi[index].dw0.denoise_maximum_history = 128; // 128-240 sampler_dndi[index].dw0.denoise_stad_threshold = 0; sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64; sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0; sampler_dndi[index].dw1.stmm_c2 = 0; sampler_dndi[index].dw1.low_temporal_difference_threshold = 8; sampler_dndi[index].dw1.temporal_difference_threshold = 16; sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength; // 0-31 sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7; // 0-15 sampler_dndi[index].dw2.denoise_edge_threshold = 7; // 0-15 sampler_dndi[index].dw2.good_neighbor_threshold = 7; // 0-63 sampler_dndi[index].dw3.maximum_stmm = 128; sampler_dndi[index].dw3.multipler_for_vecm = 2; sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0; sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64; sampler_dndi[index].dw3.stmm_blending_constant_select = 0; sampler_dndi[index].dw4.sdi_delta = 8; sampler_dndi[index].dw4.sdi_threshold = 128; sampler_dndi[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift sampler_dndi[index].dw4.stmm_shift_up = 0; sampler_dndi[index].dw4.stmm_shift_down = 0; sampler_dndi[index].dw4.minimum_stmm = 0; sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0; sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0; sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0; sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0; sampler_dndi[index].dw6.dn_enable = 1; sampler_dndi[index].dw6.di_enable = 0; sampler_dndi[index].dw6.di_partial = 0; sampler_dndi[index].dw6.dndi_top_first = dndi_top_first; sampler_dndi[index].dw6.dndi_stream_id = 1; sampler_dndi[index].dw6.dndi_first_frame = 1; sampler_dndi[index].dw6.progressive_dn = dn_progressive; sampler_dndi[index].dw6.fmd_tear_threshold = 32; sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32; sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32; sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2; sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1; sampler_dndi[index].dw7.vdi_walker_enable = 0; sampler_dndi[index].dw7.column_width_minus1 = w / 16; dri_bo_unmap(pp_context->sampler_state_table.bo); /* private function & data */ pp_context->pp_x_steps = pp_dn_x_steps; pp_context->pp_y_steps = pp_dn_y_steps; pp_context->private_context = &pp_context->pp_dn_context; pp_context->pp_set_block_parameter = pp_dn_set_block_parameter; pp_static_parameter->grf1.statistics_surface_picth = w / 2; pp_static_parameter->grf1.r1_6.di.top_field_first = 0; pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64; pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192; pp_inline_parameter->grf5.block_count_x = w / 16; /* 1 x N */ pp_inline_parameter->grf5.number_blocks = w / 16; pp_inline_parameter->grf5.block_vertical_mask = 0xff; pp_inline_parameter->grf5.block_horizontal_mask = 0xffff; pp_dn_context->dest_w = w; pp_dn_context->dest_h = h; dst_surface->flags = src_surface->flags; return VA_STATUS_SUCCESS; } static int gen7_pp_dndi_x_steps(void *private_context) { struct pp_dndi_context *pp_dndi_context = private_context; return pp_dndi_context->dest_w / 16; } static int gen7_pp_dndi_y_steps(void *private_context) { struct pp_dndi_context *pp_dndi_context = private_context; return pp_dndi_context->dest_h / 4; } static int gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y) { struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16; pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4; return 0; } extern VAStatus vpp_surface_convert(VADriverContextP ctx, struct object_surface *src_obj_surf, struct object_surface *dst_obj_surf); static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->pp_dndi_context; struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; struct object_surface *previous_in_obj_surface, *current_in_obj_surface, *previous_out_obj_surface, *current_out_obj_surface; struct gen7_sampler_dndi *sampler_dndi; int index; int w, h; int orig_w, orig_h; int dndi_top_first = 1; VAProcFilterParameterBufferDeinterlacing *di_filter_param = (VAProcFilterParameterBufferDeinterlacing *)filter_param; int is_first_frame = (pp_dndi_context->frame_order == -1); if (di_filter_param->flags & VA_DEINTERLACING_BOTTOM_FIELD) dndi_top_first = 0; else dndi_top_first = 1; /* surface */ current_in_obj_surface = (struct object_surface *)src_surface->base; if (di_filter_param->algorithm == VAProcDeinterlacingBob) { previous_in_obj_surface = current_in_obj_surface; is_first_frame = 1; } else if (di_filter_param->algorithm == VAProcDeinterlacingMotionAdaptive) { if (pp_dndi_context->frame_order == 0) { VAProcPipelineParameterBuffer *pipeline_param = pp_context->pipeline_param; if (!pipeline_param || !pipeline_param->num_forward_references || pipeline_param->forward_references[0] == VA_INVALID_ID) { WARN_ONCE("A forward temporal reference is needed for Motion adaptive deinterlacing !!!\n"); return VA_STATUS_ERROR_INVALID_PARAMETER; } else { previous_in_obj_surface = SURFACE(pipeline_param->forward_references[0]); assert(previous_in_obj_surface && previous_in_obj_surface->bo); is_first_frame = 0; } } else if (pp_dndi_context->frame_order == 1) { vpp_surface_convert(ctx, pp_dndi_context->current_out_obj_surface, (struct object_surface *)dst_surface->base); pp_dndi_context->frame_order = (pp_dndi_context->frame_order + 1) % 2; is_first_frame = 0; return VA_STATUS_SUCCESS_1; } else { previous_in_obj_surface = current_in_obj_surface; is_first_frame = 1; } } else { return VA_STATUS_ERROR_UNIMPLEMENTED; } /* source (temporal reference) YUV surface index 4 */ orig_w = previous_in_obj_surface->orig_width; orig_h = previous_in_obj_surface->orig_height; w = previous_in_obj_surface->width; h = previous_in_obj_surface->height; gen7_pp_set_surface2_state(ctx, pp_context, previous_in_obj_surface->bo, 0, orig_w, orig_h, w, 0, h, SURFACE_FORMAT_PLANAR_420_8, 1, 4); /* source surface */ orig_w = current_in_obj_surface->orig_width; orig_h = current_in_obj_surface->orig_height; w = current_in_obj_surface->width; h = current_in_obj_surface->height; /* source UV surface index 1 */ gen7_pp_set_surface_state(ctx, pp_context, current_in_obj_surface->bo, w * h, orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 1, 0); /* source YUV surface index 3 */ gen7_pp_set_surface2_state(ctx, pp_context, current_in_obj_surface->bo, 0, orig_w, orig_h, w, 0, h, SURFACE_FORMAT_PLANAR_420_8, 1, 3); /* STMM / History Statistics input surface, index 5 */ if (pp_dndi_context->stmm_bo == NULL) { pp_dndi_context->stmm_bo = dri_bo_alloc(i965->intel.bufmgr, "STMM surface", w * h, 4096); assert(pp_dndi_context->stmm_bo); } gen7_pp_set_surface_state(ctx, pp_context, pp_dndi_context->stmm_bo, 0, orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 5, 1); /* destination surface */ previous_out_obj_surface = (struct object_surface *)dst_surface->base; orig_w = previous_out_obj_surface->orig_width; orig_h = previous_out_obj_surface->orig_height; w = previous_out_obj_surface->width; h = previous_out_obj_surface->height; if (is_first_frame) { current_out_obj_surface = previous_out_obj_surface; } else { VAStatus va_status; if (pp_dndi_context->current_out_surface == VA_INVALID_SURFACE) { unsigned int tiling = 0, swizzle = 0; dri_bo_get_tiling(previous_out_obj_surface->bo, &tiling, &swizzle); va_status = i965_CreateSurfaces(ctx, orig_w, orig_h, VA_RT_FORMAT_YUV420, 1, &pp_dndi_context->current_out_surface); assert(va_status == VA_STATUS_SUCCESS); pp_dndi_context->current_out_obj_surface = SURFACE(pp_dndi_context->current_out_surface); assert(pp_dndi_context->current_out_obj_surface); i965_check_alloc_surface_bo(ctx, pp_dndi_context->current_out_obj_surface, tiling != I915_TILING_NONE, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); } current_out_obj_surface = pp_dndi_context->current_out_obj_surface; } /* destination(Previous frame) Y surface index 27 */ gen7_pp_set_surface_state(ctx, pp_context, previous_out_obj_surface->bo, 0, orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 27, 1); /* destination(Previous frame) UV surface index 28 */ gen7_pp_set_surface_state(ctx, pp_context, previous_out_obj_surface->bo, w * h, orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 28, 1); /* destination(Current frame) Y surface index 30 */ gen7_pp_set_surface_state(ctx, pp_context, current_out_obj_surface->bo, 0, orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 30, 1); /* destination(Current frame) UV surface index 31 */ orig_w = current_out_obj_surface->orig_width; orig_h = current_out_obj_surface->orig_height; w = current_out_obj_surface->width; h = current_out_obj_surface->height; gen7_pp_set_surface_state(ctx, pp_context, current_out_obj_surface->bo, w * h, orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 31, 1); /* STMM output surface, index 33 */ gen7_pp_set_surface_state(ctx, pp_context, pp_dndi_context->stmm_bo, 0, orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 33, 1); /* sampler dndi */ dri_bo_map(pp_context->sampler_state_table.bo, True); assert(pp_context->sampler_state_table.bo->virtual); assert(sizeof(*sampler_dndi) == sizeof(int) * 8); sampler_dndi = pp_context->sampler_state_table.bo->virtual; /* sample dndi index 0 */ index = 0; sampler_dndi[index].dw0.denoise_asd_threshold = 38; sampler_dndi[index].dw0.dnmh_delt = 7; sampler_dndi[index].dw0.vdi_walker_y_stride = 0; sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0; sampler_dndi[index].dw0.denoise_maximum_history = 192; // 128-240 sampler_dndi[index].dw0.denoise_stad_threshold = 140; sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 38; sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 1; sampler_dndi[index].dw1.stmm_c2 = 2; sampler_dndi[index].dw1.low_temporal_difference_threshold = 0; sampler_dndi[index].dw1.temporal_difference_threshold = 0; sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 20; // 0-31 sampler_dndi[index].dw2.bne_edge_th = 1; sampler_dndi[index].dw2.smooth_mv_th = 0; sampler_dndi[index].dw2.sad_tight_th = 5; sampler_dndi[index].dw2.cat_slope_minus1 = 9; sampler_dndi[index].dw2.good_neighbor_th = 12; sampler_dndi[index].dw3.maximum_stmm = 150; sampler_dndi[index].dw3.multipler_for_vecm = 30; sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 125; sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64; sampler_dndi[index].dw3.stmm_blending_constant_select = 0; sampler_dndi[index].dw4.sdi_delta = 5; sampler_dndi[index].dw4.sdi_threshold = 100; sampler_dndi[index].dw4.stmm_output_shift = 5; // stmm_max - stmm_min = 2 ^ stmm_output_shift sampler_dndi[index].dw4.stmm_shift_up = 1; sampler_dndi[index].dw4.stmm_shift_down = 0; sampler_dndi[index].dw4.minimum_stmm = 118; sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 175; sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 37; sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 100; sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 50; sampler_dndi[index].dw6.dn_enable = 0; sampler_dndi[index].dw6.di_enable = 1; sampler_dndi[index].dw6.di_partial = 0; sampler_dndi[index].dw6.dndi_top_first = dndi_top_first; sampler_dndi[index].dw6.dndi_stream_id = 1; sampler_dndi[index].dw6.dndi_first_frame = is_first_frame; sampler_dndi[index].dw6.progressive_dn = 0; sampler_dndi[index].dw6.mcdi_enable = 0; sampler_dndi[index].dw6.fmd_tear_threshold = 2; sampler_dndi[index].dw6.cat_th1 = 0; sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 100; sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 16; sampler_dndi[index].dw7.sad_tha = 5; sampler_dndi[index].dw7.sad_thb = 10; sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0; sampler_dndi[index].dw7.mc_pixel_consistency_th = 25; sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0; sampler_dndi[index].dw7.vdi_walker_enable = 0; sampler_dndi[index].dw7.neighborpixel_th = 10; sampler_dndi[index].dw7.column_width_minus1 = w / 16; dri_bo_unmap(pp_context->sampler_state_table.bo); /* private function & data */ pp_context->pp_x_steps = gen7_pp_dndi_x_steps; pp_context->pp_y_steps = gen7_pp_dndi_y_steps; pp_context->private_context = &pp_context->pp_dndi_context; pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter; pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2; pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4; pp_static_parameter->grf1.di_top_field_first = 0; pp_static_parameter->grf1.pointer_to_inline_parameter = 7; pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0; pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1; pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3; pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0; pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0; pp_dndi_context->dest_w = w; pp_dndi_context->dest_h = h; dst_surface->flags = I965_SURFACE_FLAG_FRAME; pp_dndi_context->frame_order = (pp_dndi_context->frame_order + 1) % 2; return VA_STATUS_SUCCESS; } static int gen7_pp_dn_x_steps(void *private_context) { struct pp_dn_context *pp_dn_context = private_context; return pp_dn_context->dest_w / 16; } static int gen7_pp_dn_y_steps(void *private_context) { struct pp_dn_context *pp_dn_context = private_context; return pp_dn_context->dest_h / 4; } static int gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y) { struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16; pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4; return 0; } static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->pp_dn_context; struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter; struct object_surface *obj_surface; struct gen7_sampler_dndi *sampler_dn; VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */ int index; int w, h; int orig_w, orig_h; int dn_strength = 15; int dndi_top_first = 1; int dn_progressive = 0; if (src_surface->flags == I965_SURFACE_FLAG_FRAME) { dndi_top_first = 1; dn_progressive = 1; } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) { dndi_top_first = 1; dn_progressive = 0; } else { dndi_top_first = 0; dn_progressive = 0; } if (dn_filter_param) { float value = dn_filter_param->value; if (value > 1.0) value = 1.0; if (value < 0.0) value = 0.0; dn_strength = (int)(value * 31.0F); } /* surface */ obj_surface = (struct object_surface *)src_surface->base; orig_w = obj_surface->orig_width; orig_h = obj_surface->orig_height; w = obj_surface->width; h = obj_surface->height; if (pp_dn_context->stmm_bo == NULL) { pp_dn_context->stmm_bo= dri_bo_alloc(i965->intel.bufmgr, "STMM surface", w * h, 4096); assert(pp_dn_context->stmm_bo); } /* source UV surface index 1 */ gen7_pp_set_surface_state(ctx, pp_context, obj_surface->bo, w * h, orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 1, 0); /* source YUV surface index 3 */ gen7_pp_set_surface2_state(ctx, pp_context, obj_surface->bo, 0, orig_w, orig_h, w, 0, h, SURFACE_FORMAT_PLANAR_420_8, 1, 3); /* source (temporal reference) YUV surface index 4 */ gen7_pp_set_surface2_state(ctx, pp_context, obj_surface->bo, 0, orig_w, orig_h, w, 0, h, SURFACE_FORMAT_PLANAR_420_8, 1, 4); /* STMM / History Statistics input surface, index 5 */ gen7_pp_set_surface_state(ctx, pp_context, pp_dn_context->stmm_bo, 0, orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 33, 1); /* destination surface */ obj_surface = (struct object_surface *)dst_surface->base; orig_w = obj_surface->orig_width; orig_h = obj_surface->orig_height; w = obj_surface->width; h = obj_surface->height; /* destination Y surface index 24 */ gen7_pp_set_surface_state(ctx, pp_context, obj_surface->bo, 0, orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 24, 1); /* destination UV surface index 25 */ gen7_pp_set_surface_state(ctx, pp_context, obj_surface->bo, w * h, orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 25, 1); /* sampler dn */ dri_bo_map(pp_context->sampler_state_table.bo, True); assert(pp_context->sampler_state_table.bo->virtual); assert(sizeof(*sampler_dn) == sizeof(int) * 8); sampler_dn = pp_context->sampler_state_table.bo->virtual; /* sample dn index 1 */ index = 0; sampler_dn[index].dw0.denoise_asd_threshold = 0; sampler_dn[index].dw0.dnmh_delt = 8; sampler_dn[index].dw0.vdi_walker_y_stride = 0; sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0; sampler_dn[index].dw0.denoise_maximum_history = 128; // 128-240 sampler_dn[index].dw0.denoise_stad_threshold = 0; sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64; sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0; sampler_dn[index].dw1.stmm_c2 = 0; sampler_dn[index].dw1.low_temporal_difference_threshold = 8; sampler_dn[index].dw1.temporal_difference_threshold = 16; sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength; // 0-31 sampler_dn[index].dw2.bne_edge_th = 1; sampler_dn[index].dw2.smooth_mv_th = 0; sampler_dn[index].dw2.sad_tight_th = 5; sampler_dn[index].dw2.cat_slope_minus1 = 9; sampler_dn[index].dw2.good_neighbor_th = 4; sampler_dn[index].dw3.maximum_stmm = 128; sampler_dn[index].dw3.multipler_for_vecm = 2; sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0; sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64; sampler_dn[index].dw3.stmm_blending_constant_select = 0; sampler_dn[index].dw4.sdi_delta = 8; sampler_dn[index].dw4.sdi_threshold = 128; sampler_dn[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift sampler_dn[index].dw4.stmm_shift_up = 0; sampler_dn[index].dw4.stmm_shift_down = 0; sampler_dn[index].dw4.minimum_stmm = 0; sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0; sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0; sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0; sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0; sampler_dn[index].dw6.dn_enable = 1; sampler_dn[index].dw6.di_enable = 0; sampler_dn[index].dw6.di_partial = 0; sampler_dn[index].dw6.dndi_top_first = dndi_top_first; sampler_dn[index].dw6.dndi_stream_id = 1; sampler_dn[index].dw6.dndi_first_frame = 1; sampler_dn[index].dw6.progressive_dn = dn_progressive; sampler_dn[index].dw6.mcdi_enable = 0; sampler_dn[index].dw6.fmd_tear_threshold = 32; sampler_dn[index].dw6.cat_th1 = 0; sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32; sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32; sampler_dn[index].dw7.sad_tha = 5; sampler_dn[index].dw7.sad_thb = 10; sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2; sampler_dn[index].dw7.mc_pixel_consistency_th = 25; sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1; sampler_dn[index].dw7.vdi_walker_enable = 0; sampler_dn[index].dw7.neighborpixel_th = 10; sampler_dn[index].dw7.column_width_minus1 = w / 16; dri_bo_unmap(pp_context->sampler_state_table.bo); /* private function & data */ pp_context->pp_x_steps = gen7_pp_dn_x_steps; pp_context->pp_y_steps = gen7_pp_dn_y_steps; pp_context->private_context = &pp_context->pp_dn_context; pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter; pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2; pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4; pp_static_parameter->grf1.di_top_field_first = 0; pp_static_parameter->grf1.pointer_to_inline_parameter = 7; pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0; pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1; pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3; pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0; pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0; pp_dn_context->dest_w = w; pp_dn_context->dest_h = h; dst_surface->flags = src_surface->flags; return VA_STATUS_SUCCESS; } static VAStatus ironlake_pp_initialize( VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, int pp_index, void *filter_param ) { VAStatus va_status; struct i965_driver_data *i965 = i965_driver_data(ctx); struct pp_module *pp_module; dri_bo *bo; int static_param_size, inline_param_size; dri_bo_unreference(pp_context->surface_state_binding_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state & binding table", (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES, 4096); assert(bo); pp_context->surface_state_binding_table.bo = bo; dri_bo_unreference(pp_context->curbe.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "constant buffer", 4096, 4096); assert(bo); pp_context->curbe.bo = bo; dri_bo_unreference(pp_context->idrt.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "interface discriptor", sizeof(struct i965_interface_descriptor), 4096); assert(bo); pp_context->idrt.bo = bo; pp_context->idrt.num_interface_descriptors = 0; dri_bo_unreference(pp_context->sampler_state_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "sampler state table", 4096, 4096); assert(bo); dri_bo_map(bo, True); memset(bo->virtual, 0, bo->size); dri_bo_unmap(bo); pp_context->sampler_state_table.bo = bo; dri_bo_unreference(pp_context->sampler_state_table.bo_8x8); bo = dri_bo_alloc(i965->intel.bufmgr, "sampler 8x8 state ", 4096, 4096); assert(bo); pp_context->sampler_state_table.bo_8x8 = bo; dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv); bo = dri_bo_alloc(i965->intel.bufmgr, "sampler 8x8 state ", 4096, 4096); assert(bo); pp_context->sampler_state_table.bo_8x8_uv = bo; dri_bo_unreference(pp_context->vfe_state.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vfe state", sizeof(struct i965_vfe_state), 4096); assert(bo); pp_context->vfe_state.bo = bo; static_param_size = sizeof(struct pp_static_parameter); inline_param_size = sizeof(struct pp_inline_parameter); memset(pp_context->pp_static_parameter, 0, static_param_size); memset(pp_context->pp_inline_parameter, 0, inline_param_size); assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES); pp_context->current_pp = pp_index; pp_module = &pp_context->pp_modules[pp_index]; if (pp_module->initialize) va_status = pp_module->initialize(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, filter_param); else va_status = VA_STATUS_ERROR_UNIMPLEMENTED; return va_status; } static VAStatus ironlake_post_processing( VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, int pp_index, void *filter_param ) { VAStatus va_status; va_status = ironlake_pp_initialize(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param); if (va_status == VA_STATUS_SUCCESS) { ironlake_pp_states_setup(ctx, pp_context); ironlake_pp_pipeline_setup(ctx, pp_context); } return va_status; } static VAStatus gen6_pp_initialize( VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, int pp_index, void *filter_param ) { VAStatus va_status; struct i965_driver_data *i965 = i965_driver_data(ctx); struct pp_module *pp_module; dri_bo *bo; int static_param_size, inline_param_size; dri_bo_unreference(pp_context->surface_state_binding_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state & binding table", (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES, 4096); assert(bo); pp_context->surface_state_binding_table.bo = bo; dri_bo_unreference(pp_context->curbe.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "constant buffer", 4096, 4096); assert(bo); pp_context->curbe.bo = bo; dri_bo_unreference(pp_context->idrt.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "interface discriptor", sizeof(struct gen6_interface_descriptor_data), 4096); assert(bo); pp_context->idrt.bo = bo; pp_context->idrt.num_interface_descriptors = 0; dri_bo_unreference(pp_context->sampler_state_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "sampler state table", 4096, 4096); assert(bo); dri_bo_map(bo, True); memset(bo->virtual, 0, bo->size); dri_bo_unmap(bo); pp_context->sampler_state_table.bo = bo; dri_bo_unreference(pp_context->sampler_state_table.bo_8x8); bo = dri_bo_alloc(i965->intel.bufmgr, "sampler 8x8 state ", 4096, 4096); assert(bo); pp_context->sampler_state_table.bo_8x8 = bo; dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv); bo = dri_bo_alloc(i965->intel.bufmgr, "sampler 8x8 state ", 4096, 4096); assert(bo); pp_context->sampler_state_table.bo_8x8_uv = bo; dri_bo_unreference(pp_context->vfe_state.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "vfe state", sizeof(struct i965_vfe_state), 4096); assert(bo); pp_context->vfe_state.bo = bo; if (IS_GEN7(i965->intel.device_id)) { static_param_size = sizeof(struct gen7_pp_static_parameter); inline_param_size = sizeof(struct gen7_pp_inline_parameter); } else { static_param_size = sizeof(struct pp_static_parameter); inline_param_size = sizeof(struct pp_inline_parameter); } memset(pp_context->pp_static_parameter, 0, static_param_size); memset(pp_context->pp_inline_parameter, 0, inline_param_size); assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES); pp_context->current_pp = pp_index; pp_module = &pp_context->pp_modules[pp_index]; if (pp_module->initialize) va_status = pp_module->initialize(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, filter_param); else va_status = VA_STATUS_ERROR_UNIMPLEMENTED; calculate_boundary_block_mask(pp_context, dst_rect); return va_status; } static VAStatus gen8_pp_initialize( VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, int pp_index, void * filter_param ) { VAStatus va_status; struct i965_driver_data *i965 = i965_driver_data(ctx); dri_bo *bo; int bo_size; unsigned int end_offset; struct pp_module *pp_module; int static_param_size, inline_param_size; dri_bo_unreference(pp_context->surface_state_binding_table.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state & binding table", (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES, 4096); assert(bo); pp_context->surface_state_binding_table.bo = bo; pp_context->idrt.num_interface_descriptors = 0; pp_context->sampler_size = 2 * 4096; bo_size = 4096 + pp_context->curbe_size + pp_context->sampler_size + pp_context->idrt_size; dri_bo_unreference(pp_context->dynamic_state.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "dynamic_state", bo_size, 4096); assert(bo); pp_context->dynamic_state.bo = bo; pp_context->dynamic_state.bo_size = bo_size; end_offset = 0; pp_context->dynamic_state.end_offset = 0; /* Constant buffer offset */ pp_context->curbe_offset = ALIGN(end_offset, 64); end_offset = pp_context->curbe_offset + pp_context->curbe_size; /* Interface descriptor offset */ pp_context->idrt_offset = ALIGN(end_offset, 64); end_offset = pp_context->idrt_offset + pp_context->idrt_size; /* Sampler state offset */ pp_context->sampler_offset = ALIGN(end_offset, 64); end_offset = pp_context->sampler_offset + pp_context->sampler_size; /* update the end offset of dynamic_state */ pp_context->dynamic_state.end_offset = ALIGN(end_offset, 64); static_param_size = sizeof(struct gen7_pp_static_parameter); inline_param_size = sizeof(struct gen7_pp_inline_parameter); memset(pp_context->pp_static_parameter, 0, static_param_size); memset(pp_context->pp_inline_parameter, 0, inline_param_size); assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES); pp_context->current_pp = pp_index; pp_module = &pp_context->pp_modules[pp_index]; if (pp_module->initialize) va_status = pp_module->initialize(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, filter_param); else va_status = VA_STATUS_ERROR_UNIMPLEMENTED; calculate_boundary_block_mask(pp_context, dst_rect); return va_status; } static void gen6_pp_interface_descriptor_table(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct gen6_interface_descriptor_data *desc; dri_bo *bo; int pp_index = pp_context->current_pp; bo = pp_context->idrt.bo; dri_bo_map(bo, True); assert(bo->virtual); desc = bo->virtual; memset(desc, 0, sizeof(*desc)); desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */ desc->desc1.single_program_flow = 1; desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754; desc->desc2.sampler_count = 1; /* 1 - 4 samplers used */ desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5; desc->desc3.binding_table_entry_count = 0; desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5); desc->desc4.constant_urb_entry_read_offset = 0; if (IS_GEN7(i965->intel.device_id)) desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */ else desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, offsetof(struct gen6_interface_descriptor_data, desc0), pp_context->pp_modules[pp_index].kernel.bo); dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, desc->desc2.sampler_count << 2, offsetof(struct gen6_interface_descriptor_data, desc2), pp_context->sampler_state_table.bo); dri_bo_unmap(bo); pp_context->idrt.num_interface_descriptors++; } static void gen8_pp_interface_descriptor_table(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct gen8_interface_descriptor_data *desc; dri_bo *bo; int pp_index = pp_context->current_pp; unsigned char *cc_ptr; bo = pp_context->dynamic_state.bo; dri_bo_map(bo, 1); assert(bo->virtual); cc_ptr = (unsigned char *)bo->virtual + pp_context->idrt_offset; desc = (struct gen8_interface_descriptor_data *) cc_ptr + pp_context->idrt.num_interface_descriptors; memset(desc, 0, sizeof(*desc)); desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.kernel_offset >> 6; /* reloc */ desc->desc2.single_program_flow = 1; desc->desc2.floating_point_mode = FLOATING_POINT_IEEE_754; desc->desc3.sampler_count = 0; /* 1 - 4 samplers used */ desc->desc3.sampler_state_pointer = pp_context->sampler_offset >> 5; desc->desc4.binding_table_entry_count = 0; desc->desc4.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5); desc->desc5.constant_urb_entry_read_offset = 0; desc->desc5.constant_urb_entry_read_length = 6; /* grf 1-6 */ dri_bo_unmap(bo); pp_context->idrt.num_interface_descriptors++; } static void gen6_pp_upload_constants(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); unsigned char *constant_buffer; int param_size; assert(sizeof(struct pp_static_parameter) == 128); assert(sizeof(struct gen7_pp_static_parameter) == 192); if (IS_GEN7(i965->intel.device_id) || IS_GEN8(i965->intel.device_id)) param_size = sizeof(struct gen7_pp_static_parameter); else param_size = sizeof(struct pp_static_parameter); dri_bo_map(pp_context->curbe.bo, 1); assert(pp_context->curbe.bo->virtual); constant_buffer = pp_context->curbe.bo->virtual; memcpy(constant_buffer, pp_context->pp_static_parameter, param_size); dri_bo_unmap(pp_context->curbe.bo); } static void gen6_pp_states_setup(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { gen6_pp_interface_descriptor_table(ctx, pp_context); gen6_pp_upload_constants(ctx, pp_context); } static void gen8_pp_upload_constants(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { unsigned char *constant_buffer; int param_size; assert(sizeof(struct gen7_pp_static_parameter) == 192); param_size = sizeof(struct gen7_pp_static_parameter); dri_bo_map(pp_context->dynamic_state.bo, 1); assert(pp_context->dynamic_state.bo->virtual); constant_buffer = (unsigned char *) pp_context->dynamic_state.bo->virtual + pp_context->curbe_offset; memcpy(constant_buffer, pp_context->pp_static_parameter, param_size); dri_bo_unmap(pp_context->dynamic_state.bo); return; } static void gen8_pp_states_setup(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { gen8_pp_interface_descriptor_table(ctx, pp_context); gen8_pp_upload_constants(ctx, pp_context); } static void gen6_pp_pipeline_select(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; BEGIN_BATCH(batch, 1); OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); ADVANCE_BATCH(batch); } static void gen6_pp_state_base_address(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; BEGIN_BATCH(batch, 10); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2)); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */ OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); ADVANCE_BATCH(batch); } static void gen8_pp_state_base_address(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; BEGIN_BATCH(batch, 16); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (16 - 2)); /* DW1 Generate state address */ OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* DW4. Surface state address */ OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */ OUT_BATCH(batch, 0); /* DW6. Dynamic state address */ OUT_RELOC(batch, pp_context->dynamic_state.bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_SAMPLER, 0, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0); /* DW8. Indirect object address */ OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0); /* DW10. Instruction base address */ OUT_RELOC(batch, pp_context->instruction_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); ADVANCE_BATCH(batch); } static void gen6_pp_vfe_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; BEGIN_BATCH(batch, 8); OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, (pp_context->vfe_gpu_state.max_num_threads - 1) << 16 | pp_context->vfe_gpu_state.num_urb_entries << 8); OUT_BATCH(batch, 0); OUT_BATCH(batch, (pp_context->vfe_gpu_state.urb_entry_size) << 16 | /* URB Entry Allocation Size, in 256 bits unit */ (pp_context->vfe_gpu_state.curbe_allocation_size)); /* CURBE Allocation Size, in 256 bits unit */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen8_pp_vfe_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; BEGIN_BATCH(batch, 9); OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (9 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, (pp_context->vfe_gpu_state.max_num_threads - 1) << 16 | pp_context->vfe_gpu_state.num_urb_entries << 8); OUT_BATCH(batch, 0); OUT_BATCH(batch, (pp_context->vfe_gpu_state.urb_entry_size) << 16 | /* URB Entry Allocation Size, in 256 bits unit */ (pp_context->vfe_gpu_state.curbe_allocation_size)); /* CURBE Allocation Size, in 256 bits unit */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen6_pp_curbe_load(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; struct i965_driver_data *i965 = i965_driver_data(ctx); int param_size; if (IS_GEN7(i965->intel.device_id) || IS_GEN8(i965->intel.device_id)) param_size = sizeof(struct gen7_pp_static_parameter); else param_size = sizeof(struct pp_static_parameter); BEGIN_BATCH(batch, 4); OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, param_size); OUT_RELOC(batch, pp_context->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_BATCH(batch); } static void gen6_interface_descriptor_load(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; BEGIN_BATCH(batch, 4); OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data)); OUT_RELOC(batch, pp_context->idrt.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_BATCH(batch); } static void gen8_interface_descriptor_load(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; BEGIN_BATCH(batch, 4); OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, pp_context->idrt.num_interface_descriptors * sizeof(struct gen8_interface_descriptor_data)); OUT_BATCH(batch, pp_context->idrt_offset); ADVANCE_BATCH(batch); } static void update_block_mask_parameter(struct i965_post_processing_context *pp_context, int x, int y, int x_steps, int y_steps) { struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter; pp_inline_parameter->grf5.block_vertical_mask = 0xff; pp_inline_parameter->grf6.block_vertical_mask_bottom = pp_context->block_vertical_mask_bottom; // for the first block, it always on the left edge. the second block will reload horizontal_mask from grf6.block_horizontal_mask_middle pp_inline_parameter->grf5.block_horizontal_mask = pp_context->block_horizontal_mask_left; pp_inline_parameter->grf6.block_horizontal_mask_middle = 0xffff; pp_inline_parameter->grf6.block_horizontal_mask_right = pp_context->block_horizontal_mask_right; /* 1 x N */ if (x_steps == 1) { if (y == y_steps-1) { pp_inline_parameter->grf5.block_vertical_mask = pp_context->block_vertical_mask_bottom; } else { pp_inline_parameter->grf6.block_vertical_mask_bottom = 0xff; } } /* M x 1 */ if (y_steps == 1) { if (x == 0) { // all blocks in this group are on the left edge pp_inline_parameter->grf6.block_horizontal_mask_middle = pp_context->block_horizontal_mask_left; pp_inline_parameter->grf6.block_horizontal_mask_right = pp_context->block_horizontal_mask_left; } else if (x == x_steps-1) { pp_inline_parameter->grf5.block_horizontal_mask = pp_context->block_horizontal_mask_right; pp_inline_parameter->grf6.block_horizontal_mask_middle = pp_context->block_horizontal_mask_right; } else { pp_inline_parameter->grf5.block_horizontal_mask = 0xffff; pp_inline_parameter->grf6.block_horizontal_mask_middle = 0xffff; pp_inline_parameter->grf6.block_horizontal_mask_right = 0xffff; } } } static void gen6_pp_object_walker(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = pp_context->batch; int x, x_steps, y, y_steps; int param_size, command_length_in_dws; dri_bo *command_buffer; unsigned int *command_ptr; if (IS_GEN7(i965->intel.device_id) || IS_GEN8(i965->intel.device_id)) param_size = sizeof(struct gen7_pp_inline_parameter); else param_size = sizeof(struct pp_inline_parameter); x_steps = pp_context->pp_x_steps(pp_context->private_context); y_steps = pp_context->pp_y_steps(pp_context->private_context); command_length_in_dws = 6 + (param_size >> 2); command_buffer = dri_bo_alloc(i965->intel.bufmgr, "command objects buffer", command_length_in_dws * 4 * x_steps * y_steps + 8, 4096); dri_bo_map(command_buffer, 1); command_ptr = command_buffer->virtual; for (y = 0; y < y_steps; y++) { for (x = 0; x < x_steps; x++) { if (!pp_context->pp_set_block_parameter(pp_context, x, y)) { // some common block parameter update goes here, apply to all pp functions if (IS_GEN6(i965->intel.device_id)) update_block_mask_parameter (pp_context, x, y, x_steps, y_steps); *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2)); *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; memcpy(command_ptr, pp_context->pp_inline_parameter, param_size); command_ptr += (param_size >> 2); } } } if (command_length_in_dws * x_steps * y_steps % 2 == 0) *command_ptr++ = 0; *command_ptr = MI_BATCH_BUFFER_END; dri_bo_unmap(command_buffer); if (IS_GEN8(i965->intel.device_id)) { BEGIN_BATCH(batch, 3); OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0)); OUT_RELOC(batch, command_buffer, I915_GEM_DOMAIN_COMMAND, 0, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } else { BEGIN_BATCH(batch, 2); OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8)); OUT_RELOC(batch, command_buffer, I915_GEM_DOMAIN_COMMAND, 0, 0); ADVANCE_BATCH(batch); } dri_bo_unreference(command_buffer); /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END * will cause control to pass back to ring buffer */ intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); intel_batchbuffer_start_atomic(batch, 0x1000); } static void gen6_pp_pipeline_setup(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; intel_batchbuffer_start_atomic(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen6_pp_pipeline_select(ctx, pp_context); gen6_pp_state_base_address(ctx, pp_context); gen6_pp_vfe_state(ctx, pp_context); gen6_pp_curbe_load(ctx, pp_context); gen6_interface_descriptor_load(ctx, pp_context); gen6_pp_object_walker(ctx, pp_context); intel_batchbuffer_end_atomic(batch); } static void gen8_pp_curbe_load(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; struct i965_driver_data *i965 = i965_driver_data(ctx); int param_size = 64; if (IS_GEN8(i965->intel.device_id)) param_size = sizeof(struct gen7_pp_static_parameter); BEGIN_BATCH(batch, 4); OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, param_size); OUT_BATCH(batch, pp_context->curbe_offset); ADVANCE_BATCH(batch); } static void gen8_pp_object_walker(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = pp_context->batch; int x, x_steps, y, y_steps; int param_size, command_length_in_dws, extra_cmd_in_dws; dri_bo *command_buffer; unsigned int *command_ptr; param_size = sizeof(struct gen7_pp_inline_parameter); if (IS_GEN8(i965->intel.device_id)) param_size = sizeof(struct gen7_pp_inline_parameter); x_steps = pp_context->pp_x_steps(pp_context->private_context); y_steps = pp_context->pp_y_steps(pp_context->private_context); command_length_in_dws = 6 + (param_size >> 2); extra_cmd_in_dws = 2; command_buffer = dri_bo_alloc(i965->intel.bufmgr, "command objects buffer", (command_length_in_dws + extra_cmd_in_dws) * 4 * x_steps * y_steps + 64, 4096); dri_bo_map(command_buffer, 1); command_ptr = command_buffer->virtual; for (y = 0; y < y_steps; y++) { for (x = 0; x < x_steps; x++) { if (!pp_context->pp_set_block_parameter(pp_context, x, y)) { *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2)); *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; *command_ptr++ = 0; memcpy(command_ptr, pp_context->pp_inline_parameter, param_size); command_ptr += (param_size >> 2); *command_ptr++ = CMD_MEDIA_STATE_FLUSH; *command_ptr++ = 0; } } } if ((command_length_in_dws + extra_cmd_in_dws) * x_steps * y_steps % 2 == 0) *command_ptr++ = 0; *command_ptr++ = MI_BATCH_BUFFER_END; *command_ptr++ = 0; dri_bo_unmap(command_buffer); if (IS_GEN8(i965->intel.device_id)) { BEGIN_BATCH(batch, 3); OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0)); OUT_RELOC(batch, command_buffer, I915_GEM_DOMAIN_COMMAND, 0, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } dri_bo_unreference(command_buffer); /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END * will cause control to pass back to ring buffer */ intel_batchbuffer_end_atomic(batch); intel_batchbuffer_flush(batch); intel_batchbuffer_start_atomic(batch, 0x1000); } static void gen8_pp_pipeline_setup(VADriverContextP ctx, struct i965_post_processing_context *pp_context) { struct intel_batchbuffer *batch = pp_context->batch; intel_batchbuffer_start_atomic(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen6_pp_pipeline_select(ctx, pp_context); gen8_pp_state_base_address(ctx, pp_context); gen8_pp_vfe_state(ctx, pp_context); gen8_pp_curbe_load(ctx, pp_context); gen8_interface_descriptor_load(ctx, pp_context); gen8_pp_vfe_state(ctx, pp_context); gen8_pp_object_walker(ctx, pp_context); intel_batchbuffer_end_atomic(batch); } static VAStatus gen6_post_processing( VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, int pp_index, void *filter_param ) { VAStatus va_status; va_status = gen6_pp_initialize(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param); if (va_status == VA_STATUS_SUCCESS) { gen6_pp_states_setup(ctx, pp_context); gen6_pp_pipeline_setup(ctx, pp_context); } if (va_status == VA_STATUS_SUCCESS_1) va_status = VA_STATUS_SUCCESS; return va_status; } static VAStatus gen8_post_processing( VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, int pp_index, void * filter_param ) { VAStatus va_status; va_status = gen8_pp_initialize(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param); if (va_status == VA_STATUS_SUCCESS) { gen8_pp_states_setup(ctx, pp_context); gen8_pp_pipeline_setup(ctx, pp_context); } return va_status; } static VAStatus i965_post_processing_internal( VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, int pp_index, void *filter_param ) { VAStatus va_status; struct i965_driver_data *i965 = i965_driver_data(ctx); if (IS_GEN8(i965->intel.device_id)) va_status = gen8_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param); else if (IS_GEN6(i965->intel.device_id) || IS_GEN7(i965->intel.device_id)) va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param); else va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param); return va_status; } static void rgb_to_yuv(unsigned int argb, unsigned char *y, unsigned char *u, unsigned char *v, unsigned char *a) { int r = ((argb >> 16) & 0xff); int g = ((argb >> 8) & 0xff); int b = ((argb >> 0) & 0xff); *y = (257 * r + 504 * g + 98 * b) / 1000 + 16; *v = (439 * r - 368 * g - 71 * b) / 1000 + 128; *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128; *a = ((argb >> 24) & 0xff); } static void i965_vpp_clear_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context, struct object_surface *obj_surface, unsigned int color) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = pp_context->batch; unsigned int blt_cmd, br13; unsigned int tiling = 0, swizzle = 0; int pitch; unsigned char y, u, v, a = 0; int region_width, region_height; /* Currently only support NV12 surface */ if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) return; rgb_to_yuv(color, &y, &u, &v, &a); if (a == 0) return; dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); blt_cmd = XY_COLOR_BLT_CMD; pitch = obj_surface->width; if (tiling != I915_TILING_NONE) { assert(tiling == I915_TILING_Y); // blt_cmd |= XY_COLOR_BLT_DST_TILED; // pitch >>= 2; } br13 = 0xf0 << 16; br13 |= BR13_8; br13 |= pitch; if (IS_GEN6(i965->intel.device_id) || IS_GEN7(i965->intel.device_id) || IS_GEN8(i965->intel.device_id)) { intel_batchbuffer_start_atomic_blt(batch, 48); BEGIN_BLT_BATCH(batch, 12); } else { intel_batchbuffer_start_atomic(batch, 48); BEGIN_BATCH(batch, 12); } region_width = obj_surface->width; region_height = obj_surface->height; OUT_BATCH(batch, blt_cmd); OUT_BATCH(batch, br13); OUT_BATCH(batch, 0 << 16 | 0); OUT_BATCH(batch, region_height << 16 | region_width); OUT_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); OUT_BATCH(batch, y); br13 = 0xf0 << 16; br13 |= BR13_565; br13 |= pitch; region_width = obj_surface->width / 2; region_height = obj_surface->height / 2; if (tiling == I915_TILING_Y) { region_height = ALIGN(obj_surface->height / 2, 32); } OUT_BATCH(batch, blt_cmd); OUT_BATCH(batch, br13); OUT_BATCH(batch, 0 << 16 | 0); OUT_BATCH(batch, region_height << 16 | region_width); OUT_RELOC(batch, obj_surface->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, obj_surface->width * obj_surface->y_cb_offset); OUT_BATCH(batch, v << 8 | u); ADVANCE_BATCH(batch); intel_batchbuffer_end_atomic(batch); } VAStatus i965_scaling_processing( VADriverContextP ctx, struct object_surface *src_surface_obj, const VARectangle *src_rect, struct object_surface *dst_surface_obj, const VARectangle *dst_rect, unsigned int flags) { VAStatus va_status = VA_STATUS_SUCCESS; struct i965_driver_data *i965 = i965_driver_data(ctx); assert(src_surface_obj->fourcc == VA_FOURCC('N', 'V', '1', '2')); assert(dst_surface_obj->fourcc == VA_FOURCC('N', 'V', '1', '2')); if (HAS_PP(i965) && (flags & I965_PP_FLAG_AVS)) { struct i965_surface src_surface; struct i965_surface dst_surface; _i965LockMutex(&i965->pp_mutex); src_surface.base = (struct object_base *)src_surface_obj; src_surface.type = I965_SURFACE_TYPE_SURFACE; src_surface.flags = I965_SURFACE_FLAG_FRAME; dst_surface.base = (struct object_base *)dst_surface_obj; dst_surface.type = I965_SURFACE_TYPE_SURFACE; dst_surface.flags = I965_SURFACE_FLAG_FRAME; va_status = i965_post_processing_internal(ctx, i965->pp_context, &src_surface, src_rect, &dst_surface, dst_rect, PP_NV12_AVS, NULL); _i965UnlockMutex(&i965->pp_mutex); } return va_status; } VASurfaceID i965_post_processing( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect, unsigned int flags, int *has_done_scaling ) { struct i965_driver_data *i965 = i965_driver_data(ctx); VASurfaceID out_surface_id = VA_INVALID_ID; VASurfaceID tmp_id = VA_INVALID_ID; *has_done_scaling = 0; if (HAS_PP(i965)) { VAStatus status; struct i965_surface src_surface; struct i965_surface dst_surface; /* Currently only support post processing for NV12 surface */ if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) return out_surface_id; _i965LockMutex(&i965->pp_mutex); if (flags & I965_PP_FLAG_MCDI) { src_surface.base = (struct object_base *)obj_surface; src_surface.type = I965_SURFACE_TYPE_SURFACE; src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ? I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST; status = i965_CreateSurfaces(ctx, obj_surface->orig_width, obj_surface->orig_height, VA_RT_FORMAT_YUV420, 1, &out_surface_id); assert(status == VA_STATUS_SUCCESS); obj_surface = SURFACE(out_surface_id); assert(obj_surface); i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); i965_vpp_clear_surface(ctx, i965->pp_context, obj_surface, 0); dst_surface.base = (struct object_base *)obj_surface; dst_surface.type = I965_SURFACE_TYPE_SURFACE; dst_surface.flags = I965_SURFACE_FLAG_FRAME; i965_post_processing_internal(ctx, i965->pp_context, &src_surface, src_rect, &dst_surface, dst_rect, PP_NV12_DNDI, NULL); } if (flags & I965_PP_FLAG_AVS) { struct i965_render_state *render_state = &i965->render_state; struct intel_region *dest_region = render_state->draw_region; if (out_surface_id != VA_INVALID_ID) tmp_id = out_surface_id; src_surface.base = (struct object_base *)obj_surface; src_surface.type = I965_SURFACE_TYPE_SURFACE; src_surface.flags = I965_SURFACE_FLAG_FRAME; status = i965_CreateSurfaces(ctx, dest_region->width, dest_region->height, VA_RT_FORMAT_YUV420, 1, &out_surface_id); assert(status == VA_STATUS_SUCCESS); obj_surface = SURFACE(out_surface_id); assert(obj_surface); i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); i965_vpp_clear_surface(ctx, i965->pp_context, obj_surface, 0); dst_surface.base = (struct object_base *)obj_surface; dst_surface.type = I965_SURFACE_TYPE_SURFACE; dst_surface.flags = I965_SURFACE_FLAG_FRAME; i965_post_processing_internal(ctx, i965->pp_context, &src_surface, src_rect, &dst_surface, dst_rect, PP_NV12_AVS, NULL); if (tmp_id != VA_INVALID_ID) i965_DestroySurfaces(ctx, &tmp_id, 1); *has_done_scaling = 1; } _i965UnlockMutex(&i965->pp_mutex); } return out_surface_id; } static VAStatus i965_image_pl2_processing(VADriverContextP ctx, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect); static VAStatus i965_image_plx_nv12_plx_processing(VADriverContextP ctx, VAStatus (*i965_image_plx_nv12_processing)( VADriverContextP, const struct i965_surface *, const VARectangle *, struct i965_surface *, const VARectangle *), const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAStatus status; VASurfaceID tmp_surface_id = VA_INVALID_SURFACE; struct object_surface *obj_surface = NULL; struct i965_surface tmp_surface; int width, height; pp_get_surface_size(ctx, dst_surface, &width, &height); status = i965_CreateSurfaces(ctx, width, height, VA_RT_FORMAT_YUV420, 1, &tmp_surface_id); assert(status == VA_STATUS_SUCCESS); obj_surface = SURFACE(tmp_surface_id); assert(obj_surface); i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420); tmp_surface.base = (struct object_base *)obj_surface; tmp_surface.type = I965_SURFACE_TYPE_SURFACE; tmp_surface.flags = I965_SURFACE_FLAG_FRAME; status = i965_image_plx_nv12_processing(ctx, src_surface, src_rect, &tmp_surface, dst_rect); if (status == VA_STATUS_SUCCESS) status = i965_image_pl2_processing(ctx, &tmp_surface, dst_rect, dst_surface, dst_rect); i965_DestroySurfaces(ctx, &tmp_surface_id, 1); return status; } static VAStatus i965_image_pl1_rgbx_processing(VADriverContextP ctx, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_post_processing_context *pp_context = i965->pp_context; int fourcc = pp_get_surface_fourcc(ctx, dst_surface); VAStatus vaStatus; switch (fourcc) { case VA_FOURCC('N', 'V', '1', '2'): vaStatus = i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, PP_RGBX_LOAD_SAVE_NV12, NULL); intel_batchbuffer_flush(pp_context->batch); break; default: vaStatus = i965_image_plx_nv12_plx_processing(ctx, i965_image_pl1_rgbx_processing, src_surface, src_rect, dst_surface, dst_rect); break; } return vaStatus; } static VAStatus i965_image_pl3_processing(VADriverContextP ctx, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_post_processing_context *pp_context = i965->pp_context; int fourcc = pp_get_surface_fourcc(ctx, dst_surface); VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED; switch (fourcc) { case VA_FOURCC('N', 'V', '1', '2'): vaStatus = i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, PP_PL3_LOAD_SAVE_N12, NULL); intel_batchbuffer_flush(pp_context->batch); break; case VA_FOURCC('I', 'M', 'C', '1'): case VA_FOURCC('I', 'M', 'C', '3'): case VA_FOURCC('Y', 'V', '1', '2'): case VA_FOURCC('I', '4', '2', '0'): vaStatus = i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, PP_PL3_LOAD_SAVE_PL3, NULL); intel_batchbuffer_flush(pp_context->batch); break; case VA_FOURCC('Y', 'U', 'Y', '2'): case VA_FOURCC('U', 'Y', 'V', 'Y'): vaStatus = i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, PP_PL3_LOAD_SAVE_PA, NULL); intel_batchbuffer_flush(pp_context->batch); break; default: vaStatus = i965_image_plx_nv12_plx_processing(ctx, i965_image_pl3_processing, src_surface, src_rect, dst_surface, dst_rect); break; } return vaStatus; } static VAStatus i965_image_pl2_processing(VADriverContextP ctx, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_post_processing_context *pp_context = i965->pp_context; int fourcc = pp_get_surface_fourcc(ctx, dst_surface); VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED; switch (fourcc) { case VA_FOURCC('N', 'V', '1', '2'): vaStatus = i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, PP_NV12_LOAD_SAVE_N12, NULL); break; case VA_FOURCC('I', 'M', 'C', '1'): case VA_FOURCC('I', 'M', 'C', '3'): case VA_FOURCC('Y', 'V', '1', '2'): case VA_FOURCC('I', '4', '2', '0'): vaStatus = i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, PP_NV12_LOAD_SAVE_PL3, NULL); break; case VA_FOURCC('Y', 'U', 'Y', '2'): case VA_FOURCC('U', 'Y', 'V', 'Y'): vaStatus = i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, PP_NV12_LOAD_SAVE_PA, NULL); break; case VA_FOURCC('B', 'G', 'R', 'X'): case VA_FOURCC('B', 'G', 'R', 'A'): case VA_FOURCC('R', 'G', 'B', 'X'): case VA_FOURCC('R', 'G', 'B', 'A'): vaStatus = i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, PP_NV12_LOAD_SAVE_RGBX, NULL); break; default: return VA_STATUS_ERROR_UNIMPLEMENTED; } intel_batchbuffer_flush(pp_context->batch); return vaStatus; } static VAStatus i965_image_pl1_processing(VADriverContextP ctx, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_post_processing_context *pp_context = i965->pp_context; int fourcc = pp_get_surface_fourcc(ctx, dst_surface); VAStatus vaStatus; switch (fourcc) { case VA_FOURCC('N', 'V', '1', '2'): vaStatus = i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, PP_PA_LOAD_SAVE_NV12, NULL); intel_batchbuffer_flush(pp_context->batch); break; case VA_FOURCC('Y', 'V', '1', '2'): vaStatus = i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, PP_PA_LOAD_SAVE_PL3, NULL); intel_batchbuffer_flush(pp_context->batch); break; case VA_FOURCC('Y', 'U', 'Y', '2'): case VA_FOURCC('U', 'Y', 'V', 'Y'): vaStatus = i965_post_processing_internal(ctx, i965->pp_context, src_surface, src_rect, dst_surface, dst_rect, PP_PA_LOAD_SAVE_PA, NULL); intel_batchbuffer_flush(pp_context->batch); break; default: vaStatus = i965_image_plx_nv12_plx_processing(ctx, i965_image_pl1_processing, src_surface, src_rect, dst_surface, dst_rect); break; } return vaStatus; } VAStatus i965_image_processing(VADriverContextP ctx, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect) { struct i965_driver_data *i965 = i965_driver_data(ctx); VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED; if (HAS_PP(i965)) { int fourcc = pp_get_surface_fourcc(ctx, src_surface); _i965LockMutex(&i965->pp_mutex); switch (fourcc) { case VA_FOURCC('Y', 'V', '1', '2'): case VA_FOURCC('I', '4', '2', '0'): case VA_FOURCC('I', 'M', 'C', '1'): case VA_FOURCC('I', 'M', 'C', '3'): case VA_FOURCC('4', '2', '2', 'H'): case VA_FOURCC('4', '2', '2', 'V'): case VA_FOURCC('4', '1', '1', 'P'): case VA_FOURCC('4', '4', '4', 'P'): status = i965_image_pl3_processing(ctx, src_surface, src_rect, dst_surface, dst_rect); break; case VA_FOURCC('N', 'V', '1', '2'): status = i965_image_pl2_processing(ctx, src_surface, src_rect, dst_surface, dst_rect); break; case VA_FOURCC('Y', 'U', 'Y', '2'): case VA_FOURCC('U', 'Y', 'V', 'Y'): status = i965_image_pl1_processing(ctx, src_surface, src_rect, dst_surface, dst_rect); break; case VA_FOURCC('B', 'G', 'R', 'A'): case VA_FOURCC('B', 'G', 'R', 'X'): case VA_FOURCC('R', 'G', 'B', 'A'): case VA_FOURCC('R', 'G', 'B', 'X'): status = i965_image_pl1_rgbx_processing(ctx, src_surface, src_rect, dst_surface, dst_rect); break; default: status = VA_STATUS_ERROR_UNIMPLEMENTED; break; } _i965UnlockMutex(&i965->pp_mutex); } return status; } static void gen8_post_processing_context_finalize(struct i965_post_processing_context *pp_context) { dri_bo_unreference(pp_context->surface_state_binding_table.bo); pp_context->surface_state_binding_table.bo = NULL; dri_bo_unreference(pp_context->pp_dndi_context.stmm_bo); pp_context->pp_dndi_context.stmm_bo = NULL; dri_bo_unreference(pp_context->pp_dn_context.stmm_bo); pp_context->pp_dn_context.stmm_bo = NULL; if (pp_context->instruction_state.bo) { dri_bo_unreference(pp_context->instruction_state.bo); pp_context->instruction_state.bo = NULL; } if (pp_context->indirect_state.bo) { dri_bo_unreference(pp_context->indirect_state.bo); pp_context->indirect_state.bo = NULL; } if (pp_context->dynamic_state.bo) { dri_bo_unreference(pp_context->dynamic_state.bo); pp_context->dynamic_state.bo = NULL; } free(pp_context->pp_static_parameter); free(pp_context->pp_inline_parameter); pp_context->pp_static_parameter = NULL; pp_context->pp_inline_parameter = NULL; } static void i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context) { int i; dri_bo_unreference(pp_context->surface_state_binding_table.bo); pp_context->surface_state_binding_table.bo = NULL; dri_bo_unreference(pp_context->curbe.bo); pp_context->curbe.bo = NULL; dri_bo_unreference(pp_context->sampler_state_table.bo); pp_context->sampler_state_table.bo = NULL; dri_bo_unreference(pp_context->sampler_state_table.bo_8x8); pp_context->sampler_state_table.bo_8x8 = NULL; dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv); pp_context->sampler_state_table.bo_8x8_uv = NULL; dri_bo_unreference(pp_context->idrt.bo); pp_context->idrt.bo = NULL; pp_context->idrt.num_interface_descriptors = 0; dri_bo_unreference(pp_context->vfe_state.bo); pp_context->vfe_state.bo = NULL; dri_bo_unreference(pp_context->pp_dndi_context.stmm_bo); pp_context->pp_dndi_context.stmm_bo = NULL; dri_bo_unreference(pp_context->pp_dn_context.stmm_bo); pp_context->pp_dn_context.stmm_bo = NULL; for (i = 0; i < NUM_PP_MODULES; i++) { struct pp_module *pp_module = &pp_context->pp_modules[i]; dri_bo_unreference(pp_module->kernel.bo); pp_module->kernel.bo = NULL; } free(pp_context->pp_static_parameter); free(pp_context->pp_inline_parameter); pp_context->pp_static_parameter = NULL; pp_context->pp_inline_parameter = NULL; } void i965_post_processing_terminate(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_post_processing_context *pp_context = i965->pp_context; if (pp_context) { if (IS_GEN8(i965->intel.device_id)) { gen8_post_processing_context_finalize(pp_context); } else { i965_post_processing_context_finalize(pp_context); } free(pp_context); } i965->pp_context = NULL; } #define VPP_CURBE_ALLOCATION_SIZE 32 static void gen8_post_processing_context_init(VADriverContextP ctx, struct i965_post_processing_context *pp_context, struct intel_batchbuffer *batch) { struct i965_driver_data *i965 = i965_driver_data(ctx); int i, kernel_size; unsigned int kernel_offset, end_offset; unsigned char *kernel_ptr; struct pp_module *pp_module; { pp_context->vfe_gpu_state.max_num_threads = 60; pp_context->vfe_gpu_state.num_urb_entries = 59; pp_context->vfe_gpu_state.gpgpu_mode = 0; pp_context->vfe_gpu_state.urb_entry_size = 16 - 1; pp_context->vfe_gpu_state.curbe_allocation_size = VPP_CURBE_ALLOCATION_SIZE; } assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen8)); if (IS_GEN8(i965->intel.device_id)) memcpy(pp_context->pp_modules, pp_modules_gen8, sizeof(pp_context->pp_modules)); else { /* should never get here !!! */ assert(0); } kernel_size = 4096 ; for (i = 0; i < NUM_PP_MODULES; i++) { pp_module = &pp_context->pp_modules[i]; if (pp_module->kernel.bin && pp_module->kernel.size) { kernel_size += pp_module->kernel.size; } } pp_context->instruction_state.bo = dri_bo_alloc(i965->intel.bufmgr, "kernel shader", kernel_size, 0x1000); if (pp_context->instruction_state.bo == NULL) { WARN_ONCE("failure to allocate the buffer space for kernel shader in VPP\n"); return; } assert(pp_context->instruction_state.bo); pp_context->instruction_state.bo_size = kernel_size; pp_context->instruction_state.end_offset = 0; end_offset = 0; dri_bo_map(pp_context->instruction_state.bo, 1); kernel_ptr = (unsigned char *)(pp_context->instruction_state.bo->virtual); for (i = 0; i < NUM_PP_MODULES; i++) { pp_module = &pp_context->pp_modules[i]; kernel_offset = ALIGN(end_offset, 64); pp_module->kernel.kernel_offset = kernel_offset; if (pp_module->kernel.bin && pp_module->kernel.size) { memcpy(kernel_ptr + kernel_offset, pp_module->kernel.bin, pp_module->kernel.size); end_offset = kernel_offset + pp_module->kernel.size; } } pp_context->instruction_state.end_offset = ALIGN(end_offset, 64); dri_bo_unmap(pp_context->instruction_state.bo); /* static & inline parameters */ if (IS_GEN8(i965->intel.device_id)) { pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1); pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1); } pp_context->pp_dndi_context.current_out_surface = VA_INVALID_SURFACE; pp_context->pp_dndi_context.current_out_obj_surface = NULL; pp_context->pp_dndi_context.frame_order = -1; pp_context->batch = batch; pp_context->idrt_size = 5 * sizeof(struct gen8_interface_descriptor_data); pp_context->curbe_size = 256; } static void i965_post_processing_context_init(VADriverContextP ctx, struct i965_post_processing_context *pp_context, struct intel_batchbuffer *batch) { struct i965_driver_data *i965 = i965_driver_data(ctx); int i; if (IS_GEN8(i965->intel.device_id)) { gen8_post_processing_context_init(ctx, pp_context, batch); return; }; if (IS_IRONLAKE(i965->intel.device_id)) { pp_context->urb.size = URB_SIZE((&i965->intel)); pp_context->urb.num_vfe_entries = 32; pp_context->urb.size_vfe_entry = 1; /* in 512 bits unit */ pp_context->urb.num_cs_entries = 1; pp_context->urb.size_cs_entry = 2; pp_context->urb.vfe_start = 0; pp_context->urb.cs_start = pp_context->urb.vfe_start + pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry; assert(pp_context->urb.cs_start + pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel))); } else { pp_context->vfe_gpu_state.max_num_threads = 60; pp_context->vfe_gpu_state.num_urb_entries = 59; pp_context->vfe_gpu_state.gpgpu_mode = 0; pp_context->vfe_gpu_state.urb_entry_size = 16 - 1; pp_context->vfe_gpu_state.curbe_allocation_size = VPP_CURBE_ALLOCATION_SIZE; } assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5)); assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6)); assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7)); assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen75)); if (IS_HASWELL(i965->intel.device_id)) memcpy(pp_context->pp_modules, pp_modules_gen75, sizeof(pp_context->pp_modules)); else if (IS_GEN7(i965->intel.device_id)) memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules)); else if (IS_GEN6(i965->intel.device_id)) memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules)); else if (IS_IRONLAKE(i965->intel.device_id)) memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules)); for (i = 0; i < NUM_PP_MODULES; i++) { struct pp_module *pp_module = &pp_context->pp_modules[i]; dri_bo_unreference(pp_module->kernel.bo); if (pp_module->kernel.bin && pp_module->kernel.size) { pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr, pp_module->kernel.name, pp_module->kernel.size, 4096); assert(pp_module->kernel.bo); dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin); } else { pp_module->kernel.bo = NULL; } } /* static & inline parameters */ if (IS_GEN7(i965->intel.device_id) || IS_GEN8(i965->intel.device_id)) { pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1); pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1); } else { pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1); pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1); } pp_context->pp_dndi_context.current_out_surface = VA_INVALID_SURFACE; pp_context->pp_dndi_context.current_out_obj_surface = NULL; pp_context->pp_dndi_context.frame_order = -1; pp_context->batch = batch; } bool i965_post_processing_init(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_post_processing_context *pp_context = i965->pp_context; if (HAS_PP(i965)) { if (pp_context == NULL) { pp_context = calloc(1, sizeof(*pp_context)); i965_post_processing_context_init(ctx, pp_context, i965->pp_batch); i965->pp_context = pp_context; } } return true; } static const int procfilter_to_pp_flag[VAProcFilterCount] = { PP_NULL, /* VAProcFilterNone */ PP_NV12_DN, /* VAProcFilterNoiseReduction */ PP_NV12_DNDI, /* VAProcFilterDeinterlacing */ PP_NULL, /* VAProcFilterSharpening */ PP_NULL, /* VAProcFilterColorBalance */ }; static const int proc_frame_to_pp_frame[3] = { I965_SURFACE_FLAG_FRAME, I965_SURFACE_FLAG_TOP_FIELD_FIRST, I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST }; #define VA_STATUS_SUCCESS_1 0xFFFFFFFE VAStatus i965_proc_picture(VADriverContextP ctx, VAProfile profile, union codec_state *codec_state, struct hw_context *hw_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context; struct proc_state *proc_state = &codec_state->proc; VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer; struct object_surface *obj_surface; struct i965_surface src_surface, dst_surface; VARectangle src_rect, dst_rect; VAStatus status; int i; VASurfaceID tmp_surfaces[VAProcFilterCount + 4]; int num_tmp_surfaces = 0; unsigned int tiling = 0, swizzle = 0; int in_width, in_height; if (pipeline_param->surface == VA_INVALID_ID || proc_state->current_render_target == VA_INVALID_ID) { status = VA_STATUS_ERROR_INVALID_SURFACE; goto error; } obj_surface = SURFACE(pipeline_param->surface); if (!obj_surface) { status = VA_STATUS_ERROR_INVALID_SURFACE; goto error; } if (!obj_surface->bo) { status = VA_STATUS_ERROR_INVALID_VALUE; /* The input surface is created without valid content */ goto error; } if (pipeline_param->num_filters && !pipeline_param->filters) { status = VA_STATUS_ERROR_INVALID_PARAMETER; goto error; } in_width = obj_surface->orig_width; in_height = obj_surface->orig_height; dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle); src_surface.base = (struct object_base *)obj_surface; src_surface.type = I965_SURFACE_TYPE_SURFACE; src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3]; VASurfaceID out_surface_id = VA_INVALID_ID; if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) { src_surface.base = (struct object_base *)obj_surface; src_surface.type = I965_SURFACE_TYPE_SURFACE; src_surface.flags = I965_SURFACE_FLAG_FRAME; src_rect.x = 0; src_rect.y = 0; src_rect.width = in_width; src_rect.height = in_height; status = i965_CreateSurfaces(ctx, in_width, in_height, VA_RT_FORMAT_YUV420, 1, &out_surface_id); assert(status == VA_STATUS_SUCCESS); tmp_surfaces[num_tmp_surfaces++] = out_surface_id; obj_surface = SURFACE(out_surface_id); assert(obj_surface); i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420); dst_surface.base = (struct object_base *)obj_surface; dst_surface.type = I965_SURFACE_TYPE_SURFACE; dst_surface.flags = I965_SURFACE_FLAG_FRAME; dst_rect.x = 0; dst_rect.y = 0; dst_rect.width = in_width; dst_rect.height = in_height; status = i965_image_processing(ctx, &src_surface, &src_rect, &dst_surface, &dst_rect); assert(status == VA_STATUS_SUCCESS); src_surface.base = (struct object_base *)obj_surface; src_surface.type = I965_SURFACE_TYPE_SURFACE; src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3]; } if (pipeline_param->surface_region) { src_rect.x = pipeline_param->surface_region->x; src_rect.y = pipeline_param->surface_region->y; src_rect.width = pipeline_param->surface_region->width; src_rect.height = pipeline_param->surface_region->height; } else { src_rect.x = 0; src_rect.y = 0; src_rect.width = in_width; src_rect.height = in_height; } if (pipeline_param->output_region) { dst_rect.x = pipeline_param->output_region->x; dst_rect.y = pipeline_param->output_region->y; dst_rect.width = pipeline_param->output_region->width; dst_rect.height = pipeline_param->output_region->height; } else { dst_rect.x = 0; dst_rect.y = 0; dst_rect.width = in_width; dst_rect.height = in_height; } proc_context->pp_context.pipeline_param = pipeline_param; for (i = 0; i < pipeline_param->num_filters; i++) { struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]); VAProcFilterParameterBufferBase *filter_param = NULL; VAProcFilterType filter_type; int kernel_index; if (!obj_buffer || !obj_buffer->buffer_store || !obj_buffer->buffer_store->buffer) { status = VA_STATUS_ERROR_INVALID_FILTER_CHAIN; goto error; } out_surface_id = VA_INVALID_ID; filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer; filter_type = filter_param->type; kernel_index = procfilter_to_pp_flag[filter_type]; if (kernel_index != PP_NULL && proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) { status = i965_CreateSurfaces(ctx, in_width, in_height, VA_RT_FORMAT_YUV420, 1, &out_surface_id); assert(status == VA_STATUS_SUCCESS); tmp_surfaces[num_tmp_surfaces++] = out_surface_id; obj_surface = SURFACE(out_surface_id); assert(obj_surface); i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); dst_surface.base = (struct object_base *)obj_surface; dst_surface.type = I965_SURFACE_TYPE_SURFACE; status = i965_post_processing_internal(ctx, &proc_context->pp_context, &src_surface, &src_rect, &dst_surface, &src_rect, kernel_index, filter_param); if (status == VA_STATUS_SUCCESS) { src_surface.base = dst_surface.base; src_surface.type = dst_surface.type; src_surface.flags = dst_surface.flags; } } } proc_context->pp_context.pipeline_param = NULL; obj_surface = SURFACE(proc_state->current_render_target); if (!obj_surface) { status = VA_STATUS_ERROR_INVALID_SURFACE; goto error; } int csc_needed = 0; if (obj_surface->fourcc && obj_surface->fourcc != VA_FOURCC('N','V','1','2')){ csc_needed = 1; out_surface_id = VA_INVALID_ID; status = i965_CreateSurfaces(ctx, obj_surface->orig_width, obj_surface->orig_height, VA_RT_FORMAT_YUV420, 1, &out_surface_id); assert(status == VA_STATUS_SUCCESS); tmp_surfaces[num_tmp_surfaces++] = out_surface_id; struct object_surface *csc_surface = SURFACE(out_surface_id); assert(csc_surface); i965_check_alloc_surface_bo(ctx, csc_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); dst_surface.base = (struct object_base *)csc_surface; } else { i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); dst_surface.base = (struct object_base *)obj_surface; } dst_surface.type = I965_SURFACE_TYPE_SURFACE; i965_vpp_clear_surface(ctx, &proc_context->pp_context, obj_surface, pipeline_param->output_background_color); // load/save doesn't support different origin offset for src and dst surface if (src_rect.width == dst_rect.width && src_rect.height == dst_rect.height && src_rect.x == dst_rect.x && src_rect.y == dst_rect.y) { i965_post_processing_internal(ctx, &proc_context->pp_context, &src_surface, &src_rect, &dst_surface, &dst_rect, PP_NV12_LOAD_SAVE_N12, NULL); } else { i965_post_processing_internal(ctx, &proc_context->pp_context, &src_surface, &src_rect, &dst_surface, &dst_rect, (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ? PP_NV12_AVS : PP_NV12_SCALING, NULL); } if (csc_needed) { src_surface.base = dst_surface.base; src_surface.type = dst_surface.type; src_surface.flags = dst_surface.flags; dst_surface.base = (struct object_base *)obj_surface; dst_surface.type = I965_SURFACE_TYPE_SURFACE; i965_image_processing(ctx, &src_surface, &dst_rect, &dst_surface, &dst_rect); } if (num_tmp_surfaces) i965_DestroySurfaces(ctx, tmp_surfaces, num_tmp_surfaces); intel_batchbuffer_flush(hw_context->batch); return VA_STATUS_SUCCESS; error: if (num_tmp_surfaces) i965_DestroySurfaces(ctx, tmp_surfaces, num_tmp_surfaces); return status; } static void i965_proc_context_destroy(void *hw_context) { struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context; i965_post_processing_context_finalize(&proc_context->pp_context); intel_batchbuffer_free(proc_context->base.batch); free(proc_context); } struct hw_context * i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config) { struct intel_driver_data *intel = intel_driver_data(ctx); struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context)); proc_context->base.destroy = i965_proc_context_destroy; proc_context->base.run = i965_proc_picture; proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0); i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch); return (struct hw_context *)proc_context; } intel-driver-1.3.0/src/i965_post_processing.h000077500000000000000000000342611231401140700210560ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #ifndef __I965_POST_PROCESSING_H__ #define __I965_POST_PROCESSING_H__ #define MAX_PP_SURFACES 48 #define I965_PP_FLAG_TOP_FIELD 1 #define I965_PP_FLAG_BOTTOM_FIELD 2 #define I965_PP_FLAG_MCDI 4 #define I965_PP_FLAG_AVS 8 enum { PP_NULL = 0, PP_NV12_LOAD_SAVE_N12, PP_NV12_LOAD_SAVE_PL3, PP_PL3_LOAD_SAVE_N12, PP_PL3_LOAD_SAVE_PL3, PP_NV12_SCALING, PP_NV12_AVS, PP_NV12_DNDI, PP_NV12_DN, PP_NV12_LOAD_SAVE_PA, PP_PL3_LOAD_SAVE_PA, PP_PA_LOAD_SAVE_NV12, PP_PA_LOAD_SAVE_PL3, PP_PA_LOAD_SAVE_PA, PP_RGBX_LOAD_SAVE_NV12, PP_NV12_LOAD_SAVE_RGBX, NUM_PP_MODULES, }; struct i965_post_processing_context; struct pp_load_save_context { int dest_x; int dest_y; int dest_w; int dest_h; }; struct pp_scaling_context { int dest_x; /* in pixel */ int dest_y; /* in pixel */ int dest_w; int dest_h; float src_normalized_x; float src_normalized_y; }; struct pp_avs_context { int dest_x; /* in pixel */ int dest_y; /* in pixel */ int dest_w; int dest_h; float src_normalized_x; float src_normalized_y; int src_w; int src_h; float horiz_range; }; struct pp_dndi_context { int dest_w; int dest_h; dri_bo *stmm_bo; int frame_order; /* -1 for the first frame */ VASurfaceID current_out_surface; struct object_surface *current_out_obj_surface; }; struct pp_dn_context { int dest_w; int dest_h; dri_bo *stmm_bo; }; struct i965_post_processing_context; struct pp_module { struct i965_kernel kernel; /* others */ VAStatus (*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect, void *filter_param); }; struct pp_static_parameter { struct { /* Procamp r1.0 */ float procamp_constant_c0; /* Load and Same r1.1 */ unsigned int source_packed_y_offset:8; unsigned int source_packed_u_offset:8; unsigned int source_packed_v_offset:8; unsigned int source_rgb_layout:8; // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout union { /* Load and Save r1.2 */ struct { unsigned int destination_packed_y_offset:8; unsigned int destination_packed_u_offset:8; unsigned int destination_packed_v_offset:8; unsigned int pad0:8; } load_and_save; /* CSC r1.2 */ struct { unsigned int pad0:24; unsigned int destination_rgb_layout:8; // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout } csc; } r1_2; /* Procamp r1.3 */ float procamp_constant_c1; /* Procamp r1.4 */ float procamp_constant_c2; /* DI r1.5 */ unsigned int statistics_surface_picth:16; /* Devided by 2 */ unsigned int pad1:16; union { /* DI r1.6 */ struct { unsigned int pad0:24; unsigned int top_field_first:8; } di; /* AVS/Scaling r1.6 */ float normalized_video_y_scaling_step; } r1_6; /* Procamp r1.7 */ float procamp_constant_c5; } grf1; struct { /* Procamp r2.0 */ float procamp_constant_c3; /* MBZ r2.1*/ unsigned int pad0; /* WG+CSC r2.2 */ float wg_csc_constant_c4; /* WG+CSC r2.3 */ float wg_csc_constant_c8; /* Procamp r2.4 */ float procamp_constant_c4; /* MBZ r2.5 */ unsigned int pad1; /* MBZ r2.6 */ unsigned int pad2; /* WG+CSC r2.7 */ float wg_csc_constant_c9; } grf2; struct { /* WG+CSC r3.0 */ float wg_csc_constant_c0; /* Blending r3.1 */ float scaling_step_ratio; /* Blending r3.2 */ float normalized_alpha_y_scaling; /* WG+CSC r3.3 */ float wg_csc_constant_c4; /* WG+CSC r3.4 */ float wg_csc_constant_c1; /* ALL r3.5 */ int horizontal_origin_offset:16; int vertical_origin_offset:16; /* Shared r3.6*/ union { /* Color filll */ unsigned int color_pixel; /* WG+CSC */ float wg_csc_constant_c2; } r3_6; /* WG+CSC r3.7 */ float wg_csc_constant_c3; } grf3; struct { /* WG+CSC r4.0 */ float wg_csc_constant_c6; /* ALL r4.1 MBZ ???*/ unsigned int pad0; /* Shared r4.2 */ union { /* AVS */ struct { unsigned int pad1:15; unsigned int nlas:1; unsigned int pad2:16; } avs; /* DI */ struct { unsigned int motion_history_coefficient_m2:8; unsigned int motion_history_coefficient_m1:8; unsigned int pad0:16; } di; } r4_2; /* WG+CSC r4.3 */ float wg_csc_constant_c7; /* WG+CSC r4.4 */ float wg_csc_constant_c10; /* AVS r4.5 */ float source_video_frame_normalized_horizontal_origin; /* MBZ r4.6 */ unsigned int pad1; /* WG+CSC r4.7 */ float wg_csc_constant_c11; } grf4; }; struct pp_inline_parameter { struct { /* ALL r5.0 */ int destination_block_horizontal_origin:16; int destination_block_vertical_origin:16; /* Shared r5.1 */ union { /* AVS/Scaling */ float source_surface_block_normalized_horizontal_origin; /* FMD */ struct { unsigned int variance_surface_vertical_origin:16; unsigned int pad0:16; } fmd; } r5_1; /* AVS/Scaling r5.2 */ float source_surface_block_normalized_vertical_origin; /* Alpha r5.3 */ float alpha_surface_block_normalized_horizontal_origin; /* Alpha r5.4 */ float alpha_surface_block_normalized_vertical_origin; /* Alpha r5.5 */ unsigned int alpha_mask_x:16; unsigned int alpha_mask_y:8; unsigned int block_count_x:8; /* r5.6 */ /* we only support M*1 or 1*N block partitation now. * -- it means asm code only need update this mask from grf6 for the last block */ unsigned int block_horizontal_mask:16; unsigned int block_vertical_mask:8; unsigned int number_blocks:8; /* AVS/Scaling r5.7 */ float normalized_video_x_scaling_step; } grf5; struct { /* AVS r6.0 */ float video_step_delta; /* r6.1 */ // sizeof(int) == 4? unsigned int block_horizontal_mask_right:16; unsigned int block_vertical_mask_bottom:8; unsigned int pad1:8; /* r6.2 */ unsigned int block_horizontal_mask_middle:16; unsigned int pad2:16; /* r6.3-r6.7 */ unsigned int padx[5]; } grf6; }; struct gen7_pp_static_parameter { struct { /* r1.0-r1.5 */ unsigned int padx[6]; /* r1.6 */ unsigned int di_statistics_surface_pitch_div2:16; unsigned int di_statistics_surface_height_div4:16; /* r1.7 */ unsigned int di_top_field_first:8; unsigned int pad0:16; unsigned int pointer_to_inline_parameter:8; /* value: 7 */ } grf1; struct { /* r2.0 */ /* Indicates whether the rgb is swapped for the src surface * 0: RGBX(MSB. X-B-G-R). 1: BGRX(MSB: X-R-G-B) */ unsigned int src_avs_rgb_swap:1; unsigned int pad3:31; /* r2.1 */ unsigned int pad2:16; unsigned int save_avs_rgb_swap:1; /* 0: RGB, 1: BGR */ unsigned int avs_wa_enable:1; /* must enabled for GEN7 */ unsigned int ief_enable:1; unsigned int avs_wa_width:13; /* 2.2 */ float avs_wa_one_div_256_width; /* 2.3 */ float avs_wa_five_div_256_width; /* 2.4 - 2.6 */ unsigned int padx[3]; /* r2.7 */ unsigned int di_destination_packed_y_component_offset:8; unsigned int di_destination_packed_u_component_offset:8; unsigned int di_destination_packed_v_component_offset:8; unsigned int pad0:8; } grf2; struct { float sampler_load_horizontal_scaling_step_ratio; unsigned int padx[7]; } grf3; struct { float sampler_load_vertical_scaling_step; unsigned int pad0; unsigned int di_hoffset_svf_from_dvf:16; unsigned int di_voffset_svf_from_dvf:16; unsigned int padx[5]; } grf4; struct { float sampler_load_vertical_frame_origin; unsigned int padx[7]; } grf5; struct { float sampler_load_horizontal_frame_origin; unsigned int padx[7]; } grf6; }; struct gen7_pp_inline_parameter { struct { /* r7.0 */ unsigned int destination_block_horizontal_origin:16; unsigned int destination_block_vertical_origin:16; /* r7.1: 0xffffffff */ unsigned int constant_0; /* r7.2 */ unsigned int pad0; /* r7.3 */ unsigned int pad1; /* r7.4 */ float sampler_load_main_video_x_scaling_step; /* r7.5 */ unsigned int pad2; /* r7.6: must be zero */ unsigned int avs_vertical_block_number; /* r7.7: 0 */ unsigned int group_id_number; } grf7; struct { unsigned int padx[8]; } grf8; }; struct i965_post_processing_context { int current_pp; struct pp_module pp_modules[NUM_PP_MODULES]; void *pp_static_parameter; void *pp_inline_parameter; struct { dri_bo *bo; } surface_state_binding_table; struct { dri_bo *bo; } curbe; struct { dri_bo *bo; int num_interface_descriptors; } idrt; struct { dri_bo *bo; } vfe_state; struct { dri_bo *bo; dri_bo *bo_8x8; dri_bo *bo_8x8_uv; } sampler_state_table; struct { unsigned int size; unsigned int vfe_start; unsigned int cs_start; unsigned int num_vfe_entries; unsigned int num_cs_entries; unsigned int size_vfe_entry; unsigned int size_cs_entry; } urb; struct { unsigned int gpgpu_mode : 1; unsigned int pad0 : 7; unsigned int max_num_threads : 16; unsigned int num_urb_entries : 8; unsigned int urb_entry_size : 16; unsigned int curbe_allocation_size : 16; } vfe_gpu_state; struct pp_load_save_context pp_load_save_context; struct pp_scaling_context pp_scaling_context; struct pp_avs_context pp_avs_context; struct pp_dndi_context pp_dndi_context; struct pp_dn_context pp_dn_context; void *private_context; /* pointer to the current private context */ void *pipeline_param; /* pointer to the pipeline parameter */ int (*pp_x_steps)(void *private_context); int (*pp_y_steps)(void *private_context); int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y); struct intel_batchbuffer *batch; unsigned int block_horizontal_mask_left:16; unsigned int block_horizontal_mask_right:16; unsigned int block_vertical_mask_bottom:8; struct { dri_bo *bo; int bo_size; unsigned int end_offset; } instruction_state; struct { dri_bo *bo; } indirect_state; struct { dri_bo *bo; int bo_size; unsigned int end_offset; } dynamic_state; unsigned int sampler_offset; int sampler_size; unsigned int idrt_offset; int idrt_size; unsigned int curbe_offset; int curbe_size; }; struct i965_proc_context { struct hw_context base; struct i965_post_processing_context pp_context; }; VASurfaceID i965_post_processing( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect, unsigned int flags, int *has_done_scaling ); VAStatus i965_scaling_processing( VADriverContextP ctx, struct object_surface *src_surface_obj, const VARectangle *src_rect, struct object_surface *dst_surface_obj, const VARectangle *dst_rect, unsigned int flags ); VAStatus i965_image_processing(VADriverContextP ctx, const struct i965_surface *src_surface, const VARectangle *src_rect, struct i965_surface *dst_surface, const VARectangle *dst_rect); void i965_post_processing_terminate(VADriverContextP ctx); bool i965_post_processing_init(VADriverContextP ctx); #endif /* __I965_POST_PROCESSING_H__ */ intel-driver-1.3.0/src/i965_render.c000066400000000000000000004653351231401140700171160ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Eric Anholt * Keith Packard * Xiang Haihao * */ /* * Most of rendering codes are ported from xf86-video-intel/src/i965_video.c */ #include #include #include #include #include #include #include "intel_batchbuffer.h" #include "intel_driver.h" #include "i965_defines.h" #include "i965_drv_video.h" #include "i965_structs.h" #include "i965_render.h" #define SF_KERNEL_NUM_GRF 16 #define SF_MAX_THREADS 1 static const uint32_t sf_kernel_static[][4] = { #include "shaders/render/exa_sf.g4b" }; #define PS_KERNEL_NUM_GRF 48 #define PS_MAX_THREADS 32 #define I965_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1) static const uint32_t ps_kernel_static[][4] = { #include "shaders/render/exa_wm_xy.g4b" #include "shaders/render/exa_wm_src_affine.g4b" #include "shaders/render/exa_wm_src_sample_planar.g4b" #include "shaders/render/exa_wm_yuv_color_balance.g4b" #include "shaders/render/exa_wm_yuv_rgb.g4b" #include "shaders/render/exa_wm_write.g4b" }; static const uint32_t ps_subpic_kernel_static[][4] = { #include "shaders/render/exa_wm_xy.g4b" #include "shaders/render/exa_wm_src_affine.g4b" #include "shaders/render/exa_wm_src_sample_argb.g4b" #include "shaders/render/exa_wm_write.g4b" }; /* On IRONLAKE */ static const uint32_t sf_kernel_static_gen5[][4] = { #include "shaders/render/exa_sf.g4b.gen5" }; static const uint32_t ps_kernel_static_gen5[][4] = { #include "shaders/render/exa_wm_xy.g4b.gen5" #include "shaders/render/exa_wm_src_affine.g4b.gen5" #include "shaders/render/exa_wm_src_sample_planar.g4b.gen5" #include "shaders/render/exa_wm_yuv_color_balance.g4b.gen5" #include "shaders/render/exa_wm_yuv_rgb.g4b.gen5" #include "shaders/render/exa_wm_write.g4b.gen5" }; static const uint32_t ps_subpic_kernel_static_gen5[][4] = { #include "shaders/render/exa_wm_xy.g4b.gen5" #include "shaders/render/exa_wm_src_affine.g4b.gen5" #include "shaders/render/exa_wm_src_sample_argb.g4b.gen5" #include "shaders/render/exa_wm_write.g4b.gen5" }; /* programs for Sandybridge */ static const uint32_t sf_kernel_static_gen6[][4] = { }; static const uint32_t ps_kernel_static_gen6[][4] = { #include "shaders/render/exa_wm_src_affine.g6b" #include "shaders/render/exa_wm_src_sample_planar.g6b" #include "shaders/render/exa_wm_yuv_color_balance.g6b" #include "shaders/render/exa_wm_yuv_rgb.g6b" #include "shaders/render/exa_wm_write.g6b" }; static const uint32_t ps_subpic_kernel_static_gen6[][4] = { #include "shaders/render/exa_wm_src_affine.g6b" #include "shaders/render/exa_wm_src_sample_argb.g6b" #include "shaders/render/exa_wm_write.g6b" }; /* programs for Ivybridge */ static const uint32_t sf_kernel_static_gen7[][4] = { }; static const uint32_t ps_kernel_static_gen7[][4] = { #include "shaders/render/exa_wm_src_affine.g7b" #include "shaders/render/exa_wm_src_sample_planar.g7b" #include "shaders/render/exa_wm_yuv_color_balance.g7b" #include "shaders/render/exa_wm_yuv_rgb.g7b" #include "shaders/render/exa_wm_write.g7b" }; static const uint32_t ps_subpic_kernel_static_gen7[][4] = { #include "shaders/render/exa_wm_src_affine.g7b" #include "shaders/render/exa_wm_src_sample_argb.g7b" #include "shaders/render/exa_wm_write.g7b" }; /* Programs for Haswell */ static const uint32_t ps_kernel_static_gen7_haswell[][4] = { #include "shaders/render/exa_wm_src_affine.g7b" #include "shaders/render/exa_wm_src_sample_planar.g7b.haswell" #include "shaders/render/exa_wm_yuv_color_balance.g7b.haswell" #include "shaders/render/exa_wm_yuv_rgb.g7b" #include "shaders/render/exa_wm_write.g7b" }; /*TODO: Modify the shader for GEN8. * Now it only uses the shader for gen7/haswell */ /* Programs for Gen8 */ static const uint32_t sf_kernel_static_gen8[][4] = { }; static const uint32_t ps_kernel_static_gen8[][4] = { #include "shaders/render/exa_wm_src_affine.g8b" #include "shaders/render/exa_wm_src_sample_planar.g8b" #include "shaders/render/exa_wm_yuv_color_balance.g8b" #include "shaders/render/exa_wm_yuv_rgb.g8b" #include "shaders/render/exa_wm_write.g8b" }; static const uint32_t ps_subpic_kernel_static_gen8[][4] = { #include "shaders/render/exa_wm_src_affine.g8b" #include "shaders/render/exa_wm_src_sample_argb.g8b" #include "shaders/render/exa_wm_write.g8b" }; #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN8, \ MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)) #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) #define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_RENDER_SURFACES) static uint32_t float_to_uint (float f) { union { uint32_t i; float f; } x; x.f = f; return x.i; } enum { SF_KERNEL = 0, PS_KERNEL, PS_SUBPIC_KERNEL }; static struct i965_kernel render_kernels_gen4[] = { { "SF", SF_KERNEL, sf_kernel_static, sizeof(sf_kernel_static), NULL }, { "PS", PS_KERNEL, ps_kernel_static, sizeof(ps_kernel_static), NULL }, { "PS_SUBPIC", PS_SUBPIC_KERNEL, ps_subpic_kernel_static, sizeof(ps_subpic_kernel_static), NULL } }; static struct i965_kernel render_kernels_gen5[] = { { "SF", SF_KERNEL, sf_kernel_static_gen5, sizeof(sf_kernel_static_gen5), NULL }, { "PS", PS_KERNEL, ps_kernel_static_gen5, sizeof(ps_kernel_static_gen5), NULL }, { "PS_SUBPIC", PS_SUBPIC_KERNEL, ps_subpic_kernel_static_gen5, sizeof(ps_subpic_kernel_static_gen5), NULL } }; static struct i965_kernel render_kernels_gen6[] = { { "SF", SF_KERNEL, sf_kernel_static_gen6, sizeof(sf_kernel_static_gen6), NULL }, { "PS", PS_KERNEL, ps_kernel_static_gen6, sizeof(ps_kernel_static_gen6), NULL }, { "PS_SUBPIC", PS_SUBPIC_KERNEL, ps_subpic_kernel_static_gen6, sizeof(ps_subpic_kernel_static_gen6), NULL } }; static struct i965_kernel render_kernels_gen7[] = { { "SF", SF_KERNEL, sf_kernel_static_gen7, sizeof(sf_kernel_static_gen7), NULL }, { "PS", PS_KERNEL, ps_kernel_static_gen7, sizeof(ps_kernel_static_gen7), NULL }, { "PS_SUBPIC", PS_SUBPIC_KERNEL, ps_subpic_kernel_static_gen7, sizeof(ps_subpic_kernel_static_gen7), NULL } }; static struct i965_kernel render_kernels_gen7_haswell[] = { { "SF", SF_KERNEL, sf_kernel_static_gen7, sizeof(sf_kernel_static_gen7), NULL }, { "PS", PS_KERNEL, ps_kernel_static_gen7_haswell, sizeof(ps_kernel_static_gen7_haswell), NULL }, { "PS_SUBPIC", PS_SUBPIC_KERNEL, ps_subpic_kernel_static_gen7, sizeof(ps_subpic_kernel_static_gen7), NULL } }; static struct i965_kernel render_kernels_gen8[] = { { "SF", SF_KERNEL, sf_kernel_static_gen8, sizeof(sf_kernel_static_gen8), NULL }, { "PS", PS_KERNEL, ps_kernel_static_gen8, sizeof(ps_kernel_static_gen8), NULL }, { "PS_SUBPIC", PS_SUBPIC_KERNEL, ps_subpic_kernel_static_gen8, sizeof(ps_subpic_kernel_static_gen8), NULL } }; #define URB_VS_ENTRIES 8 #define URB_VS_ENTRY_SIZE 1 #define URB_GS_ENTRIES 0 #define URB_GS_ENTRY_SIZE 0 #define URB_CLIP_ENTRIES 0 #define URB_CLIP_ENTRY_SIZE 0 #define URB_SF_ENTRIES 1 #define URB_SF_ENTRY_SIZE 2 #define URB_CS_ENTRIES 4 #define URB_CS_ENTRY_SIZE 4 static float yuv_to_rgb_bt601[3][4] = { {1.164, 0, 1.596, -0.06275,}, {1.164, -0.392, -0.813, -0.50196,}, {1.164, 2.017, 0, -0.50196,}, }; static float yuv_to_rgb_bt709[3][4] = { {1.164, 0, 1.793, -0.06275,}, {1.164, -0.213, -0.533, -0.50196,}, {1.164, 2.112, 0, -0.50196,}, }; static float yuv_to_rgb_smpte_240[3][4] = { {1.164, 0, 1.794, -0.06275,}, {1.164, -0.258, -0.5425, -0.50196,}, {1.164, 2.078, 0, -0.50196,}, }; static void i965_render_vs_unit(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct i965_vs_unit_state *vs_state; dri_bo_map(render_state->vs.state, 1); assert(render_state->vs.state->virtual); vs_state = render_state->vs.state->virtual; memset(vs_state, 0, sizeof(*vs_state)); if (IS_IRONLAKE(i965->intel.device_id)) vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2; else vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES; vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1; vs_state->vs6.vs_enable = 0; vs_state->vs6.vert_cache_disable = 1; dri_bo_unmap(render_state->vs.state); } static void i965_render_sf_unit(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct i965_sf_unit_state *sf_state; dri_bo_map(render_state->sf.state, 1); assert(render_state->sf.state->virtual); sf_state = render_state->sf.state->virtual; memset(sf_state, 0, sizeof(*sf_state)); sf_state->thread0.grf_reg_count = I965_GRF_BLOCKS(SF_KERNEL_NUM_GRF); sf_state->thread0.kernel_start_pointer = render_state->render_kernels[SF_KERNEL].bo->offset >> 6; sf_state->sf1.single_program_flow = 1; /* XXX */ sf_state->sf1.binding_table_entry_count = 0; sf_state->sf1.thread_priority = 0; sf_state->sf1.floating_point_mode = 0; /* Mesa does this */ sf_state->sf1.illegal_op_exception_enable = 1; sf_state->sf1.mask_stack_exception_enable = 1; sf_state->sf1.sw_exception_enable = 1; /* scratch space is not used in our kernel */ sf_state->thread2.per_thread_scratch_space = 0; sf_state->thread2.scratch_space_base_pointer = 0; sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */ sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */ sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */ sf_state->thread3.urb_entry_read_offset = 0; sf_state->thread3.dispatch_grf_start_reg = 3; sf_state->thread4.max_threads = SF_MAX_THREADS - 1; sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1; sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES; sf_state->thread4.stats_enable = 1; sf_state->sf5.viewport_transform = 0; /* skip viewport */ sf_state->sf6.cull_mode = I965_CULLMODE_NONE; sf_state->sf6.scissor = 0; sf_state->sf7.trifan_pv = 2; sf_state->sf6.dest_org_vbias = 0x8; sf_state->sf6.dest_org_hbias = 0x8; dri_bo_emit_reloc(render_state->sf.state, I915_GEM_DOMAIN_INSTRUCTION, 0, sf_state->thread0.grf_reg_count << 1, offsetof(struct i965_sf_unit_state, thread0), render_state->render_kernels[SF_KERNEL].bo); dri_bo_unmap(render_state->sf.state); } static void i965_render_sampler(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct i965_sampler_state *sampler_state; int i; assert(render_state->wm.sampler_count > 0); assert(render_state->wm.sampler_count <= MAX_SAMPLERS); dri_bo_map(render_state->wm.sampler, 1); assert(render_state->wm.sampler->virtual); sampler_state = render_state->wm.sampler->virtual; for (i = 0; i < render_state->wm.sampler_count; i++) { memset(sampler_state, 0, sizeof(*sampler_state)); sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR; sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR; sampler_state->ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state->ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state->ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state++; } dri_bo_unmap(render_state->wm.sampler); } static void i965_subpic_render_wm_unit(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct i965_wm_unit_state *wm_state; assert(render_state->wm.sampler); dri_bo_map(render_state->wm.state, 1); assert(render_state->wm.state->virtual); wm_state = render_state->wm.state->virtual; memset(wm_state, 0, sizeof(*wm_state)); wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF); wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6; wm_state->thread1.single_program_flow = 1; /* XXX */ if (IS_IRONLAKE(i965->intel.device_id)) wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */ else wm_state->thread1.binding_table_entry_count = 7; wm_state->thread2.scratch_space_base_pointer = 0; wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */ wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */ wm_state->thread3.const_urb_entry_read_length = 4; wm_state->thread3.const_urb_entry_read_offset = 0; wm_state->thread3.urb_entry_read_length = 1; /* XXX */ wm_state->thread3.urb_entry_read_offset = 0; /* XXX */ wm_state->wm4.stats_enable = 0; wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5; if (IS_IRONLAKE(i965->intel.device_id)) { wm_state->wm4.sampler_count = 0; /* hardware requirement */ } else { wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4; } wm_state->wm5.max_threads = render_state->max_wm_threads - 1; wm_state->wm5.thread_dispatch_enable = 1; wm_state->wm5.enable_16_pix = 1; wm_state->wm5.enable_8_pix = 0; wm_state->wm5.early_depth_test = 1; dri_bo_emit_reloc(render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, wm_state->thread0.grf_reg_count << 1, offsetof(struct i965_wm_unit_state, thread0), render_state->render_kernels[PS_SUBPIC_KERNEL].bo); dri_bo_emit_reloc(render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, wm_state->wm4.sampler_count << 2, offsetof(struct i965_wm_unit_state, wm4), render_state->wm.sampler); dri_bo_unmap(render_state->wm.state); } static void i965_render_wm_unit(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct i965_wm_unit_state *wm_state; assert(render_state->wm.sampler); dri_bo_map(render_state->wm.state, 1); assert(render_state->wm.state->virtual); wm_state = render_state->wm.state->virtual; memset(wm_state, 0, sizeof(*wm_state)); wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF); wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_KERNEL].bo->offset >> 6; wm_state->thread1.single_program_flow = 1; /* XXX */ if (IS_IRONLAKE(i965->intel.device_id)) wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */ else wm_state->thread1.binding_table_entry_count = 7; wm_state->thread2.scratch_space_base_pointer = 0; wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */ wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */ wm_state->thread3.const_urb_entry_read_length = 4; wm_state->thread3.const_urb_entry_read_offset = 0; wm_state->thread3.urb_entry_read_length = 1; /* XXX */ wm_state->thread3.urb_entry_read_offset = 0; /* XXX */ wm_state->wm4.stats_enable = 0; wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5; if (IS_IRONLAKE(i965->intel.device_id)) { wm_state->wm4.sampler_count = 0; /* hardware requirement */ } else { wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4; } wm_state->wm5.max_threads = render_state->max_wm_threads - 1; wm_state->wm5.thread_dispatch_enable = 1; wm_state->wm5.enable_16_pix = 1; wm_state->wm5.enable_8_pix = 0; wm_state->wm5.early_depth_test = 1; dri_bo_emit_reloc(render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, wm_state->thread0.grf_reg_count << 1, offsetof(struct i965_wm_unit_state, thread0), render_state->render_kernels[PS_KERNEL].bo); dri_bo_emit_reloc(render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, wm_state->wm4.sampler_count << 2, offsetof(struct i965_wm_unit_state, wm4), render_state->wm.sampler); dri_bo_unmap(render_state->wm.state); } static void i965_render_cc_viewport(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct i965_cc_viewport *cc_viewport; dri_bo_map(render_state->cc.viewport, 1); assert(render_state->cc.viewport->virtual); cc_viewport = render_state->cc.viewport->virtual; memset(cc_viewport, 0, sizeof(*cc_viewport)); cc_viewport->min_depth = -1.e35; cc_viewport->max_depth = 1.e35; dri_bo_unmap(render_state->cc.viewport); } static void i965_subpic_render_cc_unit(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct i965_cc_unit_state *cc_state; assert(render_state->cc.viewport); dri_bo_map(render_state->cc.state, 1); assert(render_state->cc.state->virtual); cc_state = render_state->cc.state->virtual; memset(cc_state, 0, sizeof(*cc_state)); cc_state->cc0.stencil_enable = 0; /* disable stencil */ cc_state->cc2.depth_test = 0; /* disable depth test */ cc_state->cc2.logicop_enable = 0; /* disable logic op */ cc_state->cc3.ia_blend_enable = 0 ; /* blend alpha just like colors */ cc_state->cc3.blend_enable = 1; /* enable color blend */ cc_state->cc3.alpha_test = 0; /* disable alpha test */ cc_state->cc3.alpha_test_format = 0;//0:ALPHATEST_UNORM8; /*store alpha value with UNORM8 */ cc_state->cc3.alpha_test_func = 5;//COMPAREFUNCTION_LESS; /*pass if less than the reference */ cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5; cc_state->cc5.dither_enable = 0; /* disable dither */ cc_state->cc5.logicop_func = 0xc; /* WHITE */ cc_state->cc5.statistics_enable = 1; cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD; cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_DST_ALPHA; cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_DST_ALPHA; cc_state->cc6.clamp_post_alpha_blend = 0; cc_state->cc6.clamp_pre_alpha_blend =0; /*final color = src_color*src_blend_factor +/- dst_color*dest_color_blend_factor*/ cc_state->cc6.blend_function = I965_BLENDFUNCTION_ADD; cc_state->cc6.src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA; cc_state->cc6.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA; /*alpha test reference*/ cc_state->cc7.alpha_ref.f =0.0 ; dri_bo_emit_reloc(render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, offsetof(struct i965_cc_unit_state, cc4), render_state->cc.viewport); dri_bo_unmap(render_state->cc.state); } static void i965_render_cc_unit(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct i965_cc_unit_state *cc_state; assert(render_state->cc.viewport); dri_bo_map(render_state->cc.state, 1); assert(render_state->cc.state->virtual); cc_state = render_state->cc.state->virtual; memset(cc_state, 0, sizeof(*cc_state)); cc_state->cc0.stencil_enable = 0; /* disable stencil */ cc_state->cc2.depth_test = 0; /* disable depth test */ cc_state->cc2.logicop_enable = 1; /* enable logic op */ cc_state->cc3.ia_blend_enable = 0; /* blend alpha just like colors */ cc_state->cc3.blend_enable = 0; /* disable color blend */ cc_state->cc3.alpha_test = 0; /* disable alpha test */ cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5; cc_state->cc5.dither_enable = 0; /* disable dither */ cc_state->cc5.logicop_func = 0xc; /* WHITE */ cc_state->cc5.statistics_enable = 1; cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD; cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_ONE; cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_ONE; dri_bo_emit_reloc(render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, offsetof(struct i965_cc_unit_state, cc4), render_state->cc.viewport); dri_bo_unmap(render_state->cc.state); } static void i965_render_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss3.tiled_surface = 0; ss->ss3.tile_walk = 0; break; case I915_TILING_X: ss->ss3.tiled_surface = 1; ss->ss3.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss3.tiled_surface = 1; ss->ss3.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void i965_render_set_surface_state( struct i965_surface_state *ss, dri_bo *bo, unsigned long offset, unsigned int width, unsigned int height, unsigned int pitch, unsigned int format, unsigned int flags ) { unsigned int tiling; unsigned int swizzle; memset(ss, 0, sizeof(*ss)); switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) { case I965_PP_FLAG_BOTTOM_FIELD: ss->ss0.vert_line_stride_ofs = 1; /* fall-through */ case I965_PP_FLAG_TOP_FIELD: ss->ss0.vert_line_stride = 1; height /= 2; break; } ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = format; ss->ss0.color_blend = 1; ss->ss1.base_addr = bo->offset + offset; ss->ss2.width = width - 1; ss->ss2.height = height - 1; ss->ss3.pitch = pitch - 1; dri_bo_get_tiling(bo, &tiling, &swizzle); i965_render_set_surface_tiling(ss, tiling); } static void gen7_render_set_surface_tiling(struct gen7_surface_state *ss, uint32_t tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss0.tiled_surface = 0; ss->ss0.tile_walk = 0; break; case I915_TILING_X: ss->ss0.tiled_surface = 1; ss->ss0.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss0.tiled_surface = 1; ss->ss0.tile_walk = I965_TILEWALK_YMAJOR; break; } } static void gen8_render_set_surface_tiling(struct gen8_surface_state *ss, uint32_t tiling) { switch (tiling) { case I915_TILING_NONE: ss->ss0.tiled_surface = 0; ss->ss0.tile_walk = 0; break; case I915_TILING_X: ss->ss0.tiled_surface = 1; ss->ss0.tile_walk = I965_TILEWALK_XMAJOR; break; case I915_TILING_Y: ss->ss0.tiled_surface = 1; ss->ss0.tile_walk = I965_TILEWALK_YMAJOR; break; } } /* Set "Shader Channel Select" */ void gen7_render_set_surface_scs(struct gen7_surface_state *ss) { ss->ss7.shader_chanel_select_r = HSW_SCS_RED; ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN; ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE; ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA; } /* Set "Shader Channel Select" for GEN8+ */ void gen8_render_set_surface_scs(struct gen8_surface_state *ss) { ss->ss7.shader_chanel_select_r = HSW_SCS_RED; ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN; ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE; ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA; } static void gen7_render_set_surface_state( struct gen7_surface_state *ss, dri_bo *bo, unsigned long offset, int width, int height, int pitch, int format, unsigned int flags ) { unsigned int tiling; unsigned int swizzle; memset(ss, 0, sizeof(*ss)); switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) { case I965_PP_FLAG_BOTTOM_FIELD: ss->ss0.vert_line_stride_ofs = 1; /* fall-through */ case I965_PP_FLAG_TOP_FIELD: ss->ss0.vert_line_stride = 1; height /= 2; break; } ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = format; ss->ss1.base_addr = bo->offset + offset; ss->ss2.width = width - 1; ss->ss2.height = height - 1; ss->ss3.pitch = pitch - 1; dri_bo_get_tiling(bo, &tiling, &swizzle); gen7_render_set_surface_tiling(ss, tiling); } static void gen8_render_set_surface_state( struct gen8_surface_state *ss, dri_bo *bo, unsigned long offset, int width, int height, int pitch, int format, unsigned int flags ) { unsigned int tiling; unsigned int swizzle; memset(ss, 0, sizeof(*ss)); switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) { case I965_PP_FLAG_BOTTOM_FIELD: ss->ss0.vert_line_stride_ofs = 1; /* fall-through */ case I965_PP_FLAG_TOP_FIELD: ss->ss0.vert_line_stride = 1; height /= 2; break; } ss->ss0.surface_type = I965_SURFACE_2D; ss->ss0.surface_format = format; ss->ss8.base_addr = bo->offset + offset; ss->ss2.width = width - 1; ss->ss2.height = height - 1; ss->ss3.pitch = pitch - 1; /* Always set 1(align 4 mode) per B-spec */ ss->ss0.vertical_alignment = 1; ss->ss0.horizontal_alignment = 1; dri_bo_get_tiling(bo, &tiling, &swizzle); gen8_render_set_surface_tiling(ss, tiling); } static void i965_render_src_surface_state( VADriverContextP ctx, int index, dri_bo *region, unsigned long offset, int w, int h, int pitch, int format, unsigned int flags ) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; void *ss; dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo; assert(index < MAX_RENDER_SURFACES); dri_bo_map(ss_bo, 1); assert(ss_bo->virtual); ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index); if (IS_GEN8(i965->intel.device_id)) { gen8_render_set_surface_state(ss, region, offset, w, h, pitch, format, flags); gen8_render_set_surface_scs(ss); dri_bo_emit_reloc(ss_bo, I915_GEM_DOMAIN_SAMPLER, 0, offset, SURFACE_STATE_OFFSET(index) + offsetof(struct gen8_surface_state, ss8), region); } else if (IS_GEN7(i965->intel.device_id)) { gen7_render_set_surface_state(ss, region, offset, w, h, pitch, format, flags); if (IS_HASWELL(i965->intel.device_id)) gen7_render_set_surface_scs(ss); dri_bo_emit_reloc(ss_bo, I915_GEM_DOMAIN_SAMPLER, 0, offset, SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1), region); } else { i965_render_set_surface_state(ss, region, offset, w, h, pitch, format, flags); dri_bo_emit_reloc(ss_bo, I915_GEM_DOMAIN_SAMPLER, 0, offset, SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1), region); } ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index); dri_bo_unmap(ss_bo); render_state->wm.sampler_count++; } static void i965_render_src_surfaces_state( VADriverContextP ctx, struct object_surface *obj_surface, unsigned int flags ) { int region_pitch; int rw, rh; dri_bo *region; region_pitch = obj_surface->width; rw = obj_surface->orig_width; rh = obj_surface->orig_height; region = obj_surface->bo; i965_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); /* Y */ i965_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')) { i965_render_src_surface_state(ctx, 3, region, region_pitch * obj_surface->y_cb_offset, obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch, I965_SURFACEFORMAT_R8G8_UNORM, flags); /* UV */ i965_render_src_surface_state(ctx, 4, region, region_pitch * obj_surface->y_cb_offset, obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch, I965_SURFACEFORMAT_R8G8_UNORM, flags); } else { i965_render_src_surface_state(ctx, 3, region, region_pitch * obj_surface->y_cb_offset, obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); /* U */ i965_render_src_surface_state(ctx, 4, region, region_pitch * obj_surface->y_cb_offset, obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); i965_render_src_surface_state(ctx, 5, region, region_pitch * obj_surface->y_cr_offset, obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); /* V */ i965_render_src_surface_state(ctx, 6, region, region_pitch * obj_surface->y_cr_offset, obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); } } static void i965_subpic_render_src_surfaces_state(VADriverContextP ctx, struct object_surface *obj_surface) { dri_bo *subpic_region; unsigned int index = obj_surface->subpic_render_idx; struct object_subpic *obj_subpic = obj_surface->obj_subpic[index]; struct object_image *obj_image = obj_subpic->obj_image; assert(obj_surface); assert(obj_surface->bo); subpic_region = obj_image->bo; /*subpicture surface*/ i965_render_src_surface_state(ctx, 1, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0); i965_render_src_surface_state(ctx, 2, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0); } static void i965_render_dest_surface_state(VADriverContextP ctx, int index) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct intel_region *dest_region = render_state->draw_region; void *ss; dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo; int format; assert(index < MAX_RENDER_SURFACES); if (dest_region->cpp == 2) { format = I965_SURFACEFORMAT_B5G6R5_UNORM; } else { format = I965_SURFACEFORMAT_B8G8R8A8_UNORM; } dri_bo_map(ss_bo, 1); assert(ss_bo->virtual); ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index); if (IS_GEN8(i965->intel.device_id)) { gen8_render_set_surface_state(ss, dest_region->bo, 0, dest_region->width, dest_region->height, dest_region->pitch, format, 0); gen8_render_set_surface_scs(ss); dri_bo_emit_reloc(ss_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0, SURFACE_STATE_OFFSET(index) + offsetof(struct gen8_surface_state, ss8), dest_region->bo); } else if (IS_GEN7(i965->intel.device_id)) { gen7_render_set_surface_state(ss, dest_region->bo, 0, dest_region->width, dest_region->height, dest_region->pitch, format, 0); if (IS_HASWELL(i965->intel.device_id)) gen7_render_set_surface_scs(ss); dri_bo_emit_reloc(ss_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0, SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1), dest_region->bo); } else { i965_render_set_surface_state(ss, dest_region->bo, 0, dest_region->width, dest_region->height, dest_region->pitch, format, 0); dri_bo_emit_reloc(ss_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0, SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1), dest_region->bo); } ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index); dri_bo_unmap(ss_bo); } static void i965_fill_vertex_buffer( VADriverContextP ctx, float tex_coords[4], /* [(u1,v1);(u2,v2)] */ float vid_coords[4] /* [(x1,y1);(x2,y2)] */ ) { struct i965_driver_data * const i965 = i965_driver_data(ctx); float vb[12]; enum { X1, Y1, X2, Y2 }; static const unsigned int g_rotation_indices[][6] = { [VA_ROTATION_NONE] = { X2, Y2, X1, Y2, X1, Y1 }, [VA_ROTATION_90] = { X2, Y1, X2, Y2, X1, Y2 }, [VA_ROTATION_180] = { X1, Y1, X2, Y1, X2, Y2 }, [VA_ROTATION_270] = { X1, Y2, X1, Y1, X2, Y1 }, }; const unsigned int * const rotation_indices = g_rotation_indices[i965->rotation_attrib->value]; vb[0] = tex_coords[rotation_indices[0]]; /* bottom-right corner */ vb[1] = tex_coords[rotation_indices[1]]; vb[2] = vid_coords[X2]; vb[3] = vid_coords[Y2]; vb[4] = tex_coords[rotation_indices[2]]; /* bottom-left corner */ vb[5] = tex_coords[rotation_indices[3]]; vb[6] = vid_coords[X1]; vb[7] = vid_coords[Y2]; vb[8] = tex_coords[rotation_indices[4]]; /* top-left corner */ vb[9] = tex_coords[rotation_indices[5]]; vb[10] = vid_coords[X1]; vb[11] = vid_coords[Y1]; dri_bo_subdata(i965->render_state.vb.vertex_buffer, 0, sizeof(vb), vb); } static void i965_subpic_render_upload_vertex(VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *output_rect) { unsigned int index = obj_surface->subpic_render_idx; struct object_subpic *obj_subpic = obj_surface->obj_subpic[index]; float tex_coords[4], vid_coords[4]; VARectangle dst_rect; if (obj_subpic->flags & VA_SUBPICTURE_DESTINATION_IS_SCREEN_COORD) dst_rect = obj_subpic->dst_rect; else { const float sx = (float)output_rect->width / obj_surface->orig_width; const float sy = (float)output_rect->height / obj_surface->orig_height; dst_rect.x = output_rect->x + sx * obj_subpic->dst_rect.x; dst_rect.y = output_rect->y + sy * obj_subpic->dst_rect.y; dst_rect.width = sx * obj_subpic->dst_rect.width; dst_rect.height = sy * obj_subpic->dst_rect.height; } tex_coords[0] = (float)obj_subpic->src_rect.x / obj_subpic->width; tex_coords[1] = (float)obj_subpic->src_rect.y / obj_subpic->height; tex_coords[2] = (float)(obj_subpic->src_rect.x + obj_subpic->src_rect.width) / obj_subpic->width; tex_coords[3] = (float)(obj_subpic->src_rect.y + obj_subpic->src_rect.height) / obj_subpic->height; vid_coords[0] = dst_rect.x; vid_coords[1] = dst_rect.y; vid_coords[2] = (float)(dst_rect.x + dst_rect.width); vid_coords[3] = (float)(dst_rect.y + dst_rect.height); i965_fill_vertex_buffer(ctx, tex_coords, vid_coords); } static void i965_render_upload_vertex( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect ) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct intel_region *dest_region = render_state->draw_region; float tex_coords[4], vid_coords[4]; int width, height; width = obj_surface->orig_width; height = obj_surface->orig_height; tex_coords[0] = (float)src_rect->x / width; tex_coords[1] = (float)src_rect->y / height; tex_coords[2] = (float)(src_rect->x + src_rect->width) / width; tex_coords[3] = (float)(src_rect->y + src_rect->height) / height; vid_coords[0] = dest_region->x + dst_rect->x; vid_coords[1] = dest_region->y + dst_rect->y; vid_coords[2] = vid_coords[0] + dst_rect->width; vid_coords[3] = vid_coords[1] + dst_rect->height; i965_fill_vertex_buffer(ctx, tex_coords, vid_coords); } #define PI 3.1415926 static void i965_render_upload_constants(VADriverContextP ctx, struct object_surface *obj_surface, unsigned int flags) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; unsigned short *constant_buffer; float *color_balance_base; float contrast = (float)i965->contrast_attrib->value / DEFAULT_CONTRAST; float brightness = (float)i965->brightness_attrib->value / 255; /* YUV is float in the shader */ float hue = (float)i965->hue_attrib->value / 180 * PI; float saturation = (float)i965->saturation_attrib->value / DEFAULT_SATURATION; float *yuv_to_rgb; unsigned int color_flag; dri_bo_map(render_state->curbe.bo, 1); assert(render_state->curbe.bo->virtual); constant_buffer = render_state->curbe.bo->virtual; if (obj_surface->subsampling == SUBSAMPLE_YUV400) { assert(obj_surface->fourcc == VA_FOURCC('Y', '8', '0', '0')); constant_buffer[0] = 2; } else { if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')) constant_buffer[0] = 1; else constant_buffer[0] = 0; } if (i965->contrast_attrib->value == DEFAULT_CONTRAST && i965->brightness_attrib->value == DEFAULT_BRIGHTNESS && i965->hue_attrib->value == DEFAULT_HUE && i965->saturation_attrib->value == DEFAULT_SATURATION) constant_buffer[1] = 1; /* skip color balance transformation */ else constant_buffer[1] = 0; color_balance_base = (float *)constant_buffer + 4; *color_balance_base++ = contrast; *color_balance_base++ = brightness; *color_balance_base++ = cos(hue) * contrast * saturation; *color_balance_base++ = sin(hue) * contrast * saturation; color_flag = flags & VA_SRC_COLOR_MASK; yuv_to_rgb = (float *)constant_buffer + 8; if (color_flag == VA_SRC_BT709) memcpy(yuv_to_rgb, yuv_to_rgb_bt709, sizeof(yuv_to_rgb_bt709)); else if (color_flag == VA_SRC_SMPTE_240) memcpy(yuv_to_rgb, yuv_to_rgb_smpte_240, sizeof(yuv_to_rgb_smpte_240)); else memcpy(yuv_to_rgb, yuv_to_rgb_bt601, sizeof(yuv_to_rgb_bt601)); dri_bo_unmap(render_state->curbe.bo); } static void i965_subpic_render_upload_constants(VADriverContextP ctx, struct object_surface *obj_surface) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; float *constant_buffer; float global_alpha = 1.0; unsigned int index = obj_surface->subpic_render_idx; struct object_subpic *obj_subpic = obj_surface->obj_subpic[index]; if (obj_subpic->flags & VA_SUBPICTURE_GLOBAL_ALPHA) { global_alpha = obj_subpic->global_alpha; } dri_bo_map(render_state->curbe.bo, 1); assert(render_state->curbe.bo->virtual); constant_buffer = render_state->curbe.bo->virtual; *constant_buffer = global_alpha; dri_bo_unmap(render_state->curbe.bo); } static void i965_surface_render_state_setup( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect, unsigned int flags ) { i965_render_vs_unit(ctx); i965_render_sf_unit(ctx); i965_render_dest_surface_state(ctx, 0); i965_render_src_surfaces_state(ctx, obj_surface, flags); i965_render_sampler(ctx); i965_render_wm_unit(ctx); i965_render_cc_viewport(ctx); i965_render_cc_unit(ctx); i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect); i965_render_upload_constants(ctx, obj_surface, flags); } static void i965_subpic_render_state_setup( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect ) { i965_render_vs_unit(ctx); i965_render_sf_unit(ctx); i965_render_dest_surface_state(ctx, 0); i965_subpic_render_src_surfaces_state(ctx, obj_surface); i965_render_sampler(ctx); i965_subpic_render_wm_unit(ctx); i965_render_cc_viewport(ctx); i965_subpic_render_cc_unit(ctx); i965_subpic_render_upload_constants(ctx, obj_surface); i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect); } static void i965_render_pipeline_select(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 1); OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D); ADVANCE_BATCH(batch); } static void i965_render_state_sip(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, CMD_STATE_SIP | 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void i965_render_state_base_address(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; if (IS_IRONLAKE(i965->intel.device_id)) { BEGIN_BATCH(batch, 8); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); ADVANCE_BATCH(batch); } else { BEGIN_BATCH(batch, 6); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY); ADVANCE_BATCH(batch); } } static void i965_render_binding_table_pointers(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 6); OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS | 4); OUT_BATCH(batch, 0); /* vs */ OUT_BATCH(batch, 0); /* gs */ OUT_BATCH(batch, 0); /* clip */ OUT_BATCH(batch, 0); /* sf */ OUT_BATCH(batch, BINDING_TABLE_OFFSET); ADVANCE_BATCH(batch); } static void i965_render_constant_color(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 5); OUT_BATCH(batch, CMD_CONSTANT_COLOR | 3); OUT_BATCH(batch, float_to_uint(1.0)); OUT_BATCH(batch, float_to_uint(0.0)); OUT_BATCH(batch, float_to_uint(1.0)); OUT_BATCH(batch, float_to_uint(1.0)); ADVANCE_BATCH(batch); } static void i965_render_pipelined_pointers(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 7); OUT_BATCH(batch, CMD_PIPELINED_POINTERS | 5); OUT_RELOC(batch, render_state->vs.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BATCH(batch, 0); /* disable GS */ OUT_BATCH(batch, 0); /* disable CLIP */ OUT_RELOC(batch, render_state->sf.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_RELOC(batch, render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_BATCH(batch); } static void i965_render_urb_layout(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; int urb_vs_start, urb_vs_size; int urb_gs_start, urb_gs_size; int urb_clip_start, urb_clip_size; int urb_sf_start, urb_sf_size; int urb_cs_start, urb_cs_size; urb_vs_start = 0; urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE; urb_gs_start = urb_vs_start + urb_vs_size; urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE; urb_clip_start = urb_gs_start + urb_gs_size; urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE; urb_sf_start = urb_clip_start + urb_clip_size; urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE; urb_cs_start = urb_sf_start + urb_sf_size; urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE; BEGIN_BATCH(batch, 3); OUT_BATCH(batch, CMD_URB_FENCE | UF0_CS_REALLOC | UF0_SF_REALLOC | UF0_CLIP_REALLOC | UF0_GS_REALLOC | UF0_VS_REALLOC | 1); OUT_BATCH(batch, ((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) | ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) | ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT)); OUT_BATCH(batch, ((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) | ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT)); ADVANCE_BATCH(batch); } static void i965_render_cs_urb_layout(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, CMD_CS_URB_STATE | 0); OUT_BATCH(batch, ((URB_CS_ENTRY_SIZE - 1) << 4) | /* URB Entry Allocation Size */ (URB_CS_ENTRIES << 0)); /* Number of URB Entries */ ADVANCE_BATCH(batch); } static void i965_render_constant_buffer(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2)); OUT_RELOC(batch, render_state->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, URB_CS_ENTRY_SIZE - 1); ADVANCE_BATCH(batch); } static void i965_render_drawing_rectangle(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; struct intel_region *dest_region = render_state->draw_region; BEGIN_BATCH(batch, 4); OUT_BATCH(batch, CMD_DRAWING_RECTANGLE | 2); OUT_BATCH(batch, 0x00000000); OUT_BATCH(batch, (dest_region->width - 1) | (dest_region->height - 1) << 16); OUT_BATCH(batch, 0x00000000); ADVANCE_BATCH(batch); } static void i965_render_vertex_elements(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; if (IS_IRONLAKE(i965->intel.device_id)) { BEGIN_BATCH(batch, 5); OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3); /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */ OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | (0 << VE0_OFFSET_SHIFT)); OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */ OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | (8 << VE0_OFFSET_SHIFT)); OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); ADVANCE_BATCH(batch); } else { BEGIN_BATCH(batch, 5); OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3); /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */ OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | (0 << VE0_OFFSET_SHIFT)); OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) | (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */ OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | (8 << VE0_OFFSET_SHIFT)); OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) | (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); ADVANCE_BATCH(batch); } } static void i965_render_upload_image_palette( VADriverContextP ctx, struct object_image *obj_image, unsigned int alpha ) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; unsigned int i; assert(obj_image); if (!obj_image) return; if (obj_image->image.num_palette_entries == 0) return; BEGIN_BATCH(batch, 1 + obj_image->image.num_palette_entries); OUT_BATCH(batch, CMD_SAMPLER_PALETTE_LOAD | (obj_image->image.num_palette_entries - 1)); /*fill palette*/ //int32_t out[16]; //0-23:color 23-31:alpha for (i = 0; i < obj_image->image.num_palette_entries; i++) OUT_BATCH(batch, (alpha << 24) | obj_image->palette[i]); ADVANCE_BATCH(batch); } static void i965_render_startup(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 11); OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3); OUT_BATCH(batch, (0 << VB0_BUFFER_INDEX_SHIFT) | VB0_VERTEXDATA | ((4 * 4) << VB0_BUFFER_PITCH_SHIFT)); OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0); if (IS_IRONLAKE(i965->intel.device_id)) OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4); else OUT_BATCH(batch, 3); OUT_BATCH(batch, 0); OUT_BATCH(batch, CMD_3DPRIMITIVE | _3DPRIMITIVE_VERTEX_SEQUENTIAL | (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) | (0 << 9) | 4); OUT_BATCH(batch, 3); /* vertex count per instance */ OUT_BATCH(batch, 0); /* start vertex offset */ OUT_BATCH(batch, 1); /* single instance */ OUT_BATCH(batch, 0); /* start instance location */ OUT_BATCH(batch, 0); /* index buffer offset, ignored */ ADVANCE_BATCH(batch); } static void i965_clear_dest_region(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; struct intel_region *dest_region = render_state->draw_region; unsigned int blt_cmd, br13; int pitch; blt_cmd = XY_COLOR_BLT_CMD; br13 = 0xf0 << 16; pitch = dest_region->pitch; if (dest_region->cpp == 4) { br13 |= BR13_8888; blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA); } else { assert(dest_region->cpp == 2); br13 |= BR13_565; } if (dest_region->tiling != I915_TILING_NONE) { blt_cmd |= XY_COLOR_BLT_DST_TILED; pitch /= 4; } br13 |= pitch; if (IS_GEN6(i965->intel.device_id) || IS_GEN7(i965->intel.device_id) || IS_GEN8(i965->intel.device_id)) { intel_batchbuffer_start_atomic_blt(batch, 24); BEGIN_BLT_BATCH(batch, 6); } else { intel_batchbuffer_start_atomic(batch, 24); BEGIN_BATCH(batch, 6); } OUT_BATCH(batch, blt_cmd); OUT_BATCH(batch, br13); OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x)); OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) | (dest_region->x + dest_region->width)); OUT_RELOC(batch, dest_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); OUT_BATCH(batch, 0x0); ADVANCE_BATCH(batch); intel_batchbuffer_end_atomic(batch); } static void gen8_clear_dest_region(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; struct intel_region *dest_region = render_state->draw_region; unsigned int blt_cmd, br13; int pitch; blt_cmd = GEN8_XY_COLOR_BLT_CMD; br13 = 0xf0 << 16; pitch = dest_region->pitch; if (dest_region->cpp == 4) { br13 |= BR13_8888; blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA); } else { assert(dest_region->cpp == 2); br13 |= BR13_565; } if (dest_region->tiling != I915_TILING_NONE) { blt_cmd |= XY_COLOR_BLT_DST_TILED; pitch /= 4; } br13 |= pitch; intel_batchbuffer_start_atomic_blt(batch, 24); BEGIN_BLT_BATCH(batch, 7); OUT_BATCH(batch, blt_cmd); OUT_BATCH(batch, br13); OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x)); OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) | (dest_region->x + dest_region->width)); OUT_RELOC(batch, dest_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); OUT_BATCH(batch, 0x0); OUT_BATCH(batch, 0x0); ADVANCE_BATCH(batch); intel_batchbuffer_end_atomic(batch); } static void i965_surface_render_pipeline_setup(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; i965_clear_dest_region(ctx); intel_batchbuffer_start_atomic(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); i965_render_pipeline_select(ctx); i965_render_state_sip(ctx); i965_render_state_base_address(ctx); i965_render_binding_table_pointers(ctx); i965_render_constant_color(ctx); i965_render_pipelined_pointers(ctx); i965_render_urb_layout(ctx); i965_render_cs_urb_layout(ctx); i965_render_constant_buffer(ctx); i965_render_drawing_rectangle(ctx); i965_render_vertex_elements(ctx); i965_render_startup(ctx); intel_batchbuffer_end_atomic(batch); } static void i965_subpic_render_pipeline_setup(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; intel_batchbuffer_start_atomic(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); i965_render_pipeline_select(ctx); i965_render_state_sip(ctx); i965_render_state_base_address(ctx); i965_render_binding_table_pointers(ctx); i965_render_constant_color(ctx); i965_render_pipelined_pointers(ctx); i965_render_urb_layout(ctx); i965_render_cs_urb_layout(ctx); i965_render_constant_buffer(ctx); i965_render_drawing_rectangle(ctx); i965_render_vertex_elements(ctx); i965_render_startup(ctx); intel_batchbuffer_end_atomic(batch); } static void i965_render_initialize(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; dri_bo *bo; /* VERTEX BUFFER */ dri_bo_unreference(render_state->vb.vertex_buffer); bo = dri_bo_alloc(i965->intel.bufmgr, "vertex buffer", 4096, 4096); assert(bo); render_state->vb.vertex_buffer = bo; /* VS */ dri_bo_unreference(render_state->vs.state); bo = dri_bo_alloc(i965->intel.bufmgr, "vs state", sizeof(struct i965_vs_unit_state), 64); assert(bo); render_state->vs.state = bo; /* GS */ /* CLIP */ /* SF */ dri_bo_unreference(render_state->sf.state); bo = dri_bo_alloc(i965->intel.bufmgr, "sf state", sizeof(struct i965_sf_unit_state), 64); assert(bo); render_state->sf.state = bo; /* WM */ dri_bo_unreference(render_state->wm.surface_state_binding_table_bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state & binding table", (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES, 4096); assert(bo); render_state->wm.surface_state_binding_table_bo = bo; dri_bo_unreference(render_state->wm.sampler); bo = dri_bo_alloc(i965->intel.bufmgr, "sampler state", MAX_SAMPLERS * sizeof(struct i965_sampler_state), 64); assert(bo); render_state->wm.sampler = bo; render_state->wm.sampler_count = 0; dri_bo_unreference(render_state->wm.state); bo = dri_bo_alloc(i965->intel.bufmgr, "wm state", sizeof(struct i965_wm_unit_state), 64); assert(bo); render_state->wm.state = bo; /* COLOR CALCULATOR */ dri_bo_unreference(render_state->cc.state); bo = dri_bo_alloc(i965->intel.bufmgr, "color calc state", sizeof(struct i965_cc_unit_state), 64); assert(bo); render_state->cc.state = bo; dri_bo_unreference(render_state->cc.viewport); bo = dri_bo_alloc(i965->intel.bufmgr, "cc viewport", sizeof(struct i965_cc_viewport), 64); assert(bo); render_state->cc.viewport = bo; } static void i965_render_put_surface( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect, unsigned int flags ) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; i965_render_initialize(ctx); i965_surface_render_state_setup(ctx, obj_surface, src_rect, dst_rect, flags); i965_surface_render_pipeline_setup(ctx); intel_batchbuffer_flush(batch); } static void i965_render_put_subpicture( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect ) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; unsigned int index = obj_surface->subpic_render_idx; struct object_subpic *obj_subpic = obj_surface->obj_subpic[index]; assert(obj_subpic); i965_render_initialize(ctx); i965_subpic_render_state_setup(ctx, obj_surface, src_rect, dst_rect); i965_subpic_render_pipeline_setup(ctx); i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff); intel_batchbuffer_flush(batch); } /* * for GEN6+ */ static void gen6_render_initialize(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; dri_bo *bo; /* VERTEX BUFFER */ dri_bo_unreference(render_state->vb.vertex_buffer); bo = dri_bo_alloc(i965->intel.bufmgr, "vertex buffer", 4096, 4096); assert(bo); render_state->vb.vertex_buffer = bo; /* WM */ dri_bo_unreference(render_state->wm.surface_state_binding_table_bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state & binding table", (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES, 4096); assert(bo); render_state->wm.surface_state_binding_table_bo = bo; dri_bo_unreference(render_state->wm.sampler); bo = dri_bo_alloc(i965->intel.bufmgr, "sampler state", MAX_SAMPLERS * sizeof(struct i965_sampler_state), 4096); assert(bo); render_state->wm.sampler = bo; render_state->wm.sampler_count = 0; /* COLOR CALCULATOR */ dri_bo_unreference(render_state->cc.state); bo = dri_bo_alloc(i965->intel.bufmgr, "color calc state", sizeof(struct gen6_color_calc_state), 4096); assert(bo); render_state->cc.state = bo; /* CC VIEWPORT */ dri_bo_unreference(render_state->cc.viewport); bo = dri_bo_alloc(i965->intel.bufmgr, "cc viewport", sizeof(struct i965_cc_viewport), 4096); assert(bo); render_state->cc.viewport = bo; /* BLEND STATE */ dri_bo_unreference(render_state->cc.blend); bo = dri_bo_alloc(i965->intel.bufmgr, "blend state", sizeof(struct gen6_blend_state), 4096); assert(bo); render_state->cc.blend = bo; /* DEPTH & STENCIL STATE */ dri_bo_unreference(render_state->cc.depth_stencil); bo = dri_bo_alloc(i965->intel.bufmgr, "depth & stencil state", sizeof(struct gen6_depth_stencil_state), 4096); assert(bo); render_state->cc.depth_stencil = bo; } static void gen6_render_color_calc_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen6_color_calc_state *color_calc_state; dri_bo_map(render_state->cc.state, 1); assert(render_state->cc.state->virtual); color_calc_state = render_state->cc.state->virtual; memset(color_calc_state, 0, sizeof(*color_calc_state)); color_calc_state->constant_r = 1.0; color_calc_state->constant_g = 0.0; color_calc_state->constant_b = 1.0; color_calc_state->constant_a = 1.0; dri_bo_unmap(render_state->cc.state); } static void gen6_render_blend_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen6_blend_state *blend_state; dri_bo_map(render_state->cc.blend, 1); assert(render_state->cc.blend->virtual); blend_state = render_state->cc.blend->virtual; memset(blend_state, 0, sizeof(*blend_state)); blend_state->blend1.logic_op_enable = 1; blend_state->blend1.logic_op_func = 0xc; dri_bo_unmap(render_state->cc.blend); } static void gen6_render_depth_stencil_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen6_depth_stencil_state *depth_stencil_state; dri_bo_map(render_state->cc.depth_stencil, 1); assert(render_state->cc.depth_stencil->virtual); depth_stencil_state = render_state->cc.depth_stencil->virtual; memset(depth_stencil_state, 0, sizeof(*depth_stencil_state)); dri_bo_unmap(render_state->cc.depth_stencil); } static void gen6_render_setup_states( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect, unsigned int flags ) { i965_render_dest_surface_state(ctx, 0); i965_render_src_surfaces_state(ctx, obj_surface, flags); i965_render_sampler(ctx); i965_render_cc_viewport(ctx); gen6_render_color_calc_state(ctx); gen6_render_blend_state(ctx); gen6_render_depth_stencil_state(ctx); i965_render_upload_constants(ctx, obj_surface, flags); i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect); } static void gen6_emit_invarient_states(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D); OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (3 - 2)); OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER | GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */ OUT_BATCH(batch, 0); OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2)); OUT_BATCH(batch, 1); /* Set system instruction pointer */ OUT_BATCH(batch, CMD_STATE_SIP | 0); OUT_BATCH(batch, 0); } static void gen6_emit_state_base_address(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2)); OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */ OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */ } static void gen6_emit_viewport_state_pointers(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; OUT_BATCH(batch, GEN6_3DSTATE_VIEWPORT_STATE_POINTERS | GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_RELOC(batch, render_state->cc.viewport, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } static void gen6_emit_urb(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; OUT_BATCH(batch, GEN6_3DSTATE_URB | (3 - 2)); OUT_BATCH(batch, ((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) | (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */ OUT_BATCH(batch, (0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) | (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */ } static void gen6_emit_cc_state_pointers(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2)); OUT_RELOC(batch, render_state->cc.blend, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); OUT_RELOC(batch, render_state->cc.depth_stencil, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); } static void gen6_emit_sampler_state_pointers(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; OUT_BATCH(batch, GEN6_3DSTATE_SAMPLER_STATE_POINTERS | GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS | (4 - 2)); OUT_BATCH(batch, 0); /* VS */ OUT_BATCH(batch, 0); /* GS */ OUT_RELOC(batch,render_state->wm.sampler, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); } static void gen6_emit_binding_table(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; /* Binding table pointers */ OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS | GEN6_BINDING_TABLE_MODIFY_PS | (4 - 2)); OUT_BATCH(batch, 0); /* vs */ OUT_BATCH(batch, 0); /* gs */ /* Only the PS uses the binding table */ OUT_BATCH(batch, BINDING_TABLE_OFFSET); } static void gen6_emit_depth_buffer_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; OUT_BATCH(batch, CMD_DEPTH_BUFFER | (7 - 2)); OUT_BATCH(batch, (I965_SURFACE_NULL << CMD_DEPTH_BUFFER_TYPE_SHIFT) | (I965_DEPTHFORMAT_D32_FLOAT << CMD_DEPTH_BUFFER_FORMAT_SHIFT)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, CMD_CLEAR_PARAMS | (2 - 2)); OUT_BATCH(batch, 0); } static void gen6_emit_drawing_rectangle(VADriverContextP ctx) { i965_render_drawing_rectangle(ctx); } static void gen6_emit_vs_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; /* disable VS constant buffer */ OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (5 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2)); OUT_BATCH(batch, 0); /* without VS kernel */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* pass-through */ } static void gen6_emit_gs_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; /* disable GS constant buffer */ OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (5 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2)); OUT_BATCH(batch, 0); /* without GS kernel */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* pass-through */ } static void gen6_emit_clip_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* pass-through */ OUT_BATCH(batch, 0); } static void gen6_emit_sf_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; OUT_BATCH(batch, GEN6_3DSTATE_SF | (20 - 2)); OUT_BATCH(batch, (1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) | (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) | (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT)); OUT_BATCH(batch, 0); OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE); OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* DW9 */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* DW14 */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* DW19 */ } static void gen6_emit_wm_state(VADriverContextP ctx, int kernel) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | GEN6_3DSTATE_CONSTANT_BUFFER_0_ENABLE | (5 - 2)); OUT_RELOC(batch, render_state->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, (URB_CS_ENTRY_SIZE-1)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, GEN6_3DSTATE_WM | (9 - 2)); OUT_RELOC(batch, render_state->render_kernels[kernel].bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) | (5 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT)); OUT_BATCH(batch, 0); OUT_BATCH(batch, (6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */ OUT_BATCH(batch, ((render_state->max_wm_threads - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) | GEN6_3DSTATE_WM_DISPATCH_ENABLE | GEN6_3DSTATE_WM_16_DISPATCH_ENABLE); OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) | GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); } static void gen6_emit_vertex_element_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; /* Set up our vertex elements, sourced from the single vertex buffer. */ OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2)); /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */ OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID | (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | (0 << VE0_OFFSET_SHIFT)); OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */ OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID | (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | (8 << VE0_OFFSET_SHIFT)); OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); } static void gen6_emit_vertices(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 11); OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3); OUT_BATCH(batch, (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) | GEN6_VB0_VERTEXDATA | ((4 * 4) << VB0_BUFFER_PITCH_SHIFT)); OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0); OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4); OUT_BATCH(batch, 0); OUT_BATCH(batch, CMD_3DPRIMITIVE | _3DPRIMITIVE_VERTEX_SEQUENTIAL | (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) | (0 << 9) | 4); OUT_BATCH(batch, 3); /* vertex count per instance */ OUT_BATCH(batch, 0); /* start vertex offset */ OUT_BATCH(batch, 1); /* single instance */ OUT_BATCH(batch, 0); /* start instance location */ OUT_BATCH(batch, 0); /* index buffer offset, ignored */ ADVANCE_BATCH(batch); } static void gen6_render_emit_states(VADriverContextP ctx, int kernel) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; intel_batchbuffer_start_atomic(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen6_emit_invarient_states(ctx); gen6_emit_state_base_address(ctx); gen6_emit_viewport_state_pointers(ctx); gen6_emit_urb(ctx); gen6_emit_cc_state_pointers(ctx); gen6_emit_sampler_state_pointers(ctx); gen6_emit_vs_state(ctx); gen6_emit_gs_state(ctx); gen6_emit_clip_state(ctx); gen6_emit_sf_state(ctx); gen6_emit_wm_state(ctx, kernel); gen6_emit_binding_table(ctx); gen6_emit_depth_buffer_state(ctx); gen6_emit_drawing_rectangle(ctx); gen6_emit_vertex_element_state(ctx); gen6_emit_vertices(ctx); intel_batchbuffer_end_atomic(batch); } static void gen6_render_put_surface( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect, unsigned int flags ) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; gen6_render_initialize(ctx); gen6_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags); i965_clear_dest_region(ctx); gen6_render_emit_states(ctx, PS_KERNEL); intel_batchbuffer_flush(batch); } static void gen6_subpicture_render_blend_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen6_blend_state *blend_state; dri_bo_unmap(render_state->cc.state); dri_bo_map(render_state->cc.blend, 1); assert(render_state->cc.blend->virtual); blend_state = render_state->cc.blend->virtual; memset(blend_state, 0, sizeof(*blend_state)); blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA; blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA; blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD; blend_state->blend0.blend_enable = 1; blend_state->blend1.post_blend_clamp_enable = 1; blend_state->blend1.pre_blend_clamp_enable = 1; blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */ dri_bo_unmap(render_state->cc.blend); } static void gen6_subpicture_render_setup_states( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect ) { i965_render_dest_surface_state(ctx, 0); i965_subpic_render_src_surfaces_state(ctx, obj_surface); i965_render_sampler(ctx); i965_render_cc_viewport(ctx); gen6_render_color_calc_state(ctx); gen6_subpicture_render_blend_state(ctx); gen6_render_depth_stencil_state(ctx); i965_subpic_render_upload_constants(ctx, obj_surface); i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect); } static void gen6_render_put_subpicture( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect ) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; unsigned int index = obj_surface->subpic_render_idx; struct object_subpic *obj_subpic = obj_surface->obj_subpic[index]; assert(obj_subpic); gen6_render_initialize(ctx); gen6_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect); gen6_render_emit_states(ctx, PS_SUBPIC_KERNEL); i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff); intel_batchbuffer_flush(batch); } /* * for GEN7 */ static void gen7_render_initialize(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; dri_bo *bo; /* VERTEX BUFFER */ dri_bo_unreference(render_state->vb.vertex_buffer); bo = dri_bo_alloc(i965->intel.bufmgr, "vertex buffer", 4096, 4096); assert(bo); render_state->vb.vertex_buffer = bo; /* WM */ dri_bo_unreference(render_state->wm.surface_state_binding_table_bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state & binding table", (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES, 4096); assert(bo); render_state->wm.surface_state_binding_table_bo = bo; dri_bo_unreference(render_state->wm.sampler); bo = dri_bo_alloc(i965->intel.bufmgr, "sampler state", MAX_SAMPLERS * sizeof(struct gen7_sampler_state), 4096); assert(bo); render_state->wm.sampler = bo; render_state->wm.sampler_count = 0; /* COLOR CALCULATOR */ dri_bo_unreference(render_state->cc.state); bo = dri_bo_alloc(i965->intel.bufmgr, "color calc state", sizeof(struct gen6_color_calc_state), 4096); assert(bo); render_state->cc.state = bo; /* CC VIEWPORT */ dri_bo_unreference(render_state->cc.viewport); bo = dri_bo_alloc(i965->intel.bufmgr, "cc viewport", sizeof(struct i965_cc_viewport), 4096); assert(bo); render_state->cc.viewport = bo; /* BLEND STATE */ dri_bo_unreference(render_state->cc.blend); bo = dri_bo_alloc(i965->intel.bufmgr, "blend state", sizeof(struct gen6_blend_state), 4096); assert(bo); render_state->cc.blend = bo; /* DEPTH & STENCIL STATE */ dri_bo_unreference(render_state->cc.depth_stencil); bo = dri_bo_alloc(i965->intel.bufmgr, "depth & stencil state", sizeof(struct gen6_depth_stencil_state), 4096); assert(bo); render_state->cc.depth_stencil = bo; } /* * for GEN8 */ #define ALIGNMENT 64 static void gen8_render_initialize(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; dri_bo *bo; int size; unsigned int end_offset; /* VERTEX BUFFER */ dri_bo_unreference(render_state->vb.vertex_buffer); bo = dri_bo_alloc(i965->intel.bufmgr, "vertex buffer", 4096, 4096); assert(bo); render_state->vb.vertex_buffer = bo; /* WM */ dri_bo_unreference(render_state->wm.surface_state_binding_table_bo); bo = dri_bo_alloc(i965->intel.bufmgr, "surface state & binding table", (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES, 4096); assert(bo); render_state->wm.surface_state_binding_table_bo = bo; render_state->curbe_size = 256; render_state->wm.sampler_count = 0; render_state->sampler_size = MAX_SAMPLERS * sizeof(struct gen8_sampler_state); render_state->cc_state_size = sizeof(struct gen6_color_calc_state); render_state->cc_viewport_size = sizeof(struct i965_cc_viewport); render_state->blend_state_size = sizeof(struct gen8_global_blend_state) + 16 * sizeof(struct gen8_blend_state_rt); render_state->sf_clip_size = 1024; render_state->scissor_size = 1024; size = ALIGN(render_state->curbe_size, ALIGNMENT) + ALIGN(render_state->sampler_size, ALIGNMENT) + ALIGN(render_state->cc_viewport_size, ALIGNMENT) + ALIGN(render_state->cc_state_size, ALIGNMENT) + ALIGN(render_state->blend_state_size, ALIGNMENT) + ALIGN(render_state->sf_clip_size, ALIGNMENT) + ALIGN(render_state->scissor_size, ALIGNMENT); dri_bo_unreference(render_state->dynamic_state.bo); bo = dri_bo_alloc(i965->intel.bufmgr, "dynamic_state", size, 4096); render_state->dynamic_state.bo = bo; end_offset = 0; render_state->dynamic_state.end_offset = 0; /* Constant buffer offset */ render_state->curbe_offset = end_offset; end_offset += ALIGN(render_state->curbe_size, ALIGNMENT); /* Sampler_state */ render_state->sampler_offset = end_offset; end_offset += ALIGN(render_state->sampler_size, ALIGNMENT); /* CC_VIEWPORT_state */ render_state->cc_viewport_offset = end_offset; end_offset += ALIGN(render_state->cc_viewport_size, ALIGNMENT); /* CC_STATE_state */ render_state->cc_state_offset = end_offset; end_offset += ALIGN(render_state->cc_state_size, ALIGNMENT); /* Blend_state */ render_state->blend_state_offset = end_offset; end_offset += ALIGN(render_state->blend_state_size, ALIGNMENT); /* SF_CLIP_state */ render_state->sf_clip_offset = end_offset; end_offset += ALIGN(render_state->sf_clip_size, ALIGNMENT); /* SCISSOR_state */ render_state->scissor_offset = end_offset; end_offset += ALIGN(render_state->scissor_size, ALIGNMENT); /* update the end offset of dynamic_state */ render_state->dynamic_state.end_offset = end_offset; } static void gen7_render_color_calc_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen6_color_calc_state *color_calc_state; dri_bo_map(render_state->cc.state, 1); assert(render_state->cc.state->virtual); color_calc_state = render_state->cc.state->virtual; memset(color_calc_state, 0, sizeof(*color_calc_state)); color_calc_state->constant_r = 1.0; color_calc_state->constant_g = 0.0; color_calc_state->constant_b = 1.0; color_calc_state->constant_a = 1.0; dri_bo_unmap(render_state->cc.state); } static void gen7_render_blend_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen6_blend_state *blend_state; dri_bo_map(render_state->cc.blend, 1); assert(render_state->cc.blend->virtual); blend_state = render_state->cc.blend->virtual; memset(blend_state, 0, sizeof(*blend_state)); blend_state->blend1.logic_op_enable = 1; blend_state->blend1.logic_op_func = 0xc; blend_state->blend1.pre_blend_clamp_enable = 1; dri_bo_unmap(render_state->cc.blend); } static void gen7_render_depth_stencil_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen6_depth_stencil_state *depth_stencil_state; dri_bo_map(render_state->cc.depth_stencil, 1); assert(render_state->cc.depth_stencil->virtual); depth_stencil_state = render_state->cc.depth_stencil->virtual; memset(depth_stencil_state, 0, sizeof(*depth_stencil_state)); dri_bo_unmap(render_state->cc.depth_stencil); } static void gen7_render_sampler(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen7_sampler_state *sampler_state; int i; assert(render_state->wm.sampler_count > 0); assert(render_state->wm.sampler_count <= MAX_SAMPLERS); dri_bo_map(render_state->wm.sampler, 1); assert(render_state->wm.sampler->virtual); sampler_state = render_state->wm.sampler->virtual; for (i = 0; i < render_state->wm.sampler_count; i++) { memset(sampler_state, 0, sizeof(*sampler_state)); sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR; sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR; sampler_state->ss3.r_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state->ss3.s_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state->ss3.t_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state++; } dri_bo_unmap(render_state->wm.sampler); } static void gen8_render_sampler(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen8_sampler_state *sampler_state; int i; unsigned char *cc_ptr; assert(render_state->wm.sampler_count > 0); assert(render_state->wm.sampler_count <= MAX_SAMPLERS); dri_bo_map(render_state->dynamic_state.bo, 1); assert(render_state->dynamic_state.bo->virtual); cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual + render_state->sampler_offset; sampler_state = (struct gen8_sampler_state *) cc_ptr; for (i = 0; i < render_state->wm.sampler_count; i++) { memset(sampler_state, 0, sizeof(*sampler_state)); sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR; sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR; sampler_state->ss3.r_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state->ss3.s_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state->ss3.t_wrap_mode = I965_TEXCOORDMODE_CLAMP; sampler_state++; } dri_bo_unmap(render_state->dynamic_state.bo); } static void gen7_render_setup_states( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect, unsigned int flags ) { i965_render_dest_surface_state(ctx, 0); i965_render_src_surfaces_state(ctx, obj_surface, flags); gen7_render_sampler(ctx); i965_render_cc_viewport(ctx); gen7_render_color_calc_state(ctx); gen7_render_blend_state(ctx); gen7_render_depth_stencil_state(ctx); i965_render_upload_constants(ctx, obj_surface, flags); i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect); } static void gen8_render_blend_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen8_global_blend_state *global_blend_state; struct gen8_blend_state_rt *blend_state; unsigned char *cc_ptr; dri_bo_map(render_state->dynamic_state.bo, 1); assert(render_state->dynamic_state.bo->virtual); cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual + render_state->blend_state_offset; global_blend_state = (struct gen8_global_blend_state*) cc_ptr; memset(global_blend_state, 0, render_state->blend_state_size); /* Global blend state + blend_state for Render Target */ blend_state = (struct gen8_blend_state_rt *)(global_blend_state + 1); blend_state->blend1.logic_op_enable = 1; blend_state->blend1.logic_op_func = 0xc; blend_state->blend1.pre_blend_clamp_enable = 1; dri_bo_unmap(render_state->dynamic_state.bo); } static void gen8_render_cc_viewport(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct i965_cc_viewport *cc_viewport; unsigned char *cc_ptr; dri_bo_map(render_state->dynamic_state.bo, 1); assert(render_state->dynamic_state.bo->virtual); cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual + render_state->cc_viewport_offset; cc_viewport = (struct i965_cc_viewport *) cc_ptr; memset(cc_viewport, 0, sizeof(*cc_viewport)); cc_viewport->min_depth = -1.e35; cc_viewport->max_depth = 1.e35; dri_bo_unmap(render_state->dynamic_state.bo); } static void gen8_render_color_calc_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen6_color_calc_state *color_calc_state; unsigned char *cc_ptr; dri_bo_map(render_state->dynamic_state.bo, 1); assert(render_state->dynamic_state.bo->virtual); cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual + render_state->cc_state_offset; color_calc_state = (struct gen6_color_calc_state *) cc_ptr; memset(color_calc_state, 0, sizeof(*color_calc_state)); color_calc_state->constant_r = 1.0; color_calc_state->constant_g = 0.0; color_calc_state->constant_b = 1.0; color_calc_state->constant_a = 1.0; dri_bo_unmap(render_state->dynamic_state.bo); } static void gen8_render_upload_constants(VADriverContextP ctx, struct object_surface *obj_surface, unsigned int flags) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; unsigned short *constant_buffer; unsigned char *cc_ptr; float *color_balance_base; float contrast = (float)i965->contrast_attrib->value / DEFAULT_CONTRAST; float brightness = (float)i965->brightness_attrib->value / 255; /* YUV is float in the shader */ float hue = (float)i965->hue_attrib->value / 180 * PI; float saturation = (float)i965->saturation_attrib->value / DEFAULT_SATURATION; float *yuv_to_rgb; unsigned int color_flag; dri_bo_map(render_state->dynamic_state.bo, 1); assert(render_state->dynamic_state.bo->virtual); cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual + render_state->curbe_offset; constant_buffer = (unsigned short *) cc_ptr; if (obj_surface->subsampling == SUBSAMPLE_YUV400) { assert(obj_surface->fourcc == VA_FOURCC('Y', '8', '0', '0')); *constant_buffer = 2; } else { if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')) *constant_buffer = 1; else *constant_buffer = 0; } if (i965->contrast_attrib->value == DEFAULT_CONTRAST && i965->brightness_attrib->value == DEFAULT_BRIGHTNESS && i965->hue_attrib->value == DEFAULT_HUE && i965->saturation_attrib->value == DEFAULT_SATURATION) constant_buffer[1] = 1; /* skip color balance transformation */ else constant_buffer[1] = 0; color_balance_base = (float *)constant_buffer + 4; *color_balance_base++ = contrast; *color_balance_base++ = brightness; *color_balance_base++ = cos(hue) * contrast * saturation; *color_balance_base++ = sin(hue) * contrast * saturation; color_flag = flags & VA_SRC_COLOR_MASK; yuv_to_rgb = (float *)constant_buffer + 8; if (color_flag == VA_SRC_BT709) memcpy(yuv_to_rgb, yuv_to_rgb_bt709, sizeof(yuv_to_rgb_bt709)); else if (color_flag == VA_SRC_SMPTE_240) memcpy(yuv_to_rgb, yuv_to_rgb_smpte_240, sizeof(yuv_to_rgb_smpte_240)); else memcpy(yuv_to_rgb, yuv_to_rgb_bt601, sizeof(yuv_to_rgb_bt601)); dri_bo_unmap(render_state->dynamic_state.bo); } static void gen8_render_setup_states( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect, unsigned int flags ) { i965_render_dest_surface_state(ctx, 0); i965_render_src_surfaces_state(ctx, obj_surface, flags); gen8_render_sampler(ctx); gen8_render_cc_viewport(ctx); gen8_render_color_calc_state(ctx); gen8_render_blend_state(ctx); gen8_render_upload_constants(ctx, obj_surface, flags); i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect); } static void gen7_emit_invarient_states(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 1); OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 4); OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (4 - 2)); OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER | GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2)); OUT_BATCH(batch, 1); ADVANCE_BATCH(batch); /* Set system instruction pointer */ BEGIN_BATCH(batch, 2); OUT_BATCH(batch, CMD_STATE_SIP | 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen7_emit_state_base_address(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2)); OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */ OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */ } static void gen8_emit_state_base_address(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 16); OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (16 - 2)); OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /*DW4 */ OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */ OUT_BATCH(batch, 0); /*DW6*/ /* Dynamic state base address */ OUT_RELOC(batch, render_state->dynamic_state.bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0); /*DW8*/ OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */ OUT_BATCH(batch, 0); /*DW10 */ /* Instruction base address */ OUT_RELOC(batch, render_state->instruction_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); OUT_BATCH(batch, 0); /*DW12 */ OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); /* General state upper bound */ OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */ OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); /* Indirect object upper bound */ OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY); /* Instruction access upper bound */ ADVANCE_BATCH(batch); } static void gen7_emit_viewport_state_pointers(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2)); OUT_RELOC(batch, render_state->cc.viewport, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } /* * URB layout on GEN7 * ---------------------------------------- * | PS Push Constants (8KB) | VS entries | * ---------------------------------------- */ static void gen7_emit_urb(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; unsigned int num_urb_entries = 32; if (IS_HASWELL(i965->intel.device_id)) num_urb_entries = 64; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2)); OUT_BATCH(batch, 8); /* in 1KBs */ ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_URB_VS | (2 - 2)); OUT_BATCH(batch, (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) | (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT | (1 << GEN7_URB_STARTING_ADDRESS_SHIFT)); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2)); OUT_BATCH(batch, (0 << GEN7_URB_ENTRY_SIZE_SHIFT) | (1 << GEN7_URB_STARTING_ADDRESS_SHIFT)); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2)); OUT_BATCH(batch, (0 << GEN7_URB_ENTRY_SIZE_SHIFT) | (2 << GEN7_URB_STARTING_ADDRESS_SHIFT)); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2)); OUT_BATCH(batch, (0 << GEN7_URB_ENTRY_SIZE_SHIFT) | (2 << GEN7_URB_STARTING_ADDRESS_SHIFT)); ADVANCE_BATCH(batch); } static void gen7_emit_cc_state_pointers(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2)); OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2)); OUT_RELOC(batch, render_state->cc.blend, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2)); OUT_RELOC(batch, render_state->cc.depth_stencil, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); ADVANCE_BATCH(batch); } static void gen8_emit_cc_state_pointers(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2)); OUT_BATCH(batch, (render_state->cc_state_offset + 1)); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2)); OUT_BATCH(batch, (render_state->blend_state_offset + 1)); ADVANCE_BATCH(batch); } static void gen7_emit_sampler_state_pointers(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2)); OUT_RELOC(batch, render_state->wm.sampler, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_BATCH(batch); } static void gen7_emit_binding_table(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2)); OUT_BATCH(batch, BINDING_TABLE_OFFSET); ADVANCE_BATCH(batch); } static void gen7_emit_depth_buffer_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 7); OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2)); OUT_BATCH(batch, (I965_DEPTHFORMAT_D32_FLOAT << 18) | (I965_SURFACE_NULL << 29)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 3); OUT_BATCH(batch, GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen7_emit_drawing_rectangle(VADriverContextP ctx) { i965_render_drawing_rectangle(ctx); } static void gen7_emit_vs_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; /* disable VS constant buffer */ OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (7 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2)); OUT_BATCH(batch, 0); /* without VS kernel */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* pass-through */ } static void gen7_emit_bypass_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; /* bypass GS */ BEGIN_BATCH(batch, 7); OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (7 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 7); OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2)); OUT_BATCH(batch, 0); /* without GS kernel */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* pass-through */ ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); /* disable HS */ BEGIN_BATCH(batch, 7); OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_HS | (7 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 7); OUT_BATCH(batch, GEN7_3DSTATE_HS | (7 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); /* Disable TE */ BEGIN_BATCH(batch, 4); OUT_BATCH(batch, GEN7_3DSTATE_TE | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); /* Disable DS */ BEGIN_BATCH(batch, 7); OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_DS | (7 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 6); OUT_BATCH(batch, GEN7_3DSTATE_DS | (6 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); /* Disable STREAMOUT */ BEGIN_BATCH(batch, 3); OUT_BATCH(batch, GEN7_3DSTATE_STREAMOUT | (3 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen7_emit_clip_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* pass-through */ OUT_BATCH(batch, 0); } static void gen7_emit_sf_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 14); OUT_BATCH(batch, GEN7_3DSTATE_SBE | (14 - 2)); OUT_BATCH(batch, (1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) | (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) | (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* DW4 */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* DW9 */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 7); OUT_BATCH(batch, GEN6_3DSTATE_SF | (7 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE); OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen7_emit_wm_state(VADriverContextP ctx, int kernel) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB; unsigned int num_samples = 0; if (IS_HASWELL(i965->intel.device_id)) { max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW; num_samples = 1 << GEN7_PS_SAMPLE_MASK_SHIFT_HSW; } BEGIN_BATCH(batch, 3); OUT_BATCH(batch, GEN6_3DSTATE_WM | (3 - 2)); OUT_BATCH(batch, GEN7_WM_DISPATCH_ENABLE | GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 7); OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (7 - 2)); OUT_BATCH(batch, URB_CS_ENTRY_SIZE); OUT_BATCH(batch, 0); OUT_RELOC(batch, render_state->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 8); OUT_BATCH(batch, GEN7_3DSTATE_PS | (8 - 2)); OUT_RELOC(batch, render_state->render_kernels[kernel].bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BATCH(batch, (1 << GEN7_PS_SAMPLER_COUNT_SHIFT) | (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); OUT_BATCH(batch, 0); /* scratch space base offset */ OUT_BATCH(batch, ((render_state->max_wm_threads - 1) << max_threads_shift) | num_samples | GEN7_PS_PUSH_CONSTANT_ENABLE | GEN7_PS_ATTRIBUTE_ENABLE | GEN7_PS_16_DISPATCH_ENABLE); OUT_BATCH(batch, (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0)); OUT_BATCH(batch, 0); /* kernel 1 pointer */ OUT_BATCH(batch, 0); /* kernel 2 pointer */ ADVANCE_BATCH(batch); } static void gen7_emit_vertex_element_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; /* Set up our vertex elements, sourced from the single vertex buffer. */ OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2)); /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */ OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID | (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | (0 << VE0_OFFSET_SHIFT)); OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */ OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID | (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | (8 << VE0_OFFSET_SHIFT)); OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); } static void gen7_emit_vertices(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 5); OUT_BATCH(batch, CMD_VERTEX_BUFFERS | (5 - 2)); OUT_BATCH(batch, (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) | GEN6_VB0_VERTEXDATA | GEN7_VB0_ADDRESS_MODIFYENABLE | ((4 * 4) << VB0_BUFFER_PITCH_SHIFT)); OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0); OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 7); OUT_BATCH(batch, CMD_3DPRIMITIVE | (7 - 2)); OUT_BATCH(batch, _3DPRIM_RECTLIST | GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL); OUT_BATCH(batch, 3); /* vertex count per instance */ OUT_BATCH(batch, 0); /* start vertex offset */ OUT_BATCH(batch, 1); /* single instance */ OUT_BATCH(batch, 0); /* start instance location */ OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen7_render_emit_states(VADriverContextP ctx, int kernel) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; intel_batchbuffer_start_atomic(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen7_emit_invarient_states(ctx); gen7_emit_state_base_address(ctx); gen7_emit_viewport_state_pointers(ctx); gen7_emit_urb(ctx); gen7_emit_cc_state_pointers(ctx); gen7_emit_sampler_state_pointers(ctx); gen7_emit_bypass_state(ctx); gen7_emit_vs_state(ctx); gen7_emit_clip_state(ctx); gen7_emit_sf_state(ctx); gen7_emit_wm_state(ctx, kernel); gen7_emit_binding_table(ctx); gen7_emit_depth_buffer_state(ctx); gen7_emit_drawing_rectangle(ctx); gen7_emit_vertex_element_state(ctx); gen7_emit_vertices(ctx); intel_batchbuffer_end_atomic(batch); } static void gen8_emit_vertices(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 5); OUT_BATCH(batch, CMD_VERTEX_BUFFERS | (5 - 2)); OUT_BATCH(batch, (0 << GEN8_VB0_BUFFER_INDEX_SHIFT) | (0 << GEN8_VB0_MOCS_SHIFT) | GEN7_VB0_ADDRESS_MODIFYENABLE | ((4 * 4) << VB0_BUFFER_PITCH_SHIFT)); OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 12 * 4); ADVANCE_BATCH(batch); /* Topology in 3D primitive is overrided by VF_TOPOLOGY command */ BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN8_3DSTATE_VF_TOPOLOGY | (2 - 2)); OUT_BATCH(batch, _3DPRIM_RECTLIST); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 7); OUT_BATCH(batch, CMD_3DPRIMITIVE | (7 - 2)); OUT_BATCH(batch, GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL); OUT_BATCH(batch, 3); /* vertex count per instance */ OUT_BATCH(batch, 0); /* start vertex offset */ OUT_BATCH(batch, 1); /* single instance */ OUT_BATCH(batch, 0); /* start instance location */ OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen8_emit_vertex_element_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; /* * The VUE layout * dword 0-3: pad (0, 0, 0. 0) * dword 4-7: position (x, y, 1.0, 1.0), * dword 8-11: texture coordinate 0 (u0, v0, 1.0, 1.0) */ /* Set up our vertex elements, sourced from the single vertex buffer. */ OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (7 - 2)); /* Element state 0. These are 4 dwords of 0 required for the VUE format. * We don't really know or care what they do. */ OUT_BATCH(batch, (0 << GEN8_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN8_VE0_VALID | (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | (0 << VE0_OFFSET_SHIFT)); OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) | (I965_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) | (I965_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) | (I965_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT)); /* offset 8: X, Y -> {x, y, 1.0, 1.0} */ OUT_BATCH(batch, (0 << GEN8_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN8_VE0_VALID | (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | (8 << VE0_OFFSET_SHIFT)); OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); /* offset 0: u,v -> {U, V, 1.0, 1.0} */ OUT_BATCH(batch, (0 << GEN8_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN8_VE0_VALID | (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | (0 << VE0_OFFSET_SHIFT)); OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); } static void gen8_emit_vs_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; /* disable VS constant buffer */ BEGIN_BATCH(batch, 11); OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (11 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* CS Buffer 0 */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* CS Buffer 1 */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* CS Buffer 2 */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* CS Buffer 3 */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 9); OUT_BATCH(batch, GEN6_3DSTATE_VS | (9 - 2)); OUT_BATCH(batch, 0); /* without VS kernel */ OUT_BATCH(batch, 0); /* VS shader dispatch flag */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* DW6. VS shader GRF and URB buffer definition */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* pass-through */ OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } /* * URB layout on GEN8 * ---------------------------------------- * | PS Push Constants (8KB) | VS entries | * ---------------------------------------- */ static void gen8_emit_urb(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; unsigned int num_urb_entries = 64; /* The minimum urb entries is 64 */ BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); /* Size is 8Kbs and base address is 0Kb */ BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2)); /* Size is 8Kbs and base address is 0Kb */ OUT_BATCH(batch, (0 << GEN8_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT) | (8 << GEN8_PUSH_CONSTANT_BUFFER_SIZE_SHIFT)); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_URB_VS | (2 - 2)); OUT_BATCH(batch, (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) | (4 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT | (1 << GEN7_URB_STARTING_ADDRESS_SHIFT)); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2)); OUT_BATCH(batch, (0 << GEN7_URB_ENTRY_SIZE_SHIFT) | (5 << GEN7_URB_STARTING_ADDRESS_SHIFT)); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2)); OUT_BATCH(batch, (0 << GEN7_URB_ENTRY_SIZE_SHIFT) | (6 << GEN7_URB_STARTING_ADDRESS_SHIFT)); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2)); OUT_BATCH(batch, (0 << GEN7_URB_ENTRY_SIZE_SHIFT) | (7 << GEN7_URB_STARTING_ADDRESS_SHIFT)); ADVANCE_BATCH(batch); } static void gen8_emit_bypass_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; /* bypass GS */ BEGIN_BATCH(batch, 11); OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (11 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 10); OUT_BATCH(batch, GEN6_3DSTATE_GS | (10 - 2)); /* GS shader address */ OUT_BATCH(batch, 0); /* without GS kernel */ OUT_BATCH(batch, 0); /* DW3. GS shader dispatch flag */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* DW6. GS shader GRF and URB offset/length */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* pass-through */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); /* disable HS */ BEGIN_BATCH(batch, 11); OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_HS | (11 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 9); OUT_BATCH(batch, GEN7_3DSTATE_HS | (9 - 2)); OUT_BATCH(batch, 0); /*DW2. HS pass-through */ OUT_BATCH(batch, 0); /*DW3. HS shader address */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /*DW5. HS shader flag. URB offset/length and so on */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); /* Disable TE */ BEGIN_BATCH(batch, 4); OUT_BATCH(batch, GEN7_3DSTATE_TE | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); /* Disable DS */ BEGIN_BATCH(batch, 11); OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_DS | (11 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 9); OUT_BATCH(batch, GEN7_3DSTATE_DS | (9 - 2)); /* DW1. DS shader pointer */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* DW3-5. DS shader dispatch flag.*/ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* DW6-7. DS shader pass-through, GRF,URB offset/Length,Thread Number*/ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* DW8. DS shader output URB */ OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); /* Disable STREAMOUT */ BEGIN_BATCH(batch, 5); OUT_BATCH(batch, GEN7_3DSTATE_STREAMOUT | (5 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen8_emit_invarient_states(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 1); OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN8_3DSTATE_MULTISAMPLE | (2 - 2)); OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER | GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */ ADVANCE_BATCH(batch); /* Update 3D Multisample pattern */ BEGIN_BATCH(batch, 9); OUT_BATCH(batch, GEN8_3DSTATE_SAMPLE_PATTERN | (9 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2)); OUT_BATCH(batch, 1); ADVANCE_BATCH(batch); /* Set system instruction pointer */ BEGIN_BATCH(batch, 3); OUT_BATCH(batch, CMD_STATE_SIP | 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen8_emit_clip_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* pass-through */ OUT_BATCH(batch, 0); } static void gen8_emit_sf_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 5); OUT_BATCH(batch, GEN8_3DSTATE_RASTER | (5 - 2)); OUT_BATCH(batch, GEN8_3DSTATE_RASTER_CULL_NONE); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 4); OUT_BATCH(batch, GEN7_3DSTATE_SBE | (4 - 2)); OUT_BATCH(batch, (GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH) | (GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET) | (1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) | (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) | (1 << GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); /* SBE for backend setup */ BEGIN_BATCH(batch, 11); OUT_BATCH(batch, GEN8_3DSTATE_SBE_SWIZ | (11 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 4); OUT_BATCH(batch, GEN6_3DSTATE_SF | (4 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); ADVANCE_BATCH(batch); } static void gen8_emit_wm_state(VADriverContextP ctx, int kernel) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; unsigned int num_samples = 0; unsigned int max_threads; max_threads = render_state->max_wm_threads - 2; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN8_3DSTATE_PSEXTRA | (2 - 2)); OUT_BATCH(batch, (GEN8_PSX_PIXEL_SHADER_VALID | GEN8_PSX_ATTRIBUTE_ENABLE)); ADVANCE_BATCH(batch); if (kernel == PS_KERNEL) { BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN8_3DSTATE_PSBLEND | (2 - 2)); OUT_BATCH(batch, GEN8_PS_BLEND_HAS_WRITEABLE_RT); ADVANCE_BATCH(batch); } else if (kernel == PS_SUBPIC_KERNEL) { BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN8_3DSTATE_PSBLEND | (2 - 2)); OUT_BATCH(batch, (GEN8_PS_BLEND_HAS_WRITEABLE_RT | GEN8_PS_BLEND_COLOR_BUFFER_BLEND_ENABLE | (I965_BLENDFACTOR_SRC_ALPHA << GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT) | (I965_BLENDFACTOR_INV_SRC_ALPHA << GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT) | (I965_BLENDFACTOR_SRC_ALPHA << GEN8_PS_BLEND_SRC_BLEND_FACTOR_SHIFT) | (I965_BLENDFACTOR_INV_SRC_ALPHA << GEN8_PS_BLEND_DST_BLEND_FACTOR_SHIFT))); ADVANCE_BATCH(batch); } BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN6_3DSTATE_WM | (2 - 2)); OUT_BATCH(batch, GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 11); OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (11 - 2)); OUT_BATCH(batch, URB_CS_ENTRY_SIZE); OUT_BATCH(batch, 0); /*DW3-4. Constant buffer 0 */ OUT_BATCH(batch, render_state->curbe_offset); OUT_BATCH(batch, 0); /*DW5-10. Constant buffer 1-3 */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 12); OUT_BATCH(batch, GEN7_3DSTATE_PS | (12 - 2)); /* PS shader address */ OUT_BATCH(batch, render_state->render_kernels[kernel].kernel_offset); OUT_BATCH(batch, 0); /* DW3. PS shader flag .Binding table cnt/sample cnt */ OUT_BATCH(batch, (1 << GEN7_PS_SAMPLER_COUNT_SHIFT) | (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); /* DW4-5. Scatch space */ OUT_BATCH(batch, 0); /* scratch space base offset */ OUT_BATCH(batch, 0); /* DW6. PS shader threads. */ OUT_BATCH(batch, ((max_threads - 1) << GEN8_PS_MAX_THREADS_SHIFT) | num_samples | GEN7_PS_PUSH_CONSTANT_ENABLE | GEN7_PS_16_DISPATCH_ENABLE); /* DW7. PS shader GRF */ OUT_BATCH(batch, (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0)); OUT_BATCH(batch, 0); /* kernel 1 pointer */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* kernel 2 pointer */ OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2)); OUT_BATCH(batch, BINDING_TABLE_OFFSET); ADVANCE_BATCH(batch); } static void gen8_emit_depth_buffer_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 8); OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_BUFFER | (8 - 2)); OUT_BATCH(batch, (I965_DEPTHFORMAT_D32_FLOAT << 18) | (I965_SURFACE_NULL << 29)); /* DW2-3. Depth Buffer Address */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* DW4-7. Surface structure */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); /* Update the Hier Depth buffer */ BEGIN_BATCH(batch, 5); OUT_BATCH(batch, GEN7_3DSTATE_HIER_DEPTH_BUFFER | (5 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); /* Update the stencil buffer */ BEGIN_BATCH(batch, 5); OUT_BATCH(batch, GEN7_3DSTATE_STENCIL_BUFFER | (5 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 3); OUT_BATCH(batch, GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen8_emit_depth_stencil_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 3); OUT_BATCH(batch, GEN8_3DSTATE_WM_DEPTH_STENCIL | (3 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen8_emit_wm_hz_op(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; BEGIN_BATCH(batch, 5); OUT_BATCH(batch, GEN8_3DSTATE_WM_HZ_OP | (5 - 2)); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen8_emit_viewport_state_pointers(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2)); OUT_BATCH(batch, render_state->cc_viewport_offset); ADVANCE_BATCH(batch); BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2)); OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } static void gen8_emit_sampler_state_pointers(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; struct i965_render_state *render_state = &i965->render_state; BEGIN_BATCH(batch, 2); OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2)); OUT_BATCH(batch, render_state->sampler_offset); ADVANCE_BATCH(batch); } static void gen8_render_emit_states(VADriverContextP ctx, int kernel) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; intel_batchbuffer_start_atomic(batch, 0x1000); intel_batchbuffer_emit_mi_flush(batch); gen8_emit_invarient_states(ctx); gen8_emit_state_base_address(ctx); gen8_emit_viewport_state_pointers(ctx); gen8_emit_urb(ctx); gen8_emit_cc_state_pointers(ctx); gen8_emit_sampler_state_pointers(ctx); gen8_emit_wm_hz_op(ctx); gen8_emit_bypass_state(ctx); gen8_emit_vs_state(ctx); gen8_emit_clip_state(ctx); gen8_emit_sf_state(ctx); gen8_emit_depth_stencil_state(ctx); gen8_emit_wm_state(ctx, kernel); gen8_emit_depth_buffer_state(ctx); gen7_emit_drawing_rectangle(ctx); gen8_emit_vertex_element_state(ctx); gen8_emit_vertices(ctx); intel_batchbuffer_end_atomic(batch); } static void gen7_render_put_surface( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect, unsigned int flags ) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; gen7_render_initialize(ctx); gen7_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags); i965_clear_dest_region(ctx); gen7_render_emit_states(ctx, PS_KERNEL); intel_batchbuffer_flush(batch); } static void gen8_render_put_surface( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect, unsigned int flags ) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; gen8_render_initialize(ctx); gen8_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags); gen8_clear_dest_region(ctx); gen8_render_emit_states(ctx, PS_KERNEL); intel_batchbuffer_flush(batch); } static void gen7_subpicture_render_blend_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen6_blend_state *blend_state; dri_bo_unmap(render_state->cc.state); dri_bo_map(render_state->cc.blend, 1); assert(render_state->cc.blend->virtual); blend_state = render_state->cc.blend->virtual; memset(blend_state, 0, sizeof(*blend_state)); blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA; blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA; blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD; blend_state->blend0.blend_enable = 1; blend_state->blend1.post_blend_clamp_enable = 1; blend_state->blend1.pre_blend_clamp_enable = 1; blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */ dri_bo_unmap(render_state->cc.blend); } static void gen8_subpicture_render_blend_state(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; struct gen8_global_blend_state *global_blend_state; struct gen8_blend_state_rt *blend_state; unsigned char *cc_ptr; dri_bo_map(render_state->dynamic_state.bo, 1); assert(render_state->dynamic_state.bo->virtual); cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual + render_state->blend_state_offset; global_blend_state = (struct gen8_global_blend_state*) cc_ptr; memset(global_blend_state, 0, render_state->blend_state_size); /* Global blend state + blend_state for Render Target */ blend_state = (struct gen8_blend_state_rt *)(global_blend_state + 1); blend_state->blend0.color_blend_func = I965_BLENDFUNCTION_ADD; blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA; blend_state->blend0.src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA; blend_state->blend0.alpha_blend_func = I965_BLENDFUNCTION_ADD; blend_state->blend0.ia_dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA; blend_state->blend0.ia_src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA; blend_state->blend0.colorbuf_blend = 1; blend_state->blend1.post_blend_clamp_enable = 1; blend_state->blend1.pre_blend_clamp_enable = 1; blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */ dri_bo_unmap(render_state->dynamic_state.bo); } static void gen7_subpicture_render_setup_states( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect ) { i965_render_dest_surface_state(ctx, 0); i965_subpic_render_src_surfaces_state(ctx, obj_surface); i965_render_sampler(ctx); i965_render_cc_viewport(ctx); gen7_render_color_calc_state(ctx); gen7_subpicture_render_blend_state(ctx); gen7_render_depth_stencil_state(ctx); i965_subpic_render_upload_constants(ctx, obj_surface); i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect); } static void gen8_subpic_render_upload_constants(VADriverContextP ctx, struct object_surface *obj_surface) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; float *constant_buffer; float global_alpha = 1.0; unsigned int index = obj_surface->subpic_render_idx; struct object_subpic *obj_subpic = obj_surface->obj_subpic[index]; unsigned char *cc_ptr; if (obj_subpic->flags & VA_SUBPICTURE_GLOBAL_ALPHA) { global_alpha = obj_subpic->global_alpha; } dri_bo_map(render_state->dynamic_state.bo, 1); assert(render_state->dynamic_state.bo->virtual); cc_ptr = (unsigned char *) render_state->dynamic_state.bo->virtual + render_state->curbe_offset; constant_buffer = (float *) cc_ptr; *constant_buffer = global_alpha; dri_bo_unmap(render_state->dynamic_state.bo); } static void gen8_subpicture_render_setup_states( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect ) { i965_render_dest_surface_state(ctx, 0); i965_subpic_render_src_surfaces_state(ctx, obj_surface); gen8_render_sampler(ctx); gen8_render_cc_viewport(ctx); gen8_render_color_calc_state(ctx); gen8_subpicture_render_blend_state(ctx); gen8_subpic_render_upload_constants(ctx, obj_surface); i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect); } static void gen7_render_put_subpicture( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect ) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; unsigned int index = obj_surface->subpic_render_idx; struct object_subpic *obj_subpic = obj_surface->obj_subpic[index]; assert(obj_subpic); gen7_render_initialize(ctx); gen7_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect); gen7_render_emit_states(ctx, PS_SUBPIC_KERNEL); i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff); intel_batchbuffer_flush(batch); } static void gen8_render_put_subpicture( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect ) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct intel_batchbuffer *batch = i965->batch; unsigned int index = obj_surface->subpic_render_idx; struct object_subpic *obj_subpic = obj_surface->obj_subpic[index]; assert(obj_subpic); gen8_render_initialize(ctx); gen8_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect); gen8_render_emit_states(ctx, PS_SUBPIC_KERNEL); i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff); intel_batchbuffer_flush(batch); } /* * global functions */ VAStatus i965_DestroySurfaces(VADriverContextP ctx, VASurfaceID *surface_list, int num_surfaces); void intel_render_put_surface( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect, unsigned int flags ) { struct i965_driver_data *i965 = i965_driver_data(ctx); int has_done_scaling = 0; VASurfaceID out_surface_id = i965_post_processing(ctx, obj_surface, src_rect, dst_rect, flags, &has_done_scaling); assert((!has_done_scaling) || (out_surface_id != VA_INVALID_ID)); if (out_surface_id != VA_INVALID_ID) { struct object_surface *new_obj_surface = SURFACE(out_surface_id); if (new_obj_surface && new_obj_surface->bo) obj_surface = new_obj_surface; if (has_done_scaling) src_rect = dst_rect; } if (IS_GEN8(i965->intel.device_id)) gen8_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags); else if (IS_GEN7(i965->intel.device_id)) gen7_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags); else if (IS_GEN6(i965->intel.device_id)) gen6_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags); else i965_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags); if (out_surface_id != VA_INVALID_ID) i965_DestroySurfaces(ctx, &out_surface_id, 1); } void intel_render_put_subpicture( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect ) { struct i965_driver_data *i965 = i965_driver_data(ctx); if (IS_GEN8(i965->intel.device_id)) gen8_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect); else if (IS_GEN7(i965->intel.device_id)) gen7_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect); else if (IS_GEN6(i965->intel.device_id)) gen6_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect); else i965_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect); } static bool gen8_render_init(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; int i, kernel_size; unsigned int kernel_offset, end_offset; unsigned char *kernel_ptr; struct i965_kernel *kernel; if (IS_GEN8(i965->intel.device_id)) { memcpy(render_state->render_kernels, render_kernels_gen8, sizeof(render_state->render_kernels)); } kernel_size = 4096; for (i = 0; i < NUM_RENDER_KERNEL; i++) { kernel = &render_state->render_kernels[i]; if (!kernel->size) continue; kernel_size += kernel->size; } render_state->instruction_state.bo = dri_bo_alloc(i965->intel.bufmgr, "kernel shader", kernel_size, 0x1000); if (render_state->instruction_state.bo == NULL) { WARN_ONCE("failure to allocate the buffer space for kernel shader\n"); return false; } assert(render_state->instruction_state.bo); render_state->instruction_state.bo_size = kernel_size; render_state->instruction_state.end_offset = 0; end_offset = 0; dri_bo_map(render_state->instruction_state.bo, 1); kernel_ptr = (unsigned char *)(render_state->instruction_state.bo->virtual); for (i = 0; i < NUM_RENDER_KERNEL; i++) { kernel = &render_state->render_kernels[i]; kernel_offset = end_offset; kernel->kernel_offset = kernel_offset; if (!kernel->size) continue; memcpy(kernel_ptr + kernel_offset, kernel->bin, kernel->size); end_offset += ALIGN(kernel->size, ALIGNMENT); } render_state->instruction_state.end_offset = end_offset; dri_bo_unmap(render_state->instruction_state.bo); if (IS_GEN8(i965->intel.device_id)) { render_state->max_wm_threads = 64; } else { /* should never get here !!! */ assert(0); } return true; } bool i965_render_init(VADriverContextP ctx) { struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; int i; /* kernel */ assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen5) / sizeof(render_kernels_gen5[0]))); assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen6) / sizeof(render_kernels_gen6[0]))); if (IS_GEN8(i965->intel.device_id)) { return gen8_render_init(ctx); } else if (IS_GEN7(i965->intel.device_id)) memcpy(render_state->render_kernels, (IS_HASWELL(i965->intel.device_id) ? render_kernels_gen7_haswell : render_kernels_gen7), sizeof(render_state->render_kernels)); else if (IS_GEN6(i965->intel.device_id)) memcpy(render_state->render_kernels, render_kernels_gen6, sizeof(render_state->render_kernels)); else if (IS_IRONLAKE(i965->intel.device_id)) memcpy(render_state->render_kernels, render_kernels_gen5, sizeof(render_state->render_kernels)); else memcpy(render_state->render_kernels, render_kernels_gen4, sizeof(render_state->render_kernels)); for (i = 0; i < NUM_RENDER_KERNEL; i++) { struct i965_kernel *kernel = &render_state->render_kernels[i]; if (!kernel->size) continue; kernel->bo = dri_bo_alloc(i965->intel.bufmgr, kernel->name, kernel->size, 0x1000); assert(kernel->bo); dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin); } /* constant buffer */ render_state->curbe.bo = dri_bo_alloc(i965->intel.bufmgr, "constant buffer", 4096, 64); assert(render_state->curbe.bo); if (IS_HSW_GT1(i965->intel.device_id)) { render_state->max_wm_threads = 102; } else if (IS_HSW_GT2(i965->intel.device_id)) { render_state->max_wm_threads = 204; } else if (IS_HSW_GT3(i965->intel.device_id)) { render_state->max_wm_threads = 408; } else if (IS_IVB_GT1(i965->intel.device_id) || IS_BAYTRAIL(i965->intel.device_id)) { render_state->max_wm_threads = 48; } else if (IS_IVB_GT2(i965->intel.device_id)) { render_state->max_wm_threads = 172; } else if (IS_SNB_GT1(i965->intel.device_id)) { render_state->max_wm_threads = 40; } else if (IS_SNB_GT2(i965->intel.device_id)) { render_state->max_wm_threads = 80; } else if (IS_IRONLAKE(i965->intel.device_id)) { render_state->max_wm_threads = 72; /* 12 * 6 */ } else if (IS_G4X(i965->intel.device_id)) { render_state->max_wm_threads = 50; /* 12 * 5 */ } else { /* should never get here !!! */ assert(0); } return true; } static void gen8_render_terminate(VADriverContextP ctx) { int i; struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; dri_bo_unreference(render_state->vb.vertex_buffer); render_state->vb.vertex_buffer = NULL; dri_bo_unreference(render_state->wm.surface_state_binding_table_bo); render_state->wm.surface_state_binding_table_bo = NULL; if (render_state->instruction_state.bo) { dri_bo_unreference(render_state->instruction_state.bo); render_state->instruction_state.bo = NULL; } if (render_state->dynamic_state.bo) { dri_bo_unreference(render_state->dynamic_state.bo); render_state->dynamic_state.bo = NULL; } if (render_state->indirect_state.bo) { dri_bo_unreference(render_state->indirect_state.bo); render_state->indirect_state.bo = NULL; } if (render_state->draw_region) { dri_bo_unreference(render_state->draw_region->bo); free(render_state->draw_region); render_state->draw_region = NULL; } } void i965_render_terminate(VADriverContextP ctx) { int i; struct i965_driver_data *i965 = i965_driver_data(ctx); struct i965_render_state *render_state = &i965->render_state; if (IS_GEN8(i965->intel.device_id)) { gen8_render_terminate(ctx); return; } dri_bo_unreference(render_state->curbe.bo); render_state->curbe.bo = NULL; for (i = 0; i < NUM_RENDER_KERNEL; i++) { struct i965_kernel *kernel = &render_state->render_kernels[i]; dri_bo_unreference(kernel->bo); kernel->bo = NULL; } dri_bo_unreference(render_state->vb.vertex_buffer); render_state->vb.vertex_buffer = NULL; dri_bo_unreference(render_state->vs.state); render_state->vs.state = NULL; dri_bo_unreference(render_state->sf.state); render_state->sf.state = NULL; dri_bo_unreference(render_state->wm.sampler); render_state->wm.sampler = NULL; dri_bo_unreference(render_state->wm.state); render_state->wm.state = NULL; dri_bo_unreference(render_state->wm.surface_state_binding_table_bo); dri_bo_unreference(render_state->cc.viewport); render_state->cc.viewport = NULL; dri_bo_unreference(render_state->cc.state); render_state->cc.state = NULL; dri_bo_unreference(render_state->cc.blend); render_state->cc.blend = NULL; dri_bo_unreference(render_state->cc.depth_stencil); render_state->cc.depth_stencil = NULL; if (render_state->draw_region) { dri_bo_unreference(render_state->draw_region->bo); free(render_state->draw_region); render_state->draw_region = NULL; } } intel-driver-1.3.0/src/i965_render.h000066400000000000000000000067741231401140700171210ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * */ #ifndef _I965_RENDER_H_ #define _I965_RENDER_H_ #define MAX_SAMPLERS 16 #define MAX_RENDER_SURFACES (MAX_SAMPLERS + 1) #define NUM_RENDER_KERNEL 3 #define VA_SRC_COLOR_MASK 0x000000f0 #include "i965_post_processing.h" struct i965_kernel; struct i965_render_state { struct { dri_bo *vertex_buffer; } vb; struct { dri_bo *state; } vs; struct { dri_bo *state; } sf; struct { int sampler_count; dri_bo *sampler; dri_bo *state; dri_bo *surface_state_binding_table_bo; } wm; struct { dri_bo *state; dri_bo *viewport; dri_bo *blend; dri_bo *depth_stencil; } cc; struct { dri_bo *bo; } curbe; unsigned short interleaved_uv; unsigned short inited; struct intel_region *draw_region; int pp_flag; /* 0: disable, 1: enable */ struct i965_kernel render_kernels[3]; int max_wm_threads; struct { dri_bo *bo; int bo_size; unsigned int end_offset; } instruction_state; struct { dri_bo *bo; } indirect_state; struct { dri_bo *bo; int bo_size; unsigned int end_offset; } dynamic_state; unsigned int curbe_offset; int curbe_size; unsigned int sampler_offset; int sampler_size; unsigned int cc_viewport_offset; int cc_viewport_size; unsigned int cc_state_offset; int cc_state_size; unsigned int blend_state_offset; int blend_state_size; unsigned int sf_clip_offset; int sf_clip_size; unsigned int scissor_offset; int scissor_size; }; bool i965_render_init(VADriverContextP ctx); void i965_render_terminate(VADriverContextP ctx); void intel_render_put_surface( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect, unsigned int flags ); void intel_render_put_subpicture( VADriverContextP ctx, struct object_surface *obj_surface, const VARectangle *src_rect, const VARectangle *dst_rect ); struct gen7_surface_state; void gen7_render_set_surface_scs(struct gen7_surface_state *ss); struct gen8_surface_state; void gen8_render_set_surface_scs(struct gen8_surface_state *ss); #endif /* _I965_RENDER_H_ */ intel-driver-1.3.0/src/i965_structs.h000066400000000000000000001440561231401140700173450ustar00rootroot00000000000000#ifndef _I965_STRUCTS_H_ #define _I965_STRUCTS_H_ struct i965_vfe_state { struct { unsigned int per_thread_scratch_space:4; unsigned int pad3:3; unsigned int extend_vfe_state_present:1; unsigned int pad2:2; unsigned int scratch_base:22; } vfe0; struct { unsigned int debug_counter_control:2; unsigned int children_present:1; unsigned int vfe_mode:4; unsigned int pad2:2; unsigned int num_urb_entries:7; unsigned int urb_entry_alloc_size:9; unsigned int max_threads:7; } vfe1; struct { unsigned int pad4:4; unsigned int interface_descriptor_base:28; } vfe2; }; struct i965_vfe_state_ex { struct { unsigned int pad:8; unsigned int obj_id:24; } vfex0; union { struct { unsigned int residual_grf_offset:5; unsigned int pad0:3; unsigned int weight_grf_offset:5; unsigned int pad1:3; unsigned int residual_data_offset:8; unsigned int sub_field_present_flag:2; unsigned int residual_data_fix_offset_flag:1; unsigned int pad2:5; } avc; unsigned int vc1; } vfex1; struct { unsigned int remap_index_0:4; unsigned int remap_index_1:4; unsigned int remap_index_2:4; unsigned int remap_index_3:4; unsigned int remap_index_4:4; unsigned int remap_index_5:4; unsigned int remap_index_6:4; unsigned int remap_index_7:4; }remap_table0; struct { unsigned int remap_index_8:4; unsigned int remap_index_9:4; unsigned int remap_index_10:4; unsigned int remap_index_11:4; unsigned int remap_index_12:4; unsigned int remap_index_13:4; unsigned int remap_index_14:4; unsigned int remap_index_15:4; } remap_table1; struct { unsigned int mask:8; unsigned int pad:22; unsigned int type:1; unsigned int enable:1; } scoreboard0; struct { int delta_x0:4; int delta_y0:4; int delta_x1:4; int delta_y1:4; int delta_x2:4; int delta_y2:4; int delta_x3:4; int delta_y3:4; } scoreboard1; struct { int delta_x4:4; int delta_y4:4; int delta_x5:4; int delta_y5:4; int delta_x6:4; int delta_y6:4; int delta_x7:4; int delta_y7:4; } scoreboard2; unsigned int pad; }; struct i965_vld_state { struct { unsigned int pad6:6; unsigned int scan_order:1; unsigned int intra_vlc_format:1; unsigned int quantizer_scale_type:1; unsigned int concealment_motion_vector:1; unsigned int frame_predict_frame_dct:1; unsigned int top_field_first:1; unsigned int picture_structure:2; unsigned int intra_dc_precision:2; unsigned int f_code_0_0:4; unsigned int f_code_0_1:4; unsigned int f_code_1_0:4; unsigned int f_code_1_1:4; } vld0; struct { unsigned int pad2:9; unsigned int picture_coding_type:2; unsigned int pad:21; } vld1; struct { unsigned int index_0:4; unsigned int index_1:4; unsigned int index_2:4; unsigned int index_3:4; unsigned int index_4:4; unsigned int index_5:4; unsigned int index_6:4; unsigned int index_7:4; } desc_remap_table0; struct { unsigned int index_8:4; unsigned int index_9:4; unsigned int index_10:4; unsigned int index_11:4; unsigned int index_12:4; unsigned int index_13:4; unsigned int index_14:4; unsigned int index_15:4; } desc_remap_table1; }; struct i965_interface_descriptor { struct { unsigned int grf_reg_blocks:4; unsigned int pad:2; unsigned int kernel_start_pointer:26; } desc0; struct { unsigned int pad:7; unsigned int software_exception:1; unsigned int pad2:3; unsigned int maskstack_exception:1; unsigned int pad3:1; unsigned int illegal_opcode_exception:1; unsigned int pad4:2; unsigned int floating_point_mode:1; unsigned int thread_priority:1; unsigned int single_program_flow:1; unsigned int pad5:1; unsigned int const_urb_entry_read_offset:6; unsigned int const_urb_entry_read_len:6; } desc1; struct { unsigned int pad:2; unsigned int sampler_count:3; unsigned int sampler_state_pointer:27; } desc2; struct { unsigned int binding_table_entry_count:5; unsigned int binding_table_pointer:27; } desc3; }; struct i965_surface_state { struct { unsigned int cube_pos_z:1; unsigned int cube_neg_z:1; unsigned int cube_pos_y:1; unsigned int cube_neg_y:1; unsigned int cube_pos_x:1; unsigned int cube_neg_x:1; unsigned int pad:2; unsigned int render_cache_read_mode:1; unsigned int cube_map_corner_mode:1; unsigned int mipmap_layout_mode:1; unsigned int vert_line_stride_ofs:1; unsigned int vert_line_stride:1; unsigned int color_blend:1; unsigned int writedisable_blue:1; unsigned int writedisable_green:1; unsigned int writedisable_red:1; unsigned int writedisable_alpha:1; unsigned int surface_format:9; unsigned int data_return_format:1; unsigned int pad0:1; unsigned int surface_type:3; } ss0; struct { unsigned int base_addr; } ss1; struct { unsigned int render_target_rotation:2; unsigned int mip_count:4; unsigned int width:13; unsigned int height:13; } ss2; struct { unsigned int tile_walk:1; unsigned int tiled_surface:1; unsigned int pad:1; unsigned int pitch:18; unsigned int depth:11; } ss3; struct { unsigned int pad:19; unsigned int min_array_elt:9; unsigned int min_lod:4; } ss4; struct { unsigned int pad:20; unsigned int y_offset:4; unsigned int pad2:1; unsigned int x_offset:7; } ss5; }; struct thread0 { unsigned int pad0:1; unsigned int grf_reg_count:3; unsigned int pad1:2; unsigned int kernel_start_pointer:26; }; struct thread1 { unsigned int ext_halt_exception_enable:1; unsigned int sw_exception_enable:1; unsigned int mask_stack_exception_enable:1; unsigned int timeout_exception_enable:1; unsigned int illegal_op_exception_enable:1; unsigned int pad0:3; unsigned int depth_coef_urb_read_offset:6; /* WM only */ unsigned int pad1:2; unsigned int floating_point_mode:1; unsigned int thread_priority:1; unsigned int binding_table_entry_count:8; unsigned int pad3:5; unsigned int single_program_flow:1; }; struct thread2 { unsigned int per_thread_scratch_space:4; unsigned int pad0:6; unsigned int scratch_space_base_pointer:22; }; struct thread3 { unsigned int dispatch_grf_start_reg:4; unsigned int urb_entry_read_offset:6; unsigned int pad0:1; unsigned int urb_entry_read_length:6; unsigned int pad1:1; unsigned int const_urb_entry_read_offset:6; unsigned int pad2:1; unsigned int const_urb_entry_read_length:6; unsigned int pad3:1; }; struct i965_vs_unit_state { struct thread0 thread0; struct thread1 thread1; struct thread2 thread2; struct thread3 thread3; struct { unsigned int pad0:10; unsigned int stats_enable:1; unsigned int nr_urb_entries:7; unsigned int pad1:1; unsigned int urb_entry_allocation_size:5; unsigned int pad2:1; unsigned int max_threads:4; unsigned int pad3:3; } thread4; struct { unsigned int sampler_count:3; unsigned int pad0:2; unsigned int sampler_state_pointer:27; } vs5; struct { unsigned int vs_enable:1; unsigned int vert_cache_disable:1; unsigned int pad0:30; } vs6; }; struct i965_gs_unit_state { struct thread0 thread0; struct thread1 thread1; struct thread2 thread2; struct thread3 thread3; struct { unsigned int pad0:10; unsigned int stats_enable:1; unsigned int nr_urb_entries:7; unsigned int pad1:1; unsigned int urb_entry_allocation_size:5; unsigned int pad2:1; unsigned int max_threads:1; unsigned int pad3:6; } thread4; struct { unsigned int sampler_count:3; unsigned int pad0:2; unsigned int sampler_state_pointer:27; } gs5; struct { unsigned int max_vp_index:4; unsigned int pad0:26; unsigned int reorder_enable:1; unsigned int pad1:1; } gs6; }; struct i965_clip_unit_state { struct thread0 thread0; struct thread1 thread1; struct thread2 thread2; struct thread3 thread3; struct { unsigned int pad0:9; unsigned int gs_output_stats:1; /* not always */ unsigned int stats_enable:1; unsigned int nr_urb_entries:7; unsigned int pad1:1; unsigned int urb_entry_allocation_size:5; unsigned int pad2:1; unsigned int max_threads:6; /* may be less */ unsigned int pad3:1; } thread4; struct { unsigned int pad0:13; unsigned int clip_mode:3; unsigned int userclip_enable_flags:8; unsigned int userclip_must_clip:1; unsigned int pad1:1; unsigned int guard_band_enable:1; unsigned int viewport_z_clip_enable:1; unsigned int viewport_xy_clip_enable:1; unsigned int vertex_position_space:1; unsigned int api_mode:1; unsigned int pad2:1; } clip5; struct { unsigned int pad0:5; unsigned int clipper_viewport_state_ptr:27; } clip6; float viewport_xmin; float viewport_xmax; float viewport_ymin; float viewport_ymax; }; struct i965_sf_unit_state { struct thread0 thread0; struct { unsigned int pad0:7; unsigned int sw_exception_enable:1; unsigned int pad1:3; unsigned int mask_stack_exception_enable:1; unsigned int pad2:1; unsigned int illegal_op_exception_enable:1; unsigned int pad3:2; unsigned int floating_point_mode:1; unsigned int thread_priority:1; unsigned int binding_table_entry_count:8; unsigned int pad4:5; unsigned int single_program_flow:1; } sf1; struct thread2 thread2; struct thread3 thread3; struct { unsigned int pad0:10; unsigned int stats_enable:1; unsigned int nr_urb_entries:7; unsigned int pad1:1; unsigned int urb_entry_allocation_size:5; unsigned int pad2:1; unsigned int max_threads:6; unsigned int pad3:1; } thread4; struct { unsigned int front_winding:1; unsigned int viewport_transform:1; unsigned int pad0:3; unsigned int sf_viewport_state_offset:27; } sf5; struct { unsigned int pad0:9; unsigned int dest_org_vbias:4; unsigned int dest_org_hbias:4; unsigned int scissor:1; unsigned int disable_2x2_trifilter:1; unsigned int disable_zero_pix_trifilter:1; unsigned int point_rast_rule:2; unsigned int line_endcap_aa_region_width:2; unsigned int line_width:4; unsigned int fast_scissor_disable:1; unsigned int cull_mode:2; unsigned int aa_enable:1; } sf6; struct { unsigned int point_size:11; unsigned int use_point_size_state:1; unsigned int subpixel_precision:1; unsigned int sprite_point:1; unsigned int pad0:11; unsigned int trifan_pv:2; unsigned int linestrip_pv:2; unsigned int tristrip_pv:2; unsigned int line_last_pixel_enable:1; } sf7; }; struct i965_sampler_state { struct { unsigned int shadow_function:3; unsigned int lod_bias:11; unsigned int min_filter:3; unsigned int mag_filter:3; unsigned int mip_filter:2; unsigned int base_level:5; unsigned int pad:1; unsigned int lod_preclamp:1; unsigned int border_color_mode:1; unsigned int pad0:1; unsigned int disable:1; } ss0; struct { unsigned int r_wrap_mode:3; unsigned int t_wrap_mode:3; unsigned int s_wrap_mode:3; unsigned int pad:3; unsigned int max_lod:10; unsigned int min_lod:10; } ss1; struct { unsigned int pad:5; unsigned int border_color_pointer:27; } ss2; struct { unsigned int pad:19; unsigned int max_aniso:3; unsigned int chroma_key_mode:1; unsigned int chroma_key_index:2; unsigned int chroma_key_enable:1; unsigned int monochrome_filter_width:3; unsigned int monochrome_filter_height:3; } ss3; }; struct i965_wm_unit_state { struct thread0 thread0; struct thread1 thread1; struct thread2 thread2; struct thread3 thread3; struct { unsigned int stats_enable:1; unsigned int pad0:1; unsigned int sampler_count:3; unsigned int sampler_state_pointer:27; } wm4; struct { unsigned int enable_8_pix:1; unsigned int enable_16_pix:1; unsigned int enable_32_pix:1; unsigned int pad0:7; unsigned int legacy_global_depth_bias:1; unsigned int line_stipple:1; unsigned int depth_offset:1; unsigned int polygon_stipple:1; unsigned int line_aa_region_width:2; unsigned int line_endcap_aa_region_width:2; unsigned int early_depth_test:1; unsigned int thread_dispatch_enable:1; unsigned int program_uses_depth:1; unsigned int program_computes_depth:1; unsigned int program_uses_killpixel:1; unsigned int legacy_line_rast: 1; unsigned int transposed_urb_read:1; unsigned int max_threads:7; } wm5; float global_depth_offset_constant; float global_depth_offset_scale; }; struct i965_cc_viewport { float min_depth; float max_depth; }; struct i965_cc_unit_state { struct { unsigned int pad0:3; unsigned int bf_stencil_pass_depth_pass_op:3; unsigned int bf_stencil_pass_depth_fail_op:3; unsigned int bf_stencil_fail_op:3; unsigned int bf_stencil_func:3; unsigned int bf_stencil_enable:1; unsigned int pad1:2; unsigned int stencil_write_enable:1; unsigned int stencil_pass_depth_pass_op:3; unsigned int stencil_pass_depth_fail_op:3; unsigned int stencil_fail_op:3; unsigned int stencil_func:3; unsigned int stencil_enable:1; } cc0; struct { unsigned int bf_stencil_ref:8; unsigned int stencil_write_mask:8; unsigned int stencil_test_mask:8; unsigned int stencil_ref:8; } cc1; struct { unsigned int logicop_enable:1; unsigned int pad0:10; unsigned int depth_write_enable:1; unsigned int depth_test_function:3; unsigned int depth_test:1; unsigned int bf_stencil_write_mask:8; unsigned int bf_stencil_test_mask:8; } cc2; struct { unsigned int pad0:8; unsigned int alpha_test_func:3; unsigned int alpha_test:1; unsigned int blend_enable:1; unsigned int ia_blend_enable:1; unsigned int pad1:1; unsigned int alpha_test_format:1; unsigned int pad2:16; } cc3; struct { unsigned int pad0:5; unsigned int cc_viewport_state_offset:27; } cc4; struct { unsigned int pad0:2; unsigned int ia_dest_blend_factor:5; unsigned int ia_src_blend_factor:5; unsigned int ia_blend_function:3; unsigned int statistics_enable:1; unsigned int logicop_func:4; unsigned int pad1:11; unsigned int dither_enable:1; } cc5; struct { unsigned int clamp_post_alpha_blend:1; unsigned int clamp_pre_alpha_blend:1; unsigned int clamp_range:2; unsigned int pad0:11; unsigned int y_dither_offset:2; unsigned int x_dither_offset:2; unsigned int dest_blend_factor:5; unsigned int src_blend_factor:5; unsigned int blend_function:3; } cc6; struct { union { float f; unsigned char ub[4]; } alpha_ref; } cc7; }; struct i965_sampler_8x8 { struct { unsigned int pad0:16; unsigned int chroma_key_index:2; unsigned int chroma_key_enable:1; unsigned int pad1:8; unsigned int ief_filter_size:1; unsigned int ief_filter_type:1; unsigned int ief_bypass:1; unsigned int pad2:1; unsigned int avs_filter_type:1; } dw0; struct { unsigned int pad0:5; unsigned int sampler_8x8_state_pointer:27; } dw1; struct { unsigned int weak_edge_threshold:4; unsigned int strong_edge_threshold:4; unsigned int global_noise_estimation:8; unsigned int pad0:16; } dw2; struct { unsigned int r3x_coefficient:5; unsigned int pad0:1; unsigned int r3c_coefficient:5; unsigned int pad1:3; unsigned int gain_factor:6; unsigned int non_edge_weight:3; unsigned int pad2:1; unsigned int regular_weight:3; unsigned int pad3:1; unsigned int strong_edge_weight:3; unsigned int pad4:1; } dw3; struct { unsigned int pad0:2; unsigned int mr_boost:1; unsigned int mr_threshold:4; unsigned int steepness_boost:1; unsigned int steepness_threshold:4; unsigned int pad1:2; unsigned int r5x_coefficient:5; unsigned int pad2:1; unsigned int r5cx_coefficient:5; unsigned int pad3:1; unsigned int r5c_coefficient:5; unsigned int pad4:1; } dw4; struct { unsigned int pwl1_point_1:8; unsigned int pwl1_point_2:8; unsigned int pwl1_point_3:8; unsigned int pwl1_point_4:8; } dw5; struct { unsigned int pwl1_point_5:8; unsigned int pwl1_point_6:8; unsigned int pwl1_r3_bias_0:8; unsigned int pwl1_r3_bias_1:8; } dw6; struct { unsigned int pwl1_r3_bias_2:8; unsigned int pwl1_r3_bias_3:8; unsigned int pwl1_r3_bias_4:8; unsigned int pwl1_r3_bias_5:8; } dw7; struct { unsigned int pwl1_r3_bias_6:8; unsigned int pwl1_r5_bias_0:8; unsigned int pwl1_r5_bias_1:8; unsigned int pwl1_r5_bias_2:8; } dw8; struct { unsigned int pwl1_r5_bias_3:8; unsigned int pwl1_r5_bias_4:8; unsigned int pwl1_r5_bias_5:8; unsigned int pwl1_r5_bias_6:8; } dw9; struct { int pwl1_r3_slope_0:8; int pwl1_r3_slope_1:8; int pwl1_r3_slope_2:8; int pwl1_r3_slope_3:8; } dw10; struct { int pwl1_r3_slope_4:8; int pwl1_r3_slope_5:8; int pwl1_r3_slope_6:8; int pwl1_r5_slope_0:8; } dw11; struct { int pwl1_r5_slope_1:8; int pwl1_r5_slope_2:8; int pwl1_r5_slope_3:8; int pwl1_r5_slope_4:8; } dw12; struct { int pwl1_r5_slope_5:8; int pwl1_r5_slope_6:8; unsigned int limiter_boost:4; unsigned int pad0:4; unsigned int minimum_limiter:4; unsigned int maximum_limiter:4; } dw13; struct { unsigned int pad0:8; unsigned int clip_limiter:10; unsigned int pad1:14; } dw14; unsigned int dw15; /* Just a pad */ }; struct i965_sampler_8x8_coefficient { struct { int table_0x_filter_c0:8; int table_0x_filter_c1:8; int table_0x_filter_c2:8; int table_0x_filter_c3:8; } dw0; struct { int table_0x_filter_c4:8; int table_0x_filter_c5:8; int table_0x_filter_c6:8; int table_0x_filter_c7:8; } dw1; struct { int table_0y_filter_c0:8; int table_0y_filter_c1:8; int table_0y_filter_c2:8; int table_0y_filter_c3:8; } dw2; struct { int table_0y_filter_c4:8; int table_0y_filter_c5:8; int table_0y_filter_c6:8; int table_0y_filter_c7:8; } dw3; struct { int table_1x_filter_c0:8; int table_1x_filter_c1:8; int table_1x_filter_c2:8; int table_1x_filter_c3:8; } dw4; struct { int table_1x_filter_c4:8; int table_1x_filter_c5:8; int table_1x_filter_c6:8; int table_1x_filter_c7:8; } dw5; struct { int table_1y_filter_c0:8; int table_1y_filter_c1:8; int table_1y_filter_c2:8; int table_1y_filter_c3:8; } dw6; struct { int table_1y_filter_c4:8; int table_1y_filter_c5:8; int table_1y_filter_c6:8; int table_1y_filter_c7:8; } dw7; }; struct i965_sampler_8x8_state { struct i965_sampler_8x8_coefficient coefficients[17]; struct { unsigned int transition_area_with_8_pixels:3; unsigned int pad0:1; unsigned int transition_area_with_4_pixels:3; unsigned int pad1:1; unsigned int max_derivative_8_pixels:8; unsigned int max_derivative_4_pixels:8; unsigned int default_sharpness_level:8; } dw136; struct { unsigned int bit_field_name:1; unsigned int adaptive_filter_for_all_channel:1; unsigned int pad0:19; unsigned int bypass_y_adaptive_filtering:1; unsigned int bypass_x_adaptive_filtering:1; unsigned int pad1:9; } dw137; }; struct i965_surface_state2 { struct { unsigned int surface_base_address; } ss0; struct { unsigned int cbcr_pixel_offset_v_direction:2; unsigned int pad0:4; unsigned int width:13; unsigned int height:13; } ss1; struct { unsigned int tile_walk:1; unsigned int tiled_surface:1; unsigned int half_pitch_for_chroma:1; unsigned int pitch:17; unsigned int pad0:2; unsigned int surface_object_control_data:4; unsigned int pad1:1; unsigned int interleave_chroma:1; unsigned int surface_format:4; } ss2; struct { unsigned int y_offset_for_cb:13; unsigned int pad0:3; unsigned int x_offset_for_cb:13; unsigned int pad1:3; } ss3; struct { unsigned int y_offset_for_cr:13; unsigned int pad0:3; unsigned int x_offset_for_cr:13; unsigned int pad1:3; } ss4; }; struct i965_sampler_dndi { struct { unsigned int denoise_asd_threshold:8; unsigned int denoise_history_delta:8; unsigned int denoise_maximum_history:8; unsigned int denoise_stad_threshold:8; } dw0; struct { unsigned int denoise_threshold_for_sum_of_complexity_measure:8; unsigned int denoise_moving_pixel_threshold:5; unsigned int stmm_c2:3; unsigned int low_temporal_difference_threshold:6; unsigned int pad0:2; unsigned int temporal_difference_threshold:6; unsigned int pad1:2; } dw1; struct { unsigned int block_noise_estimate_noise_threshold:8; unsigned int block_noise_estimate_edge_threshold:8; unsigned int denoise_edge_threshold:8; unsigned int good_neighbor_threshold:8; } dw2; struct { unsigned int maximum_stmm:8; unsigned int multipler_for_vecm:6; unsigned int pad0:2; unsigned int blending_constant_across_time_for_small_values_of_stmm:8; unsigned int blending_constant_across_time_for_large_values_of_stmm:7; unsigned int stmm_blending_constant_select:1; } dw3; struct { unsigned int sdi_delta:8; unsigned int sdi_threshold:8; unsigned int stmm_output_shift:4; unsigned int stmm_shift_up:2; unsigned int stmm_shift_down:2; unsigned int minimum_stmm:8; } dw4; struct { unsigned int fmd_temporal_difference_threshold:8; unsigned int sdi_fallback_mode_2_constant:8; unsigned int sdi_fallback_mode_1_t2_constant:8; unsigned int sdi_fallback_mode_1_t1_constant:8; } dw5; struct { unsigned int dn_enable:1; unsigned int di_enable:1; unsigned int di_partial:1; unsigned int dndi_top_first:1; unsigned int dndi_stream_id:1; unsigned int dndi_first_frame:1; unsigned int progressive_dn:1; unsigned int pad0:1; unsigned int fmd_tear_threshold:6; unsigned int pad1:2; unsigned int fmd2_vertical_difference_threshold:8; unsigned int fmd1_vertical_difference_threshold:8; } dw6; struct { unsigned int pad0:8; unsigned int fmd_for_1st_field_of_current_frame:2; unsigned int pad1:6; unsigned int fmd_for_2nd_field_of_previous_frame:2; unsigned int vdi_walker_enable:1; unsigned int pad2:4; unsigned int column_width_minus1:9; } dw7; }; struct gen8_interface_descriptor_data { struct { unsigned int pad0:6; unsigned int kernel_start_pointer:26; } desc0; struct { unsigned int kernel_start_pointer_high:16; unsigned int pad0:16; } desc1; struct { unsigned int pad0:7; unsigned int software_exception_enable:1; unsigned int pad1:3; unsigned int maskstack_exception_enable:1; unsigned int pad2:1; unsigned int illegal_opcode_exception_enable:1; unsigned int pad3:2; unsigned int floating_point_mode:1; unsigned int thread_priority:1; unsigned int single_program_flow:1; unsigned int denorm_mode:1; unsigned int pad4:12; } desc2; struct { unsigned int pad0:2; unsigned int sampler_count:3; unsigned int sampler_state_pointer:27; } desc3; struct { unsigned int binding_table_entry_count:5; unsigned int binding_table_pointer:11; unsigned int pad0: 16; } desc4; struct { unsigned int constant_urb_entry_read_offset:16; unsigned int constant_urb_entry_read_length:16; } desc5; struct { unsigned int num_threads_in_tg:10; unsigned int pad0:5; unsigned int global_barrier_enable:1; unsigned int shared_local_memory_size:5; unsigned int barrier_enable:1; unsigned int rounding_mode:2; unsigned int pad1:8; } desc6; struct { unsigned int cross_thread_constant_data_read_length:8; unsigned int pad0:24; } desc7; }; struct gen8_surface_state { struct { unsigned int cube_pos_z:1; unsigned int cube_neg_z:1; unsigned int cube_pos_y:1; unsigned int cube_neg_y:1; unsigned int cube_pos_x:1; unsigned int cube_neg_x:1; unsigned int media_boundary_pixel_mode:2; unsigned int render_cache_read_write:1; unsigned int sampler_l2bypass_disable:1; unsigned int vert_line_stride_ofs:1; unsigned int vert_line_stride:1; unsigned int tile_walk:1; unsigned int tiled_surface:1; unsigned int horizontal_alignment:2; /* Field 16 */ unsigned int vertical_alignment:2; unsigned int surface_format:9; /**< BRW_SURFACEFORMAT_x */ unsigned int pad0:1; unsigned int is_array:1; unsigned int surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */ } ss0; struct { unsigned int surface_qpitch:15; unsigned int pad0:4; unsigned int base_mip_level:5; unsigned int surface_mocs:7; unsigned int pad1:1; } ss1; struct { unsigned int width:14; unsigned int pad0:2; unsigned int height:14; unsigned int pad1:2; } ss2; struct { unsigned int pitch:18; unsigned int pad:3; unsigned int depth:11; } ss3; struct { unsigned int multisample_position_palette_index:3; unsigned int num_multisamples:3; unsigned int multisampled_surface_storage_format:1; unsigned int render_target_view_extent:11; unsigned int min_array_elt:11; unsigned int rotation:2; unsigned int force_ncmp_reduce_type:1; } ss4; struct { unsigned int mip_count:4; unsigned int min_lod:4; unsigned int pad0:4; unsigned int pad1:2; unsigned int coherence_type:1; unsigned int pad2:3; unsigned int pad3:2; unsigned int ewa_disable_cube:1; unsigned int y_offset:3; unsigned int pad4:1; unsigned int x_offset:7; } ss5; struct { unsigned int y_offset_uv_plane:14; unsigned int pad0:2; unsigned int x_offset_uv_plane:14; unsigned int pad1:1; unsigned int separate_uv_plane:1; } ss6; struct { unsigned int resource_min_lod:12; unsigned int pad0:4; unsigned int shader_chanel_select_a:3; unsigned int shader_chanel_select_b:3; unsigned int shader_chanel_select_g:3; unsigned int shader_chanel_select_r:3; unsigned int alpha_clear_color:1; unsigned int blue_clear_color:1; unsigned int green_clear_color:1; unsigned int red_clear_color:1; } ss7; struct { unsigned int base_addr; } ss8; struct { unsigned int base_addr_high:16; unsigned int pad0:16; } ss9; struct { unsigned int pad0:12; unsigned int aux_base_addr:20; } ss10; union { struct { unsigned int y_offset_v_plane:14; unsigned int pad0:2; unsigned int x_offset_v_plane:14; unsigned int pad1:2; } planar; struct { unsigned int aux_base_addr_high:16; unsigned int pad2:16; } aux_buffer; } ss11; struct { unsigned int hier_depth_clear; } ss12; struct { unsigned int pad0; } ss13; struct { unsigned int pad0; } ss14; struct { unsigned int pad0; } ss15; }; struct gen8_surface_state2 { struct { unsigned int pad0; } ss0; struct { unsigned int cbcr_pixel_offset_v_direction:2; unsigned int picture_structure:2; unsigned int width:14; unsigned int height:14; } ss1; struct { unsigned int tile_walk:1; unsigned int tiled_surface:1; unsigned int half_pitch_for_chroma:1; unsigned int pitch:18; unsigned int address_ctrl:1; /* clamp or mirror mode */ unsigned int pad0:4; unsigned int interleave_chroma:1; unsigned int surface_format:5; } ss2; struct { unsigned int y_offset_for_cb:14; unsigned int pad0:2; unsigned int x_offset_for_cb:14; unsigned int pad1:2; } ss3; struct { unsigned int y_offset_for_cr:15; unsigned int pad0:1; unsigned int x_offset_for_cr:14; unsigned int pad1:2; } ss4; struct { unsigned int surface_object_mocs:7; unsigned int pad0:11; unsigned int pad1:2; unsigned int pad2:10; unsigned int vert_line_stride_offset:1; unsigned int vert_line_stride:1; } ss5; struct { unsigned int base_addr; } ss6; struct { unsigned int base_addr_high:16; unsigned int pad0:16; } ss7; }; struct gen8_sampler_state { struct { unsigned int aniso_algorithm:1; unsigned int lod_bias:13; unsigned int min_filter:3; unsigned int mag_filter:3; unsigned int mip_filter:2; unsigned int base_level:5; unsigned int lod_preclamp:2; unsigned int default_color_mode:1; unsigned int pad0:1; unsigned int disable:1; } ss0; struct { unsigned int cube_control_mode:1; unsigned int shadow_function:3; unsigned int chroma_key_mode:1; unsigned int chroma_key_index:2; unsigned int chroma_key_enable:1; unsigned int max_lod:12; unsigned int min_lod:12; } ss1; struct { unsigned int lod_clamp_mag_mode:1; /* MIPNONE or MIPFILTER */ unsigned int flex_filter_vert_align:1; unsigned int flex_filter_hort_align:1; unsigned int flex_filter_coff_size:1; /* coff8 or coff 16 */ unsigned int flex_filter_mode:1; unsigned int pad0:1; unsigned int indirect_state_pointer:18; /* point to the SAMPLE_INDIRECT_STATE */ union { unsigned char nonsep_filter_footer_highmask; struct { unsigned char pad1:2; unsigned char sep_filter_height:2; unsigned char sep_filter_width:2; unsigned char sep_filter_coff_size:2; } sep_filter; } ss2_byte3; } ss2; struct { unsigned int r_wrap_mode:3; unsigned int t_wrap_mode:3; unsigned int s_wrap_mode:3; unsigned int pad0:1; unsigned int non_normalized_coord:1; unsigned int trilinear_quality:2; unsigned int address_round:6; unsigned int max_aniso:3; unsigned int pad1:2; unsigned int nonsep_filter_foot_lowmask:8; } ss3; }; struct gen8_global_blend_state { unsigned int pad0:19; unsigned int ydither_offset:2; unsigned int xdither_offset:2; unsigned int color_dither_enable:1; unsigned int alpha_test_func:3; unsigned int alpha_test_enable:1; unsigned int alpha_to_coverage_dither:1; unsigned int alpha_to_one:1; unsigned int ia_blend_enable:1; unsigned int alpha_to_coverage:1; }; struct gen8_blend_state_rt { struct { unsigned int blue_write_dis:1; unsigned int green_write_dis:1; unsigned int red_write_dis:1; unsigned int alpha_write_dis:1; unsigned int pad0:1; unsigned int alpha_blend_func:3; unsigned int ia_dest_blend_factor:5; unsigned int ia_src_blend_factor:5; unsigned int color_blend_func:3; unsigned int dest_blend_factor:5; unsigned int src_blend_factor:5; unsigned int colorbuf_blend:1; } blend0; struct { unsigned int post_blend_clamp_enable:1; unsigned int pre_blend_clamp_enable:1; unsigned int clamp_range:2; unsigned int pre_blend_src_clamp:1; unsigned int pad0:22; unsigned int logic_op_func:4; unsigned int logic_op_enable:1; } blend1; }; /* TODO: Add the sampler_8x8 for Gen8+. * AVS/Convolve is 256DWs. * MinMaxfilter/Erode/Dilate: 8DWs*/ struct gen6_blend_state { struct { unsigned int dest_blend_factor:5; unsigned int source_blend_factor:5; unsigned int pad3:1; unsigned int blend_func:3; unsigned int pad2:1; unsigned int ia_dest_blend_factor:5; unsigned int ia_source_blend_factor:5; unsigned int pad1:1; unsigned int ia_blend_func:3; unsigned int pad0:1; unsigned int ia_blend_enable:1; unsigned int blend_enable:1; } blend0; struct { unsigned int post_blend_clamp_enable:1; unsigned int pre_blend_clamp_enable:1; unsigned int clamp_range:2; unsigned int pad0:4; unsigned int x_dither_offset:2; unsigned int y_dither_offset:2; unsigned int dither_enable:1; unsigned int alpha_test_func:3; unsigned int alpha_test_enable:1; unsigned int pad1:1; unsigned int logic_op_func:4; unsigned int logic_op_enable:1; unsigned int pad2:1; unsigned int write_disable_b:1; unsigned int write_disable_g:1; unsigned int write_disable_r:1; unsigned int write_disable_a:1; unsigned int pad3:1; unsigned int alpha_to_coverage_dither:1; unsigned int alpha_to_one:1; unsigned int alpha_to_coverage:1; } blend1; }; struct gen6_color_calc_state { struct { unsigned int alpha_test_format:1; unsigned int pad0:14; unsigned int round_disable:1; unsigned int bf_stencil_ref:8; unsigned int stencil_ref:8; } cc0; union { float alpha_ref_f; struct { unsigned int ui:8; unsigned int pad0:24; } alpha_ref_fi; } cc1; float constant_r; float constant_g; float constant_b; float constant_a; }; struct gen6_depth_stencil_state { struct { unsigned int pad0:3; unsigned int bf_stencil_pass_depth_pass_op:3; unsigned int bf_stencil_pass_depth_fail_op:3; unsigned int bf_stencil_fail_op:3; unsigned int bf_stencil_func:3; unsigned int bf_stencil_enable:1; unsigned int pad1:2; unsigned int stencil_write_enable:1; unsigned int stencil_pass_depth_pass_op:3; unsigned int stencil_pass_depth_fail_op:3; unsigned int stencil_fail_op:3; unsigned int stencil_func:3; unsigned int stencil_enable:1; } ds0; struct { unsigned int bf_stencil_write_mask:8; unsigned int bf_stencil_test_mask:8; unsigned int stencil_write_mask:8; unsigned int stencil_test_mask:8; } ds1; struct { unsigned int pad0:26; unsigned int depth_write_enable:1; unsigned int depth_test_func:3; unsigned int pad1:1; unsigned int depth_test_enable:1; } ds2; }; struct gen6_interface_descriptor_data { struct { unsigned int pad0:6; unsigned int kernel_start_pointer:26; } desc0; struct { unsigned int pad0:7; unsigned int software_exception_enable:1; unsigned int pad1:3; unsigned int maskstack_exception_enable:1; unsigned int pad2:1; unsigned int illegal_opcode_exception_enable:1; unsigned int pad3:2; unsigned int floating_point_mode:1; unsigned int thread_priority:1; unsigned int single_program_flow:1; unsigned int pad4:13; } desc1; struct { unsigned int pad0:2; unsigned int sampler_count:3; unsigned int sampler_state_pointer:27; } desc2; struct { unsigned int binding_table_entry_count:5; unsigned int binding_table_pointer:27; } desc3; struct { unsigned int constant_urb_entry_read_offset:16; unsigned int constant_urb_entry_read_length:16; } desc4; union { struct { unsigned int num_threads:8; unsigned int barrier_return_byte:8; unsigned int shared_local_memory_size:5; unsigned int barrier_enable:1; unsigned int rounding_mode:2; unsigned int barrier_return_grf_offset:8; } gen7; struct { unsigned int barrier_id:4; unsigned int pad0:28; } gen6; } desc5; struct { unsigned int cross_thread_constant_data_read_length:8; unsigned int pad0:24; } desc6; struct { unsigned int pad0; } desc7; }; struct gen7_surface_state { struct { unsigned int cube_pos_z:1; unsigned int cube_neg_z:1; unsigned int cube_pos_y:1; unsigned int cube_neg_y:1; unsigned int cube_pos_x:1; unsigned int cube_neg_x:1; unsigned int pad2:2; unsigned int render_cache_read_write:1; unsigned int pad1:1; unsigned int surface_array_spacing:1; unsigned int vert_line_stride_ofs:1; unsigned int vert_line_stride:1; unsigned int tile_walk:1; unsigned int tiled_surface:1; unsigned int horizontal_alignment:1; unsigned int vertical_alignment:2; unsigned int surface_format:9; /**< BRW_SURFACEFORMAT_x */ unsigned int pad0:1; unsigned int is_array:1; unsigned int surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */ } ss0; struct { unsigned int base_addr; } ss1; struct { unsigned int width:14; unsigned int pad1:2; unsigned int height:14; unsigned int pad0:2; } ss2; struct { unsigned int pitch:18; unsigned int pad:3; unsigned int depth:11; } ss3; struct { unsigned int multisample_position_palette_index:3; unsigned int num_multisamples:3; unsigned int multisampled_surface_storage_format:1; unsigned int render_target_view_extent:11; unsigned int min_array_elt:11; unsigned int rotation:2; unsigned int pad0:1; } ss4; struct { unsigned int mip_count:4; unsigned int min_lod:4; unsigned int pad1:12; unsigned int y_offset:4; unsigned int pad0:1; unsigned int x_offset:7; } ss5; struct { unsigned int pad; /* Multisample Control Surface stuff */ } ss6; struct { unsigned int resource_min_lod:12; unsigned int pad0:4; unsigned int shader_chanel_select_a:3; unsigned int shader_chanel_select_b:3; unsigned int shader_chanel_select_g:3; unsigned int shader_chanel_select_r:3; unsigned int alpha_clear_color:1; unsigned int blue_clear_color:1; unsigned int green_clear_color:1; unsigned int red_clear_color:1; } ss7; }; struct gen7_sampler_state { struct { unsigned int aniso_algorithm:1; unsigned int lod_bias:13; unsigned int min_filter:3; unsigned int mag_filter:3; unsigned int mip_filter:2; unsigned int base_level:5; unsigned int pad1:1; unsigned int lod_preclamp:1; unsigned int default_color_mode:1; unsigned int pad0:1; unsigned int disable:1; } ss0; struct { unsigned int cube_control_mode:1; unsigned int shadow_function:3; unsigned int pad:4; unsigned int max_lod:12; unsigned int min_lod:12; } ss1; struct { unsigned int pad:5; unsigned int default_color_pointer:27; } ss2; struct { unsigned int r_wrap_mode:3; unsigned int t_wrap_mode:3; unsigned int s_wrap_mode:3; unsigned int pad:1; unsigned int non_normalized_coord:1; unsigned int trilinear_quality:2; unsigned int address_round:6; unsigned int max_aniso:3; unsigned int chroma_key_mode:1; unsigned int chroma_key_index:2; unsigned int chroma_key_enable:1; unsigned int pad0:6; } ss3; }; struct gen7_surface_state2 { struct { unsigned int surface_base_address; } ss0; struct { unsigned int cbcr_pixel_offset_v_direction:2; unsigned int picture_structure:2; unsigned int width:14; unsigned int height:14; } ss1; struct { unsigned int tile_walk:1; unsigned int tiled_surface:1; unsigned int half_pitch_for_chroma:1; unsigned int pitch:18; unsigned int pad0:1; unsigned int surface_object_control_data:4; unsigned int pad1:1; unsigned int interleave_chroma:1; unsigned int surface_format:4; } ss2; struct { unsigned int y_offset_for_cb:15; unsigned int pad0:1; unsigned int x_offset_for_cb:14; unsigned int pad1:2; } ss3; struct { unsigned int y_offset_for_cr:15; unsigned int pad0:1; unsigned int x_offset_for_cr:14; unsigned int pad1:2; } ss4; struct { unsigned int pad0; } ss5; struct { unsigned int pad0; } ss6; struct { unsigned int pad0; } ss7; }; struct gen7_sampler_8x8 { struct { unsigned int global_noise_estimation:8; unsigned int pad0:8; unsigned int chroma_key_index:2; unsigned int chroma_key_enable:1; unsigned int pad1:10; unsigned int ief_bypass:1; unsigned int pad2:1; unsigned int disable_8x8_filter:1; } dw0; struct { unsigned int pad0:5; unsigned int sampler_8x8_state_pointer:27; } dw1; struct { unsigned int weak_edge_threshold:6; unsigned int pad0:2; unsigned int strong_edge_threshold:6; unsigned int pad1:2; unsigned int r5x_coefficient:5; unsigned int r5cx_coefficient:5; unsigned int r5c_coefficient:5; unsigned int pad2:1; } dw2; struct { unsigned int r3x_coefficient:5; unsigned int pad0:1; unsigned int r3c_coefficient:5; unsigned int pad1:3; unsigned int gain_factor:6; unsigned int non_edge_weight:3; unsigned int pad2:1; unsigned int regular_weight:3; unsigned int pad3:1; unsigned int strong_edge_weight:3; unsigned int ief4_smooth_enable:1; } dw3; }; /* This can also be used for BDW+ */ struct gen7_sampler_dndi { struct { unsigned int denoise_asd_threshold:8; unsigned int dnmh_delt:4; unsigned int vdi_walker_y_stride:2; unsigned int vdi_walker_frame_sharing_enable:1; unsigned int pad0:1; unsigned int denoise_maximum_history:8; unsigned int denoise_stad_threshold:8; } dw0; struct { unsigned int denoise_threshold_for_sum_of_complexity_measure:8; unsigned int denoise_moving_pixel_threshold:5; unsigned int stmm_c2:3; unsigned int low_temporal_difference_threshold:6; unsigned int pad0:2; unsigned int temporal_difference_threshold:6; unsigned int pad1:2; } dw1; struct { unsigned int block_noise_estimate_noise_threshold:8; unsigned int bne_edge_th:4; unsigned int pad0:2; unsigned int smooth_mv_th:2; unsigned int sad_tight_th:4; unsigned int cat_slope_minus1:4; unsigned int good_neighbor_th:6; unsigned int pad1:2; } dw2; struct { unsigned int maximum_stmm:8; unsigned int multipler_for_vecm:6; unsigned int pad0:2; unsigned int blending_constant_across_time_for_small_values_of_stmm:8; unsigned int blending_constant_across_time_for_large_values_of_stmm:7; unsigned int stmm_blending_constant_select:1; } dw3; struct { unsigned int sdi_delta:8; unsigned int sdi_threshold:8; unsigned int stmm_output_shift:4; unsigned int stmm_shift_up:2; unsigned int stmm_shift_down:2; unsigned int minimum_stmm:8; } dw4; struct { unsigned int fmd_temporal_difference_threshold:8; unsigned int sdi_fallback_mode_2_constant:8; unsigned int sdi_fallback_mode_1_t2_constant:8; unsigned int sdi_fallback_mode_1_t1_constant:8; } dw5; struct { unsigned int dn_enable:1; unsigned int di_enable:1; unsigned int di_partial:1; unsigned int dndi_top_first:1; unsigned int dndi_stream_id:1; unsigned int dndi_first_frame:1; unsigned int progressive_dn:1; unsigned int mcdi_enable:1; unsigned int fmd_tear_threshold:6; unsigned int cat_th1:2; unsigned int fmd2_vertical_difference_threshold:8; unsigned int fmd1_vertical_difference_threshold:8; } dw6; struct { unsigned int sad_tha:4; unsigned int sad_thb:4; unsigned int fmd_for_1st_field_of_current_frame:2; unsigned int mc_pixel_consistency_th:6; unsigned int fmd_for_2nd_field_of_previous_frame:2; unsigned int vdi_walker_enable:1; unsigned int neighborpixel_th:4; unsigned int column_width_minus1:9; } dw7; }; struct gen8_sampler_8x8_avs { struct { unsigned int gain_factor:6; unsigned int weak_edge_threshold:6; unsigned int strong_edge_threshold:6; unsigned int r3x_coefficient:5; unsigned int r3c_coefficient:5; unsigned int chroma_key_index:2; unsigned int chroma_key_enable:1; unsigned int pad1:1; } dw0; struct { unsigned int pad0; } dw1; struct { unsigned int global_noise_estimation:8; unsigned int non_edge_weight:3; unsigned int regular_weight:3; unsigned int strong_edge_weight:3; unsigned int r5x_coefficient:5; unsigned int r5cx_coefficient:5; unsigned int r5c_coefficient:5; } dw2; struct { unsigned int sin_alpha:8; /* S0.7 */ unsigned int cos_alpha:8; /* S0.7 */ unsigned int sat_max:6; unsigned int hue_max:6; unsigned int enable_8tap_filter:2; unsigned int ief4_smooth_enable:1; unsigned int skin_ief_enable:1; } dw3; struct { unsigned int s3u:11; /* S2.8 */ unsigned int pad0:1; unsigned int diamond_margin:3; unsigned int vy_std_enable:1; unsigned int umid:8; unsigned int vmid:8; } dw4; struct { unsigned int diamond_dv:7; unsigned int diamond_th:6; unsigned int diamond_alpha:8; unsigned int hs_margin:3; unsigned int diamond_du:7; unsigned int skin_detailfilter:1; } dw5; struct { unsigned int y_point1:8; unsigned int y_point2:8; unsigned int y_point3:8; unsigned int y_point4:8; } dw6; struct { unsigned int inv_margin_vyl:16; unsigned int pad0:16; } dw7; struct { unsigned int inv_margin_vyu:16; unsigned int p0l:8; unsigned int p1l:8; } dw8; struct { unsigned int p2l:8; unsigned int p3l:8; unsigned int b0l:8; unsigned int b1l:8; } dw9; struct { unsigned int b2l:8; unsigned int b3l:8; unsigned int s0l:11; unsigned int y_slope2:5; } dw10; struct { unsigned int s1l:11; unsigned int s2l:11; unsigned int pad0:10; } dw11; struct { unsigned int s3l:11; unsigned int p0u:8; unsigned int p1u:8; unsigned int y_slope1:5; } dw12; struct { unsigned int p2u:8; unsigned int p3u:8; unsigned int b0u:8; unsigned int b1u:8; } dw13; struct { unsigned int b2u:8; unsigned int b3u:8; unsigned int s0u:11; unsigned int pad0:5; } dw14; struct { unsigned int s1u:11; unsigned int s2u:11; unsigned int pad0:10; } dw15; /* DW16-DW151 */ struct i965_sampler_8x8_coefficient coefficients[17]; struct { unsigned int transition_area_with_8_pixels:3; unsigned int pad0:1; unsigned int transition_area_with_4_pixels:3; unsigned int pad1:1; unsigned int max_derivative_8_pixels:8; unsigned int max_derivative_4_pixels:8; unsigned int default_sharpness_level:8; } dw152; struct { unsigned int rgb_adaptive:1; unsigned int adaptive_filter_for_all_channel:1; unsigned int pad0:19; unsigned int bypass_y_adaptive_filtering:1; unsigned int bypass_x_adaptive_filtering:1; unsigned int pad1:9; } dw153; /* Reserved to 256DW */ unsigned int reserved[102]; }; #define SURFACE_STATE_PADDED_SIZE_0_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32) #define SURFACE_STATE_PADDED_SIZE_1_GEN7 ALIGN(sizeof(struct gen7_surface_state2), 32) #define SURFACE_STATE_PADDED_SIZE_GEN7 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7) #define SURFACE_STATE_PADDED_SIZE_0_GEN6 ALIGN(sizeof(struct i965_surface_state), 32) #define SURFACE_STATE_PADDED_SIZE_1_GEN6 ALIGN(sizeof(struct i965_surface_state2), 32) #define SURFACE_STATE_PADDED_SIZE_GEN6 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6) #define SURFACE_STATE_PADDED_SIZE_0_GEN8 ALIGN(sizeof(struct gen8_surface_state), 32) #define SURFACE_STATE_PADDED_SIZE_1_GEN8 ALIGN(sizeof(struct gen8_surface_state2), 32) #define SURFACE_STATE_PADDED_SIZE_GEN8 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN8, SURFACE_STATE_PADDED_SIZE_1_GEN8) #endif /* _I965_STRUCTS_H_ */ intel-driver-1.3.0/src/intel_batchbuffer.c000066400000000000000000000350331231401140700205150ustar00rootroot00000000000000/************************************************************************** * * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * **************************************************************************/ #include #include #include #include "intel_batchbuffer.h" #define MAX_BATCH_SIZE 0x400000 static void intel_batchbuffer_reset(struct intel_batchbuffer *batch, int buffer_size) { struct intel_driver_data *intel = batch->intel; int batch_size = buffer_size; assert(batch->flag == I915_EXEC_RENDER || batch->flag == I915_EXEC_BLT || batch->flag == I915_EXEC_BSD || batch->flag == I915_EXEC_VEBOX); dri_bo_unreference(batch->buffer); batch->buffer = dri_bo_alloc(intel->bufmgr, "batch buffer", batch_size, 0x1000); assert(batch->buffer); dri_bo_map(batch->buffer, 1); assert(batch->buffer->virtual); batch->map = batch->buffer->virtual; batch->size = batch_size; batch->ptr = batch->map; batch->atomic = 0; } static unsigned int intel_batchbuffer_space(struct intel_batchbuffer *batch) { return (batch->size - BATCH_RESERVED) - (batch->ptr - batch->map); } struct intel_batchbuffer * intel_batchbuffer_new(struct intel_driver_data *intel, int flag, int buffer_size) { struct intel_batchbuffer *batch = calloc(1, sizeof(*batch)); assert(flag == I915_EXEC_RENDER || flag == I915_EXEC_BSD || flag == I915_EXEC_BLT || flag == I915_EXEC_VEBOX); if (!buffer_size || buffer_size < BATCH_SIZE) { buffer_size = BATCH_SIZE; } /* the buffer size can't exceed 4M */ if (buffer_size > MAX_BATCH_SIZE) { buffer_size = MAX_BATCH_SIZE; } batch->intel = intel; batch->flag = flag; batch->run = drm_intel_bo_mrb_exec; if (IS_GEN6(intel->device_id) && flag == I915_EXEC_RENDER) batch->wa_render_bo = dri_bo_alloc(intel->bufmgr, "wa scratch", 4096, 4096); else batch->wa_render_bo = NULL; intel_batchbuffer_reset(batch, buffer_size); return batch; } void intel_batchbuffer_free(struct intel_batchbuffer *batch) { if (batch->map) { dri_bo_unmap(batch->buffer); batch->map = NULL; } dri_bo_unreference(batch->buffer); dri_bo_unreference(batch->wa_render_bo); free(batch); } void intel_batchbuffer_flush(struct intel_batchbuffer *batch) { unsigned int used = batch->ptr - batch->map; if (used == 0) { return; } if ((used & 4) == 0) { *(unsigned int*)batch->ptr = 0; batch->ptr += 4; } *(unsigned int*)batch->ptr = MI_BATCH_BUFFER_END; batch->ptr += 4; dri_bo_unmap(batch->buffer); used = batch->ptr - batch->map; batch->run(batch->buffer, used, 0, 0, 0, batch->flag); intel_batchbuffer_reset(batch, batch->size); } void intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, unsigned int x) { assert(intel_batchbuffer_space(batch) >= 4); *(unsigned int *)batch->ptr = x; batch->ptr += 4; } void intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, dri_bo *bo, uint32_t read_domains, uint32_t write_domains, uint32_t delta) { assert(batch->ptr - batch->map < batch->size); dri_bo_emit_reloc(batch->buffer, read_domains, write_domains, delta, batch->ptr - batch->map, bo); intel_batchbuffer_emit_dword(batch, bo->offset + delta); } void intel_batchbuffer_require_space(struct intel_batchbuffer *batch, unsigned int size) { assert(size < batch->size - 8); if (intel_batchbuffer_space(batch) < size) { intel_batchbuffer_flush(batch); } } void intel_batchbuffer_data(struct intel_batchbuffer *batch, void *data, unsigned int size) { assert((size & 3) == 0); intel_batchbuffer_require_space(batch, size); assert(batch->ptr); memcpy(batch->ptr, data, size); batch->ptr += size; } void intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch) { struct intel_driver_data *intel = batch->intel; if (IS_GEN6(intel->device_id) || IS_GEN7(intel->device_id) || IS_GEN8(intel->device_id)) { if (batch->flag == I915_EXEC_RENDER) { if (IS_GEN8(intel->device_id)) { BEGIN_BATCH(batch, 6); OUT_BATCH(batch, CMD_PIPE_CONTROL | (6 - 2)); OUT_BATCH(batch, CMD_PIPE_CONTROL_WC_FLUSH | CMD_PIPE_CONTROL_TC_FLUSH | CMD_PIPE_CONTROL_DC_FLUSH | CMD_PIPE_CONTROL_NOWRITE); OUT_BATCH(batch, 0); /* write address */ OUT_BATCH(batch, 0); OUT_BATCH(batch, 0); /* write data */ OUT_BATCH(batch, 0); ADVANCE_BATCH(batch); } else if (IS_GEN6(intel->device_id)) { assert(batch->wa_render_bo); BEGIN_BATCH(batch, 4 * 3); OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2)); OUT_BATCH(batch, CMD_PIPE_CONTROL_CS_STALL | CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD); OUT_BATCH(batch, 0); /* address */ OUT_BATCH(batch, 0); /* write data */ OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2)); OUT_BATCH(batch, CMD_PIPE_CONTROL_WRITE_QWORD); OUT_RELOC(batch, batch->wa_render_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); OUT_BATCH(batch, 0); /* write data */ /* now finally the _real flush */ OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2)); OUT_BATCH(batch, CMD_PIPE_CONTROL_WC_FLUSH | CMD_PIPE_CONTROL_TC_FLUSH | CMD_PIPE_CONTROL_NOWRITE); OUT_BATCH(batch, 0); /* write address */ OUT_BATCH(batch, 0); /* write data */ ADVANCE_BATCH(batch); } else { BEGIN_BATCH(batch, 4); OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2)); OUT_BATCH(batch, CMD_PIPE_CONTROL_WC_FLUSH | CMD_PIPE_CONTROL_TC_FLUSH | CMD_PIPE_CONTROL_DC_FLUSH | CMD_PIPE_CONTROL_NOWRITE); OUT_BATCH(batch, 0); /* write address */ OUT_BATCH(batch, 0); /* write data */ ADVANCE_BATCH(batch); } } else { if (batch->flag == I915_EXEC_BLT) { BEGIN_BLT_BATCH(batch, 4); OUT_BLT_BATCH(batch, MI_FLUSH_DW); OUT_BLT_BATCH(batch, 0); OUT_BLT_BATCH(batch, 0); OUT_BLT_BATCH(batch, 0); ADVANCE_BLT_BATCH(batch); }else if (batch->flag == I915_EXEC_VEBOX) { BEGIN_VEB_BATCH(batch, 4); OUT_VEB_BATCH(batch, MI_FLUSH_DW); OUT_VEB_BATCH(batch, 0); OUT_VEB_BATCH(batch, 0); OUT_VEB_BATCH(batch, 0); ADVANCE_VEB_BATCH(batch); } else { assert(batch->flag == I915_EXEC_BSD); BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MI_FLUSH_DW | MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); OUT_BCS_BATCH(batch, 0); ADVANCE_BCS_BATCH(batch); } } } else { if (batch->flag == I915_EXEC_RENDER) { BEGIN_BATCH(batch, 1); OUT_BATCH(batch, MI_FLUSH | MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE); ADVANCE_BATCH(batch); } else { assert(batch->flag == I915_EXEC_BSD); BEGIN_BCS_BATCH(batch, 1); OUT_BCS_BATCH(batch, MI_FLUSH | MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE); ADVANCE_BCS_BATCH(batch); } } } void intel_batchbuffer_begin_batch(struct intel_batchbuffer *batch, int total) { batch->emit_total = total * 4; batch->emit_start = batch->ptr; } void intel_batchbuffer_advance_batch(struct intel_batchbuffer *batch) { assert(batch->emit_total == (batch->ptr - batch->emit_start)); } void intel_batchbuffer_check_batchbuffer_flag(struct intel_batchbuffer *batch, int flag) { if (flag != I915_EXEC_RENDER && flag != I915_EXEC_BLT && flag != I915_EXEC_BSD && flag != I915_EXEC_VEBOX) return; if (batch->flag == flag) return; intel_batchbuffer_flush(batch); batch->flag = flag; } int intel_batchbuffer_check_free_space(struct intel_batchbuffer *batch, int size) { return intel_batchbuffer_space(batch) >= size; } static void intel_batchbuffer_start_atomic_helper(struct intel_batchbuffer *batch, int flag, unsigned int size) { assert(!batch->atomic); intel_batchbuffer_check_batchbuffer_flag(batch, flag); intel_batchbuffer_require_space(batch, size); batch->atomic = 1; } void intel_batchbuffer_start_atomic(struct intel_batchbuffer *batch, unsigned int size) { intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_RENDER, size); } void intel_batchbuffer_start_atomic_blt(struct intel_batchbuffer *batch, unsigned int size) { intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_BLT, size); } void intel_batchbuffer_start_atomic_bcs(struct intel_batchbuffer *batch, unsigned int size) { intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_BSD, size); } void intel_batchbuffer_start_atomic_veb(struct intel_batchbuffer *batch, unsigned int size) { intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_VEBOX, size); } void intel_batchbuffer_end_atomic(struct intel_batchbuffer *batch) { assert(batch->atomic); batch->atomic = 0; } int intel_batchbuffer_used_size(struct intel_batchbuffer *batch) { return batch->ptr - batch->map; } void intel_batchbuffer_align(struct intel_batchbuffer *batch, unsigned int alignedment) { int used = batch->ptr - batch->map; int pad_size; assert((alignedment & 3) == 0); pad_size = ALIGN(used, alignedment) - used; assert((pad_size & 3) == 0); assert(intel_batchbuffer_space(batch) >= pad_size); while (pad_size >= 4) { intel_batchbuffer_emit_dword(batch, 0); pad_size -= 4; } } intel-driver-1.3.0/src/intel_batchbuffer.h000066400000000000000000000107321231401140700205210ustar00rootroot00000000000000#ifndef _INTEL_BATCHBUFFER_H_ #define _INTEL_BATCHBUFFER_H_ #include #include #include #include #include "intel_driver.h" struct intel_batchbuffer { struct intel_driver_data *intel; dri_bo *buffer; unsigned int size; unsigned char *map; unsigned char *ptr; int atomic; int flag; int emit_total; unsigned char *emit_start; int (*run)(drm_intel_bo *bo, int used, drm_clip_rect_t *cliprects, int num_cliprects, int DR4, unsigned int ring_flag); /* Used for Sandybdrige workaround */ dri_bo *wa_render_bo; }; struct intel_batchbuffer *intel_batchbuffer_new(struct intel_driver_data *intel, int flag, int buffer_size); void intel_batchbuffer_free(struct intel_batchbuffer *batch); void intel_batchbuffer_start_atomic(struct intel_batchbuffer *batch, unsigned int size); void intel_batchbuffer_start_atomic_bcs(struct intel_batchbuffer *batch, unsigned int size); void intel_batchbuffer_start_atomic_blt(struct intel_batchbuffer *batch, unsigned int size); void intel_batchbuffer_start_atomic_veb(struct intel_batchbuffer *batch, unsigned int size); void intel_batchbuffer_end_atomic(struct intel_batchbuffer *batch); void intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, unsigned int x); void intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, dri_bo *bo, uint32_t read_domains, uint32_t write_domains, uint32_t delta); void intel_batchbuffer_require_space(struct intel_batchbuffer *batch, unsigned int size); void intel_batchbuffer_data(struct intel_batchbuffer *batch, void *data, unsigned int size); void intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch); void intel_batchbuffer_flush(struct intel_batchbuffer *batch); void intel_batchbuffer_begin_batch(struct intel_batchbuffer *batch, int total); void intel_batchbuffer_advance_batch(struct intel_batchbuffer *batch); void intel_batchbuffer_check_batchbuffer_flag(struct intel_batchbuffer *batch, int flag); int intel_batchbuffer_check_free_space(struct intel_batchbuffer *batch, int size); int intel_batchbuffer_used_size(struct intel_batchbuffer *batch); void intel_batchbuffer_align(struct intel_batchbuffer *batch, unsigned int alignedment); #define __BEGIN_BATCH(batch, n, f) do { \ assert(f == batch->flag); \ intel_batchbuffer_check_batchbuffer_flag(batch, f); \ intel_batchbuffer_require_space(batch, (n) * 4); \ intel_batchbuffer_begin_batch(batch, (n)); \ } while (0) #define __OUT_BATCH(batch, d) do { \ intel_batchbuffer_emit_dword(batch, d); \ } while (0) #define __OUT_RELOC(batch, bo, read_domains, write_domain, delta) do { \ assert((delta) >= 0); \ intel_batchbuffer_emit_reloc(batch, bo, \ read_domains, write_domain, \ delta); \ } while (0) #define __ADVANCE_BATCH(batch) do { \ intel_batchbuffer_advance_batch(batch); \ } while (0) #define BEGIN_BATCH(batch, n) __BEGIN_BATCH(batch, n, I915_EXEC_RENDER) #define BEGIN_BLT_BATCH(batch, n) __BEGIN_BATCH(batch, n, I915_EXEC_BLT) #define BEGIN_BCS_BATCH(batch, n) __BEGIN_BATCH(batch, n, I915_EXEC_BSD) #define BEGIN_VEB_BATCH(batch, n) __BEGIN_BATCH(batch, n, I915_EXEC_VEBOX) #define OUT_BATCH(batch, d) __OUT_BATCH(batch, d) #define OUT_BLT_BATCH(batch, d) __OUT_BATCH(batch, d) #define OUT_BCS_BATCH(batch, d) __OUT_BATCH(batch, d) #define OUT_VEB_BATCH(batch, d) __OUT_BATCH(batch, d) #define OUT_RELOC(batch, bo, read_domains, write_domain, delta) \ __OUT_RELOC(batch, bo, read_domains, write_domain, delta) #define OUT_BLT_RELOC(batch, bo, read_domains, write_domain, delta) \ __OUT_RELOC(batch, bo, read_domains, write_domain, delta) #define OUT_BCS_RELOC(batch, bo, read_domains, write_domain, delta) \ __OUT_RELOC(batch, bo, read_domains, write_domain, delta) #define ADVANCE_BATCH(batch) __ADVANCE_BATCH(batch) #define ADVANCE_BLT_BATCH(batch) __ADVANCE_BATCH(batch) #define ADVANCE_BCS_BATCH(batch) __ADVANCE_BATCH(batch) #define ADVANCE_VEB_BATCH(batch) __ADVANCE_BATCH(batch) #endif /* _INTEL_BATCHBUFFER_H_ */ intel-driver-1.3.0/src/intel_batchbuffer_dump.c000066400000000000000000000625371231401140700215530ustar00rootroot00000000000000#include #include #include #include #include "intel_driver.h" #include "intel_batchbuffer_dump.h" #ifdef I965_DEBUG #define BUFFER_FAIL(_count, _len, _name) do { \ fprintf(gout, "Buffer size too small in %s (%d < %d)\n", \ (_name), (_count), (_len)); \ (*failures)++; \ return count; \ } while (0) static FILE *gout; static void instr_out(unsigned int *data, unsigned int offset, unsigned int index, char *fmt, ...) { va_list va; fprintf(gout, "0x%08x: 0x%08x:%s ", offset + index * 4, data[index], index == 0 ? "" : " "); va_start(va, fmt); vfprintf(gout, fmt, va); va_end(va); } static int dump_mi(unsigned int *data, unsigned int offset, int count, unsigned int device, int *failures) { unsigned int opcode; int length, i; struct { unsigned int opcode; int mask_length; int min_len; int max_len; char *name; } mi_commands[] = { { 0x00, 0, 1, 1, "MI_NOOP" }, { 0x04, 0, 1, 1, "MI_FLUSH" }, { 0x0a, 0, 1, 1, "MI_BATCH_BUFFER_END" }, { 0x26, 0x3f, 4, 5, "MI_FLUSH_DW" }, }; opcode = ((data[0] & MASK_MI_OPCODE) >> SHIFT_MI_OPCODE); for (i = 0; i < sizeof(mi_commands) / sizeof(mi_commands[0]); i++) { if (opcode == mi_commands[i].opcode) { int index; length = 1; instr_out(data, offset, 0, "%s\n", mi_commands[i].name); if (mi_commands[i].max_len > 1) { length = (data[0] & mi_commands[i].mask_length) + 2; if (length < mi_commands[i].min_len || length > mi_commands[i].max_len) { fprintf(gout, "Bad length (%d) in %s, [%d, %d]\n", length, mi_commands[i].name, mi_commands[i].min_len, mi_commands[i].max_len); } } for (index = 1; index < length; index++) { if (index >= count) BUFFER_FAIL(count, length, mi_commands[i].name); instr_out(data, offset, index, "dword %d\n", index); } return length; } } instr_out(data, offset, 0, "UNKNOWN MI COMMAND\n"); (*failures)++; return 1; } static int dump_gfxpipe_3d(unsigned int *data, unsigned int offset, int count, unsigned int device, int *failures) { instr_out(data, offset, 0, "UNKNOWN 3D COMMAND\n"); (*failures)++; return 1; } static void dump_avc_bsd_img_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { int img_struct = ((data[3] >> 8) & 0x3); instr_out(data, offset, 1, "frame size: %d\n", (data[1] & 0xffff)); instr_out(data, offset, 2, "width: %d, height: %d\n", (data[2] & 0xff), (data[2] >> 16) & 0xff); instr_out(data, offset, 3, "second_chroma_qp_offset: %d," "chroma_qp_offset: %d," "QM present flag: %d," "image struct: %s," "img_dec_fs_idc: %d," "\n", (data[3] >> 24) & 0x1f, (data[3] >> 16) & 0x1f, (data[3] >> 10) & 0x1, (img_struct == 0) ? "frame" : (img_struct == 2) ? "invalid" : (img_struct == 1) ? "top field" : "bottom field", data[3] & 0xff); instr_out(data, offset, 4, "residual off: 0x%x," "16MV: %d," "chroma fmt: %d," "CABAC: %d," "non-ref: %d," "constrained intra: %d," "direct8x8: %d," "trans8x8: %d," "MB only: %d," "MBAFF: %d," "\n", (data[4] >> 24) & 0xff, (data[4] >> 12) & 0x1, (data[4] >> 10) & 0x3, (data[4] >> 7) & 0x1, (data[4] >> 6) & 0x1, (data[4] >> 5) & 0x1, (data[4] >> 4) & 0x1, (data[4] >> 3) & 0x1, (data[4] >> 2) & 0x1, (data[4] >> 1) & 0x1); instr_out(data, offset, 5, "AVC-IT Command Header\n"); } static void dump_avc_bsd_qm_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { unsigned int length = ((data[0] & MASK_GFXPIPE_LENGTH) >> SHIFT_GFXPIPE_LENGTH) + 2; int i; instr_out(data, offset, 1, "user default: %02x, QM list present: %02x\n", (data[1] >> 8) & 0xff, data[1] & 0xff); for (i = 2; i < length; i++) { instr_out(data, offset, i, "dword %d\n", i); } } static void dump_avc_bsd_slice_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { } static void dump_avc_bsd_buf_base_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { int i; instr_out(data, offset, 1, "BSD row store base address\n"); instr_out(data, offset, 2, "MPR row store base address\n"); instr_out(data, offset, 3, "AVC-IT command buffer base address\n"); instr_out(data, offset, 4, "AVC-IT data buffer: 0x%08x, write offset: 0x%x\n", data[4] & 0xFFFFF000, data[4] & 0xFC0); instr_out(data, offset, 5, "ILDB data buffer\n"); for (i = 6; i < 38; i++) { instr_out(data, offset, i, "Direct MV read base address for reference frame %d\n", i - 6); } instr_out(data, offset, 38, "direct mv wr0 top\n"); instr_out(data, offset, 39, "direct mv wr0 bottom\n"); for (i = 40; i < 74; i++) { instr_out(data, offset, i, "POC List %d\n", i - 40); } } static void dump_bsd_ind_obj_base_addr(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { instr_out(data, offset, 1, "AVC indirect object base address\n"); instr_out(data, offset, 2, "AVC Indirect Object Access Upper Bound\n"); } static void dump_ironlake_avc_bsd_object(unsigned int *data, unsigned int offset, int *failures) { int slice_type = data[3] & 0xf; int i, is_phantom = ((data[1] & 0x3fffff) == 0); if (!is_phantom) { instr_out(data, offset, 1, "Encrypted: %d, bitsteam length: %d\n", data[1] >> 31, data[1] & 0x3fffff); instr_out(data, offset, 2, "Indirect Data Start Address: %d\n", data[2] & 0x1fffffff); instr_out(data, offset, 3, "%s Slice\n", slice_type == 0 ? "P" : slice_type == 1 ? "B" : "I"); instr_out(data, offset, 4, "Num_Ref_Idx_L1: %d," "Num_Ref_Idx_L0: %d," "Log2WeightDenomChroma: %d," "Log2WeightDenomLuma: %d" "\n", (data[4] >> 24) & 0x3f, (data[4] >> 16) & 0x3f, (data[4] >> 8) & 0x3, (data[4] >> 0) & 0x3); instr_out(data, offset, 5, "WeightedPredIdc: %d," "DirectPredType: %d," "DisableDeblockingFilter: %d," "CabacInitIdc: %d," "SliceQp: %d," "SliceBetaOffsetDiv2: %d," "SliceAlphaC0OffsetDiv2: %d" "\n", (data[5] >> 30) & 0x3, (data[5] >> 29) & 0x1, (data[5] >> 27) & 0x3, (data[5] >> 24) & 0x3, (data[5] >> 16) & 0x3f, (data[5] >> 8) & 0xf, (data[5] >> 0) & 0xf); instr_out(data, offset, 6, "Slice_MB_Start_Vert_Pos: %d," "Slice_MB_Start_Hor_Pos: %d," "Slice_Start_Mb_Num: %d" "\n", (data[6] >> 24) & 0xff, (data[6] >> 16) & 0xff, (data[6] >> 0) & 0x7fff); instr_out(data, offset, 7, "Fix_Prev_Mb_Skipped: %d," "First_MB_Bit_Offset: %d" "\n", (data[7] >> 7) & 0x1, (data[7] >> 0) & 0x7); for (i = 8; i < 16; i++) instr_out(data, offset, i, "dword %d\n", i); } else { instr_out(data, offset, 1, "phantom slice\n"); for (i = 2; i < 6; i++) instr_out(data, offset, i, "dword %d\n", i); instr_out(data, offset, 6, "Slice_Start_Mb_Num: %d" "\n", (data[6] >> 0) & 0x7fff); for (i = 7; i < 16; i++) instr_out(data, offset, i, "dword %d\n", i); } } static void dump_g4x_avc_bsd_object(unsigned int *data, unsigned int offset, int *failures) { } static void dump_avc_bsd_object(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { if (IS_IRONLAKE(device)) dump_ironlake_avc_bsd_object(data, offset, failures); else dump_g4x_avc_bsd_object(data, offset, failures); } static int dump_bsd_avc(unsigned int *data, unsigned int offset, int count, unsigned int device, int *failures) { unsigned int subopcode; int length, i; struct { unsigned int subopcode; int min_len; int max_len; char *name; void (*detail)(unsigned int *data, unsigned int offset, unsigned int device, int *failures); } avc_commands[] = { { 0x00, 0x06, 0x06, "AVC_BSD_IMG_STATE", dump_avc_bsd_img_state }, { 0x01, 0x02, 0x3a, "AVC_BSD_QM_STATE", dump_avc_bsd_qm_state }, { 0x02, 0x02, 0xd2, "AVC_BSD_SLICE_STATE", NULL }, { 0x03, 0x4a, 0x4a, "AVC_BSD_BUF_BASE_STATE", dump_avc_bsd_buf_base_state }, { 0x04, 0x03, 0x03, "BSD_IND_OBJ_BASE_ADDR", dump_bsd_ind_obj_base_addr }, { 0x08, 0x08, 0x10, "AVC_BSD_OBJECT", dump_avc_bsd_object }, }; subopcode = ((data[0] & MASK_GFXPIPE_SUBOPCODE) >> SHIFT_GFXPIPE_SUBOPCODE); for (i = 0; i < sizeof(avc_commands) / sizeof(avc_commands[0]); i++) { if (subopcode == avc_commands[i].subopcode) { unsigned int index; length = (data[0] & MASK_GFXPIPE_LENGTH) >> SHIFT_GFXPIPE_LENGTH; length += 2; instr_out(data, offset, 0, "%s\n", avc_commands[i].name); if (length < avc_commands[i].min_len || length > avc_commands[i].max_len) { fprintf(gout, "Bad length(%d) in %s [%d, %d]\n", length, avc_commands[i].name, avc_commands[i].min_len, avc_commands[i].max_len); } if (length - 1 >= count) BUFFER_FAIL(count, length, avc_commands[i].name); if (avc_commands[i].detail) avc_commands[i].detail(data, offset, device, failures); else { for (index = 1; index < length; index++) instr_out(data, offset, index, "dword %d\n", index); } return length; } } instr_out(data, offset, 0, "UNKNOWN AVC COMMAND\n"); (*failures)++; return 1; } static int dump_gfxpipe_bsd(unsigned int *data, unsigned int offset, int count, unsigned int device, int *failures) { int length; switch ((data[0] & MASK_GFXPIPE_OPCODE) >> SHIFT_GFXPIPE_OPCODE) { case OPCODE_BSD_AVC: length = dump_bsd_avc(data, offset, count, device, failures); break; default: length = 1; (*failures)++; instr_out(data, offset, 0, "UNKNOWN BSD OPCODE\n"); break; } return length; } static void dump_mfx_mode_select(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { instr_out(data, offset, 1, "decoder mode: %d(%s)," "post deblocking output enable %d," "pre deblocking output enable %d," "codec select: %d(%s)," "standard select: %d(%s)" "\n", (data[1] >> 16) & 0x1, ((data[1] >> 16) & 0x1) ? "IT" : "VLD", (data[1] >> 9) & 0x1, (data[1] >> 8) & 0x1, (data[1] >> 4) & 0x1, ((data[1] >> 4) & 0x1) ? "Encode" : "Decode", (data[1] >> 0) & 0x3, ((data[1] >> 0) & 0x3) == 0 ? "MPEG2" : ((data[1] >> 0) & 0x3) == 1 ? "VC1" : ((data[1] >> 0) & 0x3) == 2 ? "AVC" : "Reserved"); instr_out(data, offset, 2, "dword 02\n"); instr_out(data, offset, 3, "dword 03\n"); } static void dump_mfx_surface_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { instr_out(data, offset, 1, "dword 01\n"); instr_out(data, offset, 2, "dword 02\n"); instr_out(data, offset, 3, "dword 03\n"); instr_out(data, offset, 4, "dword 04\n"); instr_out(data, offset, 5, "dword 05\n"); } static void dump_mfx_pipe_buf_addr_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { instr_out(data, offset, 1, "dword 01\n"); instr_out(data, offset, 2, "dword 02\n"); instr_out(data, offset, 3, "dword 03\n"); instr_out(data, offset, 4, "dword 04\n"); instr_out(data, offset, 5, "dword 05\n"); instr_out(data, offset, 6, "dword 06\n"); instr_out(data, offset, 7, "dword 07\n"); instr_out(data, offset, 8, "dword 08\n"); instr_out(data, offset, 9, "dword 09\n"); instr_out(data, offset, 10, "dword 10\n"); instr_out(data, offset, 11, "dword 11\n"); instr_out(data, offset, 12, "dword 12\n"); instr_out(data, offset, 13, "dword 13\n"); instr_out(data, offset, 14, "dword 14\n"); instr_out(data, offset, 15, "dword 15\n"); instr_out(data, offset, 16, "dword 16\n"); instr_out(data, offset, 17, "dword 17\n"); instr_out(data, offset, 18, "dword 18\n"); instr_out(data, offset, 19, "dword 19\n"); instr_out(data, offset, 20, "dword 20\n"); instr_out(data, offset, 21, "dword 21\n"); instr_out(data, offset, 22, "dword 22\n"); instr_out(data, offset, 24, "dword 23\n"); } static void dump_mfx_ind_obj_base_addr_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { instr_out(data, offset, 1, "dword 01\n"); instr_out(data, offset, 2, "dword 02\n"); instr_out(data, offset, 3, "dword 03\n"); instr_out(data, offset, 4, "dword 04\n"); instr_out(data, offset, 5, "dword 05\n"); instr_out(data, offset, 6, "dword 06\n"); instr_out(data, offset, 7, "dword 07\n"); instr_out(data, offset, 8, "dword 08\n"); instr_out(data, offset, 9, "dword 09\n"); instr_out(data, offset, 10, "dword 10\n"); } static void dump_mfx_bsp_buf_base_addr_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { instr_out(data, offset, 1, "dword 01\n"); instr_out(data, offset, 2, "dword 02\n"); instr_out(data, offset, 3, "dword 03\n"); } static void dump_mfx_aes_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { instr_out(data, offset, 1, "dword 01\n"); instr_out(data, offset, 2, "dword 02\n"); instr_out(data, offset, 3, "dword 03\n"); instr_out(data, offset, 4, "dword 04\n"); instr_out(data, offset, 5, "dword 05\n"); instr_out(data, offset, 6, "dword 06\n"); } static void dump_mfx_state_pointer(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { instr_out(data, offset, 1, "dword 01\n"); } static int dump_mfx_common(unsigned int *data, unsigned int offset, int count, unsigned int device, int *failures) { unsigned int subopcode; int length, i; struct { unsigned int subopcode; int min_len; int max_len; char *name; void (*detail)(unsigned int *data, unsigned int offset, unsigned int device, int *failures); } mfx_common_commands[] = { { SUBOPCODE_MFX(0, 0), 0x04, 0x04, "MFX_PIPE_MODE_SELECT", dump_mfx_mode_select }, { SUBOPCODE_MFX(0, 1), 0x06, 0x06, "MFX_SURFACE_STATE", dump_mfx_surface_state }, { SUBOPCODE_MFX(0, 2), 0x18, 0x18, "MFX_PIPE_BUF_ADDR_STATE", dump_mfx_pipe_buf_addr_state }, { SUBOPCODE_MFX(0, 3), 0x0b, 0x0b, "MFX_IND_OBJ_BASE_ADDR_STATE", dump_mfx_ind_obj_base_addr_state }, { SUBOPCODE_MFX(0, 4), 0x04, 0x04, "MFX_BSP_BUF_BASE_ADDR_STATE", dump_mfx_bsp_buf_base_addr_state }, { SUBOPCODE_MFX(0, 5), 0x07, 0x07, "MFX_AES_STATE", dump_mfx_aes_state }, { SUBOPCODE_MFX(0, 6), 0x00, 0x00, "MFX_STATE_POINTER", dump_mfx_state_pointer }, }; subopcode = ((data[0] & MASK_GFXPIPE_SUBOPCODE) >> SHIFT_GFXPIPE_SUBOPCODE); for (i = 0; i < ARRAY_ELEMS(mfx_common_commands); i++) { if (subopcode == mfx_common_commands[i].subopcode) { unsigned int index; length = (data[0] & MASK_GFXPIPE_LENGTH) >> SHIFT_GFXPIPE_LENGTH; length += 2; instr_out(data, offset, 0, "%s\n", mfx_common_commands[i].name); if (length < mfx_common_commands[i].min_len || length > mfx_common_commands[i].max_len) { fprintf(gout, "Bad length(%d) in %s [%d, %d]\n", length, mfx_common_commands[i].name, mfx_common_commands[i].min_len, mfx_common_commands[i].max_len); } if (length - 1 >= count) BUFFER_FAIL(count, length, mfx_common_commands[i].name); if (mfx_common_commands[i].detail) mfx_common_commands[i].detail(data, offset, device, failures); else { for (index = 1; index < length; index++) instr_out(data, offset, index, "dword %d\n", index); } return length; } } instr_out(data, offset, 0, "UNKNOWN MFX COMMON COMMAND\n"); (*failures)++; return 1; } static void dump_mfx_avc_img_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { instr_out(data, offset, 1, "dword 01\n"); instr_out(data, offset, 2, "dword 02\n"); instr_out(data, offset, 3, "dword 03\n"); instr_out(data, offset, 4, "dword 04\n"); instr_out(data, offset, 5, "dword 05\n"); instr_out(data, offset, 6, "dword 06\n"); instr_out(data, offset, 7, "dword 07\n"); instr_out(data, offset, 8, "dword 08\n"); instr_out(data, offset, 9, "dword 09\n"); instr_out(data, offset, 10, "dword 10\n"); instr_out(data, offset, 11, "dword 11\n"); instr_out(data, offset, 12, "dword 12\n"); } static void dump_mfx_avc_qm_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { unsigned int length = ((data[0] & MASK_GFXPIPE_LENGTH) >> SHIFT_GFXPIPE_LENGTH) + 2; int i; instr_out(data, offset, 1, "user default: %02x, QM list present: %02x\n", (data[1] >> 8) & 0xff, data[1] & 0xff); for (i = 2; i < length; i++) { instr_out(data, offset, i, "dword %d\n", i); } } static void dump_mfx_avc_directmode_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { int i; for (i = 1; i < 33; i++) { instr_out(data, offset, i, "Direct MV Buffer Base Address for Picture %d\n", i - 1); } for (i = 33; i < 35; i++) { instr_out(data, offset, i, "Direct MV Buffer Base Address for Current Decoding Frame/Field\n"); } for (i = 35; i < 69; i++) { instr_out(data, offset, i, "POC List\n"); } } static void dump_mfx_avc_slice_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { instr_out(data, offset, 1, "dword 01\n"); instr_out(data, offset, 2, "dword 02\n"); instr_out(data, offset, 3, "dword 03\n"); instr_out(data, offset, 4, "dword 04\n"); instr_out(data, offset, 5, "dword 05\n"); instr_out(data, offset, 6, "dword 06\n"); instr_out(data, offset, 7, "dword 07\n"); instr_out(data, offset, 8, "dword 08\n"); instr_out(data, offset, 9, "dword 09\n"); } static void dump_mfx_avc_ref_idx_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { instr_out(data, offset, 1, "dword 01\n"); instr_out(data, offset, 2, "dword 02\n"); instr_out(data, offset, 3, "dword 03\n"); instr_out(data, offset, 4, "dword 04\n"); instr_out(data, offset, 5, "dword 05\n"); instr_out(data, offset, 6, "dword 06\n"); instr_out(data, offset, 7, "dword 07\n"); instr_out(data, offset, 8, "dword 08\n"); instr_out(data, offset, 9, "dword 09\n"); } static void dump_mfx_avc_weightoffset_state(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { int i; instr_out(data, offset, 1, "Weight and Offset L%d table\n", (data[1] >> 0) & 0x1); for (i = 2; i < 31; i++) { instr_out(data, offset, i, "dword %d\n", i); } } static void dump_mfd_bsd_object(unsigned int *data, unsigned int offset, unsigned int device, int *failures) { int is_phantom_slice = ((data[1] & 0x3fffff) == 0); if (is_phantom_slice) { instr_out(data, offset, 1, "phantom slice\n"); instr_out(data, offset, 2, "dword 02\n"); instr_out(data, offset, 3, "dword 03\n"); instr_out(data, offset, 4, "dword 04\n"); instr_out(data, offset, 5, "dword 05\n"); } else { instr_out(data, offset, 1, "Indirect BSD Data Length: %d\n", data[1] & 0x3fffff); instr_out(data, offset, 2, "Indirect BSD Data Start Address: 0x%08x\n", data[2] & 0x1fffffff); instr_out(data, offset, 3, "dword 03\n"); instr_out(data, offset, 4, "First_MB_Byte_Offset of Slice Data from Slice Header: 0x%08x," "slice header skip mode: %d" "\n", (data[4] >> 16), (data[4] >> 6) & 0x1); instr_out(data, offset, 5, "dword 05\n"); } } static int dump_mfx_avc(unsigned int *data, unsigned int offset, int count, unsigned int device, int *failures) { unsigned int subopcode; int length, i; struct { unsigned int subopcode; int min_len; int max_len; char *name; void (*detail)(unsigned int *data, unsigned int offset, unsigned int device, int *failures); } mfx_avc_commands[] = { { SUBOPCODE_MFX(0, 0), 0x0d, 0x0d, "MFX_AVC_IMG_STATE", dump_mfx_avc_img_state }, { SUBOPCODE_MFX(0, 1), 0x02, 0x3a, "MFX_AVC_QM_STATE", dump_mfx_avc_qm_state }, { SUBOPCODE_MFX(0, 2), 0x45, 0x45, "MFX_AVC_DIRECTMODE_STATE", dump_mfx_avc_directmode_state }, { SUBOPCODE_MFX(0, 3), 0x0b, 0x0b, "MFX_AVC_SLICE_STATE", dump_mfx_avc_slice_state }, { SUBOPCODE_MFX(0, 4), 0x0a, 0x0a, "MFX_AVC_REF_IDX_STATE", dump_mfx_avc_ref_idx_state }, { SUBOPCODE_MFX(0, 5), 0x32, 0x32, "MFX_AVC_WEIGHTOFFSET_STATE", dump_mfx_avc_weightoffset_state }, { SUBOPCODE_MFX(1, 8), 0x06, 0x06, "MFD_AVC_BSD_OBJECT", dump_mfd_bsd_object }, }; subopcode = ((data[0] & MASK_GFXPIPE_SUBOPCODE) >> SHIFT_GFXPIPE_SUBOPCODE); for (i = 0; i < ARRAY_ELEMS(mfx_avc_commands); i++) { if (subopcode == mfx_avc_commands[i].subopcode) { unsigned int index; length = (data[0] & MASK_GFXPIPE_LENGTH) >> SHIFT_GFXPIPE_LENGTH; length += 2; instr_out(data, offset, 0, "%s\n", mfx_avc_commands[i].name); if (length < mfx_avc_commands[i].min_len || length > mfx_avc_commands[i].max_len) { fprintf(gout, "Bad length(%d) in %s [%d, %d]\n", length, mfx_avc_commands[i].name, mfx_avc_commands[i].min_len, mfx_avc_commands[i].max_len); } if (length - 1 >= count) BUFFER_FAIL(count, length, mfx_avc_commands[i].name); if (mfx_avc_commands[i].detail) mfx_avc_commands[i].detail(data, offset, device, failures); else { for (index = 1; index < length; index++) instr_out(data, offset, index, "dword %d\n", index); } return length; } } instr_out(data, offset, 0, "UNKNOWN MFX AVC COMMAND\n"); (*failures)++; return 1; } static int dump_gfxpipe_mfx(unsigned int *data, unsigned int offset, int count, unsigned int device, int *failures) { int length; switch ((data[0] & MASK_GFXPIPE_OPCODE) >> SHIFT_GFXPIPE_OPCODE) { case OPCODE_MFX_COMMON: length = dump_mfx_common(data, offset, count, device, failures); break; case OPCODE_MFX_AVC: length = dump_mfx_avc(data, offset, count, device, failures); break; default: length = 1; (*failures)++; instr_out(data, offset, 0, "UNKNOWN MFX OPCODE\n"); break; } return length; } static int dump_gfxpipe(unsigned int *data, unsigned int offset, int count, unsigned int device, int *failures) { int length; switch ((data[0] & MASK_GFXPIPE_SUBTYPE) >> SHIFT_GFXPIPE_SUBTYPE) { case GFXPIPE_3D: length = dump_gfxpipe_3d(data, offset, count, device, failures); break; case GFXPIPE_BSD: if (IS_GEN6(device)) length = dump_gfxpipe_mfx(data, offset, count, device, failures); else length = dump_gfxpipe_bsd(data, offset, count, device, failures); break; default: length = 1; (*failures)++; instr_out(data, offset, 0, "UNKNOWN GFXPIPE COMMAND\n"); break; } return length; } int intel_batchbuffer_dump(unsigned int *data, unsigned int offset, int count, unsigned int device) { int index = 0; int failures = 0; gout = fopen("/tmp/bsd_command_dump.txt", "w+"); while (index < count) { switch ((data[index] & MASK_CMD_TYPE) >> SHIFT_CMD_TYPE) { case CMD_TYPE_MI: index += dump_mi(data + index, offset + index * 4, count - index, device, &failures); break; case CMD_TYPE_GFXPIPE: index += dump_gfxpipe(data + index, offset + index * 4, count - index, device, &failures); break; default: instr_out(data, offset, index, "UNKNOWN COMMAND\n"); failures++; index++; break; } fflush(gout); } fclose(gout); return failures; } #endif intel-driver-1.3.0/src/intel_batchbuffer_dump.h000066400000000000000000000026151231401140700215470ustar00rootroot00000000000000#ifndef _INTEL_BATCHBUFFER_DUMP_H_ #define _INTEL_BATCHBUFFER_DUMP_H_ #define MASK_CMD_TYPE 0xE0000000 #define SHIFT_CMD_TYPE 29 #define CMD_TYPE_GFXPIPE 3 #define CMD_TYPE_BLT 2 #define CMD_TYPE_MI 0 /* GFXPIPE */ #define MASK_GFXPIPE_SUBTYPE 0x18000000 #define MASK_GFXPIPE_OPCODE 0x07000000 #define MASK_GFXPIPE_SUBOPCODE 0x00FF0000 #define MASK_GFXPIPE_LENGTH 0x0000FFFF #define SHIFT_GFXPIPE_SUBTYPE 27 #define SHIFT_GFXPIPE_OPCODE 24 #define SHIFT_GFXPIPE_SUBOPCODE 16 #define SHIFT_GFXPIPE_LENGTH 0 /* 3D */ #define GFXPIPE_3D 3 /* BSD */ #define GFXPIPE_BSD 2 #define OPCODE_BSD_AVC 4 #define SUBOPCODE_BSD_IMG 0 #define SUBOPCODE_BSD_QM 1 #define SUBOPCODE_BSD_SLICE 2 #define SUBOPCODE_BSD_BUF_BASE 3 #define SUBOPCODE_BSD_IND_OBJ 4 #define SUBOPCODE_BSD_OBJECT 8 /* MFX */ #define OPCODE_MFX_COMMON 0 #define OPCODE_MFX_AVC 1 #define SUBOPCODE_MFX(A, B) ((A) << 5 | (B)) /* MI */ #define MASK_MI_OPCODE 0x1F800000 #define SHIFT_MI_OPCODE 23 #define OPCODE_MI_FLUSH 0x04 #define OPCODE_MI_BATCH_BUFFER_END 0x0A #ifdef I965_DEBUG int intel_batchbuffer_dump(unsigned int *data, unsigned int offset, int count, unsigned int device); #endif #endif /* _INTEL_BATCHBUFFER_DUMP_H_ */ intel-driver-1.3.0/src/intel_compiler.h000066400000000000000000000007571231401140700200660ustar00rootroot00000000000000#ifndef _INTEL_COMPILER_H_ #define _INTEL_COMPILER_H_ /** * Function inlining */ #if defined(__GNUC__) # define INLINE __inline__ #elif (__STDC_VERSION__ >= 199901L) /* C99 */ # define INLINE inline #else # define INLINE #endif /** * Function visibility */ #if defined(__GNUC__) # define DLL_HIDDEN __attribute__((visibility("hidden"))) # define DLL_EXPORT __attribute__((visibility("default"))) #else # define DLL_HIDDEN # define DLL_EXPORT #endif #endif /* _INTEL_COMPILER_H_ */ intel-driver-1.3.0/src/intel_driver.c000066400000000000000000000073001231401140700175310ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * Zou Nan hai * */ #include "sysdeps.h" #include #include "intel_batchbuffer.h" #include "intel_memman.h" #include "intel_driver.h" static Bool intel_driver_get_param(struct intel_driver_data *intel, int param, int *value) { struct drm_i915_getparam gp; gp.param = param; gp.value = value; return drmCommandWriteRead(intel->fd, DRM_I915_GETPARAM, &gp, sizeof(gp)) == 0; } static void intel_driver_get_revid(struct intel_driver_data *intel, int *value) { #define PCI_REVID 8 FILE *fp; char config_data[16]; fp = fopen("/sys/devices/pci0000:00/0000:00:02.0/config", "r"); if (fp) { if (fread(config_data, 1, 16, fp)) *value = config_data[PCI_REVID]; else *value = 2; /* assume it is at least B-steping */ fclose(fp); } else { *value = 2; /* assume it is at least B-steping */ } return; } bool intel_driver_init(VADriverContextP ctx) { struct intel_driver_data *intel = intel_driver_data(ctx); struct drm_state * const drm_state = (struct drm_state *)ctx->drm_state; int has_exec2 = 0, has_bsd = 0, has_blt = 0, has_vebox = 0; assert(drm_state); assert(VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_DRI1) || VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_DRI2) || VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_CUSTOM)); intel->fd = drm_state->fd; intel->dri2Enabled = (VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_DRI2) || VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_CUSTOM)); if (!intel->dri2Enabled) { return false; } intel->locked = 0; pthread_mutex_init(&intel->ctxmutex, NULL); intel_driver_get_param(intel, I915_PARAM_CHIPSET_ID, &intel->device_id); if (intel_driver_get_param(intel, I915_PARAM_HAS_EXECBUF2, &has_exec2)) intel->has_exec2 = has_exec2; if (intel_driver_get_param(intel, I915_PARAM_HAS_BSD, &has_bsd)) intel->has_bsd = has_bsd; if (intel_driver_get_param(intel, I915_PARAM_HAS_BLT, &has_blt)) intel->has_blt = has_blt; if (intel_driver_get_param(intel, I915_PARAM_HAS_VEBOX, &has_vebox)) intel->has_vebox = !!has_vebox; intel_driver_get_revid(intel, &intel->revision); intel_memman_init(intel); return true; } void intel_driver_terminate(VADriverContextP ctx) { struct intel_driver_data *intel = intel_driver_data(ctx); intel_memman_terminate(intel); pthread_mutex_destroy(&intel->ctxmutex); } intel-driver-1.3.0/src/intel_driver.h000066400000000000000000000437021231401140700175440ustar00rootroot00000000000000#ifndef _INTEL_DRIVER_H_ #define _INTEL_DRIVER_H_ #include #include #include #include #include #include #include #include #include "va_backend_compat.h" #include "intel_compiler.h" #define BATCH_SIZE 0x80000 #define BATCH_RESERVED 0x10 #define CMD_MI (0x0 << 29) #define CMD_2D (0x2 << 29) #define CMD_3D (0x3 << 29) #define MI_NOOP (CMD_MI | 0) #define MI_BATCH_BUFFER_END (CMD_MI | (0xA << 23)) #define MI_BATCH_BUFFER_START (CMD_MI | (0x31 << 23)) #define MI_FLUSH (CMD_MI | (0x4 << 23)) #define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0) #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2) #define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7) #define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04) #define XY_COLOR_BLT_WRITE_ALPHA (1 << 21) #define XY_COLOR_BLT_WRITE_RGB (1 << 20) #define XY_COLOR_BLT_DST_TILED (1 << 11) #define GEN8_XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x05) /* BR13 */ #define BR13_8 (0x0 << 24) #define BR13_565 (0x1 << 24) #define BR13_1555 (0x2 << 24) #define BR13_8888 (0x3 << 24) #define CMD_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16)) #define CMD_PIPE_CONTROL_CS_STALL (1 << 20) #define CMD_PIPE_CONTROL_NOWRITE (0 << 14) #define CMD_PIPE_CONTROL_WRITE_QWORD (1 << 14) #define CMD_PIPE_CONTROL_WRITE_DEPTH (2 << 14) #define CMD_PIPE_CONTROL_WRITE_TIME (3 << 14) #define CMD_PIPE_CONTROL_DEPTH_STALL (1 << 13) #define CMD_PIPE_CONTROL_WC_FLUSH (1 << 12) #define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11) #define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10) #define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) #define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5) #define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2) #define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2) #define CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1) #define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) struct intel_batchbuffer; #define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1)) #define MIN(a, b) ((a) < (b) ? (a) : (b)) #define MAX(a, b) ((a) > (b) ? (a) : (b)) #define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0])) #define Bool int #define True 1 #define False 0 #define SET_BLOCKED_SIGSET() do { \ sigset_t bl_mask; \ sigfillset(&bl_mask); \ sigdelset(&bl_mask, SIGFPE); \ sigdelset(&bl_mask, SIGILL); \ sigdelset(&bl_mask, SIGSEGV); \ sigdelset(&bl_mask, SIGBUS); \ sigdelset(&bl_mask, SIGKILL); \ pthread_sigmask(SIG_SETMASK, &bl_mask, &intel->sa_mask); \ } while (0) #define RESTORE_BLOCKED_SIGSET() do { \ pthread_sigmask(SIG_SETMASK, &intel->sa_mask, NULL); \ } while (0) #define PPTHREAD_MUTEX_LOCK() do { \ SET_BLOCKED_SIGSET(); \ pthread_mutex_lock(&intel->ctxmutex); \ } while (0) #define PPTHREAD_MUTEX_UNLOCK() do { \ pthread_mutex_unlock(&intel->ctxmutex); \ RESTORE_BLOCKED_SIGSET(); \ } while (0) #define WARN_ONCE(...) do { \ static int g_once = 1; \ if (g_once) { \ g_once = 0; \ printf("WARNING: " __VA_ARGS__); \ } \ } while (0) struct intel_driver_data { int fd; int device_id; int revision; int dri2Enabled; sigset_t sa_mask; pthread_mutex_t ctxmutex; int locked; dri_bufmgr *bufmgr; unsigned int has_exec2 : 1; /* Flag: has execbuffer2? */ unsigned int has_bsd : 1; /* Flag: has bitstream decoder for H.264? */ unsigned int has_blt : 1; /* Flag: has BLT unit? */ unsigned int has_vebox : 1; /* Flag: has VEBOX unit */ }; bool intel_driver_init(VADriverContextP ctx); void intel_driver_terminate(VADriverContextP ctx); static INLINE struct intel_driver_data * intel_driver_data(VADriverContextP ctx) { return (struct intel_driver_data *)ctx->pDriverData; } struct intel_region { int x; int y; unsigned int width; unsigned int height; unsigned int cpp; unsigned int pitch; unsigned int tiling; unsigned int swizzle; dri_bo *bo; }; #define PCI_CHIP_GM45_GM 0x2A42 #define PCI_CHIP_IGD_E_G 0x2E02 #define PCI_CHIP_Q45_G 0x2E12 #define PCI_CHIP_G45_G 0x2E22 #define PCI_CHIP_G41_G 0x2E32 #define PCI_CHIP_B43_G 0x2E42 #define PCI_CHIP_B43_G1 0x2E92 #define PCI_CHIP_IRONLAKE_D_G 0x0042 #define PCI_CHIP_IRONLAKE_M_G 0x0046 #ifndef PCI_CHIP_SANDYBRIDGE_GT1 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* Desktop */ #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* Mobile */ #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 #define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A /* Server */ #endif #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* Desktop */ #define PCI_CHIP_IVYBRIDGE_GT2 0x0162 #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */ #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */ #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ #define PCI_CHIP_HASWELL_GT2 0x0412 #define PCI_CHIP_HASWELL_GT3 0x0422 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ #define PCI_CHIP_HASWELL_M_GT2 0x0416 #define PCI_CHIP_HASWELL_M_GT3 0x0426 #define PCI_CHIP_HASWELL_S_GT1 0x040a /* Server */ #define PCI_CHIP_HASWELL_S_GT2 0x041a #define PCI_CHIP_HASWELL_S_GT3 0x042a #define PCI_CHIP_HASWELL_B_GT1 0x040b /* Reserved */ #define PCI_CHIP_HASWELL_B_GT2 0x041b #define PCI_CHIP_HASWELL_B_GT3 0x042b #define PCI_CHIP_HASWELL_E_GT1 0x040e /* Reserved */ #define PCI_CHIP_HASWELL_E_GT2 0x041e #define PCI_CHIP_HASWELL_E_GT3 0x042e #define PCI_CHIP_HASWELL_SDV_GT1 0x0c02 /* Desktop */ #define PCI_CHIP_HASWELL_SDV_GT2 0x0c12 #define PCI_CHIP_HASWELL_SDV_GT3 0x0c22 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0c06 /* Mobile */ #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0c16 #define PCI_CHIP_HASWELL_SDV_M_GT3 0x0c26 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0c0a /* Server */ #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0c1a #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0c2a #define PCI_CHIP_HASWELL_SDV_B_GT1 0x0c0b /* Reserved */ #define PCI_CHIP_HASWELL_SDV_B_GT2 0x0c1b #define PCI_CHIP_HASWELL_SDV_B_GT3 0x0c2b #define PCI_CHIP_HASWELL_SDV_E_GT1 0x0c0e /* Reserved */ #define PCI_CHIP_HASWELL_SDV_E_GT2 0x0c1e #define PCI_CHIP_HASWELL_SDV_E_GT3 0x0c2e #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 #define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A #define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */ #define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B #define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B #define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */ #define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E #define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 #define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A #define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */ #define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B #define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B #define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */ #define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E #define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E #define PCI_CHIP_BAYTRAIL_M_1 0x0F31 #define PCI_CHIP_BAYTRAIL_M_2 0x0F32 #define PCI_CHIP_BAYTRAIL_M_3 0x0F33 #define PCI_CHIP_BAYTRAIL_M_4 0x0157 #define PCI_CHIP_BAYTRAIL_D 0x0155 #define PCI_CHIP_BROADWELL_MS_GT1 0x1602 #define PCI_CHIP_BROADWELL_MS_GT2 0x1612 #define PCI_CHIP_BROADWELL_MS_GT2PLUS 0x1622 #define PCI_CHIP_BROADWELL_M_GT1_1 0x1606 #define PCI_CHIP_BROADWELL_M_GT2_1 0x1616 #define PCI_CHIP_BROADWELL_M_GT2PLUS_1 0x1626 #define PCI_CHIP_BROADWELL_M_GT1_2 0x160B #define PCI_CHIP_BROADWELL_M_GT2_2 0x161B #define PCI_CHIP_BROADWELL_M_GT2PLUS_2 0x162B #define PCI_CHIP_BROADWELL_M_GT1_3 0x160E #define PCI_CHIP_BROADWELL_M_GT2_3 0x161E #define PCI_CHIP_BROADWELL_M_GT2PLUS_3 0x162E #define PCI_CHIP_BROADWELL_D_GT1_1 0x160A #define PCI_CHIP_BROADWELL_D_GT2_1 0x161A #define PCI_CHIP_BROADWELL_D_GT2PLUS_1 0x162A #define PCI_CHIP_BROADWELL_D_GT1_2 0x160D #define PCI_CHIP_BROADWELL_D_GT2_2 0x161D #define PCI_CHIP_BROADWELL_D_GT2PLUS_2 0x162D #define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \ devid == PCI_CHIP_Q45_G || \ devid == PCI_CHIP_G45_G || \ devid == PCI_CHIP_G41_G || \ devid == PCI_CHIP_B43_G || \ devid == PCI_CHIP_B43_G1) #define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM) #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) #define IS_IRONLAKE_D(devid) (devid == PCI_CHIP_IRONLAKE_D_G) #define IS_IRONLAKE_M(devid) (devid == PCI_CHIP_IRONLAKE_M_G) #define IS_IRONLAKE(devid) (IS_IRONLAKE_D(devid) || IS_IRONLAKE_M(devid)) #define IS_SNB_GT1(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \ devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \ devid == PCI_CHIP_SANDYBRIDGE_S_GT) #define IS_SNB_GT2(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \ devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \ devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \ devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS) #define IS_GEN6(devid) (IS_SNB_GT1(devid) || \ IS_SNB_GT2(devid)) #define IS_BAYTRAIL_M1(devid) (devid == PCI_CHIP_BAYTRAIL_M_1) #define IS_BAYTRAIL_M2(devid) (devid == PCI_CHIP_BAYTRAIL_M_2) #define IS_BAYTRAIL_M3(devid) (devid == PCI_CHIP_BAYTRAIL_M_3) #define IS_BAYTRAIL_D(devid) (devid == PCI_CHIP_BAYTRAIL_D) #define IS_BAYTRAIL(devid) (IS_BAYTRAIL_M1(devid) || \ IS_BAYTRAIL_M2(devid) || \ IS_BAYTRAIL_M3(devid) || \ IS_BAYTRAIL_D(devid) ) #define IS_IVB_GT1(devid) (devid == PCI_CHIP_IVYBRIDGE_GT1 || \ devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \ devid == PCI_CHIP_IVYBRIDGE_S_GT1) #define IS_IVB_GT2(devid) (devid == PCI_CHIP_IVYBRIDGE_GT2 || \ devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \ devid == PCI_CHIP_IVYBRIDGE_S_GT2) #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || \ IS_IVB_GT2(devid) || \ IS_BAYTRAIL(devid) ) #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ devid == PCI_CHIP_HASWELL_M_GT1 || \ devid == PCI_CHIP_HASWELL_S_GT1 || \ devid == PCI_CHIP_HASWELL_B_GT1 || \ devid == PCI_CHIP_HASWELL_E_GT1 || \ devid == PCI_CHIP_HASWELL_SDV_GT1 || \ devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \ devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \ devid == PCI_CHIP_HASWELL_SDV_B_GT1 || \ devid == PCI_CHIP_HASWELL_SDV_E_GT1 || \ devid == PCI_CHIP_HASWELL_CRW_GT1 || \ devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \ devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \ devid == PCI_CHIP_HASWELL_CRW_B_GT1 || \ devid == PCI_CHIP_HASWELL_CRW_E_GT1 || \ devid == PCI_CHIP_HASWELL_ULT_GT1 || \ devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \ devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \ devid == PCI_CHIP_HASWELL_ULT_B_GT1 || \ devid == PCI_CHIP_HASWELL_ULT_E_GT1) #define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2|| \ devid == PCI_CHIP_HASWELL_M_GT2|| \ devid == PCI_CHIP_HASWELL_S_GT2|| \ devid == PCI_CHIP_HASWELL_B_GT2 || \ devid == PCI_CHIP_HASWELL_E_GT2 || \ devid == PCI_CHIP_HASWELL_SDV_GT2|| \ devid == PCI_CHIP_HASWELL_SDV_M_GT2|| \ devid == PCI_CHIP_HASWELL_SDV_S_GT2|| \ devid == PCI_CHIP_HASWELL_SDV_B_GT2 || \ devid == PCI_CHIP_HASWELL_SDV_E_GT2 || \ devid == PCI_CHIP_HASWELL_CRW_GT2|| \ devid == PCI_CHIP_HASWELL_CRW_M_GT2|| \ devid == PCI_CHIP_HASWELL_CRW_S_GT2|| \ devid == PCI_CHIP_HASWELL_CRW_B_GT2|| \ devid == PCI_CHIP_HASWELL_CRW_E_GT2|| \ devid == PCI_CHIP_HASWELL_ULT_GT2|| \ devid == PCI_CHIP_HASWELL_ULT_M_GT2|| \ devid == PCI_CHIP_HASWELL_ULT_S_GT2|| \ devid == PCI_CHIP_HASWELL_ULT_B_GT2 || \ devid == PCI_CHIP_HASWELL_ULT_E_GT2) #define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_GT3 || \ devid == PCI_CHIP_HASWELL_M_GT3 || \ devid == PCI_CHIP_HASWELL_S_GT3 || \ devid == PCI_CHIP_HASWELL_B_GT3 || \ devid == PCI_CHIP_HASWELL_E_GT3 || \ devid == PCI_CHIP_HASWELL_SDV_GT3 || \ devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \ devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \ devid == PCI_CHIP_HASWELL_SDV_B_GT3 || \ devid == PCI_CHIP_HASWELL_SDV_E_GT3 || \ devid == PCI_CHIP_HASWELL_CRW_GT3 || \ devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \ devid == PCI_CHIP_HASWELL_CRW_S_GT3 || \ devid == PCI_CHIP_HASWELL_CRW_B_GT3 || \ devid == PCI_CHIP_HASWELL_CRW_E_GT3 || \ devid == PCI_CHIP_HASWELL_ULT_GT3 || \ devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \ devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \ devid == PCI_CHIP_HASWELL_ULT_B_GT3 || \ devid == PCI_CHIP_HASWELL_ULT_E_GT3) #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ IS_HSW_GT2(devid) || \ IS_HSW_GT3(devid)) #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ IS_HASWELL(devid)) #define IS_BDW_GT1(devid) (devid == PCI_CHIP_BROADWELL_M_GT1_1 || \ devid == PCI_CHIP_BROADWELL_M_GT1_2 || \ devid == PCI_CHIP_BROADWELL_M_GT1_3 || \ devid == PCI_CHIP_BROADWELL_D_GT1_1 || \ devid == PCI_CHIP_BROADWELL_D_GT1_2 || \ devid == PCI_CHIP_BROADWELL_MS_GT1) #define IS_BDW_GT2(devid) (devid == PCI_CHIP_BROADWELL_M_GT2_1 || \ devid == PCI_CHIP_BROADWELL_M_GT2_2 || \ devid == PCI_CHIP_BROADWELL_M_GT2_3 || \ devid == PCI_CHIP_BROADWELL_D_GT2_1 || \ devid == PCI_CHIP_BROADWELL_D_GT2_2 || \ devid == PCI_CHIP_BROADWELL_MS_GT2) #define IS_BDW_GT2PLUS(devid) (devid == PCI_CHIP_BROADWELL_M_GT2PLUS_1 || \ devid == PCI_CHIP_BROADWELL_M_GT2PLUS_2 || \ devid == PCI_CHIP_BROADWELL_M_GT2PLUS_3 || \ devid == PCI_CHIP_BROADWELL_D_GT2PLUS_1 || \ devid == PCI_CHIP_BROADWELL_D_GT2PLUS_2 || \ devid == PCI_CHIP_BROADWELL_MS_GT2PLUS) #define IS_GEN8(devid) (IS_BDW_GT1(devid) || \ IS_BDW_GT2(devid) || \ IS_BDW_GT2PLUS(devid)) #endif /* _INTEL_DRIVER_H_ */ intel-driver-1.3.0/src/intel_media.h000066400000000000000000000031271231401140700173250ustar00rootroot00000000000000/* * Copyright (C) 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef INTEL_MEDIA_H #define INTEL_MEDIA_H #include #include #include #include typedef struct gen_avc_surface GenAvcSurface; struct gen_avc_surface { dri_bo *dmv_top; dri_bo *dmv_bottom; int dmv_bottom_flag; }; extern void gen_free_avc_surface(void **data); extern int intel_format_convert(float src, int out_int_bits, int out_frac_bits,int out_sign_flag); #endif /* INTEL_MEDIA_H */ intel-driver-1.3.0/src/intel_media_common.c000066400000000000000000000053361231401140700206740ustar00rootroot00000000000000/* * Copyright (C) 2006-2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include "intel_driver.h" #include "intel_media.h" static pthread_mutex_t free_avc_surface_lock = PTHREAD_MUTEX_INITIALIZER; void gen_free_avc_surface(void **data) { GenAvcSurface *avc_surface; pthread_mutex_lock(&free_avc_surface_lock); avc_surface = *data; if (!avc_surface) { pthread_mutex_unlock(&free_avc_surface_lock); return; } dri_bo_unreference(avc_surface->dmv_top); avc_surface->dmv_top = NULL; dri_bo_unreference(avc_surface->dmv_bottom); avc_surface->dmv_bottom = NULL; free(avc_surface); *data = NULL; pthread_mutex_unlock(&free_avc_surface_lock); } /* This is to convert one float to the given format interger. * For example: 1.25 to S1.6 or U2.6 and so on */ int intel_format_convert(float src, int out_int_bits, int out_frac_bits,int out_sign_flag) { unsigned char negative_flag = (src < 0.0) ? 1 : 0; float src_1 = (!negative_flag)? src: -src ; unsigned int factor = 1 << out_frac_bits; int output_value = 0; unsigned int integer_part = floorf(src_1); unsigned int fraction_part = ((int)((src_1 - integer_part) * factor)) & (factor - 1) ; output_value = (integer_part << out_frac_bits) | fraction_part; if(negative_flag) output_value = (~output_value + 1) & ((1 <<(out_int_bits + out_frac_bits)) -1); if(out_sign_flag == 1 && negative_flag) { output_value |= negative_flag <<(out_int_bits + out_frac_bits); } return output_value; } intel-driver-1.3.0/src/intel_memman.c000066400000000000000000000032041231401140700175070ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Xiang Haihao * Zou Nan hai * */ #include #include "intel_driver.h" Bool intel_memman_init(struct intel_driver_data *intel) { intel->bufmgr = intel_bufmgr_gem_init(intel->fd, BATCH_SIZE); assert(intel->bufmgr); intel_bufmgr_gem_enable_reuse(intel->bufmgr); return True; } Bool intel_memman_terminate(struct intel_driver_data *intel) { drm_intel_bufmgr_destroy(intel->bufmgr); return True; } intel-driver-1.3.0/src/intel_memman.h000066400000000000000000000003111231401140700175100ustar00rootroot00000000000000#ifndef _INTEL_MEMMAN_H_ #define _INTEL_MEMMAN_H_ Bool intel_memman_init(struct intel_driver_data *intel); Bool intel_memman_terminate(struct intel_driver_data *intel); #endif /* _INTEL_MEMMAN_H_ */ intel-driver-1.3.0/src/object_heap.c000066400000000000000000000162351231401140700173150ustar00rootroot00000000000000/* * Copyright (c) 2007 Intel Corporation. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "object_heap.h" #include "assert.h" #include #include #include #define ASSERT assert #define LAST_FREE -1 #define ALLOCATED -2 /* * Expands the heap * Return 0 on success, -1 on error */ static int object_heap_expand( object_heap_p heap ) { int i; void *new_heap_index; int next_free; int new_heap_size = heap->heap_size + heap->heap_increment; int bucket_index = new_heap_size / heap->heap_increment - 1; if (bucket_index >= heap->num_buckets) { int new_num_buckets = heap->num_buckets + 8; void **new_bucket; new_bucket = realloc(heap->bucket, new_num_buckets * sizeof(void *)); if (NULL == new_bucket) { return -1; } heap->num_buckets = new_num_buckets; heap->bucket = new_bucket; } new_heap_index = (void *) malloc( heap->heap_increment * heap->object_size ); if ( NULL == new_heap_index ) { return -1; /* Out of memory */ } heap->bucket[bucket_index] = new_heap_index; next_free = heap->next_free; for(i = new_heap_size; i-- > heap->heap_size; ) { object_base_p obj = (object_base_p) (new_heap_index + (i - heap->heap_size) * heap->object_size); obj->id = i + heap->id_offset; obj->next_free = next_free; next_free = i; } heap->next_free = next_free; heap->heap_size = new_heap_size; return 0; /* Success */ } /* * Return 0 on success, -1 on error */ int object_heap_init( object_heap_p heap, int object_size, int id_offset) { heap->object_size = object_size; heap->id_offset = id_offset & OBJECT_HEAP_OFFSET_MASK; heap->heap_size = 0; heap->heap_increment = 16; heap->next_free = LAST_FREE; heap->num_buckets = 0; heap->bucket = NULL; if (object_heap_expand(heap) == 0) { ASSERT(heap->heap_size); _i965InitMutex(&heap->mutex); return 0; } else { ASSERT(!heap->heap_size); ASSERT(!heap->bucket || !heap->bucket[0]); free(heap->bucket); return -1; } } /* * Allocates an object * Returns the object ID on success, returns -1 on error */ int object_heap_allocate( object_heap_p heap ) { object_base_p obj; int bucket_index, obj_index; _i965LockMutex(&heap->mutex); if ( LAST_FREE == heap->next_free ) { if( -1 == object_heap_expand( heap ) ) { _i965UnlockMutex(&heap->mutex); return -1; /* Out of memory */ } } ASSERT( heap->next_free >= 0 ); bucket_index = heap->next_free / heap->heap_increment; obj_index = heap->next_free % heap->heap_increment; obj = (object_base_p) (heap->bucket[bucket_index] + obj_index * heap->object_size); heap->next_free = obj->next_free; _i965UnlockMutex(&heap->mutex); obj->next_free = ALLOCATED; return obj->id; } /* * Lookup an object by object ID * Returns a pointer to the object on success, returns NULL on error */ object_base_p object_heap_lookup( object_heap_p heap, int id ) { object_base_p obj; int bucket_index, obj_index; _i965LockMutex(&heap->mutex); if ( (id < heap->id_offset) || (id > (heap->heap_size+heap->id_offset)) ) { _i965UnlockMutex(&heap->mutex); return NULL; } id &= OBJECT_HEAP_ID_MASK; bucket_index = id / heap->heap_increment; obj_index = id % heap->heap_increment; obj = (object_base_p) (heap->bucket[bucket_index] + obj_index * heap->object_size); _i965UnlockMutex(&heap->mutex); /* Check if the object has in fact been allocated */ if ( obj->next_free != ALLOCATED ) { return NULL; } return obj; } /* * Iterate over all objects in the heap. * Returns a pointer to the first object on the heap, returns NULL if heap is empty. */ object_base_p object_heap_first( object_heap_p heap, object_heap_iterator *iter ) { *iter = -1; return object_heap_next( heap, iter ); } /* * Iterate over all objects in the heap. * Returns a pointer to the next object on the heap, returns NULL if heap is empty. */ object_base_p object_heap_next( object_heap_p heap, object_heap_iterator *iter ) { object_base_p obj; int i = *iter + 1; int bucket_index, obj_index; _i965LockMutex(&heap->mutex); while ( i < heap->heap_size) { bucket_index = i / heap->heap_increment; obj_index = i % heap->heap_increment; obj = (object_base_p) (heap->bucket[bucket_index] + obj_index * heap->object_size); if (obj->next_free == ALLOCATED) { _i965UnlockMutex(&heap->mutex); *iter = i; return obj; } i++; } _i965UnlockMutex(&heap->mutex); *iter = i; return NULL; } /* * Frees an object */ void object_heap_free( object_heap_p heap, object_base_p obj ) { /* Don't complain about NULL pointers */ if (NULL != obj) { /* Check if the object has in fact been allocated */ ASSERT( obj->next_free == ALLOCATED ); _i965LockMutex(&heap->mutex); obj->next_free = heap->next_free; heap->next_free = obj->id & OBJECT_HEAP_ID_MASK; _i965UnlockMutex(&heap->mutex); } } /* * Destroys a heap, the heap must be empty. */ void object_heap_destroy( object_heap_p heap ) { object_base_p obj; int i; int bucket_index, obj_index; if (heap->heap_size) { _i965DestroyMutex(&heap->mutex); /* Check if heap is empty */ for (i = 0; i < heap->heap_size; i++) { /* Check if object is not still allocated */ bucket_index = i / heap->heap_increment; obj_index = i % heap->heap_increment; obj = (object_base_p) (heap->bucket[bucket_index] + obj_index * heap->object_size); ASSERT( obj->next_free != ALLOCATED ); } for (i = 0; i < heap->heap_size / heap->heap_increment; i++) { free(heap->bucket[i]); } free(heap->bucket); } heap->bucket = NULL; heap->heap_size = 0; heap->next_free = LAST_FREE; } intel-driver-1.3.0/src/object_heap.h000066400000000000000000000053731231401140700173230ustar00rootroot00000000000000/* * Copyright (c) 2007 Intel Corporation. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _OBJECT_HEAP_H_ #define _OBJECT_HEAP_H_ #include "i965_mutext.h" #define OBJECT_HEAP_OFFSET_MASK 0x7F000000 #define OBJECT_HEAP_ID_MASK 0x00FFFFFF typedef struct object_base *object_base_p; typedef struct object_heap *object_heap_p; struct object_base { int id; int next_free; }; struct object_heap { int object_size; int id_offset; int next_free; int heap_size; int heap_increment; _I965Mutex mutex; void **bucket; int num_buckets; }; typedef int object_heap_iterator; /* * Return 0 on success, -1 on error */ int object_heap_init( object_heap_p heap, int object_size, int id_offset); /* * Allocates an object * Returns the object ID on success, returns -1 on error */ int object_heap_allocate( object_heap_p heap ); /* * Lookup an allocated object by object ID * Returns a pointer to the object on success, returns NULL on error */ object_base_p object_heap_lookup( object_heap_p heap, int id ); /* * Iterate over all objects in the heap. * Returns a pointer to the first object on the heap, returns NULL if heap is empty. */ object_base_p object_heap_first( object_heap_p heap, object_heap_iterator *iter ); /* * Iterate over all objects in the heap. * Returns a pointer to the next object on the heap, returns NULL if heap is empty. */ object_base_p object_heap_next( object_heap_p heap, object_heap_iterator *iter ); /* * Frees an object */ void object_heap_free( object_heap_p heap, object_base_p obj ); /* * Destroys a heap, the heap must be empty. */ void object_heap_destroy( object_heap_p heap ); #endif /* _OBJECT_HEAP_H_ */ intel-driver-1.3.0/src/shaders/000077500000000000000000000000001231401140700163305ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/Makefile.am000066400000000000000000000002611231401140700203630ustar00rootroot00000000000000SUBDIRS = h264 mpeg2 render post_processing vme utils EXTRA_DIST = gpp.py # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/gpp.py000077500000000000000000000123011231401140700174700ustar00rootroot00000000000000#!/usr/bin/env python #coding=UTF-8 # Copyright © 2011 Intel Corporation # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice (including the next # paragraph) shall be included in all copies or substantial portions of the # Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. # # Authors: # Chen, Yangyang # Han, Haofu # import sys class Block: def __init__(self, ln=0, s=None): assert type(ln) == int assert type(s) == str or s == None self.lineno = ln self.text = s self.subblocks = [] def append(self, block): self.subblocks.append(block) def checkfor(self, line): import re p = r'\$\s*for\s*' if re.match(p, line) == None: raise Exception(self.__errmsg('syntax error')) tail = line.split('(', 1)[1].rsplit(')', 1) conds = tail[0].split(';') lb = tail[1] if lb.strip() != '{': raise Exception(self.__errmsg('missing "{"')) if len(conds) != 3: raise Exception(self.__errmsg('syntax error(miss ";"?)')) init = conds[0] cond = conds[1] step = conds[2] self.__parse_init(init) self.__parse_cond(cond) self.__parse_step(step) def __parse_init(self, init): inits = init.split(',') self.param_init = [] for ini in inits: try: val = eval(ini) self.param_init.append(val) except: raise Exception(self.__errmsg('non an exp: %s'%ini)) self.param_num = len(inits) def __parse_cond(self, cond): cond = cond.strip() if cond[0] in ['<', '>']: if cond[1] == '=': self.param_op = cond[:2] limit = cond[2:] else: self.param_op = cond[0] limit = cond[1:] try: self.param_limit = eval(limit) except: raise Exception(self.__errmsg('non an exp: %s'%limit)) else: raise Exception(self.__errmsg('syntax error')) def __parse_step(self, step): steps = step.split(',') if len(steps) != self.param_num: raise Exception(self.__errmsg('params number no match')) self.param_step = [] for st in steps: try: val = eval(st) self.param_step.append(val) except: raise Exception(self.__errmsg('non an exp: %s'%st)) def __errmsg(self, msg=''): return '%d: %s' % (self.lineno, msg) def readlines(f): lines = f.readlines() buf = [] for line in lines: if '\\n' in line: tmp = line.split('\\n') buf.extend(tmp) else: buf.append(line) return buf def parselines(lines): root = Block(0) stack = [root] lineno = 0 for line in lines: lineno += 1 line = line.strip() if line.startswith('$'): block = Block(lineno) block.checkfor(line) stack[-1].append(block) stack.append(block) elif line.startswith('}'): stack.pop() elif line and not line.startswith('#'): stack[-1].append(Block(lineno, line)) return root def writeblocks(outfile, blocks): buf = [] def check_cond(op, cur, lim): assert op in ['<', '>', '<=', '>='] assert type(cur) == int assert type(lim) == int return eval('%d %s %d' % (cur, op, lim)) def do_writeblock(block, curs): if block.text != None: import re p = r'\%(\d+)' newline = block.text params = set(re.findall(p, block.text)) for param in params: index = int(param) - 1 if index >= len(curs): raise Exception('%d: too many param(%%%d)'%(block.lineno, index+1)) newline = newline.replace('%%%d'%(index+1), str(curs[index])) if newline and \ not newline.startswith('.') and \ not newline.endswith(':') and \ not newline.endswith(';'): newline += ';' buf.append(newline) else: for_curs = block.param_init while check_cond(block.param_op, for_curs[0], block.param_limit): for sblock in block.subblocks: do_writeblock(sblock, for_curs) for i in range(0, block.param_num): for_curs[i] += block.param_step[i] for block in blocks.subblocks: do_writeblock(block, []) outfile.write('\n'.join(buf)) outfile.write('\n') if __name__ == '__main__': argc = len(sys.argv) if argc == 1: print >>sys.stderr, 'no input file' sys.exit(0) try: infile = open(sys.argv[1], 'r') except IOError: print >>sys.stderr, 'can not open %s' % sys.argv[1] sys.exit(1) if argc == 2: outfile = sys.stdout else: try: outfile = open(sys.argv[2], 'w') except IOError: print >>sys.stderr, 'can not write to %s' % sys.argv[2] sys.exit(1) lines = readlines(infile) try: infile.close() except IOError: pass blocks = parselines(lines) writeblocks(outfile, blocks) intel-driver-1.3.0/src/shaders/h264/000077500000000000000000000000001231401140700170135ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/h264/Makefile.am000066400000000000000000000001701231401140700210450ustar00rootroot00000000000000SUBDIRS = ildb mc # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/h264/ildb/000077500000000000000000000000001231401140700177255ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB.inc000066400000000000000000001054341231401140700216320ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__AVC_ILDB_HEADER__) // Make sure this file is only included once #define __AVC_ILDB_HEADER__ // Module name: AVC_ILDB.inc #undef ORIX #undef ORIY //========== Root thread input parameters ================================================== #define RootParam r1 // :w #define MBsCntX r1.0 // :w, MB count per row #define MBsCntY r1.1 // :w, MB count per col //#define PicType r1.2 // :w, Picture type #define MaxThreads r1.3 // :w, Max Thread limit #define EntrySignature r1.4 // :w, Debug flag #define BitFields r1.5 // :uw #define MbaffFlag BIT0 // :w, mbaff flag, bit 0 in BitFields #define BotFieldFlag BIT1 // :w, bottom field flag, bit 1 in BitFields #define CntlDataExpFlag BIT2 // :w, Control Data Expansion Flag, bit 2 in BitFields #define RampConst r1.12 // 8 :ub, Ramp constant, r1.12 - r1.19:ub #define StepToNextMB r1.20 // :b, 2 bytes #define Minus2Minus1 r1.22 // :b, 2 bytes // next one starts at r1.11:w #define TopFieldFlag 0xFFFD // :w, top field flag, used to set bit1 to 0. //========== Root Locals ============================================================= // Variables in root kernel for launching child therad #define ChildParam r2.0 // :w //Not used #define URBOffset r2.3 // :w, Each row occupies 4 URB entries. All children in the same row use the same set of URB entries #define CurCol r2.10 // :w, current col #define CurColB r2.20 // :b, current col #define CurRow r2.11 // :w, current row #define CurRowB r2.22 // :b, current row #define LastCol r2.12 // :w, last col #define LastRow r2.13 // :w, last row // Root local constants during spawning process #define Col_Boundary r3.0 // :w, #define Row_Boundary r3.1 // :w, //#define TotalBlocks r3.2 // :w, Total blocks in the frame #define URB_EntriesPerMB_2 r3.3 // :w, = URB entries per MB, but in differnt form #define URBOffsetUVBase r3.4 // :w, UV Base offset in URB #define Temp1_D r3.6 // :d: #define Temp1_W r3.12 // :w, Temp1 #define Temp1_B r3.24 // :b, = Temp1_W #define Temp2_W r3.13 // :w, Temp2 #define Temp2_B r3.26 // :b, = Temp2_W // Root local variables #define JumpTable r4 // :d, jump table #define JUMPTABLE_BASE 4*32 #define JumpAddr a0.7 #define TopRowForScan r5.0 // :w, track the top row for scan. All rows above this row is deblocked already. // Child Thread R0 Header Field #define MRF0 m0 #define CT_R0Hdr m1 /* .declare GatewayAperture Base=r50.0 ElementSize=4 SrcRegion=REGION(8,1) Type=ud #define GatewayApertureB 1600 // r50 byte offset from r0.0 // Chroma root thread updates luma root's ThreadLimit at r10.0:w via gateway #define ThreadLimit r62.0 // :w, thread limit //r56.0 #define THREAD_LIMIT_OFFSET 0x01800000 // Offset from r50 to r56 = 12*32 = 384 = 0x0180. 0x180 << 16 = 0x01800000 //#define THREAD_LIMIT_OFFSET 0x00C00000 // Offset from r50 to r56 = 6*32 = 192 = 0x00C0. 0xC0 << 16 = 0x00C00000 */ // Gateway size is 16 GRF. 68 rows of MBs takes 9 GRFs (r6 - r14) // For CTG: Expended to support 1280 rows of pixel (80 rows of MBs). It requires 10 GRFs (r6 - r15) .declare GatewayAperture Base=r6.0 ElementSize=4 SrcRegion=REGION(8,1) Type=ud #define GatewayApertureB 192 // r0.0 byte offset from r0.0 // Chroma root thread updates luma root's ThreadLimit at r10.0:w via gateway #define ThreadLimit r18.0 // :w, thread limit #define THREAD_LIMIT_OFFSET 0x01800000 // Offset from r50 to r56 = 12*32 = 384 = 0x0180. 0x180 << 16 = 0x01800000 #define TotalBlocks r18.1 // :w, Total blocks in the frame // Root local variables #define ChildThreadsID r19.0 // :w, Child thread ID, unique to each child #define OutstandingThreads r20.0 // :w, Outstanding threads #define ProcessedMBs r20.1 // :w, # of MBs processed #define URBOffset r21.0 // :w, Each row occupies 4 URB entries. All children in the same row use the same set of URB entries //================================================================================= #define ScoreBd_Size 128 //96 // size of Status[] or ProcCol[] #define ScoreBd_Idx 2 //#define Saved_Col 0 #define StatusAddr a0.4 // :w, point to r50 //================================================================================= // Gateway payload #define GatewayPayload r48.0 // :ud #define GatewayPayloadKey r48.8 // :uw #define DispatchID r48.20 // :ub #define RegBase_GatewaySize r48.5 // :ud, used in open a gateway #define Offset_Length r48.5 // :ud, used in forwardmsg back to root #define EUID_TID r48.9 // :uw, used in forwardmsg back to root // Gateway response #define GatewayResponse r49.0 // :ud, one GRF #define URBWriteMsgDesc a0.0 // Used in URB write, :ud #define URBWriteMsgDescLow a0.0 // Used in URB write, :uw #define URBWriteMsgDescHigh a0.1 // Used in URB write, :uw .declare WritebackResponse Base=r50 ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 1 GRF for write backs ///////////////////////////////////////////////////////////////////////////////////////////// // IDesc Order Offset // // 0) luma root 0 from luma root // 1) luma child 16 from luma root // 2) chroma root 32 from luma root // 3) chroma child 16 from chroma root // 4) luma field root 0 from luma field root // 5) luma field child 16 from luma field root // 6) chroma field root 32 from luma field root // 7) chroma field child 16 from chroma field root // 8) luma Mbaff root 0 from luma Mbaff root // 9) luma Mbaff child 16 from luma Mbaff root // 10) chroma Mbaff root 32 from luma Mbaff root // 11) chroma Mbaff child 16 from chroma Mbaff root // IDesc offset within non-mbaff or mbaff mode #define CHROMA_ROOT_OFFSET 32 // Offset from luma root to chroma root #define CHILD_OFFSET 16 // Offset from luma root to luma child, // and from chroma root to chroma child ///////////////////////////////////////////////////////////////////////////////////////////// //========== End of Root Variables ====================================================== //========== Child thread input parameters ============================================== //#define MBsCntX r1.0 // :w, MB count per row (same as root) //#define MBsCntY r1.1 // :w, MB count per col (same as root) //#define PicTypeC r1.2 // :w, Picture type same as root thread (same as root) #define URBOffsetC r1.3 // :w, #define EntrySignatureC r1.4 // :w, Debug field (same as root) //#define BitFields r1.5 // :w (same as root) //#define MbaffFlag BIT0 // :w, mbaff flag, bit 0 in BitFields //#define BotFieldFlag BIT1 // :w, bottom field flag, bit 1 in BitFields //#define CntlDataExpFlag BIT2 // :w, Control Data Expansion Flag, bit 2 in BitFields #define RampConstC r1.12 // 8 :ub, Ramp constant, r1.12 - r1.19:ub. #define ORIX r1.10 // :w, carry over from root r1 in MB count #define ORIY r1.11 // :w, carry over from root r1 in MB count #define LastColC r1.12 // :w, last col #define LastRowC r1.13 // :w, last row .declare GatewayApertureC Base=r1.0 ElementSize=4 SrcRegion=REGION(8,1) Type=ud #define GatewayApertureCBase 32 // r1 byte offset from r0.0 //========== Child Variables ============================================================ // Mbaff Alpha, Beta, Tc0 vectors for an edge .declare Mbaff_ALPHA Base=r14.0 ElementSize=2 SrcRegion=REGION(8,1) Type=uw // r14 .declare Mbaff_BETA Base=r15.0 ElementSize=2 SrcRegion=REGION(8,1) Type=uw // r15 .declare Mbaff_TC0 Base=r16.0 ElementSize=2 SrcRegion=REGION(8,1) Type=uw // r16 .declare RRampW Base=r17.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w // r17 .declare Mbaff_ALPHA2 Base=r45.0 ElementSize=2 SrcRegion=REGION(8,1) Type=uw // alpha2 = (alpha >> 2) + 2 #define ORIX_CUR r46.0 // :w, current block origin X in bytes #define ORIY_CUR r46.1 // :w, current block origin Y in bytes #define ORIX_LEFT r46.2 // :w, left block origin X in bytes #define ORIY_LEFT r46.3 // :w, left block origin Y in bytes #define ORIX_TOP r46.4 // :w, top block origin X in bytes #define ORIY_TOP r46.5 // :w, top block origin Y in bytes //#define FilterSampleFlag r46.6 // :uw, #define CTemp0_W r46.7 // :w, child Temp0 #define alpha r46.8 // :w, Scaler version for non Mbaff #define beta r46.9 // :w, Scaler version for non Mbaff #define tc0 r46.20 // 4 :ub, r46.20 ~ r46.23, Scaler version for non Mbaff #define MaskA r46.12 // :uw #define MaskB r46.13 // :uw // Child control flags #define DualFieldMode r47.0 // Cur MB is frame based, above MB is field based in mbaff mode // :uw, 0 = not in dual field mode, 1 = in dual field mode, filter both top and bot fields #define GateWayOffsetC r47.1 // :w, Gateway offset for child writing into root space #define CntrlDataOffsetY r47.1 // :ud, MB control data data offset #define alpha2 r47.4 // :uw, alpha2 = (alpha >> 2) + 2 #define VertEdgePattern r47.5 // :uw, #define CTemp1_W r47.6 // :w, child Temp1 #define CTemp1_B r47.12 // :b, = child Temp1_W #define CTemp2_W r47.7 // :w, child Temp2 #define CTemp2_B r47.14 // :b, = child Temp2_W // Used in child #define ECM_AddrReg a0.4 // Edge Control Map register #define P_AddrReg a0.6 // point to P samples in left or top MB #define Q_AddrReg a0.7 // point to Q samples in cur MB .declare RTempD Base=r26.0 ElementSize=4 SrcRegion=REGION(8,1) Type=d // r26-27 .declare RTempB Base=r26.0 ElementSize=1 SrcRegion=REGION(8,4) Type=ub // r26-27 .declare RTempW Base=r26.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w // r26-27 #define LEFT_TEMP_D RTempD #define LEFT_TEMP_B RTempB #define LEFT_TEMP_W RTempW .declare TempRow0 Base=r26.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare TempRow0B Base=r26.0 ElementSize=1 SrcRegion=REGION(8,2) Type=ub .declare TempRow1 Base=r27.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare TempRow1B Base=r27.0 ElementSize=1 SrcRegion=REGION(8,2) Type=ub .declare CUR_TEMP_D Base=r28.0 ElementSize=4 SrcRegion=REGION(8,1) Type=d // 8 GRFs .declare CUR_TEMP_B Base=r28.0 ElementSize=1 SrcRegion=REGION(8,4) Type=ub .declare CUR_TEMP_W Base=r28.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w #define FilterSampleFlag r28.0 // :uw, .declare A Base=r28.0 ElementSize=2 SrcRegion=REGION(16,1) Type=w .declare BB Base=r29.0 ElementSize=2 SrcRegion=REGION(16,1) Type=w .declare TempRow3 Base=r30.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare TempRow3B Base=r30.0 ElementSize=1 SrcRegion=REGION(8,2) Type=ub .declare tc0_exp Base=r30.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare tc8 Base=r30.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare tc_exp Base=r31.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare tx_exp_8 Base=r31.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare q0_p0 Base=r32.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare ABS_q0_p0 Base=r33.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare ap Base=r34.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare aq Base=r35.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w // These buffers have the src data for each edge to be beblocked. // They have modified pixels from previous edges. // // Y: // +----+----+----+----+----+----+----+----+ // | p3 | p2 | P1 | p0 | q0 | q1 | q2 | q3 | // +----+----+----+----+----+----+----+----+ // // p3 = r[P_AddrReg, 0]<16;16,1> // p2 = r[P_AddrReg, 16]<16;16,1> // p1 = r[P_AddrReg, 32]<16;16,1> // p0 = r[P_AddrReg, 48]<16;16,1> // q0 = r[Q_AddrReg, 0]<16;16,1> // q1 = r[Q_AddrReg, 16]<16;16,1> // q2 = r[Q_AddrReg, 32]<16;16,1> // q3 = r[Q_AddrReg, 48]<16;16,1> .declare p0123_W Base=r36.0 ElementSize=2 SrcRegion=REGION(16,1) Type=uw // r36, r37 .declare q0123_W Base=r38.0 ElementSize=2 SrcRegion=REGION(16,1) Type=uw // r38, r39 .declare p3 Base=r36.0 ElementSize=1 SrcRegion=REGION(8,1) Type=ub .declare p2 Base=r36.16 ElementSize=1 SrcRegion=REGION(8,1) Type=ub .declare p1 Base=r37.0 ElementSize=1 SrcRegion=REGION(8,1) Type=ub .declare p0 Base=r37.16 ElementSize=1 SrcRegion=REGION(8,1) Type=ub .declare q0 Base=r38.0 ElementSize=1 SrcRegion=REGION(8,1) Type=ub .declare q1 Base=r38.16 ElementSize=1 SrcRegion=REGION(8,1) Type=ub .declare q2 Base=r39.0 ElementSize=1 SrcRegion=REGION(8,1) Type=ub .declare q3 Base=r39.16 ElementSize=1 SrcRegion=REGION(8,1) Type=ub .declare TempRow2 Base=r38.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w // Temp space for mbaff dual field mode #define ABOVE_CUR_MB_BASE 40*GRFWIB // Byte offset to r40 .declare ABOVE_CUR_MB_YW Base=r40 ElementSize=2 SrcRegion=REGION(8,1) Type=uw .declare ABOVE_CUR_MB_UW Base=r40 ElementSize=2 SrcRegion=REGION(8,1) Type=uw .declare P0_plus_P1 Base=r41.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare Q0_plus_Q1 Base=r42.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare P2_plus_P3 Base=r43.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare Q2_plus_Q3 Base=r44.0 ElementSize=2 SrcRegion=REGION(8,1) Type=w ////////////////////////////////////////////////////////////////////////////////////////// // MB control data reference // Expanded control data is in r18 - r25 .declare CNTRL_DATA_D Base=r18 ElementSize=4 SrcRegion=REGION(8,1) Type=ud // For read, 8 GRFs #define CNTRL_DATA_BASE 18*GRFWIB // Base offset to r18 // Bit mask for extracting bits #define MbaffFrameFlag 0x01 #define FieldModeCurrentMbFlag 0x02 #define FieldModeLeftMbFlag 0x04 #define FieldModeAboveMbFlag 0x08 #define FilterInternal8x8EdgesFlag 0x10 #define FilterInternal4x4EdgesFlag 0x20 #define FilterLeftMbEdgeFlag 0x40 #define FilterTopMbEdgeFlag 0x80 #define DISABLE_ILDB_FLAG 0x01 // Exact bit pattern for left and cur MB coding mode (frame vs. field) #define LEFT_FRAME_CUR_FRAME 0x00 #define LEFT_FRAME_CUR_FIELD 0x02 #define LEFT_FIELD_CUR_FRAME 0x04 #define LEFT_FIELD_CUR_FIELD 0x06 // Exact bit pattern for above and cur MB coding mode (frame vs. field) #define ABOVE_FRAME_CUR_FRAME 0x00 #define ABOVE_FRAME_CUR_FIELD 0x02 #define ABOVE_FIELD_CUR_FRAME 0x08 #define ABOVE_FIELD_CUR_FIELD 0x0A //========== MB control data field offset in byte ========== #if !defined(_APPLE) // GRF0 - GRF1 holds original control data // GRF0 #define HorizOrigin 0 #define VertOrigin 1 #define BitFlags 2 // Bit flags #define bbSinternalLeftVert 4 // Internal left vertical bS, 2 bits per bS for 4 Y pixels and 2 U/V pixels #define bbSinternalMidVert 5 // Internal mid vertical bS #define bbSinternalRightVert 6 // Internal right vertical bS #define bbSinternalTopHorz 7 // Internal top horizontal bS #define bbSinternalMidHorz 8 // Internal mid horizontal bS #define bbSinternalBotHorz 9 // Internal bottom horizontal bS #define wbSLeft0 10 // External left vertical bS (0), 4 bits per bS for 4 Y pixels and 2 U/V pixels, and byte 11 #define wbSLeft1 12 // External left vertical bS (1), and byte 13 #define wbSTop0 14 // External top horizontal bS (0), and byte 15 #define wbSTop1 16 // Externaltop horizontal bS (1), and byte 17 #define bIndexAinternal_Y 18 // Internal index A for Y #define bIndexBinternal_Y 19 // Internal index B for Y #define bIndexAleft0_Y 20 // Left index A for Y (0) #define bIndexBleft0_Y 21 // Left index B for Y (0) #define bIndexAleft1_Y 22 // Left index A for Y (1) #define bIndexBleft1_Y 23 // Left index B for Y (1) #define bIndexAtop0_Y 24 // Top index A for Y (0) #define bIndexBtop0_Y 25 // Top index B for Y (0) #define bIndexAtop1_Y 26 // Top index A for Y (1) #define bIndexBtop1_Y 27 // Top index B for Y (1) #define bIndexAinternal_Cb 28 // Internal index A for Cb #define bIndexBinternal_Cb 29 // Internal index B for Cb #define bIndexAleft0_Cb 30 // Left index A for Cb (0) #define bIndexBleft0_Cb 31 // Left index B for Cb (0) // GRF1 #define bIndexAleft1_Cb 32 // Left index A for Cb (1) #define bIndexBleft1_Cb 33 // Left index B for Cb (1) #define bIndexAtop0_Cb 34 // Top index A for Cb (0) #define bIndexBtop0_Cb 35 // Top index B for Cb (0) #define bIndexAtop1_Cb 36 // Top index A for Cb (1) #define bIndexBtop1_Cb 37 // Top index B for Cb (1) #define bIndexAinternal_Cr 38 // Internal index A for Cr #define bIndexBinternal_Cr 39 // Internal index B for Cr #define bIndexAleft0_Cr 40 // Left index A for Cr (0) #define bIndexBleft0_Cr 41 // Left index B for Cr (0) #define bIndexAleft1_Cr 42 // Left index A for Cr (1) #define bIndexBleft1_Cr 43 // Left index B for Cr (1) #define bIndexAtop0_Cr 44 // Top index A for Cr (0) #define bIndexBtop0_Cr 45 // Top index B for Cr (0) #define bIndexAtop1_Cr 46 // Top index A for Cr (1) #define bIndexBtop1_Cr 47 // Top index B for Cr (1) #define ExtBitFlags 48 // Extended bit flags, such as disable ILDB bits // Offset 49 - 63 not used //===== GRF2 - GRF7 hold expanded control data ===== // GRF2 #define wEdgeCntlMap_IntLeftVert 64 // Derived from bbSinternalLeftVert, 1 bit per pixel #define wEdgeCntlMap_IntMidVert 66 // Derived from bbSinternalLeftVert #define wEdgeCntlMap_IntRightVert 68 // Derived from bbSinternalRightVert #define wEdgeCntlMap_IntTopHorz 70 // Derived from bbSinternalTopHorz, 1bit per pixel #define wEdgeCntlMap_IntMidHorz 72 // Derived from bbSinternalMidHorz #define wEdgeCntlMap_IntBotHorz 74 // Derived from bbSinternalBotHorz // Offset 76 - 79 not used #define wEdgeCntlMapA_ExtLeftVert0 80 // Derived from wbSLeft0, 1bit per pixel #define wEdgeCntlMapB_ExtLeftVert0 82 // Derived from wbSLeft0 #define wEdgeCntlMapA_ExtTopHorz0 84 // Derived from wbSTop0, 1bit per pixel #define wEdgeCntlMapB_ExtTopHorz0 86 // Derived from wbSTop0 #define wEdgeCntlMapA_ExtLeftVert1 88 // Derived from wbSLeft1, 1bit per pixel #define wEdgeCntlMapB_ExtLeftVert1 90 // Derived from wbSLeft1 #define wEdgeCntlMapA_ExtTopHorz1 92 // Derived from wbSTop1, 1bit per pixel #define wEdgeCntlMapB_ExtTopHorz1 94 // Derived from wbSTop1 // GRF3 #define bTc0_v00_0_Y 96 // Derived from bSv00_0 and bIndexAleft0_Y, 4 pixels per tc0 #define bTc0_v10_0_Y 97 // Derived from bSv10_0 and bIndexAleft0_Y #define bTc0_v20_0_Y 98 // Derived from bSv20_0 and bIndexAleft0_Y #define bTc0_v30_0_Y 99 // Derived from bSv30_0 and bIndexAleft0_Y #define bTc0_v01_Y 100 // Derived from bSv01 and bIndexAinternal_Y #define bTc0_v11_Y 101 // Derived from bSv11 and bIndexAinternal_Y #define bTc0_v21_Y 102 // Derived from bSv21 and bIndexAinternal_Y #define bTc0_v31_Y 103 // Derived from bSv31 and bIndexAinternal_Y #define bTc0_v02_Y 104 // Derived from bSv02 and bIndexAinternal_Y #define bTc0_v12_Y 105 // Derived from bSv12 and bIndexAinternal_Y #define bTc0_v22_Y 106 // Derived from bSv22 and bIndexAinternal_Y #define bTc0_v32_Y 107 // Derived from bSv32 and bIndexAinternal_Y #define bTc0_v03_Y 108 // Derived from bSv03 and bIndexAinternal_Y #define bTc0_v13_Y 109 // Derived from bSv13 and bIndexAinternal_Y #define bTc0_v23_Y 110 // Derived from bSv23 and bIndexAinternal_Y #define bTc0_v33_Y 111 // Derived from bSv33 and bIndexAinternal_Y #define bTc0_h00_0_Y 112 // Derived from bSh00_0 and bIndexAleft0_Y #define bTc0_h01_0_Y 113 // Derived from bSh01_0 and bIndexAleft0_Y #define bTc0_h02_0_Y 114 // Derived from bSh02_0 and bIndexAleft0_Y #define bTc0_h03_0_Y 115 // Derived from bSh03_0 and bIndexAleft0_Y #define bTc0_h10_Y 116 // Derived from bSh10 and bIndexAinternal_Y #define bTc0_h11_Y 117 // Derived from bSh11 and bIndexAinternal_Y #define bTc0_h12_Y 118 // Derived from bSh12 and bIndexAinternal_Y #define bTc0_h13_Y 119 // Derived from bSh13 and bIndexAinternal_Y #define bTc0_h20_Y 120 // Derived from bSh20 and bIndexAinternal_Y #define bTc0_h21_Y 121 // Derived from bSh21 and bIndexAinternal_Y #define bTc0_h22_Y 122 // Derived from bSh22 and bIndexAinternal_Y #define bTc0_h23_Y 123 // Derived from bSh23 and bIndexAinternal_Y #define bTc0_h30_Y 124 // Derived from bSh30 and bIndexAinternal_Y #define bTc0_h31_Y 125 // Derived from bSh31 and bIndexAinternal_Y #define bTc0_h32_Y 126 // Derived from bSh32 and bIndexAinternal_Y #define bTc0_h33_Y 127 // Derived from bSh33 and bIndexAinternal_Y // GRF4 #define bAlphaLeft0_Y 128 // Derived from bIndexAleft0_Y #define bBetaLeft0_Y 129 // Derived from bIndexBleft0_Y #define bAlphaTop0_Y 130 // Derived from bIndexAtop0_Y #define bBetaTop0_Y 131 // Derived from bIndexBtop0_Y #define bAlphaInternal_Y 132 // Derived from bIndexAinternal_Y #define bBetaInternal_Y 133 // Derived from bIndexBinternal_Y // Offset 134 - 135 not used // Offset 136 - 143 not used #define bAlphaLeft1_Y 144 // Derived from bIndexAleft1_Y Used in Mbaff mode only #define bBetaLeft1_Y 145 // Derived from bIndexBleft1_Y Used in Mbaff mode only #define bAlphaTop1_Y 146 // Derived from bIndexAtop1_Y Used in Mbaff mode only #define bBetaTop1_Y 147 // Derived from bIndexBtop1_Y Used in Mbaff mode only // Offset 148 - 151 not used #define bTc0_v00_1_Y 152 // Derived from bSv00_1 and bIndexAleft1_Y Used in Mbaff mode only #define bTc0_v10_1_Y 153 // Derived from bSv10_1 and bIndexAleft1_Y Used in Mbaff mode only #define bTc0_v20_1_Y 154 // Derived from bSv20_1 and bIndexAleft1_Y Used in Mbaff mode only #define bTc0_v30_1_Y 155 // Derived from bSv30_1 and bIndexAleft1_Y Used in Mbaff mode only #define bTc0_h00_1_Y 156 // Derived from bSh00_1 and bIndexAleft1_Y Used in Mbaff mode only #define bTc0_h01_1_Y 157 // Derived from bSh01_1 and bIndexAleft1_Y Used in Mbaff mode only #define bTc0_h02_1_Y 158 // Derived from bSh02_1 and bIndexAleft1_Y Used in Mbaff mode only #define bTc0_h03_1_Y 159 // Derived from bSh03_1 and bIndexAleft1_Y Used in Mbaff mode only // GRF5 #define bTc0_v00_0_Cb 160 // Derived from bSv00_0 and bIndexAleft0_Cb, 2 pixels per tc0 Left0 #define bTc0_v10_0_Cb 161 // Derived from bSv10_0 and bIndexAleft0_Cb #define bTc0_v20_0_Cb 162 // Derived from bSv20_0 and bIndexAleft0_Cb #define bTc0_v30_0_Cb 163 // Derived from bSv30_0 and bIndexAleft0_Cb #define bTc0_v02_Cb 164 // Derived from bSv02 and bIndexAinternal_Cb MidVert #define bTc0_v12_Cb 165 // Derived from bSv12 and bIndexAinternal_Cb #define bTc0_v22_Cb 166 // Derived from bSv22 and bIndexAinternal_Cb #define bTc0_v32_Cb 167 // Derived from bSv32 and bIndexAinternal_Cb #define bTc0_h00_0_Cb 168 // Derived from bSh00_0 and bIndexAleft0_Cb Top0 #define bTc0_h01_0_Cb 169 // Derived from bSh01_0 and bIndexAleft0_Cb #define bTc0_h02_0_Cb 170 // Derived from bSh02_0 and bIndexAleft0_Cb #define bTc0_h03_0_Cb 171 // Derived from bSh03_0 and bIndexAleft0_Cb #define bTc0_h20_Cb 172 // Derived from bSh20 and bIndexAinternal_Cb MidHorz #define bTc0_h21_Cb 173 // Derived from bSh21 and bIndexAinternal_Cb #define bTc0_h22_Cb 174 // Derived from bSh22 and bIndexAinternal_Cb #define bTc0_h23_Cb 175 // Derived from bSh23 and bIndexAinternal_Cb #define bTc0_v00_0_Cr 176 // Derived from bSv00_0 and bIndexAleft0_Cr, 2 pixels per tc0 Left0 #define bTc0_v10_0_Cr 177 // Derived from bSv10_0 and bIndexAleft0_Cr #define bTc0_v20_0_Cr 178 // Derived from bSv20_0 and bIndexAleft0_Cr #define bTc0_v30_0_Cr 179 // Derived from bSv30_0 and bIndexAleft0_Cr #define bTc0_v02_Cr 180 // Derived from bSv02 and bIndexAinternal_Cr Mid Vert #define bTc0_v12_Cr 181 // Derived from bSv12 and bIndexAinternal_Cr #define bTc0_v22_Cr 182 // Derived from bSv22 and bIndexAinternal_Cr #define bTc0_v32_Cr 183 // Derived from bSv32 and bIndexAinternal_Cr #define bTc0_h00_0_Cr 184 // Derived from bSh00_0 and bIndexAleft0_Cr, 2 pixels per tc0 Top0 #define bTc0_h01_0_Cr 185 // Derived from bSh01_0 and bIndexAleft0_Cr #define bTc0_h02_0_Cr 186 // Derived from bSh02_0 and bIndexAleft0_Cr #define bTc0_h03_0_Cr 187 // Derived from bSh03_0 and bIndexAleft0_Cr #define bTc0_h20_Cr 188 // Derived from bSh20 and bIndexAinternal_Cr Mid Horz #define bTc0_h21_Cr 189 // Derived from bSh21 and bIndexAinternal_Cr #define bTc0_h22_Cr 190 // Derived from bSh22 and bIndexAinternal_Cr #define bTc0_h23_Cr 191 // Derived from bSh23 and bIndexAinternal_Cr // GRF6 #define bAlphaLeft0_Cb 192 // Derived from bIndexAleft0_Cb #define bBetaLeft0_Cb 193 // Derived from bIndexBleft0_Cb #define bAlphaTop0_Cb 194 // Derived from bIndexAtop0_Cb #define bBetaTop0_Cb 195 // Derived from bIndexBtop0_Cb #define bAlphaInternal_Cb 196 // Derived from bIndexAinternal_Cb #define bBetaInternal_Cb 197 // Derived from bIndexBinternal_Cb // Offset 198 - 199 not used #define bAlphaLeft0_Cr 200 // Derived from bIndexAleft0_Cr #define bBetaLeft0_Cr 201 // Derived from bIndexBleft0_Cr #define bAlphaTop0_Cr 202 // Derived from bIndexAtop0_Cr #define bBetaTop0_Cr 203 // Derived from bIndexBtop0_Cr #define bAlphaInternal_Cr 204 // Derived from bIndexAinternal_Cr #define bBetaInternal_Cr 205 // Derived from bIndexBinternal_Cr // Offset 206 - 223 not used // GRF7 #define bAlphaLeft1_Cb 224 // Derived from bIndexAleft1_Cb Used in Mbaff mode only #define bBetaLeft1_Cb 225 // Derived from bIndexBleft1_Cb Used in Mbaff mode only #define bAlphaTop1_Cb 226 // Derived from bIndexAtop1_Cb Used in Mbaff mode only #define bBetaTop1_Cb 227 // Derived from bIndexBtop1_Cb Used in Mbaff mode only // Offset 228 - 231 not used #define bTc0_v00_1_Cb 232 // Derived from bSv00_1 and bIndexAleft1_Cb Used in Mbaff mode only #define bTc0_v10_1_Cb 233 // Derived from bSv10_1 and bIndexAleft1_Cb Used in Mbaff mode only #define bTc0_v20_1_Cb 234 // Derived from bSv20_1 and bIndexAleft1_Cb Used in Mbaff mode only #define bTc0_v30_1_Cb 235 // Derived from bSv30_1 and bIndexAleft1_Cb Used in Mbaff mode only #define bTc0_h00_1_Cb 236 // Derived from bSh00_1 and bIndexAleft1_Cb Used in Mbaff mode only #define bTc0_h01_1_Cb 237 // Derived from bSh01_1 and bIndexAleft1_Cb Used in Mbaff mode only #define bTc0_h02_1_Cb 238 // Derived from bSh02_1 and bIndexAleft1_Cb Used in Mbaff mode only #define bTc0_h03_1_Cb 239 // Derived from bSh03_1 and bIndexAleft1_Cb Used in Mbaff mode only #define bAlphaLeft1_Cr 240 // Derived from bIndexAleft1_Cr Used in Mbaff mode only #define bBetaLeft1_Cr 241 // Derived from bIndexBleft1_Cr Used in Mbaff mode only #define bAlphaTop1_Cr 242 // Derived from bIndexAtop1_Cr Used in Mbaff mode only #define bBetaTop1_Cr 243 // Derived from bIndexBtop1_Cr Used in Mbaff mode only // Offset 244 - 247 not used #define bTc0_v00_1_Cr 248 // Derived from bSv00_1 and bIndexAleft1_Cr Used in Mbaff mode only #define bTc0_v10_1_Cr 249 // Derived from bSv10_1 and bIndexAleft1_Cr Used in Mbaff mode only #define bTc0_v20_1_Cr 250 // Derived from bSv20_1 and bIndexAleft1_Cr Used in Mbaff mode only #define bTc0_v30_1_Cr 251 // Derived from bSv30_1 and bIndexAleft1_Cr Used in Mbaff mode only #define bTc0_h00_1_Cr 252 // Derived from bSh00_1 and bIndexAleft1_Cr Used in Mbaff mode only #define bTc0_h01_1_Cr 253 // Derived from bSh01_1 and bIndexAleft1_Cr Used in Mbaff mode only #define bTc0_h02_1_Cr 254 // Derived from bSh02_1 and bIndexAleft1_Cr Used in Mbaff mode only #define bTc0_h03_1_Cr 255 // Derived from bSh03_1 and bIndexAleft1_Cr Used in Mbaff mode only #else // _APPLE is defined //******** Crestline for Apple, progressive only, 88 bytes ********** // GRF0 #define HorizOrigin 0 #define VertOrigin 1 #define BitFlags 2 // Bit flags #define wEdgeCntlMap_IntLeftVert 4 // Derived from bbSinternalLeftVert, 1 bit per pixel #define wEdgeCntlMap_IntMidVert 6 // Derived from bbSinternalLeftVert #define wEdgeCntlMap_IntRightVert 8 // Derived from bbSinternalRightVert #define wEdgeCntlMap_IntTopHorz 10 // Derived from bbSinternalTopHorz, 1bit per pixel #define wEdgeCntlMap_IntMidHorz 12 // Derived from bbSinternalMidHorz #define wEdgeCntlMap_IntBotHorz 14 // Derived from bbSinternalBotHorz #define wEdgeCntlMapA_ExtLeftVert0 16 // Derived from wbSLeft0, 1bit per pixel #define wEdgeCntlMapB_ExtLeftVert0 18 // Derived from wbSLeft0 #define wEdgeCntlMapA_ExtTopHorz0 20 // Derived from wbSTop0, 1bit per pixel #define wEdgeCntlMapB_ExtTopHorz0 22 // Derived from wbSTop0 #define bAlphaLeft0_Y 24 // Derived from bIndexAleft0_Y #define bBetaLeft0_Y 25 // Derived from bIndexBleft0_Y #define bAlphaTop0_Y 26 // Derived from bIndexAtop0_Y #define bBetaTop0_Y 27 // Derived from bIndexBtop0_Y #define bAlphaInternal_Y 28 // Derived from bIndexAinternal_Y #define bBetaInternal_Y 29 // Derived from bIndexBinternal_Y // GRF1 #define bTc0_v00_0_Y 32 // Derived from bSv00_0 and bIndexAleft0_Y, 4 pixels per tc0 #define bTc0_v10_0_Y 33 // Derived from bSv10_0 and bIndexAleft0_Y #define bTc0_v20_0_Y 34 // Derived from bSv20_0 and bIndexAleft0_Y #define bTc0_v30_0_Y 35 // Derived from bSv30_0 and bIndexAleft0_Y #define bTc0_v01_Y 36 // Derived from bSv01 and bIndexAinternal_Y #define bTc0_v11_Y 37 // Derived from bSv11 and bIndexAinternal_Y #define bTc0_v21_Y 38 // Derived from bSv21 and bIndexAinternal_Y #define bTc0_v31_Y 39 // Derived from bSv31 and bIndexAinternal_Y #define bTc0_v02_Y 40 // Derived from bSv02 and bIndexAinternal_Y #define bTc0_v12_Y 41 // Derived from bSv12 and bIndexAinternal_Y #define bTc0_v22_Y 42 // Derived from bSv22 and bIndexAinternal_Y #define bTc0_v32_Y 43 // Derived from bSv32 and bIndexAinternal_Y #define bTc0_v03_Y 44 // Derived from bSv03 and bIndexAinternal_Y #define bTc0_v13_Y 45 // Derived from bSv13 and bIndexAinternal_Y #define bTc0_v23_Y 46 // Derived from bSv23 and bIndexAinternal_Y #define bTc0_v33_Y 47 // Derived from bSv33 and bIndexAinternal_Y #define bTc0_h00_0_Y 48 // Derived from bSh00_0 and bIndexAleft0_Y #define bTc0_h01_0_Y 49 // Derived from bSh01_0 and bIndexAleft0_Y #define bTc0_h02_0_Y 50 // Derived from bSh02_0 and bIndexAleft0_Y #define bTc0_h03_0_Y 51 // Derived from bSh03_0 and bIndexAleft0_Y #define bTc0_h10_Y 52 // Derived from bSh10 and bIndexAinternal_Y #define bTc0_h11_Y 53 // Derived from bSh11 and bIndexAinternal_Y #define bTc0_h12_Y 54 // Derived from bSh12 and bIndexAinternal_Y #define bTc0_h13_Y 55 // Derived from bSh13 and bIndexAinternal_Y #define bTc0_h20_Y 56 // Derived from bSh20 and bIndexAinternal_Y #define bTc0_h21_Y 57 // Derived from bSh21 and bIndexAinternal_Y #define bTc0_h22_Y 58 // Derived from bSh22 and bIndexAinternal_Y #define bTc0_h23_Y 59 // Derived from bSh23 and bIndexAinternal_Y #define bTc0_h30_Y 60 // Derived from bSh30 and bIndexAinternal_Y #define bTc0_h31_Y 61 // Derived from bSh31 and bIndexAinternal_Y #define bTc0_h32_Y 62 // Derived from bSh32 and bIndexAinternal_Y #define bTc0_h33_Y 63 // Derived from bSh33 and bIndexAinternal_Y // GRF2, #define bTc0_v00_0_Cb 64 // Derived from bSv00_0 and bIndexAleft0_Cb, 2 pixels per tc0 Left0 #define bTc0_v10_0_Cb 65 // Derived from bSv10_0 and bIndexAleft0_Cb #define bTc0_v20_0_Cb 66 // Derived from bSv20_0 and bIndexAleft0_Cb #define bTc0_v30_0_Cb 67 // Derived from bSv30_0 and bIndexAleft0_Cb #define bTc0_v02_Cb 68 // Derived from bSv02 and bIndexAinternal_Cb MidVert #define bTc0_v12_Cb 69 // Derived from bSv12 and bIndexAinternal_Cb #define bTc0_v22_Cb 70 // Derived from bSv22 and bIndexAinternal_Cb #define bTc0_v32_Cb 71 // Derived from bSv32 and bIndexAinternal_Cb #define bTc0_h00_0_Cb 72 // Derived from bSh00_0 and bIndexAleft0_Cb Top0 #define bTc0_h01_0_Cb 73 // Derived from bSh01_0 and bIndexAleft0_Cb #define bTc0_h02_0_Cb 74 // Derived from bSh02_0 and bIndexAleft0_Cb #define bTc0_h03_0_Cb 75 // Derived from bSh03_0 and bIndexAleft0_Cb #define bTc0_h20_Cb 76 // Derived from bSh20 and bIndexAinternal_Cb MidHorz #define bTc0_h21_Cb 77 // Derived from bSh21 and bIndexAinternal_Cb #define bTc0_h22_Cb 78 // Derived from bSh22 and bIndexAinternal_Cb #define bTc0_h23_Cb 79 // Derived from bSh23 and bIndexAinternal_Cb #define bAlphaLeft0_Cb 80 // Derived from bIndexAleft0_Cb #define bBetaLeft0_Cb 81 // Derived from bIndexBleft0_Cb #define bAlphaTop0_Cb 82 // Derived from bIndexAtop0_Cb #define bBetaTop0_Cb 83 // Derived from bIndexBtop0_Cb #define bAlphaInternal_Cb 84 // Derived from bIndexAinternal_Cb #define bBetaInternal_Cb 85 // Derived from bIndexBinternal_Cb #define ExtBitFlags 86 // Extended bit flags, such as disable ILDB bits // Shared between Cb and Cr #define bTc0_v00_0_Cr bTc0_v00_0_Cb #define bTc0_v10_0_Cr bTc0_v10_0_Cb #define bTc0_v20_0_Cr bTc0_v20_0_Cb #define bTc0_v30_0_Cr bTc0_v30_0_Cb #define bTc0_v02_Cr bTc0_v02_Cb #define bTc0_v12_Cr bTc0_v12_Cb #define bTc0_v22_Cr bTc0_v22_Cb #define bTc0_v32_Cr bTc0_v32_Cb #define bTc0_h00_0_Cr bTc0_h00_0_Cb #define bTc0_h01_0_Cr bTc0_h01_0_Cb #define bTc0_h02_0_Cr bTc0_h02_0_Cb #define bTc0_h03_0_Cr bTc0_h03_0_Cb #define bTc0_h20_Cr bTc0_h20_Cb #define bTc0_h21_Cr bTc0_h21_Cb #define bTc0_h22_Cr bTc0_h22_Cb #define bTc0_h23_Cr bTc0_h23_Cb #define bAlphaLeft0_Cr bAlphaLeft0_Cb #define bBetaLeft0_Cr bBetaLeft0_Cb #define bAlphaTop0_Cr bAlphaTop0_Cb #define bBetaTop0_Cr bBetaTop0_Cb #define bAlphaInternal_Cr bAlphaInternal_Cb #define bBetaInternal_Cr bBetaInternal_Cb #endif //========== End of Child Variables =============================================================== #if !defined(COMBINED_KERNEL) #define ILDB_LABEL(x) x // No symbol extension for standalone kernels #endif #endif // !defined(__AVC_ILDB_HEADER__) intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Child_Field_UV.asm000066400000000000000000000004511231401140700244520ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #include "AVC_ILDB_Child_UV.asm" intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Child_Field_Y.asm000066400000000000000000000004501231401140700243270ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #include "AVC_ILDB_Child_Y.asm" intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Child_Mbaff_UV.asm000066400000000000000000000153651231401140700244540ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////////////////////////////////////////////////////////////////////////////////////////////////////////// // AVC Child Kernel (Vertical and horizontal de-block a 4:2:0 MB UV comp) // // First de-block vertical edges from left to right. // Second de-block horizontal edge from top to bottom. // // For 4:2:0, chroma is always de-blocked at 8x8. // NV12 format allows to filter U and V together. // ////////////////////////////////////////////////////////////////////////////////////////////////////////////// #define AVC_ILDB .kernel AVC_ILDB_CHILD_MBAFF_UV #if defined(COMBINED_KERNEL) ILDB_LABEL(AVC_ILDB_CHILD_UV): #endif #include "SetupVPKernel.asm" #include "AVC_ILDB.inc" #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xE997:w #endif // Setup temp buf used by load and save code #define BUF_B RTempB #define BUF_W RTempW #define BUF_D RTempD // Init local variables mul (4) ORIX_CUR<2>:w ORIX<0;1,0>:w 16:w { NoDDClr } // Expand X addr to bytes, repeat 4 times mul (4) ORIY_CUR<2>:w ORIY<0;1,0>:w 32:w { NoDDChk } // Expand Y addr to bytes, repeat 4 times mov (2) f0.0<1>:w 0:w mov (1) GateWayOffsetC:uw ORIY:uw // Use row # as Gateway offset //=== Null Kernel =============================================================== // jmpi ILDB_LABEL(POST_ILDB_UV) //=============================================================================== //==================================================================================== // Assuming the MB control data is laid out in scan line order in a rectangle with width = 16 bytes. // Control data has dimension of X x Y = 16 x N bytes, where N = W x H / 16 // Each MB has 256 bytes of control data // For CRESTLINE, 256 bytes are stored in memory and fetched into GRF. // MB_offset = MBsCntX * CurRow + CurCol // Byte_offset = MB_offset * (256 << Mbaff_flag), Mbaff_flag = 0 or 1. // Base address of a control data block = (x, y) = (0, y'=y/x), region width is 16 bytes // where y' = Byte_offset / 16 = MB_offset * (16 << Mbaff_flag) // MBCntrlDataOffsetY holds y'. // For BearLake-C, 64 bytes are stored in memory and dataport expands to 256 bytes. Need to use a special read command on BL-C. // MB_offset = MBsCntX * CurRow + CurCol // Byte_offset = MB_offset * (64 << Mbaff_flag), Mbaff_flag = 0 or 1. // MBCntrlDataOffsetY holds globel byte offset. #if !defined(DEV_CL) mul (1) CntrlDataOffsetY:ud MBsCntX:w ORIY:w add (1) CntrlDataOffsetY:ud CntrlDataOffsetY:ud ORIX:w mul (1) CntrlDataOffsetY:ud CntrlDataOffsetY:ud 128:uw #endif //==================================================================================== add (1) ORIX_LEFT:w ORIX_LEFT:w -4:w add (1) ORIY_TOP:w ORIY_TOP:w -4:w //=========== Process Top MB ============ and (1) BitFields:w BitFields:w TopFieldFlag:w // Reset BotFieldFlag // Build a ramp from 0 to 15 mov (16) RRampW(0)<1> RampConstC<0;8,1>:ub add (8) RRampW(0,8)<1> RRampW(0,8) 8:w // RRampW = ramp 15-0 ILDB_LABEL(RE_ENTRY_UV): // for bootom field // Load current MB control data #if defined(DEV_CL) #include "Load_ILDB_Cntrl_Data_64DW.asm" // Crestline #else #include "Load_ILDB_Cntrl_Data_16DW.asm" // Cantiga and beyond #endif // Init addr register for vertical control data mov (1) ECM_AddrReg<1>:w CNTRL_DATA_BASE:w // Init ECM_AddrReg // Use free cycles here // Check loaded control data and.z.f0.1 (16) null<1>:uw r[ECM_AddrReg, wEdgeCntlMap_IntLeftVert]<16;16,1>:uw 0xFFFF:uw // Skip ILDB? and.nz.f0.0 (1) null:w r[ECM_AddrReg, ExtBitFlags]:ub DISABLE_ILDB_FLAG:w // Skip ILDB? // Set DualFieldMode for all data read, write and deblocking and (1) CTemp1_W:uw r[ECM_AddrReg, BitFlags]:ub FieldModeAboveMbFlag+FieldModeCurrentMbFlag:uw // Get Vert Edge Pattern (frame vs. field MBs) and (1) VertEdgePattern:uw r[ECM_AddrReg, BitFlags]:ub FieldModeLeftMbFlag+FieldModeCurrentMbFlag:uw (f0.1.all16h) jmpi ILDB_LABEL(SKIP_ILDB_UV) // Skip ILDB (f0.0) jmpi ILDB_LABEL(SKIP_ILDB_UV) // Skip ILDB // Set DualFieldMode for all data read, write and deblocking // and (1) CTemp1_W:uw r[ECM_AddrReg, BitFlags]:ub FieldModeAboveMbFlag+FieldModeCurrentMbFlag:uw cmp.z.f0.0 (1) null:w CTemp1_W:uw ABOVE_FIELD_CUR_FRAME:w and (1) DualFieldMode:w f0.0:w 0x0001:w #include "load_Cur_UV_8x8T_Mbaff.asm" // Load transposed data 8x8 #include "load_Left_UV_2x8T_Mbaff.asm" // Load left MB (2x8) UV data from memory if exists #include "Transpose_Cur_UV_8x8.asm" #include "Transpose_Left_UV_2x8.asm" //---------- Perform vertical ILDB filting on UV ---------- #include "AVC_ILDB_Filter_Mbaff_UV_v.asm" //--------------------------------------------------------- #include "save_Left_UV_8x2T_Mbaff.asm" // Write left MB (2x8) Y data to memory if exists #include "load_Top_UV_8x2_Mbaff.asm" // Load top MB (8x2) Y data from memory if exists #include "Transpose_Cur_UV_8x8.asm" // Transpose a MB for horizontal edge de-blocking //---------- Perform horizontal ILDB filting on UV ---------- #include "AVC_ILDB_Filter_Mbaff_UV_h.asm" //----------------------------------------------------------- #include "save_Cur_UV_8x8_Mbaff.asm" // Write 8x8 #include "save_Top_UV_8x2_Mbaff.asm" // Write top MB (8x2) if not the top row //----------------------------------------------------------- ILDB_LABEL(SKIP_ILDB_UV): and.z.f0.0 (1) null:w BitFields:w BotFieldFlag:w //=========== Process Bottom MB ============ or (1) BitFields:w BitFields:w BotFieldFlag:w // Set BotFieldFlag to 1 (f0.0) jmpi ILDB_LABEL(RE_ENTRY_UV) // Loop back for bottom deblocking // Fall through to finish //=========== Check write commit of the last write ============ mov (8) WritebackResponse(0)<1> WritebackResponse(0) ILDB_LABEL(POST_ILDB_UV): // Send notification thru Gateway to root thread, update chroma Status[CurRow] #include "AVC_ILDB_ForwardMsg.asm" #if !defined(GW_DCN) // For non-ILK chipsets //child send EOT : Request type = 1 END_CHILD_THREAD #endif // !defined(DEV_ILK) // The thread finishs here //------------------------------------------------------------------------------ //////////////////////////////////////////////////////////////////////////////// // Include other subrutines being called #include "AVC_ILDB_Chroma_Core_Mbaff.asm" #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Child_Mbaff_Y.asm000066400000000000000000000164561231401140700243340ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////////////////////////////////////////////////////////////////////////////////////////////////////////// // AVC Child Kernel (Vertical and horizontal de-block a 4:2:0 MB Y comp) // // First, de-block vertical edges from left to right. // Second, de-block horizontal edge from top to bottom. // // ***** MBAFF Mode ***** // This version deblocks top MB first, followed by bottom MB. // // Need variable CurMB to indicate top MB or bottom MB (CurMB = 0 or 1). // We can use BotFieldFlag in BitFields to represent it. // // Usage: // 1) Access control data for top // CntrlDataOffsetY + CurMB * Control data block size (64 DWs for CL, 16 DWs for BLC) // // 2) Load frame/field video data based on flags: FieldModeCurrentMbFlag, FieldModeLeftMbFlag, FieldModeaboveMbFlag, // // E.g. // if (pCntlData->BitField & FieldModeCurrentMbFlag) // cur_y = ORIX_CUR.y + CurMB * 1; // Add field vertical offset for bot field MB . // else // cur_y = ORIX_CUR.y + CurMB * MB_Rows_Y; // Add bottom MB vertical offset for bot MB // // ////////////////////////////////////////////////////////////////////////////////////////////////////////////// #define AVC_ILDB .kernel AVC_ILDB_CHILD_MBAFF_Y #if defined(COMBINED_KERNEL) ILDB_LABEL(AVC_ILDB_CHILD_Y): #endif #include "SetupVPKernel.asm" #include "AVC_ILDB.inc" #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xE998:w #endif // Setup temp buf used by load and save code #define BUF_B RTempB #define BUF_D RTempD // Init local variables // These coordinates are in progressive fashion mul (4) ORIX_CUR<2>:w ORIX<0;1,0>:w 16:w { NoDDClr } // Expand X addr to bytes, repeat 4 times mul (4) ORIY_CUR<2>:w ORIY<0;1,0>:w 32:w { NoDDChk } // Expand Y addr to bytes, repeat 4 times mov (2) f0.0<1>:w 0:w mov (1) GateWayOffsetC:uw ORIY:uw // Use row # as Gateway offset //=== Null Kernel =============================================================== // jmpi POST_ILDB //=============================================================================== //==================================================================================== // Assuming the MB control data is laid out in scan line order in a rectangle with width = 16 bytes. // Control data has dimension of X x Y = 16 x N bytes, where N = W x H / 16 // Each MB has 256 bytes of control data // For CRESTLINE, 256 bytes are stored in memory and fetched into GRF. // MB_offset = MBsCntX * CurRow + CurCol // Byte_offset = MB_offset * (256 << Mbaff_flag), Mbaff_flag = 0 or 1. // Base address of a control data block = (x, y) = (0, y'=y/x), region width is 16 bytes // where y' = Byte_offset / 16 = MB_offset * (16 << Mbaff_flag) // MBCntrlDataOffsetY holds y'. // For BearLake-C, 64 bytes are stored in memory and dataport expands to 256 bytes. Need to use a special read command on BL-C. // MB_offset = MBsCntX * CurRow + CurCol // Byte_offset = MB_offset * (64 << Mbaff_flag), Mbaff_flag = 0 or 1. // MBCntrlDataOffsetY holds globel byte offset. #if !defined(DEV_CL) mul (1) CntrlDataOffsetY:ud MBsCntX:w ORIY:w add (1) CntrlDataOffsetY:ud CntrlDataOffsetY:ud ORIX:w mul (1) CntrlDataOffsetY:ud CntrlDataOffsetY:ud 128:uw #endif //==================================================================================== add (1) ORIX_LEFT:w ORIX_LEFT:w -4:w add (1) ORIY_TOP:w ORIY_TOP:w -4:w //=========== Process Top MB ============ and (1) BitFields:w BitFields:w TopFieldFlag:w // Reset BotFieldFlag RE_ENTRY: // for bootom field // Load current MB control data #if defined(DEV_CL) #include "Load_ILDB_Cntrl_Data_64DW.asm" // Crestline #else #include "Load_ILDB_Cntrl_Data_16DW.asm" // Cantiga and beyond #endif // Init addr register for vertical control data mov (1) ECM_AddrReg<1>:w CNTRL_DATA_BASE:w // Init edge control map AddrReg // Check loaded control data and.z.f0.1 (16) null<1>:uw r[ECM_AddrReg, wEdgeCntlMap_IntLeftVert]<16;16,1>:uw 0xFFFF:uw // Skip ILDB? and.nz.f0.0 (1) null:w r[ECM_AddrReg, ExtBitFlags]:ub DISABLE_ILDB_FLAG:w // Skip ILDB? // Use free cycles here // Set DualFieldMode for all data read, write and deblocking and (1) CTemp1_W:uw r[ECM_AddrReg, BitFlags]:ub FieldModeAboveMbFlag+FieldModeCurrentMbFlag:uw // Get Vert Edge Pattern (frame vs. field MBs) and (1) VertEdgePattern:uw r[ECM_AddrReg, BitFlags]:ub FieldModeLeftMbFlag+FieldModeCurrentMbFlag:uw (f0.1.all16h) jmpi SKIP_ILDB // Skip ILDB (f0.0) jmpi SKIP_ILDB // Skip ILDB // Set DualFieldMode for all data read, write and deblocking // and (1) CTemp1_W:uw r[ECM_AddrReg, BitFlags]:ub FieldModeAboveMbFlag+FieldModeCurrentMbFlag:uw cmp.z.f0.0 (1) null:w CTemp1_W:uw ABOVE_FIELD_CUR_FRAME:w and (1) DualFieldMode:w f0.0:w 0x0001:w // Load current MB // DDD1 #include "load_Cur_Y_16x16T_Mbaff.asm" // Load cur Y, 16x16, transpose #include "load_Left_Y_4x16T_Mbaff.asm" // Load left MB (4x16) Y data from memory if exists #include "Transpose_Cur_Y_16x16.asm" #include "Transpose_Left_Y_4x16.asm" //---------- Perform vertical ILDB filting on Y---------- #include "AVC_ILDB_Filter_Mbaff_Y_v.asm" //------------------------------------------------------- #include "save_Left_Y_16x4T_Mbaff.asm" // Write left MB (4x16) Y data to memory if exists #include "load_Top_Y_16x4_Mbaff.asm" // Load top MB (16x4) Y data from memory if exists #include "Transpose_Cur_Y_16x16.asm" // Transpose a MB for horizontal edge de-blocking //---------- Perform horizontal ILDB filting on Y ---------- #include "AVC_ILDB_Filter_Mbaff_Y_h.asm" //---------------------------------------------------------- #include "save_Cur_Y_16x16_Mbaff.asm" // Write cur MB (16x16) #include "save_Top_Y_16x4_Mbaff.asm" // Write top MB (16x4) if not the top row SKIP_ILDB: //---------------------------------------------------------- and.z.f0.0 (1) null:w BitFields:w BotFieldFlag:w //=========== Process Bottom MB ============ or (1) BitFields:w BitFields:w BotFieldFlag:w // Set BotFieldFlag to 1 (f0.0) jmpi RE_ENTRY // Loop back for bottom deblocking // Fall through to finish //=========== Check write commit of the last write ============ mov (8) WritebackResponse(0)<1> WritebackResponse(0) POST_ILDB: //--------------------------------------------------------------------------- // Send notification thru Gateway to root thread, update luma Status[CurRow] #include "AVC_ILDB_ForwardMsg.asm" #if !defined(GW_DCN) // For non-ILK chipsets //child send EOT : Request type = 1 END_CHILD_THREAD #endif // !defined(DEV_ILK) // The thread finishs here //------------------------------------------------------------------------------ //////////////////////////////////////////////////////////////////////////////// // Include other subrutines being called #include "AVC_ILDB_Luma_Core_Mbaff.asm" #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Child_UV.asm000066400000000000000000000152601231401140700233530ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////////////////////////////////////////////////////////////////////////////////////////////////////////// // AVC Child Kernel (Vertical and horizontal de-block a 4:2:0 MB UV comp) // // First de-block vertical edges from left to right. // Second de-block horizontal edge from top to bottom. // // For 4:2:0, chroma is always de-blocked at 8x8. // NV12 format allows to filter U and V together. // ////////////////////////////////////////////////////////////////////////////////////////////////////////////// #define AVC_ILDB .kernel AVC_ILDB_CHILD_UV #if defined(COMBINED_KERNEL) ILDB_LABEL(AVC_ILDB_CHILD_UV): #endif #include "SetupVPKernel.asm" #include "AVC_ILDB.inc" #if defined(_DEBUG) mov (1) EntrySignatureC:w 0x9997:w #endif // Init local variables shl (8) ORIX_CUR<1>:w ORIX<0;2,1>:w 4:w // Expand addr to bytes, repeat (x,y) 4 times // Init addr register for vertical control data mov (1) ECM_AddrReg<1>:w CNTRL_DATA_BASE:w // Init ECM_AddrReg //=== Null Kernel =============================================================== // jmpi ILDB_LABEL(POST_ILDB_UV_UV) //=============================================================================== #if defined(DEV_CL) mov (1) acc0.0:w 240:w #else //==================================================================================== // For BearLake-C, 64 bytes are stored in memory and dataport expands to 256 bytes. Need to use a special read command on BL-C. // MB_offset = MBsCntX * CurRow + CurCol // MBCntrlDataOffsetY = globel_byte_offset = MB_offset * 64 mul (1) CntrlDataOffsetY:ud MBsCntX:w ORIY:w add (1) CntrlDataOffsetY:ud CntrlDataOffsetY:ud ORIX:w // Assign to MSGSRC.2:ud for memory access // mul (1) CntrlDataOffsetY:ud CntrlDataOffsetY:ud 64:uw mul (1) MSGSRC.2:ud CntrlDataOffsetY:ud 64:uw mov (1) acc0.0:w 320:w #endif mac (1) URBOffsetC:w ORIY:w 4:w // UV URB entries are right after Y entries // Init local variables // shl (8) ORIX_CUR<1>:w ORIX<0;2,1>:w 4:w // Expand addr to bytes, repeat (x,y) 4 times add (1) ORIX_LEFT:w ORIX_LEFT:w -4:w add (1) ORIY_TOP:w ORIY_TOP:w -4:w // Build a ramp from 0 to 15 mov (16) RRampW(0)<1> RampConstC<0;8,1>:ub add (8) RRampW(0,8)<1> RRampW(0,8) 8:w // RRampW = ramp 15-0 // Load current MB control data #if defined(DEV_CL) #if defined(_APPLE) #include "Load_ILDB_Cntrl_Data_22DW.asm" // Crestline for Apple, progressive only #else #include "Load_ILDB_Cntrl_Data_64DW.asm" // Crestline #endif #else #include "Load_ILDB_Cntrl_Data_16DW.asm" // Cantiga and beyond #endif // Check loaded control data #if defined(_APPLE) and.z.f0.1 (8) null<1>:uw r[ECM_AddrReg, wEdgeCntlMap_IntLeftVert]<8;8,1>:uw 0xFFFF:uw // Skip ILDB? (f0.1) and.z.f0.1 (2) null<1>:uw r[ECM_AddrReg, wEdgeCntlMapA_ExtTopHorz0]<2;2,1>:uw 0xFFFF:uw // Skip ILDB? #else and.z.f0.1 (16) null<1>:uw r[ECM_AddrReg, wEdgeCntlMap_IntLeftVert]<16;16,1>:uw 0xFFFF:uw // Skip ILDB? #endif and.nz.f0.0 (1) null:w r[ECM_AddrReg, ExtBitFlags]:ub DISABLE_ILDB_FLAG:w // Skip ILDB? mov (1) GateWayOffsetC:uw ORIY:uw // Use row # as Gateway offset #if defined(_APPLE) (f0.1.all8h) jmpi ILDB_LABEL(READ_FOR_URB_UV) // Skip ILDB #else (f0.1.all16h) jmpi ILDB_LABEL(READ_FOR_URB_UV) // Skip ILDB #endif (f0.0) jmpi ILDB_LABEL(READ_FOR_URB_UV) // Skip ILDB #include "load_Cur_UV_8x8T.asm" // Load transposed data 8x8 // #include "load_Left_UV_2x8T.asm" #include "load_Top_UV_8x2.asm" // Load top MB (8x2) Y data from memory if exists #include "Transpose_Cur_UV_8x8.asm" // #include "Transpose_Left_UV_2x8.asm" //---------- Perform vertical ILDB filting on UV ---------- #include "AVC_ILDB_Filter_UV_v.asm" //--------------------------------------------------------- #include "save_Left_UV_8x2T.asm" // Write left MB (2x8) Y data to memory if exists #include "Transpose_Cur_UV_8x8.asm" // Transpose a MB for horizontal edge de-blocking //---------- Perform horizontal ILDB filting on UV ---------- #include "AVC_ILDB_Filter_UV_h.asm" //----------------------------------------------------------- #include "save_Cur_UV_8x8.asm" // Write 8x8 #include "save_Top_UV_8x2.asm" // Write top MB (8x2) if not the top row //---------- Write right most 4 columns of cur MB to URB ---------- // Transpose the right most 2 cols 2x8 (word) in GRF to 8x2 in BUF_D. It is 2 left most cols in cur MB. #include "Transpose_Cur_UV_2x8.asm" ILDB_LABEL(WRITE_URB_UV): mov (8) m1<1>:ud LEFT_TEMP_D(1)<8;8,1> // Copy 1 GRF to 1 URB entry (U+V) #include "writeURB_UV_Child.asm" //----------------------------------------------------------------- //=========== Check write commit of the last write ============ mov (8) WritebackResponse(0)<1> WritebackResponse(0) ILDB_LABEL(POST_ILDB_UV): //--------------------------------- // Send notification thru Gateway to root thread, update chroma Status[CurRow] #include "AVC_ILDB_ForwardMsg.asm" #if !defined(GW_DCN) // For non-ILK chipsets //child send EOT : Request type = 1 END_CHILD_THREAD #endif // !defined(DEV_ILK) // The thread finishs here //------------------------------------------------------------------------------ ILDB_LABEL(READ_FOR_URB_UV): // Still need to prepare URB data for the right neighbor MB #include "load_Cur_UV_Right_Most_2x8.asm" // Load cur MB ( right most 4x16) Y data from memory #include "Transpose_Cur_UV_Right_Most_2x8.asm" // jmpi ILDB_LABEL(WRITE_URB_UV) mov (8) m1<1>:ud LEFT_TEMP_D(1)<8;8,1> // Copy 1 GRF to 1 URB entry (U+V) #include "writeURB_UV_Child.asm" //----------------------------------------------------------------- // Send notification thru Gateway to root thread, update chroma Status[CurRow] #include "AVC_ILDB_ForwardMsg.asm" #if !defined(GW_DCN) // For non-ILK chipsets //child send EOT : Request type = 1 END_CHILD_THREAD #endif // !defined(DEV_ILK) // The thread finishs here //------------------------------------------------------------------------------ //////////////////////////////////////////////////////////////////////////////// // Include other subrutines being called // #include "AVC_ILDB_Luma_Core.asm" #include "AVC_ILDB_Chroma_Core.asm" #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Child_Y.asm000066400000000000000000000150741231401140700232340ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////////////////////////////////////////////////////////////////////////////////////////////////////////// // AVC Child Kernel (Vertical and horizontal de-block a 4:2:0 MB Y comp) // // First, de-block vertical edges from left to right. // Second, de-block horizontal edge from top to bottom. // // If transform_size_8x8_flag = 1, luma is de-blocked at 8x8. Otherwise, luma is de-blocked at 4x4. // ////////////////////////////////////////////////////////////////////////////////////////////////////////////// #define AVC_ILDB .kernel AVC_ILDB_CHILD_Y #if defined(COMBINED_KERNEL) ILDB_LABEL(AVC_ILDB_CHILD_Y): #endif #include "SetupVPKernel.asm" #include "AVC_ILDB.inc" #if defined(_DEBUG) mov (1) EntrySignatureC:w 0x9998:w #endif // Init local variables shl (8) ORIX_CUR<1>:w ORIX<0;2,1>:w 4:w // Expand addr to bytes, repeat (x,y) 4 times // Init addr register for vertical control data mov (1) ECM_AddrReg<1>:w CNTRL_DATA_BASE:w // Init edge control map AddrReg //=== Null Kernel =============================================================== // jmpi ILDB_LABEL(POST_ILDB_Y) //=============================================================================== mul (1) URBOffsetC:uw ORIY:uw 4:w #if !defined(DEV_CL) //==================================================================================== // For BearLake-C, 64 bytes are stored in memory and dataport expands to 256 bytes. Need to use a special read command on BL-C. // MB_offset = MBsCntX * CurRow + CurCol // MBCntrlDataOffsetY = globel_byte_offset = MB_offset * 64 mul (1) CntrlDataOffsetY:ud MBsCntX:w ORIY:w add (1) CntrlDataOffsetY:ud CntrlDataOffsetY:ud ORIX:w // Assign to MSGSRC.2:ud for memory access // mul (1) CntrlDataOffsetY:ud CntrlDataOffsetY:ud 64:uw mul (1) MSGSRC.2:ud CntrlDataOffsetY:ud 64:uw #endif // Load current MB control data #if defined(DEV_CL) #if defined(_APPLE) #include "Load_ILDB_Cntrl_Data_22DW.asm" // Crestline for Apple, progressive only #else #include "Load_ILDB_Cntrl_Data_64DW.asm" // Crestline #endif #else #include "Load_ILDB_Cntrl_Data_16DW.asm" // Cantiga and beyond #endif // Check loaded control data #if defined(_APPLE) and.z.f0.1 (8) null<1>:uw r[ECM_AddrReg, wEdgeCntlMap_IntLeftVert]<8;8,1>:uw 0xFFFF:uw // Skip ILDB? (f0.1) and.z.f0.1 (2) null<1>:uw r[ECM_AddrReg, wEdgeCntlMapA_ExtTopHorz0]<2;2,1>:uw 0xFFFF:uw // Skip ILDB? #else and.z.f0.1 (16) null<1>:uw r[ECM_AddrReg, wEdgeCntlMap_IntLeftVert]<16;16,1>:uw 0xFFFF:uw // Skip ILDB? #endif and.nz.f0.0 (1) null:w r[ECM_AddrReg, ExtBitFlags]:ub DISABLE_ILDB_FLAG:w // Skip ILDB? // Use free cycles here add (1) ORIX_LEFT:w ORIX_LEFT:w -4:w // add (1) ORIY_TOP:w ORIY_TOP:w -4:w mov (1) GateWayOffsetC:uw ORIY:uw // Use row # as Gateway offset #if defined(_APPLE) (f0.1.all8h) jmpi ILDB_LABEL(READ_FOR_URB_Y) // Skip ILDB #else (f0.1.all16h) jmpi ILDB_LABEL(READ_FOR_URB_Y) // Skip ILDB #endif (f0.0) jmpi ILDB_LABEL(READ_FOR_URB_Y) // Skip ILDB add (1) ORIY_TOP:w ORIY_TOP:w -4:w // Bettr performance is observed if boundary MBs are not checked and skipped. #include "load_Cur_Y_16x16T.asm" // Load cur MB Y, 16x16, transpose // #include "load_Left_Y_4x16T.asm" // Load left MB (4x16) Y data from memory #include "load_Top_Y_16x4.asm" // Load top MB (16x4) Y data from memory #include "Transpose_Cur_Y_16x16.asm" // #include "Transpose_Left_Y_4x16.asm" //---------- Perform vertical ILDB filting on Y --------- #include "AVC_ILDB_Filter_Y_v.asm" //------------------------------------------------------- #include "save_Left_Y_16x4T.asm" // Write left MB (4x16) Y data to memory #include "Transpose_Cur_Y_16x16.asm" // Transpose a MB for horizontal edge de-blocking //---------- Perform horizontal ILDB filting on Y ------- #include "AVC_ILDB_Filter_Y_h.asm" //------------------------------------------------------- #include "save_Cur_Y_16x16.asm" // Write cur MB (16x16) #include "save_Top_Y_16x4.asm" // Write top MB (16x4) //---------- Write right most 4 columns of cur MB to URB ---------- // Transpose the right most 4 cols 4x16 in GRF to 16x4 in LEFT_TEMP_B. It is 4 left most cols in cur MB. #include "Transpose_Cur_Y_4x16.asm" ILDB_LABEL(WRITE_URB_Y): // Note: LEFT_TEMP_B(2) = TOP_TEMP_B(0), TOP_TEMP_B must be avail mov (16) m1<1>:ud LEFT_TEMP_D(2)<8;8,1> // Copy 2 GRFs to 2 URB entries (Y) #include "writeURB_Y_Child.asm" //----------------------------------------------------------------- //=========== Check write commit of the last write ============ mov (8) WritebackResponse(0)<1> WritebackResponse(0) ILDB_LABEL(POST_ILDB_Y): // Send notification thru Gateway to root thread, update luma Status[CurRow] #include "AVC_ILDB_ForwardMsg.asm" #if !defined(GW_DCN) // For non-ILK chipsets //child send EOT : Request type = 1 END_CHILD_THREAD #endif // !defined(DEV_ILK) // The thread finishs here //------------------------------------------------------------------------------ ILDB_LABEL(READ_FOR_URB_Y): // Still need to prepare URB data for the right neighbor MB #include "load_Cur_Y_Right_Most_4x16.asm" // Load cur MB ( right most 4x16) Y data from memory #include "Transpose_Cur_Y_Right_Most_4x16.asm" // jmpi ILDB_LABEL(WRITE_URB_Y) // Note: LEFT_TEMP_B(2) = TOP_TEMP_B(0), TOP_TEMP_B must be avail mov (16) m1<1>:ud LEFT_TEMP_D(2)<8;8,1> // Copy 2 GRFs to 2 URB entries (Y) #include "writeURB_Y_Child.asm" //----------------------------------------------------------------- // Send notification thru Gateway to root thread, update luma Status[CurRow] #include "AVC_ILDB_ForwardMsg.asm" #if !defined(GW_DCN) // For non-ILK chipsets //child send EOT : Request type = 1 END_CHILD_THREAD #endif // !defined(DEV_ILK) // The thread finishs here //------------------------------------------------------------------------------ //////////////////////////////////////////////////////////////////////////////// // Include other subrutines being called #include "AVC_ILDB_Luma_Core.asm" // #include "AVC_ILDB_Chroma_Core.asm" #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Chroma_Core.asm000066400000000000000000000126731231401140700241040ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__AVC_ILDB_CHROMA_CORE__) // Make sure this file is only included once #define __AVC_ILDB_CHROMA_CORE__ ////////// AVC ILDB Chroma Core ///////////////////////////////////////////////////////////////////////////////// // // This core performs AVC U or V ILDB filtering on one horizontal edge (8 pixels) of a MB. // If data is transposed, it can also de-block a vertical edge. // // Bafore calling this subroutine, caller needs to set the following parameters. // // - EdgeCntlMap1 // Edge control map A // - EdgeCntlMap2 // Edge control map B // - P_AddrReg // Src and dest address register for P pixels // - Q_AddrReg // Src and dest address register for Q pixels // - alpha // alpha corresponding to the edge to be filtered // - beta // beta corresponding to the edge to be filtered // - tc0 // tc0 corresponding to the edge to be filtered // // U or V: // +----+----+----+----+ // | P1 | p0 | q0 | q1 | // +----+----+----+----+ // // p1 = r[P_AddrReg, 0]<16;8,2> // p0 = r[P_AddrReg, 16]<16;8,2> // q0 = r[Q_AddrReg, 0]<16;8,2> // q1 = r[Q_AddrReg, 16]<16;8,2> // ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // The region is both src and dest // P0-P3 and Q0-Q3 should be only used if they have not been modified to new values #undef P1 #undef P0 #undef Q0 #undef Q1 #define P1 r[P_AddrReg, 0]<16;8,2>:ub #define P0 r[P_AddrReg, 16]<16;8,2>:ub #define Q0 r[Q_AddrReg, 0]<16;8,2>:ub #define Q1 r[Q_AddrReg, 16]<16;8,2>:ub // New region as dest #undef NewP0 #undef NewQ0 #define NewP0 r[P_AddrReg, 16]<2>:ub #define NewQ0 r[Q_AddrReg, 0]<2>:ub // Filter one chroma edge FILTER_UV: #if defined(_DEBUG) mov (1) EntrySignatureC:w 0x1112:w #endif //---------- Derive filterSampleflag in AVC spec, equition (8-469) ---------- // bS is in MaskA // Src copy of the p1, p0, q0, q1 // mov (8) p1(0)<1> r[P_AddrReg, 0]<16;8,2>:ub // mov (8) p0(0)<1> r[P_AddrReg, 16]<16;8,2>:ub // mov (8) q0(0)<1> r[Q_AddrReg, 0]<16;8,2>:ub // mov (8) q1(0)<1> r[Q_AddrReg, 16]<16;8,2>:ub // mov (1) f0.0:uw MaskA:uw add (8) q0_p0(0)<1> Q0 -P0 // q0-p0 add (8) TempRow0(0)<1> P1 -P0 // p1-p0 add (8) TempRow1(0)<1> Q1 -Q0 // q1-q0 // Build FilterSampleFlag // abs(q0-p0) < alpha (f0.0) cmp.l.f0.0 (16) null:w (abs)q0_p0(0) alpha:w // abs(p1-p0) < Beta (f0.0) cmp.l.f0.0 (16) null:w (abs)TempRow0(0) beta:w // abs(q1-q0) < Beta (f0.0) cmp.l.f0.0 (16) null:w (abs)TempRow1(0) beta:w //----------------------------------------------------------------------------------------- // if (f0.0) if (8) UV_ENDIF1 // For channels whose edge control map1 = 1 ---> perform de-blocking // mov (1) f0.1:w MaskB:w {NoMask} // Now check for which algorithm to apply (f0.1) if (8) UV_ELSE2 // For channels whose edge control map2 = 1 ---> bS = 4 algorithm // p0' = (2*p1 + p0 + q1 + 2) >> 2 // q0' = (2*q1 + q0 + p1 + 2) >> 2 // Optimized version: // A = (p1 + q1 + 2) // p0' = (p0 + p1 + A) >> 2 // q0' = (q0 + q1 + A) >> 2 //------------------------------------------------------------------------------------ // p0' = (2*p1 + p0 + q1 + 2) >> 2 add (8) acc0<1>:w Q1 2:w mac (8) acc0<1>:w P1 2:w add (8) acc0<1>:w acc0<8;8,1>:w P0 shr.sat (8) TempRow0B(0)<2> acc0<8;8,1>:w 2:w // q0' = (2*q1 + q0 + p1 + 2) >> 2 add (8) acc0<1>:w P1 2:w mac (8) acc0<1>:w Q1 2:w add (8) acc0<1>:w acc0<8;8,1>:w Q0 shr.sat (8) TempRow1B(0)<2> acc0<8;8,1>:w 2:w mov (8) NewP0 TempRow0B(0) // p0' mov (8) NewQ0 TempRow1B(0) // q0' UV_ELSE2: else (8) UV_ENDIF2 // For channels whose edge control map2 = 0 ---> bS < 4 algorithm // Expand tc0 (tc0 has 4 bytes) // mov (8) tc0_exp(0)<1> tc0<1;2,0>:ub {NoMask} // tc0_exp = tc0, each tc0 is duplicated 2 times for 2 adjcent pixels mov (8) acc0<1>:w tc0<1;2,0>:ub {NoMask} // tc0_exp = tc0, each tc0 is duplicated 2 times for 2 adjcent pixels // tc_exp = tc0_exp + 1 // add (8) tc_exp(0)<1> tc0_exp(0) 1:w add (8) tc_exp(0)<1> acc0<8;8,1>:w 1:w // delta = Clip3(-tc, tc, ((((q0 - p0)<<2) + (p1-q1) + 4) >> 3)) // 4 * (q0-p0) + p1 - q1 + 4 add (8) acc0<1>:w P1 4:w mac (8) acc0<1>:w q0_p0(0) 4:w add (8) acc0<1>:w acc0<8;8,1>:w -Q1 shr (8) TempRow0(0)<1> acc0<8;8,1>:w 3:w // tc clip cmp.g.f0.0 (8) null:w TempRow0(0) tc_exp(0) // Clip if > tc0 cmp.l.f0.1 (8) null:w TempRow0(0) -tc_exp(0) // Clip if < -tc0 (f0.0) mov (8) TempRow0(0)<1> tc_exp(0) (f0.1) mov (8) TempRow0(0)<1> -tc_exp(0) // p0' = Clip1(p0 + delta) = Clip3(0, 0xFF, p0 + delta) add.sat (8) TempRow1B(0)<2> P0 TempRow0(0) // p0+delta // q0' = Clip1(q0 - delta) = Clip3(0, 0xFF, q0 - delta) add.sat (8) TempRow0B(0)<2> Q0 -TempRow0(0) // q0-delta mov (8) NewP0 TempRow1B(0) // p0' mov (8) NewQ0 TempRow0B(0) // q0' endif UV_ENDIF2: UV_ENDIF1: endif RETURN #endif // !defined(__AVC_ILDB_CHROMA_CORE__) intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Chroma_Core_Mbaff.asm000066400000000000000000000113331231401140700251670ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////// AVC ILDB Chroma Core Mbaff ///////////////////////////////////////////////////////////////////////////////// // // This core performs AVC U or V ILDB filtering on one horizontal edge (8 pixels) of a MB. // If data is transposed, it can also de-block a vertical edge. // // Bafore calling this subroutine, caller needs to set the following parameters. // // - EdgeCntlMap1 // Edge control map A // - EdgeCntlMap2 // Edge control map B // - P_AddrReg // Src and dest address register for P pixels // - Q_AddrReg // Src and dest address register for Q pixels // - alpha // alpha corresponding to the edge to be filtered // - beta // beta corresponding to the edge to be filtered // - tc0 // tc0 corresponding to the edge to be filtered // // U or V: // +----+----+----+----+ // | P1 | p0 | q0 | q1 | // +----+----+----+----+ // // p1 = r[P_AddrReg, 0]<16;8,2> // p0 = r[P_AddrReg, 16]<16;8,2> // q0 = r[Q_AddrReg, 0]<16;8,2> // q1 = r[Q_AddrReg, 16]<16;8,2> // ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // The region is both src and dest // P0-P3 and Q0-Q3 should be only used if they have not been modified to new values #undef P1 #undef P0 #undef Q0 #undef Q1 #define P1 r[P_AddrReg, 0]<16;8,2>:ub #define P0 r[P_AddrReg, 16]<16;8,2>:ub #define Q0 r[Q_AddrReg, 0]<16;8,2>:ub #define Q1 r[Q_AddrReg, 16]<16;8,2>:ub // New region as dest #undef NewP0 #undef NewQ0 #define NewP0 r[P_AddrReg, 16]<2>:ub #define NewQ0 r[Q_AddrReg, 0]<2>:ub // Filter one chroma edge - mbaff FILTER_UV_MBAFF: #if defined(_DEBUG) mov (1) EntrySignatureC:w 0x1112:w #endif //---------- Derive filterSampleflag in AVC spec, equition (8-469) ---------- //===== Assume f0.0 contains MaskA when entering this routine // mov (1) f0.0:uw MaskA:uw add (8) q0_p0(0)<1> Q0 -P0 // q0-p0 add (8) TempRow0(0)<1> P1 -P0 // p1-p0 add (8) TempRow1(0)<1> Q1 -Q0 // q1-q0 // Build FilterSampleFlag // abs(q0-p0) < alpha (f0.0) cmp.l.f0.0 (16) null:w (abs)q0_p0(0) Mbaff_ALPHA(0) // abs(p1-p0) < Beta (f0.0) cmp.l.f0.0 (16) null:w (abs)TempRow0(0) Mbaff_BETA(0) // abs(q1-q0) < Beta (f0.0) cmp.l.f0.0 (16) null:w (abs)TempRow1(0) Mbaff_BETA(0) //----------------------------------------------------------------------------------------- // if (f0.0) if (8) MBAFF_UV_ENDIF1 // For channels whose edge control map1 = 1 ---> perform de-blocking // mov (1) f0.1:w MaskB:w {NoMask} // Now check for which algorithm to apply (f0.1) if (8) MBAFF_UV_ELSE2 // For channels whose edge control map2 = 1 ---> bS = 4 algorithm // p0' = (2*p1 + P0 + q1 + 2) >> 2 // q0' = (2*q1 + q0 + p1 + 2) >> 2 //------------------------------------------------------------------------------------ // p0' = (2*p1 + p0 + q1 + 2) >> 2 add (8) acc0<1>:w Q1 2:w mac (8) acc0<1>:w P1 2:w add (8) acc0<1>:w acc0<8;8,1>:w P0 shr.sat (8) TempRow0B(0)<2> acc0<8;8,1>:w 2:w // q0' = (2*q1 + q0 + p1 + 2) >> 2 add (8) acc0<1>:w P1 2:w mac (8) acc0<1>:w Q1 2:w add (8) acc0<1>:w acc0<8;8,1>:w Q0 shr.sat (8) TempRow1B(0)<2> acc0<8;8,1>:w 2:w mov (8) NewP0 TempRow0B(0) // p0' mov (8) NewQ0 TempRow1B(0) // q0' MBAFF_UV_ELSE2: else (8) MBAFF_UV_ENDIF2 // For channels whose edge control map2 = 0 ---> bS < 4 algorithm // tc_exp = tc0_exp + 1 add (8) tc_exp(0)<1> Mbaff_TC0(0) 1:w // delta = Clip3(-tc, tc, ((((q0 - p0)<<2) + (p1-q1) + 4) >> 3)) // 4 * (q0-p0) + p1 - q1 + 4 add (8) acc0<1>:w P1 4:w mac (8) acc0<1>:w q0_p0(0) 4:w add (8) acc0<1>:w acc0<8;8,1>:w -Q1 shr (8) TempRow0(0)<1> acc0<8;8,1>:w 3:w // tc clip cmp.g.f0.0 (8) null:w TempRow0(0) tc_exp(0) // Clip if > tc0 cmp.l.f0.1 (8) null:w TempRow0(0) -tc_exp(0) // Clip if < -tc0 (f0.0) mov (8) TempRow0(0)<1> tc_exp(0) (f0.1) mov (8) TempRow0(0)<1> -tc_exp(0) // p0' = Clip1(p0 + delta) = Clip3(0, 0xFF, p0 + delta) add.sat (8) TempRow1B(0)<2> P0 TempRow0(0) // p0+delta // q0' = Clip1(q0 - delta) = Clip3(0, 0xFF, q0 - delta) add.sat (8) TempRow0B(0)<2> Q0 -TempRow0(0) // q0-delta mov (8) NewP0 TempRow1B(0) // p0' mov (8) NewQ0 TempRow0B(0) // q0' endif MBAFF_UV_ENDIF2: MBAFF_UV_ENDIF1: endif RETURN intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_CloseGateway.asm000066400000000000000000000013251231401140700243020ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //----- Close a Message Gateway ----- #if defined(_DEBUG) mov (1) EntrySignature:b 0x4444:w #endif // Message descriptor // bit 31 EOD // 27:24 FFID = 0x0011 for msg gateway // 23:20 msg length = 1 MRF // 19:16 Response length = 0 // 1:0 SubFuncID = 01 for CloseGateway // Message descriptor: 0 000 0011 0001 0000 + 0 0 000000000000 01 ==> 0000 0011 0001 0000 0000 0000 0000 0001 send (8) null:ud m7 r0.0<0;1,0>:ud MSG_GW CGWMSGDSC intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Dep_Check.asm000066400000000000000000000162701231401140700235250ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- Check dependency and spawn all MBs ---------- // Launch the 1st round of child threads for Vertical ILDB #if defined(_DEBUG) mov (1) EntrySignature:w 0x3333:w #endif //===================================================================== // Jump Table 1 // 0 0 ---> Goto ALL_SPAWNED // 0 1 ---> Goto ALL_SPAWNED // 1 0 ---> Goto SLEEP_ENTRY // 1 1 ---> Goto POST_SLEEP mov (2) JumpTable.0<1>:d 0:d { NoDDClr } #if defined(CHROMA_ROOT) mov (1) JumpTable.2:d SLEEP_ENTRY_UV_ILDB_FRAME_IP-ALL_SPAWNED_UV_ILDB_FRAME_IP:d { NoDDClr, NoDDChk } mov (1) JumpTable.3:d POST_SLEEP_UV_ILDB_FRAME_IP-ALL_SPAWNED_UV_ILDB_FRAME_IP:d { NoDDChk } #else mov (1) JumpTable.2:d SLEEP_ENTRY_Y_ILDB_FRAME_IP-ALL_SPAWNED_Y_ILDB_FRAME_IP:d { NoDDClr, NoDDChk } mov (1) JumpTable.3:d POST_SLEEP_Y_ILDB_FRAME_IP-ALL_SPAWNED_Y_ILDB_FRAME_IP:d { NoDDChk } #endif //===================================================================== mov (2) f0.0<1>:w 0:w // Get m0 most of fields ready for URB write mov (8) MRF0<1>:ud MSGSRC.0<8;8,1>:ud // Add child kernel offset add (1) CT_R0Hdr.2:ud r0.2:ud CHILD_OFFSET:w // Init mov (1) Col_Boundary:w 2:w mov (1) Row_Boundary:w LastRow:w mov (1) TopRowForScan:w 0:w mov (2) OutstandingThreads<1>:w 0:w // Init Scoreboard (idle = 0x00FF, busy = 0x0000) // Low word is saved col. High word is busy/idle status mov (16) GatewayAperture(0)<1> 0x00FF00FF:ud // Init r6-r7 mov (16) GatewayAperture(2)<1> 0x00FF00FF:ud // Init r8-r9 mov (16) GatewayAperture(4)<1> 0x00FF00FF:ud // Init r10-r11 mov (16) GatewayAperture(6)<1> 0x00FF00FF:ud // Init r12-r13 mov (16) GatewayAperture(8)<1> 0x00FF00FF:ud // Init r14-r15 mul (1) StatusAddr:w CurRow:w 4:w // dword to bytes offset conversion //===================================================================== //SPAWN_LOOP: //===== OutstandingThreads < ThreadLimit ? ============================ cmp.l.f0.1 (1) null:w OutstandingThreads:w ThreadLimit:w // Check the thread limit #if defined(CHROMA_ROOT) (f0.1) jmpi ILDB_LABEL(POST_SLEEP_UV) #else // LUMA_ROOT (f0.1) jmpi ILDB_LABEL(POST_SLEEP_Y) #endif #if defined(CHROMA_ROOT) ILDB_LABEL(SLEEP_ENTRY_UV): #else // LUMA_ROOT ILDB_LABEL(SLEEP_ENTRY_Y): #endif //===== Goto Sleep ==================================================== // Either reached max thread limit or no child thread can be spawned due to dependency. add (1) OutstandingThreads:w OutstandingThreads:w -1:w // Do this before wait is faster wait n0.0:d #if defined(CHROMA_ROOT) ILDB_LABEL(POST_SLEEP_UV): #else // LUMA_ROOT ILDB_LABEL(POST_SLEEP_Y): #endif //===== Luma Status[CurRow] == busy ? ===== cmp.z.f0.0 (1) null:uw r[StatusAddr, GatewayApertureB+ScoreBd_Idx]:uw 0:uw // Check west neighbor cmp.g.f0.1 (1) null:w CurCol:w LastCol:w // Check if the curCol > LastCol #if defined(CHROMA_ROOT) mov (16) acc0.0<1>:w URBOffsetUVBase<0;1,0>:w // Add offset to UV base (MBsCntY * URB_EBTRIES_PER_MB) mac (1) URBOffset:w CurRow:w 4:w // 4 entries per row #else mul (1) URBOffset:w CurRow:w 4:w // 4 entries per row #endif #if defined(CHROMA_ROOT) (f0.0) jmpi ILDB_LABEL(SLEEP_ENTRY_UV) // Current row has a child thread running, can not spawn a new child thread, go back to sleep (f0.1) jmpi ILDB_LABEL(NEXT_MB_UV) // skip MB if the curCol > LastCol #else // LUMA_ROOT (f0.0) jmpi ILDB_LABEL(SLEEP_ENTRY_Y) // Current row has a child thread running, can not spawn a new child thread, go back to sleep (f0.1) jmpi ILDB_LABEL(NEXT_MB_Y) // skip MB if the curCol > LastCol #endif //========== Spwan a child thread ======================================== // Save cur col and set Status[CurRow] to busy mov (2) r[StatusAddr, GatewayApertureB]<1>:uw CurColB<2;2,1>:ub // Store the new col // Increase OutstandingThreads and ProcessedMBs by 1 add (2) OutstandingThreads<1>:w OutstandingThreads<2;2,1>:w 1:w #include "AVC_ILDB_SpawnChild.asm" //===== Find next MB =================================================== #if defined(CHROMA_ROOT) ILDB_LABEL(NEXT_MB_UV): #else // LUMA_ROOT ILDB_LABEL(NEXT_MB_Y): #endif // Check pic boundary, results are in f0.0 bit0 and bit1 cmp.ge.f0.0 (2) null<1>:w CurCol<2;2,1>:w Col_Boundary<2;2,1>:w // Update TopRowForScan if the curCol = LastCol (f0.1) add (1) TopRowForScan:w CurRow:w 1:w // cmp.l.f0.1 (1) null<1>:w ProcessedMBs:w TotalBlocks:w // Processed all blocks ? // 2 sets compare // ProcessedMBs:w < TotalBlocks:w OutstandingThreads:w < ThreadLimit:wProcessedMBs:w // 0 0 ---> Goto ALL_SPAWNED // 0 1 ---> Goto ALL_SPAWNED // 1 0 ---> Goto SLEEP_ENTRY // 1 1 ---> Goto POST_SLEEP cmp.l.f0.1 (2) null<1>:w OutstandingThreads<2;2,1>:w ThreadLimit<2;2,1>:w // Just do it in stalled cycles mov (1) acc0.0:w 4:w mac (1) StatusAddr:w CurRow:w 4:w // dword to bytes offset conversion add (2) CurCol<1>:w CurCol<2;2,1>:w StepToNextMB<2;2,1>:b // CurCol -= 2 and CurRow += 1 // Set f0.0 if turning around is needed, assuming bit 15 - 2 are zeros for correct comparison. cmp.nz.f0.0 (1) null<1>:w f0.0:w 0x01:w mul (1) JumpAddr:w f0.1:w 4:w // byte offet in dword count // The next MB is at the row TopRowForScan (f0.0) mul (1) StatusAddr:w TopRowForScan:w 4:w // dword to bytes offset conversion (f0.0) mov (1) CurRow:w TopRowForScan:w { NoDDClr } // Restart from the top row that has MBs not deblocked yet. (f0.0) add (1) CurCol:w r[StatusAddr, GatewayApertureB]:uw 1:w { NoDDChk } //===== Processed all blocks ? ========================================= // (f0.1) jmpi SPAWN_LOOP jmpi r[JumpAddr, JUMPTABLE_BASE]:d //JUMP_BASE: //====================================================================== // All MB are spawned at this point, check for outstanding thread count #if defined(CHROMA_ROOT) ILDB_LABEL(ALL_SPAWNED_UV): #else // LUMA_ROOT ILDB_LABEL(ALL_SPAWNED_Y): #endif cmp.e.f0.1 (1) null:w OutstandingThreads:w 0:w // Check before goto sleep #if defined(CHROMA_ROOT) (f0.1) jmpi ILDB_LABEL(ALL_DONE_UV) #else // LUMA_ROOT (f0.1) jmpi ILDB_LABEL(ALL_DONE_Y) #endif wait n0.0:d // Wake up by a finished child thread add (1) OutstandingThreads:w OutstandingThreads:w -1:w #if defined(CHROMA_ROOT) // One thread is free and give it to luma thread limit --- Increase luma thread limit by one. #include "AVC_ILDB_LumaThrdLimit.asm" #endif #if defined(CHROMA_ROOT) jmpi ILDB_LABEL(ALL_SPAWNED_UV) // Waked up and goto dependency check #else // LUMA_ROOT jmpi ILDB_LABEL(ALL_SPAWNED_Y) // Waked up and goto dependency check #endif // All child threads are finsihed at this point #if defined(CHROMA_ROOT) ILDB_LABEL(ALL_DONE_UV): #else // LUMA_ROOT ILDB_LABEL(ALL_DONE_Y): #endif intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Filter_Mbaff_UV_h.asm000066400000000000000000000170161231401140700251600ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////// AVC ILDB filter horizontal Mbaff UV /////////////////////////////////////////////////////// // // This filter code prepares the src data and control data for ILDB filtering on all horizontal edges of UV. // // It sssumes the data for horizontal de-blocking is already transposed. // // Chroma: // // +-------+-------+ H0 Edge // | | | // | | | // | | | // +-------+-------+ H1 Edge // | | | // | | | // | | | // +-------+-------+ // ///////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xBBBC:w #endif //=============== Chroma deblocking ================ //---------- Deblock UV external top edge ---------- and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterTopMbEdgeFlag:w // Check for FilterTopMbEdgeFlag mov (1) f0.1:w DualFieldMode:w // Check for dual field mode // Get Luma maskA and maskB shr (16) TempRow0(0)<1> r[ECM_AddrReg, wEdgeCntlMapA_ExtTopHorz0]<0;1,0>:uw RRampW(0) shr (16) TempRow1(0)<1> r[ECM_AddrReg, wEdgeCntlMapB_ExtTopHorz0]<0;1,0>:uw RRampW(0) (f0.0) jmpi H0_UV_DONE // Skip H0 UV edge (f0.1) jmpi DUAL_FIELD_UV // Non dual field mode // Extract UV MaskA and MaskB from every other bit of Y masks and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w and.nz.f0.1 (8) null:w TempRow1(0)<16;8,2> 1:w // Ext U // p1 = Prev MB U row 0 // p0 = Prev MB U row 1 // q0 = Cur MB U row 0 // q1 = Cur MB U row 1 mov (1) P_AddrReg:w PREV_MB_U_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_U_BASE:w { NoDDChk } mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaTop0_Cb]<0;1,0>:ub mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaTop0_Cb]<0;1,0>:ub mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h00_0_Cb]<1;2,0>:ub // Store UV MaskA and MaskB mov (2) MaskA<1>:uw f0.0<2;2,1>:uw CALL(FILTER_UV_MBAFF, 1) // Ext V mov (1) P_AddrReg:w PREV_MB_V_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_V_BASE:w { NoDDChk } mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaTop0_Cr]<0;1,0>:ub mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaTop0_Cr]<0;1,0>:ub mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h00_0_Cr]<1;2,0>:ub // Set UV MaskA and MaskB mov (2) f0.0<1>:uw MaskA<2;2,1>:uw CALL(FILTER_UV_MBAFF, 1) jmpi H0_UV_DONE DUAL_FIELD_UV: // Dual field mode, FieldModeCurrentMbFlag=0 && FieldModeAboveMbFlag=1 //===== Ext U, Top field // Extract UV MaskA and MaskB from every other bit of Y masks and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w and.nz.f0.1 (8) null:w TempRow1(0)<16;8,2> 1:w mov (1) P_AddrReg:w ABOVE_CUR_MB_BASE:w { NoDDClr } mov (1) Q_AddrReg:w ABOVE_CUR_MB_BASE+32:w { NoDDChk } mov (16) ABOVE_CUR_MB_UW(0)<1> PREV_MB_UW(0, 0)<16;8,1> // Copy p1, p0 mov (16) ABOVE_CUR_MB_UW(1)<1> SRC_UW(0, 0)<16;8,1> // Copy q1, q0 //===== Ext U, top field mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaTop0_Cb]<0;1,0>:ub mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaTop0_Cb]<0;1,0>:ub mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h00_0_Cb]<1;2,0>:ub // Store UV MaskA and MaskB mov (2) MaskA<1>:uw f0.0<2;2,1>:uw CALL(FILTER_UV_MBAFF, 1) // Ext U, top field //===== Ext V, top field mov (1) P_AddrReg:w ABOVE_CUR_MB_BASE+1:w { NoDDClr } mov (1) Q_AddrReg:w ABOVE_CUR_MB_BASE+33:w { NoDDChk } mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaTop0_Cr]<0;1,0>:ub mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaTop0_Cr]<0;1,0>:ub mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h00_0_Cr]<1;2,0>:ub // Set UV MaskA and MaskB mov (2) f0.0<1>:uw MaskA<2;2,1>:uw CALL(FILTER_UV_MBAFF, 1) // Ext U, top field // Prefetch for bottom field // Get bot field Luma maskA and maskB shr (16) TempRow0(0)<1> r[ECM_AddrReg, wEdgeCntlMapA_ExtTopHorz1]<0;1,0>:uw RRampW(0) shr (16) TempRow1(0)<1> r[ECM_AddrReg, wEdgeCntlMapB_ExtTopHorz1]<0;1,0>:uw RRampW(0) // Save deblocked top field rows mov (8) PREV_MB_UW(1, 0)<1> ABOVE_CUR_MB_UW(0, 8) // Copy p0 mov (8) SRC_UW(0, 0)<1> ABOVE_CUR_MB_UW(1, 0) // Copy q0 //========================================================================== //===== Ext U, Bot field // Extract UV MaskA and MaskB from every other bit of Y masks and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w and.nz.f0.1 (8) null:w TempRow1(0)<16;8,2> 1:w mov (1) P_AddrReg:w ABOVE_CUR_MB_BASE:w { NoDDClr } mov (1) Q_AddrReg:w ABOVE_CUR_MB_BASE+32:w { NoDDChk } mov (16) ABOVE_CUR_MB_UW(0)<1> PREV_MB_UW(0, 8)<16;8,1> // Copy p1, p0 mov (16) ABOVE_CUR_MB_UW(1)<1> SRC_UW(0, 8)<16;8,1> // Copy q1, q0 //===== Ext U, bottom field mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaTop1_Cb]<0;1,0>:ub mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaTop1_Cb]<0;1,0>:ub mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h00_1_Cb]<1;2,0>:ub // Store UV MaskA and MaskB mov (2) MaskA<1>:uw f0.0<2;2,1>:uw CALL(FILTER_UV_MBAFF, 1) // Ext U, bottom field //===== Ext V, bot field mov (1) P_AddrReg:w ABOVE_CUR_MB_BASE+1:w { NoDDClr } mov (1) Q_AddrReg:w ABOVE_CUR_MB_BASE+33:w { NoDDChk } mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaTop1_Cr]<0;1,0>:ub mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaTop1_Cr]<0;1,0>:ub mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h00_1_Cr]<1;2,0>:ub // Set UV MaskA and MaskB mov (2) f0.0<1>:uw MaskA<2;2,1>:uw CALL(FILTER_UV_MBAFF, 1) // Ext V, bottom field // Save deblocked bot field rows mov (8) PREV_MB_UW(1, 8)<1> ABOVE_CUR_MB_UW(0, 8) // Copy p0 mov (8) SRC_UW(0, 8)<1> ABOVE_CUR_MB_UW(1, 0) // Copy q0 //======================================== H0_UV_DONE: //---------- Deblock U internal horz middle edge ---------- //***** Need to take every other bit to form U maskA in core shr (16) TempRow0(0)<1> r[ECM_AddrReg, wEdgeCntlMap_IntMidHorz]<0;1,0>:uw RRampW(0) // p1 = Cur MB U row 2 // p0 = Cur MB U row 3 // q0 = Cur MB U row 4 // q1 = Cur MB U row 5 mov (1) P_AddrReg:w 4*UV_ROW_WIDTH+SRC_MB_U_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 8*UV_ROW_WIDTH+SRC_MB_U_BASE:w { NoDDChk } mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaInternal_Cb]<0;1,0>:ub mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaInternal_Cb]<0;1,0>:ub mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h20_Cb]<1;2,0>:ub and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w // Store UV MaskA and MaskB mov (1) f0.1:uw 0:w mov (1) MaskB:uw 0:w { NoDDClr } mov (1) MaskA:uw f0.0:uw { NoDDChk } CALL(FILTER_UV_MBAFF, 1) //----------------------------------------------- //---------- Deblock V internal horz middle edge ---------- // p1 = Cur MB V row 2 // p0 = Cur MB V row 3 // q0 = Cur MB V row 4 // q1 = Cur MB V row 5 mov (1) P_AddrReg:w 4*UV_ROW_WIDTH+SRC_MB_V_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 8*UV_ROW_WIDTH+SRC_MB_V_BASE:w { NoDDChk } mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaInternal_Cr]<0;1,0>:ub mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaInternal_Cr]<0;1,0>:ub mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h20_Cr]<1;2,0>:ub // Set UV MaskA and MaskB mov (2) f0.0<1>:uw MaskA<2;2,1>:uw CALL(FILTER_UV_MBAFF, 1) //----------------------------------------------- intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Filter_Mbaff_UV_v.asm000066400000000000000000000174431231401140700252020ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////// AVC LDB filter vertical Mbaff UV /////////////////////////////////////////////////////// // // This filter code prepares the src data and control data for ILDB filtering on all vertical edges of UV. // // It sssumes the data for vertical de-blocking is already transposed. // // Chroma: // // +-------+-------+ // | | | // | | | // | | | // +-------+-------+ // | | | // | | | // | | | // +-------+-------+ // // V0 V1 // Edge Edge // ///////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xBBBC:w #endif //=============== Chroma deblocking ================ //---------- Deblock U external left edge ---------- and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterLeftMbEdgeFlag:w // Check for FilterLeftMbEdgeFlag cmp.z.f0.1 (1) null:w VertEdgePattern:uw LEFT_FIELD_CUR_FRAME:w // Get Luma maskA and maskB shr (16) TempRow0(0)<1> r[ECM_AddrReg, wEdgeCntlMapA_ExtLeftVert0]<0;1,0>:uw RRampW(0) shr (16) TempRow1(0)<1> r[ECM_AddrReg, wEdgeCntlMapB_ExtLeftVert0]<0;1,0>:uw RRampW(0) (f0.0) jmpi BYPASS_V0_UV // Do not deblock Left ext edge cmp.z.f0.0 (1) null:w VertEdgePattern:uw LEFT_FRAME_CUR_FIELD:w (-f0.1) jmpi V0_U_NEXT1 // Jump if not LEFT_FIELD_CUR_FRAME //----- For LEFT_FIELD_CUR_FRAME // Extract UV MaskA and MaskB from every other 2 bits of Y masks and.nz.f0.0 (8) null:w TempRow0(0)<4;2,1> 1:w and.nz.f0.1 (8) null:w TempRow1(0)<4;2,1> 1:w // For FieldModeLeftMbFlag=1 && FieldModeCurrentMbFlag=0 mov (4) Mbaff_ALPHA(0,0)<2> r[ECM_AddrReg, bAlphaLeft0_Cb]<0;1,0>:ub { NoDDClr } mov (4) Mbaff_ALPHA(0,1)<2> r[ECM_AddrReg, bAlphaLeft1_Cb]<0;1,0>:ub { NoDDChk } mov (4) Mbaff_BETA(0,0)<2> r[ECM_AddrReg, bBetaLeft0_Cb]<0;1,0>:ub { NoDDClr } mov (4) Mbaff_BETA(0,1)<2> r[ECM_AddrReg, bBetaLeft1_Cb]<0;1,0>:ub { NoDDChk } mov (4) Mbaff_TC0(0,0)<2> r[ECM_AddrReg, bTc0_v00_0_Cb]<4;4,1>:ub { NoDDClr } mov (4) Mbaff_TC0(0,1)<2> r[ECM_AddrReg, bTc0_v00_1_Cb]<4;4,1>:ub { NoDDChk } jmpi V0_U_NEXT3 V0_U_NEXT1: (-f0.0) jmpi V0_U_NEXT2 // Jump if not LEFT_FRAME_CUR_FIELD //----- For LEFT_FRAME_CUR_FIELD // Extract UV MaskA and MaskB from every other bit of Y masks and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w and.nz.f0.1 (8) null:w TempRow1(0)<16;8,2> 1:w // For FieldModeLeftMbFlag=0 && FieldModeCurrentMbFlag=1 mov (4) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Cb]<0;1,0>:ub { NoDDClr } mov (4) Mbaff_ALPHA(0,4)<1> r[ECM_AddrReg, bAlphaLeft1_Cb]<0;1,0>:ub { NoDDChk } mov (4) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaLeft0_Cb]<0;1,0>:ub { NoDDClr } mov (4) Mbaff_BETA(0,4)<1> r[ECM_AddrReg, bBetaLeft1_Cb]<0;1,0>:ub { NoDDChk } mov (4) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v00_0_Cb]<4;4,1>:ub { NoDDClr } mov (4) Mbaff_TC0(0,4)<1> r[ECM_AddrReg, bTc0_v00_1_Cb]<4;4,1>:ub { NoDDChk } jmpi V0_U_NEXT3 V0_U_NEXT2: // Extract UV MaskA and MaskB from every other bit of Y masks and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w and.nz.f0.1 (8) null:w TempRow1(0)<16;8,2> 1:w // Both are frames or fields mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Cb]<0;1,0>:ub mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaLeft0_Cb]<0;1,0>:ub mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v00_0_Cb]<1;2,0>:ub V0_U_NEXT3: // p1 = Prev MB U row 0 // p0 = Prev MB U row 1 // q0 = Cur MB U row 0 // q1 = Cur MB U row 1 mov (1) P_AddrReg:w PREV_MB_U_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_U_BASE:w { NoDDChk } // Store UV MaskA and MaskB mov (2) MaskA<1>:uw f0.0<2;2,1>:uw CALL(FILTER_UV_MBAFF, 1) //----------------------------------------------- //---------- Deblock V external left edge ---------- // No change to MaskA and MaskB cmp.z.f0.0 (4) null:w VertEdgePattern:uw LEFT_FIELD_CUR_FRAME:w cmp.z.f0.1 (4) null:w VertEdgePattern:uw LEFT_FRAME_CUR_FIELD:w // both are frame or field mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Cr]<0;1,0>:ub mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaLeft0_Cr]<0;1,0>:ub mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v00_0_Cr]<1;2,0>:ub // p1 = Prev MB V row 0 // p0 = Prev MB V row 1 // q0 = Cur MB V row 0 // q1 = Cur MB V row 1 mov (1) P_AddrReg:w PREV_MB_V_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_V_BASE:w { NoDDChk } // For FieldModeLeftMbFlag=1 && FieldModeCurrentMbFlag=0 (f0.0) mov (4) Mbaff_ALPHA(0,0)<2> r[ECM_AddrReg, bAlphaLeft0_Cr]<0;1,0>:ub { NoDDClr } (f0.0) mov (4) Mbaff_ALPHA(0,1)<2> r[ECM_AddrReg, bAlphaLeft1_Cr]<0;1,0>:ub { NoDDChk } (f0.0) mov (4) Mbaff_BETA(0,0)<2> r[ECM_AddrReg, bBetaLeft0_Cr]<0;1,0>:ub { NoDDClr } (f0.0) mov (4) Mbaff_BETA(0,1)<2> r[ECM_AddrReg, bBetaLeft1_Cr]<0;1,0>:ub { NoDDChk } (f0.0) mov (4) Mbaff_TC0(0,0)<2> r[ECM_AddrReg, bTc0_v00_0_Cr]<4;4,1>:ub { NoDDClr } (f0.0) mov (4) Mbaff_TC0(0,1)<2> r[ECM_AddrReg, bTc0_v00_1_Cr]<4;4,1>:ub { NoDDChk } // For FieldModeLeftMbFlag=0 && FieldModeCurrentMbFlag=1 (f0.1) mov (4) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Cr]<0;1,0>:ub { NoDDClr } (f0.1) mov (4) Mbaff_ALPHA(0,4)<1> r[ECM_AddrReg, bAlphaLeft1_Cr]<0;1,0>:ub { NoDDChk } (f0.1) mov (4) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaLeft0_Cr]<0;1,0>:ub { NoDDClr } (f0.1) mov (4) Mbaff_BETA(0,4)<1> r[ECM_AddrReg, bBetaLeft1_Cr]<0;1,0>:ub { NoDDChk } (f0.1) mov (4) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v00_0_Cr]<4;4,1>:ub { NoDDClr } (f0.1) mov (4) Mbaff_TC0(0,4)<1> r[ECM_AddrReg, bTc0_v00_1_Cr]<4;4,1>:ub { NoDDChk } // Set UV MaskA and MaskB mov (2) f0.0<1>:uw MaskA<2;2,1>:uw CALL(FILTER_UV_MBAFF, 1) //----------------------------------------------- BYPASS_V0_UV: // Set EdgeCntlMap2 = 0, so it always uses bS < 4 algorithm. // Same alpha and beta for all internal vert and horiz edges //---------- Deblock U internal vert middle edge ---------- //***** Need to take every other bit to form U or V maskA shr (16) TempRow0(0)<1> r[ECM_AddrReg, wEdgeCntlMap_IntMidVert]<0;1,0>:uw RRampW(0) // p1 = Cur MB U row 2 // p0 = Cur MB U row 3 // q0 = Cur MB U row 4 // q1 = Cur MB U row 5 mov (1) P_AddrReg:w 4*UV_ROW_WIDTH+SRC_MB_U_BASE:w { NoDDClr } // Skip 2 U rows and 2 V rows mov (1) Q_AddrReg:w 8*UV_ROW_WIDTH+SRC_MB_U_BASE:w { NoDDChk } mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaInternal_Cb]<0;1,0>:ub mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaInternal_Cb]<0;1,0>:ub mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v02_Cb]<1;2,0>:ub and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w // Store MaskA and MaskB mov (1) f0.1:uw 0:w mov (1) MaskB:uw 0:w { NoDDClr } mov (1) MaskA:uw f0.0:uw { NoDDChk } CALL(FILTER_UV_MBAFF, 1) //----------------------------------------------- //---------- Deblock V internal vert middle edge ---------- // P1 = Cur MB V row 2 // P0 = Cur MB V row 3 // Q0 = Cur MB V row 4 // Q1 = Cur MB V row 5 mov (1) P_AddrReg:w 4*UV_ROW_WIDTH+SRC_MB_V_BASE:w { NoDDClr } // Skip 2 U rows and 2 V rows mov (1) Q_AddrReg:w 8*UV_ROW_WIDTH+SRC_MB_V_BASE:w { NoDDChk } // Put MaskA into f0.0 // Put MaskB into f0.1 mov (2) f0.0<1>:uw MaskA<2;2,1>:uw mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaInternal_Cr]<0;1,0>:ub mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaInternal_Cr]<0;1,0>:ub mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v02_Cr]<1;2,0>:ub CALL(FILTER_UV_MBAFF, 1) //----------------------------------------------- intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Filter_Mbaff_Y_h.asm000066400000000000000000000220511231401140700250310ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////// AVC ILDB filter horizontal Mbaff Y /////////////////////////////////////////////////////// // // This filter code prepares the src data and control data for ILDB filtering on all horizontal edges of Y. // // It sssumes the data for horizontal de-blocking is already transposed. // // Luma: // // +-------+-------+-------+-------+ H0 Edge // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ H1 Edge // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ H2 Edge // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ H3 Edge // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ // ///////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xBBBB:w #endif //========== Luma deblocking ========== //---------- Deblock Y external top edge (H0) ---------- // Bypass deblocking if it is the top edge of the picture. and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterTopMbEdgeFlag:w // Check for FilterTopMbEdgeFlag mov (1) f0.1:w DualFieldMode:w // Check for dual field mode // Non dual field mode // Get (alpha >> 2) + 2 shr (16) Mbaff_ALPHA2(0,0)<1> r[ECM_AddrReg, bAlphaTop0_Y]<0;1,0>:ub 2:w // alpha >> 2 mov (2) MaskA<1>:uw r[ECM_AddrReg, wEdgeCntlMapA_ExtTopHorz0]<2;2,1>:uw // Ext Y mov (16) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaTop0_Y]<0;1,0>:ub mov (16) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaTop0_Y]<0;1,0>:ub mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h00_0_Y]<1;4,0>:ub add (16) Mbaff_ALPHA2(0,0)<1> Mbaff_ALPHA2(0,0)<16;16,1> 2:w // alpha2 = (alpha >> 2) + 2 (f0.0) jmpi H0_Y_DONE // Skip Ext Y deblocking (f0.1) jmpi DUAL_FIELD_Y mov (1) P_AddrReg:w PREV_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_Y_BASE:w { NoDDChk } CALL(FILTER_Y_MBAFF, 1) // Non dual field deblocking jmpi H0_Y_DONE DUAL_FIELD_Y: // Dual field mode, FieldModeCurrentMbFlag=0 && FieldModeAboveMbFlag=1 mov (1) P_AddrReg:w ABOVE_CUR_MB_BASE:w { NoDDClr } mov (1) Q_AddrReg:w ABOVE_CUR_MB_BASE+64:w { NoDDChk } // Must use PREV_MB_YW. TOP_MB_YW is not big enough. // Get top field rows mov (16) ABOVE_CUR_MB_YW(0)<1> PREV_MB_YW(0, 0)<16;8,1> // Copy p3, p2 mov (16) ABOVE_CUR_MB_YW(1)<1> PREV_MB_YW(2, 0)<16;8,1> // Copy p1, p0 mov (16) ABOVE_CUR_MB_YW(2)<1> SRC_YW(0, 0)<16;8,1> // Copy q0, q1 mov (16) ABOVE_CUR_MB_YW(3)<1> SRC_YW(2, 0)<16;8,1> // Copy q2, q3 CALL(FILTER_Y_MBAFF, 1) // Ext Y, top field // Save deblocked top field rows mov (8) PREV_MB_YW(1, 0)<1> ABOVE_CUR_MB_YW(0, 8) // Copy p2 mov (8) PREV_MB_YW(2, 0)<1> ABOVE_CUR_MB_YW(1, 0) // Copy p1 mov (8) PREV_MB_YW(3, 0)<1> ABOVE_CUR_MB_YW(1, 8) // Copy p0 mov (8) SRC_YW(0, 0)<1> ABOVE_CUR_MB_YW(2, 0) // Copy q0 mov (8) SRC_YW(1, 0)<1> ABOVE_CUR_MB_YW(2, 8) // Copy q1 mov (8) SRC_YW(2, 0)<1> ABOVE_CUR_MB_YW(3, 0) // Copy q2 //================================================================================== // Bottom field // Get (alpha >> 2) + 2 shr (16) Mbaff_ALPHA2(0,0)<1> r[ECM_AddrReg, bAlphaTop1_Y]<0;1,0>:ub 2:w // alpha >> 2 mov (1) P_AddrReg:w ABOVE_CUR_MB_BASE:w { NoDDClr } mov (1) Q_AddrReg:w ABOVE_CUR_MB_BASE+64:w { NoDDChk } // Get bot field rows mov (16) ABOVE_CUR_MB_YW(0)<1> PREV_MB_YW(0, 8)<16;8,1> // Copy p3, p2 mov (16) ABOVE_CUR_MB_YW(1)<1> PREV_MB_YW(2, 8)<16;8,1> // Copy p1, p0 mov (16) ABOVE_CUR_MB_YW(2)<1> SRC_YW(0, 8)<16;8,1> // Copy q0, q1 mov (16) ABOVE_CUR_MB_YW(3)<1> SRC_YW(2, 8)<16;8,1> // Copy q2, q3 mov (2) MaskA<1>:uw r[ECM_AddrReg, wEdgeCntlMapA_ExtTopHorz1]<2;2,1>:uw mov (16) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaTop1_Y]<0;1,0>:ub mov (16) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaTop1_Y]<0;1,0>:ub mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h00_1_Y]<1;4,0>:ub add (16) Mbaff_ALPHA2(0,0)<1> Mbaff_ALPHA2(0,0)<16;16,1> 2:w // alpha2 = (alpha >> 2) + 2 CALL(FILTER_Y_MBAFF, 1) // Ext Y, bot field // Save deblocked top field rows mov (8) PREV_MB_YW(1, 8)<1> ABOVE_CUR_MB_YW(0, 8) // Copy p2 mov (8) PREV_MB_YW(2, 8)<1> ABOVE_CUR_MB_YW(1, 0) // Copy p1 mov (8) PREV_MB_YW(3, 8)<1> ABOVE_CUR_MB_YW(1, 8) // Copy p0 mov (8) SRC_YW(0, 8)<1> ABOVE_CUR_MB_YW(2, 0) // Copy q0 mov (8) SRC_YW(1, 8)<1> ABOVE_CUR_MB_YW(2, 8) // Copy q1 mov (8) SRC_YW(2, 8)<1> ABOVE_CUR_MB_YW(3, 0) // Copy q2 //================================================================================== H0_Y_DONE: //BYPASS_H0_Y: //------------------------------------------------------------------ // Same alpha, alpha2, beta and MaskB for all internal edges // Get (alpha >> 2) + 2 shr (16) Mbaff_ALPHA2(0,0)<1> r[ECM_AddrReg, bAlphaInternal_Y]<0;1,0>:ub 2:w // alpha >> 2 // alpha = bAlphaInternal_Y // beta = bBetaInternal_Y mov (16) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaInternal_Y]<0;1,0>:ub mov (16) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaInternal_Y]<0;1,0>:ub mov (1) MaskB:uw 0:w // Set MaskB = 0 for all 3 edges, so it always uses bS < 4 algorithm. add (16) Mbaff_ALPHA2(0,0)<1> Mbaff_ALPHA2(0,0)<16;16,1> 2:w // alpha2 = (alpha >> 2) + 2 //---------- Deblock Y internal top edge (H1) ---------- // Bypass deblocking if FilterInternal4x4EdgesFlag = 0 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal4x4EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // (f0.0) jmpi BYPASS_H1_Y // p3 = Cur MB Y row 0 = r[P_AddrReg, 0]<16;16,1> // p2 = Cur MB Y row 1 = r[P_AddrReg, 16]<16;16,1> // p1 = Cur MB Y row 2 = r[P_AddrReg, 32]<16;16,1> // p0 = Cur MB Y row 3 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 4 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 5 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 6 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 7 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w SRC_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 4*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk } mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntTopHorz]:uw // tc0 has bTc0_h13_Y + bTc0_h12_Y + bTc0_h11_Y + bTc0_h10_Y mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h10_Y]<1;4,0>:ub // CALL(FILTER_Y_MBAFF, 1) PRED_CALL(-f0.0, FILTER_Y_MBAFF, 1) //BYPASS_H1_Y: //------------------------------------------------------------------ //---------- Deblock Y internal mid horizontal edge (H2) ---------- // Bypass deblocking if FilterInternal8x8EdgesFlag = 0 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal8x8EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // (f0.0) jmpi BYPASS_H2_Y // p3 = Cur MB Y row 4 = r[P_AddrReg, 0]<16;16,1> // p2 = Cur MB Y row 5 = r[P_AddrReg, 16]<16;16,1> // p1 = Cur MB Y row 6 = r[P_AddrReg, 32]<16;16,1> // p0 = Cur MB Y row 7 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 8 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 9 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 10 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 11 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w 4*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 8*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk } mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntMidHorz]:uw // tc0 has bTc0_h23_Y + bTc0_h22_Y + bTc0_h21_Y + bTc0_h20_Y mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h20_Y]<1;4,0>:ub // CALL(FILTER_Y_MBAFF, 1) PRED_CALL(-f0.0, FILTER_Y_MBAFF, 1) //BYPASS_H2_Y: //----------------------------------------------- //---------- Deblock Y internal bottom edge (H3) ---------- // Bypass deblocking if FilterInternal4x4EdgesFlag = 0 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal4x4EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // (f0.0) jmpi BYPASS_H3_Y // p3 = Cur MB Y row 8 = r[P_AddrReg, 0]<16;16,1> // p2 = Cur MB Y row 9 = r[P_AddrReg, 16]<16;16,1> // p1 = Cur MB Y row 10 = r[P_AddrReg, 32]<16;16,1> // p0 = Cur MB Y row 11 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 12 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 13 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 14 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 15 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w 8*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 12*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk } mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntBotHorz]:uw // tc0 has bTc0_h33_Y + bTc0_h32_Y + bTc0_h31_Y + bTc0_h30_Y mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_h30_Y]<1;4,0>:ub // CALL(FILTER_Y_MBAFF, 1) PRED_CALL(-f0.0, FILTER_Y_MBAFF, 1) //BYPASS_H3_Y: //----------------------------------------------- intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Filter_Mbaff_Y_v.asm000066400000000000000000000260001231401140700250450ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////// AVC ILDB filter vertical Mbaff Y /////////////////////////////////////////////////////// // // This filter code prepares the src data and control data for ILDB filtering on all vertical edges of Y. // // It sssumes the data for vertical de-blocking is already transposed. // // Luma: // // +-------+-------+-------+-------+ // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ // // V0 V1 V2 V3 // Edge Edge Edge Edge // ///////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xBBBB:w #endif //========== Luma deblocking ========== //---------- Deblock Y external left edge (V0) ---------- cmp.z.f0.0 (8) null:w VertEdgePattern:uw LEFT_FIELD_CUR_FRAME:w cmp.z.f0.1 (8) null:w VertEdgePattern:uw LEFT_FRAME_CUR_FIELD:w // Intial set for both are frame or field mov (16) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub mov (16) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaLeft0_Y]<0;1,0>:ub mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v00_0_Y]<1;4,0>:ub // For FieldModeCurrentMbFlag=1 && FieldModeLeftMbFlag=0 (f0.0) mov (8) Mbaff_ALPHA(0,0)<2> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub { NoDDClr } (f0.0) mov (8) Mbaff_ALPHA(0,1)<2> r[ECM_AddrReg, bAlphaLeft1_Y]<0;1,0>:ub { NoDDChk } (f0.0) mov (8) Mbaff_BETA(0,0)<2> r[ECM_AddrReg, bBetaLeft0_Y]<0;1,0>:ub { NoDDClr } (f0.0) mov (8) Mbaff_BETA(0,1)<2> r[ECM_AddrReg, bBetaLeft1_Y]<0;1,0>:ub { NoDDChk } (f0.0) mov (8) Mbaff_TC0(0,0)<2> r[ECM_AddrReg, bTc0_v00_0_Y]<1;2,0>:ub { NoDDClr } (f0.0) mov (8) Mbaff_TC0(0,1)<2> r[ECM_AddrReg, bTc0_v00_1_Y]<1;2,0>:ub { NoDDChk } and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterLeftMbEdgeFlag:w // Check for FilterLeftMbEdgeFlag // For FieldModeCurrentMbFlag=0 && FieldModeLeftMbFlag=1 (f0.1) mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub { NoDDClr } (f0.1) mov (8) Mbaff_ALPHA(0,8)<1> r[ECM_AddrReg, bAlphaLeft1_Y]<0;1,0>:ub { NoDDChk } (f0.1) mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaLeft0_Y]<0;1,0>:ub { NoDDClr } (f0.1) mov (8) Mbaff_BETA(0,8)<1> r[ECM_AddrReg, bBetaLeft1_Y]<0;1,0>:ub { NoDDChk } (f0.1) mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v00_0_Y]<1;2,0>:ub { NoDDClr } (f0.1) mov (8) Mbaff_TC0(0,8)<1> r[ECM_AddrReg, bTc0_v00_1_Y]<1;2,0>:ub { NoDDChk } // Get (alpha >> 2) + 2 shr (16) Mbaff_ALPHA2(0,0)<1> Mbaff_ALPHA(0) 2:w // alpha >> 2 // p3 = Prev MB Y row 0 = r[P_AddrReg, 0]<16;16,1> // p2 = Prev MB Y row 1 = r[P_AddrReg, 16]<16;16,1> // p1 = Prev MB Y row 2 = r[P_AddrReg, 32]<16;16,1> // p0 = Prev MB Y row 3 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 0 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 1 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 2 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 3 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w PREV_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_Y_BASE:w { NoDDChk } // Set MaskA and MaskB mov (2) MaskA<1>:uw r[ECM_AddrReg, wEdgeCntlMapA_ExtLeftVert0]<2;2,1>:uw add (16) Mbaff_ALPHA2(0,0)<1> Mbaff_ALPHA2(0,0)<16;16,1> 2:w // alpha2 = (alpha >> 2) + 2 // CALL(FILTER_Y_MBAFF, 1) PRED_CALL(-f0.0, FILTER_Y_MBAFF, 1) //BYPASS_V0_Y: //------------------------------------------------------------------ /* //---------- Deblock Y external left edge (V0) ---------- and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterLeftMbEdgeFlag:w // Check for FilterLeftMbEdgeFlag (f0.0) jmpi ILDB_LABEL(BYPASS_EXT_LEFT_EDGE_Y) // Get vertical border edge control data // mov (1) f0.0 0:w and (1) CTemp1_W:uw r[ECM_AddrReg, BitFlags]:ub FieldModeLeftMbFlag+FieldModeCurrentMbFlag:uw cmp.z.f0.0 (1) null:w CTemp1_W:uw LEFT_FIELD_CUR_FRAME:w (-f0.0) jmpi LEFT_EDGE_Y_NEXT1 // For FieldModeCurrentMbFlag=1 && FieldModeLeftMbFlag=0 mov (8) Mbaff_ALPHA(0,0)<2> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub { NoDDClr } mov (8) Mbaff_ALPHA(0,1)<2> r[ECM_AddrReg, bAlphaLeft1_Y]<0;1,0>:ub { NoDDChk } mov (8) Mbaff_BETA(0,0)<2> r[ECM_AddrReg, bBetaLeft0_Y]<0;1,0>:ub { NoDDClr } mov (8) Mbaff_BETA(0,1)<2> r[ECM_AddrReg, bBetaLeft1_Y]<0;1,0>:ub { NoDDChk } mov (8) Mbaff_TC0(0,0)<2> r[ECM_AddrReg, bTc0_v00_0_Y]<1;2,0>:ub { NoDDClr } mov (8) Mbaff_TC0(0,1)<2> r[ECM_AddrReg, bTc0_v00_1_Y]<1;2,0>:ub { NoDDChk } jmpi LEFT_EDGE_Y_ALPHA_BETA_TC0_SELECTED LEFT_EDGE_Y_NEXT1: cmp.z.f0.0 (1) null:w CTemp1_W:uw LEFT_FRAME_CUR_FIELD:w (-f0.0) jmpi LEFT_EDGE_Y_NEXT2 // For FieldModeCurrentMbFlag=0 && FieldModeLeftMbFlag=1 mov (8) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub { NoDDClr } mov (8) Mbaff_ALPHA(0,8)<1> r[ECM_AddrReg, bAlphaLeft1_Y]<0;1,0>:ub { NoDDChk } mov (8) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaLeft0_Y]<0;1,0>:ub { NoDDClr } mov (8) Mbaff_BETA(0,8)<1> r[ECM_AddrReg, bBetaLeft1_Y]<0;1,0>:ub { NoDDChk } mov (8) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v00_0_Y]<1;2,0>:ub { NoDDClr } mov (8) Mbaff_TC0(0,8)<1> r[ECM_AddrReg, bTc0_v00_1_Y]<1;2,0>:ub { NoDDChk } jmpi LEFT_EDGE_Y_ALPHA_BETA_TC0_SELECTED LEFT_EDGE_Y_NEXT2: // both are frame or field mov (16) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub mov (16) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaLeft0_Y]<0;1,0>:ub mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v00_0_Y]<1;4,0>:ub LEFT_EDGE_Y_ALPHA_BETA_TC0_SELECTED: mov (2) MaskA<1>:uw r[ECM_AddrReg, wEdgeCntlMapA_ExtLeftVert0]<2;2,1>:uw // p3 = Prev MB Y row 0 = r[P_AddrReg, 0]<16;16,1> // p2 = Prev MB Y row 1 = r[P_AddrReg, 16]<16;16,1> // p1 = Prev MB Y row 2 = r[P_AddrReg, 32]<16;16,1> // p0 = Prev MB Y row 3 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 0 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 1 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 2 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 3 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w PREV_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_Y_BASE:w { NoDDChk } // Get (alpha >> 2) + 2 shr (16) Mbaff_ALPHA2(0,0)<1> r[ECM_AddrReg, bAlphaLeft0_Y]<0;1,0>:ub 2:w // alpha >> 2 add (16) Mbaff_ALPHA2(0,0)<1> Mbaff_ALPHA2(0,0)<16;16,1> 2:w // alpha2 = (alpha >> 2) + 2 CALL(FILTER_Y_MBAFF, 1) ILDB_LABEL(BYPASS_EXT_LEFT_EDGE_Y): //------------------------------------------------------------------ */ // Same alpha, alpha2, beta and MaskB for all internal edges // Get (alpha >> 2) + 2 shr (16) Mbaff_ALPHA2(0,0)<1> r[ECM_AddrReg, bAlphaInternal_Y]<0;1,0>:ub 2:w // alpha >> 2 // alpha = bAlphaInternal_Y // beta = bBetaInternal_Y mov (16) Mbaff_ALPHA(0,0)<1> r[ECM_AddrReg, bAlphaInternal_Y]<0;1,0>:ub mov (16) Mbaff_BETA(0,0)<1> r[ECM_AddrReg, bBetaInternal_Y]<0;1,0>:ub mov (1) MaskB:uw 0:w // Set MaskB = 0 for all 3 edges, so it always uses bS < 4 algorithm. add (16) Mbaff_ALPHA2(0,0)<1> Mbaff_ALPHA2(0,0)<16;16,1> 2:w // alpha2 = (alpha >> 2) + 2 //---------- Deblock Y internal left edge (V1) ---------- // Bypass deblocking if FilterInternal4x4EdgesFlag = 0 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal4x4EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // (f0.0) jmpi BYPASS_V1_Y // p3 = Cur MB Y row 0 = r[P_AddrReg, 0]<16;16,1> // p2 = Cur MB Y row 1 = r[P_AddrReg, 16]<16;16,1> // p1 = Cur MB Y row 2 = r[P_AddrReg, 32]<16;16,1> // p0 = Cur MB Y row 3 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 4 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 5 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 6 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 7 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w SRC_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 4*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk } mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntLeftVert]:uw // tc0 has bTc0_v31_Y + bTc0_v21_Y + bTc0_v11_Y + bTc0_v01_Y mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v01_Y]<1;4,0>:ub // CALL(FILTER_Y_MBAFF, 1) PRED_CALL(-f0.0, FILTER_Y_MBAFF, 1) BYPASS_V1_Y: //------------------------------------------------------------------ //---------- Deblock Y internal mid vert edge (V2) ---------- // Bypass deblocking if FilterInternal8x8EdgesFlag = 0 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal8x8EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // (f0.0) jmpi BYPASS_V2_Y // p3 = Cur MB Y row 4 = r[P_AddrReg, 0]<16;16,1> // p2 = Cur MB Y row 5 = r[P_AddrReg, 16]<16;16,1> // p1 = Cur MB Y row 6 = r[P_AddrReg, 32]<16;16,1> // p0 = Cur MB Y row 7 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 8 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 9 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 10 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 11 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w 4*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 8*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk } mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntMidVert]:uw // tc0 has bTc0_v32_Y + bTc0_v22_Y + bTc0_v12_Y + bTc0_v02_Y mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v02_Y]<1;4,0>:ub // CALL(FILTER_Y_MBAFF, 1) PRED_CALL(-f0.0, FILTER_Y_MBAFF, 1) BYPASS_V2_Y: //----------------------------------------------- //---------- Deblock Y interal right edge (V3) ---------- // Bypass deblocking if FilterInternal4x4EdgesFlag = 0 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal4x4EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // (f0.0) jmpi BYPASS_V3_Y // p3 = Cur MB Y row 8 = r[P_AddrReg, 0]<16;16,1> // p2 = Cur MB Y row 9 = r[P_AddrReg, 16]<16;16,1> // p1 = Cur MB Y row 10 = r[P_AddrReg, 32]<16;16,1> // p0 = Cur MB Y row 11 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 12 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 13 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 14 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 15 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w 8*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 12*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk } mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntRightVert]:uw // tc0 has bTc0_v33_Y + bTc0_v23_Y + bTc0_v13_Y + bTc0_v03_Y mov (16) Mbaff_TC0(0,0)<1> r[ECM_AddrReg, bTc0_v03_Y]<1;4,0>:ub // CALL(FILTER_Y_MBAFF, 1) PRED_CALL(-f0.0, FILTER_Y_MBAFF, 1) BYPASS_V3_Y: //----------------------------------------------- intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Filter_UV_h.asm000066400000000000000000000122021231401140700240550ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////// AVC ILDB filter horizontal UV /////////////////////////////////////////////////////// // // This filter code prepares the src data and control data for ILDB filtering on all horizontal edges of UV. // // It sssumes the data for horizontal de-blocking is already transposed. // // Chroma: // // +-------+-------+ H0 Edge // | | | // | | | // | | | // +-------+-------+ H1 Edge // | | | // | | | // | | | // +-------+-------+ // ///////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xBBBC:w #endif //=============== Chroma deblocking ================ //---------- Deblock U external top edge ---------- and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterTopMbEdgeFlag:w // Check for FilterTopMbEdgeFlag // (f0.0) jmpi BYPASS_EXT_TOP_EDGE_UV // Get horizontal border edge control data. //***** Need to take every other bit to form U maskA and mask B // Get Luma maskA and maskB shr (16) TempRow0(0)<1> r[ECM_AddrReg, wEdgeCntlMapA_ExtTopHorz0]<0;1,0>:uw RRampW(0) shr (16) TempRow1(0)<1> r[ECM_AddrReg, wEdgeCntlMapB_ExtTopHorz0]<0;1,0>:uw RRampW(0) (f0.0) jmpi ILDB_LABEL(BYPASS_EXT_TOP_EDGE_UV) // Extract UV MaskA and MaskB from every other bit of Y masks and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w and.nz.f0.1 (8) null:w TempRow1(0)<16;8,2> 1:w //---------- Deblock U external edge ---------- // p1 = Prev MB U row 0 // p0 = Prev MB U row 1 // q0 = Cur MB U row 0 // q1 = Cur MB U row 1 // mov (1) P_AddrReg:w PREV_MB_U_BASE:w { NoDDClr } mov (1) P_AddrReg:w TOP_MB_U_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_U_BASE:w { NoDDChk } // alpha = bAlphaTop0_Cb, beta = bBetaTop0_Cb mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaTop0_Cb]<2;2,1>:ub { NoDDClr } // tc0 has bTc0_h03_0_Cb + bTc0_h02_0_Cb + bTc0_h01_0_Cb + bTc0_h00_0_Cb mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_h00_0_Cb]<4;4,1>:ub { NoDDChk } // UV MaskA and MaskB mov (2) MaskA<1>:uw f0.0<2;2,1>:uw CALL(FILTER_UV, 1) //---------- Deblock V external top edge ---------- // p1 = Prev MB V row 0 // p0 = Prev MB V row 1 // q0 = Cur MB V row 0 // q1 = Cur MB V row 1 // mov (1) P_AddrReg:w PREV_MB_V_BASE:w { NoDDClr } mov (1) P_AddrReg:w TOP_MB_V_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_V_BASE:w { NoDDChk } // alpha = bAlphaTop0_Cr, beta = bBetaTop0_Cr mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaTop0_Cr]<2;2,1>:ub { NoDDClr } // tc0 has bTc0_h03_0_Cr + bTc0_h02_0_Cr + bTc0_h01_0_Cr + bTc0_h00_0_Cr mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_h00_0_Cr]<4;4,1>:ub { NoDDChk } // UV MaskA and MaskB mov (2) f0.0<1>:uw MaskA<2;2,1>:uw CALL(FILTER_UV, 1) ILDB_LABEL(BYPASS_EXT_TOP_EDGE_UV): // Set EdgeCntlMap2 = 0, so it always uses bS < 4 algorithm. // Bypass deblocking if FilterInternal4x4EdgesFlag = 0 // and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal4x4EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // (f0.0) jmpi BYPASS_4x4_DEBLOCK_H //---------- Deblock U internal horz middle edge ---------- //***** Need to take every other bit to form U maskA // Get Luma maskA and maskB shr (16) TempRow0(0)<1> r[ECM_AddrReg, wEdgeCntlMap_IntMidHorz]<0;1,0>:uw RRampW(0) // p1 = Cur MB U row 2 // p0 = Cur MB U row 3 // q0 = Cur MB U row 4 // q1 = Cur MB U row 5 mov (1) P_AddrReg:w 4*UV_ROW_WIDTH+SRC_MB_U_BASE:w { NoDDClr } // Skip 2 U rows and 2 V rows mov (1) Q_AddrReg:w 8*UV_ROW_WIDTH+SRC_MB_U_BASE:w { NoDDChk } // alpha = bAlphaInternal_Cb, beta = bBetaInternal_Cb mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaInternal_Cb]<2;2,1>:ub { NoDDClr } // tc0 has bTc0_h23_Cb + bTc0_h22_Cb + bTc0_h21_Cb + bTc0_h20_Cb mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_h20_Cb]<4;4,1>:ub { NoDDChk } // Extract UV MaskA and MaskB from every other bit of Y masks and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w // UV MaskA and MaskB mov (1) f0.1:uw 0:w mov (1) MaskB:uw 0:w { NoDDClr } mov (1) MaskA:uw f0.0:uw { NoDDChk } CALL(FILTER_UV, 1) //---------- Deblock V internal horz middle edge ---------- // p1 = Cur MB V row 2 // p0 = Cur MB V row 3 // q0 = Cur MB V row 4 // q1 = Cur MB V row 5 mov (1) P_AddrReg:w 4*UV_ROW_WIDTH+SRC_MB_V_BASE:w { NoDDClr } // Skip 2 U rows and 2 V rows mov (1) Q_AddrReg:w 8*UV_ROW_WIDTH+SRC_MB_V_BASE:w { NoDDChk } // alpha = bAlphaInternal_Cr, beta = bBetaInternal_Cr mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaInternal_Cr]<2;2,1>:ub { NoDDClr } // tc0 has bTc0_h23_Cr + bTc0_h22_Cr + bTc0_h21_Cr + bTc0_h20_Cr mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_h20_Cr]<4;4,1>:ub { NoDDChk } // UV MaskA and MaskB mov (2) f0.0<1>:uw MaskA<2;2,1>:uw CALL(FILTER_UV, 1) //BYPASS_4x4_DEBLOCK_H: intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Filter_UV_v.asm000066400000000000000000000113341231401140700241000ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////// AVC LDB filter vertical UV /////////////////////////////////////////////////////// // // This filter code prepares the src data and control data for ILDB filtering on all vertical edges of UV. // // It sssumes the data for vertical de-blocking is already transposed. // // Chroma: // // +-------+-------+ // | | | // | | | // | | | // +-------+-------+ // | | | // | | | // | | | // +-------+-------+ // // V0 V1 // Edge Edge // ///////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xBBBC:w #endif //=============== Chroma deblocking ================ and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterLeftMbEdgeFlag:w // Check for FilterLeftMbEdgeFlag // (f0.0) jmpi BYPASS_EXT_LEFT_EDGE_UV // Get vertical border edge control data. // Get Luma maskA and maskB shr (16) TempRow0(0)<1> r[ECM_AddrReg, wEdgeCntlMapA_ExtLeftVert0]<0;1,0>:uw RRampW(0) shr (16) TempRow1(0)<1> r[ECM_AddrReg, wEdgeCntlMapB_ExtLeftVert0]<0;1,0>:uw RRampW(0) (f0.0) jmpi ILDB_LABEL(BYPASS_EXT_LEFT_EDGE_UV) // Extract UV MaskA and MaskB from every other bit of Y masks and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w and.nz.f0.1 (8) null:w TempRow1(0)<16;8,2> 1:w //---------- Deblock U external edge ---------- // p1 = Prev MB U row 0 // p0 = Prev MB U row 1 // q0 = Cur MB U row 0 // q1 = Cur MB U row 1 mov (1) P_AddrReg:w PREV_MB_U_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_U_BASE:w { NoDDChk } // alpha = bAlphaLeft0_Cb, beta = bBetaLeft0_Cb mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaLeft0_Cb]<2;2,1>:ub { NoDDClr } // tc0 has bTc0_v30_0_Cb + bTc0_v20_0_Cb + bTc0_v10_0_Cb + bTc0_v00_0_Cb mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_v00_0_Cb]<4;4,1>:ub { NoDDChk } // UV MaskA and MaskB mov (2) MaskA<1>:uw f0.0<2;2,1>:uw CALL(FILTER_UV, 1) //---------- Deblock V external edge ---------- // p1 = Prev MB V row 0 // p0 = Prev MB V row 1 // q0 = Cur MB V row 0 // q1 = Cur MB V row 1 mov (1) P_AddrReg:w PREV_MB_V_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_V_BASE:w { NoDDChk } // for vert edge: alpha = bAlphaLeft0_Cr, beta = bBetaLeft0_Cr mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaLeft0_Cr]<2;2,1>:ub { NoDDClr } // tc0 has bTc0_v30_0_Cr + bTc0_v20_0_Cr + bTc0_v10_0_Cr + bTc0_v00_0_Cr mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_v00_0_Cr]<4;4,1>:ub { NoDDChk } // UV MaskA and MaskB mov (2) f0.0<1>:uw MaskA<2;2,1>:uw CALL(FILTER_UV, 1) ILDB_LABEL(BYPASS_EXT_LEFT_EDGE_UV): // Set EdgeCntlMap2 = 0, so it always uses bS < 4 algorithm. // Same alpha and beta for all internal vert and horiz edges //***** Need to take every other bit to form U or V maskA // Get Luma maskA and maskB shr (16) TempRow0(0)<1> r[ECM_AddrReg, wEdgeCntlMap_IntMidVert]<0;1,0>:uw RRampW(0) //---------- Deblock U internal edge ---------- // p1 = Cur MB U row 2 // p0 = Cur MB U row 3 // q0 = Cur MB U row 4 // q1 = Cur MB U row 5 mov (1) P_AddrReg:w 4*UV_ROW_WIDTH+SRC_MB_U_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 8*UV_ROW_WIDTH+SRC_MB_U_BASE:w { NoDDChk } // alpha = bAlphaInternal_Cb, beta = bBetaInternal_Cb mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaInternal_Cb]<2;2,1>:ub { NoDDClr } // tc0 has bTc0_v32_Cb + bTc0_v22_Cb + bTc0_v12_Cb + bTc0_v02_Cb mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_v02_Cb]<4;4,1>:ub { NoDDChk } // Extract UV MaskA and MaskB from every other bit of Y masks and.nz.f0.0 (8) null:w TempRow0(0)<16;8,2> 1:w // UV MaskA and MaskB mov (1) f0.1:uw 0:w mov (1) MaskB:uw 0:w { NoDDClr } mov (1) MaskA:uw f0.0:uw { NoDDChk } CALL(FILTER_UV, 1) //---------- Deblock V internal edge ---------- // P1 = Cur MB V row 2 // P0 = Cur MB V row 3 // Q0 = Cur MB V row 4 // Q1 = Cur MB V row 5 mov (1) P_AddrReg:w 4*UV_ROW_WIDTH+SRC_MB_V_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 8*UV_ROW_WIDTH+SRC_MB_V_BASE:w { NoDDChk } // alpha = bAlphaInternal_Cr, beta = bBetaInternal_Cr mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaInternal_Cr]<2;2,1>:ub { NoDDClr } // tc0 has bTc0_v32_Cr + bTc0_v22_Cr + bTc0_v12_Cr + bTc0_v02_Cr mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_v02_Cr]<4;4,1>:ub { NoDDChk } // UV MaskA and MaskB mov (2) f0.0<1>:uw MaskA<2;2,1>:uw CALL(FILTER_UV, 1) //BYPASS_4x4_DEBLOCK_V: intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Filter_Y_h.asm000066400000000000000000000171041231401140700237410ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////// AVC ILDB filter horizontal Y /////////////////////////////////////////////////////// // // This filter code prepares the src data and control data for ILDB filtering on all horizontal edges of Y. // // It sssumes the data for horizontal de-blocking is already transposed. // // Luma: // // +-------+-------+-------+-------+ H0 Edge // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ H1 Edge // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ H2 Edge // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ H3 Edge // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ // ///////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xBBBB:w #endif //========== Luma deblocking ========== //---------- Deblock Y external top edge (H0) ---------- // Bypass deblocking if it is the top edge of the picture. and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterTopMbEdgeFlag:w // Check for FilterTopMbEdgeFlag // and.z.f0.1 (1) null:uw r[ECM_AddrReg, wEdgeCntlMapA_ExtTopHorz0]:uw 0xFFFF:uw // MaskA = 0? // Get (alpha >> 2) + 2 shr (1) alpha2:w r[ECM_AddrReg, bAlphaTop0_Y]:ub 2:w // alpha >> 2 // p3 = Prev MB Y row 0 = r[P_AddrReg, 0]<16;16,1> // p2 = Prev MB Y row 1 = r[P_AddrReg, 16]<16;16,1> // p1 = Prev MB Y row 2 = r[P_AddrReg, 32]<16;16,1> // p0 = Prev MB Y row 3 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 0 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 1 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 2 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 3 = r[Q_AddrReg, 48]<16;16,1> // mov (1) P_AddrReg:w PREV_MB_Y_BASE:w { NoDDClr } mov (1) P_AddrReg:w TOP_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_Y_BASE:w { NoDDChk } // Get horizontal border edge control data // alpha = bAlphaTop0_Y // beta = bBetaTop0_Y mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaTop0_Y]<2;2,1>:ub { NoDDClr } // 2 channels for alpha and beta mov (2) MaskA<1>:uw r[ECM_AddrReg, wEdgeCntlMapA_ExtTopHorz0]<2;2,1>:uw { NoDDClr, NoDDChk } // tc0 has bTc0_h03_0_Y | bTc0_h02_0_Y | bTc0_h01_0_Y | bTc0_h00_0_Y mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_h00_0_Y]<4;4,1>:ub { NoDDChk } // (f0.0) jmpi BYPASS_EXT_TOP_EDGE_Y // (f0.0.anyv) jmpi BYPASS_EXT_TOP_EDGE_Y add (1) alpha2:w alpha2:w 2:w // alpha2 = (alpha >> 2) + 2 // CALL(FILTER_Y, 1) PRED_CALL(-f0.0, FILTER_Y, 1) //BYPASS_EXT_TOP_EDGE_Y: //------------------------------------------------------------------ // Same alpha, alpha2, beta and MaskB for all internal edges // Get (alpha >> 2) + 2 shr (1) alpha2:w r[ECM_AddrReg, bAlphaInternal_Y]:ub 2:w // alpha >> 2 // alpha = bAlphaInternal_Y // beta = bBetaInternal_Y mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaInternal_Y]<2;2,1>:ub { NoDDClr } // Set MaskB = 0 for all 3 int edges, so it always uses bS < 4 algorithm. mov (1) MaskB:uw 0:w { NoDDChk } add (1) alpha2:w alpha2:w 2:w // alpha2 = (alpha >> 2) + 2 //---------- Deblock Y internal top edge (H1) ---------- // Bypass deblocking if FilterInternal4x4EdgesFlag = 0 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal4x4EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // p3 = Cur MB Y row 0 = r[P_AddrReg, 0]<16;16,1> // p2 = Cur MB Y row 1 = r[P_AddrReg, 16]<16;16,1> // p1 = Cur MB Y row 2 = r[P_AddrReg, 32]<16;16,1> // p0 = Cur MB Y row 3 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 4 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 5 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 6 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 7 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w SRC_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 4*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk } mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntTopHorz]:uw { NoDDClr } // tc0 has bTc0_h13_Y + bTc0_h12_Y + bTc0_h11_Y + bTc0_h10_Y mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_h10_Y]<4;4,1>:ub { NoDDChk } // (f0.0) jmpi BYPASS_4x4_DEBLOCK_H // (f0.0.anyv) jmpi BYPASS_4x4_DEBLOCK_H // CALL(FILTER_Y, 1) PRED_CALL(-f0.0, FILTER_Y, 1) //BYPASS_4x4_DEBLOCK_H: //------------------------------------------------------------------ //---------- Deblock Y internal mid horizontal edge (H2) ---------- // Bypass deblocking if FilterInternal8x8EdgesFlag = 0 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal8x8EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // and.z.f0.1 (1) null:uw r[ECM_AddrReg, wEdgeCntlMap_IntMidHorz]:uw 0xFFFF:uw // MaskA = 0? // p3 = Cur MB Y row 4 = r[P_AddrReg, 0]<16;16,1> // p2 = Cur MB Y row 5 = r[P_AddrReg, 16]<16;16,1> // p1 = Cur MB Y row 6 = r[P_AddrReg, 32]<16;16,1> // p0 = Cur MB Y row 7 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 8 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 9 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 10 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 11 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w 4*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 8*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk } mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntMidHorz]:uw { NoDDClr } // mov (1) MaskB:uw 0:w // Set MaskB = 0, so it always uses bS < 4 algorithm. // tc0 has bTc0_h23_Y + bTc0_h22_Y + bTc0_h21_Y + bTc0_h20_Y mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_h20_Y]<4;4,1>:ub { NoDDChk } // (f0.0) jmpi BYPASS_8x8_DEBLOCK_H // (f0.0.anyv) jmpi BYPASS_8x8_DEBLOCK_H // CALL(FILTER_Y, 1) PRED_CALL(-f0.0, FILTER_Y, 1) //BYPASS_8x8_DEBLOCK_H: //----------------------------------------------- //---------- Deblock Y internal bottom edge (H3) ---------- // Bypass deblocking if FilterInternal4x4EdgesFlag = 0 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal4x4EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // and.z.f0.1 (1) null:uw r[ECM_AddrReg, wEdgeCntlMap_IntBotHorz]:uw 0xFFFF:uw // MaskA = 0? // p3 = Cur MB Y row 8 = r[P_AddrReg, 0]<16;16,1> // p2 = Cur MB Y row 9 = r[P_AddrReg, 16]<16;16,1> // p1 = Cur MB Y row 10 = r[P_AddrReg, 32]<16;16,1> // p0 = Cur MB Y row 11 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 12 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 13 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 14 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 15 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w 8*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 12*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk } mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntBotHorz]:uw { NoDDClr } // mov (1) MaskB:uw 0:w // Set MaskB = 0, so it always uses bS < 4 algorithm. // tc0 has bTc0_h33_Y + bTc0_h32_Y + bTc0_h31_Y + bTc0_h30_Y mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_h30_Y]<4;4,1>:ub { NoDDChk } // (f0.0) jmpi BYPASS_4x4_DEBLOCK_H2 // (f0.0.anyv) jmpi BYPASS_4x4_DEBLOCK_H2 // CALL(FILTER_Y, 1) PRED_CALL(-f0.0, FILTER_Y, 1) //BYPASS_4x4_DEBLOCK_H2: //----------------------------------------------- intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Filter_Y_v.asm000066400000000000000000000171121231401140700237560ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////// AVC ILDB filter vertical Y /////////////////////////////////////////////////////// // // This filter code prepares the src data and control data for ILDB filtering on all vertical edges of Y. // // It sssumes the data for vertical de-blocking is already transposed. // // Luma: // // +-------+-------+-------+-------+ // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ // | | | | | // | | | | | // | | | | | // +-------+-------+-------+-------+ // // V0 V1 V2 V3 // Edge Edge Edge Edge // ///////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xBBBB:w #endif //========== Luma deblocking ========== //---------- Deblock Y external left edge (V0) ---------- // Bypass deblocking if it is left edge of the picture. and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterLeftMbEdgeFlag:w // Check for FilterLeftMbEdgeFlag // and.z.f0.1 (1) null:uw r[ECM_AddrReg, wEdgeCntlMapA_ExtLeftVert0]:uw 0xFFFF:uw // MaskA = 0? // Get (alpha >> 2) + 2 shr (1) alpha2:w r[ECM_AddrReg, bAlphaLeft0_Y]:ub 2:w // alpha >> 2 // p3 = Prev MB Y row 0 = r[P_AddrReg, 0]<16;16,1> // p2 = Prev MB Y row 1 = r[P_AddrReg, 16]<16;16,1> // p1 = Prev MB Y row 2 = r[P_AddrReg, 32]<16;16,1> // p0 = Prev MB Y row 3 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 0 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 1 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 2 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 3 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w PREV_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w SRC_MB_Y_BASE:w { NoDDChk } // Get vertical border edge control data // alpha = bAlphaLeft0_Y // beta = bBetaLeft0_Y mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaLeft0_Y]<2;2,1>:ub { NoDDClr } // 2 channels for alpha and beta mov (2) MaskA<1>:uw r[ECM_AddrReg, wEdgeCntlMapA_ExtLeftVert0]<2;2,1>:uw { NoDDClr, NoDDChk } // tc0 has bTc0_v30_0_Y | bTc0_v20_0_Y | bTc0_v10_0_Y | bTc0_v00_0_Y mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_v00_0_Y]<4;4,1>:ub { NoDDChk } // (f0.0) jmpi BYPASS_EXT_LEFT_EDGE_Y // (f0.0.anyv) jmpi BYPASS_EXT_LEFT_EDGE_Y add (1) alpha2:w alpha2:w 2:w // alpha2 = (alpha >> 2) + 2 // CALL(FILTER_Y, 1) PRED_CALL(-f0.0, FILTER_Y, 1) //BYPASS_EXT_LEFT_EDGE_Y: //------------------------------------------------------------------ // Same alpha, alpha2, beta and MaskB for all internal edges // Get (alpha >> 2) + 2 shr (1) alpha2:w r[ECM_AddrReg, bAlphaInternal_Y]:ub 2:w // alpha >> 2 // alpha = bAlphaInternal_Y // beta = bBetaInternal_Y mov (2) alpha<1>:w r[ECM_AddrReg, bAlphaInternal_Y]<2;2,1>:ub { NoDDClr } // Set MaskB = 0 for all 3 int edges, so it always uses bS < 4 algorithm. mov (1) MaskB:uw 0:w { NoDDChk } add (1) alpha2:w alpha2:w 2:w // alpha2 = (alpha >> 2) + 2 //---------- Deblock Y internal left edge (V1) ---------- // Bypass deblocking if FilterInternal4x4EdgesFlag = 0 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal4x4EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // and.z.f0.1 (1) null:uw r[ECM_AddrReg, wEdgeCntlMap_IntLeftVert]:uw 0xFFFF:uw // MaskA = 0? // p3 = Cur MB Y row 0 = r[P_AddrReg, 0]<16;16,1> // p2 = Cur MB Y row 1 = r[P_AddrReg, 16]<16;16,1> // p1 = Cur MB Y row 2 = r[P_AddrReg, 32]<16;16,1> // p0 = Cur MB Y row 3 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 4 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 5 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 6 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 7 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w SRC_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 4*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk } mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntLeftVert]:uw { NoDDClr } // tc0 has bTc0_v31_Y + bTc0_v21_Y + bTc0_v11_Y + bTc0_v01_Y mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_v01_Y]<4;4,1>:ub { NoDDChk } // (f0.0) jmpi BYPASS_4x4_DEBLOCK_V // (f0.0.anyv) jmpi BYPASS_4x4_DEBLOCK_V // CALL(FILTER_Y, 1) PRED_CALL(-f0.0, FILTER_Y, 1) //BYPASS_4x4_DEBLOCK_V: //------------------------------------------------------------------ //---------- Deblock Y internal mid vert edge (V2) ---------- // Bypass deblocking if FilterInternal8x8EdgesFlag = 0 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal8x8EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // and.z.f0.1 (1) null:uw r[ECM_AddrReg, wEdgeCntlMap_IntMidVert]:uw 0xFFFF:uw // MaskA = 0? // p3 = Cur MB Y row 4 = r[P_AddrReg, 0]<16;16,1> // p2 = Cur MB Y row 5 = r[P_AddrReg, 16]<16;16,1> // p1 = Cur MB Y row 6 = r[P_AddrReg, 32]<16;16,1> // p0 = Cur MB Y row 7 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 8 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 9 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 10 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 11 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w 4*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 8*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk } mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntMidVert]:uw { NoDDClr } // mov (1) MaskB:uw 0:w // Set MaskB = 0, so it always uses bS < 4 algorithm. // tc0 has bTc0_v32_Y + bTc0_v22_Y + bTc0_v12_Y + bTc0_v02_Y mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_v02_Y]<4;4,1>:ub { NoDDChk } // (f0.0) jmpi BYPASS_8x8_DEBLOCK_V // (f0.0.anyv) jmpi BYPASS_8x8_DEBLOCK_V // CALL(FILTER_Y, 1) PRED_CALL(-f0.0, FILTER_Y, 1) //BYPASS_8x8_DEBLOCK_V: //----------------------------------------------- //---------- Deblock Y interal right edge (V3) ---------- // Bypass deblocking if FilterInternal4x4EdgesFlag = 0 and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FilterInternal4x4EdgesFlag:w // Check for FilterInternal4x4EdgesFlag // and.z.f0.1 (1) null:uw r[ECM_AddrReg, wEdgeCntlMap_IntRightVert]:uw 0xFFFF:uw // MaskA = 0? // p3 = Cur MB Y row 8 = r[P_AddrReg, 0]<16;16,1> // p2 = Cur MB Y row 9 = r[P_AddrReg, 16]<16;16,1> // p1 = Cur MB Y row 10 = r[P_AddrReg, 32]<16;16,1> // p0 = Cur MB Y row 11 = r[P_AddrReg, 48]<16;16,1> // q0 = Cur MB Y row 12 = r[Q_AddrReg, 0]<16;16,1> // q1 = Cur MB Y row 13 = r[Q_AddrReg, 16]<16;16,1> // q2 = Cur MB Y row 14 = r[Q_AddrReg, 32]<16;16,1> // q3 = Cur MB Y row 15 = r[Q_AddrReg, 48]<16;16,1> mov (1) P_AddrReg:w 8*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDClr } mov (1) Q_AddrReg:w 12*Y_ROW_WIDTH+SRC_MB_Y_BASE:w { NoDDChk } mov (1) MaskA:uw r[ECM_AddrReg, wEdgeCntlMap_IntRightVert]:uw { NoDDClr } // mov (1) MaskB:uw 0:w // Set MaskB = 0, so it always uses bS < 4 algorithm. // tc0 has bTc0_v33_Y + bTc0_v23_Y + bTc0_v13_Y + bTc0_v03_Y mov (4) tc0<1>:ub r[ECM_AddrReg, bTc0_v03_Y]<4;4,1>:ub { NoDDChk } // (f0.0) jmpi BYPASS_4x4_DEBLOCK_V2 // (f0.0.anyv) jmpi BYPASS_4x4_DEBLOCK_V2 // CALL(FILTER_Y, 1) PRED_CALL(-f0.0, FILTER_Y, 1) //BYPASS_4x4_DEBLOCK_V2: //----------------------------------------------- intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_ForwardMsg.asm000066400000000000000000000041431231401140700237670ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //========== Forward message to root thread through gateway ========== // Each child thread write a byte into the root GRF r50 defiend in open Gataway. #if defined(_DEBUG) mov (1) EntrySignatureC:w 0x7777:w #endif // Init payload to r0 mov (8) GatewayPayload<1>:ud 0:w //{ NoDDClr } // Forward a message: // Offset = x relative to r50 (defiend in open gataway), x = ORIX >> 4 [bit 28:16] // Need to shift left 16 // shift 2 more bits for byte to word offset //shl (1) Offset_Length:ud GateWayOffsetC:w 16:w { NoDDClr, NoDDChk } shl (1) Offset_Length:ud GateWayOffsetC:w 18:w // 2 bytes offset add (1) Offset_Length:ud Offset_Length:ud 0x00020000:d { NoDDClr } // Length = 1 byte, [bit 10:8 = 000] //000 xxxxxxxxxxxxx 00000 000 00000000 ==> 000x xxxx xxxx xxxx 0000 0000 0000 0000 //mov (1) DispatchID:ub r0.20:ub // Dispatch ID //Move in EUid and Thread ID that we received from the PARENT thread mov (1) EUID_TID:uw r0.6:uw { NoDDClr, NoDDChk } mov (1) GatewayPayloadKey:uw 0x1212:uw { NoDDClr, NoDDChk } // Key //mov (4) GatewayPayload<1>:ud 0:ud { NoDDClr, NoDDChk } // Init payload low 4 dword // Write back one byte (value = 0xFF) to root thread GRF to indicate this child thread is finished // All lower 4 bytes must be assigned to the same byte value. mov (4) GatewayPayload<1>:ub 0xFFFF:uw { NoDDChk } // msg descriptor bit 15 set to '1' for notification #ifdef GW_DCN // For ILK, EOT bit should also be set to terminate the thread. This is to fix a timing related HW issue. // send (8) null:ud m0 GatewayPayload<8;8,1>:ud MSG_GW_EOT FWDMSGDSC+NOTIFYMSG #else send (8) null:ud m0 GatewayPayload<8;8,1>:ud MSG_GW FWDMSGDSC+NOTIFYMSG #endif // GW_DCN //========== Forward Msg Done ======================================== intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_LumaThrdLimit.asm000066400000000000000000000032041231401140700244300ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //========== Forward message to root thread through gateway ========== // Chroma root kenrel updates luma thread limit. #if defined(_DEBUG) mov (1) EntrySignatureC:w 0x7788:w #endif // Init payload to r0 mov (8) GatewayPayload<1>:ud 0:w { NoDDClr } // Forward a message: // Offset = x relative to r50 (defiend in open gataway), x = ORIX >> 4 [bit 28:16] // Need to shift left 16 mov (1) Offset_Length:ud THREAD_LIMIT_OFFSET:ud { NoDDClr, NoDDChk } // Length = 1 byte, [bit 10:8 = 000] //000 xxxxxxxxxxxxx 00000 000 00000000 ==> 000x xxxx xxxx xxxx 0000 0000 0000 0000 //mov (1) DispatchID:ub r0.20:ub // Dispatch ID // Copy EUid and Thread ID that we received from the PARENT thread mov (1) EUID_TID:uw r0.6:uw { NoDDClr, NoDDChk } mov (1) GatewayPayloadKey:uw 0x1212:uw { NoDDChk } // Key //mov (4) GatewayPayload<1>:ud 0:ud { NoDDClr, NoDDChk } // Init payload low 4 dword // Write back one byte (value = 0xFF) to root thread GRF to indicate this child thread is finished // All lower 4 bytes must be assigned to the same byte value. add (1) Temp1_W:w MaxThreads:uw -OutstandingThreads:uw mov (4) GatewayPayload<1>:ub Temp1_B<0;1,0>:ub send (8) GatewayResponse:ud m0 GatewayPayload<8;8,1>:ud MSG_GW FWDMSGDSC //========== Forward Msg Done ======================================== intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Luma_Core.asm000066400000000000000000000362501231401140700235660ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__AVC_ILDB_LUMA_CORE__) // Make sure this file is only included once #define __AVC_ILDB_LUMA_CORE__ ////////// AVC ILDB Luma Core ///////////////////////////////////////////////////////////////////////////////// // // This core performs AVC LUMA ILDB filtering on one horizontal edge (16 pixels) of a MB. // If data is transposed, it can also de-block a vertical edge. // // Bafore calling this subroutine, caller needs to set the following parameters. // // - EdgeCntlMap1 // Edge control map A // - EdgeCntlMap2 // Edge control map B // - P_AddrReg // Src and dest address register for P pixels // - Q_AddrReg // Src and dest address register for Q pixels // - alpha // alpha corresponding to the edge to be filtered // - beta // beta corresponding to the edge to be filtered // - tc0 // tc0 corresponding to the edge to be filtered // // // +----+----+----+----+----+----+----+----+ // | p3 | p2 | P1 | p0 | q0 | q1 | q2 | q3 | // +----+----+----+----+----+----+----+----+ // // p3 = r[P_AddrReg, 0]<16;16,1> // p2 = r[P_AddrReg, 16]<16;16,1> // p1 = r[P_AddrReg, 32]<16;16,1> // p0 = r[P_AddrReg, 48]<16;16,1> // q0 = r[Q_AddrReg, 0]<16;16,1> // q1 = r[Q_AddrReg, 16]<16;16,1> // q2 = r[Q_AddrReg, 32]<16;16,1> // q3 = r[Q_AddrReg, 48]<16;16,1> // ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // The region is both src and dest // P0-P3 and Q0-Q3 should be only used if they have not been modified to new values #undef P3 #undef P2 #undef P1 #undef P0 #undef Q0 #undef Q1 #undef Q2 #undef Q3 #define P3 r[P_AddrReg, 0]<16;16,1>:ub #define P2 r[P_AddrReg, 16]<16;16,1>:ub #define P1 r[P_AddrReg, 32]<16;16,1>:ub #define P0 r[P_AddrReg, 48]<16;16,1>:ub #define Q0 r[Q_AddrReg, 0]<16;16,1>:ub #define Q1 r[Q_AddrReg, 16]<16;16,1>:ub #define Q2 r[Q_AddrReg, 32]<16;16,1>:ub #define Q3 r[Q_AddrReg, 48]<16;16,1>:ub // New region as dest #undef NewP2 #undef NewP1 #undef NewP0 #undef NewQ0 #undef NewQ1 #undef NewQ2 #define NewP2 r[P_AddrReg, 16]<1>:ub #define NewP1 r[P_AddrReg, 32]<1>:ub #define NewP0 r[P_AddrReg, 48]<1>:ub #define NewQ0 r[Q_AddrReg, 0]<1>:ub #define NewQ1 r[Q_AddrReg, 16]<1>:ub #define NewQ2 r[Q_AddrReg, 32]<1>:ub // Filter one luma edge FILTER_Y: #if defined(_DEBUG) mov (1) EntrySignatureC:w 0x1111:w #endif //---------- Derive filterSampleflag in AVC spec, equition (8-469) ---------- // bS is in MaskA // Src copy of the p3, p2, p1, p0, q0, q1, q2, q3 // mov (16) p0123_W(0)<1> r[P_AddrReg]<16;16,1>:uw // mov (16) p0123_W(1)<1> r[P_AddrReg, 32]<16;16,1>:uw // mov (16) q0123_W(0)<1> r[Q_AddrReg]<16;16,1>:uw // mov (16) q0123_W(1)<1> r[Q_AddrReg, 32]<16;16,1>:uw mov (2) f0.0<1>:uw MaskA<2;2,1>:uw add (16) q0_p0(0)<1> Q0 -P0 // q0-p0 add (16) TempRow0(0)<1> P1 -P0 // p1-p0 add (16) TempRow1(0)<1> Q1 -Q0 // q1-q0 // Build FilterSampleFlag // abs(q0-p0) < alpha (f0.0) cmp.l.f0.0 (16) null:w (abs)q0_p0(0) alpha:w // abs(p1-p0) < Beta (f0.0) cmp.l.f0.0 (16) null:w (abs)TempRow0(0) beta:w // abs(q1-q0) < Beta (f0.0) cmp.l.f0.0 (16) null:w (abs)TempRow1(0) beta:w //----------------------------------------------------------------------------------------- (f0.0) if (16) Y_ENDIF1 // For channels whose edge control map1 = 1 ---> perform de-blocking // mov (1) f0.1:uw MaskB:uw {NoMask} // Now check for which algorithm to apply // (abs)ap = |p2-p0| add (16) ap(0)<1> P2 -P0 // ap = p2-p0 // (abs)aq = |q2-q0| add (16) aq(0)<1> Q2 -Q0 // aq = q2-q0 // Make a copy of unmodified p0 and p1 for use in q0'and q1' calculation mov (16) p0123_W(1)<1> r[P_AddrReg, 32]<16;16,1>:uw {NoMask} (f0.1) if (16) Y_ELSE2 // For channels whose edge control map2 = 1 ---> bS = 4 algorithm // Compute q0', q1' and q2' //----------------------------------------------------------------------------- // bS = 4 Algorithm : // // gama = |p0-q0| < ((alpha >> 2) + 2) // deltap = (ap> 3; // p1' = ( p2 + p1 + p0 + q0 + 2) >> 2; // p2' = (2*p3 +3*p2 + p1 + p0 + q0 + 4) >> 3; // } else { // p0' = ( 2*p1 + p0 + q1 + 2) >> 2; // } //----------------------------------------------------------------------------- // gama = |p0-q0| < ((alpha >> 2) + 2) = |p0-q0| < alpha2 cmp.l.f0.1 (16) null:w (abs)q0_p0(0) alpha2:w // Common P01 = p0 + p1 add (16) P0_plus_P1(0)<1> P0 P1 // Common Q01 = q0 + q1 add (16) Q0_plus_Q1(0)<1> Q0 Q1 // mov (1) CTemp1_W:w f0.1:uw {NoMask} mov (1) f0.0:uw f0.1:uw {NoMask} // deltap = ((abs)ap < beta) && gama (f0.1) cmp.l.f0.1 (16) null:w (abs)ap(0) beta<0;1,0>:w // (abs)ap < beta ? // deltaq = ((abs)aq < beta) && gama (f0.0) cmp.l.f0.0 (16) null:w (abs)aq(0) beta<0;1,0>:w // (abs)aq < beta ? // mov (1) CTemp1_W:w f0.0:uw {NoMask} // gama = |p0-q0| < ((alpha >> 2) + 2) for each channel // and (1) f0.1:w f0.1:uw CTemp1_W:w {NoMask} // deltap = (ap P2 P3 // A = (p1 + p0) + q0 = P01 + q0 add (16) A(0)<1> P0_plus_P1(0) Q0 // A = P01 + q0 // Now acc0 = A // B = p2 + (p1 + p0 + q0) + 4 = p2 + A + 4 // add (16) acc0.0<1>:w P2 4:w // p2 + 4 // add (16) BB(0)<1> acc0.0<16;16,1>:w A(0) // B = p2 + A + 4 add (16) acc0.0<1>:w acc0.0<16;16,1>:w 4:w // p2 + 4 add (16) BB(0)<1> acc0.0<16;16,1>:w P2 // B = p2 + A + 4 // Now acc0 = B // p2' = (2*p3 +3*p2 + A + 4) >> 3 = (2*(p3+p2) + B) >> 3 // mov (16) acc0.0<1>:w BB(0) mac (16) acc0.0<1>:w P2_plus_P3(0) 2:w shr.sat (16) TempRow3B(0)<2> acc0.0<16;16,1>:w 3:w // p1' = (p2 + A + 2) >> 2 = (B - 2) >> 2 add (16) acc0.0<1>:w BB(0) -2:w shr.sat (16) TempRow1B(0)<2> acc0.0<16;16,1>:w 2:w // p0' = (p2 +2*A + q1 + 4) >> 3 = (B + A + q1) >> 3 add (16) acc0.0<1>:w Q1 A(0) // B + A add (16) acc0.0<1>:w acc0.0<16;16,1>:w BB(0) // B + A + q1 shr.sat (16) TempRow0B(0)<2> acc0.0<16;16,1>:w 3:w // (B + A + q1) >> 3 // p2' = (2*p3 +3*p2 + A + 4) >> 3 = (2*(p3+p2) + B) >> 3 // mov (16) acc0.0<1>:w BB(0) // mac (16) acc0.0<1>:w P2_plus_P3(0) 2:w // shr.sat (16) TempRow3B(0)<2> acc0.0<16;16,1>:w 3:w mov (16) NewP2 TempRow3B(0) // p2' mov (16) NewP1 TempRow1B(0) // p1' mov (16) NewP0 TempRow0B(0) // p0' Y_ELSE3: else (16) Y_ENDIF3 // for channels its deltap = false // p0' = (2*p1 + p0 + q1 + 2) >> 2 = (p1 + P01 + q1 + 2) >> 2 add (16) acc0.0<1>:w P1 P0_plus_P1(0) // p1 + P01 (TempRow1(0) = P01) add (16) acc0.0<1>:w acc0.0<16;16,1>:w Q1 add (16) acc0.0<1>:w acc0.0<16;16,1>:w 2:w // p1 + P01 + q1 + 2 shr.sat (16) TempRow0B(0)<2> acc0.0<16;16,1>:w 2:w // >> 2 mov (16) NewP0 TempRow0B(0) // p0' endif Y_ENDIF3: // Compute q0', q1' and q2' //----------------------------------------------------------------------------- // bS = 4 Algorithm (cont): // // deltaq = (aq> 3; // q1' = ( q2 + q1 + q0 + p0 + 2) >> 2; // q2' = (2*q3 +3*q2 + q1 + q0 + p0 + 4) >> 3; // } else { // q0' = ( 2*q1 + q0 + p1 + 2) >> 2; // } // deltaq = ((abs)aq < beta) && gama // cmp.l.f0.1 (16) null:w (abs)aq(0) beta<0;1,0>:w // (abs)aq < beta ? // Common Q01 = q0 + q1 // add (16) Q0_plus_Q1(0)<1> Q0 Q1 // and (1) f0.1:w f0.1:uw CTemp1_W:w {NoMask} // deltaq = ((abs)ap < beta) && gama (f0.0) if (16) Y_ELSE4 // for channels its deltaq = true add (16) Q2_plus_Q3(0)<1> Q2 Q3 // A = (q1 + q0) + p0 = Q01 + p0 add (16) A(0)<1> Q0_plus_Q1(0) p0(0) // A = q1+q0 + p0 // Acc0 = A // B = q2 + q1 + q0 + p0 + 4 = q2 + A + 4 add (16) acc0.0<1>:w acc0.0<16;16,1>:w 4:w // q2 + 4 add (16) BB(0)<1> acc0.0<16;16,1>:w Q2 // B = q2 + A + 4 // Acc0 = B // q2' = (2*q3 +3*q2 + A + 4) >> 3 = (2*(q3+q2) + B) >> 3 // mov (16) acc0.0<1>:w BB(0) mac (16) acc0.0<1>:w Q2_plus_Q3(0) 2:w shr.sat (16) TempRow3B(0)<2> acc0.0<16;16,1>:w 3:w // q1' = (q2 + A + 2) >> 2 = (B - 2) >> 2 add (16) acc0.0<1>:w BB(0) -2:w shr.sat (16) TempRow1B(0)<2> acc0.0<16;16,1>:w 2:w // q0' = (q2 +2*A + p1 + 4) >> 3 = (B + A + p1) >> 3 add (16) acc0.0<1>:w p1(0) A(0) add (16) acc0.0<1>:w acc0.0<16;16,1>:w BB(0) shr.sat (16) TempRow0B(0)<2> acc0.0<16;16,1>:w 3:w mov (16) NewQ2 TempRow3B(0) // q2' mov (16) NewQ1 TempRow1B(0) // q1' mov (16) NewQ0 TempRow0B(0) // q0' Y_ELSE4: else (16) Y_ENDIF4 // for channels its deltaq = false // q0' = (2*q1 + q0 + p1 + 2) >> 2 = (q1 + Q01 + p1 + 2) >> 2 // Use original p1 values in p1(0) add (16) acc0.0<1>:w p1(0) Q0_plus_Q1(0) // p1 + P01 (TempRow1(0) = P01) add (16) acc0.0<1>:w acc0.0<16;16,1>:w Q1 add (16) acc0.0<1>:w acc0.0<16;16,1>:w 2:w // p1 + P01 + q1 + 2 shr.sat (16) TempRow0B(0)<2> acc0.0<16;16,1>:w 2:w // >> 2 mov (16) NewQ0 TempRow0B(0) // q0' endif Y_ENDIF4: // Done with bS = 4 algorithm Y_ELSE2: else (16) Y_ENDIF2 // For channels whose edge control map2 = 0 ---> bS < 4 algorithm //----------------------------------------------------------------------------- // bS < 4 Algorithm : // tc = tc0 + (|p2-p0|> 3)) // p0' = Clip1(p0 + delta) = Clip3(0, 0xFF, p0 + delta) // q0' = Clip1(q0 - delta) = Clip3(0, 0xFF, q0 - delta) // if (|p2-p0|>1) - (p1<<1)) >> 1 ) // if (|q2-q0|>1) - (q1<<1)) >> 1 ) //----------------------------------------------------------------------------- // Expand tc0 mov (16) tc_exp(0)<1> tc0<1;4,0>:ub {NoMask} mov (16) tc0_exp(0)<1> tc0<1;4,0>:ub {NoMask} // tc0_exp = tc0, each tc0 is duplicated 4 times for 4 adjcent 4 pixels // tc_exp = tc0_exp + (|p2-p0| tc0_exp(0) // tc = tc0_exp first cmp.l.f0.0 (16) null:w (abs)ap(0) beta:w // |p2-p0|< Beta ? ---> (abs)ap < Beta ? cmp.l.f0.1 (16) null:w (abs)aq(0) beta:w // |q2-q0|< Beta ? ---> (abs)aq < Beta ? //--- Use free cycles here --- // delta = Clip3(-tc, tc, ((((q0-p0)<<2) + (p1-q1) + 4) >> 3)) // 4 * (q0-p0) + p1 - q1 + 4 add (16) acc0<1>:w P1 4:w // p1 + 4 mac (16) acc0<1>:w q0_p0(0) 4:w // 4 * (q0-p0) + p1 + 4 add (16) acc0<1>:w acc0<16;16,1>:w -Q1 // 4 * (q0-p0) + p1 - q1 + 4 shr (16) TempRow0(0)<1> acc0<16;16,1>:w 3:w // Continue on getting tc_exp (f0.0) add (16) tc_exp(0)<1> tc_exp(0) 1:w // tc0_exp + (|p2-p0|:w f0.0<2;2,1>:w {NoMask} // Save |p2-p0| tc_exp(0) 1:w // tc_exp = tc0_exp + (|p2-p0| tc cmp.l.f0.1 (16) null:w TempRow0(0) -tc_exp(0) // Clip if delta' < -tc //--- Use free cycles here --- // common = (p0+q0+1) >> 1 ---> TempRow2(0) // Same as avg of p0 and q0 avg (16) TempRow2(0)<1> P0 Q0 // Continue on cliping tc to get delta (f0.0) mov (16) TempRow0(0)<1> tc_exp(0) (f0.1) mov (16) TempRow0(0)<1> -tc_exp(0) //--- Use free cycles here --- mov (2) f0.0<1>:w CTemp1_W<2;2,1>:w {NoMask} // CTemp1_W = (|p2-p0| P0 TempRow0(0) // p0+delta add.sat (16) TempRow0B(0)<2> Q0 -TempRow0(0) // q0-delta mov (16) NewP0 TempRow1B(0) // p0' mov (16) NewQ0 TempRow0B(0) // q0' //----------------------------------------------------------------------- // Now compute p1' and q1' // if (|p2-p0|> 1 = (p2 + common - (p1*2)) >> 1 add (16) acc0<1>:w P2 TempRow2(0) // TempRow2(0) = common = (p0+q0+1) >> 1 mac (16) acc0<1>:w P1 -2:w shr (16) TempRow1(0)<1> acc0<16;16,1>:w 1:w // tc clip to get tc_adj cmp.g.f0.0 (16) null:w TempRow1(0) tc0_exp(0) // Clip if delta' > tc cmp.l.f0.1 (16) null:w TempRow1(0) -tc0_exp(0) // Clip if delta' < -tc (f0.0) mov (16) TempRow1(0)<1> tc0_exp(0) (f0.1) mov (16) TempRow1(0)<1> -tc0_exp(0) //--- Use free cycles here --- mov (1) f0.1:w CTemp2_W:w {NoMask} // CTemp2_W = (|q2-q0| P1 TempRow1(0) // p1+tc_adj mov (16) NewP1 TempRow1B(0) // p1' //------------------------------------------------------------------------ Y_ENDIF6: endif // if (|q2-q0|> 1 // same as q2 + common - (q1 * 2) add (16) acc0<1>:w Q2 TempRow2(0) mac (16) acc0<1>:w Q1 -2:w shr (16) TempRow1(0)<1> acc0<16;16,1>:w 1:w // tc clip to get tc_adj cmp.g.f0.0 (16) null:w TempRow1(0) tc0_exp(0) // Clip if delta' > tc cmp.l.f0.1 (16) null:w TempRow1(0) -tc0_exp(0) // Clip if delta' < -tc (f0.0) mov (16) TempRow1(0)<1> tc0_exp(0) (f0.1) mov (16) TempRow1(0)<1> -tc0_exp(0) // q1' = q1 + tc_adj add.sat (16) TempRow1B(0)<2> Q1 TempRow1(0) // q1+tc_adj mov (16) NewQ1 TempRow1B(0) // q1' //------------------------------------------------------------------------ Y_ENDIF7: endif endif Y_ENDIF2: Y_ENDIF1: endif RETURN #endif // !defined(__AVC_ILDB_LUMA_CORE__) intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Luma_Core_Mbaff.asm000066400000000000000000000335711231401140700246640ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__AVC_ILDB_LUMA_CORE_MBAFF__) // Make sure this file is only included once #define __AVC_ILDB_LUMA_CORE_MBAFF__ ////////// AVC ILDB Luma Core Mbaff ///////////////////////////////////////////////////////////////////////////////// // // This core performs AVC LUMA ILDB filtering on one horizontal edge (16 pixels) of a MB. // If data is transposed, it can also de-block a vertical edge. // // Bafore calling this subroutine, caller needs to set the following parameters. // // - EdgeCntlMap1 // Edge control map A // - EdgeCntlMap2 // Edge control map B // - P_AddrReg // Src and dest address register for P pixels // - Q_AddrReg // Src and dest address register for Q pixels // - alpha // alpha corresponding to the edge to be filtered // - beta // beta corresponding to the edge to be filtered // - tc0 // tc0 corresponding to the edge to be filtered // // // +----+----+----+----+----+----+----+----+ // | p3 | p2 | P1 | p0 | q0 | q1 | q2 | q3 | // +----+----+----+----+----+----+----+----+ // // p3 = r[P_AddrReg, 0]<16;16,1> // p2 = r[P_AddrReg, 16]<16;16,1> // p1 = r[P_AddrReg, 32]<16;16,1> // p0 = r[P_AddrReg, 48]<16;16,1> // q0 = r[Q_AddrReg, 0]<16;16,1> // q1 = r[Q_AddrReg, 16]<16;16,1> // q2 = r[Q_AddrReg, 32]<16;16,1> // q3 = r[Q_AddrReg, 48]<16;16,1> // ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // The region is both src and dest // P0-P3 and Q0-Q3 should be only used if they have not been modified to new values #undef P3 #undef P2 #undef P1 #undef P0 #undef Q0 #undef Q1 #undef Q2 #undef Q3 #define P3 r[P_AddrReg, 0]<16;16,1>:ub #define P2 r[P_AddrReg, 16]<16;16,1>:ub #define P1 r[P_AddrReg, 32]<16;16,1>:ub #define P0 r[P_AddrReg, 48]<16;16,1>:ub #define Q0 r[Q_AddrReg, 0]<16;16,1>:ub #define Q1 r[Q_AddrReg, 16]<16;16,1>:ub #define Q2 r[Q_AddrReg, 32]<16;16,1>:ub #define Q3 r[Q_AddrReg, 48]<16;16,1>:ub // New region as dest #undef NewP2 #undef NewP1 #undef NewP0 #undef NewQ0 #undef NewQ1 #undef NewQ2 #define NewP2 r[P_AddrReg, 16]<1>:ub #define NewP1 r[P_AddrReg, 32]<1>:ub #define NewP0 r[P_AddrReg, 48]<1>:ub #define NewQ0 r[Q_AddrReg, 0]<1>:ub #define NewQ1 r[Q_AddrReg, 16]<1>:ub #define NewQ2 r[Q_AddrReg, 32]<1>:ub // Filter one luma edge - mbaff FILTER_Y_MBAFF: #if defined(_DEBUG) mov (1) EntrySignatureC:w 0x1111:w #endif //---------- Derive filterSampleflag in AVC spec, equition (8-469) ---------- // bS is in MaskA // Src copy of the p3, p2, p1, p0, q0, q1, q2, q3 // mov (16) p0123_W(0)<1> r[P_AddrReg]<16;16,1>:uw // mov (16) p0123_W(1)<1> r[P_AddrReg, 32]<16;16,1>:uw // mov (16) q0123_W(0)<1> r[Q_AddrReg]<16;16,1>:uw // mov (16) q0123_W(1)<1> r[Q_AddrReg, 32]<16;16,1>:uw // Move MaskA and MaskB to flag regs mov (2) f0.0<1>:uw MaskA<2;2,1>:uw add (16) q0_p0(0)<1> Q0 -P0 // q0-p0 add (16) TempRow0(0)<1> P1 -P0 // p1-p0 add (16) TempRow1(0)<1> Q1 -Q0 // q1-q0 // abs(q0-p0) < alpha (f0.0) cmp.l.f0.0 (16) null:w (abs)q0_p0(0) Mbaff_ALPHA(0) // abs(p1-p0) < Beta (f0.0) cmp.l.f0.0 (16) null:w (abs)TempRow0(0) Mbaff_BETA(0) // abs(q1-q0) < Beta (f0.0) cmp.l.f0.0 (16) null:w (abs)TempRow1(0) Mbaff_BETA(0) //----------------------------------------------------------------------------------------- (f0.0) if (16) MBAFF_Y_ENDIF1 // For channels whose edge control map1 = 1 ---> perform de-blocking // mov (1) f0.1:uw MaskB:uw {NoMask} // Now check for which algorithm to apply // (abs)ap = |p2-p0| add (16) ap(0)<1> P2 -P0 // (abs)aq = |q2-q0| add (16) aq(0)<1> Q2 -Q0 // Make a copy of unmodified p0 and p1 for use in q0'and q1' calculation mov (16) p0123_W(1)<1> r[P_AddrReg, 32]<16;16,1>:uw {NoMask} (f0.1) if (16) MBAFF_Y_ELSE2 // For channels whose edge control map2 = 1 ---> bS = 4 algorithm // Compute q0', q1' and q2' //----------------------------------------------------------------------------- // bS = 4 Algorithm : // // gama = |p0-q0| < ((alpha >> 2) + 2) // deltap = (ap> 3; // p1' = ( p2 + p1 + p0 + q0 + 2) >> 2; // p2' = (2*p3 +3*p2 + p1 + p0 + q0 + 4) >> 3; // } else { // p0' = ( 2*p1 + p0 + q1 + 2) >> 2; // } //----------------------------------------------------------------------------- // gama = |p0-q0| < ((alpha >> 2) + 2) = |p0-q0| < alpha2 cmp.l.f0.1 (16) null:w (abs)q0_p0(0) Mbaff_ALPHA2(0) // Common P01 = p0 + p1 add (16) P0_plus_P1(0)<1> P0 P1 // Common Q01 = q0 + q1 add (16) Q0_plus_Q1(0)<1> Q0 Q1 mov (1) f0.0:uw f0.1:uw {NoMask} // deltap = ((abs)ap < beta) && gama (f0.1) cmp.l.f0.1 (16) null:w (abs)ap(0) Mbaff_BETA(0) // (abs)ap < beta ? // deltaq = ((abs)aq < beta) && gama (f0.0) cmp.l.f0.0 (16) null:w (abs)aq(0) Mbaff_BETA(0) // (abs)aq < beta ? (f0.1) if (16) MBAFF_Y_ELSE3 // for channels its deltap = true add (16) P2_plus_P3(0)<1> P2 P3 // A = p1 + p0 + q0 = P01 + q0 add (16) A(0)<1> P0_plus_P1(0) Q0 // A = P01 + q0 // Now acc0 = A // B = p2 + p1 + p0 + q0 + 4 = p2 + A + 4 add (16) acc0.0<1>:w acc0.0<16;16,1>:w 4:w // p2 + 4 add (16) BB(0)<1> acc0.0<16;16,1>:w P2 // B = p2 + A + 4 // Now acc0 = B // p2' = (2*p3 +3*p2 + A + 4) >> 3 = (2*(p3+p2) + B) >> 3 mac (16) acc0.0<1>:w P2_plus_P3(0) 2:w shr.sat (16) TempRow3B(0)<2> acc0.0<16;16,1>:w 3:w // p1' = (p2 + A + 2) >> 2 = (B - 2) >> 2 add (16) acc0.0<1>:w BB(0) -2:w shr.sat (16) TempRow1B(0)<2> acc0.0<16;16,1>:w 2:w // p0' = (p2 +2*A + q1 + 4) >> 3 = (B + A + q1) >> 3 add (16) acc0.0<1>:w Q1 A(0) // B + A add (16) acc0.0<1>:w acc0.0<16;16,1>:w BB(0) // B + A + q1 shr.sat (16) TempRow0B(0)<2> acc0.0<16;16,1>:w 3:w // (B + A + q1) >> 3 mov (16) NewP2 TempRow3B(0) // p2' mov (16) NewP1 TempRow1B(0) // p1' mov (16) NewP0 TempRow0B(0) // p0' MBAFF_Y_ELSE3: else (16) MBAFF_Y_ENDIF3 // for channels its deltap = false // p0' = (2*p1 + p0 + q1 + 2) >> 2 = (p1 + P01 + q1 + 2) >> 2 add (16) acc0.0<1>:w P1 P0_plus_P1(0) // p1 + P01 (TempRow1(0) = P01) add (16) acc0.0<1>:w acc0.0<16;16,1>:w Q1 add (16) acc0.0<1>:w acc0.0<16;16,1>:w 2:w // p1 + P01 + q1 + 2 shr.sat (16) TempRow0B(0)<2> acc0.0<16;16,1>:w 2:w // >> 2 mov (16) NewP0 TempRow0B(0) // p0' endif MBAFF_Y_ENDIF3: // Compute q0', q1' and q2' //----------------------------------------------------------------------------- // bS = 4 Algorithm (cont): // // deltaq = (aq> 3; // q1' = ( q2 + q1 + q0 + p0 + 2) >> 2; // q2' = (2*q3 +3*q2 + q1 + q0 + p0 + 4) >> 3; // } else { // q0' = ( 2*q1 + q0 + p1 + 2) >> 2; // } (f0.0) if (16) MBAFF_Y_ELSE4 // for channels its deltaq = true add (16) Q2_plus_Q3(0)<1> Q2 Q3 // A = q1 + q0 + p0 = Q01 + p0 add (16) A(0)<1> Q0_plus_Q1(0) p0(0) // A = q1+q0 + p0 // B = q2 + q1 + q0 + p0 + 4 = q2 + A + 4 add (16) acc0.0<1>:w acc0.0<16;16,1>:w 4:w // q2 + 4 add (16) BB(0)<1> acc0.0<16;16,1>:w Q2 // B = q2 + A + 4 // Acc0 = B // q2' = (2*q3 +3*q2 + A + 4) >> 3 = (2*(q3+q2) + B) >> 3 mac (16) acc0.0<1>:w Q2_plus_Q3(0) 2:w shr.sat (16) TempRow3B(0)<2> acc0.0<16;16,1>:w 3:w // q1' = (q2 + A + 2) >> 2 = (B - 2) >> 2 add (16) acc0.0<1>:w BB(0) -2:w shr.sat (16) TempRow1B(0)<2> acc0.0<16;16,1>:w 2:w // q0' = (q2 +2*A + p1 + 4) >> 3 = (B + A + p1) >> 3 add (16) acc0.0<1>:w p1(0) A(0) add (16) acc0.0<1>:w acc0.0<16;16,1>:w BB(0) shr.sat (16) TempRow0B(0)<2> acc0.0<16;16,1>:w 3:w mov (16) NewQ2 TempRow3B(0) // q2' mov (16) NewQ1 TempRow1B(0) // q1' mov (16) NewQ0 TempRow0B(0) // q0' MBAFF_Y_ELSE4: else (16) MBAFF_Y_ENDIF4 // for channels its deltaq = false // q0' = (2*q1 + q0 + p1 + 2) >> 2 = (q1 + Q01 + p1 + 2) >> 2 // Use original p1 values in p1(0) add (16) acc0.0<1>:w p1(0) Q0_plus_Q1(0) // p1 + P01 (TempRow1(0) = P01) add (16) acc0.0<1>:w acc0.0<16;16,1>:w Q1 add (16) acc0.0<1>:w acc0.0<16;16,1>:w 2:w // p1 + P01 + q1 + 2 shr.sat (16) TempRow0B(0)<2> acc0.0<16;16,1>:w 2:w // >> 2 mov (16) NewQ0 TempRow0B(0) // q0' endif MBAFF_Y_ENDIF4: // Done with bS = 4 algorithm MBAFF_Y_ELSE2: else (16) MBAFF_Y_ENDIF2 // For channels whose edge control map2 = 0 ---> bS < 4 algorithm //----------------------------------------------------------------------------- // bS < 4 Algorithm : // tc = tc0 + (|p2-p0|> 3)) // p0' = Clip1(p0 + delta) = Clip3(0, 0xFF, p0 + delta) // q0' = Clip1(q0 - delta) = Clip3(0, 0xFF, q0 - delta) // if (|p2-p0|>1) - (p1<<1)) >> 1 ) // if (|q2-q0|>1) - (q1<<1)) >> 1 ) //----------------------------------------------------------------------------- mov (16) tc_exp(0)<1> Mbaff_TC0(0) // tc = tc0_exp first cmp.l.f0.0 (16) null:w (abs)ap(0) Mbaff_BETA(0) // |p2-p0|> 3)) // 4 * (q0-p0) + p1 - q1 + 4 add (16) acc0<1>:w P1 4:w // p1 + 4 mac (16) acc0<1>:w q0_p0(0) 4:w // 4 * (q0-p0) + p1 + 4 add (16) acc0<1>:w acc0<16;16,1>:w -Q1 // 4 * (q0-p0) + p1 - q1 + 4 shr (16) TempRow0(0)<1> acc0<16;16,1>:w 3:w // Continue on getting tc_exp (f0.0) add (16) tc_exp(0)<1> tc_exp(0) 1:w // tc0_exp + (|p2-p0|:w f0.0<2;2,1>:w {NoMask} // Save |p2-p0| tc_exp(0) 1:w // tc_exp = tc0_exp + (|p2-p0| tc cmp.l.f0.1 (16) null:w TempRow0(0) -tc_exp(0) // Clip if delta' < -tc //--- Use free cycles here --- // common = (p0+q0+1) >> 1 ---> TempRow2(0) // Same as avg of p0 and q0 avg (16) TempRow2(0)<1> P0 Q0 // Continue on cliping tc to get delta (f0.0) mov (16) TempRow0(0)<1> tc_exp(0) (f0.1) mov (16) TempRow0(0)<1> -tc_exp(0) //--- Use free cycles here --- mov (2) f0.0<1>:w CTemp1_W<2;2,1>:w {NoMask} // CTemp1_W = (|p2-p0| P0 TempRow0(0) // p0+delta add.sat (16) TempRow0B(0)<2> Q0 -TempRow0(0) // q0-delta mov (16) NewP0 TempRow1B(0) // p0' mov (16) NewQ0 TempRow0B(0) // q0' //----------------------------------------------------------------------- // Now compute p1' and q1' // if (|p2-p0|> 1 = (p2 + common - (p1*2)) >> 1 add (16) acc0<1>:w P2 TempRow2(0) // TempRow2(0) = common = (p0+q0+1) >> 1 mac (16) acc0<1>:w P1 -2:w shr (16) TempRow1(0)<1> acc0<16;16,1>:w 1:w // tc clip to get tc_adj cmp.g.f0.0 (16) null:w TempRow1(0) Mbaff_TC0(0) // Clip if delta' > tc cmp.l.f0.1 (16) null:w TempRow1(0) -Mbaff_TC0(0) // Clip if delta' < -tc (f0.0) mov (16) TempRow1(0)<1> Mbaff_TC0(0) (f0.1) mov (16) TempRow1(0)<1> -Mbaff_TC0(0) //--- Use free cycles here --- mov (1) f0.1:w CTemp2_W:w {NoMask} // CTemp2_W = (|q2-q0| P1 TempRow1(0) // p1+tc_adj mov (16) NewP1 TempRow1B(0) // p1' //------------------------------------------------------------------------ MBAFF_Y_ENDIF6: endif // if (|q2-q0|> 1 // same as q2 + common - (q1 * 2) add (16) acc0<1>:w Q2 TempRow2(0) mac (16) acc0<1>:w Q1 -2:w shr (16) TempRow1(0)<1> acc0<16;16,1>:w 1:w // tc clip to get tc_adj cmp.g.f0.0 (16) null:w TempRow1(0) Mbaff_TC0(0) // Clip if delta' > tc cmp.l.f0.1 (16) null:w TempRow1(0) -Mbaff_TC0(0) // Clip if delta' < -tc (f0.0) mov (16) TempRow1(0)<1> Mbaff_TC0(0) (f0.1) mov (16) TempRow1(0)<1> -Mbaff_TC0(0) // q1' = q1 + tc_adj add.sat (16) TempRow1B(0)<2> Q1 TempRow1(0) // q1+tc_adj mov (16) NewQ1 TempRow1B(0) // q1' //------------------------------------------------------------------------ MBAFF_Y_ENDIF7: endif endif MBAFF_Y_ENDIF2: MBAFF_Y_ENDIF1: endif RETURN #endif // !defined(__AVC_ILDB_LUMA_CORE_MBAFF__) intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_OpenGateway.asm000066400000000000000000000031671231401140700241440ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //----- Open a Message Gateway ----- // The parent thread is the recipient thread #if defined(_DEBUG) mov (1) EntrySignature:w 0x1111:w #endif mov (8) GatewayPayload<1>:ud r0.0<8;8,1>:ud // Init payload to r0 // r50- (16 GRFs) are the GRFs child thread can wtite to. // Reg base is at bit 28:21, Gateway size is at [bit 10:8] // r6: 6 = 00000110 //000 00000110 0000000000 100 00000000 ==> 0000 0000 1100 0000 0000 0100 0000 0000 mov (1) RegBase_GatewaySize:ud 0x00C00400:ud // Reg base + Gateway size (16 GRFs) //000 00110010 0000000000 100 00000000 ==> 0000 0110 0100 0000 0000 0100 0000 0000 //mov (1) RegBase_GatewaySize:ud 0x06400400:ud // Reg base (r50 = 0x640 byte offset) + Gateway size (16 GRFs) //mov (1) DispatchID:ub r0.20:ub // Dispatch ID mov (1) GatewayPayloadKey:uw 0x1212:uw // Key=0x1212 // Message descriptor // bit 31 EOD // 27:24 FFID = 0x0011 for msg gateway // 23:20 msg length = 1 MRF // 19:16 Response length = 0 // 14 AckReg = 1 // 1:0 SubFuncID = 00 for OpenGateway // Message descriptor: 0 000 0011 0001 0000 + 0 1 000000000000 00 ==> 0000 0011 0001 0000 0100 0000 0000 0000 // Send message to gateway: the ack message is put into response GRF r49 ==> Good for debugging send (8) GatewayResponse:ud m7 GatewayPayload<8;8,1>:ud MSG_GW OGWMSGDSC //----- End of Open a Message Gateway ----- intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Root_Field_UV.asm000066400000000000000000000004501231401140700243510ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #include "AVC_ILDB_Root_UV.asm" intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Root_Field_Y.asm000066400000000000000000000004471231401140700242350ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #include "AVC_ILDB_Root_Y.asm" intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Root_Mbaff_UV.asm000066400000000000000000000114461231401140700243500ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ///////////////////////////////////////////////////////////////////////////////////// // Kernel name: AVC_ILDB_Root_Mbaff.asm // // Root kernel serves as a scheduler for child threads. // // // ***** Note ***** // Initial design bundle MB pair for each thread, and share AVC_ILDB_MB_Dep_Check.asm // with non mbaff kernels. // // Optimization will be done later, putting top and bottom MBs on separate threads. // // ///////////////////////////////////////////////////////////////////////////////////// // // $Revision: 1 $ // $Date: 10/19/06 5:06p $ // // ---------------------------------------------------- // AVC_ILDB_ROOT_MBAFF_UV // ---------------------------------------------------- #define AVC_ILDB .kernel AVC_ILDB_ROOT_MBAFF_UV #if defined(COMBINED_KERNEL) ILDB_LABEL(AVC_ILDB_ROOT_UV): #endif #include "SetupVPKernel.asm" #include "AVC_ILDB.inc" #if defined(_DEBUG) ///////////////////////////////////////////////////////////////////////////////////// // Init URB space for running on RTL. It satisfies reading an unwritten URB entries. // Will remove it for production release. //mov (8) m1:ud 0x11111111:ud //mov (8) m2:ud 0x22222222:ud //mov (8) m3:ud 0x33333333:ud //mov (8) m4:ud 0x44444444:ud //mov (1) Temp1_W:w 0:w //ILDB_INIT_URB: //mul (1) URBOffset:w Temp1_W:w 4:w //shl (1) URBWriteMsgDescLow:uw URBOffset:w 4:w // Msg descriptor: URB write dest offset (9:4) //mov (1) URBWriteMsgDescHigh:uw 0x0650:uw // Msg descriptor: URB write 5 MRFs (m0 - m4) //#include "writeURB.asm" //add (1) Temp1_W:w Temp1_W:w 1:w // Increase block count //cmp.l.f0.0 (1) null Temp1_W:w MBsCntY:w // Check the block count limit //(f0.0) jmpi ILDB_INIT_URB // Loop back ///////////////////////////////////////////////////////////////////////////////////// mov (1) EntrySignature:w 0xEFF0:w #endif //---------------------------------------------------------------------------------------------------------------- // Set global variable mov (32) ChildParam:uw 0:uw // Reset local variables //mul (1) TotalBlocks:w MBsCntX:w MBsCntY:w // Total # of MB pairs //add (1) GatewayApertureE:w MBsCntY:w GatewayApertureB:w // Aperture End = aperture Head + BlockCntY // 2 URB entries for Y: // Entry 0 - Child thread R0Hdr // Entry 1 - input parameter to child kernel (child r1) #define URB_ENTRIES_PER_MB 2 // URB_ENTRIES_PER_MB in differnt form, the final desired format is (URB_ENTRIES_PER_MB-1) << 10 mov (1) URB_EntriesPerMB_2:w URB_ENTRIES_PER_MB-1:w shl (1) URB_EntriesPerMB_2:w URB_EntriesPerMB_2:w 10:w #define CHROMA_ROOT // Compiling flag for chroma only //mul (1) URBOffsetUVBase:w MBsCntY:w URB_ENTRIES_PER_MB:w // Right after Y entries // URB base for UV kernels #if defined(DEV_CL) mov (1) URBOffsetUVBase:w 240:w #else mov (1) URBOffsetUVBase:w 320:w #endif mov (1) ChildThreadsID:uw 3:uw shr (1) ThreadLimit:w MaxThreads:w 1:w // Initial luma thread limit to 50% mul (1) TotalBlocks:w MBsCntX:w MBsCntY:w // MBs to be processed count down from TotalBlocks //***** Init CT_R0Hdr fields that are common to all threads ************************* mov (8) CT_R0Hdr.0:ud r0.0<8;8,1>:ud // Init to root R0 header mov (1) CT_R0Hdr.7:ud r0.6:ud // Copy Parent Thread Cnt; JJ did the change on 06/20/2006 mov (1) CT_R0Hdr.31:ub 0:w // Reset the highest byte mov (1) CT_R0Hdr.3:ud 0x00000000 mov (1) CT_R0Hdr.6:uw sr0.0:uw // sr0.0: state reg contains general thread states, e.g. EUID/TID. //***** Init ChildParam fields that are common to all threads *********************** mov (8) ChildParam<1>:ud RootParam<8;8,1>:ud // Copy all root parameters mov (4) CurCol<1>:w 0:w // Reset CurCol, CurRow add (2) LastCol<1>:w MBsCntX<2;2,1>:w -1:w // Get LastCol and LastRow mov (1) URBWriteMsgDesc:ud MSG_LEN(2)+URBWMSGDSC:ud //=================================================================================== #include "AVC_ILDB_OpenGateway.asm" // Open root thread gateway for receiving notification #include "AVC_ILDB_Dep_Check.asm" // Check dependency and spawn all MBs //#include "AVC_ILDB_UpdateThrdLimit.asm" // Update thread limit in luma root thread via gateway #include "AVC_ILDB_CloseGateway.asm" // Close root thread gateway // Chroma root EOT = child send EOT : Request type = 1 END_CHILD_THREAD #undef CHROMA_ROOT #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Root_Mbaff_Y.asm000066400000000000000000000117411231401140700242240ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ///////////////////////////////////////////////////////////////////////////////////// // Kernel name: AVC_ILDB_Root_Mbaff.asm // // Root kernel serves as a scheduler for child threads. // // // ***** Note ***** // Initial design bundle MB pair for each thread, and share AVC_ILDB_MB_Dep_Check.asm // with non mbaff kernels. // // Optimization will be done later, putting top and bottom MBs on separate threads. // // ///////////////////////////////////////////////////////////////////////////////////// // // $Revision: 1 $ // $Date: 10/19/06 5:06p $ // // ---------------------------------------------------- // AVC_ILDB_ROOT_MBAFF_Y // ---------------------------------------------------- #define AVC_ILDB .kernel AVC_ILDB_ROOT_MBAFF_Y #if defined(COMBINED_KERNEL) ILDB_LABEL(AVC_ILDB_ROOT_Y): #endif #include "SetupVPKernel.asm" #include "AVC_ILDB.inc" #if defined(_DEBUG) ///////////////////////////////////////////////////////////////////////////////////// // Init URB space for running on RTL. It satisfies reading an unwritten URB entries. // Will remove it for production release. //mov (8) m1:ud 0x11111111:ud //mov (8) m2:ud 0x22222222:ud //mov (8) m3:ud 0x33333333:ud //mov (8) m4:ud 0x44444444:ud //mov (1) Temp1_W:w 0:w //ILDB_INIT_URB: //mul (1) URBOffset:w Temp1_W:w 4:w //shl (1) URBWriteMsgDescLow:uw URBOffset:w 4:w // Msg descriptor: URB write dest offset (9:4) //mov (1) URBWriteMsgDescHigh:uw 0x0650:uw // Msg descriptor: URB write 5 MRFs (m0 - m4) //#include "writeURB.asm" //add (1) Temp1_W:w Temp1_W:w 1:w // Increase block count //cmp.l.f0.0 (1) null Temp1_W:w MBsCntY:w // Check the block count limit //(f0.0) jmpi ILDB_INIT_URB // Loop back ///////////////////////////////////////////////////////////////////////////////////// mov (1) EntrySignature:w 0xEFF0:w #endif //---------------------------------------------------------------------------------------------------------------- // Set global variable mov (32) ChildParam:uw 0:uw // Reset local variables //mul (1) TotalBlocks:w MBsCntX:w MBsCntY:w // Total # of MB pairs //add (1) GatewayApertureE:w MBsCntY:w GatewayApertureB:w // Aperture End = aperture Head + BlockCntY // 2 URB entries for Y: // Entry 0 - Child thread R0Hdr // Entry 1 - input parameter to child kernel (child r1) #undef URB_ENTRIES_PER_MB #define URB_ENTRIES_PER_MB 2 // URB_ENTRIES_PER_MB in differnt form, the final desired format is (URB_ENTRIES_PER_MB-1) << 10 mov (1) URB_EntriesPerMB_2:w URB_ENTRIES_PER_MB-1:w shl (1) URB_EntriesPerMB_2:w URB_EntriesPerMB_2:w 10:w mov (1) ChildThreadsID:uw 1:uw // ChildThreadsID for chroma root shr (1) ThreadLimit:w MaxThreads:w 1:w // Initial luma thread limit to 50% mul (1) TotalBlocks:w MBsCntX:w MBsCntY:w // MBs to be processed count down from TotalBlocks //***** Init CT_R0Hdr fields that are common to all threads ************************* mov (8) CT_R0Hdr.0:ud r0.0<8;8,1>:ud // Init to root R0 header mov (1) CT_R0Hdr.7:ud r0.6:ud // Copy Parent Thread Cnt; JJ did the change on 06/20/2006 mov (1) CT_R0Hdr.31:ub 0:w // Reset the highest byte mov (1) CT_R0Hdr.3:ud 0x00000000 mov (1) CT_R0Hdr.6:uw sr0.0:uw // sr0.0: state reg contains general thread states, e.g. EUID/TID. //***** Init ChildParam fields that are common to all threads *********************** mov (8) ChildParam<1>:ud RootParam<8;8,1>:ud // Copy all root parameters mov (4) CurCol<1>:w 0:w // Reset CurCol, CurRow add (2) LastCol<1>:w MBsCntX<2;2,1>:w -1:w // Get LastCol and LastRow mov (1) URBWriteMsgDesc:ud MSG_LEN(2)+URBWMSGDSC:ud //=================================================================================== #include "AVC_ILDB_OpenGateway.asm" // Open root thread gateway for receiving notification #if defined(DEV_CL) mov (1) URBOffset:uw 240:uw // Use chroma URB offset to spawn chroma root #else mov (1) URBOffset:uw 320:uw // Use chroma URB offset to spawn chroma root #endif #include "AVC_ILDB_SpawnChromaRoot.asm" // Spawn chroma root mov (1) URBOffset:uw 0:uw // Use luma URB offset to spawn luma child mov (1) ChildThreadsID:uw 2:uw // Starting ChildThreadsID for luma child threads #include "AVC_ILDB_Dep_Check.asm" // Check dependency and spawn all MBs // Wait for UV root thread to finish ILDB_LABEL(WAIT_FOR_UV): cmp.l.f0.0 (1) null:w ThreadLimit:w MaxThreads:w (f0.0) jmpi ILDB_LABEL(WAIT_FOR_UV) #include "AVC_ILDB_CloseGateway.asm" // Close root thread gateway END_THREAD // End of root thread #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Root_UV.asm000066400000000000000000000105261231401140700232530ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: AVC_ILDB_Root_UV.asm // // Root kernel serves as a scheduler for child threads // // $Revision: 1 $ // $Date: 10/19/06 5:06p $ // // ---------------------------------------------------- // AVC_ILDB_ROOT_UV // ---------------------------------------------------- #define AVC_ILDB .kernel AVC_ILDB_ROOT_UV #if defined(COMBINED_KERNEL) ILDB_LABEL(AVC_ILDB_ROOT_UV): #endif #include "SetupVPKernel.asm" #include "AVC_ILDB.inc" #if defined(_DEBUG) mov (1) EntrySignature:w 0xFF11:w #endif ///////////////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) // Init URB space for running on RTL. It satisfies reading an unwritten URB entries. // Will remove it for production release. mov (8) m1:ud 0x55555555:ud mov (8) m2:ud 0x66666666:ud mov (8) m3:ud 0x77777777:ud mov (8) m4:ud 0x88888888:ud mov (1) Temp1_W:w MBsCntY:w shl (1) Temp2_W:w MBsCntY:w 1:w ILDB_LABEL(ILDB_INIT_URB_UV): mul (1) URBOffset:uw Temp1_W:uw 4:w // Each thread uses 4 URB entries (1 r0 + 1 inline + 2 data) mov (1) URBWriteMsgDesc:ud MSG_LEN(4)+URBWMSGDSC:ud // Msg descriptor: URB write msg length = 5 #include "writeURB.asm" add (1) Temp1_W:w Temp1_W:w 1:w // Increase block count cmp.l.f0.0 (1) null Temp1_W:w Temp2_W:w // Check the block count limit (f0.0) jmpi ILDB_LABEL(ILDB_INIT_URB_UV) // Loop back mov (1) EntrySignature:w 0xFFF0:w #endif ///////////////////////////////////////////////////////////////////////////////////// // Set global variable mov (32) ChildParam:uw 0:uw // Reset local variables, 2 GRFs //mul (1) TotalBlocks:w MBsCntX:w MBsCntY:w // Total # of blocks //add (1) GatewayApertureE:w MBsCntY:w GatewayApertureB:w // Aperture End = aperture Head + BlockCntY // 4 URB entries for Y: // Entry 0 - Child thread R0Hdr // Entry 1 - input parameter to child kernel (child r1) // Entry 2 - Prev MB data UV 2x8 // Entry 3 - Unused #define URB_ENTRIES_PER_MB 4 // URB_ENTRIES_PER_MB in differnt form, the final desired format is (URB_ENTRIES_PER_MB-1) << 10 mov (1) URB_EntriesPerMB_2:w URB_ENTRIES_PER_MB-1:w shl (1) URB_EntriesPerMB_2:w URB_EntriesPerMB_2:w 10:w #define CHROMA_ROOT // Compiling flag for chroma only // URB base for UV kernels #if defined(DEV_CL) mov (1) URBOffsetUVBase:w 240:w #else mov (1) URBOffsetUVBase:w 320:w #endif mov (1) ChildThreadsID:uw 3:uw shr (1) ThreadLimit:w MaxThreads:w 1:w // Initial luma thread limit to 50% mul (1) TotalBlocks:w MBsCntX:w MBsCntY:w // MBs to be processed count down from TotalBlocks //***** Init CT_R0Hdr fields that are common to all threads ************************* mov (8) CT_R0Hdr.0:ud r0.0<8;8,1>:ud // Init to root R0 header mov (1) CT_R0Hdr.7:ud r0.6:ud // Copy Parent Thread Cnt; JJ did the change on 06/20/2006 mov (1) CT_R0Hdr.31:ub 0:w // Reset the highest byte mov (1) CT_R0Hdr.3:ud 0x00000000 mov (1) CT_R0Hdr.6:uw sr0.0:uw // sr0.0: state reg contains general thread states, e.g. EUID/TID. //***** Init ChildParam fields that are common to all threads *********************** mov (8) ChildParam<1>:ud RootParam<8;8,1>:ud // Copy all root parameters mov (4) CurCol<1>:w 0:w // Reset CurCol, CurRow, add (2) LastCol<1>:w MBsCntX<2;2,1>:w -1:w // Get LastCol and LastRow mov (1) URBWriteMsgDesc:ud MSG_LEN(2)+URBWMSGDSC:ud //=================================================================================== #include "AVC_ILDB_OpenGateway.asm" // Open gateway for receiving notification #include "AVC_ILDB_Dep_Check.asm" // Check dependency and spawn all luma child threads in parallel with chroma root //#include "AVC_ILDB_LumaThrdLimit.asm" // Update thread limit in luma root thread via gateway #include "AVC_ILDB_CloseGateway.asm" // Close root thread gateway // Chroma root EOT = child send EOT : Request type = 1 END_CHILD_THREAD #undef CHROMA_ROOT #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Root_Y.asm000066400000000000000000000114661231401140700231350ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: AVC_ILDB_Root_Y.asm // // Root kernel serves as a scheduler for child threads // // $Revision: 1 $ // $Date: 10/19/06 5:06p $ // // ---------------------------------------------------- // AVC_ILDB_ROOT_Y // ---------------------------------------------------- #define AVC_ILDB .kernel AVC_ILDB_ROOT_Y #if defined(COMBINED_KERNEL) ILDB_LABEL(AVC_ILDB_ROOT_Y): #endif #include "SetupVPKernel.asm" #include "AVC_ILDB.inc" ///////////////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) // Init URB space for running on RTL. It satisfies reading an unwritten URB entries. // Will remove it for production release. mov (8) m1:ud 0x11111111:ud mov (8) m2:ud 0x22222222:ud mov (8) m3:ud 0x33333333:ud mov (8) m4:ud 0x44444444:ud mov (1) Temp1_W:w 0:w ILDB_LABEL(ILDB_INIT_URB_Y): //mul (1) Temp2_W:w Temp1_W:w 4:w // URBOffset //shl (1) URBWriteMsgDescLow:uw Temp2_W:w 4:w // Msg descriptor: URB write dest offset (9:4) //mov (1) URBWriteMsgDescHigh:uw 0x0650:uw // Msg descriptor: URB write 5 MRFs (m0 - m4) //mul (1) URBOffset:uw Temp1_W:uw 4:w // Each thread uses 4 URB entries (1 r0 + 1 inline + 2 data) mul (1) URBOffset:uw Temp1_W:uw 2:w // Each thread uses 2 URB entries (1 r0 + 1 inline) mov (1) URBWriteMsgDesc:ud MSG_LEN(2)+URBWMSGDSC:ud // Msg descriptor: URB write msg length = 3 #include "writeURB.asm" add (1) Temp1_W:w Temp1_W:w 1:w // Increase block count cmp.l.f0.0 (1) null Temp1_W:w MBsCntY:w // Check the block count limit (f0.0) jmpi ILDB_LABEL(ILDB_INIT_URB_Y) // Loop back mov (1) EntrySignature:w 0xFFF0:w #endif ///////////////////////////////////////////////////////////////////////////////////// // Set global variable mov (32) ChildParam:uw 0:uw // Reset local variables, 2 GRFs //mul (1) TotalBlocks:w MBsCntX:w MBsCntY:w // Total # of blocks //add (1) GatewayApertureE:w MBsCntY:w GatewayApertureB:w // Aperture End = aperture Head + BlockCntY // 4 URB entries for Y: // Entry 0 - Child thread R0Hdr // Entry 1 - input parameter to child kernel (child r1) // Entry 2 - Prev MB data Y 4x16, col 1 and col 0 // Entry 3 - Prev MB data Y 4x16, col 3 and col 2 #undef URB_ENTRIES_PER_MB #define URB_ENTRIES_PER_MB 4 // URB_ENTRIES_PER_MB in differnt form, the final desired format is (URB_ENTRIES_PER_MB-1) << 10 mov (1) URB_EntriesPerMB_2:w URB_ENTRIES_PER_MB-1:w shl (1) URB_EntriesPerMB_2:w URB_EntriesPerMB_2:w 10:w shr (1) ThreadLimit:w MaxThreads:w 1:w // Initial luma thread limit to 50% mul (1) TotalBlocks:w MBsCntX:w MBsCntY:w // MBs to be processed count down from TotalBlocks //***** Init CT_R0Hdr fields that are common to all threads ************************* mov (8) CT_R0Hdr.0:ud r0.0<8;8,1>:ud // Init to root R0 header mov (1) CT_R0Hdr.7:ud r0.6:ud // Copy Parent Thread Cnt; JJ did the change on 06/20/2006 mov (1) CT_R0Hdr.31:ub 0:w // Reset the highest byte mov (1) CT_R0Hdr.3:ud 0x00000000 mov (1) CT_R0Hdr.6:uw sr0.0:uw // sr0.0: state reg contains general thread states, e.g. EUID/TID. //***** Init ChildParam fields that are common to all threads *********************** mov (8) ChildParam<1>:ud RootParam<8;8,1>:ud // Copy all root parameters mov (4) CurCol<1>:w 0:w // Reset CurCol, CurRow, add (2) LastCol<1>:w MBsCntX<2;2,1>:w -1:w // Get LastCol and LastRow mov (1) URBWriteMsgDesc:ud MSG_LEN(2)+URBWMSGDSC:ud //=================================================================================== #include "AVC_ILDB_OpenGateway.asm" // Open gateway for receiving notification #if defined(DEV_CL) mov (1) URBOffset:uw 240:uw // Use chroma URB offset to spawn chroma root #else mov (1) URBOffset:uw 320:uw // Use chroma URB offset to spawn chroma root #endif #include "AVC_ILDB_SpawnChromaRoot.asm" // Spawn chroma root mov (1) URBOffset:uw 0:uw // Use luma URB offset to spawn luma child mov (1) ChildThreadsID:uw 2:uw // Starting ChildThreadsID for luma child threads #include "AVC_ILDB_Dep_Check.asm" // Check dependency and spawn all luma child threads in parallel with chroma root // Wait for UV root thread to finish ILDB_LABEL(WAIT_FOR_UV): cmp.l.f0.0 (1) null:w ThreadLimit:w MaxThreads:w (f0.0) jmpi ILDB_LABEL(WAIT_FOR_UV) #include "AVC_ILDB_CloseGateway.asm" // Close root thread gateway END_THREAD // End of root thread #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_Spawn.asm000066400000000000000000000014501231401140700230020ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //=============== Spawn a child thread for a vertical child =============== #if defined(_DEBUG) mov (1) EntrySignature:w 0x6666:w #endif mul (1) URBOffset:uw CurRow:uw 2:w // 5:w // Each row uses 5 URB entries (R0, child R0, 3 GRFs of data from left MB) mov (8) CT_R0Hdr.0:ud r0.0<8;8,1>:ud // Init to root R0 header // R0.2: Interface Discriptor Ptr. Add offset 16 for next Interface Discriptor for child kernel add (1) CT_R0Hdr.2:ud r0.2:ud IDesc_Child_Offset:w #include "AVC_ILDB_SpawnChild.asm" intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_SpawnChild.asm000066400000000000000000000035071231401140700237530ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //=============== Spawn a child thread for Luma or Chroma =============== //----- Create child thread R0 header ----- #if defined(_DEBUG) mov (1) EntrySignature:w 0xAAAA:w #endif //***** Set CT_R0Hdr fields that change for every thread // Restore CT_R0Hdr.4:ud to r0.4:ud mov (1) CT_R0Hdr.4:ud r0.4:ud // R0.2: Interface Discriptor Ptr. Add a child offset for child kernel // add (1) CT_R0Hdr.2:ud r0.2:ud CHILD_OFFSET:w // Assign a new Thread Count for this child mov (1) CT_R0Hdr.6:ud ChildThreadsID:uw //----- Prepare URB for launching a child thread ----- mov (16) m2.0:w ChildParam<16;16,1>:w shr (1) MRF0.0:uw URBOffset:uw 1:w add (1) ChildThreadsID:uw ChildThreadsID:uw 2:uw // Luma child=even, chroma child=odd //-------------------------------------------------- // #include "writeURB.asm" send null:uw MRF0 null:ud URBWRITE URBWriteMsgDesc:ud // URB write //-------------------------------------------------- // Set URB handle for child thread launching: // URB handle Length (bit 15:10) - 0000 0000 0000 0000 yyyy yy00 0000 0000 // URB handle offset (bit 9:0) - 0000 0000 0000 0000 0000 00xx xxxx xxxx or (1) CT_R0Hdr.4:ud URB_EntriesPerMB_2:w URBOffset:uw // 2 URB entries: // Entry 0 - CT_R0Hdr // Entry 1 - input parameter to child kernel //----- Spawn a child now ----- send (8) null:ud CT_R0Hdr null:ud TS TSMSGDSC // send (8) null:ud CT_Spawn_Reg null:ud 0x07100001 // Restore CT_R0Hdr.4:ud to r0.4:ud for next use // mov (1) CT_R0Hdr.4:ud r0.4:ud intel-driver-1.3.0/src/shaders/h264/ildb/AVC_ILDB_SpawnChromaRoot.asm000066400000000000000000000027351231401140700250070ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //=============== Spawn a chroma root thread =============== //----- Create chroma root thread R0 header ----- #if defined(_DEBUG) mov (1) EntrySignature:w 0xAABA:w #endif // Restore CT_R0Hdr.4:ud to r0.4:ud // mov (1) CT_R0Hdr.4:ud r0.4:ud // R0.2: Interface Discriptor Ptr. Add child offset for child kernel add (1) CT_R0Hdr.2:ud r0.2:ud CHROMA_ROOT_OFFSET:w // Assign a new Thread Count for this child mov (1) CT_R0Hdr.6:ud 1:w // ThreadID=1 for chroma root //----- Copy luma root r1 for launching chroma root thread ----- mov (16) m2.0:w RootParam<16;16,1>:w #include "writeURB.asm" //-------------------------------------------------- // Set URB handle for child thread launching: // URB handle Length (bit 15:10) - 0000 0000 0000 0000 yyyy yy00 0000 0000 // URB handle offset (bit 9:0) - 0000 0000 0000 0000 0000 00xx xxxx xxxx or (1) CT_R0Hdr.4:ud URB_EntriesPerMB_2:w URBOffset:uw // 2 URB entries: // Entry 0 - CT_R0Hdr // Entry 1 - input parameter to child kernel //----- Spawn a child now ----- send (8) null:ud CT_R0Hdr null:ud TS TSMSGDSC // Restore CT_R0Hdr.4:ud to r0.4:ud for next use mov (1) CT_R0Hdr.4:ud r0.4:ud intel-driver-1.3.0/src/shaders/h264/ildb/Child_Undefs.inc000066400000000000000000000010211231401140700227410ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: Child_Undefs.inc // // Undefine global symbols for new process in child thread // #undef P1 #undef P2 #undef P3 #undef P4 #undef P5 #undef P6 #undef P7 #undef P8 #undef EDGECNTLMAP #undef CLIP_NEGATIVE #undef CLIP_DONE intel-driver-1.3.0/src/shaders/h264/ildb/ILDB_header.inc000066400000000000000000000305741231401140700224530ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__ILDB_HEADER__) // Make sure this file is only included once #define __ILDB_HEADER__ // Module name: ILDB_header.inc // .default_execution_size (16) .default_register_type :ub #undef NULLREG #undef RETURN_REG #undef EOTMSGDSC #undef MSGSRC #undef END_THREAD #undef TSMSGDSC // ----------- Common constant definitions ------------ // // Bit position constants // #define BIT0 0x01 #define BIT1 0x02 #define BIT2 0x04 #define BIT3 0x08 #define BIT4 0x10 #define BIT5 0x20 #define BIT6 0x40 #define BIT7 0x80 #define BIT8 0x0100 #define BIT9 0x0200 #define BIT10 0x0400 #define BIT11 0x0800 #define BIT12 0x1000 #define BIT13 0x2000 #define BIT14 0x4000 #define BIT15 0x8000 #define BIT16 0x00010000 #define BIT17 0x00020000 #define BIT18 0x00040000 #define BIT19 0x00080000 #define BIT20 0x00100000 #define BIT21 0x00200000 #define BIT22 0x00400000 #define BIT23 0x00800000 #define BIT24 0x01000000 #define BIT25 0x02000000 #define BIT26 0x04000000 #define BIT27 0x08000000 #define BIT28 0x10000000 #define BIT29 0x20000000 #define BIT30 0x40000000 #define BIT31 0x80000000 // Common constants // #define INST_SIZE 16 // Instruction size in byte #define GRFWIB 32 // GRF register width in byte #define GRFWIW 16 // GRF register width in word #define GRFWID 8 // GRF register width in dword #define TOP_FIELD 0 #define BOTTOM_FIELD 1 #define PREVIOUS_FRAME 0 // Previous frame #define CURRENT_FRAME 1 // Current frame #define NEXT_FRAME 2 // Next frame #define Y_ROW_WIDTH 16 // in bytes #define UV_ROW_WIDTH 8 // Useful macros // #define REGION(Width,HStride) // Region definition when ExecSize = Width #define NULLREG null<1>:d #define NULLREGW null<1>:w #define RETURN_REG r62 // Return pointer for all sub-routine calls (type DWORD) #define CALL(subFunc, skipInst) add (1) RETURN_REG<1>:ud ip:ud (1+skipInst)*INST_SIZE \n\ jmpi (1) subFunc #define RETURN mov (1) ip:ud RETURN_REG<0;1,0>:ud // Return to calling module #define PRED_CALL(flag, subFunc, skipInst) add (1) RETURN_REG<1>:ud ip:ud (1+skipInst)*INST_SIZE \n\ (flag) jmpi (1) subFunc // Definitions for surface states, GRF regions, and common data fields // // Note: Each kernel needs to define a specific symbol before including this // header file to ensure correct definitions. // #if defined(AVC_ILDB) .reg_count_total 64 .reg_count_payload 4 // Binding Table Index #define BI_CNTRL_DATA 0 // Control data map #define BI_SRC_Y 1 #define BI_SRC_UV 2 #define BI_DEST_Y 3 #define BI_DEST_UV 4 //========== Left MB, 4x16 in r2 and r3 ========== #define PREV_MB_Y_BASE 64 //2*GRFWIB // Byte offset to r2 .declare PREV_MB_YD Base=r2 ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare PREV_MB_YW Base=r2 ElementSize=2 SrcRegion=REGION(8,1) Type=uw .declare PREV_MB_YB Base=r2 ElementSize=1 SrcRegion=REGION(16,1) Type=ub #define PREV_MB_U_BASE 64 //2*GRFWIB // seperate thread from Y // Byte offset to r2 .declare PREV_MB_UD Base=r2 ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare PREV_MB_UW Base=r2 ElementSize=2 SrcRegion=REGION(16,1) Type=uw .declare PREV_MB_UB Base=r2 ElementSize=1 SrcRegion=REGION(16,1) Type=ub #define PREV_MB_V_BASE 65 //2*GRFWIB+1 // NV12 // Byte offset to r2.1 .declare PREV_MB_VB Base=r2.1 ElementSize=1 SrcRegion=REGION(16,1) Type=ub //========== Top MB, 16x4 in r4 and r5 ========== #define TOP_MB_Y_BASE 128 //4*GRFWIB // Byte offset to r4 .declare TOP_MB_YD Base=r4 ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare TOP_MB_YW Base=r4 ElementSize=2 SrcRegion=REGION(8,1) Type=uw .declare TOP_MB_YB Base=r4 ElementSize=1 SrcRegion=REGION(16,1) Type=ub #define TOP_MB_U_BASE 128 //4*GRFWIB // seperate thread from Y // Byte offset to r4 .declare TOP_MB_UD Base=r4 ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare TOP_MB_UW Base=r4 ElementSize=2 SrcRegion=REGION(16,1) Type=uw .declare TOP_MB_UB Base=r4 ElementSize=1 SrcRegion=REGION(16,1) Type=ub #define TOP_MB_V_BASE 129 //4*GRFWIB+1 // NV12 // Byte offset to r4.1 .declare TOP_MB_VB Base=r4.1 ElementSize=1 SrcRegion=REGION(16,1) Type=ub //========== Current MB, 16x16 in r6-r13 ========== #define SRC_MB_Y_BASE 192 //6*GRFWIB // Byte offset to r6 .declare SRC_YD Base=r6 ElementSize=4 SrcRegion=REGION(8,1) Type=ud // For read and write, 8 GRFs .declare SRC_YW Base=r6 ElementSize=2 SrcRegion=REGION(8,1) Type=uw .declare SRC_YB Base=r6 ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8 GRFs #define SRC_MB_U_BASE 192 //6*GRFWIB // seperate thread from Y // Byte offset to r6 .declare SRC_UD Base=r6 ElementSize=4 SrcRegion=REGION(8,1) Type=ud // For read and write, 2 GRFs .declare SRC_UW Base=r6 ElementSize=2 SrcRegion=REGION(16,1) Type=uw // For read and write, 4 GRFs .declare SRC_UB Base=r6 ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 2 GRFs #define SRC_MB_V_BASE 193 // 6*GRFWIB+1 // NV12 // Byte offset to r6.1 .declare SRC_VD Base=r6.1 ElementSize=4 SrcRegion=REGION(8,1) Type=ud // For read and write, 2 GRFs .declare SRC_VW Base=r6.1 ElementSize=2 SrcRegion=REGION(16,1) Type=uw // For read and write, 4 GRFs .declare SRC_VB Base=r6.1 ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 2 GRFs #else // No kernel specified, define nothing. .reg_count_total 64 .reg_count_payload 2 #define SRCAOFF r1.0:ud // Offset into alpha data #define SRCOFF r1.1:ud // Offset into source YUV data #define ORIX r1.4 // :w, H. origin of the destination block in pel #define ORIY r1.5 // :w, V. origin of the destination block in pel #endif // ----------- Message Payload Header fields------------ // #define IDP r0.2:ud // Interface Descriptor Pointer #define BTP r0.4:ud // Binding Table Pointer // ----------- Common Message Descriptor ------------ // #ifdef DEV_ILK #define GW_DCN // Should be enabled only for ILK-B0 and beyond #define MSG_GW 0x03 // Message Gateway #define MSG_GW_EOT 0x23 // Message Gateway plus EOT bit set (For ILK only) #define DAPREAD 0x04 // Data Port Read Extended Message Descriptor, #define DAPWRITE 0x05 // Data Port Write Extended Message Descriptor, #define URBWRITE 0x06 // URB #define TS 0x07 // Thread Spawner Extended Message Descriptor #define TS_EOT 0x27 // End of Thread Extended Message Descriptor #define EOTMSGDSC 0x02000000 // End of Thread Message Descriptor /w URB handle dereferenced (used by root kernel) #define CHILD_EOTMSGDSC 0x02000012 // End of Child Thread Message Descriptor w/o URB handle dereferenced // Data Port Message Descriptor #define DWBRMSGDSC_RC 0x02086000 // DWORD Block Read Message Descriptor, reading from render cache = 6. #define DWBRMSGDSC_RC_TF 0x02086600 // DWORD Block Read Message Descriptor, reading from render cache = 6. #define DWBRMSGDSC_RC_BF 0x02086700 // DWORD Block Read Message Descriptor, reading from render cache = 6. #define DWBRMSGDSC_SC 0x0208A000 // DWORD Block Read Message Descriptor, reading from sampler cache = A. #define DWBRMSGDSC_SC_TF 0x0208E600 // DWORD Block Read Message Descriptor, reading top field from field mode sampler cache. #define DWBRMSGDSC_SC_BF 0x0208E700 // DWORD Block Read Message Descriptor, reading bottom field from field mode sampler cache. #define ILDBRMSGDSC 0x02085800 // AVC ILDB Control Data Read Msg Desc on Bearlake-C #define DWBWMSGDSC 0x02082000 // DWORD Block Write Message Descriptor #define DWBWMSGDSC_WC 0x0218A000 // DWORD Block Write Message Descriptor + write commit // URB Message Descriptor #define URBWMSGDSC 0x02080000 // URB Write Message Descriptor // Thread Spawner Message Descriptor #define TSMSGDSC 0x02000001 // Message Gateway Message Descriptors #define OGWMSGDSC 0x02000000 // OpenGateway Message Descriptor #define CGWMSGDSC 0x02000001 // CloseGateway Message Descriptor #define FWDMSGDSC 0x02000002 // ForwardMsg Message Descriptor #define NOTIFYMSG 0x00008000 // Send notification with ForwardMsg message #define RESP_LEN(len) 0x100000*len #define MSG_LEN(len) 0x2000000*len #else // Pre DEV_ILK #define MSG_GW #define MSG_GW_EOT #define DAPREAD #define DAPWRITE #define URBWRITE #define TS #define TS_EOT #define EOTMSGDSC 0x87100000 // End of Thread Message Descriptor /w URB handle dereferenced (used by root kernel) #define CHILD_EOTMSGDSC 0x87100012 // End of Child Thread Message Descriptor w/o URB handle dereferenced // Data Port Message Descriptor #define DWBRMSGDSC_RC 0x04106000 // DWORD Block Read Message Descriptor, reading from render cache = 6. #define DWBRMSGDSC_RC_TF 0x04106600 // DWORD Block Read Message Descriptor, reading from render cache = 6. #define DWBRMSGDSC_RC_BF 0x04106700 // DWORD Block Read Message Descriptor, reading from render cache = 6. #define DWBRMSGDSC_SC 0x0410A000 // DWORD Block Read Message Descriptor, reading from sampler cache = A. #define DWBRMSGDSC_SC_TF 0x0410A600 // DWORD Block Read Message Descriptor, reading top field from field mode sampler cache. #define DWBRMSGDSC_SC_BF 0x0410A700 // DWORD Block Read Message Descriptor, reading bottom field from field mode sampler cache. #define ILDBRMSGDSC 0x04105800 // AVC ILDB Control Data Read Msg Desc on Bearlake-C #define DWBWMSGDSC 0x05102000 // DWORD Block Write Message Descriptor #define DWBWMSGDSC_WC 0x0511A000 // DWORD Block Write Message Descriptor + write commit // URB Message Descriptor #define URBWMSGDSC 0x06100000 // URB Write Message Descriptor // Thread Spawner Message Descriptor #define TSMSGDSC 0x07100001 // Message Gateway Message Descriptors #define OGWMSGDSC 0x03100000 // OpenGateway Message Descriptor #define CGWMSGDSC 0x03100001 // CloseGateway Message Descriptor #define FWDMSGDSC 0x03100002 // ForwardMsg Message Descriptor #define NOTIFYMSG 0x00008000 // Send notification with ForwardMsg message #define RESP_LEN(len) 0x10000*len #define MSG_LEN(len) 0x100000*len // bits 15 - 0 = 01 011 000 00000000 = 0101 1000 0000 0000 = 5800 // Render cache, AVC loop rd, #endif // DEV_ILK // Enable frame/field selection in message descriptor #define ENMSGDSCFM 0x400 // Enable MSGDSC to select frame surface #define ENMSGDSCTF 0x600 // Enable MSGDSC to select top field surface #define ENMSGDSCBF 0x700 // Enable MSGDSC to select bottom field surface #define END_THREAD send (8) NULLREG MSGHDR r0:ud TS_EOT EOTMSGDSC #define END_CHILD_THREAD send (8) NULLREG MSGHDR r0:ud TS_EOT CHILD_EOTMSGDSC // ----------- Message related register ------------ // #define MSGHDR m1 // Message Payload Header #define MSGHDRY m1 // Message Payload Header register for Y data #define MSGHDRU m2 // Message Payload Header register for U data #define MSGHDRV m3 // Message Payload Header register for V data #define MSGHDRC m1 // Message Payload Header register for CUR MB #define MSGHDRL m2 // Message Payload Header register for LEFT MB #define MSGHDRT m3 // Message Payload Header register for TOP MB #define MSGHDRYA m4 // Second Message Payload Header register for Y data #define MSGSRC r63 // Message source register #define MSGDSC a0.0:ud // Message Descriptor register (type DWORD) #define MH_ORI MSGSRC.0 // DWORD block R/W message header block offset #define MH_ORIX MSGSRC.0 // DWORD block R/W message header X offset #define MH_ORIY MSGSRC.1 // DWORD block R/W message header Y offset #define MH_SIZE MSGSRC.2 // DWORD block R/W message header block width & height // M2 - M9 for message data payload .declare MSGPAYLOADB Base=m2 ElementSize=1 SrcRegion=REGION(16,1) Type=ub .declare MSGPAYLOADW Base=m2 ElementSize=2 SrcRegion=REGION(16,1) Type=uw .declare MSGPAYLOADD Base=m2 ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare MSGPAYLOADF Base=m2 ElementSize=4 SrcRegion=REGION(8,1) Type=f // End of ILDB_header.inc #endif // !defined(__ILDB_HEADER__) intel-driver-1.3.0/src/shaders/h264/ildb/Load_ILDB_Cntrl_Data.asm000066400000000000000000000061421231401140700241760ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: load_ILDB_Cntrl_Data.asm // // This module loads AVC ILDB control data for one MB. // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // CNTRL_DATA_D: CNTRL_DATA_D Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 8 GRFs // // Binding table index: // BI_CNTRL_DATA: Binding table index of control data surface // //---------------------------------------------------------------- // We need to get control data offset for the bottom MB in mbaff mode. // That is, get f0.1=1 if MbaffFlag==1 && BotFieldFlag==1 and (1) CTemp1_W:uw BitFields:uw MbaffFlag+BotFieldFlag:uw // Mute all other bits and.nz.f0.0 (1) null:w BitFields:w CntlDataExpFlag:w // Get CntlDataExpFlag cmp.e.f0.1 (1) NULLREGW CTemp1_W:uw MbaffFlag+BotFieldFlag:uw // Check mbaff and bot flags (f0.0) jmpi ILDB_LABEL(READ_BLC_CNTL_DATA) // On Crestline, MB control data in memory occupy 64 DWs (expanded). // mov (1) MSGSRC.0<1>:ud 0:w { NoDDClr } // Block origin X // mov (1) MSGSRC.1<1>:ud CntrlDataOffsetY:ud { NoDDClr, NoDDChk } // Block origin Y // mov (1) MSGSRC.2<1>:ud 0x000F000F:ud { NoDDChk } // Block width and height (16x16=256 bytes) mov (2) MSGSRC.0<1>:ud ORIX_CUR<2;2,1>:uw { NoDDClr } // Block origin X,Y mov (1) MSGSRC.2<1>:ud 0x000F000F:ud { NoDDChk } // Block width and height (16x16=256 bytes) (f0.1) add (1) MSGSRC.1:ud MSGSRC.1:ud 16:w // +16 to for bottom MB in a pair send (8) CNTRL_DATA_D(0)<1> MSGHDRY MSGSRC<8;8,1>:ud DAPREAD DWBRMSGDSC_SC+0x00080000+BI_CNTRL_DATA // Receive 8 GRFs jmpi ILDB_LABEL(READ_CNTL_DATA_DONE) ILDB_LABEL(READ_BLC_CNTL_DATA): // On Bearlake-C, MB control data in memory occupy 16 DWs. Data port returns 8 GRFs with expanded control data. // Global offset mov (1) MSGSRC.2:ud CntrlDataOffsetY:ud // CntrlDataOffsetY is the global offset (f0.1) add (1) MSGSRC.2:ud MSGSRC.2:ud 64:w // +64 to the next MB control data (bot MB) send (8) CNTRL_DATA_D(0)<1> MSGHDRY MSGSRC<8;8,1>:ud DAPREAD RESP_LEN(8)+ILDBRMSGDSC+BI_CNTRL_DATA // Receive 8 GRFs ILDB_LABEL(READ_CNTL_DATA_DONE): // End of load_ILDB_Cntrl_Data.asm // AVC ILDB control data message header format //DWord Bit Description //M0.7 31:0 Debug //M0.6 31:0 Debug //M0.5 31:8 Ignored // 7:0 Dispatch ID. // This ID is assigned by the fixed function unit and is a unique identifier for the thread. It is used to free up resources used by the thread upon thread completion. //M0.4 31:0 Ignored //M0.3 31:0 Ignored //M0.2 31:0 Global Offset. Specifies the global byte offset into the buffer. // This offset must be OWord aligned (bits 3:0 MBZ) Format = U32 Range = [0,FFFFFFF0h] //M0.1 31:0 Ignored //M0.0 31:0 Ignored intel-driver-1.3.0/src/shaders/h264/ildb/Load_ILDB_Cntrl_Data_16DW.asm000066400000000000000000000043571231401140700247450ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: load_ILDB_Cntrl_Data_16DW.asm // // This module loads AVC ILDB 64DW control data for one MB CTG. // Dataport expands from 16DW to 64DW. // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // CNTRL_DATA_D: CNTRL_DATA_D Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 8 GRFs // // Binding table index: // BI_CNTRL_DATA: Binding table index of control data surface // //---------------------------------------------------------------- // On CTG, MB control data in memory occupy 16 DWs. Data port returns 8 GRFs with expanded control data. #if defined(_MBAFF) // We need to get control data offset for the bottom MB in mbaff mode. // That is, get f0.1=1 if MbaffFlag==1 && BotFieldFlag==1 // and (1) CTemp1_W:uw BitFields:uw MbaffFlag+BotFieldFlag:uw // Mute all other bits // cmp.e.f0.1 (1) NULLREGW CTemp1_W:uw MbaffFlag+BotFieldFlag:uw // Check mbaff and bot flags and.ne.f0.1 (1) NULLREGW BitFields:uw BotFieldFlag:uw // Global offset mov (1) MSGSRC.2:ud CntrlDataOffsetY:ud (f0.1) add (1) MSGSRC.2:ud MSGSRC.2:ud 64:w // +64 to the next MB control data (bot MB) #endif send (8) CNTRL_DATA_D(0)<1> MSGHDRY MSGSRC<8;8,1>:ud DAPREAD RESP_LEN(8)+ILDBRMSGDSC+BI_CNTRL_DATA // Receive 8 GRFs // End of load_ILDB_Cntrl_Data_16DW.asm // AVC ILDB control data message header format //DWord Bit Description //M0.7 31:0 Debug //M0.6 31:0 Debug //M0.5 31:8 Ignored // 7:0 Dispatch ID. // This ID is assigned by the fixed function unit and is a unique identifier for the thread. It is used to free up resources used by the thread upon thread completion. //M0.4 31:0 Ignored //M0.3 31:0 Ignored //M0.2 31:0 Global Offset. Specifies the global byte offset into the buffer. // This offset must be OWord aligned (bits 3:0 MBZ) Format = U32 Range = [0,FFFFFFF0h] //M0.1 31:0 Ignored //M0.0 31:0 Ignored intel-driver-1.3.0/src/shaders/h264/ildb/Load_ILDB_Cntrl_Data_22DW.asm000066400000000000000000000026711231401140700247370ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: load_ILDB_Cntrl_Data_22DW.asm // // ********** Apple only module ********** // // This module loads AVC ILDB 22DW control data for one MB for CLN. // The reduced control data set is for progressive picture ONLY. // // Control data memory layout for each MB is 8x11 = 88 bytes. // It ocuppies 3 GRFs after reading in. // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // CNTRL_DATA_D: CNTRL_DATA_D Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 3 GRFs // // Binding table index: // BI_CNTRL_DATA: Binding table index of control data surface // //---------------------------------------------------------------- mul (1) MSGSRC.0<1>:ud ORIX:uw 8:uw { NoDDClr } // Block origin X mul (1) MSGSRC.1<1>:ud ORIY:uw 11:uw { NoDDClr, NoDDChk } // Block origin Y mov (1) MSGSRC.2<1>:ud 0x000A0007:ud { NoDDChk } // Block width and height (8x11=88 bytes) send (8) CNTRL_DATA_D(0)<1> MSGHDRY MSGSRC<8;8,1>:ud DAPREAD RESP_LEN(3)+DWBRMSGDSC_SC+BI_CNTRL_DATA // Receive 3 GRFs // End of load_ILDB_Cntrl_Data_22DW.asm intel-driver-1.3.0/src/shaders/h264/ildb/Load_ILDB_Cntrl_Data_64DW.asm000066400000000000000000000032521231401140700247410ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: load_ILDB_Cntrl_Data_64DW.asm // // This module loads AVC ILDB 64DW control data for one MB for CLN. // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // CNTRL_DATA_D: CNTRL_DATA_D Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 8 GRFs // // Binding table index: // BI_CNTRL_DATA: Binding table index of control data surface // //---------------------------------------------------------------- // On CLN, MB control data in memory occupy 64 DWs. #if defined(_MBAFF) // We need to get control data offset for the bottom MB in mbaff mode. // That is, set f0.1=1 if MbaffFlag==1 && BotFieldFlag==1 and (1) acc0.0:uw BitFields:uw MbaffFlag+BotFieldFlag:uw // Mute all other bits cmp.e.f0.1 (1) NULLREGW acc0.0:uw MbaffFlag+BotFieldFlag:uw // Check mbaff and bot flags #endif // CTemp1_W mov (2) MSGSRC.0<1>:ud ORIX_CUR<2;2,1>:uw { NoDDClr } // Block origin X,Y mov (1) MSGSRC.2<1>:ud 0x000F000F:ud { NoDDChk } // Block width and height (16x16=256 bytes) #if defined(_MBAFF) (f0.1) add (1) MSGSRC.1:ud MSGSRC.1:ud 16:w // +16 to the bottom MB control data (bot MB) #endif send (8) CNTRL_DATA_D(0)<1> MSGHDRY MSGSRC<8;8,1>:ud DAPREAD RESP_LEN(8)+DWBRMSGDSC_SC+BI_CNTRL_DATA // Receive 8 GRFs // End of load_ILDB_Cntrl_Data_64DW.asm intel-driver-1.3.0/src/shaders/h264/ildb/Makefile.am000066400000000000000000000052021231401140700217600ustar00rootroot00000000000000INTEL_ILDB_INC = \ AVC_ILDB.inc \ Child_Undefs.inc \ ILDB_header.inc \ Root_Undefs.inc \ $(NULL) INTEL_ILDB_ASM = \ AVC_ILDB_Child_Field_UV.asm \ AVC_ILDB_Child_Field_Y.asm \ AVC_ILDB_Child_Mbaff_UV.asm \ AVC_ILDB_Child_Mbaff_Y.asm \ AVC_ILDB_Child_UV.asm \ AVC_ILDB_Child_Y.asm \ AVC_ILDB_Chroma_Core.asm \ AVC_ILDB_Chroma_Core_Mbaff.asm \ AVC_ILDB_CloseGateway.asm \ AVC_ILDB_Dep_Check.asm \ AVC_ILDB_Filter_Mbaff_UV_h.asm \ AVC_ILDB_Filter_Mbaff_UV_v.asm \ AVC_ILDB_Filter_Mbaff_Y_h.asm \ AVC_ILDB_Filter_Mbaff_Y_v.asm \ AVC_ILDB_Filter_UV_h.asm \ AVC_ILDB_Filter_UV_v.asm \ AVC_ILDB_Filter_Y_h.asm \ AVC_ILDB_Filter_Y_v.asm \ AVC_ILDB_ForwardMsg.asm \ AVC_ILDB_LumaThrdLimit.asm \ AVC_ILDB_Luma_Core.asm \ AVC_ILDB_Luma_Core_Mbaff.asm \ AVC_ILDB_OpenGateway.asm \ AVC_ILDB_Root_Field_UV.asm \ AVC_ILDB_Root_Field_Y.asm \ AVC_ILDB_Root_Mbaff_UV.asm \ AVC_ILDB_Root_Mbaff_Y.asm \ AVC_ILDB_Root_UV.asm \ AVC_ILDB_Root_Y.asm \ AVC_ILDB_Spawn.asm \ AVC_ILDB_SpawnChild.asm \ AVC_ILDB_SpawnChromaRoot.asm \ Load_ILDB_Cntrl_Data.asm \ Load_ILDB_Cntrl_Data_16DW.asm \ Load_ILDB_Cntrl_Data_22DW.asm \ Load_ILDB_Cntrl_Data_64DW.asm \ SetupVPKernel.asm \ TransposeNV12_16x16.asm \ TransposeNV12_4x16.asm \ Transpose_Cur_UV_2x8.asm \ Transpose_Cur_UV_8x8.asm \ Transpose_Cur_UV_Right_Most_2x8.asm \ Transpose_Cur_Y_16x16.asm \ Transpose_Cur_Y_4x16.asm \ Transpose_Cur_Y_Right_Most_4x16.asm \ Transpose_Left_UV_2x8.asm \ Transpose_Left_Y_4x16.asm \ loadNV12_16x16T.asm \ loadNV12_16x4.asm \ load_Cur_UV_8x8T.asm \ load_Cur_UV_8x8T_Mbaff.asm \ load_Cur_UV_Right_Most_2x8.asm \ load_Cur_Y_16x16T.asm \ load_Cur_Y_16x16T_Mbaff.asm \ load_Cur_Y_Right_Most_4x16.asm \ load_Left_UV_2x8T.asm \ load_Left_UV_2x8T_Mbaff.asm \ load_Left_Y_4x16T.asm \ load_Left_Y_4x16T_Mbaff.asm \ load_Top_UV_8x2.asm \ load_Top_UV_8x2_Mbaff.asm \ load_Top_Y_16x4.asm \ load_Top_Y_16x4_Mbaff.asm \ saveNV12_16x16.asm \ saveNV12_16x4.asm \ saveNV12_16x4T.asm \ save_Cur_UV_8x8.asm \ save_Cur_UV_8x8_Mbaff.asm \ save_Cur_Y_16x16.asm \ save_Cur_Y_16x16_Mbaff.asm \ save_Left_UV_8x2T.asm \ save_Left_UV_8x2T_Mbaff.asm \ save_Left_Y_16x4T.asm \ save_Left_Y_16x4T_Mbaff.asm \ save_Top_UV_8x2.asm \ save_Top_UV_8x2_Mbaff.asm \ save_Top_Y_16x4.asm \ save_Top_Y_16x4_Mbaff.asm \ writeURB.asm \ writeURB_UV_Child.asm \ writeURB_Y_Child.asm \ $(NULL) EXTRA_DIST = \ $(INTEL_ILDB_ASM) \ $(INTEL_ILDB_INC) \ $(NULL) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/h264/ildb/Root_Undefs.inc000066400000000000000000000012741231401140700226530ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: Root_Undefs.inc // // Undefine global symbols for new process in root thread // #undef READ_BI #undef WRITE_BI #undef ILDB_H_INDEPENDENT #undef ILDB_H_INDEPENDENT_CONT #undef ILDB_H_DEPENDENT #undef ILDB_H_DEPENDENT_SCAN #undef ILDB_H_NO_DEPENDENT #undef ILDB_V_INDEPENDENT #undef ILDB_V_INDEPENDENT_CONT #undef ILDB_V_DEPENDENT #undef ILDB_V_DEPENDENT_SCAN #undef ILDB_V_NO_DEPENDENT intel-driver-1.3.0/src/shaders/h264/ildb/SetupVPKernel.asm000066400000000000000000000010571231401140700231410ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: SetupVPKernel.asm // // Initial setup for running video-processing kernels // #include "ILDB_header.inc" // // Now, begin source code.... // .code mov (8) MSGSRC.0<1>:ud r0.0<8;8,1>:ud // Initialize message payload header with R0 // End of SetupVPKernel intel-driver-1.3.0/src/shaders/h264/ildb/TransposeNV12_16x16.asm000066400000000000000000000146641231401140700236740ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////////////////////////////////////////////////////////////////////////////////////// // Module name: TransposeNV12_16x16.asm // // Transpose a 16x16 NV12 MB. The output is also in NV12 // //---------------------------------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region is :ub // SRC_YB: SRC_YB Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8 GRFs // SRC_UW: SRC_UW Base=rxx ElementSize=2 SrcRegion=REGION(8,1) Type=uw // 4 GRFs // // Temp buffer: // BUF_B: BUF_B Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8 GRFs // BUF_W: BUF_W Base=rxx ElementSize=2 SrcRegion=REGION(8,1) Type=uw // 4 GRFs // ////////////////////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDDA:w #endif // Transpose Y (16x16 bytes) // The first step mov (16) BUF_B(0,0)<1> SRC_YB(0,0)<16;4,1> mov (16) BUF_B(0,16)<1> SRC_YB(2,0)<16;4,1> mov (16) BUF_B(1,0)<1> SRC_YB(4,0)<16;4,1> mov (16) BUF_B(1,16)<1> SRC_YB(6,0)<16;4,1> mov (16) BUF_B(2,0)<1> SRC_YB(0,4)<16;4,1> mov (16) BUF_B(2,16)<1> SRC_YB(2,4)<16;4,1> mov (16) BUF_B(3,0)<1> SRC_YB(4,4)<16;4,1> mov (16) BUF_B(3,16)<1> SRC_YB(6,4)<16;4,1> mov (16) BUF_B(4,0)<1> SRC_YB(0,8)<16;4,1> mov (16) BUF_B(4,16)<1> SRC_YB(2,8)<16;4,1> mov (16) BUF_B(5,0)<1> SRC_YB(4,8)<16;4,1> mov (16) BUF_B(5,16)<1> SRC_YB(6,8)<16;4,1> mov (16) BUF_B(6,0)<1> SRC_YB(0,12)<16;4,1> mov (16) BUF_B(6,16)<1> SRC_YB(2,12)<16;4,1> mov (16) BUF_B(7,0)<1> SRC_YB(4,12)<16;4,1> mov (16) BUF_B(7,16)<1> SRC_YB(6,12)<16;4,1> // The second step mov (16) SRC_YB(0,0)<1> BUF_B(0,0)<32;8,4> mov (16) SRC_YB(0,16)<1> BUF_B(0,1)<32;8,4> mov (16) SRC_YB(1,0)<1> BUF_B(0,2)<32;8,4> mov (16) SRC_YB(1,16)<1> BUF_B(0,3)<32;8,4> mov (16) SRC_YB(2,0)<1> BUF_B(2,0)<32;8,4> mov (16) SRC_YB(2,16)<1> BUF_B(2,1)<32;8,4> mov (16) SRC_YB(3,0)<1> BUF_B(2,2)<32;8,4> mov (16) SRC_YB(3,16)<1> BUF_B(2,3)<32;8,4> mov (16) SRC_YB(4,0)<1> BUF_B(4,0)<32;8,4> mov (16) SRC_YB(4,16)<1> BUF_B(4,1)<32;8,4> mov (16) SRC_YB(5,0)<1> BUF_B(4,2)<32;8,4> mov (16) SRC_YB(5,16)<1> BUF_B(4,3)<32;8,4> mov (16) SRC_YB(6,0)<1> BUF_B(6,0)<32;8,4> mov (16) SRC_YB(6,16)<1> BUF_B(6,1)<32;8,4> mov (16) SRC_YB(7,0)<1> BUF_B(6,2)<32;8,4> mov (16) SRC_YB(7,16)<1> BUF_B(6,3)<32;8,4> // Y is transposed. ////////////////////////////////////////////////////////////////////////////////////////////////////////// // Src U and V are mixed in NV12 format. U on even bytes, V on odd bytes. // Transpose by treating UV pair as a word. // Src U 8x8 and V 8x8 are mixed. (each pix is specified as yx) // +-----------------------+-----------------------+-----------------------+-----------------------+ // |17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 07 07 06 06 05 05 04 04 03 03 02 02 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |37 37 36 36 35 35 34 34 33 33 32 32 31 31 30 30 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |57 57 56 56 55 55 54 54 53 53 52 52 51 51 50 50 47 47 46 46 45 45 44 44 43 43 42 42 41 41 40 40| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |77 77 76 76 75 75 74 74 73 73 72 72 71 71 70 70 67 67 66 66 65 65 64 64 63 63 62 62 61 61 60 60| // +-----------------------+-----------------------+-----------------------+-----------------------+ // First step (16) <1>:w <==== <8;4,1>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |33 33 32 32 31 31 30 30 23 23 22 22 21 21 20 20 13 13 12 12 11 11 10 10 03 03 02 02 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 73 72 72 71 71 70 70 63 63 62 62 61 61 60 60 53 53 52 52 51 51 50 50 43 43 42 42 41 41 40 40| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |37 37 36 36 35 35 34 34 27 27 26 26 25 25 24 24 17 17 16 16 15 15 14 14 07 07 06 06 05 05 04 04| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |77 77 76 76 75 75 74 74 67 67 66 66 65 65 64 64 57 57 56 56 55 55 54 54 47 47 46 46 45 45 44 44| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // Transpose UV (8x8 words), The first step mov (16) BUF_W(0,0)<1> SRC_UW(0,0)<8;4,1> mov (16) BUF_W(1,0)<1> SRC_UW(2,0)<8;4,1> mov (16) BUF_W(2,0)<1> SRC_UW(0,4)<8;4,1> mov (16) BUF_W(3,0)<1> SRC_UW(2,4)<8;4,1> // Second step (16) <1>:w <=== <16;4,4>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 61 61 51 51 41 41 31 31 21 21 11 11 01 01 70 70 60 60 50 50 40 40 30 30 20 20 10 10 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 73 63 63 53 53 43 43 33 33 23 23 13 13 03 03 72 72 62 62 52 52 42 42 32 32 22 22 12 12 02 02| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |75 75 65 65 55 55 45 45 35 35 25 25 15 15 05 05 74 74 64 64 54 54 44 44 34 34 24 24 14 14 04 04| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |77 77 67 67 57 57 47 47 37 37 27 27 17 17 07 07 76 76 66 66 56 56 46 46 36 36 26 26 16 16 06 06| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // Transpose UV (8x8 words), The second step mov (8) SRC_UW(0,0)<1> BUF_W(0,0)<16;4,4> mov (8) SRC_UW(0,8)<1> BUF_W(0,1)<16;4,4> mov (8) SRC_UW(1,0)<1> BUF_W(0,2)<16;4,4> mov (8) SRC_UW(1,8)<1> BUF_W(0,3)<16;4,4> mov (8) SRC_UW(2,0)<1> BUF_W(2,0)<16;4,4> mov (8) SRC_UW(2,8)<1> BUF_W(2,1)<16;4,4> mov (8) SRC_UW(3,0)<1> BUF_W(2,2)<16;4,4> mov (8) SRC_UW(3,8)<1> BUF_W(2,3)<16;4,4> // U and V are now transposed and separated. intel-driver-1.3.0/src/shaders/h264/ildb/TransposeNV12_4x16.asm000066400000000000000000000104241231401140700235770ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////////////////////////////////////////////////////////////////////////////////////// // Module name: TransposeNV12_4x16.asm // // Transpose a 4x16 internal planar to 16x4 internal planar block // //---------------------------------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region is :ub // SRC_YB: SRC_YB Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8 GRFs // SRC_UW: SRC_UB Base=rxx ElementSize=2 SrcRegion=REGION(8,1) Type=uw // 4 GRFs // // Temp buffer: // BUF_B: BUF_B Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8 GRFs // BUF_W: BUF_W Base=rxx ElementSize=2 SrcRegion=REGION(8,1) Type=uw // 4 GRFs // ////////////////////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDDB:w #endif // Transpose Y (4x16) right most 4 columns // The first step mov (16) BUF_B(0,0)<1> SRC_YB(0,0)<16;4,1> // Read 2 rows, write 1 row mov (16) BUF_B(0,16)<1> SRC_YB(2,0)<16;4,1> mov (16) BUF_B(1,0)<1> SRC_YB(4,0)<16;4,1> mov (16) BUF_B(1,16)<1> SRC_YB(6,0)<16;4,1> // The second step mov (16) BUF_B(2,0)<1> BUF_B(0,0)<32;8,4> // Read 2 rows, write 1 row mov (16) BUF_B(2,16)<1> BUF_B(0,1)<32;8,4> mov (16) BUF_B(3,0)<1> BUF_B(0,2)<32;8,4> mov (16) BUF_B(3,16)<1> BUF_B(0,3)<32;8,4> // Y is now transposed. the result is in BUF_B(2) and BUF_B(3). // Transpose UV (4x8), right most 2 columns in word // Use BUF_W(0) as temp buf // Src U 8x8 and V 8x8 are mixed. (each pix is specified as yx) // +-----------------------+-----------------------+-----------------------+-----------------------+ // |17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 07 07 06 06 05 05 04 04 03 03 02 02 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |37 37 36 36 35 35 34 34 33 33 32 32 31 31 30 30 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |57 57 56 56 55 55 54 54 53 53 52 52 51 51 50 50 47 47 46 46 45 45 44 44 43 43 42 42 41 41 40 40| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |77 77 76 76 75 75 74 74 73 73 72 72 71 71 70 70 67 67 66 66 65 65 64 64 63 63 62 62 61 61 60 60| // +-----------------------+-----------------------+-----------------------+-----------------------+ // First step (8) <1>:w <==== <8;2,1>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 70 70 61 61 60 60 51 51 50 50 41 41 40 40 31 31 30 30 21 21 20 20 11 11 10 10 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ mov (8) BUF_W(0,0)<1> SRC_UW(0,0)<8;2,1> mov (8) BUF_W(0,8)<1> SRC_UW(2,0)<8;2,1> // Second step (16) <1>:w <==== <1;8,2>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 61 61 51 51 41 41 31 31 21 21 11 11 01 01 70 70 60 60 50 50 40 40 30 30 20 20 10 10 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ mov (16) BUF_W(1,0)<1> BUF_W(0,0)<1;8,2> // UV are now transposed. the result is in BUF_W(1). //The first step //mov (16) BUF_B(0,0)<1> SRC_UW(0,0)<8;2,1> // Read 2 rows, write 1 row // The second step //mov (8) SRC_UB(4,0)<1> BUF_B(0,0)<16;8,2> // Read 1 row, write 1 row //mov (8) SRC_UB(4,8)<1> BUF_B(0,1)<16;8,2> // Read 1 row, write 1 row // Transpose V (8x8), right most 2 columns // The first step //mov (16) BUF_B(0,0)<1> SRC_VB(0,1)<8;2,1> // Read 2 rows, write 1 row // The second step //mov (8) SRC_UB(4,16)<1> BUF_B(0,0)<16;8,2> // Read 1 row, write 1 row //mov (8) SRC_UB(4,24)<1> BUF_B(0,1)<16;8,2> // Read 1 row, write 1 row // U and V are now transposed. the result is in BUF_B(4). intel-driver-1.3.0/src/shaders/h264/ildb/Transpose_Cur_UV_2x8.asm000066400000000000000000000057021231401140700243350ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////////////////////////////////////////////////////////////////////////////////////// // Module name: Transpose_UV_2x8.asm // // Transpose UV 2x8 to 8x2 block (2x8U + 2x8V in NV12) // //---------------------------------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region is :ub // SRC_UW: SRC_UB Base=rxx ElementSize=2 SrcRegion=REGION(8,1) Type=uw // 4 GRFs // // Temp buffer: // BUF_W: BUF_W Base=rxx ElementSize=2 SrcRegion=REGION(8,1) Type=uw // 4 GRFs // ////////////////////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDDB:w #endif // Transpose UV (4x8), right most 2 columns in word // Use BUF_W(0) as temp buf // Src U 8x8 and V 8x8 are mixed. (each pix is specified as yx) // +-----------------------+-----------------------+-----------------------+-----------------------+ // |17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 07 07 06 06 05 05 04 04 03 03 02 02 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |37 37 36 36 35 35 34 34 33 33 32 32 31 31 30 30 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |57 57 56 56 55 55 54 54 53 53 52 52 51 51 50 50 47 47 46 46 45 45 44 44 43 43 42 42 41 41 40 40| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |77 77 76 76 75 75 74 74 73 73 72 72 71 71 70 70 67 67 66 66 65 65 64 64 63 63 62 62 61 61 60 60| // +-----------------------+-----------------------+-----------------------+-----------------------+ // First step (8) <1>:w <==== <8;2,1>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |77 77 76 76 67 67 66 66 57 57 56 56 47 47 46 46 37 37 36 36 27 27 26 26 17 17 16 16 07 07 06 06| // +-----------------------+-----------------------+-----------------------+-----------------------+ mov (8) LEFT_TEMP_W(0,0)<1> SRC_UW(0,6)<8;2,1> { NoDDClr } mov (8) LEFT_TEMP_W(0,8)<1> SRC_UW(2,6)<8;2,1> { NoDDChk } // Second step (16) <1>:w <==== <1;8,2>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |77 77 67 67 57 57 47 47 37 37 27 27 17 17 07 07 76 76 66 66 56 56 46 46 36 36 26 26 16 16 06 06| // +-----------------------+-----------------------+-----------------------+-----------------------+ mov (16) LEFT_TEMP_W(1,0)<1> LEFT_TEMP_W(0,0)<1;8,2> // UV are now transposed. the result is in BUF_W(1) intel-driver-1.3.0/src/shaders/h264/ildb/Transpose_Cur_UV_8x8.asm000066400000000000000000000116231231401140700243420ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////////////////////////////////////////////////////////////////////////////////////// // Module name: Transpose_UV_8x8.asm // // Transpose a 8x8 UV block. (8x8U + 8x8V) The output is also in NV12 // //---------------------------------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region is :ub // SRC_UW: SRC_UW Base=rxx ElementSize=2 SrcRegion=REGION(8,1) Type=uw // 4 GRFs // // Temp buffer: // BUF_W: BUF_W Base=rxx ElementSize=2 SrcRegion=REGION(8,1) Type=uw // 4 GRFs // ////////////////////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDDA:w #endif ////////////////////////////////////////////////////////////////////////////////////////////////////////// // Src U and V are mixed in NV12 format. U on even bytes, V on odd bytes. // Transpose by treating UV pair as a word. // Src U 8x8 and V 8x8 are mixed. (each pix is specified as yx) // +-----------------------+-----------------------+-----------------------+-----------------------+ // |17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 07 07 06 06 05 05 04 04 03 03 02 02 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |37 37 36 36 35 35 34 34 33 33 32 32 31 31 30 30 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |57 57 56 56 55 55 54 54 53 53 52 52 51 51 50 50 47 47 46 46 45 45 44 44 43 43 42 42 41 41 40 40| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |77 77 76 76 75 75 74 74 73 73 72 72 71 71 70 70 67 67 66 66 65 65 64 64 63 63 62 62 61 61 60 60| // +-----------------------+-----------------------+-----------------------+-----------------------+ // First step (16) <1>:w <==== <8;4,1>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |33 33 32 32 31 31 30 30 23 23 22 22 21 21 20 20 13 13 12 12 11 11 10 10 03 03 02 02 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 73 72 72 71 71 70 70 63 63 62 62 61 61 60 60 53 53 52 52 51 51 50 50 43 43 42 42 41 41 40 40| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |37 37 36 36 35 35 34 34 27 27 26 26 25 25 24 24 17 17 16 16 15 15 14 14 07 07 06 06 05 05 04 04| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |77 77 76 76 75 75 74 74 67 67 66 66 65 65 64 64 57 57 56 56 55 55 54 54 47 47 46 46 45 45 44 44| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // Transpose UV (8x8 words), The first step mov (16) CUR_TEMP_W(0,0)<1> SRC_UW(0,0)<8;4,1> mov (16) CUR_TEMP_W(1,0)<1> SRC_UW(2,0)<8;4,1> mov (16) CUR_TEMP_W(2,0)<1> SRC_UW(0,4)<8;4,1> mov (16) CUR_TEMP_W(3,0)<1> SRC_UW(2,4)<8;4,1> // Second step (16) <1>:w <=== <16;4,4>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 61 61 51 51 41 41 31 31 21 21 11 11 01 01 70 70 60 60 50 50 40 40 30 30 20 20 10 10 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 73 63 63 53 53 43 43 33 33 23 23 13 13 03 03 72 72 62 62 52 52 42 42 32 32 22 22 12 12 02 02| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |75 75 65 65 55 55 45 45 35 35 25 25 15 15 05 05 74 74 64 64 54 54 44 44 34 34 24 24 14 14 04 04| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |77 77 67 67 57 57 47 47 37 37 27 27 17 17 07 07 76 76 66 66 56 56 46 46 36 36 26 26 16 16 06 06| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // Transpose UV (8x8 words), The second step mov (8) SRC_UW(0,0)<1> CUR_TEMP_W(0,0)<16;4,4> { NoDDClr } mov (8) SRC_UW(0,8)<1> CUR_TEMP_W(0,1)<16;4,4> { NoDDChk } mov (8) SRC_UW(1,0)<1> CUR_TEMP_W(0,2)<16;4,4> { NoDDClr } mov (8) SRC_UW(1,8)<1> CUR_TEMP_W(0,3)<16;4,4> { NoDDChk } mov (8) SRC_UW(2,0)<1> CUR_TEMP_W(2,0)<16;4,4> { NoDDClr } mov (8) SRC_UW(2,8)<1> CUR_TEMP_W(2,1)<16;4,4> { NoDDChk } mov (8) SRC_UW(3,0)<1> CUR_TEMP_W(2,2)<16;4,4> { NoDDClr } mov (8) SRC_UW(3,8)<1> CUR_TEMP_W(2,3)<16;4,4> { NoDDChk } // U and V are now transposed and separated. intel-driver-1.3.0/src/shaders/h264/ildb/Transpose_Cur_UV_Right_Most_2x8.asm000066400000000000000000000023771231401140700265010ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Transpose Cur MB Right Most 2x8 to 8x2 // Assume source is LEFT_TEMP_W(0), and detination is LEFT_TEMP_W(1) // Input from dport for transpose: // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 70 70 61 61 60 60 51 51 50 50 41 41 40 40 31 31 30 30 21 21 20 20 11 11 10 10 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // Output of transpose: <1> <=== <16;8,2>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 61 61 51 51 41 41 31 31 21 21 11 11 01 01 70 70 60 60 50 50 40 40 30 30 20 20 10 10 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // mov (8) LEFT_TEMP_W(1,0)<1> LEFT_TEMP_W(0,0)<16;8,2> { NoDDClr } // mov (8) LEFT_TEMP_W(1,8)<1> LEFT_TEMP_W(0,1)<16;8,2> { NoDDChk } mov (16) LEFT_TEMP_W(1,0)<1> LEFT_TEMP_W(0,0)<1;8,2> intel-driver-1.3.0/src/shaders/h264/ildb/Transpose_Cur_Y_16x16.asm000066400000000000000000000060631231401140700243600ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////////////////////////////////////////////////////////////////////////////////////// // Module name: Transpose_Y_16x16.asm // // Transpose Y 16x16 block. // //---------------------------------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region is :ub // SRC_YB: SRC_YB Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8 GRFs // // Temp buffer: // CUR_TEMP_B: BUF_B Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8 GRFs // ////////////////////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDDA:w #endif // Transpose Y (16x16 bytes) // The first step mov (16) CUR_TEMP_B(0,0)<1> SRC_YB(0,0)<16;4,1> { NoDDClr } mov (16) CUR_TEMP_B(0,16)<1> SRC_YB(2,0)<16;4,1> { NoDDChk } mov (16) CUR_TEMP_B(1,0)<1> SRC_YB(4,0)<16;4,1> { NoDDClr } mov (16) CUR_TEMP_B(1,16)<1> SRC_YB(6,0)<16;4,1> { NoDDChk } mov (16) CUR_TEMP_B(2,0)<1> SRC_YB(0,4)<16;4,1> { NoDDClr } mov (16) CUR_TEMP_B(2,16)<1> SRC_YB(2,4)<16;4,1> { NoDDChk } mov (16) CUR_TEMP_B(3,0)<1> SRC_YB(4,4)<16;4,1> { NoDDClr } mov (16) CUR_TEMP_B(3,16)<1> SRC_YB(6,4)<16;4,1> { NoDDChk } mov (16) CUR_TEMP_B(4,0)<1> SRC_YB(0,8)<16;4,1> { NoDDClr } mov (16) CUR_TEMP_B(4,16)<1> SRC_YB(2,8)<16;4,1> { NoDDChk } mov (16) CUR_TEMP_B(5,0)<1> SRC_YB(4,8)<16;4,1> { NoDDClr } mov (16) CUR_TEMP_B(5,16)<1> SRC_YB(6,8)<16;4,1> { NoDDChk } mov (16) CUR_TEMP_B(6,0)<1> SRC_YB(0,12)<16;4,1> { NoDDClr } mov (16) CUR_TEMP_B(6,16)<1> SRC_YB(2,12)<16;4,1> { NoDDChk } mov (16) CUR_TEMP_B(7,0)<1> SRC_YB(4,12)<16;4,1> { NoDDClr } mov (16) CUR_TEMP_B(7,16)<1> SRC_YB(6,12)<16;4,1> { NoDDChk } // The second step mov (16) SRC_YB(0,0)<1> CUR_TEMP_B(0,0)<32;8,4> { NoDDClr } mov (16) SRC_YB(0,16)<1> CUR_TEMP_B(0,1)<32;8,4> { NoDDChk } mov (16) SRC_YB(1,0)<1> CUR_TEMP_B(0,2)<32;8,4> { NoDDClr } mov (16) SRC_YB(1,16)<1> CUR_TEMP_B(0,3)<32;8,4> { NoDDChk } mov (16) SRC_YB(2,0)<1> CUR_TEMP_B(2,0)<32;8,4> { NoDDClr } mov (16) SRC_YB(2,16)<1> CUR_TEMP_B(2,1)<32;8,4> { NoDDChk } mov (16) SRC_YB(3,0)<1> CUR_TEMP_B(2,2)<32;8,4> { NoDDClr } mov (16) SRC_YB(3,16)<1> CUR_TEMP_B(2,3)<32;8,4> { NoDDChk } mov (16) SRC_YB(4,0)<1> CUR_TEMP_B(4,0)<32;8,4> { NoDDClr } mov (16) SRC_YB(4,16)<1> CUR_TEMP_B(4,1)<32;8,4> { NoDDChk } mov (16) SRC_YB(5,0)<1> CUR_TEMP_B(4,2)<32;8,4> { NoDDClr } mov (16) SRC_YB(5,16)<1> CUR_TEMP_B(4,3)<32;8,4> { NoDDChk } mov (16) SRC_YB(6,0)<1> CUR_TEMP_B(6,0)<32;8,4> { NoDDClr } mov (16) SRC_YB(6,16)<1> CUR_TEMP_B(6,1)<32;8,4> { NoDDChk } mov (16) SRC_YB(7,0)<1> CUR_TEMP_B(6,2)<32;8,4> { NoDDClr } mov (16) SRC_YB(7,16)<1> CUR_TEMP_B(6,3)<32;8,4> { NoDDChk } // Y is transposed. intel-driver-1.3.0/src/shaders/h264/ildb/Transpose_Cur_Y_4x16.asm000066400000000000000000000107251231401140700242750ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////////////////////////////////////////////////////////////////////////////////////// // Module name: Transpose_Y_4x16.asm // // Transpose a 4x16 internal planar to 16x4 internal planar block. // The src block is 16x16. Right moft 4 columns are transposed. // //---------------------------------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region is :ub // SRC_YB: SRC_YB Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8 GRFs // // Temp buffer: // BUF_B: BUF_B Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8 GRFs // ////////////////////////////////////////////////////////////////////////////////////////// #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDDB:w #endif // Transpose Y (4x16) right most 4 columns // +-----------------------+-----------------------+-----------------------+-----------------------+ // |1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |5f 5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50 4f 4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70 6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |9f 9e 9d 9c 9b 9a 99 98 97 96 95 94 93 92 91 90 8f 8e 8d 8c 8b 8a 89 88 87 86 85 84 83 82 81 80| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |bf be bd bc bb ba b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 af ae ad ac ab aa a9 a8 a7 a6 a5 a4 a3 a2 a1 a0| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cf ce cd cc cb ca c9 c8 c7 c6 c5 c4 c3 c2 c1 c0| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |ff fe fd fc fb fa f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 ef ee ed ec eb ea e9 e8 e7 e6 e5 e4 e3 e2 e1 e0| // +-----------------------+-----------------------+-----------------------+-----------------------+ // The first step // +-----------------------+-----------------------+-----------------------+-----------------------+ // |7f 7e 7d 7c 6f 6e 6d 6c 5f 5e 5d 5c 4f 4e 4d 4c 3f 3e 3d 3c 2f 2e 2d 2c 1f 1e 1d 1c 0f 0e 0d 0c| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |ff fe fd fc ef ee ed ec df de dd dc cf ce cd cc bf be bd bc af ae ad ac 9f 9e 9d 9c 8f 8e 8d 8c| // +-----------------------+-----------------------+-----------------------+-----------------------+ // The second step // +-----------------------+-----------------------+-----------------------+-----------------------+ // |fd ed dd cd bd ad 9d 8d 7d 6d 5d 4d 3d 2d 1d 0d fc ec dc cc bc ac 9c 8c 7c 6c 5c 4c 3c 2c 1c 0c| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |ff ef df cf bf af 9f 8f 7f 6f 5f 4f 3f 2f 1f 0f fe ee de ce be ae 9e 8e 7e 6e 5e 4e 3e 2e 1e 0e| // +-----------------------+-----------------------+-----------------------+-----------------------+ mov (16) LEFT_TEMP_B(0,0)<1> SRC_YB(0,12)<16;4,1> { NoDDClr } mov (16) LEFT_TEMP_B(0,16)<1> SRC_YB(2,12)<16;4,1> { NoDDChk } mov (16) LEFT_TEMP_B(1,0)<1> SRC_YB(4,12)<16;4,1> { NoDDClr } mov (16) LEFT_TEMP_B(1,16)<1> SRC_YB(6,12)<16;4,1> { NoDDChk } // The second step mov (16) LEFT_TEMP_B(2,0)<1> LEFT_TEMP_B(0,0)<32;8,4> { NoDDClr } mov (16) LEFT_TEMP_B(2,16)<1> LEFT_TEMP_B(0,1)<32;8,4> { NoDDChk } mov (16) LEFT_TEMP_B(3,0)<1> LEFT_TEMP_B(0,2)<32;8,4> { NoDDClr } mov (16) LEFT_TEMP_B(3,16)<1> LEFT_TEMP_B(0,3)<32;8,4> { NoDDChk } // Y is now transposed. the result is in LEFT_TEMP_B(2) and LEFT_TEMP_B(3). intel-driver-1.3.0/src/shaders/h264/ildb/Transpose_Cur_Y_Right_Most_4x16.asm000066400000000000000000000034211231401140700264270ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Transpose cur Y right most 4x16 to 16x4 // Assume source is LEFT_TEMP_B(0), and detination is LEFT_TEMP_B(2) // Input received from dport: // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 72 71 70 63 62 61 60 53 52 51 50 43 42 41 40 33 32 31 30 23 22 21 20 13 12 11 10 03 02 01 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 f2 f1 f0 e3 e2 e1 e0 d3 d2 d1 d0 c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0 93 92 91 90 83 82 81 80| // +-----------------------+-----------------------+-----------------------+-----------------------+ // Output of transpose: <1> <= <32;8,4> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f1 e1 d1 c1 b1 a1 91 81 71 61 51 41 31 21 11 01 f0 e0 d0 c0 b0 a0 90 80 70 60 50 40 30 20 10 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 e3 d3 c3 b3 a3 93 83 73 63 53 43 33 23 13 03 f2 e2 d2 c2 b2 a2 92 82 72 62 52 42 32 22 12 02| // +-----------------------+-----------------------+-----------------------+-----------------------+ // Transpose the data, also occupy 2 GRFs mov (16) LEFT_TEMP_B(2)<1> LEFT_TEMP_B(0, 0)<32;8,4> { NoDDClr } mov (16) LEFT_TEMP_B(2, 16)<1> LEFT_TEMP_B(0, 1)<32;8,4> { NoDDChk } mov (16) LEFT_TEMP_B(3)<1> LEFT_TEMP_B(0, 2)<32;8,4> { NoDDClr } mov (16) LEFT_TEMP_B(3, 16)<1> LEFT_TEMP_B(0, 3)<32;8,4> { NoDDChk } intel-driver-1.3.0/src/shaders/h264/ildb/Transpose_Left_UV_2x8.asm000066400000000000000000000025561231401140700245020ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Transpose left MB 2x8 to 8x2 // Assume source is LEFT_TEMP_W, and detination is PREV_MB_UW // Input from dport for transpose: // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 70 70 61 61 60 60 51 51 50 50 41 41 40 40 31 31 30 30 21 21 20 20 11 11 10 10 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // Output of transpose: <1> <=== <16;8,2>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 61 61 51 51 41 41 31 31 21 21 11 11 01 01 70 70 60 60 50 50 40 40 30 30 20 20 10 10 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // mov (8) PREV_MB_UW(0,0)<1> BUF_W(0,0)<16;8,2> { NoDDClr } // mov (8) PREV_MB_UW(0,8)<1> BUF_W(0,1)<16;8,2> { NoDDChk } // mov (8) PREV_MB_UW(0,0)<1> LEFT_TEMP_W(0,0)<16;8,2> { NoDDClr } // mov (8) PREV_MB_UW(0,8)<1> LEFT_TEMP_W(0,1)<16;8,2> { NoDDChk } mov (16) PREV_MB_UW(0,0)<1> LEFT_TEMP_W(0,0)<1;8,2> intel-driver-1.3.0/src/shaders/h264/ildb/Transpose_Left_Y_4x16.asm000066400000000000000000000033751231401140700244410ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Transpose left MB 4x16 to 16x4 // Assume source is LEFT_TEMP_B, and detination is PREV_MB_YB // Input received from dport: // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 72 71 70 63 62 61 60 53 52 51 50 43 42 41 40 33 32 31 30 23 22 21 20 13 12 11 10 03 02 01 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 f2 f1 f0 e3 e2 e1 e0 d3 d2 d1 d0 c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0 93 92 91 90 83 82 81 80| // +-----------------------+-----------------------+-----------------------+-----------------------+ // Output of transpose: <1> <= <32;8,4> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f1 e1 d1 c1 b1 a1 91 81 71 61 51 41 31 21 11 01 f0 e0 d0 c0 b0 a0 90 80 70 60 50 40 30 20 10 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 e3 d3 c3 b3 a3 93 83 73 63 53 43 33 23 13 03 f2 e2 d2 c2 b2 a2 92 82 72 62 52 42 32 22 12 02| // +-----------------------+-----------------------+-----------------------+-----------------------+ // Transpose the data, also occupy 2 GRFs mov (16) PREV_MB_YB(0)<1> LEFT_TEMP_B(0, 0)<32;8,4> { NoDDClr } mov (16) PREV_MB_YB(0, 16)<1> LEFT_TEMP_B(0, 1)<32;8,4> { NoDDChk } mov (16) PREV_MB_YB(1)<1> LEFT_TEMP_B(0, 2)<32;8,4> { NoDDClr } mov (16) PREV_MB_YB(1, 16)<1> LEFT_TEMP_B(0, 3)<32;8,4> { NoDDChk } intel-driver-1.3.0/src/shaders/h264/ildb/loadNV12_16x16T.asm000066400000000000000000000040761231401140700227550ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: loadNV12_16x16T.asm // // Load and transpose NV12 16x16 block // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_YD: SRC_YD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 8 GRFs // SRC_UD: SRC_UD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud (U+V for NV12) // 4 GRFs // // Source region is :ub. The same region as :ud region // SRC_YB: SRC_YB Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8 GRFs // SRC_UB: SRC_UB Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 2 GRFs // SRC_VB: SRC_VB Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 2 GRFs // // Binding table index: // BI_SRC_Y: Binding table index of Y surface // BI_SRC_UV: Binding table index of UV surface (NV12) // // Temp buffer: // BUF_B: BUF_B Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD1:w #endif // Read Y mov (2) MSGSRC.0<1>:ud ORIX_CUR<2;2,1>:w // Block origin mov (1) MSGSRC.2<1>:ud 0x000F000F:ud // Block width and height (16x16) send (8) SRC_YD(0)<1> MSGHDRY MSGSRC<8;8,1>:ud DAPREAD RESP_LEN(8)+DWBRMSGDSC_RC+BI_SRC_Y // Read 8 GRFs // Read U+V asr (1) MSGSRC.1:ud MSGSRC.1:ud 1:w // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2<1>:ud 0x0007000F:ud // NV12 U+V block width and height (16x8) send (8) SRC_UD(0)<1> MSGHDRU MSGSRC<8;8,1>:ud DAPREAD RESP_LEN(4)+DWBRMSGDSC_RC+BI_SRC_UV // Read 4 GRFs #include "TransposeNV12_16x16.asm" // #include "Transpose_Y_16x16.asm" // #include "Transpose_NV12_UV_16x8.asm" // End of loadNV12_16x16T intel-driver-1.3.0/src/shaders/h264/ildb/loadNV12_16x4.asm000066400000000000000000000042001231401140700225330ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module Name: Loadnv12_16X4.Asm // // Load Nv12 16X4 Block // //---------------------------------------------------------------- // Symbols Need To Be Defined Before Including This Module // // Source Region In :Ud // Src_Yd: Src_Yd Base=Rxx Elementsize=4 Srcregion=Region(8,1) Type=Ud // 3 Grfs (2 For Y, 1 For U+V) // // Source Region Is :Ub. The Same Region As :Ud Region // Src_Yb: Src_Yb Base=Rxx Elementsize=1 Srcregion=Region(16,1) Type=Ub // 2 Grfs // Src_Ub: Src_Ub Base=Rxx Elementsize=1 Srcregion=Region(16,1) Type=Ub // 0.5 Grf // Src_Vb: Src_Vb Base=Rxx Elementsize=1 Srcregion=Region(16,1) Type=Ub // 0.5 Grf // // Binding Table Index: // Bi_Src_Y: Binding Table Index Of Y Surface // Bi_Src_UV: Binding Table Index Of UV Surface (Nv12) // // Temp Buffer: // Buf_D: Buf_D Base=Rxx Elementsize=4 Srcregion=Region(8,1) Type=Ud // Buf_B: Buf_B Base=Rxx Elementsize=1 Srcregion=Region(16,1) Type=Ub // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD2:w #endif // Read Y mov (2) MSGSRC.0<1>:ud ORIX<2;2,1>:w // Block origin mov (1) MSGSRC.2<1>:ud 0x0003000F:ud // Block width and height (16x4) send (8) PREV_MB_YD(0)<1> MSGHDRY MSGSRC<8;8,1>:ud DAPREAD RESP_LEN(2)+DWBRMSGDSC_RC+BI_SRC_Y // Read 2 GRFs // Read U+V asr (1) MSGSRC.1:ud MSGSRC.1:ud 1:w // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2<1>:ud 0x0001000F:ud // NV12 U+V block width and height (16x2) // Load NV12 U+V tp a temp buf send (8) BUF_D(0)<1> MSGHDRU MSGSRC<8;8,1>:ud DAPREAD RESP_LEN(1)+DWBRMSGDSC_RC+BI_SRC_UV // Read 1 GRF // Convert NV12 U+V to internal planar U and V and place them right after Y. // mov (16) SRC_UB(0,0)<1> BUF_B(0,0)<32;16,2> // mov (16) SRC_VB(0,0)<1> BUF_B(0,1)<32;16,2> // End of loadNV12_16x4.asm intel-driver-1.3.0/src/shaders/h264/ildb/load_Cur_UV_8x8T.asm000066400000000000000000000046251231401140700234330ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: load_Cur_UV_8x8T.asm // // Load and transpose UV 8x8 block (NV12: 8x8U and 8x8V mixed) // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_UD: SRC_UD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud (U+V for NV12) // 4 GRFs // // Binding table index: // BI_SRC_UV: Binding table index of UV surface (NV12) // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD1:w #endif // Read U+V blk #if defined(_PROGRESSIVE) mov (1) MSGSRC.0:ud ORIX_CUR:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_CUR:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x0007000F:ud { NoDDChk } // NV12 U+V block width and height (16x8 bytes) //send (8) SRC_UD(0)<1> MSGHDRU MSGSRC<8;8,1>:ud DWBRMSGDSC_SC+0x00040000+BI_SRC_UV mov (1) MSGDSC RESP_LEN(4)+DWBRMSGDSC_SC+BI_SRC_UV:ud #endif #if defined(_FIELD) // cmp.z.f0.0 (1) NULLREGW PicTypeC:w 0:w // Get pic type flag and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag // they are used later in this file mov (1) MSGSRC.0:ud ORIX_CUR:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_CUR:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x0007000F:ud { NoDDChk } // NV12 U+V block width and height (16x8 bytes) // Set message descriptor // Frame picture // (f0.0) mov (1) MSGDSC RESP_LEN(4)+DWBRMSGDSC_SC+BI_SRC_UV:ud // Read 4 GRFs from SRC_UV // (f0.0) jmpi load_UV_8x8T // Field picture (f0.1) mov (1) MSGDSC RESP_LEN(4)+DWBRMSGDSC_SC_BF+BI_SRC_UV:ud // Read 4 GRFs from SRC_UV bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(4)+DWBRMSGDSC_SC_TF+BI_SRC_UV:ud // Read 4 GRFs from SRC_UV top field //load_UV_8x8T: #endif send (8) SRC_UD(0)<1> MSGHDRU MSGSRC<8;8,1>:ud DAPREAD MSGDSC // #include "Transpose_Cur_UV_8x8.asm" // End of load_UV_8x8T intel-driver-1.3.0/src/shaders/h264/ildb/load_Cur_UV_8x8T_Mbaff.asm000066400000000000000000000043301231401140700245170ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: load_Cur_UV_8x8T.asm // // Load and transpose UV 8x8 block (NV12: 8x8U and 8x8V mixed) // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_UD: SRC_UD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud (U+V for NV12) // 4 GRFs // // Binding table index: // BI_SRC_UV: Binding table index of UV surface (NV12) // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD1:w #endif // FieldModeCurrentMbFlag determines how to access left MB and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag // Read U+V mov (1) MSGSRC.0:ud ORIX_CUR:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_CUR:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x0007000F:ud { NoDDChk } // NV12 U+V block width and height (16x8 bytes) // Set message descriptor (f0.0) if (1) ILDB_LABEL(ELSE_UV_8X8T) // Frame picture mov (1) MSGDSC RESP_LEN(4)+DWBRMSGDSC_SC+BI_SRC_UV:ud // Read 4 GRFs from SRC_UV (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 8:w // Add vertical offset 8 for bot MB in MBAFF mode ILDB_LABEL(ELSE_UV_8X8T): else (1) ILDB_LABEL(ENDIF_UV_8X8T) // Field picture (f0.1) mov (1) MSGDSC RESP_LEN(4)+DWBRMSGDSC_SC_BF+BI_SRC_UV:ud // Read 4 GRFs from SRC_UV bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(4)+DWBRMSGDSC_SC_TF+BI_SRC_UV:ud // Read 4 GRFs from SRC_UV top field asr (1) MSGSRC.1:d MSGSRC.1:d 1:w // Reduce y by half in field access mode endif ILDB_LABEL(ENDIF_UV_8X8T): send (8) SRC_UD(0)<1> MSGHDRU MSGSRC<8;8,1>:ud DAPREAD MSGDSC // #include "Transpose_Cur_UV_8x8.asm" // End of load_UV_8x8T intel-driver-1.3.0/src/shaders/h264/ildb/load_Cur_UV_Right_Most_2x8.asm000066400000000000000000000043611231401140700254350ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module Name: Load_Cur_UV_Right_Most_2X8.Asm #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD0:w #endif #if defined(_PROGRESSIVE) // Read U+V, (UV MB size = 16x8) add (1) MSGSRC.0:ud ORIX_CUR:w 12:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_CUR:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x00070003:ud { NoDDChk } // NV12 U+V block width and height (4x8) send (8) LEFT_TEMP_D(0)<1> MSGHDRU MSGSRC<8;8,1>:ud DAPREAD RESP_LEN(1)+DWBRMSGDSC_RC+BI_DEST_UV #endif #if defined(_FIELD) || defined(_MBAFF) // FieldModeCurrentMbFlag determines how to access left MB and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag // Read U+V add (1) MSGSRC.0:ud ORIX_CUR:w 12:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_CUR:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x00070003:ud { NoDDChk } // NV12 U+V block width and height (4x8) // Load NV12 U+V // Set message descriptor (f0.0) if (1) ILDB_LABEL(ELSE_Y_2x8T) // Frame picture mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC+BI_DEST_UV:ud // Read 1 GRF from SRC_UV (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 8:w // Add vertical offset 8 for bot MB in MBAFF mode ILDB_LABEL(ELSE_Y_2x8T): else (1) ILDB_LABEL(ENDIF_Y_2x8T) // Field picture (f0.1) mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC_BF+BI_DEST_UV:ud // Read 1 GRF from SRC_Y bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC_TF+BI_DEST_UV:ud // Read 1 GRF from SRC_Y top field endif ILDB_LABEL(ENDIF_Y_2x8T): // Read 1 GRF from DEST surface as the above MB has been deblocked. // send (8) BUF_D(0)<1> MSGHDRU MSGSRC<8;8,1>:ud MSGDSC send (8) LEFT_TEMP_D(0)<1> MSGHDRU MSGSRC<8;8,1>:ud DAPREAD MSGDSC #endif intel-driver-1.3.0/src/shaders/h264/ildb/load_Cur_Y_16x16T.asm000066400000000000000000000042031231401140700234370ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: load_Y_16x16T.asm // // Load and transpose Y 16x16 block // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_YD: SRC_YD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 8 GRFs // // Binding table index: // BI_SRC_Y: Binding table index of Y surface // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD1:w #endif // Read Y #if defined(_PROGRESSIVE) mov (2) MSGSRC.0<1>:ud ORIX_CUR<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x000F000F:ud { NoDDChk } // Block width and height (16x16) //send (8) SRC_YD(0)<1> MSGHDRC MSGSRC<8;8,1>:ud DWBRMSGDSC_SMPLR+0x00080000+BI_SRC_Y mov (1) MSGDSC RESP_LEN(8)+DWBRMSGDSC_SC+BI_SRC_Y:ud #endif #if defined(_FIELD) // cmp.z.f0.0 (1) NULLREGW PicTypeC:w 0:w // Get pic type flag and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag // they are used later in this file mov (2) MSGSRC.0<1>:ud ORIX_CUR<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x000F000F:ud { NoDDChk } // Block width and height (16x16) // Set message descriptor // Frame picture // (f0.0) mov (1) MSGDSC RESP_LEN(8)+DWBRMSGDSC_SC+BI_SRC_Y:ud // Read 8 GRFs from SRC_Y // (f0.0) jmpi load_Y_16x16T // Non frame picture (f0.1) mov (1) MSGDSC RESP_LEN(8)+DWBRMSGDSC_SC_BF+BI_SRC_Y:ud // Read 8 GRFs from SRC_Y bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(8)+DWBRMSGDSC_SC_TF+BI_SRC_Y:ud // Read 8 GRFs from SRC_Y top field //load_Y_16x16T: #endif send (8) SRC_YD(0)<1> MSGHDRC MSGSRC<8;8,1>:ud DAPREAD MSGDSC // #include "Transpose_Cur_Y_16x16.asm" // End of load_Y_16x16T intel-driver-1.3.0/src/shaders/h264/ildb/load_Cur_Y_16x16T_Mbaff.asm000066400000000000000000000040721231401140700245360ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: load_Y_16x16T.asm // // Load and transpose Y 16x16 block // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_YD: SRC_YD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 8 GRFs // // Binding table index: // BI_SRC_Y: Binding table index of Y surface // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD1:w #endif // FieldModeCurrentMbFlag determines how to access left MB and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag // Read Y mov (2) MSGSRC.0<1>:d ORIX_CUR<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x000F000F:ud { NoDDChk } // Block width and height (16x16) // Set message descriptor, etc. (f0.0) if (1) ILDB_LABEL(ELSE_Y_16x16T) // Frame picture mov (1) MSGDSC RESP_LEN(8)+DWBRMSGDSC_SC+BI_SRC_Y:ud // Read 8 GRFs from SRC_Y (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 16:w // Add vertical offset 16 for bot MB in MBAFF mode ILDB_LABEL(ELSE_Y_16x16T): else (1) ILDB_LABEL(ENDIF_Y_16x16T) // Field picture (f0.1) mov (1) MSGDSC RESP_LEN(8)+DWBRMSGDSC_SC_BF+BI_SRC_Y:ud // Read 8 GRFs from SRC_Y bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(8)+DWBRMSGDSC_SC_TF+BI_SRC_Y:ud // Read 8 GRFs from SRC_Y top field asr (1) MSGSRC.1:d MSGSRC.1:d 1:w // Reduce y by half in field access mode endif ILDB_LABEL(ENDIF_Y_16x16T): send (8) SRC_YD(0)<1> MSGHDRY MSGSRC<8;8,1>:ud DAPREAD MSGDSC // #include "Transpose_Cur_Y_16x16.asm" // End of load_Y_16x16T intel-driver-1.3.0/src/shaders/h264/ildb/load_Cur_Y_Right_Most_4x16.asm000066400000000000000000000071521231401140700253750ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: load_Cur_Y_Right_Most_4x16.asm // // Load luma cur MB right most 4x16 into LEFT_TEMP_B #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD0:w #endif #if defined(_PROGRESSIVE) // Read Y add (1) MSGSRC.0<1>:ud ORIX_CUR:w 12:w { NoDDClr } // Block origin, move right 12 bytes mov (1) MSGSRC.1<1>:ud ORIY_CUR:w { NoDDClr, NoDDChk } // Block origin mov (1) MSGSRC.2<1>:ud 0x000F0003:ud { NoDDChk } // Block width and height (4x16) send (8) LEFT_TEMP_D(0)<1> MSGHDRL MSGSRC<8;8,1>:ud DAPREAD RESP_LEN(2)+DWBRMSGDSC_RC+BI_DEST_Y #endif #if defined(_FIELD) || defined(_MBAFF) // FieldModeCurrentMbFlag determines how to access left MB and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag // Read Y add (1) MSGSRC.0<1>:ud ORIX_CUR:w 12:w { NoDDClr } // Block origin, move right 12 bytes mov (1) MSGSRC.1<1>:ud ORIY_CUR:w { NoDDClr, NoDDChk } // Block origin mov (1) MSGSRC.2<1>:ud 0x000F0003:ud { NoDDChk } // Block width and height (4x16) // Set message descriptor, etc. (f0.0) if (1) ILDB_LABEL(ELSE_Y_4x16T) // Frame picture mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC+BI_DEST_Y:ud // Read 2 GRFs from DEST_Y (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 16:w // Add vertical offset 16 for bot MB in MBAFF mode ILDB_LABEL(ELSE_Y_4x16T): else (1) ILDB_LABEL(ENDIF_Y_4x16T) // Field picture (f0.1) mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC_BF+BI_DEST_Y:ud // Read 2 GRFs from DEST_Y bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC_TF+BI_DEST_Y:ud // Read 2 GRFs from DEST_Y top field endif ILDB_LABEL(ENDIF_Y_4x16T): // send (8) BUF_D(0)<1> MSGHDRY MSGSRC<8;8,1>:ud MSGDSC send (8) LEFT_TEMP_D(0)<1> MSGHDRL MSGSRC<8;8,1>:ud DAPREAD MSGDSC #endif // Transpose 4x16 to 16x4 // Input received from dport: // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 72 71 70 63 62 61 60 53 52 51 50 43 42 41 40 33 32 31 30 23 22 21 20 13 12 11 10 03 02 01 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 f2 f1 f0 e3 e2 e1 e0 d3 d2 d1 d0 c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0 93 92 91 90 83 82 81 80| // +-----------------------+-----------------------+-----------------------+-----------------------+ // Output of transpose: <1> <= <32;8,4> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f1 e1 d1 c1 b1 a1 91 81 71 61 51 41 31 21 11 01 f0 e0 d0 c0 b0 a0 90 80 70 60 50 40 30 20 10 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 e3 d3 c3 b3 a3 93 83 73 63 53 43 33 23 13 03 f2 e2 d2 c2 b2 a2 92 82 72 62 52 42 32 22 12 02| // +-----------------------+-----------------------+-----------------------+-----------------------+ /* // Transpose the data, also occupy 2 GRFs mov (16) PREV_MB_YB(0)<1> BUF_B(0, 0)<32;8,4> { NoDDClr } mov (16) PREV_MB_YB(0, 16)<1> BUF_B(0, 1)<32;8,4> { NoDDChk } mov (16) PREV_MB_YB(1)<1> BUF_B(0, 2)<32;8,4> { NoDDClr } mov (16) PREV_MB_YB(1, 16)<1> BUF_B(0, 3)<32;8,4> { NoDDChk } */ // End of load_Y_4x16T intel-driver-1.3.0/src/shaders/h264/ildb/load_Left_UV_2x8T.asm000066400000000000000000000052251231401140700235630ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module Name: Load_Left_UV_2X8T.Asm // // Load UV 8X2 Block // //---------------------------------------------------------------- // Symbols ceed To be defined before including this module // // Source Region Is :UB // BUF_D: BUF_D Base=Rxx Elementsize=4 Srcregion=Region(8,1) Type=UD // Binding Table Index: // BI_SRC_UV: Binding Table Index Of UV Surface (NV12) // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD0:w #endif #if defined(_PROGRESSIVE) // Read U+V mov (1) MSGSRC.0:ud ORIX_LEFT:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_LEFT:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x00070003:ud { NoDDChk } // NV12 U+V block width and height (4x8) send (8) LEFT_TEMP_D(0)<1> MSGHDRU MSGSRC<8;8,1>:ud DAPREAD RESP_LEN(1)+DWBRMSGDSC_RC+BI_DEST_UV #endif #if defined(_FIELD) || defined(_MBAFF) // FieldModeCurrentMbFlag determines how to access left MB and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag // Read U+V mov (1) MSGSRC.0:ud ORIX_LEFT:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_LEFT:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x00070003:ud { NoDDChk } // NV12 U+V block width and height (4x8) // Load NV12 U+V // Set message descriptor (f0.0) if (1) ILDB_LABEL(ELSE_Y_2x8T) // Frame picture mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC+BI_DEST_UV:ud // Read 1 GRF from SRC_UV (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 8:w // Add vertical offset 8 for bot MB in MBAFF mode ILDB_LABEL(ELSE_Y_2x8T): else (1) ILDB_LABEL(ENDIF_Y_2x8T) // Field picture (f0.1) mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC_BF+BI_DEST_UV:ud // Read 1 GRF from SRC_Y bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC_TF+BI_DEST_UV:ud // Read 1 GRF from SRC_Y top field endif ILDB_LABEL(ENDIF_Y_2x8T): // Read 1 GRF from DEST surface as the above MB has been deblocked. // send (8) BUF_D(0)<1> MSGHDRU MSGSRC<8;8,1>:ud MSGDSC send (8) LEFT_TEMP_D(0)<1> MSGHDRU MSGSRC<8;8,1>:ud DAPREAD MSGDSC #endif // End of load_Left_UV_2x8T.asm intel-driver-1.3.0/src/shaders/h264/ildb/load_Left_UV_2x8T_Mbaff.asm000066400000000000000000000060771231401140700246640ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module Name: Load_Left_UV_2X8T.Asm // // Load UV 8X2 Block // //---------------------------------------------------------------- // Symbols ceed To be defined before including this module // // Source Region Is :UB // BUF_D: BUF_D Base=Rxx Elementsize=4 Srcregion=Region(8,1) Type=UD // Binding Table Index: // BI_SRC_UV: Binding Table Index Of UV Surface (NV12) // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD0:w #endif // FieldModeCurrentMbFlag determines how to access left MB and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag // Read U+V mov (1) MSGSRC.0:ud ORIX_LEFT:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_LEFT:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x00070003:ud { NoDDChk } // NV12 U+V block width and height (4x8) // Load NV12 U+V // Set message descriptor (f0.0) if (1) ILDB_LABEL(ELSE_Y_2x8T) // Frame picture mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC+BI_DEST_UV:ud // Read 1 GRF from SRC_UV (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 8:w // Add vertical offset 8 for bot MB in MBAFF mode ILDB_LABEL(ELSE_Y_2x8T): else (1) ILDB_LABEL(ENDIF_Y_2x8T) // Field picture (f0.1) mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC_BF+BI_DEST_UV:ud // Read 1 GRF from SRC_Y bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC_TF+BI_DEST_UV:ud // Read 1 GRF from SRC_Y top field asr (1) MSGSRC.1:d MSGSRC.1:d 1:w // Reduce y by half in field access mode endif ILDB_LABEL(ENDIF_Y_2x8T): // Read 1 GRF from DEST surface as the above MB has been deblocked. // send (8) BUF_D(0)<1> MSGHDRU MSGSRC<8;8,1>:ud MSGDSC send (8) LEFT_TEMP_D(0)<1> MSGHDRU MSGSRC<8;8,1>:ud DAPREAD MSGDSC // Input from dport for transpose: // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 70 70 61 61 60 60 51 51 50 50 41 41 40 40 31 31 30 30 21 21 20 20 11 11 10 10 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // Output of transpose: <1> <=== <16;8,2>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 61 61 51 51 41 41 31 31 21 21 11 11 01 01 70 70 60 60 50 50 40 40 30 30 20 20 10 10 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ /* mov (8) PREV_MB_UW(0,0)<1> BUF_W(0,0)<16;8,2> { NoDDClr } mov (8) PREV_MB_UW(0,8)<1> BUF_W(0,1)<16;8,2> { NoDDChk } */ // End of load_Left_UV_2x8T.asm intel-driver-1.3.0/src/shaders/h264/ildb/load_Left_Y_4x16T.asm000066400000000000000000000076061231401140700235270ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: load_Y_4x16T.asm // // Load luma left MB 4x16 and transpose 4x16 to 16x4. // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // PREV_MB_YD: PREV_MB_YD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 2 GRFs // // Binding table index: // BI_SRC_Y: Binding table index of Y surface // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD0:w #endif #if defined(_PROGRESSIVE) // Read Y mov (2) MSGSRC.0<1>:ud ORIX_LEFT<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x000F0003:ud { NoDDChk } // Block width and height (4x16) // mov (1) MSGDSC DWBRMSGDSC_RC+0x00020000+BI_DEST_Y:ud // Read 2 GRFs from DEST_Y send (8) LEFT_TEMP_D(0)<1> MSGHDRL MSGSRC<8;8,1>:ud DAPREAD RESP_LEN(2)+DWBRMSGDSC_RC+BI_DEST_Y #endif #if defined(_FIELD) || defined(_MBAFF) // FieldModeCurrentMbFlag determines how to access left MB and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag // Read Y mov (2) MSGSRC.0<1>:ud ORIX_LEFT<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x000F0003:ud { NoDDChk } // Block width and height (4x16) // Set message descriptor, etc. (f0.0) if (1) ILDB_LABEL(ELSE_Y_4x16T) // Frame picture mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC+BI_DEST_Y:ud // Read 2 GRFs from DEST_Y (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 16:w // Add vertical offset 16 for bot MB in MBAFF mode ILDB_LABEL(ELSE_Y_4x16T): else (1) ILDB_LABEL(ENDIF_Y_4x16T) // Field picture (f0.1) mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC_BF+BI_DEST_Y:ud // Read 2 GRFs from DEST_Y bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC_TF+BI_DEST_Y:ud // Read 2 GRFs from DEST_Y top field endif ILDB_LABEL(ENDIF_Y_4x16T): // send (8) BUF_D(0)<1> MSGHDRY MSGSRC<8;8,1>:ud MSGDSC send (8) LEFT_TEMP_D(0)<1> MSGHDRL MSGSRC<8;8,1>:ud DAPREAD MSGDSC #endif // Transpose 4x16 to 16x4 // Input received from dport: // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 72 71 70 63 62 61 60 53 52 51 50 43 42 41 40 33 32 31 30 23 22 21 20 13 12 11 10 03 02 01 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 f2 f1 f0 e3 e2 e1 e0 d3 d2 d1 d0 c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0 93 92 91 90 83 82 81 80| // +-----------------------+-----------------------+-----------------------+-----------------------+ // Output of transpose: <1> <= <32;8,4> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f1 e1 d1 c1 b1 a1 91 81 71 61 51 41 31 21 11 01 f0 e0 d0 c0 b0 a0 90 80 70 60 50 40 30 20 10 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 e3 d3 c3 b3 a3 93 83 73 63 53 43 33 23 13 03 f2 e2 d2 c2 b2 a2 92 82 72 62 52 42 32 22 12 02| // +-----------------------+-----------------------+-----------------------+-----------------------+ /* // Transpose the data, also occupy 2 GRFs mov (16) PREV_MB_YB(0)<1> BUF_B(0, 0)<32;8,4> { NoDDClr } mov (16) PREV_MB_YB(0, 16)<1> BUF_B(0, 1)<32;8,4> { NoDDChk } mov (16) PREV_MB_YB(1)<1> BUF_B(0, 2)<32;8,4> { NoDDClr } mov (16) PREV_MB_YB(1, 16)<1> BUF_B(0, 3)<32;8,4> { NoDDChk } */ // End of load_Y_4x16T intel-driver-1.3.0/src/shaders/h264/ildb/load_Left_Y_4x16T_Mbaff.asm000066400000000000000000000067261231401140700246240ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: load_Y_4x16T.asm // // Load luma left MB 4x16 and transpose 4x16 to 16x4. // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // PREV_MB_YD: PREV_MB_YD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 2 GRFs // // Binding table index: // BI_SRC_Y: Binding table index of Y surface // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD0:w #endif // FieldModeCurrentMbFlag determines how to access left MB and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag // Read Y mov (2) MSGSRC.0<1>:ud ORIX_LEFT<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x000F0003:ud { NoDDChk } // Block width and height (4x16) // Set message descriptor, etc. (f0.0) if (1) ELSE_Y_4x16T // Frame picture mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC+BI_DEST_Y:ud // Read 2 GRFs from DEST_Y (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 16:w // Add vertical offset 16 for bot MB in MBAFF mode ELSE_Y_4x16T: else (1) ENDIF_Y_4x16T // Field picture (f0.1) mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC_BF+BI_DEST_Y:ud // Read 2 GRFs from DEST_Y bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC_TF+BI_DEST_Y:ud // Read 2 GRFs from DEST_Y top field asr (1) MSGSRC.1:d MSGSRC.1:d 1:w // Reduce y by half in field access mode endif ENDIF_Y_4x16T: // send (8) BUF_D(0)<1> MSGHDRY MSGSRC<8;8,1>:ud MSGDSC send (8) LEFT_TEMP_D(0)<1> MSGHDRL MSGSRC<8;8,1>:ud DAPREAD MSGDSC // Transpose 4x16 to 16x4 // Input received from dport: // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 72 71 70 63 62 61 60 53 52 51 50 43 42 41 40 33 32 31 30 23 22 21 20 13 12 11 10 03 02 01 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 f2 f1 f0 e3 e2 e1 e0 d3 d2 d1 d0 c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0 93 92 91 90 83 82 81 80| // +-----------------------+-----------------------+-----------------------+-----------------------+ // Output of transpose: <1> <= <32;8,4> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f1 e1 d1 c1 b1 a1 91 81 71 61 51 41 31 21 11 01 f0 e0 d0 c0 b0 a0 90 80 70 60 50 40 30 20 10 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 e3 d3 c3 b3 a3 93 83 73 63 53 43 33 23 13 03 f2 e2 d2 c2 b2 a2 92 82 72 62 52 42 32 22 12 02| // +-----------------------+-----------------------+-----------------------+-----------------------+ /* // Transpose the data, also occupy 2 GRFs mov (16) PREV_MB_YB(0)<1> BUF_B(0, 0)<32;8,4> { NoDDClr } mov (16) PREV_MB_YB(0, 16)<1> BUF_B(0, 1)<32;8,4> { NoDDChk } mov (16) PREV_MB_YB(1)<1> BUF_B(0, 2)<32;8,4> { NoDDClr } mov (16) PREV_MB_YB(1, 16)<1> BUF_B(0, 3)<32;8,4> { NoDDChk } */ // End of load_Y_4x16T intel-driver-1.3.0/src/shaders/h264/ildb/load_Top_UV_8x2.asm000066400000000000000000000050371231401140700233100ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module Name: Load_Top_UV_8X2.Asm // // Load UV 8X2 Block // //---------------------------------------------------------------- // Symbols ceed To be defined before including this module // // Source Region Is :UB // BUF_D: BUF_D Base=Rxx Elementsize=4 Srcregion=Region(8,1) Type=UD // Binding Table Index: // BI_SRC_UV: Binding Table Index Of UV Surface (NV12) // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD2:w #endif #if defined(_PROGRESSIVE) // Read U+V mov (1) MSGSRC.0:ud ORIX_TOP:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_TOP:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x0001000F:ud { NoDDChk } // NV12 U+V block width and height (16x2) // Read 1 GRF from DEST surface as the above MB has been deblocked. //send (8) TOP_MB_UD(0)<1> MSGHDRU MSGSRC<8;8,1>:ud RESP_LEN(1)+DWBRMSGDSC_RC+BI_DEST_UV mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC+BI_DEST_UV:ud #endif #if defined(_FIELD) // cmp.z.f0.0 (1) NULLREGW PicTypeC:w 0:w // Get pic type flag and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag // They are used later in this file // Read U+V mov (1) MSGSRC.0:ud ORIX_TOP:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_TOP:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x0001000F:ud { NoDDChk } // NV12 U+V block width and height (16x2) // Load NV12 U+V // Set message descriptor // Frame picture // (f0.0) mov (1) MSGDSC DWBRMSGDSC_RC+0x00010000+BI_DEST_UV:ud // Read 1 GRF from SRC_UV // (f0.0) jmpi Load_Top_UV_8x2 // Field picture (f0.1) mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC_BF+BI_DEST_UV:ud // Read 1 GRF from SRC_Y bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC_TF+BI_DEST_UV:ud // Read 1 GRF from SRC_Y top field //Load_Top_UV_8x2: // Read 1 GRF from DEST surface as the above MB has been deblocked. // send (8) PREV_MB_UD(0)<1> MSGHDRU MSGSRC<8;8,1>:ud MSGDSC #endif send (8) TOP_MB_UD(0)<1> MSGHDRU MSGSRC<8;8,1>:ud DAPREAD MSGDSC // End of load_Top_UV_8x2.asm intel-driver-1.3.0/src/shaders/h264/ildb/load_Top_UV_8x2_Mbaff.asm000066400000000000000000000052261231401140700244030ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module Name: Load_Top_UV_8X2.Asm // // Load UV 8X2 Block // //---------------------------------------------------------------- // Symbols ceed To be defined before including this module // // Source Region Is :UB // BUF_D: BUF_D Base=Rxx Elementsize=4 Srcregion=Region(8,1) Type=UD // Binding Table Index: // BI_SRC_UV: Binding Table Index Of UV Surface (NV12) // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD2:w #endif // FieldModeCurrentMbFlag determines how to access above MB and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Read U+V mov (1) MSGSRC.0:ud ORIX_TOP:w { NoDDClr } // Block origin asr (1) MSGSRC.1:d ORIY_TOP:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x0001000F:ud { NoDDChk } // NV12 U+V block width and height (16x2) // Load NV12 U+V // Set message descriptor (f0.0) if (1) ELSE_UV_8X2 // Frame picture mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC+BI_DEST_UV:ud // Read 1 GRF from SRC_UV // Add vertical offset 8 for bot MB in MBAFF mode (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 8:w // Dual field mode setup and.z.f0.1 (1) NULLREGW DualFieldMode:w 1:w (f0.1) jmpi NOT_DUAL_FIELD_UV add (1) MSGSRC.1:d MSGSRC.1:d -2:w { NoDDClr } // Load 4 lines in stead of 2 mov (1) MSGSRC.2:ud 0x0003000F:ud { NoDDChk } // New block width and height (16x8) add (1) MSGDSC MSGDSC RESP_LEN(1):ud // 1 more GRF to receive NOT_DUAL_FIELD_UV: ELSE_UV_8X2: else (1) ENDIF_UV_8X2 // Field picture asr (1) MSGSRC.1:d ORIY_CUR:w 2:w // asr 1: NV12 U+V block origin y = half of Y comp // asr 1: Reduce y by half in field access mode (f0.1) mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC_BF+BI_DEST_UV:ud // Read 1 GRF from SRC_Y bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC_TF+BI_DEST_UV:ud // Read 1 GRF from SRC_Y top field add (1) MSGSRC.1:d MSGSRC.1:d -2:w // for last 2 rows of above MB endif ENDIF_UV_8X2: // Read 1 GRF from DEST surface as the above MB has been deblocked. send (8) PREV_MB_UD(0)<1> MSGHDRU MSGSRC<8;8,1>:ud DAPREAD MSGDSC // End of load_Top_UV_8x2.asm intel-driver-1.3.0/src/shaders/h264/ildb/load_Top_Y_16x4.asm000066400000000000000000000047621231401140700232530ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module Name: Load_Y_16X4.asm // // Load Y 16X4 Block to PREV_MB_YD // //---------------------------------------------------------------- // Symbols Need To Be Defined Before Including This Module // // Source Region In :Ud // Src_YD: Src_Yd Base=Rxx Elementsize=4 Srcregion=Region(8,1) Type=Ud // 3 Grfs (2 For Y, 1 For U+V) // // Source Region Is :Ub. The Same Region As :Ud Region // Src_YB: Src_Yb Base=Rxx Elementsize=1 Srcregion=Region(16,1) Type=Ub // 2 Grfs // // Binding Table Index: // Bi_Src_Y: Binding Table Index Of Y Surface // // Temp Buffer: // Buf_D: Buf_D Base=Rxx Elementsize=4 Srcregion=Region(8,1) Type=Ud // Buf_B: Buf_B Base=Rxx Elementsize=1 Srcregion=Region(16,1) Type=Ub // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD2:w #endif #if defined(_PROGRESSIVE) // Read Y mov (2) MSGSRC.0<1>:ud ORIX_TOP<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x0003000F:ud { NoDDChk } // Block width and height (16x4) mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC+BI_DEST_Y:ud // Read 2 GRFs from SRC_Y #endif #if defined(_FIELD) // cmp.z.f0.0 (1) NULLREGW PicTypeC:w 0:w // Get pic type flag and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag // they are used later in this file mov (2) MSGSRC.0<1>:ud ORIX_TOP<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x0003000F:ud { NoDDChk } // Block width and height (16x4) // Set message descriptor // Frame picture // (f0.0) mov (1) MSGDSC DWBRMSGDSC_RC+0x00020000+BI_DEST_Y:ud // Read 2 GRFs from SRC_Y // (f0.0) jmpi load_Y_16x4 // Field picture (f0.1) mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC_BF+BI_DEST_Y:ud // Read 2 GRFs from SRC_Y bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC_TF+BI_DEST_Y:ud // Read 2 GRFs from SRC_Y top field //load_Y_16x4: // Read 2 GRFs from DEST surface, as the above MB has been deblocked // send (8) PREV_MB_YD(0)<1> MSGHDRY MSGSRC<8;8,1>:ud MSGDSC #endif send (8) TOP_MB_YD(0)<1> MSGHDRT MSGSRC<8;8,1>:ud DAPREAD MSGDSC // End of load_Y_16x4.asm intel-driver-1.3.0/src/shaders/h264/ildb/load_Top_Y_16x4_Mbaff.asm000066400000000000000000000054101231401140700243350ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module Name: Load_Y_16X4.asm // // Load Y 16X4 Block to PREV_MB_YD // //---------------------------------------------------------------- // Symbols Need To Be Defined Before Including This Module // // Source Region In :Ud // Src_YD: Src_Yd Base=Rxx Elementsize=4 Srcregion=Region(8,1) Type=Ud // 3 Grfs (2 For Y, 1 For U+V) // // Source Region Is :Ub. The Same Region As :Ud Region // Src_YB: Src_Yb Base=Rxx Elementsize=1 Srcregion=Region(16,1) Type=Ub // 2 Grfs // // Binding Table Index: // Bi_Src_Y: Binding Table Index Of Y Surface // // Temp Buffer: // Buf_D: Buf_D Base=Rxx Elementsize=4 Srcregion=Region(8,1) Type=Ud // Buf_B: Buf_B Base=Rxx Elementsize=1 Srcregion=Region(16,1) Type=Ub // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD2:w #endif // FieldModeCurrentMbFlag determines how to access above MB and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Read Y mov (2) MSGSRC.0<1>:ud ORIX_TOP<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x0003000F:ud { NoDDChk } // Block width and height (16x4) // Set message descriptor (f0.0) if (1) ELSE_Y_16x4 // Frame picture mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC+BI_DEST_Y:ud // Read 2 GRFs from SRC_Y // Add vertical offset 16 for bot MB in MBAFF mode (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 16:w // Dual field mode setup and.z.f0.1 (1) NULLREGW DualFieldMode:w 1:w (f0.1) jmpi NOT_DUAL_FIELD add (1) MSGSRC.1:d MSGSRC.1:d -4:w { NoDDClr } // Load 8 lines in above MB mov (1) MSGSRC.2:ud 0x0007000F:ud { NoDDChk } // New block width and height (16x8) add (1) MSGDSC MSGDSC RESP_LEN(2):ud // 2 more GRF to receive NOT_DUAL_FIELD: ELSE_Y_16x4: else (1) ENDIF_Y_16x4 asr (1) MSGSRC.1:d ORIY_CUR:w 1:w // Reduce y by half in field access mode // Field picture (f0.1) mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC_BF+BI_DEST_Y:ud // Read 2 GRFs from SRC_Y bottom field (-f0.1) mov (1) MSGDSC RESP_LEN(2)+DWBRMSGDSC_RC_TF+BI_DEST_Y:ud // Read 2 GRFs from SRC_Y top field add (1) MSGSRC.1:d MSGSRC.1:d -4:w // for last 4 rows of above MB endif ENDIF_Y_16x4: // Read 2 GRFs from DEST surface, as the above MB has been deblocked send (8) PREV_MB_YD(0)<1> MSGHDRY MSGSRC<8;8,1>:ud DAPREAD MSGDSC // End of load_Y_16x4.asm intel-driver-1.3.0/src/shaders/h264/ildb/saveNV12_16x16.asm000066400000000000000000000034501231401140700226430ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: saveNV12_16x16.asm // // Save a NV12 16x16 block // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_YD: SRC_YD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 8 GRFs // SRC_UD: SRC_UD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 4 GRF // // Binding table index: // BI_DEST_Y: Binding table index of Y surface // BI_DEST_UV: Binding table index of UV surface (NV12) // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD4:w #endif mov (2) MSGSRC.0<1>:ud ORIX_CUR<2;2,1>:w // Block origin mov (1) MSGSRC.2<1>:ud 0x000F000F:ud // Block width and height (16x16) // Pack Y mov (16) MSGPAYLOADD(0)<1> SRC_YD(0) // Compressed inst mov (16) MSGPAYLOADD(2)<1> SRC_YD(2) mov (16) MSGPAYLOADD(4)<1> SRC_YD(4) mov (16) MSGPAYLOADD(6)<1> SRC_YD(6) send (8) NULLREG MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSG_LEN(8)+DWBWMSGDSC+BI_DEST_Y // Write 8 GRFs asr (1) MSGSRC.1:ud MSGSRC.1:ud 1:w // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2<1>:ud 0x0007000F:ud // NV12 U+V block width and height (16x8) mov (16) MSGPAYLOADD(0)<1> SRC_UD(0) // Compressed inst mov (16) MSGPAYLOADD(2)<1> SRC_UD(2) send (8) NULLREG MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSG_LEN(4)+DWBWMSGDSC+BI_DEST_UV // Write 4 GRFs // End of saveNV12_16x16.asm intel-driver-1.3.0/src/shaders/h264/ildb/saveNV12_16x4.asm000066400000000000000000000033531231401140700225620ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: saveNV12_16x4.asm // // Save a NV12 16x4 block // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_YD: SRC_YD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 2 GRFs // SRC_UD: SRC_UD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 1 GRF // // Binding table index: // BI_DEST_Y: Binding table index of Y surface // BI_DEST_UV: Binding table index of UV surface (NV12) // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD5:w #endif mov (2) MSGSRC.0<1>:ud ORIX_TOP<2;2,1>:w // Block origin mov (1) MSGSRC.2<1>:ud 0x0003000F:ud // Block width and height (16x4) // Pack Y mov (16) MSGPAYLOADD(0)<1> SRC_YD(0) // Compressed inst send (8) NULLREG MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSG_LEN(2)+DWBWMSGDSC+BI_DEST_Y // Write 2 GRFs asr (1) MSGSRC.1:ud MSGSRC.1:ud 1:w // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2<1>:ud 0x0001000F:ud // NV12 U+V block width and height (16x2) // Pack U and V // mov (16) MSGPAYLOADB(0,0)<2> SRC_UB(0,0) // mov (16) MSGPAYLOADB(0,1)<2> SRC_VB(0,0) mov (8) MSGPAYLOADD(0,0)<1> SRC_UD(0) send (8) NULLREG MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSG_LEN(1)+DWBWMSGDSC+BI_DEST_UV // Write 1 GRF // End of saveNV12_16x4.asm intel-driver-1.3.0/src/shaders/h264/ildb/saveNV12_16x4T.asm000066400000000000000000000126411231401140700227060ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: saveNV12_16x4T.asm // // Transpose 16x4 to 4x16 YNV12 data and write to memory // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Left MB region: // PREV_MB_YB: Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // PREV_MB_UW: Base=ryy ElementSize=2 SrcRegion=REGION(8,1) Type=uw // Binding table index: // BI_SRC_Y: Binding table index of Y surface // BI_SRC_UV: Binding table index of UV surface (NV12) // // Temp buffer: // BUF_B: BUF_B Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // BUF_W: BUF_W Base=rxx ElementSize=1 SrcRegion=REGION(8,1) Type=uw // // #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD6:w #endif mov (2) MSGSRC.0<1>:ud ORIX_LEFT<2;2,1>:w // Block origin mov (1) MSGSRC.2<1>:ud 0x000F0003:ud // 4x16 // Transpose Y, save them to MRFs // 16x4 Y src in GRF (each pix is specified as yx) // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f1 e1 d1 c1 b1 a1 91 81 71 61 51 41 31 21 11 01 f0 e0 d0 c0 b0 a0 90 80 70 60 50 40 30 20 10 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 e3 d3 c3 b3 a3 93 83 73 63 53 43 33 23 13 03 f2 e2 d2 c2 b2 a2 92 82 72 62 52 42 32 22 12 02| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // First step (16) <1> <=== <16;4,1> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 63 53 43 72 62 52 42 71 61 51 41 70 60 50 40 33 23 13 03 32 22 12 02 31 21 11 01 30 20 10 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 e3 d3 c3 f2 e2 d2 c2 f1 e1 d1 c1 f0 e0 d0 c0 b3 a3 93 83 b2 a2 92 82 b1 a1 91 81 b0 a0 90 80| // +-----------------------+-----------------------+-----------------------+-----------------------+ // The first step mov (16) BUF_B(0,0)<1> PREV_MB_YB(0,0)<16;4,1> mov (16) BUF_B(0,16)<1> PREV_MB_YB(0,4)<16;4,1> mov (16) BUF_B(1,0)<1> PREV_MB_YB(0,8)<16;4,1> mov (16) BUF_B(1,16)<1> PREV_MB_YB(0,12)<16;4,1> // // Second step (16) <1> <=== <1;4,4> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 72 71 70 63 62 61 60 53 52 51 50 43 42 41 40 33 32 31 30 23 22 21 20 13 12 11 10 03 02 01 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 f2 f1 f0 e3 e2 e1 e0 d3 d2 d1 d0 c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0 93 92 91 90 83 82 81 80| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // The second step // mov (16) MSGPAYLOADB(0,0)<1> BUF_B(0,0)<32;8,4> // Read 2 rows, write 1 row // mov (16) MSGPAYLOADB(0,16)<1> BUF_B(0,1)<32;8,4> // mov (16) MSGPAYLOADB(1,0)<1> BUF_B(0,2)<32;8,4> // mov (16) MSGPAYLOADB(1,16)<1> BUF_B(0,3)<32;8,4> mov (16) MSGPAYLOADB(0,0)<1> BUF_B(0,0)<1;4,4> mov (16) MSGPAYLOADB(0,16)<1> BUF_B(0,16)<1;4,4> mov (16) MSGPAYLOADB(1,0)<1> BUF_B(1,0)<1;4,4> mov (16) MSGPAYLOADB(1,16)<1> BUF_B(1,16)<1;4,4> // Transposed Y in 4x16 is ready for writting to dataport. // send (8) NULLREG MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSG_LEN(2)+DWBWMSGDSC+BI_DEST_Y // Write 2 GRFs ///////////////////////////////////////////////////////////////////////////////////////////////////// // Transpose U/V, save them to MRFs in NV12 format asr (1) MSGSRC.1:ud MSGSRC.1:ud 1:w // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2<1>:ud 0x00070003:ud // NV12 U+V block width and height (4x8) // 16x2 UV src in GRF (each pix is specified as yx) // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 61 61 51 51 41 41 31 31 21 21 11 11 01 01 70 70 60 60 50 50 40 40 30 30 20 20 10 10 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // First step (8) <1> <=== <8;4,1>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 61 61 51 51 41 41 70 70 60 60 50 50 40 40 31 31 21 21 11 11 01 01 30 30 20 20 10 10 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ mov (8) BUF_W(0,0)<1> PREV_MB_UW(0,0)<8;4,1> mov (8) BUF_W(0,8)<1> PREV_MB_UW(0,4)<8;4,1> // Second step (8) <1> <=== <1;2,4> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 70 70 61 61 60 60 51 51 50 50 41 41 40 40 31 31 30 30 21 21 20 20 11 11 10 10 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ mov (8) MSGPAYLOADW(0,0)<1> BUF_W(0,0)<1;2,4> mov (8) MSGPAYLOADW(0,8)<1> BUF_W(0,8)<1;2,4> // Transposed U+V in NV12 in 4x8 is ready for writting to dataport. send (8) NULLREG MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSG_LEN(1)+DWBWMSGDSC+BI_DEST_UV // Write 1 GRF intel-driver-1.3.0/src/shaders/h264/ildb/save_Cur_UV_8x8.asm000066400000000000000000000035341231401140700233240ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_Cur_UV_8x8.asm // // Save UV 8x8 block (8x8U + 8x8V in NV12) // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_UD: SRC_UD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 4 GRF // // Binding table index: // BI_DEST_UV: Binding table index of UV surface (NV12) // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD4:w #endif #if defined(_FIELD) and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag #endif mov (1) MSGSRC.0:ud ORIX_CUR:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_CUR:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x0007000F:ud { NoDDChk } // NV12 U+V block width and height (16x8) mov (16) MSGPAYLOADD(0)<1> SRC_UD(0) // Compressed inst mov (16) MSGPAYLOADD(2)<1> SRC_UD(2) #if defined(_PROGRESSIVE) mov (1) MSGDSC MSG_LEN(4)+DWBWMSGDSC+BI_DEST_UV:ud // send (8) NULLREG MSGHDR MSGSRC<8;8,1>:ud DWBWMSGDSC+0x00400000+BI_DEST_UV #endif #if defined(_FIELD) // Field picture (f0.1) mov (1) MSGDSC MSG_LEN(4)+DWBWMSGDSC+ENMSGDSCBF+BI_DEST_UV:ud // Write 4 GRFs to DEST_UV bottom field (-f0.1) mov (1) MSGDSC MSG_LEN(4)+DWBWMSGDSC+ENMSGDSCTF+BI_DEST_UV:ud // Write 4 GRFs to DEST_UV top field #endif send (8) null:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC // End of save_Cur_UV_8x8.asm intel-driver-1.3.0/src/shaders/h264/ildb/save_Cur_UV_8x8_Mbaff.asm000066400000000000000000000041321231401140700244120ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_Cur_UV_8x8.asm // // Save UV 8x8 block (8x8U + 8x8V in NV12) // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_UD: SRC_UD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 4 GRF // // Binding table index: // BI_DEST_UV: Binding table index of UV surface (NV12) // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD4:w #endif and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w mov (1) MSGSRC.0:ud ORIX_CUR:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_CUR:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x0007000F:ud { NoDDChk } // NV12 U+V block width and height (16x8) mov (16) MSGPAYLOADD(0)<1> SRC_UD(0) // Compressed inst mov (16) MSGPAYLOADD(2)<1> SRC_UD(2) // Set message descriptor (f0.0) if (1) ELSE_UV_8X8 // Frame picture mov (1) MSGDSC MSG_LEN(4)+DWBWMSGDSC+BI_DEST_UV:ud // Write 4 GRFs to DEST_UV (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 8:w // Add vertical offset 8 for bot MB in MBAFF mode ELSE_UV_8X8: else (1) ENDIF_UV_8X8 // Field picture (f0.1) mov (1) MSGDSC MSG_LEN(4)+DWBWMSGDSC+ENMSGDSCBF+BI_DEST_UV:ud // Write 4 GRFs to DEST_UV bottom field (-f0.1) mov (1) MSGDSC MSG_LEN(4)+DWBWMSGDSC+ENMSGDSCTF+BI_DEST_UV:ud // Write 4 GRFs to DEST_UV top field asr (1) MSGSRC.1:d MSGSRC.1:d 1:w // Reduce y by half in field access mode endif ENDIF_UV_8X8: send (8) null:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC // End of save_Cur_UV_8x8.asm intel-driver-1.3.0/src/shaders/h264/ildb/save_Cur_Y_16x16.asm000066400000000000000000000035131231401140700233350ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_Cur_Y_16x16.asm // // Save a Y 16x16 block // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_YD: SRC_YD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 8 GRFs // // Binding table index: // BI_DEST_Y: Binding table index of Y surface // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD4:w #endif #if defined(_FIELD) and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag #endif mov (2) MSGSRC.0<1>:ud ORIX_CUR<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x000F000F:ud { NoDDChk } // Block width and height (16x16) // Pack Y mov (16) MSGPAYLOADD(0)<1> SRC_YD(0) // Compressed inst mov (16) MSGPAYLOADD(2)<1> SRC_YD(2) mov (16) MSGPAYLOADD(4)<1> SRC_YD(4) mov (16) MSGPAYLOADD(6)<1> SRC_YD(6) #if defined(_PROGRESSIVE) mov (1) MSGDSC MSG_LEN(8)+DWBWMSGDSC+BI_DEST_Y:ud // send (8) NULLREG MSGHDR MSGSRC<8;8,1>:ud DWBWMSGDSC+0x00800000+BI_DEST_Y #endif #if defined(_FIELD) // Field picture (f0.1) mov (1) MSGDSC MSG_LEN(8)+DWBWMSGDSC+ENMSGDSCBF+BI_DEST_Y:ud // Write 8 GRFs to DEST_Y bottom field (-f0.1) mov (1) MSGDSC MSG_LEN(8)+DWBWMSGDSC+ENMSGDSCTF+BI_DEST_Y:ud // Write 8 GRFs to DEST_Y top field #endif send (8) null:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC // End of save_Cur_Y_16x16.asm intel-driver-1.3.0/src/shaders/h264/ildb/save_Cur_Y_16x16_Mbaff.asm000066400000000000000000000040771231401140700244360ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_Cur_Y_16x16.asm // // Save a Y 16x16 block // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_YD: SRC_YD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 8 GRFs // // Binding table index: // BI_DEST_Y: Binding table index of Y surface // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD4:w #endif and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w mov (2) MSGSRC.0<1>:ud ORIX_CUR<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x000F000F:ud { NoDDChk } // Block width and height (16x16 or 12x16) // Pack Y mov (16) MSGPAYLOADD(0)<1> SRC_YD(0) // Compressed inst mov (16) MSGPAYLOADD(2)<1> SRC_YD(2) mov (16) MSGPAYLOADD(4)<1> SRC_YD(4) mov (16) MSGPAYLOADD(6)<1> SRC_YD(6) // Set message descriptor (f0.0) if (1) ELSE_Y_16x16 // Frame picture mov (1) MSGDSC MSG_LEN(8)+DWBWMSGDSC+BI_DEST_Y:ud // Write 8 GRFs to DEST_Y (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 16:w // Add vertical offset 16 for bot MB in MBAFF mode ELSE_Y_16x16: else (1) ENDIF_Y_16x16 // Field picture (f0.1) mov (1) MSGDSC MSG_LEN(8)+DWBWMSGDSC+ENMSGDSCBF+BI_DEST_Y:ud // Write 8 GRFs to DEST_Y bottom field (-f0.1) mov (1) MSGDSC MSG_LEN(8)+DWBWMSGDSC+ENMSGDSCTF+BI_DEST_Y:ud // Write 8 GRFs to DEST_Y top field asr (1) MSGSRC.1:d MSGSRC.1:d 1:w // Reduce y by half in field access mode endif ENDIF_Y_16x16: send (8) null:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC // End of save_Cur_Y_16x16.asm intel-driver-1.3.0/src/shaders/h264/ildb/save_Left_UV_8x2T.asm000066400000000000000000000061731231401140700236050ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_Left_UV_8x2T.asm // // Transpose 8x2 to 2x8 UV data and write to memory // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Left MB region: // PREV_MB_UW: Base=ryy ElementSize=2 SrcRegion=REGION(8,1) Type=uw // Binding table index: // BI_SRC_UV: Binding table index of UV surface (NV12) // // Temp buffer: // BUF_W: BUF_W Base=rxx ElementSize=1 SrcRegion=REGION(8,1) Type=uw // // #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD6:w #endif #if defined(_FIELD) and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag #endif // Transpose U/V, save them to MRFs in NV12 format mov (1) MSGSRC.0:ud ORIX_LEFT:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_LEFT:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x00070003:ud { NoDDChk } // NV12 U+V block width and height (4x8) // 16x2 UV src in GRF (each pix is specified as yx) // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 61 61 51 51 41 41 31 31 21 21 11 11 01 01 70 70 60 60 50 50 40 40 30 30 20 20 10 10 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // First step (8) <1> <=== <8;4,1>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 61 61 51 51 41 41 70 70 60 60 50 50 40 40 31 31 21 21 11 11 01 01 30 30 20 20 10 10 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ mov (8) LEFT_TEMP_W(0,0)<1> PREV_MB_UW(0,0)<8;4,1> { NoDDClr } mov (8) LEFT_TEMP_W(0,8)<1> PREV_MB_UW(0,4)<8;4,1> { NoDDChk } // Second step (8) <1> <=== <1;2,4> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 70 70 61 61 60 60 51 51 50 50 41 41 40 40 31 31 30 30 21 21 20 20 11 11 10 10 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ mov (8) MSGPAYLOADW(0,0)<1> LEFT_TEMP_W(0,0)<1;2,4> mov (8) MSGPAYLOADW(0,8)<1> LEFT_TEMP_W(0,8)<1;2,4> // Transposed U+V in NV12 in 4x8 is ready for writting to dataport. #if defined(_PROGRESSIVE) mov (1) MSGDSC MSG_LEN(1)+DWBWMSGDSC+BI_DEST_UV:ud // send (8) NULLREG MSGHDR MSGSRC<8;8,1>:ud DWBWMSGDSC+0x00100000+BI_DEST_UV #endif #if defined(_FIELD) // Field picture (f0.1) mov (1) MSGDSC MSG_LEN(1)+DWBWMSGDSC+ENMSGDSCBF+BI_DEST_UV:ud // Write 1 GRF to DEST_UV bottom field (-f0.1) mov (1) MSGDSC MSG_LEN(1)+DWBWMSGDSC+ENMSGDSCTF+BI_DEST_UV:ud // Write 1 GRF to DEST_UV top field #endif send (8) null:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC intel-driver-1.3.0/src/shaders/h264/ildb/save_Left_UV_8x2T_Mbaff.asm000066400000000000000000000065461231401140700247040ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_Left_UV_8x2T.asm // // Transpose 8x2 to 2x8 UV data and write to memory // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Left MB region: // PREV_MB_UW: Base=ryy ElementSize=2 SrcRegion=REGION(8,1) Type=uw // Binding table index: // BI_SRC_UV: Binding table index of UV surface (NV12) // // Temp buffer: // BUF_W: BUF_W Base=rxx ElementSize=1 SrcRegion=REGION(8,1) Type=uw // // #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD6:w #endif and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Transpose U/V, save them to MRFs in NV12 format mov (1) MSGSRC.0:ud ORIX_LEFT:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_LEFT:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x00070003:ud { NoDDChk } // NV12 U+V block width and height (4x8) // 16x2 UV src in GRF (each pix is specified as yx) // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 61 61 51 51 41 41 31 31 21 21 11 11 01 01 70 70 60 60 50 50 40 40 30 30 20 20 10 10 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // First step (8) <1> <=== <8;4,1>:w // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 61 61 51 51 41 41 70 70 60 60 50 50 40 40 31 31 21 21 11 11 01 01 30 30 20 20 10 10 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ mov (8) BUF_W(0,0)<1> PREV_MB_UW(0,0)<8;4,1> { NoDDClr } mov (8) BUF_W(0,8)<1> PREV_MB_UW(0,4)<8;4,1> { NoDDChk } // Second step (8) <1> <=== <1;2,4> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |71 71 70 70 61 61 60 60 51 51 50 50 41 41 40 40 31 31 30 30 21 21 20 20 11 11 10 10 01 01 00 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ mov (8) MSGPAYLOADW(0,0)<1> BUF_W(0,0)<1;2,4> mov (8) MSGPAYLOADW(0,8)<1> BUF_W(0,8)<1;2,4> // Transposed U+V in NV12 in 4x8 is ready for writting to dataport. // Set message descriptor (f0.0) if (1) ELSE_UV_8X2T // Frame picture mov (1) MSGDSC MSG_LEN(1)+DWBWMSGDSC+BI_DEST_UV:ud // Write 1 GRF to DEST_UV (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 8:w // Add vertical offset 8 for bot MB in MBAFF mode ELSE_UV_8X2T: else (1) ENDIF_UV_8X2T // Field picture (f0.1) mov (1) MSGDSC MSG_LEN(1)+DWBWMSGDSC+ENMSGDSCBF+BI_DEST_UV:ud // Write 1 GRF to DEST_UV bottom field (-f0.1) mov (1) MSGDSC MSG_LEN(1)+DWBWMSGDSC+ENMSGDSCTF+BI_DEST_UV:ud // Write 1 GRF to DEST_UV top field asr (1) MSGSRC.1:d MSGSRC.1:d 1:w // Reduce y by half in field access mode endif ENDIF_UV_8X2T: send (8) null:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC intel-driver-1.3.0/src/shaders/h264/ildb/save_Left_Y_16x4T.asm000066400000000000000000000075611231401140700235460ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_Left_Y_16x4T.asm // // Transpose 16x4 to 4x16 Y data and write to memory // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Left MB region: // PREV_MB_YB: Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Binding table index: // BI_SRC_Y: Binding table index of Y surface // // Temp buffer: // BUF_B: BUF_B Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // // #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD6:w #endif #if defined(_FIELD) and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag #endif mov (2) MSGSRC.0<1>:ud ORIX_LEFT<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x000F0003:ud { NoDDChk } // 4x16 // Transpose Y, save them to MRFs // 16x4 Y src in GRF (each pix is specified as yx) // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f1 e1 d1 c1 b1 a1 91 81 71 61 51 41 31 21 11 01 f0 e0 d0 c0 b0 a0 90 80 70 60 50 40 30 20 10 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 e3 d3 c3 b3 a3 93 83 73 63 53 43 33 23 13 03 f2 e2 d2 c2 b2 a2 92 82 72 62 52 42 32 22 12 02| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // First step (16) <1> <=== <16;4,1> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 63 53 43 72 62 52 42 71 61 51 41 70 60 50 40 33 23 13 03 32 22 12 02 31 21 11 01 30 20 10 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 e3 d3 c3 f2 e2 d2 c2 f1 e1 d1 c1 f0 e0 d0 c0 b3 a3 93 83 b2 a2 92 82 b1 a1 91 81 b0 a0 90 80| // +-----------------------+-----------------------+-----------------------+-----------------------+ // The first step mov (16) LEFT_TEMP_B(0,0)<1> PREV_MB_YB(0,0)<16;4,1> { NoDDClr } mov (16) LEFT_TEMP_B(0,16)<1> PREV_MB_YB(0,4)<16;4,1> { NoDDChk } mov (16) LEFT_TEMP_B(1,0)<1> PREV_MB_YB(0,8)<16;4,1> { NoDDClr } mov (16) LEFT_TEMP_B(1,16)<1> PREV_MB_YB(0,12)<16;4,1> { NoDDChk } // // Second step (16) <1> <=== <1;4,4> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 72 71 70 63 62 61 60 53 52 51 50 43 42 41 40 33 32 31 30 23 22 21 20 13 12 11 10 03 02 01 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 f2 f1 f0 e3 e2 e1 e0 d3 d2 d1 d0 c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0 93 92 91 90 83 82 81 80| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // The second step mov (16) MSGPAYLOADB(0,0)<1> LEFT_TEMP_B(0,0)<1;4,4> mov (16) MSGPAYLOADB(0,16)<1> LEFT_TEMP_B(0,16)<1;4,4> mov (16) MSGPAYLOADB(1,0)<1> LEFT_TEMP_B(1,0)<1;4,4> mov (16) MSGPAYLOADB(1,16)<1> LEFT_TEMP_B(1,16)<1;4,4> // Transposed Y in 4x16 is ready for writting to dataport. #if defined(_PROGRESSIVE) mov (1) MSGDSC MSG_LEN(2)+DWBWMSGDSC+BI_DEST_Y:ud // send (8) NULLREG MSGHDR MSGSRC<8;8,1>:ud DWBWMSGDSC+0x00200000+BI_DEST_Y #endif #if defined(_FIELD) // Field picture (f0.1) mov (1) MSGDSC MSG_LEN(2)+DWBWMSGDSC+ENMSGDSCBF+BI_DEST_Y:ud // Write 2 GRFs to DEST_Y bottom field (-f0.1) mov (1) MSGDSC MSG_LEN(2)+DWBWMSGDSC+ENMSGDSCTF+BI_DEST_Y:ud // Write 2 GRFs to DEST_Y top field #endif send (8) null:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC intel-driver-1.3.0/src/shaders/h264/ildb/save_Left_Y_16x4T_Mbaff.asm000066400000000000000000000102261231401140700246310ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_Left_Y_16x4T.asm // // Transpose 16x4 to 4x16 Y data and write to memory // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Left MB region: // PREV_MB_YB: Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Binding table index: // BI_SRC_Y: Binding table index of Y surface // // Temp buffer: // BUF_B: BUF_B Base=rxx ElementSize=1 SrcRegion=REGION(16,1) Type=ub // // #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD6:w #endif and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w mov (2) MSGSRC.0<1>:ud ORIX_LEFT<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x000F0003:ud { NoDDChk } // 4x16 // Transpose Y, save them to MRFs // 16x4 Y src in GRF (each pix is specified as yx) // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f1 e1 d1 c1 b1 a1 91 81 71 61 51 41 31 21 11 01 f0 e0 d0 c0 b0 a0 90 80 70 60 50 40 30 20 10 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 e3 d3 c3 b3 a3 93 83 73 63 53 43 33 23 13 03 f2 e2 d2 c2 b2 a2 92 82 72 62 52 42 32 22 12 02| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // First step (16) <1> <=== <16;4,1> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 63 53 43 72 62 52 42 71 61 51 41 70 60 50 40 33 23 13 03 32 22 12 02 31 21 11 01 30 20 10 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 e3 d3 c3 f2 e2 d2 c2 f1 e1 d1 c1 f0 e0 d0 c0 b3 a3 93 83 b2 a2 92 82 b1 a1 91 81 b0 a0 90 80| // +-----------------------+-----------------------+-----------------------+-----------------------+ // The first step mov (16) BUF_B(0,0)<1> PREV_MB_YB(0,0)<16;4,1> { NoDDClr } mov (16) BUF_B(0,16)<1> PREV_MB_YB(0,4)<16;4,1> { NoDDChk } mov (16) BUF_B(1,0)<1> PREV_MB_YB(0,8)<16;4,1> { NoDDClr } mov (16) BUF_B(1,16)<1> PREV_MB_YB(0,12)<16;4,1> { NoDDChk } // // Second step (16) <1> <=== <1;4,4> // +-----------------------+-----------------------+-----------------------+-----------------------+ // |73 72 71 70 63 62 61 60 53 52 51 50 43 42 41 40 33 32 31 30 23 22 21 20 13 12 11 10 03 02 01 00| // +-----------------------+-----------------------+-----------------------+-----------------------+ // |f3 f2 f1 f0 e3 e2 e1 e0 d3 d2 d1 d0 c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0 93 92 91 90 83 82 81 80| // +-----------------------+-----------------------+-----------------------+-----------------------+ // // The second step mov (16) MSGPAYLOADB(0,0)<1> BUF_B(0,0)<1;4,4> mov (16) MSGPAYLOADB(0,16)<1> BUF_B(0,16)<1;4,4> mov (16) MSGPAYLOADB(1,0)<1> BUF_B(1,0)<1;4,4> mov (16) MSGPAYLOADB(1,16)<1> BUF_B(1,16)<1;4,4> // Transposed Y in 4x16 is ready for writting to dataport. //***** Left MB is loaded the same as indicated by FieldModeCurrentMbFlag. // Set message descriptor (f0.0) if (1) ELSE_Y_16x4T // Frame picture mov (1) MSGDSC MSG_LEN(2)+DWBWMSGDSC+BI_DEST_Y:ud // Write 2 GRFs to DEST_Y (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 16:w // Add vertical offset 16 for bot MB in MBAFF mode ELSE_Y_16x4T: else (1) ENDIF_Y_16x4T // Field picture (f0.1) mov (1) MSGDSC MSG_LEN(2)+DWBWMSGDSC+ENMSGDSCBF+BI_DEST_Y:ud // Write 2 GRFs to DEST_Y bottom field (-f0.1) mov (1) MSGDSC MSG_LEN(2)+DWBWMSGDSC+ENMSGDSCTF+BI_DEST_Y:ud // Write 2 GRFs to DEST_Y top field asr (1) MSGSRC.1:d MSGSRC.1:d 1:w // Reduce y by half in field access mode endif ENDIF_Y_16x4T: send (8) null:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC intel-driver-1.3.0/src/shaders/h264/ildb/save_Top_UV_8x2.asm000066400000000000000000000034731231401140700233310ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_Top_UV_8x2.asm // // Save UV 8x2 block (8x2U + 8x2V in NV12) // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_UD: SRC_UD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 1 GRF // // Binding table index: // BI_DEST_UV: Binding table index of UV surface (NV12) // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD5:w #endif #if defined(_FIELD) and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag #endif mov (1) MSGSRC.0:ud ORIX_TOP:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_TOP:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x0001000F:ud { NoDDChk } // NV12 U+V block width and height (16x2) mov (8) MSGPAYLOADD(0,0)<1> TOP_MB_UD(0) #if defined(_PROGRESSIVE) mov (1) MSGDSC MSG_LEN(1)+DWBWMSGDSC_WC+BI_DEST_UV:ud // send (8) NULLREG MSGHDR MSGSRC<8;8,1>:ud DWBWMSGDSC+0x00100000+BI_DEST_UV #endif #if defined(_FIELD) // Field picture (f0.1) mov (1) MSGDSC MSG_LEN(1)+DWBWMSGDSC_WC+ENMSGDSCBF+BI_DEST_UV:ud // Write 1 GRF to DEST_Y bottom field (-f0.1) mov (1) MSGDSC MSG_LEN(1)+DWBWMSGDSC_WC+ENMSGDSCTF+BI_DEST_UV:ud // Write 1 GRF to DEST_Y top field #endif send (8) WritebackResponse(0)<1> MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC // End of save_Top_UV_8x2.asm intel-driver-1.3.0/src/shaders/h264/ildb/save_Top_UV_8x2_Mbaff.asm000066400000000000000000000047441231401140700244260ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_Top_UV_8x2.asm // // Save UV 8x2 block (8x2U + 8x2V in NV12) // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_UD: SRC_UD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 1 GRF // // Binding table index: // BI_DEST_UV: Binding table index of UV surface (NV12) // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD5:w #endif and.z.f0.1 (8) NULLREGW DualFieldMode<0;1,0>:w 1:w // FieldModeCurrentMbFlag determines how to access above MB and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w // Pack U and V mov (1) MSGSRC.0:ud ORIX_TOP:w { NoDDClr } // Block origin asr (1) MSGSRC.1:ud ORIY_TOP:w 1:w { NoDDClr, NoDDChk } // NV12 U+V block origin y = half of Y comp mov (1) MSGSRC.2:ud 0x0001000F:ud { NoDDChk } // NV12 U+V block width and height (16x2) // Dual field mode (f0.1) mov (8) MSGPAYLOADD(0)<1> PREV_MB_UD(0) (-f0.1) mov (8) MSGPAYLOADD(0)<1> PREV_MB_UD(1) // for dual field mode, write last 2 rows // Set message descriptor and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w (f0.0) if (1) ELSE_UV_8X2_SAVE // Frame picture mov (1) MSGDSC MSG_LEN(1)+DWBWMSGDSC_WC+BI_DEST_UV:ud // Write 1 GRFs to DEST_UV // Add vertical offset 8 for bot MB in MBAFF mode (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 8:w ELSE_UV_8X2_SAVE: else (1) ENDIF_UV_8X2_SAVE asr (1) MSGSRC.1:d ORIY_CUR:w 2:w // asr 1: NV12 U+V block origin y = half of Y comp // asr 1: Reduce y by half in field access mode // Field picture (f0.1) mov (1) MSGDSC MSG_LEN(1)+DWBWMSGDSC_WC+ENMSGDSCBF+BI_DEST_UV:ud // Write 1 GRF to DEST_Y bottom field (-f0.1) mov (1) MSGDSC MSG_LEN(1)+DWBWMSGDSC_WC+ENMSGDSCTF+BI_DEST_UV:ud // Write 1 GRF to DEST_Y top field add (1) MSGSRC.1:d MSGSRC.1:d -2:w // for last 4 rows of above MB endif ENDIF_UV_8X2_SAVE: send (8) WritebackResponse(0)<1> MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC // End of save_Top_UV_8x2.asm intel-driver-1.3.0/src/shaders/h264/ildb/save_Top_Y_16x4.asm000066400000000000000000000033241231401140700232630ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_Top_Y_16x4.asm // // Save a Y 16x4 block // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_YD: SRC_YD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 2 GRFs // // Binding table index: // BI_DEST_Y: Binding table index of Y surface // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD5:w #endif #if defined(_FIELD) and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w // Get bottom field flag #endif mov (2) MSGSRC.0<1>:ud ORIX_TOP<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x0003000F:ud { NoDDChk } // Block width and height (16x4) // Pack Y mov (16) MSGPAYLOADD(0)<1> TOP_MB_YD(0) // Compressed inst #if defined(_PROGRESSIVE) mov (1) MSGDSC MSG_LEN(2)+DWBWMSGDSC_WC+BI_DEST_Y:ud // send (8) NULLREG MSGHDR MSGSRC<8;8,1>:ud DWBWMSGDSC+0x00200000+BI_DEST_Y #endif #if defined(_FIELD) // Field picture (f0.1) mov (1) MSGDSC MSG_LEN(2)+DWBWMSGDSC_WC+ENMSGDSCBF+BI_DEST_Y:ud // Write 2 GRFs to DEST_Y bottom field (-f0.1) mov (1) MSGDSC MSG_LEN(2)+DWBWMSGDSC_WC+ENMSGDSCTF+BI_DEST_Y:ud // Write 2 GRFs to DEST_Y top field #endif send (8) WritebackResponse(0)<1> MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC // End of save_Top_Y_16x4.asm intel-driver-1.3.0/src/shaders/h264/ildb/save_Top_Y_16x4_Mbaff.asm000066400000000000000000000044561231401140700243650ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_Top_Y_16x4.asm // // Save a Y 16x4 block // //---------------------------------------------------------------- // Symbols need to be defined before including this module // // Source region in :ud // SRC_YD: SRC_YD Base=rxx ElementSize=4 SrcRegion=REGION(8,1) Type=ud // 2 GRFs // // Binding table index: // BI_DEST_Y: Binding table index of Y surface // //---------------------------------------------------------------- #if defined(_DEBUG) mov (1) EntrySignatureC:w 0xDDD5:w #endif and.z.f0.1 (16) NULLREGW DualFieldMode<0;1,0>:w 1:w // FieldModeCurrentMbFlag determines how to access above MB and.z.f0.0 (1) null:w r[ECM_AddrReg, BitFlags]:ub FieldModeCurrentMbFlag:w mov (2) MSGSRC.0<1>:ud ORIX_TOP<2;2,1>:w { NoDDClr } // Block origin mov (1) MSGSRC.2<1>:ud 0x0003000F:ud { NoDDChk } // Block width and height (16x4) // Pack Y // Dual field mode (f0.1) mov (16) MSGPAYLOADD(0)<1> PREV_MB_YD(0) // Compressed inst (-f0.1) mov (16) MSGPAYLOADD(0)<1> PREV_MB_YD(2) // for dual field mode, write last 4 rows // Set message descriptor and.nz.f0.1 (1) NULLREGW BitFields:w BotFieldFlag:w (f0.0) if (1) ELSE_Y_16x4_SAVE // Frame picture mov (1) MSGDSC MSG_LEN(2)+DWBWMSGDSC_WC+BI_DEST_Y:ud // Write 2 GRFs to DEST_Y // Add vertical offset 16 for bot MB in MBAFF mode (f0.1) add (1) MSGSRC.1:d MSGSRC.1:d 16:w ELSE_Y_16x4_SAVE: else (1) ENDIF_Y_16x4_SAVE asr (1) MSGSRC.1:d ORIY_CUR:w 1:w // Reduce y by half in field access mode // Field picture (f0.1) mov (1) MSGDSC MSG_LEN(2)+DWBWMSGDSC_WC+ENMSGDSCBF+BI_DEST_Y:ud // Write 2 GRFs to DEST_Y bottom field (-f0.1) mov (1) MSGDSC MSG_LEN(2)+DWBWMSGDSC_WC+ENMSGDSCTF+BI_DEST_Y:ud // Write 2 GRFs to DEST_Y top field add (1) MSGSRC.1:d MSGSRC.1:d -4:w // for last 4 rows of above MB endif ENDIF_Y_16x4_SAVE: send (8) WritebackResponse(0)<1> MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC // End of save_Top_Y_16x4.asm intel-driver-1.3.0/src/shaders/h264/ildb/writeURB.asm000066400000000000000000000026341231401140700221370ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: WriteURB.asm // // General purpose module to write data to URB using the URB handle/offset in r0 // //---------------------------------------------------------------- // Assume: // - a0.0 and a0.1 is meg desc, has been assign with URB offset and msg size // - MRFs are alrady assigned with data. //---------------------------------------------------------------- // // 16x16 byte pixel block can be saved using just 1 "send" instruction. #if defined(_DEBUG) mov (1) EntrySignature:w 0x3535:w #endif // URB write header: //mov (8) MSGSRC.0:ud r0.0<8;8,1>:ud // Copy parent R0 header //shr (1) Temp2_W:uw URBOffset:uw 1:w // divide by 2, because URB entry is counted by 512bits. Offset is counted by 256bits. //add (1) MSGSRC.0:uw r0.0:uw Temp2_W:uw shr (1) MSGSRC.0:uw URBOffset:uw 1:w // divide by 2, because URB entry is counted by 512bits. Offset is counted by 256bits. //mov (1) MSGSRC.0:uw URBOffset_2:uw //mov (1) MSGSRC.1:ud 0:ud // Reset Handle 1 send null:uw m0 MSGSRC<8;8,1>:uw URBWRITE URBWriteMsgDesc:ud // URB write //send null:ud MRF0 null:ud URBWriteMsgDesc:ud // URB write intel-driver-1.3.0/src/shaders/h264/ildb/writeURB_UV_Child.asm000066400000000000000000000027331231401140700236540ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: WriteURB_Child.asm // // General purpose module to write data to URB using the URB handle/offset in r0 // //---------------------------------------------------------------- // Assume: // - a0.0 and a0.1 is meg desc, has been assign with URB offset and msg size // - MRFs are alrady assigned with data. //---------------------------------------------------------------- // // 16x16 byte pixel block can be saved using just 1 "send" instruction. #if defined(_DEBUG) mov (1) EntrySignatureC:w 0x3535:w #endif // URB write header: //mov (8) MSGSRC.0:ud r0.0<8;8,1>:ud // Copy parent R0 header //shr (1) Temp2_W:uw URBOffsetC:uw 1:w // divide by 2, because URB entry is counted by 512bits. Offset is counted by 256bits. //add (1) MSGSRC.0:uw r0.0:uw Temp2_W:uw shr (1) MSGSRC.0:uw URBOffsetC:uw 1:w // divide by 2, because URB entry is counted by 512bits. Offset is counted by 256bits. //mov (1) MSGSRC.1:ud 0:ud // Reset Handle 1 // URB write 1 MRFs, // Current MB offset is in URBOffset, use it as write origin // Add 2 to offset to store data be be passed to the right MB send null:uw m0 MSGSRC<8;8,1>:uw URBWRITE MSG_LEN(1)+URBWMSGDSC+0x20 // URB write intel-driver-1.3.0/src/shaders/h264/ildb/writeURB_Y_Child.asm000066400000000000000000000030111231401140700235200ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: WriteURB_Child.asm // // General purpose module to write data to URB using the URB handle/offset in r0 // //---------------------------------------------------------------- // Assume: // - a0.0 and a0.1 is meg desc, has been assign with URB offset and msg size // - MRFs are alrady assigned with data. //---------------------------------------------------------------- // // 16x16 byte pixel block can be saved using just 1 "send" instruction. #if defined(_DEBUG) mov (1) EntrySignatureC:w 0x3535:w #endif // URB write header: //mov (8) MSGSRC.0:ud r0.0<8;8,1>:ud // Copy parent R0 header //shr (1) Temp2_W:uw URBOffsetC:uw 1:w // divide by 2, because URB entry is counted by 512bits. Offset is counted by 256bits. //add (1) MSGSRC.0:uw r0.0:uw Temp2_W:uw shr (1) MSGSRC.0:uw URBOffsetC:uw 1:w // divide by 2, because URB entry is counted by 512bits. Offset is counted by 256bits. //mov (1) MSGSRC.1:ud 0:ud // Reset Handle 1 // URB write 2 MRFs, // Current MB offset is in URBOffset, use it as write origin // Add 2 to offset to store data be be passed to the right MB //mov (1) URBWriteMsgDesc:ud 0x06300020:ud send null:uw m0 MSGSRC<8;8,1>:uw URBWRITE MSG_LEN(2)+URBWMSGDSC+0x20 // URB write intel-driver-1.3.0/src/shaders/h264/mc/000077500000000000000000000000001231401140700174125ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/h264/mc/AVCMCInter.asm000066400000000000000000000171571231401140700217620ustar00rootroot00000000000000/* * All inter-prediction macroblock kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: AVCMCInter.asm #ifdef INTERLABEL #undef INTERLABEL #endif #if defined(MBAFF) // < MBaff_Motion > #define INTERLABEL(x) x##_##MBF #elif defined(FIELD) // < FieldMB_Motion > #define INTERLABEL(x) x##_##FLD #else // FRAME // < FrameMB_Motion > #define INTERLABEL(x) x##_##FRM #endif // // Decoding an inter-prediction macroblock (conditional compile) // -DMBAFF : MBAff picture MB // -DFRAME : Frame picture MB // -DFIELD : Field picture MB // -DMBAFF -DMONO : MBAff mono picture MB // -DFRAME -DMONO : Frame mono picture MB // -DFIELD -DMONO : Field mono picture MB //#if !defined(__AVCMCInter__) // Make sure this is only included once //#define __AVCMCInter__ // TODO: header files need to be in sync with intra prediction #include "header.inc" #include "inter_Header.inc" // TODO: Kernel names for mono cases #if defined(MBAFF) .kernel MBAff_Motion MBAFF_MB: #elif defined(FIELD) .kernel FieldMB_Motion FIELD_MB: #else // Frame .kernel FrameMB_Motion FRAME_MB: #endif #ifdef _DEBUG // WA for FULSIM so we'll know which kernel is being debugged #if defined(MBAFF) mov (1) acc0:ud 0x0aaa55a5:ud #elif defined(FIELD) mov (1) acc0:ud 0x0baa55a5:ud #else // Frame mov (1) acc0:ud 0x0caa55a5:ud #endif #endif #ifdef SW_SCOREBOARD CALL(scoreboard_start_inter,1) #endif mov (8) gMSGSRC<1>:ud r0.0<8;8,1>:ud // Initialize message header payload with R0 and (1) gwMBTYPE<1> gMBTYPE:ub nMBTYPE_MASK:w // MB type shl (2) gX<1>:w gORIX<2;2,1>:ub 4:w // Convert MB origin to pixel unit // #include "process_inter16x16.asm" // Handle B_L0_16x16 case with zero MVs and weighted pred off. // In the case of B_L0_16x16 with zero MVs and weighted pred off, the kernel jumps to INTERLABEL(EXIT_LOOP). INTERLABEL(INIT_MBPARA): #include "initialize_MBPara.asm" //========================= BEGIN - LOOP_SUBMB =========================== mov (1) gLOOP_SUBMB:uw 0:uw // 0, 2, 4, 6 INTERLABEL(LOOP_SUBMB): //========================== BEGIN - LOOP_DIR ============================ // Prediction flag (gPREDFLAG - 0:Pred_L0, 1:Pred_L1, 2:BiPred) asr (1) gPREDFLAG:w gSUBMB_MODE:ub gLOOP_SUBMB:uw mov (1) gLOOP_DIR:uw 1:uw // 1, 0 and (1) gPREDFLAG:w gPREDFLAG:w 0x3:w INTERLABEL(LOOP_DIR): cmp.e.f0.0 (1) null:w gLOOP_DIR:w gPREDFLAG:w (f0.0) jmpi INTERLABEL(LOOP_DIR_CONTINUE) // Get binding table index // & reference picture parity (gREFPARITY - 0:top, 0x100:bottom, x:frame) // & address of interpolation result cmp.e.f0.1 (1) null:w gLOOP_DIR:w 1:w (f0.1) mov (1) gpINTP:ud nOFFSET_INTP0:ud {NoDDClr} // (f0.1) and (1) gBIDX:w r[pBIDX]:ub 0x7f:w {NoDDChk} // (-f0.1) mov (1) gpINTP:ud nOFFSET_INTP1:ud {NoDDClr} // (-f0.1) and (1) gBIDX:w r[pBIDX,4]:ub 0x7f:w {NoDDChk} // #if defined(MBAFF) || defined(FIELD) (f0.1) and (1) gREFPARITY:w r[pBIDX]:ub 0x80:w (-f0.1) and (1) gREFPARITY:w r[pBIDX,4]:ub 0x80:w shl (1) gREFPARITY:w gREFPARITY<0;1,0>:w 1:w #endif // Sub MB shape asr (1) gSHAPETEMP:w gSUBMB_SHAPE:ub gLOOP_SUBMB:w // Chroma MV adjustment & Set message descriptor for frame/field read #if defined(MBAFF) #include "chromaMVAdjust.asm" and.nz.f0.0 (1) null:uw gFIELDMBFLAG:ub nFIELDMB_MASK:uw (f0.0) add (1) gD0:ud gBIDX:uw nDWBRMSGDSC_SC_TF:ud (-f0.0) add (1) gMSGDSC_R:ud gBIDX:uw nDWBRMSGDSC_SC:ud (f0.0) add (1) gMSGDSC_R:ud gD0:ud gREFPARITY:uw #elif defined(FIELD) #include "chromaMVAdjust.asm" add (1) gMSGDSC_R:ud gBIDX:uw nDWBRMSGDSC_SC_TF:ud add (1) gMSGDSC_R:ud gMSGDSC_R:ud gREFPARITY:uw #else // FRAME add (1) gMSGDSC_R:ud gBIDX:uw nDWBRMSGDSC_SC:ud #endif and.nz.f0.1 (1) null:w gSHAPETEMP:w 3:w (f0.1) jmpi INTERLABEL(PROCESS4x4) //======================== BEGIN - PROCESS 8x8 =========================== // Reference block load #include "loadRef_Y_16x13.asm" #ifndef MONO #if defined(MBAFF) || defined(FIELD) add (1) r[pMV,2]:w r[pMV,2]:w gCHRMVADJ:w #endif #include "loadRef_C_10x5.asm" #endif // Interpolation //CALL_INTER(INTERLABEL(Interpolate_Y_8x8_Func), 1) #include "interpolate_Y_8x8.asm" #ifndef MONO //CALL_INTER(INTERLABEL(Interpolate_C_4x4_Func), 1) #include "interpolate_C_4x4.asm" #endif jmpi INTERLABEL(ROUND_SHIFT_C) //========================= END - PROCESS 8x8 ============================ //======================== BEGIN - LOOP_SUBMBPT ========================== INTERLABEL(PROCESS4x4): mov (1) gLOOP_SUBMBPT:uw 4:uw // 4, 3, 2, 1 INTERLABEL(LOOP_SUBMBPT): // Reference block load #include "loadRef_Y_16x9.asm" #ifndef MONO #if defined(MBAFF) || defined(FIELD) add (1) r[pMV,2]:w r[pMV,2]:w gCHRMVADJ:w #endif #include "loadRef_C_6x3.asm" #endif // Interpolation #include "interpolate_Y_4x4.asm" #ifndef MONO #include "interpolate_C_2x2.asm" #endif cmp.e.f0.0 (1) null:w gLOOP_SUBMBPT:uw 3:w add.z.f0.1 (1) gLOOP_SUBMBPT:uw gLOOP_SUBMBPT:uw -1:w add (1) pMV:w pMV:w 8:w (-f0.0) add (1) gpINTP:ud gpINTP:ud 0x00080008:ud // 8 & 8 (f0.0) add (1) gpINTP:ud gpINTP:ud 0x00180038:ud // 24 & 56 (-f0.1) jmpi INTERLABEL(LOOP_SUBMBPT) cmp.e.f0.1 null:w gLOOP_DIR:w 1:w add (1) pMV:w pMV:w -32:w (f0.1) mov (1) gpINTP:ud nOFFSET_INTP0:ud (-f0.1) mov (1) gpINTP:ud nOFFSET_INTP1:ud mov (1) pRESULT:uw gpINTPC:uw //========================= END - LOOP_SUBMBPT =========================== INTERLABEL(ROUND_SHIFT_C): #ifndef MONO #include "roundShift_C_4x4.asm" #endif INTERLABEL(LOOP_DIR_CONTINUE): add.nz.f0.1 (1) gLOOP_DIR:uw gLOOP_DIR:uw -1:w add (1) pMV:w pMV:w 4:w (-f0.1) jmpi INTERLABEL(LOOP_DIR) //=========================== END - LOOP_DIR ============================= INTERLABEL(Weighted_Prediction): #include "weightedPred.asm" and.z.f0.1 (16) null<1>:w gLOOP_SUBMB<0;1,0>:uw 2:w #include "recon_Y_8x8.asm" #ifndef MONO #include "recon_C_4x4.asm" (-f0.1) add (1) pERRORC:w pERRORC:w 48:w #endif cmp.e.f0.1 (1) null:w gLOOP_SUBMB:uw 6:w add (1) gLOOP_SUBMB:uw gLOOP_SUBMB:uw 2:w add (1) pWGT_BIDX:ud pWGT_BIDX:ud 0x00100001:ud // 12 & 1 add (1) pMV:w pMV:w gMVSTEP:w (-f0.1) jmpi INTERLABEL(LOOP_SUBMB) //========================== END - LOOP_SUBMB ============================ INTERLABEL(EXIT_LOOP): #include "writeRecon_YC.asm" #ifdef SW_SCOREBOARD wait n0:ud // Now wait for scoreboard to response #include "Soreboard_update.asm" // scorboard update function #else // Check for write commit first if SW scoreboard is disabled mov (1) gREG_WRITE_COMMIT_Y<1>:ud gREG_WRITE_COMMIT_Y<0;1,0>:ud // Make sure Y write is committed mov (1) gREG_WRITE_COMMIT_UV<1>:ud gREG_WRITE_COMMIT_UV<0;1,0>:ud // Make sure U/V write is committed #endif // Terminate the thread // END_THREAD //#include "Interpolate_Y_8x8_Func.asm" //#include "Interpolate_C_4x4_Func.asm" //#include "WeightedPred_Y_Func.asm" //#include "WeightedPred_C_Func.asm" .end_code .end_kernel //#endif // !defined(__AVCMCInter__) intel-driver-1.3.0/src/shaders/h264/mc/AllAVC.asm000066400000000000000000000225201231401140700211570ustar00rootroot00000000000000/* * All HWMC kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: AllAVC.asm // // All HWMC kernels merged into this file // // $Revision: 2 $ // $Date: 9/10/06 2:02a $ // // Note: To enable SW scoreboard for ILK AVC kernels, simply toggle the HW_SCOREBOARD // and SW_SCOREBOARD definition as described below. // // ---------------------------------------------------- // Main: ALLINTRA // ---------------------------------------------------- #define COMBINED_KERNEL #define ENABLE_ILDB // WA for *Stim tool issue, should be removed later #ifdef DEV_ILK #define INSTFACTOR 2 // 128-bit count as 2 instructions #else #define INSTFACTOR 1 // 128-bit is 1 instruction #endif // DEV_ILK #ifdef DEV_CTG #define SW_SCOREBOARD // SW Scoreboard should be enabled for CTG and earlier #undef HW_SCOREBOARD // HW Scoreboard should be disabled for CTG and earlier #else #define HW_SCOREBOARD // HW Scoreboard should be enabled for ILK and beyond #undef SW_SCOREBOARD // SW Scoreboard should be disabled for ILK and beyond #endif // DEV_CTG #ifdef BOOTSTRAP # ifdef ENABLE_ILDB # define ALL_SPAWNED_UV_ILDB_FRAME_IP 0 # define SLEEP_ENTRY_UV_ILDB_FRAME_IP 0 # define POST_SLEEP_UV_ILDB_FRAME_IP 0 # define ALL_SPAWNED_Y_ILDB_FRAME_IP 0 # define SLEEP_ENTRY_Y_ILDB_FRAME_IP 0 # define POST_SLEEP_Y_ILDB_FRAME_IP 0 # endif #elif defined(DEV_ILK) # include "export.inc.gen5" #elif defined(DEV_CTG) # include "export.inc" #endif #if defined(_EXPORT) #include "AllAVC_Export.inc" #elif defined(_BUILD) #include "AllAVC.ich" // ISAasm dumped .exports #include "AllAVC_Export.inc" // Keep jumping targets aligned, only for CTG and beyond #include "AllAVC_Build.inc" #else #endif .kernel AllAVC // Build all intra prediction kernels // #ifdef INTRA_16x16_PAD_NENOP $for(0; #define _PROGRESSIVE #define ILDB_LABEL(x) x##_ILDB_FRAME #ifdef AVC_ILDB_ROOT_Y_ILDB_FRAME_PAD_NENOP $for(0; #define _FIELD #define ILDB_LABEL(x) x##_ILDB_FIELD #ifdef AVC_ILDB_ROOT_Y_ILDB_FIELD_PAD_NENOP $for(0; #define _MBAFF #define ILDB_LABEL(x) x##_ILDB_MBAFF #ifdef AVC_ILDB_ROOT_Y_ILDB_MBAFF_PAD_NENOP $for(0; , Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // 2857702934 // 0xAA551616 - GUID for Intra_16x16 luma prediction mode offsets // 0 // Offset to Intra_16x16 luma prediction mode 0 // 9 // Offset to Intra_16x16 luma prediction mode 1 // 19 // Offset to Intra_16x16 luma prediction mode 2 // 42 // Offset to Intra_16x16 luma prediction mode 3 // 2857699336 // 0xAA550808 - GUID for Intra_8x8 luma prediction mode offsets // 0 // Offset to Intra_8x8 luma prediction mode 0 // 5 // Offset to Intra_8x8 luma prediction mode 1 // 10 // Offset to Intra_8x8 luma prediction mode 2 // 26 // Offset to Intra_8x8 luma prediction mode 3 // 36 // Offset to Intra_8x8 luma prediction mode 4 // 50 // Offset to Intra_8x8 luma prediction mode 5 // 68 // Offset to Intra_8x8 luma prediction mode 6 // 85 // Offset to Intra_8x8 luma prediction mode 7 // 95 // Offset to Intra_8x8 luma prediction mode 8 // 2857698308 // 0xAA550404 - GUID for Intra_4x4 luma prediction mode offsets // 0 // Offset to Intra_4x4 luma prediction mode 0 // 2 // Offset to Intra_4x4 luma prediction mode 1 // 4 // Offset to Intra_4x4 luma prediction mode 2 // 16 // Offset to Intra_4x4 luma prediction mode 3 // 23 // Offset to Intra_4x4 luma prediction mode 4 // 32 // Offset to Intra_4x4 luma prediction mode 5 // 45 // Offset to Intra_4x4 luma prediction mode 6 // 59 // Offset to Intra_4x4 luma prediction mode 7 // 66 // Offset to Intra_4x4 luma prediction mode 8 // 2857700364 // 0xAA550C0C - GUID for intra chroma prediction mode offsets // 0 // Offset to intra chroma prediction mode 0 // 30 // Offset to intra chroma prediction mode 1 // 36 // Offset to intra chroma prediction mode 2 // 41 // Offset to intra chroma prediction mode 3 // Kernel name: AllAVCField.asm // // All field picture HWMC kernels merged into this file // // $Revision: 1 $ // $Date: 4/13/06 4:35p $ // // ---------------------------------------------------- // Main: AllAVCField // ---------------------------------------------------- #define ALLHWMC #define COMBINED_KERNEL .kernel AllAVCField #include "Intra_PCM.asm" #include "Intra_16x16.asm" #include "Intra_8x8.asm" #include "Intra_4x4.asm" #include "scoreboard.asm" #define FIELD #include "AVCMCInter.asm" // End of AllAVCField .end_kernel intel-driver-1.3.0/src/shaders/h264/mc/AllAVCFrame.asm000066400000000000000000000052241231401140700221340ustar00rootroot00000000000000/* * All frame picture HWMC kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // 2857702934 // 0xAA551616 - GUID for Intra_16x16 luma prediction mode offsets // 0 // Offset to Intra_16x16 luma prediction mode 0 // 9 // Offset to Intra_16x16 luma prediction mode 1 // 19 // Offset to Intra_16x16 luma prediction mode 2 // 42 // Offset to Intra_16x16 luma prediction mode 3 // 2857699336 // 0xAA550808 - GUID for Intra_8x8 luma prediction mode offsets // 0 // Offset to Intra_8x8 luma prediction mode 0 // 5 // Offset to Intra_8x8 luma prediction mode 1 // 10 // Offset to Intra_8x8 luma prediction mode 2 // 26 // Offset to Intra_8x8 luma prediction mode 3 // 36 // Offset to Intra_8x8 luma prediction mode 4 // 50 // Offset to Intra_8x8 luma prediction mode 5 // 68 // Offset to Intra_8x8 luma prediction mode 6 // 85 // Offset to Intra_8x8 luma prediction mode 7 // 95 // Offset to Intra_8x8 luma prediction mode 8 // 2857698308 // 0xAA550404 - GUID for Intra_4x4 luma prediction mode offsets // 0 // Offset to Intra_4x4 luma prediction mode 0 // 2 // Offset to Intra_4x4 luma prediction mode 1 // 4 // Offset to Intra_4x4 luma prediction mode 2 // 16 // Offset to Intra_4x4 luma prediction mode 3 // 23 // Offset to Intra_4x4 luma prediction mode 4 // 32 // Offset to Intra_4x4 luma prediction mode 5 // 45 // Offset to Intra_4x4 luma prediction mode 6 // 59 // Offset to Intra_4x4 luma prediction mode 7 // 66 // Offset to Intra_4x4 luma prediction mode 8 // 2857700364 // 0xAA550C0C - GUID for intra chroma prediction mode offsets // 0 // Offset to intra chroma prediction mode 0 // 30 // Offset to intra chroma prediction mode 1 // 36 // Offset to intra chroma prediction mode 2 // 41 // Offset to intra chroma prediction mode 3 // Kernel name: AllAVCFrame.asm // // All frame picture HWMC kernels merged into this file // // $Revision: 1 $ // $Date: 4/13/06 4:35p $ // // ---------------------------------------------------- // Main: AllAVCFrame // ---------------------------------------------------- #define ALLHWMC #define COMBINED_KERNEL .kernel AllAVCFrame #include "Intra_PCM.asm" #include "Intra_16x16.asm" #include "Intra_8x8.asm" #include "Intra_4x4.asm" #include "scoreboard.asm" #include "AVCMCInter.asm" // End of AllAVCFrame .end_kernel intel-driver-1.3.0/src/shaders/h264/mc/AllAVCMBAFF.asm000066400000000000000000000052601231401140700217150ustar00rootroot00000000000000/* * All MBAFF frame picture HWMC kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // 2857702934 // 0xAA551616 - GUID for Intra_16x16 luma prediction mode offsets // 0 // Offset to Intra_16x16 luma prediction mode 0 // 9 // Offset to Intra_16x16 luma prediction mode 1 // 19 // Offset to Intra_16x16 luma prediction mode 2 // 42 // Offset to Intra_16x16 luma prediction mode 3 // 2857699336 // 0xAA550808 - GUID for Intra_8x8 luma prediction mode offsets // 0 // Offset to Intra_8x8 luma prediction mode 0 // 5 // Offset to Intra_8x8 luma prediction mode 1 // 10 // Offset to Intra_8x8 luma prediction mode 2 // 26 // Offset to Intra_8x8 luma prediction mode 3 // 36 // Offset to Intra_8x8 luma prediction mode 4 // 50 // Offset to Intra_8x8 luma prediction mode 5 // 68 // Offset to Intra_8x8 luma prediction mode 6 // 85 // Offset to Intra_8x8 luma prediction mode 7 // 95 // Offset to Intra_8x8 luma prediction mode 8 // 2857698308 // 0xAA550404 - GUID for Intra_4x4 luma prediction mode offsets // 0 // Offset to Intra_4x4 luma prediction mode 0 // 2 // Offset to Intra_4x4 luma prediction mode 1 // 4 // Offset to Intra_4x4 luma prediction mode 2 // 16 // Offset to Intra_4x4 luma prediction mode 3 // 23 // Offset to Intra_4x4 luma prediction mode 4 // 32 // Offset to Intra_4x4 luma prediction mode 5 // 45 // Offset to Intra_4x4 luma prediction mode 6 // 59 // Offset to Intra_4x4 luma prediction mode 7 // 66 // Offset to Intra_4x4 luma prediction mode 8 // 2857700364 // 0xAA550C0C - GUID for intra chroma prediction mode offsets // 0 // Offset to intra chroma prediction mode 0 // 30 // Offset to intra chroma prediction mode 1 // 36 // Offset to intra chroma prediction mode 2 // 41 // Offset to intra chroma prediction mode 3 // Kernel name: AllAVCMBAFF.asm // // All MBAFF frame picture HWMC kernels merged into this file // // $Revision: 1 $ // $Date: 4/13/06 4:35p $ // // ---------------------------------------------------- // Main: AllAVCMBAFF // ---------------------------------------------------- #define ALLHWMC #define COMBINED_KERNEL .kernel AllAVCMBAFF #include "Intra_PCM.asm" #include "Intra_16x16.asm" #include "Intra_8x8.asm" #include "Intra_4x4.asm" #include "scoreboard.asm" #define MBAFF #include "AVCMCInter.asm" // End of AllAVCMBAFF .end_kernel intel-driver-1.3.0/src/shaders/h264/mc/AllAVC_Build.inc000066400000000000000000000131651231401140700222740ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ $table { AllAVC_END_IP/INSTFACTOR // Total instruction count #if (defined(SW_SCOREBOARD) || defined(HW_SCOREBOARD)) && defined(ENABLE_ILDB) // 23 // Total kernel count #elif defined(SW_SCOREBOARD) || defined(HW_SCOREBOARD) // 11 // Total kernel count #elif defined(ENABLE_ILDB) // 21 // Total kernel count #else // 11 // Total kernel count #endif INTRA_16x16_ENTRY/INSTFACTOR // Instruction offset to 'Intra_16x16' INTRA_8x8_ENTRY/INSTFACTOR // Instruction offset to 'Intra_8x8' INTRA_4x4_ENTRY/INSTFACTOR // Instruction offset to 'Intra_4x4' INTRA_PCM_ENTRY/INSTFACTOR // Instruction offset to 'Intra_PCM' FRAME_MB_ENTRY/INSTFACTOR // Instruction offset to 'FrameMB_Motion' FIELD_MB_ENTRY/INSTFACTOR // Instruction offset to 'FieldMB_Motion' MBAFF_MB_ENTRY/INSTFACTOR // Instruction offset to 'MBAff_Motion' #ifdef SW_SCOREBOARD SCOREBOARD_ENTRY/INSTFACTOR // Instruction offset to 'scoreboard' SCOREBOARD_MBAFF_ENTRY/INSTFACTOR // Instruction offset to 'scoreboard_MBAFF' #elif defined(HW_SCOREBOARD) SETHWSCOREBOARD_ENTRY/INSTFACTOR // Instruction offset to 'AVC_SetIntraDepend' SETHWSCOREBOARD_MBAFF_ENTRY/INSTFACTOR // Instruction offset to 'AVC_SetIntraDependMBAFF' #endif // SW_SCOREBOARD #ifdef ENABLE_ILDB AVC_ILDB_ROOT_Y_ILDB_FRAME_ENTRY/INSTFACTOR // Instruction offset to 'AVC_ILDB_Root_Y' AVC_ILDB_CHILD_Y_ILDB_FRAME_ENTRY/INSTFACTOR // Instruction offset to 'AVC_ILDB_Child_Y' AVC_ILDB_ROOT_UV_ILDB_FRAME_ENTRY/INSTFACTOR // Instruction offset to 'AVC_ILDB_Root_UV' AVC_ILDB_CHILD_UV_ILDB_FRAME_ENTRY/INSTFACTOR // Instruction offset to 'AVC_ILDB_Child_UV' AVC_ILDB_ROOT_Y_ILDB_FIELD_ENTRY/INSTFACTOR // Instruction offset to 'AVC_ILDB_Root_Field_Y' AVC_ILDB_CHILD_Y_ILDB_FIELD_ENTRY/INSTFACTOR // Instruction offset to 'AVC_ILDB_Child_Field_Y' AVC_ILDB_ROOT_UV_ILDB_FIELD_ENTRY/INSTFACTOR // Instruction offset to 'AVC_ILDB_Root_Field_UV' AVC_ILDB_CHILD_UV_ILDB_FIELD_ENTRY/INSTFACTOR // Instruction offset to 'AVC_ILDB_Child_Field_UV' AVC_ILDB_ROOT_Y_ILDB_MBAFF_ENTRY/INSTFACTOR // Instruction offset to 'AVC_ILDB_Root_Mbaff_Y' AVC_ILDB_CHILD_Y_ILDB_MBAFF_ENTRY/INSTFACTOR // Instruction offset to 'AVC_ILDB_Child_Mbaff_Y' AVC_ILDB_ROOT_UV_ILDB_MBAFF_ENTRY/INSTFACTOR // Instruction offset to 'AVC_ILDB_Root_Mbaff_UV' AVC_ILDB_CHILD_UV_ILDB_MBAFF_ENTRY/INSTFACTOR // Instruction offset to 'AVC_ILDB_Child_Mbaff_UV' #endif // ENABLE_ILDB BSDRESET_ENTRY/INSTFACTOR // Instruction offset to 'BSDReset' DCRESETDUMMY_ENTRY/INSTFACTOR // Instruction offset to 'DCResetDummy' // 0 // Instruction offset to Intra_4x4_luma_prediction_mode_0 INTRA_4X4_HORIZONTAL_IP-INTRA_4X4_VERTICAL_IP // Instruction offset to Intra_4x4_luma_prediction_mode_1 INTRA_4X4_DC_IP-INTRA_4X4_VERTICAL_IP // Instruction offset to Intra_4x4_luma_prediction_mode_2 INTRA_4X4_DIAG_DOWN_LEFT_IP-INTRA_4X4_VERTICAL_IP // Instruction offset to Intra_4x4_luma_prediction_mode_3 INTRA_4X4_DIAG_DOWN_RIGHT_IP-INTRA_4X4_VERTICAL_IP // Instruction offset to Intra_4x4_luma_prediction_mode_4 INTRA_4X4_VERT_RIGHT_IP-INTRA_4X4_VERTICAL_IP // Instruction offset to Intra_4x4_luma_prediction_mode_5 INTRA_4X4_HOR_DOWN_IP-INTRA_4X4_VERTICAL_IP // Instruction offset to Intra_4x4_luma_prediction_mode_6 INTRA_4X4_VERT_LEFT_IP-INTRA_4X4_VERTICAL_IP // Instruction offset to Intra_4x4_luma_prediction_mode_7 INTRA_4X4_HOR_UP_IP-INTRA_4X4_VERTICAL_IP // Instruction offset to Intra_4x4_luma_prediction_mode_8 // 0 // Instruction offset to Intra_8x8_luma_prediction_mode_0 INTRA_8X8_HORIZONTAL_IP-INTRA_8X8_VERTICAL_IP // Instruction offset to Intra_8x8_luma_prediction_mode_1 INTRA_8X8_DC_IP-INTRA_8X8_VERTICAL_IP // Instruction offset to Intra_8x8_luma_prediction_mode_2 INTRA_8X8_DIAG_DOWN_LEFT_IP-INTRA_8X8_VERTICAL_IP // Instruction offset to Intra_8x8_luma_prediction_mode_3 INTRA_8X8_DIAG_DOWN_RIGHT_IP-INTRA_8X8_VERTICAL_IP // Instruction offset to Intra_8x8_luma_prediction_mode_4 INTRA_8X8_VERT_RIGHT_IP-INTRA_8X8_VERTICAL_IP // Instruction offset to Intra_8x8_luma_prediction_mode_5 INTRA_8X8_HOR_DOWN_IP-INTRA_8X8_VERTICAL_IP // Instruction offset to Intra_8x8_luma_prediction_mode_6 INTRA_8X8_VERT_LEFT_IP-INTRA_8X8_VERTICAL_IP // Instruction offset to Intra_8x8_luma_prediction_mode_7 INTRA_8X8_HOR_UP_IP-INTRA_8X8_VERTICAL_IP // Instruction offset to Intra_8x8_luma_prediction_mode_8 // 0 // Instruction offset to Intra_16x16_luma_prediction_mode_0 INTRA_16x16_HORIZONTAL_IP-INTRA_16x16_VERTICAL_IP // Instruction offset to Intra_16x16_luma_prediction_mode_1 INTRA_16x16_DC_IP-INTRA_16x16_VERTICAL_IP // Instruction offset to Intra_16x16_luma_prediction_mode_2 INTRA_16x16_PLANE_IP-INTRA_16x16_VERTICAL_IP // Instruction offset to Intra_16x16_luma_prediction_mode_3 // 0 // Instruction offset to intra_chroma_prediction_mode_0 INTRA_CHROMA_HORIZONTAL_IP-INTRA_CHROMA_DC_IP // Instruction offset to intra_chroma_prediction_mode_1 INTRA_CHROMA_VERTICAL_IP-INTRA_CHROMA_DC_IP // Instruction offset to intra_chroma_prediction_mode_2 INTRA_Chroma_PLANE_IP-INTRA_CHROMA_DC_IP // Instruction offset to intra_chroma_prediction_mode_3 intra_Pred_4x4_Y_IP-ADD_ERROR_SB3_IP*0x100+intra_Pred_4x4_Y_IP-ADD_ERROR_SB2_IP*0x100+intra_Pred_4x4_Y_IP-ADD_ERROR_SB1_IP*0x100+intra_Pred_4x4_Y_IP-ADD_ERROR_SB0_IP // Instruction offset to intra_4x4_pred_module } intel-driver-1.3.0/src/shaders/h264/mc/AllAVC_Export.inc000066400000000000000000000106241231401140700225130ustar00rootroot00000000000000.export entry_point INTRA_16x16 .export entry_point INTRA_8x8 .export entry_point INTRA_4x4 .export entry_point INTRA_PCM .export entry_point FRAME_MB .export entry_point FIELD_MB .export entry_point MBAFF_MB #ifdef SW_SCOREBOARD .export entry_point SCOREBOARD .export entry_point SCOREBOARD_MBAFF #elif defined(HW_SCOREBOARD) .export entry_point SETHWSCOREBOARD .export entry_point SETHWSCOREBOARD_MBAFF #endif // SW_SCOREBOARD #ifdef ENABLE_ILDB .export entry_point AVC_ILDB_ROOT_Y_ILDB_FRAME .export entry_point AVC_ILDB_CHILD_Y_ILDB_FRAME .export entry_point AVC_ILDB_ROOT_UV_ILDB_FRAME .export entry_point AVC_ILDB_CHILD_UV_ILDB_FRAME .export entry_point AVC_ILDB_ROOT_Y_ILDB_FIELD .export entry_point AVC_ILDB_CHILD_Y_ILDB_FIELD .export entry_point AVC_ILDB_ROOT_UV_ILDB_FIELD .export entry_point AVC_ILDB_CHILD_UV_ILDB_FIELD .export entry_point AVC_ILDB_ROOT_Y_ILDB_MBAFF .export entry_point AVC_ILDB_CHILD_Y_ILDB_MBAFF .export entry_point AVC_ILDB_ROOT_UV_ILDB_MBAFF .export entry_point AVC_ILDB_CHILD_UV_ILDB_MBAFF #endif // ENABLE_ILDB .export entry_point BSDRESET .export entry_point DCRESETDUMMY .export label INTRA_16x16_VERTICAL .export label INTRA_16x16_HORIZONTAL .export label INTRA_16x16_DC .export label INTRA_16x16_PLANE .export label INTRA_8X8_VERTICAL .export label INTRA_8X8_HORIZONTAL .export label INTRA_8X8_DC .export label INTRA_8X8_DIAG_DOWN_LEFT .export label INTRA_8X8_DIAG_DOWN_RIGHT .export label INTRA_8X8_VERT_RIGHT .export label INTRA_8X8_HOR_DOWN .export label INTRA_8X8_VERT_LEFT .export label INTRA_8X8_HOR_UP .export label INTRA_4X4_VERTICAL .export label INTRA_4X4_HORIZONTAL .export label INTRA_4X4_DC .export label INTRA_4X4_DIAG_DOWN_LEFT .export label INTRA_4X4_DIAG_DOWN_RIGHT .export label INTRA_4X4_VERT_RIGHT .export label INTRA_4X4_HOR_DOWN .export label INTRA_4X4_VERT_LEFT .export label INTRA_4X4_HOR_UP .export label INTRA_CHROMA_DC .export label INTRA_CHROMA_HORIZONTAL .export label INTRA_CHROMA_VERTICAL .export label INTRA_Chroma_PLANE .export label intra_Pred_4x4_Y .export label ADD_ERROR_SB0 .export label ADD_ERROR_SB1 .export label ADD_ERROR_SB2 .export label ADD_ERROR_SB3 .export label AllAVC_END #ifdef SW_SCOREBOARD .export label MB_Loop .export label No_Message .export label Dependency_Check .export label Notify_MSG .export label Update_CurMB .export label MBAFF_MB_Loop .export label MBAFF_No_Message .export label MBAFF_Dependency_Check .export label MBAFF_Notify_MSG .export label MBAFF_Update_CurMB //.export label // Definitions for first pass MC kernel building #ifndef No_Message_IP #define No_Message_IP 0 #endif #ifndef Dependency_Check_IP #define Dependency_Check_IP 0 #endif #ifndef Notify_MSG_IP #define Notify_MSG_IP 0 #endif #ifndef Update_CurMB_IP #define Update_CurMB_IP 0 #endif #ifndef MBAFF_No_Message_IP #define MBAFF_No_Message_IP 0 #endif #ifndef MBAFF_Dependency_Check_IP #define MBAFF_Dependency_Check_IP 0 #endif #ifndef MBAFF_Notify_MSG_IP #define MBAFF_Notify_MSG_IP 0 #endif #ifndef AS_ENABLED #ifndef MBAFF_MB_Loop_IP #define MBAFF_MB_Loop_IP 0 #endif #ifndef MB_Loop_IP #define MB_Loop_IP 0 #endif #endif // End AS_ENABLED #ifndef MBAFF_Update_CurMB_IP #define MBAFF_Update_CurMB_IP 0 #endif #endif // SW_SCOREBOARD /* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #ifdef ENABLE_ILDB .export label ALL_SPAWNED_UV_ILDB_FRAME .export label SLEEP_ENTRY_UV_ILDB_FRAME .export label POST_SLEEP_UV_ILDB_FRAME .export label ALL_SPAWNED_Y_ILDB_FRAME .export label SLEEP_ENTRY_Y_ILDB_FRAME .export label POST_SLEEP_Y_ILDB_FRAME // Definitions for first pass ILDB kernel building #ifndef ALL_SPAWNED_UV_ILDB_FRAME_IP #define ALL_SPAWNED_UV_ILDB_FRAME_IP 0 #endif #ifndef SLEEP_ENTRY_UV_ILDB_FRAME_IP #define SLEEP_ENTRY_UV_ILDB_FRAME_IP 0 #endif #ifndef POST_SLEEP_UV_ILDB_FRAME_IP #define POST_SLEEP_UV_ILDB_FRAME_IP 0 #endif #ifndef ALL_SPAWNED_Y_ILDB_FRAME_IP #define ALL_SPAWNED_Y_ILDB_FRAME_IP 0 #endif #ifndef SLEEP_ENTRY_Y_ILDB_FRAME_IP #define SLEEP_ENTRY_Y_ILDB_FRAME_IP 0 #endif #ifndef POST_SLEEP_Y_ILDB_FRAME_IP #define POST_SLEEP_Y_ILDB_FRAME_IP 0 #endif #endif // ENABLE_ILDB intel-driver-1.3.0/src/shaders/h264/mc/AllIntra.asm000066400000000000000000000051711231401140700216260ustar00rootroot00000000000000/* * All intra-prediction macroblock kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // 2857702934 // 0xAA551616 - GUID for Intra_16x16 luma prediction mode offsets // 0 // Offset to Intra_16x16 luma prediction mode 0 // 9 // Offset to Intra_16x16 luma prediction mode 1 // 19 // Offset to Intra_16x16 luma prediction mode 2 // 42 // Offset to Intra_16x16 luma prediction mode 3 // 2857699336 // 0xAA550808 - GUID for Intra_8x8 luma prediction mode offsets // 0 // Offset to Intra_8x8 luma prediction mode 0 // 5 // Offset to Intra_8x8 luma prediction mode 1 // 10 // Offset to Intra_8x8 luma prediction mode 2 // 26 // Offset to Intra_8x8 luma prediction mode 3 // 36 // Offset to Intra_8x8 luma prediction mode 4 // 50 // Offset to Intra_8x8 luma prediction mode 5 // 68 // Offset to Intra_8x8 luma prediction mode 6 // 85 // Offset to Intra_8x8 luma prediction mode 7 // 95 // Offset to Intra_8x8 luma prediction mode 8 // 2857698308 // 0xAA550404 - GUID for Intra_4x4 luma prediction mode offsets // 0 // Offset to Intra_4x4 luma prediction mode 0 // 2 // Offset to Intra_4x4 luma prediction mode 1 // 4 // Offset to Intra_4x4 luma prediction mode 2 // 16 // Offset to Intra_4x4 luma prediction mode 3 // 23 // Offset to Intra_4x4 luma prediction mode 4 // 32 // Offset to Intra_4x4 luma prediction mode 5 // 45 // Offset to Intra_4x4 luma prediction mode 6 // 59 // Offset to Intra_4x4 luma prediction mode 7 // 66 // Offset to Intra_4x4 luma prediction mode 8 // 2857700364 // 0xAA550C0C - GUID for intra chroma prediction mode offsets // 0 // Offset to intra chroma prediction mode 0 // 30 // Offset to intra chroma prediction mode 1 // 36 // Offset to intra chroma prediction mode 2 // 41 // Offset to intra chroma prediction mode 3 // Kernel name: AllIntra.asm // // All HWMC kernels merged into this file // // $Revision: 1 $ // $Date: 4/13/06 4:35p $ // // ---------------------------------------------------- // Main: ALLINTRA // ---------------------------------------------------- #define ALLHWMC #define COMBINED_KERNEL .kernel ALLINTRA // All frame destination HWMC kernels // #include "Intra_PCM.asm" #include "Intra_16x16.asm" #include "Intra_8x8.asm" #include "Intra_4x4.asm" // End of ALLINTRA .end_kernel intel-driver-1.3.0/src/shaders/h264/mc/BSDReset.asm000066400000000000000000000020361231401140700215300ustar00rootroot00000000000000/* * Initial kernel for filling initial BSD command buffer * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: BSDReset.asm // // Initial kernel for filling initial BSD command buffer // // ---------------------------------------------------- // Main: BSDReset // ---------------------------------------------------- .kernel BSDReset BSDRESET: #include "header.inc" .code #ifdef SW_SCOREBOARD CALL(scoreboard_start_inter,1) wait n0:ud // Now wait for scoreboard to response #define BSDRESET_ENABLE #include "scoreboard_update.asm" // scorboard update function #undef BSDRESET_ENABLE #endif // defined(SW_SCOREBOARD) // Terminate the thread // END_THREAD #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif // !defined(COMBINED_KERNEL) intel-driver-1.3.0/src/shaders/h264/mc/DCResetDummy.asm000066400000000000000000000014031231401140700224170ustar00rootroot00000000000000/* * Dummy kernel * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: DCResetDummy.asm // // Dummy kernel used by driver for debug-counter reset SW WA // // ---------------------------------------------------- // Main: DCResetDummy // ---------------------------------------------------- .kernel DCResetDummy DCRESETDUMMY: #include "header.inc" .code // Terminate the thread // END_THREAD #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif // !defined(COMBINED_KERNEL) intel-driver-1.3.0/src/shaders/h264/mc/Decode_Chroma_Intra.asm000066400000000000000000000016651231401140700237350ustar00rootroot00000000000000/* * Decode both intra chroma blocks * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__DECODE_CHROMA_INTRA__) // Make sure this is only included once #define __DECODE_CHROMA_INTRA__ // Module name: Decode_Chroma_Intra.asm // // Decode both intra chroma blocks // decode_Chroma_Intra: #ifndef MONO #include "load_Intra_Ref_UV.asm" // Load intra U/V reference data #include "intra_Pred_Chroma.asm" // Intra predict chroma blocks #include "add_Error_UV.asm" // Add error data to predicted U/V data blocks #endif // !defined(MONO) #include "save_8x8_UV.asm" // Save to destination U/V frame surface RETURN // End of Decode_Chroma_Intra #endif // !defined(__DECODE_CHROMA_INTRA__) intel-driver-1.3.0/src/shaders/h264/mc/EndIntraThread.asm000066400000000000000000000015641231401140700227560ustar00rootroot00000000000000/* * Common module to end current intra thread * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: EndIntraThread.asm // // Common module to end current intra thread // #ifndef SW_SCOREBOARD // Check for write commit first if SW scoreboard is disabled mov (1) REG_WRITE_COMMIT_Y<1>:ud REG_WRITE_COMMIT_Y<0;1,0>:ud // Make sure Y write is committed mov (1) REG_WRITE_COMMIT_UV<1>:ud REG_WRITE_COMMIT_UV<0;1,0>:ud // Make sure U/V write is committed #endif END_THREAD #include "Intra_funcLib.asm" #ifndef COMBINED_KERNEL // For standalone kernel only .end_code .end_kernel #endif // COMBINED_KERNEL // End of EndIntraThread intel-driver-1.3.0/src/shaders/h264/mc/HwmcOnlyHeader.inc000066400000000000000000000012441231401140700227570ustar00rootroot00000000000000/* * Header file used only in HWMC_ONLY mode * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: HwmcOnlyHeader.inc // // Header file used only in HWMC_ONLY mode // #include "header.inc" #if !defined(__HWMCONLYHEADER__) // Make sure the following are only included once #define __HWMCONLYHEADER__ .reg_count_total 64 .reg_count_payload 2 // // Now, begin source code.... // .code #endif // !defined(__HWMCONLYHEADER__) intel-driver-1.3.0/src/shaders/h264/mc/Intra_16x16.asm000066400000000000000000000030501231401140700220340ustar00rootroot00000000000000/* * Decode Intra_16x16 macroblock * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: Intra_16x16.asm // // Decoding of Intra_16x16 macroblock // // $Revision: 8 $ // $Date: 10/18/06 4:10p $ // // ---------------------------------------------------- // Main: Intra_16x16 // ---------------------------------------------------- #define INTRA_16X16 .kernel Intra_16x16 INTRA_16x16: #ifdef _DEBUG // WA for FULSIM so we'll know which kernel is being debugged mov (1) acc0:ud 0x00aa55a5:ud #endif #include "SetupForHWMC.asm" #ifdef SW_SCOREBOARD CALL(scoreboard_start_intra,1) #endif #ifdef SW_SCOREBOARD wait n0:ud // Now wait for scoreboard to response #endif // // Decode Y blocks // // Load reference data from neighboring macroblocks CALL(load_Intra_Ref_Y,1) // Intra predict Intra_16x16 luma block #include "intra_pred_16x16_Y.asm" // Add error data to predicted intra data #include "add_Error_16x16_Y.asm" // Save decoded Y picture CALL(save_16x16_Y,1) // // Decode U/V blocks // // Note: The decoding for chroma blocks will be the same for all intra prediction mode // CALL(decode_Chroma_Intra,1) #ifdef SW_SCOREBOARD #include "scoreboard_update.asm" #endif // Terminate the thread // #include "EndIntraThread.asm" // End of Intra_16x16 intel-driver-1.3.0/src/shaders/h264/mc/Intra_4x4.asm000066400000000000000000000167461231401140700217060ustar00rootroot00000000000000/* * Decode Intra_4x4 macroblock * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: Intra_4x4.asm // // Decoding of Intra_4x4 macroblock // // $Revision: 12 $ // $Date: 10/18/06 4:10p $ // // ---------------------------------------------------- // Main: Intra_4x4 // ---------------------------------------------------- #define INTRA_4X4 .kernel Intra_4x4 INTRA_4x4: #ifdef _DEBUG // WA for FULSIM so we'll know which kernel is being debugged mov (1) acc0:ud 0x02aa55a5:ud #endif #include "SetupForHWMC.asm" #undef PPREDBUF_Y #define PPREDBUF_Y a0.3 // Pointer to predicted Y picture #define REG_INTRA_PRED_AVAIL REG_INTRA_TEMP_4 #define REG_INTRA_4X4_PRED REG_INTRA_TEMP_7 // Store predicted Intra_4x4 data // Offset where 4x4 predicted data blocks are stored #define PREDSUBBLK0 0*GRFWIB #define PREDSUBBLK1 1*GRFWIB #define PREDSUBBLK2 2*GRFWIB #define PREDSUBBLK3 3*GRFWIB #define PREDSUBBLK4 4*GRFWIB #define PREDSUBBLK5 5*GRFWIB #define PREDSUBBLK6 6*GRFWIB #define PREDSUBBLK7 7*GRFWIB #define PREDSUBBLK8 8*GRFWIB #define PREDSUBBLK9 9*GRFWIB #define PREDSUBBLK10 10*GRFWIB #define PREDSUBBLK11 11*GRFWIB #define PREDSUBBLK12 12*GRFWIB #define PREDSUBBLK13 13*GRFWIB #define PREDSUBBLK14 14*GRFWIB #define PREDSUBBLK15 15*GRFWIB // 4x4 error block byte offset within the 8x8 error block #define ERRBLK0 0 #define ERRBLK1 8 #define ERRBLK2 64 #define ERRBLK3 72 #ifdef SW_SCOREBOARD CALL(scoreboard_start_intra,1) #endif #ifdef SW_SCOREBOARD wait n0:ud // Now wait for scoreboard to response #endif // // Decode Y blocks // // Load reference data from neighboring macroblocks CALL(load_Intra_Ref_Y,1) mov (1) PERROR<1>:w ERRBUF*GRFWIB:w // Pointer to macroblock error data mov (1) PPREDBUF_Y<1>:w PREDBUF*GRFWIB:w // Pointer to predicted data shr (2) REG_INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL_FLAG_BYTE<0;1,0>:ub 0x40:v and.nz.f0.0 (8) NULLREG REG_INTRA_PRED_AVAIL_FLAG_BYTE<0;1,0>:ub 4:w // Top-right macroblock available for intra prediction? (-f0.0.any8h) mov (8) INTRA_REF_TOP(0,16)<1> INTRA_REF_TOP(0,15)REGION(1,0) // Extend right boundary of MB B to C // Intra predict Intra_4x4 luma blocks // // Sub-macroblock 0 ***************** mov (16) REF_TOP0(0)<1> INTRA_REF_TOP0(0) // Top reference data mov (8) REF_LEFT(0)<1> INTRA_REF_LEFT(0)REGION(8,4) // Left reference data shr (4) PRED_MODE<1>:w INTRA_PRED_MODE(0)<1;2,0> 0x4040:v // Expand IntraPredMode to 1 byte/block CALL(intra_Pred_4x4_Y_4,1) add (1) PERROR<1>:w PERROR<0;1,0>:w 0x0080:w // Pointers to next error block or (1) REG_INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL<0;1,0>:w 0x1:w // Left neighbor is available now // Sub-macroblock 1 ***************** mov (16) REF_TOP0(0)<1> INTRA_REF_TOP0(0,8) // Top reference data mov (4) REF_LEFT(0)<1> r[PPREDBUF_Y,PREDSUBBLK1+6]<8;1,0>:ub // Left reference data (top half) mov (4) REF_LEFT(0,4)<1> r[PPREDBUF_Y,PREDSUBBLK3+6]<8;1,0>:ub // Left reference data (bottom half) shr (4) PRED_MODE<1>:w INTRA_PRED_MODE(0,2)<1;2,0> 0x4040:v // Expand IntraPredMode to 1 byte/block add (1) PPREDBUF_Y<1>:w PPREDBUF_Y<0;1,0>:w 4*GRFWIB:w // Pointer to predicted sub-macroblock 1 CALL(intra_Pred_4x4_Y_4,1) add (1) PERROR<1>:w PERROR<0;1,0>:w 0x0080:w // Pointers to next error block or (1) REG_INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL.1<0;1,0>:w 0x2:w // Top neighbor is available now // Pack constructed data from word-aligned to byte-aligned format // to speed up save_4x4_Y module later // PPREDBUF_Y now points to sub-block #4 mov (16) r[PPREDBUF_Y,-PREDSUBBLK4]<1>:ub r[PPREDBUF_Y,-PREDSUBBLK4]<32;16,2>:ub // Sub-block 0 mov (16) r[PPREDBUF_Y,0-PREDSUBBLK4+16]<1>:ub r[PPREDBUF_Y,-PREDSUBBLK3]<32;16,2>:ub // Sub-block 1 mov (16) r[PPREDBUF_Y,-PREDSUBBLK2]<1>:ub r[PPREDBUF_Y,-PREDSUBBLK2]<32;16,2>:ub // Sub-block 2 mov (16) r[PPREDBUF_Y,0-PREDSUBBLK2+16]<1>:ub r[PPREDBUF_Y,-PREDSUBBLK1]<32;16,2>:ub // Sub-block 3 mov (16) r[PPREDBUF_Y,-PREDSUBBLK3]<1>:ub r[PPREDBUF_Y]<32;16,2>:ub // Sub-block 4 mov (16) r[PPREDBUF_Y,0-PREDSUBBLK3+16]<1>:ub r[PPREDBUF_Y,PREDSUBBLK1]<32;16,2>:ub // Sub-block 5 mov (16) r[PPREDBUF_Y,-PREDSUBBLK1]<1>:ub r[PPREDBUF_Y,PREDSUBBLK2]<32;16,2>:ub // Sub-block 6 mov (16) r[PPREDBUF_Y,0-PREDSUBBLK1+16]<1>:ub r[PPREDBUF_Y,PREDSUBBLK3]<32;16,2>:ub // Sub-block 7 // Sub-macroblock 2 ***************** mov (4) REF_TOP0(0)<1> INTRA_REF_LEFT0(0,28)REGION(4,1) // Top-left reference data mov (8) REF_TOP0(0,4)<1> r[PPREDBUF_Y,0-2*GRFWIB+12]<16;4,1>:ub // Top reference data from SB 2,3 mov (8) REF_TOP0(0,12)<1> r[PPREDBUF_Y,0-GRFWIB+12]<16;4,1>:ub // Top reference data from SB 6,7 mov (8) REF_TOP0(0,20)<1> r[PPREDBUF_Y,0-GRFWIB+31]<0;1,0>:ub // Top-right reference data mov (16) REG_INTRA_REF_TOP<1>:w REF_TOP_W(0) // Store top reference data for SubMB #2 and #3. mov (8) REF_LEFT(0)<1> INTRA_REF_LEFT(1)REGION(8,4) // Left reference data shr (4) PRED_MODE<1>:w INTRA_PRED_MODE(0,4)<1;2,0> 0x4040:v // Expand IntraPredMode to 1 byte/block CALL(intra_Pred_4x4_Y_4,1) add (1) PERROR<1>:w PERROR<0;1,0>:w 0x0080:w // Pointers to next error block or (1) REG_INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL<0;1,0>:w 0x1:w // Left neighbor is available now // Sub-macroblock 3 ***************** mov (16) REF_TOP0(0)<1> INTRA_REF_TOP0(0,8) // Top reference data mov (8) REF_TOP0(0,16)<1> INTRA_REF_TOP0(0,24)REGION(8,1) // Top reference data mov (4) REF_LEFT(0)<1> r[PPREDBUF_Y,PREDSUBBLK1+6]<8;1,0>:ub // Left reference data (top half) mov (4) REF_LEFT(0,4)<1> r[PPREDBUF_Y,PREDSUBBLK3+6]<8;1,0>:ub // Left reference data (bottom half) shr (4) PRED_MODE<1>:w INTRA_PRED_MODE(0,6)<1;2,0> 0x4040:v // Expand IntraPredMode to 1 byte/block add (1) PPREDBUF_Y<1>:w PPREDBUF_Y<0;1,0>:w 4*GRFWIB:w // Pointer to predicted sub-macroblock 3 CALL(intra_Pred_4x4_Y_4,1) // Pack constructed data from word-aligned to byte-aligned format // to speed up save_4x4_Y module later // PPREDBUF_Y now points to sub-block #12 mov (16) r[PPREDBUF_Y,-PREDSUBBLK4]<1>:ub r[PPREDBUF_Y,-PREDSUBBLK4]<32;16,2>:ub // Sub-block 8 mov (16) r[PPREDBUF_Y,0-PREDSUBBLK4+16]<1>:ub r[PPREDBUF_Y,-PREDSUBBLK3]<32;16,2>:ub // Sub-block 9 mov (16) r[PPREDBUF_Y,-PREDSUBBLK2]<1>:ub r[PPREDBUF_Y,-PREDSUBBLK2]<32;16,2>:ub // Sub-block 10 mov (16) r[PPREDBUF_Y,0-PREDSUBBLK2+16]<1>:ub r[PPREDBUF_Y,-PREDSUBBLK1]<32;16,2>:ub // Sub-block 11 mov (16) r[PPREDBUF_Y,-PREDSUBBLK3]<1>:ub r[PPREDBUF_Y]<32;16,2>:ub // Sub-block 12 mov (16) r[PPREDBUF_Y,0-PREDSUBBLK3+16]<1>:ub r[PPREDBUF_Y,PREDSUBBLK1]<32;16,2>:ub // Sub-block 13 mov (16) r[PPREDBUF_Y,-PREDSUBBLK1]<1>:ub r[PPREDBUF_Y,PREDSUBBLK2]<32;16,2>:ub // Sub-block 14 mov (16) r[PPREDBUF_Y,0-PREDSUBBLK1+16]<1>:ub r[PPREDBUF_Y,PREDSUBBLK3]<32;16,2>:ub // Sub-block 15 // All 4 sub-macroblock (containing 4 intra_4x4 blocks) have be constructed // Save constructed Y picture CALL(save_4x4_Y,1) // Save Intra_4x4 predicted luma data. // // Decode U/V blocks // // Note: The decoding for chroma blocks will be the same for all intra prediction mode // CALL(decode_Chroma_Intra,1) #ifdef SW_SCOREBOARD #include "scoreboard_update.asm" #endif // Terminate the thread // #include "EndIntraThread.asm" // End of Intra_4x4 intel-driver-1.3.0/src/shaders/h264/mc/Intra_8x8.asm000066400000000000000000000232371231401140700217070ustar00rootroot00000000000000/* * Decode Intra_8x8 macroblock * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: Intra_8x8.asm // // Decoding of Intra_8x8 macroblock // // $Revision: 12 $ // $Date: 10/18/06 4:10p $ // // ---------------------------------------------------- // Main: Intra_8x8 // ---------------------------------------------------- #define INTRA_8X8 .kernel Intra_8x8 INTRA_8x8: #ifdef _DEBUG // WA for FULSIM so we'll know which kernel is being debugged mov (1) acc0:ud 0x01aa55a5:ud #endif #include "SetupForHWMC.asm" #define REG_INTRA_PRED_AVAIL REG_INTRA_TEMP_4 #define INTRA_PRED_AVAIL REG_INTRA_TEMP_4.4 // Offset where 8x8 predicted data blocks are stored #define PREDBLK0 0*GRFWIB #define PREDBLK1 4*GRFWIB #define PREDBLK2 8*GRFWIB #define PREDBLK3 12*GRFWIB #ifdef SW_SCOREBOARD // Update "E" flag with "F" flag information mov (1) REG_INTRA_TEMP_0<1>:w REG_INTRA_PRED_AVAIL_FLAG_WORD<0;1,0>:w // Store original Intra_Pred_Avail_Flag and.nz.f0.0 (1) NULLREG REG_MBAFF_PIC MBAFF_PIC // Is current MBAFF picture and.z.f0.1 (1) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_LEFT_TH_AVAIL_FLAG // Is "A" not available? (f0.0) and.z.f0.0 (1) NULLREG REG_FIELD_MACROBLOCK_FLAG FIELD_MACROBLOCK_FLAG // Is current frame MB? (f0.1) and.nz.f0.1 (1) NULLREG REG_INTRA_PRED_8X8_BLK2_AVAIL_FLAG INTRA_PRED_8X8_BLK2_AVAIL_FLAG // Is "F" flag set? (f0.0.allv) or (1) REG_INTRA_PRED_AVAIL_FLAG_WORD<1>:w REG_INTRA_PRED_AVAIL_FLAG_WORD<0;1,0>:w INTRA_PRED_LEFT_BH_AVAIL_FLAG // Set "E" to 1 if all conditions meet CALL(scoreboard_start_intra,1) mov (1) REG_INTRA_PRED_AVAIL_FLAG_WORD<1>:w REG_INTRA_TEMP_0<0;1,0>:w // Restore original Intra_Pred_Avail_Flag #endif #ifdef SW_SCOREBOARD wait n0:ud // Now wait for scoreboard to response #endif // // Decode Y blocks // // Load reference data from neighboring macroblocks CALL(load_Intra_Ref_Y,1) mov (1) PERROR<1>:w ERRBUF*GRFWIB:w // Pointer to macroblock error data mov (1) PDECBUF_UD<1>:ud 0x00010001*PREDBUF*GRFWIB+0x00100000:ud // Pointers to predicted data shr (2) REG_INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL_FLAG_BYTE<0;1,0>:ub 0x40:v #if 1 mov (4) REF_LEFT_D(0,0)<1> 0:ud // This is to make validation easier. Without it, DRAM mismatch occurs. #endif // Intra predict Intra_8x8 luma blocks // // Sub-macroblock 0 ***************** mov (16) REF_TOP_W(0)<1> REG_INTRA_REF_TOP<16;16,1>:w // Copy entire top reference data and.nz.f0.0 (8) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_UP_LEFT_AVAIL_FLAG // Is "D" available? (-f0.0) mov (1) REF_TOP(0,-1)<1> INTRA_REF_TOP(0)REGION(1,0) // p[-1,-1] = p[0,-1] mov (8) REF_LEFT(0,2)<1> INTRA_REF_LEFT(0) // Left reference data, (leave 2 for reference filtering) (-f0.0) mov (1) REF_LEFT(0,1)<1> INTRA_REF_LEFT(0)REGION(1,0) // p[-1,-1]=p[-1,0] (f0.0.any2h) mov (2) REF_LEFT(0,0)<1> INTRA_REF_TOP(0,-1)REGION(1,0) // p'[-1,y] (y=0,1) = p[-1,-1] and.nz.f0.1 (1) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_UP_AVAIL_FLAG // Is "B" available? (f0.1) mov (1) REF_LEFT(0,0)<1> INTRA_REF_TOP(0,0)REGION(1,0) // p[0,-1] for left filtering and.nz.f0.1 (1) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_LEFT_TH_AVAIL_FLAG // Is "A" available? (-f0.1) mov (1) REF_LEFT(0,2)<1> INTRA_REF_TOP(0,-1)REGION(1,0) // p'[-1,2] = p[-1,-1] and (1) PRED_MODE<1>:w INTRA_PRED_MODE(0)REGION(1,0) 0x0F:w // Intra pred mode for current block mov (1) INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL<0;1,0>:w // Top/Left neighbor available flags CALL(intra_Pred_8x8_Y,1) add (1) PERROR<1>:w PERROR<0;1,0>:w 0x0080:w // Pointers to next error block // Sub-macroblock 1 ***************** mov (16) REF_TOP0(0)<1> INTRA_REF_TOP(0,4) // Top reference data and.nz.f0.1 (8) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_UP_RIGHT_AVAIL_FLAG // Is "C" available? (f0.1.any8h) mov (8) REF_TOP(0,8)<1> INTRA_REF_TOP(0,16)<8;8,1> // Take data from "C" (-f0.1.any8h) mov (8) REF_TOP(0,8)<1> INTRA_REF_TOP(0,15)REGION(1,0) // Repeat last pixel from "B" mov (4) REF_LEFT(0,2)<1> DEC_Y(0,14)<16;1,0> // Left reference data (top half) (leave 2 for reference filtering) mov (4) REF_LEFT(0,6)<1> DEC_Y(2,14)<16;1,0> // Left reference data (bottom half) mov (2) REF_LEFT(0,0)<1> INTRA_REF_TOP(0,7)REGION(1,0) // p'[-1,y] (y=0,1) = p[-1,-1] and.nz.f0.1 (1) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_UP_AVAIL_FLAG // Is "B" available? (f0.1) mov (1) REF_LEFT(0,0)<1> INTRA_REF_TOP(0,8)REGION(1,0) // p[-1,-1] for left filtering (-f0.1) mov (1) REF_LEFT(0,1)<1> DEC_Y(0,14)REGION(1,0) // p[-1,-1] = p[-1,0] shr (1) PRED_MODE<1>:w INTRA_PRED_MODE(0)REGION(1,0) 4:w // Intra pred mode for current block add (2) PPREDBUF_Y<1>:w PPREDBUF_Y<2;2,1>:w 4*GRFWIB:w // Pointer to predicted sub-macroblock 1 or (1) INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL<0;1,0>:w 1:w // Left neighbor is available CALL(intra_Pred_8x8_Y,1) add (1) PERROR<1>:w PERROR<0;1,0>:w 0x0080:w // Pointers to next error block // Pack constructed data from word-aligned to byte-aligned format and interlace Y0 and Y1(every two Y rows) // to speed up save_8x8_Y module later // PPREDBUF_Y now points to sub-macroblock Y1 mov (32) r[PPREDBUF_Y,-PREDBLK1]<1>:ub DEC_Y(0)<32;16,2> {Compr} // First 4 Y0 rows mov (32) r[PPREDBUF_Y,0-PREDBLK1+32]<1>:ub DEC_Y(4)<32;16,2> {Compr} // First 4 Y1 rows mov (32) r[PPREDBUF_Y,0-PREDBLK1+64]<1>:ub DEC_Y(2)<32;16,2> {Compr} // Second 4 Y0 rows mov (32) r[PPREDBUF_Y,0-PREDBLK1+96]<1>:ub DEC_Y(6)<32;16,2> {Compr} // Second 4 Y1 rows // Sub-macroblock 2 ***************** // Intra_8x8 special available flag handling and.nz.f0.0 (1) NULLREG REG_MBAFF_PIC MBAFF_PIC // Is current MBAFF picture and.z.f0.1 (1) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_LEFT_TH_AVAIL_FLAG // Is "A" not available? (f0.0) and.z.f0.0 (1) NULLREG REG_FIELD_MACROBLOCK_FLAG FIELD_MACROBLOCK_FLAG // Is current frame MB? (f0.1) and.nz.f0.1 (1) NULLREG REG_INTRA_PRED_8X8_BLK2_AVAIL_FLAG INTRA_PRED_8X8_BLK2_AVAIL_FLAG // Is special intra_8x8 available flag set? (f0.0.allv) mov (1) REF_TOP(0,-1)<1> INTRA_REF_LEFT0(0,31)REGION(1,0) // Top-left reference data (f0.0.allv) jmpi (1) INTRA_8x8_BLK2 // Done intra_8x8 special available flag handling and.nz.f0.0 (8) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_LEFT_TH_AVAIL_FLAG // Is top-half "A" available? (f0.0.any4h) mov (4) REF_TOP0(0)<1> INTRA_REF_LEFT0(0,28)REGION(4,1) // Top-left reference data (-f0.0) mov (1) REF_TOP(0,-1)<1> DEC_Y(2,24)REGION(1,0) // p[-1,-1] = p[0,-1] INTRA_8x8_BLK2: mov (8) REF_TOP(0)<1> DEC_Y(2,24)REGION(8,1) // Top reference data mov (8) REF_TOP(0,8)<1> DEC_Y(3,24)REGION(8,1) // Top reference data mov (8) REF_LEFT(0,2)<1> INTRA_REF_LEFT(1) // Left reference data, (leave 2 for reference filtering) mov (1) REF_LEFT(0,0)<1> DEC_Y(2,24)REGION(1,0) // p'[-1,0] = p[0,-1] since "B" is always available (f0.0) mov (1) REF_LEFT(0,1)<1> INTRA_REF_LEFT(0,28)REGION(1,0) // p[-1,1] = p[-1,-1] if top-half "A" available (-f0.0) mov (1) REF_LEFT(0,1)<1> INTRA_REF_LEFT(1)REGION(1,0) // p[-1,1] = p[-1,0] and.nz.f0.1 (1) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_LEFT_BH_AVAIL_FLAG // Is bottom-half "A" available? (-f0.1) mov (1) REF_LEFT(0,2)<1> INTRA_REF_LEFT(0,28)REGION(1,0) // p'[-1,2] = p[-1,-1] and (1) PRED_MODE<1>:w INTRA_PRED_MODE(0,1)REGION(1,0) 0x0F:w // Intra pred mode for current block or (1) INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL.1<0;1,0>:w 2:w // Top neighbor is available CALL(intra_Pred_8x8_Y,1) add (1) PERROR<1>:w PERROR<0;1,0>:w 0x0080:w // Pointers to next error block // Sub-macroblock 3 ***************** mov (4) REF_TOP0(0)<1> DEC_Y(2,28)REGION(4,1) // Top-left reference data mov (8) REF_TOP(0)<1> DEC_Y(3,24)REGION(8,1) // Top reference data mov (16) REF_TOP(0,8)<1> DEC_Y(3,31)REGION(1,0) // Top-right reference data mov (4) REF_LEFT(0,2)<1> DEC_Y(4,14)<16;1,0> // Left reference data (top half) (leave 2 for reference filtering) mov (4) REF_LEFT(0,6)<1> DEC_Y(6,14)<16;1,0> // Left reference data (bottom half) mov (1) REF_LEFT(0,0)<1> DEC_Y(3,24)REGION(1,0) // p[-1,0] = p[0,-1] mov (1) REF_LEFT(0,1)<1> DEC_Y(2,31)REGION(1,0) // p[-1,1] = p[-1,-1] shr (1) PRED_MODE<1>:w INTRA_PRED_MODE(0,1)REGION(1,0) 4:w // Intra pred mode for current block add (2) PPREDBUF_Y<1>:w PPREDBUF_Y<2;2,1>:w 4*GRFWIB:w // Pointer to predicted sub-macroblock 3 or (1) INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL<0;1,0>:w 3:w // Top and Left neighbor are available CALL(intra_Pred_8x8_Y,1) // Pack constructed data from word-aligned to byte-aligned format // to speed up save_8x8_Y module later // PPREDBUF_Y now points to sub-macroblock Y1 mov (32) r[PPREDBUF_Y,-PREDBLK1]<1>:ub DEC_Y(4)<32;16,2> {Compr} // First 4 Y2 rows mov (32) r[PPREDBUF_Y,0-PREDBLK1+32]<1>:ub DEC_Y(8)<32;16,2> {Compr} // First 4 Y3 rows mov (32) r[PPREDBUF_Y,0-PREDBLK1+64]<1>:ub DEC_Y(6)<32;16,2> {Compr} // Second 4 Y2 rows mov (32) r[PPREDBUF_Y,0-PREDBLK1+96]<1>:ub DEC_Y(10)<32;16,2> {Compr} // Second 4 Y3 rows // All 4 sub-macroblock (containing 4 intra_8x8 blocks) have be constructed // Save constructed Y picture CALL(save_8x8_Y,1) // Save Intra_8x8 predicted luma data. // // Decode U/V blocks // // Note: The decoding for chroma blocks will be the same for all intra prediction mode // CALL(decode_Chroma_Intra,1) #ifdef SW_SCOREBOARD #include "scoreboard_update.asm" #endif // Terminate the thread // #include "EndIntraThread.asm" // End of Intra_8x8 intel-driver-1.3.0/src/shaders/h264/mc/Intra_PCM.asm000066400000000000000000000027571231401140700217030ustar00rootroot00000000000000/* * Decode Intra_PCM macroblock * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: Intra_PCM.asm // // Decoding of I_PCM macroblock // // $Revision: 8 $ // $Date: 10/18/06 4:10p $ // // ---------------------------------------------------- // Main: Intra_PCM // ---------------------------------------------------- .kernel Intra_PCM INTRA_PCM: #ifdef _DEBUG // WA for FULSIM so we'll know which kernel is being debugged mov (1) acc0:ud 0x03aa55a5:ud #endif #include "SetupForHWMC.asm" // Not actually needed here but just want to slow down the Intra-PCM to avoid race condition // #ifdef SW_SCOREBOARD and (1) REG_INTRA_PRED_AVAIL_FLAG_WORD<1>:w REG_INTRA_PRED_AVAIL_FLAG_WORD<0;1,0>:w 0xffe0:w // Ensure all neighbor avail flags are "0" CALL(scoreboard_start_intra,1) wait n0:ud // Now wait for scoreboard to response #endif // // Decoding Y blocks // // In I_PCM mode, the samples are already arranged in raster scan order within the macroblock. // We just need to save them to picture buffers // #include "save_I_PCM.asm" // Save to destination picture buffers #ifdef SW_SCOREBOARD #include "scoreboard_update.asm" #endif // Terminate the thread // #include "EndIntraThread.asm" // End of Intra_PCM intel-driver-1.3.0/src/shaders/h264/mc/Intra_funcLib.asm000066400000000000000000000033371231401140700226410ustar00rootroot00000000000000/* * Library of common modules shared among different intra prediction kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: Intra_funcLib.asm // // Library of common modules shared among different intra prediction kernels // // Note: Any sub-modules, if they are #included in more than one kernel, // should be moved to this module. // #if defined(INTRA_16X16) #undef INTRA_16X16 #include "load_Intra_Ref_Y.asm" // Load intra Y reference data #include "Decode_Chroma_Intra.asm" // Decode chroma blocks #include "save_16x16_Y.asm" // Save to destination Y frame surface #elif defined(INTRA_8X8) #undef INTRA_8X8 #include "load_Intra_Ref_Y.asm" // Load intra Y reference data #include "Decode_Chroma_Intra.asm" // Decode chroma blocks #include "intra_Pred_8x8_Y.asm" // Intra predict Intra_4x4 blocks #include "save_8x8_Y.asm" // Save to destination Y frame surface #elif defined(INTRA_4X4) #undef INTRA_4X4 #include "load_Intra_Ref_Y.asm" // Load intra Y reference data #include "Decode_Chroma_Intra.asm" // Decode chroma blocks #include "intra_Pred_4x4_Y_4.asm" // Intra predict Intra_4x4 blocks #include "save_4x4_Y.asm" // Save to destination Y frame surface #else // For all merged kernels #endif #ifdef SW_SCOREBOARD #include "scoreboard_start_intra.asm" // scorboard intra start function #include "scoreboard_start_inter.asm" // scorboard inter start function #endif // SW_SCOREBOARD // End of Intra_funcLib intel-driver-1.3.0/src/shaders/h264/mc/Makefile.am000066400000000000000000000137401231401140700214530ustar00rootroot00000000000000 INTEL_G4I = INTEL_G4A = null.g4a INTEL_G4B = null.g4b INTEL_G4B_GEN5 = null.g4b.gen5 INTEL_MC_G4B = avc_mc.g4b INTEL_MC_G4B_GEN5 = avc_mc.g4b.gen5 INTEL_MC_EXPORT = export.inc INTEL_MC_EXPORT_GEN5 = export.inc.gen5 INTEL_MC_ASM = \ add_Error_16x16_Y.asm \ add_Error_UV.asm \ AllAVC.asm \ AllAVCField.asm \ AllAVCFrame.asm \ AllAVCMBAFF.asm \ AllIntra.asm \ AVCMCInter.asm \ BSDReset.asm \ chromaMVAdjust.asm \ DCResetDummy.asm \ Decode_Chroma_Intra.asm \ EndIntraThread.asm \ initialize_MBPara.asm \ interpolate_C_2x2.asm \ interpolate_C_4x4.asm \ interpolate_Y_4x4.asm \ interpolate_Y_8x8.asm \ Intra_16x16.asm \ Intra_4x4.asm \ Intra_8x8.asm \ Intra_funcLib.asm \ Intra_PCM.asm \ intra_pred_16x16_Y.asm \ intra_Pred_4x4_Y_4.asm \ intra_Pred_8x8_Y.asm \ intra_Pred_Chroma.asm \ load_Intra_Ref_UV.asm \ load_Intra_Ref_Y.asm \ loadRef_C_10x5.asm \ loadRef_C_6x3.asm \ loadRef_Y_16x13.asm \ loadRef_Y_16x9.asm \ recon_C_4x4.asm \ recon_Y_8x8.asm \ roundShift_C_4x4.asm \ save_16x16_Y.asm \ save_4x4_Y.asm \ save_8x8_UV.asm \ save_8x8_Y.asm \ save_I_PCM.asm \ scoreboard.asm \ scoreboard_MBAFF.asm \ scoreboard_restore_AS.asm \ scoreboard_save_AS.asm \ scoreboard_sip.asm \ scoreboard_start_inter.asm \ scoreboard_start_intra.asm \ scoreboard_update.asm \ SetHWScoreboard.asm \ SetHWScoreboard_MBAFF.asm \ set_SB_offset.asm \ SetupForHWMC.asm \ weightedPred.asm \ writeRecon_C_8x4.asm \ writeRecon_Y_16x8.asm \ writeRecon_YC.asm INTEL_MC_INC = \ AllAVC_Build.inc \ AllAVC_Export.inc \ export.inc \ header.inc \ HwmcOnlyHeader.inc \ inter_Header.inc \ intra_Header.inc \ Scoreboard_header.inc \ SetHWScoreboard_header.inc \ $(NULL) INTEL_ILDB_ASM = \ ../ildb/AVC_ILDB_Child_Field_UV.asm \ ../ildb/AVC_ILDB_Child_Field_Y.asm \ ../ildb/AVC_ILDB_Child_Mbaff_UV.asm \ ../ildb/AVC_ILDB_Child_Mbaff_Y.asm \ ../ildb/AVC_ILDB_Child_UV.asm \ ../ildb/AVC_ILDB_Child_Y.asm \ ../ildb/AVC_ILDB_Chroma_Core.asm \ ../ildb/AVC_ILDB_Chroma_Core_Mbaff.asm \ ../ildb/AVC_ILDB_CloseGateway.asm \ ../ildb/AVC_ILDB_Dep_Check.asm \ ../ildb/AVC_ILDB_Filter_Mbaff_UV_h.asm \ ../ildb/AVC_ILDB_Filter_Mbaff_UV_v.asm \ ../ildb/AVC_ILDB_Filter_Mbaff_Y_h.asm \ ../ildb/AVC_ILDB_Filter_Mbaff_Y_v.asm \ ../ildb/AVC_ILDB_Filter_UV_h.asm \ ../ildb/AVC_ILDB_Filter_UV_v.asm \ ../ildb/AVC_ILDB_Filter_Y_h.asm \ ../ildb/AVC_ILDB_Filter_Y_v.asm \ ../ildb/AVC_ILDB_ForwardMsg.asm \ ../ildb/AVC_ILDB_Luma_Core.asm \ ../ildb/AVC_ILDB_Luma_Core_Mbaff.asm \ ../ildb/AVC_ILDB_LumaThrdLimit.asm \ ../ildb/AVC_ILDB_OpenGateway.asm \ ../ildb/AVC_ILDB_Root_Field_UV.asm \ ../ildb/AVC_ILDB_Root_Field_Y.asm \ ../ildb/AVC_ILDB_Root_Mbaff_UV.asm \ ../ildb/AVC_ILDB_Root_Mbaff_Y.asm \ ../ildb/AVC_ILDB_Root_UV.asm \ ../ildb/AVC_ILDB_Root_Y.asm \ ../ildb/AVC_ILDB_Spawn.asm \ ../ildb/AVC_ILDB_SpawnChild.asm \ ../ildb/AVC_ILDB_SpawnChromaRoot.asm \ ../ildb/load_Cur_UV_8x8T.asm \ ../ildb/load_Cur_UV_8x8T_Mbaff.asm \ ../ildb/load_Cur_UV_Right_Most_2x8.asm \ ../ildb/load_Cur_Y_16x16T.asm \ ../ildb/load_Cur_Y_16x16T_Mbaff.asm \ ../ildb/load_Cur_Y_Right_Most_4x16.asm \ ../ildb/Load_ILDB_Cntrl_Data_16DW.asm \ ../ildb/Load_ILDB_Cntrl_Data_22DW.asm \ ../ildb/Load_ILDB_Cntrl_Data_64DW.asm \ ../ildb/Load_ILDB_Cntrl_Data.asm \ ../ildb/load_Left_UV_2x8T.asm \ ../ildb/load_Left_UV_2x8T_Mbaff.asm \ ../ildb/load_Left_Y_4x16T.asm \ ../ildb/load_Left_Y_4x16T_Mbaff.asm \ ../ildb/loadNV12_16x16T.asm \ ../ildb/loadNV12_16x4.asm \ ../ildb/load_Top_UV_8x2.asm \ ../ildb/load_Top_UV_8x2_Mbaff.asm \ ../ildb/load_Top_Y_16x4.asm \ ../ildb/load_Top_Y_16x4_Mbaff.asm \ ../ildb/save_Cur_UV_8x8.asm \ ../ildb/save_Cur_UV_8x8_Mbaff.asm \ ../ildb/save_Cur_Y_16x16.asm \ ../ildb/save_Cur_Y_16x16_Mbaff.asm \ ../ildb/save_Left_UV_8x2T.asm \ ../ildb/save_Left_UV_8x2T_Mbaff.asm \ ../ildb/save_Left_Y_16x4T.asm \ ../ildb/save_Left_Y_16x4T_Mbaff.asm \ ../ildb/saveNV12_16x16.asm \ ../ildb/saveNV12_16x4.asm \ ../ildb/saveNV12_16x4T.asm \ ../ildb/save_Top_UV_8x2.asm \ ../ildb/save_Top_UV_8x2_Mbaff.asm \ ../ildb/save_Top_Y_16x4.asm \ ../ildb/save_Top_Y_16x4_Mbaff.asm \ ../ildb/SetupVPKernel.asm \ ../ildb/Transpose_Cur_UV_2x8.asm \ ../ildb/Transpose_Cur_UV_8x8.asm \ ../ildb/Transpose_Cur_UV_Right_Most_2x8.asm \ ../ildb/Transpose_Cur_Y_16x16.asm \ ../ildb/Transpose_Cur_Y_4x16.asm \ ../ildb/Transpose_Cur_Y_Right_Most_4x16.asm \ ../ildb/Transpose_Left_UV_2x8.asm \ ../ildb/Transpose_Left_Y_4x16.asm \ ../ildb/TransposeNV12_16x16.asm \ ../ildb/TransposeNV12_4x16.asm \ ../ildb/writeURB.asm \ ../ildb/writeURB_UV_Child.asm \ ../ildb/writeURB_Y_Child.asm INTEL_MC_GEN5_ASM = avc_mc.gen5.asm TARGETS = if HAVE_GEN4ASM TARGETS += $(INTEL_MC_G4B_GEN5) endif all-local: $(TARGETS) SUFFIXES = .g4a .g4b .gen5.asm if HAVE_GEN4ASM .g4a.g4b: $(AM_V_GEN)m4 $*.g4a > $*.g4m && \ $(AM_V_GEN)$(GEN4ASM) -o $@ $*.g4m && \ $(AM_V_GEN)$(GEN4ASM) -g 5 -o $@.gen5 $*.g4m && \ rm $*.g4m $(INTEL_MC_GEN5_ASM): $(INTEL_MC_ASM) $(INTEL_MC_INC) $(INTEL_ILDB_ASM) $(AM_V_GEN)cpp -DDEV_ILK -DBOOTSTRAP -I ../ildb/ AllAVC.asm > _mc0.$@ && \ ../../gpp.py _mc0.$@ $@ && \ $(GEN4ASM) -l list -a -e tmp.$(INTEL_MC_EXPORT_GEN5) -g 5 $@ \ -o /dev/null && \ mv tmp.$(INTEL_MC_EXPORT_GEN5) $(INTEL_MC_EXPORT_GEN5) && \ cpp -DDEV_ILK -I ../ildb/ AllAVC.asm > _mc1.$@ && \ ../../gpp.py _mc1.$@ $@ && \ rm _mc0.$@ _mc1.$@ $(INTEL_MC_G4B_GEN5): $(INTEL_MC_GEN5_ASM) $(AM_V_GEN)$(GEN4ASM) -l list -a -e tmp.$(INTEL_MC_EXPORT_GEN5) -g 5 $< \ -o $@ && \ cat tmp.$(INTEL_MC_EXPORT_GEN5) | sed "s/_IP/_IP_GEN5/g" \ > $(INTEL_MC_EXPORT_GEN5) && \ rm tmp.$(INTEL_MC_EXPORT_GEN5) $(INTEL_G4B): $(INTEL_G4I) endif CLEANFILES = $(INTEL_MC_GEN5_ASM) EXTRA_DIST = \ $(INTEL_G4A) \ $(INTEL_G4B) \ $(INTEL_G4B_GEN5) \ $(INTEL_G4I) \ $(INTEL_MC_ASM) \ $(INTEL_MC_EXPORT) \ $(INTEL_MC_EXPORT_GEN5) \ $(INTEL_MC_G4B) \ $(INTEL_MC_G4B_GEN5) \ $(INTEL_MC_INC) \ list \ $(NULL) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/h264/mc/Scoreboard_header.inc000066400000000000000000000105561231401140700235070ustar00rootroot00000000000000/* * Common header file for both scoreboard and scoreboard_MBAFF kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__SCOREBOARD_HEADER__) // Make sure this file is only included once #define __SCOREBOARD_HEADER__ // Module name: scoreboard_header.inc // // Common header file for both scoreboard and scoreboard_MBAFF kernels // #define ONE_MB_WA // Enable WA for 1-MB wide pictures. To disable WA, simply comment out this line. #define INLINE_REG_OFF 1 #define INLINE_REG r1 #define INLINE_REG1 r2 #define DONEFLAG 0x40 // Bit mask of "completed" thread flag // GRF r1 map // #define WIDTHINMB_1 INLINE_REG.0 // :uw type. Picture width in MB - 1 #define HEIGHTINMB_1 INLINE_REG.1 // :uw type. Picture height in MB - 1 #define TotalMB INLINE_REG.2 // :uw type. Total number of macroblocks #define WFLen_B INLINE_REG.3 // :uw type. Bottom MB Wavefront length (Reserved for MBAFF scoreboard) #define WFLen INLINE_REG.4 // :uw type. Wavefront length (used as loop counter) #define WFLenY INLINE_REG.5 // :uw type. Wavefront length (vertical component) #define StartX INLINE_REG.6 // :uw type. Start X of current wavefront #define StartY INLINE_REG.7 // :uw type. Start Y of current wavefront #define StartXD INLINE_REG.3 // :ud type. Start (X,Y) of current wavefront #define CASE00PTR INLINE_REG.4 // :ud type. Pointer to "inter start" handler #define WFLen_Save INLINE_REG.10 // :uw type. Saved Wavefront length (Reserved for MBAFF scoreboard) #define CASE10PTR INLINE_REG.6 // :ud type. Pointer to "intra start" handler #define CASE11PTR INLINE_REG.7 // :ud type. Pointer to "inter complete" handler // GRF r2 map // .declare WFStart Base=GRF(2) ElementSize=2 SrcRegion=REGION(4,1) Type=w // Start MB of recent 4 wavefronts, actually use 5 WORDs .declare WFStart_T Base=GRF(2) ElementSize=2 SrcRegion=REGION(4,1) Type=w // Start MB of recent 4 wavefronts .declare WFStart_B Base=GRF(2).4 ElementSize=2 SrcRegion=REGION(4,1) Type=w // Start MB of recent 4 wavefronts #define NewWFOffsetD INLINE_REG1.5 // :d type. Offsets used for new wavefront = 0x01ffff00 (0, -1, -1, 1) #define NewWFOffset INLINE_REG1.20 // :b type. Offsets used for new wavefront = 0x01ffff00 (0, -1, -1, 1) #define AVAILFLAGD INLINE_REG1.6 // :ud type. Neighbor available flags = 0x08020401 (in ACBD order) #define AVAILFLAG INLINE_REG1.24 // :ub type. Neighbor available flags as above #define AVAILFLAG1D INLINE_REG1.7 // :ud type. Top-half neighbor available flags = 0x80402010 (in A_Bxxx order) .declare MBINDEX Base=GRF(3) ElementSize=2 SrcRegion=REGION(16,1) Type=w // MB order # of current MB group (Cur, ACBD and AC_B_D_) #define AR_SAVE r3.8 // :uw type. Saved Address Register information #define CMDPTR a0.0 // :uw type. DWORD Pointer to the scoreboard #define DEPPTR a0.0 // :uw type. Pointer to the dependency scoreboard - Current MB #define DEPPTRL a0.1 // :uw type. Pointer to the dependency scoreboard - Left MB #define DEPPTRTR a0.2 // :uw type. Pointer to the dependency scoreboard - Top right MB #define DEPPTRT a0.3 // :uw type. Pointer to the dependency scoreboard - Top MB #define DEPPTRTL a0.4 // :uw type. Pointer to the dependency scoreboard - Top left MB #define DEPPTRLB a0.5 // :uw type. Pointer to the dependency scoreboard - Left bottom-half MB #define PMSGSEL a0.7 // :uw type. Pointer to current message in message handling table #define CMD_SB_REG_OFF 4 .declare CMD_SB Base=GRF(4) ElementSize=4 SrcRegion=REGION(8,1) Type=ud // Command scoreboard (64 GRF) #ifdef AS_ENABLED // Definitions for Advanced Scheduler support #define AS_INT BIT23 // "Preemption Exception Status" bit in cr0.1:ud control register #define AS_INT_EN BIT10 // "Preemption Exception Enable" bit in cr0.1:ud control register #define TH_INT BIT2 // "Thread Interrupted" bit in message descriptor #define TH_RES BIT0 // "Thread Restart Enable" bit in R0 header r0.2 #define AS_SAVE 34 // Surface state for saving scoreboard contents // Ensure not to conflict with existing binding table entries #endif // End AS_ENABLED // End of scoreboard_header #endif // !defined(__SCOREBOARD_HEADER__) intel-driver-1.3.0/src/shaders/h264/mc/SetHWScoreboard.asm000066400000000000000000000230141231401140700231120ustar00rootroot00000000000000/* * Set dependency control HW scoreboard kernel * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: SetHWScoreboard.asm // // Set dependency control HW scoreboard kernel // // ---------------------------------------------------- // Main: SetHWScoreboard // ---------------------------------------------------- .kernel SetHWScoreboard SETHWSCOREBOARD: #ifdef _DEBUG // WA for FULSIM so we'll know which kernel is being debugged mov (1) acc0:ud 0xf0aa55a5:ud #endif #include "header.inc" #include "SetHWScoreboard_header.inc" // // Now, begin source code.... // .code // Separate the TotalMB so TotalMB will be multiple of 8 // and RemainderMB will hold the TotalMB%8 // and.z.f0.1 (1) RemainderMB<1>:uw TotalMB<0;1,0>:uw 0x0007:uw // number of %8 commands and.z.f0.0 (1) TotalMB<1>:uw TotalMB<0;1,0>:uw 0xfff8:uw // Number of 8-command blocks mov (1) MB_SHIFT_MASK_W<1>:uw 0x100*16+12:w // Set up shift values (12, 16) // Initialize common DAP read header // mov (8) MRF_READ_HEADER_SRC<1>:ud r0.0<8;8,1>:ud shl (1) MRF_READ_HEADER_SRC.2<1>:ud StartingMB<0;1,0>:uw 6:uw // Byte-aligned offset being read // Initialize Inter DAP write header mov (8) MRF_INTER_WRITE_HEADER<1>:ud r0.0<8;8,1>:ud (f0.0) jmpi (1) SetHWScoreboard_Remainder // Jump if TotalMB < 8 //------------------------------------------------------------------------ // Command buffer parsing loop // Each loop will handle 8 commands //------------------------------------------------------------------------ // SetHWScoreboard_Loop: // Load block 0 (Commands 0/1) mov (8) MRF_READ_HEADER0.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud send (16) CMD_BUFFER_W(0)<1> MRF_READ_HEADER0 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Load block 1 (Commands 2/3) mov (8) MRF_READ_HEADER1.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) MRF_READ_HEADER1.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 128:ud // Point to next 2-command block send (16) CMD_BUFFER_W(4)<1> MRF_READ_HEADER1 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Load block 2 (Commands 4/5) mov (8) MRF_READ_HEADER2.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) MRF_READ_HEADER2.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 256:ud // Point to next 2-command block send (16) CMD_BUFFER_W(8)<1> MRF_READ_HEADER2 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Load block 3 (Commands 6/7) mov (8) MRF_READ_HEADER3.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) MRF_READ_HEADER3.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 384:ud // Point to next 2-command block send (16) CMD_BUFFER_W(12)<1> MRF_READ_HEADER3 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Start parsing commands $for(0; <16; 2) { and.nz.f0.1 (8) NULLREG CMD_BUFFER_D(%1,4)<0;1,0> IS_INTRA_MB:ud // Is it an "Intra" MB? or (1) CMD_BUFFER_D(%1,2)<1> CMD_BUFFER_D(%1,2)<0;1,0> BIT21:ud // Set "Use Scoreboard" for every MB shl (2) CMD_BUFFER_W(%1,2)<1> CMD_BUFFER_W(%1,14)<0;1,0> MB_SHIFT_MASK_B<2;2,1>:b // Set HW SB masks mov (2) CMD_BUFFER_B(%1,4)<2> CMD_BUFFER_B(%1,20)<2;2,1> // Set scoreboard (X,Y) for intra MB (-f0.1) mov (2) CMD_BUFFER_W(%1,2)<1> CMD_BUFFER_B(%1,20)<2;2,1> // Set scoreboard (X,Y) for inter MB (f0.1) jmpi (1) Parse_8_Loop_%1 // Inter Macroblock // Output MEDIA_OBJECT command in raster scan order mul (16) acc0<1>:uw CMD_BUFFER_B(%1,21)<0;1,0> PicWidthMB<0;1,0>:uw // MB offset = Y*W add (16) acc0<1>:uw acc0<8;8,1>:uw CMD_BUFFER_B(%1,20)<0;1,0> // MB offset = Y*W+X shl (1) MRF_INTER_WRITE_HEADER.2<1>:ud acc0.2<0;1,0>:uw 6:uw // Byte-aligned MB offset mov (16) MRF_INTER_WRITE_DATA0<1>:ud CMD_BUFFER_D(%1)<8;8,1> {Compr} // Copy entire command to inter buffer mov (16) CMD_BUFFER_D(%1)<1> 0:ud {Compr} // Clear original command send (16) NULLREGW MRF_INTER_WRITE_HEADER null:uw DAPWRITE MSG_LEN(2)+OWBWMSGDSC+OWORD_4+BI_CMD_BUFFER Parse_8_Loop_%1: } add.z.f0.0 (1) TotalMB<1>:w TotalMB<0;1,0>:w -8:w // Update remaining number of 8-command blocks // Output modified intra commands // Write block 0 mov (8) MRF_INTRA_WRITE_HEADER.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud $for(0; <4; 2) { mov (16) MRF_CMD_BUF_D(%1)<1> CMD_BUFFER_D(%1)<8;8,1> {Compr} } send (16) NULLREGW MRF_INTRA_WRITE_HEADER null:uw DAPWRITE MSG_LEN(4)+OWBWMSGDSC+OWORD_8+BI_CMD_BUFFER // Write block 1 mov (8) m1.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) m1.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 128:ud // Point to next 2-command block mov (16) m2<1>:ud CMD_BUFFER_D(4)<8;8,1> {Compr} mov (16) m4<1>:ud CMD_BUFFER_D(6)<8;8,1> {Compr} send (16) NULLREGW m1 null:uw DAPWRITE MSG_LEN(4)+OWBWMSGDSC+OWORD_8+BI_CMD_BUFFER // Write block 2 add (1) MRF_INTRA_WRITE_HEADER.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 256:ud // Point to next 2-command block $for(0; <4; 2) { mov (16) MRF_CMD_BUF_D(%1)<1> CMD_BUFFER_D(%1+8)<8;8,1> {Compr} } send (16) NULLREGW MRF_INTRA_WRITE_HEADER null:uw DAPWRITE MSG_LEN(4)+OWBWMSGDSC+OWORD_8+BI_CMD_BUFFER // Write block 3 add (1) m1.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 384:ud // Point to next 2-command block mov (16) m2<1>:ud CMD_BUFFER_D(12)<8;8,1> {Compr} mov (16) m4<1>:ud CMD_BUFFER_D(14)<8;8,1> {Compr} send (16) NULLREGW m1 null:uw DAPWRITE MSG_LEN(4)+OWBWMSGDSC+OWORD_8+BI_CMD_BUFFER // Update message header for next DAP read add (1) MRF_READ_HEADER_SRC.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 512:ud // Point to next block of 8-commands cmp.z.f0.1 (1) NULLREG RemainderMB<0;1,0>:w 0:uw // Check if remainder MB = 0 (-f0.0) jmpi (1) SetHWScoreboard_Loop // Continue if more command blocks remain SetHWScoreboard_Remainder: // f0.1 should have been set to indicate if RemainderMB = 0 // (f0.1) jmpi (1) SetHWScoreboard_Done // Stop if all commands have been updated // Blindly load next 8 commands anyway // // Load block 0 (Commands 0/1) mov (8) MRF_READ_HEADER0.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud send (16) CMD_BUFFER_W(0)<1> MRF_READ_HEADER0 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Load block 1 (Commands 2/3) mov (8) MRF_READ_HEADER1.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) MRF_READ_HEADER1.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 128:ud // Point to next 2-command block send (16) CMD_BUFFER_W(4)<1> MRF_READ_HEADER1 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Load block 2 (Commands 4/5) mov (8) MRF_READ_HEADER2.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) MRF_READ_HEADER2.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 256:ud // Point to next 2-command block send (16) CMD_BUFFER_W(8)<1> MRF_READ_HEADER2 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Load block 3 (Commands 6/7) mov (8) MRF_READ_HEADER3.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) MRF_READ_HEADER3.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 384:ud // Point to next 2-command block send (16) CMD_BUFFER_W(12)<1> MRF_READ_HEADER3 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Initialize necessary pointers mov (1) a0.1<1>:ud ((CMD_BUFFER_REG_OFF+1)*0x10000+CMD_BUFFER_REG_OFF)*32 // a0.2:w points to command buffer (first half) // a0.3:w points to command buffer (second half) // Initialize Inter DAP write header mov (8) MRF_INTER_WRITE_HEADER<1>:ud r0.0<8;8,1>:ud SetHWScoreboard_Remainder_Loop: and.nz.f0.1 (8) NULLREG r[a0.2,4*4]<0;1,0>:ud IS_INTRA_MB:ud // Is it an "Intra" MB? add.z.f0.0 (1) RemainderMB<1>:w RemainderMB<0;1,0>:w -1:w // Decrement MB # or (1) r[a0.2,2*4]<1>:ud r[a0.2,2*4]<0;1,0>:ud BIT21:ud // Set "Use Scoreboard" for every MB shl (2) r[a0.2,2*2]<1>:uw r[a0.2,14*2]<0;1,0>:uw MB_SHIFT_MASK_B<2;2,1>:b // Set HW SB masks mov (2) r[a0.2,4*1]<2>:ub r[a0.2,5*4]<2;2,1>:ub // Set scoreboard (X,Y) for intra MB (-f0.1) mov (2) r[a0.2,4*1]<1>:uw r[a0.2,5*4]<2;2,1>:ub // Set scoreboard (X,Y) for inter MB (f0.1) jmpi (1) Output_Remainder_Intra // Inter Macroblock // Output MEDIA_OBJECT command in raster scan order mul (16) acc0<1>:uw r[a0.2,21]<0;1,0>:ub PicWidthMB<0;1,0>:uw // MB offset = Y*W add (16) acc0<1>:uw acc0<8;8,1>:uw r[a0.2,20]<0;1,0>:ub // MB offset = Y*W+X shl (1) MRF_INTER_WRITE_HEADER.2<1>:ud acc0.2<0;1,0>:uw 6:uw // Byte-aligned MB offset mov (16) MRF_INTER_WRITE_DATA0<1>:ud r[a0.2]<8;8,1>:ud {Compr} // Copy entire command to inter buffer mov (16) r[a0.2]<1>:ud 0:ud {Compr} // Clear original command send (16) NULLREGW MRF_INTER_WRITE_HEADER null:uw DAPWRITE MSG_LEN(2)+OWBWMSGDSC+OWORD_4+BI_CMD_BUFFER Output_Remainder_Intra: // Intra MB command always output mov (8) MRF_INTRA_WRITE_HEADER.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud mov (16) MRF_CMD_BUF_D(0)<1> r[a0.2]<8;8,1>:ud {Compr} // Copy entire command to intra buffer send (16) NULLREGW MRF_INTRA_WRITE_HEADER null:uw DAPWRITE MSG_LEN(2)+OWBWMSGDSC+OWORD_4+BI_CMD_BUFFER add (1) MRF_READ_HEADER_SRC.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 64:ud // Point to next command add (1) a0.1<1>:ud a0.1<0;1,0>:ud 0x00400040:ud // Update pointers (-f0.0) jmpi (1) SetHWScoreboard_Remainder_Loop // All MBs have been decoded. Terminate the thread now // SetHWScoreboard_Done: END_THREAD #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif // End of SetHWScoreboard intel-driver-1.3.0/src/shaders/h264/mc/SetHWScoreboard_MBAFF.asm000066400000000000000000000322761231401140700240170ustar00rootroot00000000000000/* * Set dependency control HW scoreboard kernel for MBAFF picture * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: SetHWScoreboard_MBAFF.asm // // Set dependency control HW scoreboard kernel for MBAFF picture // // ---------------------------------------------------- // Main: SetHWScoreboard_MBAFF // ---------------------------------------------------- .kernel SetHWScoreboard_MBAFF SETHWSCOREBOARD_MBAFF: #ifdef _DEBUG // WA for FULSIM so we'll know which kernel is being debugged mov (1) acc0:ud 0xf1aa55a5:ud #endif #include "header.inc" #include "SetHWScoreboard_header.inc" // // Now, begin source code.... // .code // Separate the TotalMB so TotalMB will be multiple of 8 // and RemainderMB will hold the TotalMB%8 // and.z.f0.1 (1) RemainderMB<1>:uw TotalMB<0;1,0>:uw 0x0007:uw // number of %8 commands and.z.f0.0 (1) TotalMB<1>:uw TotalMB<0;1,0>:uw 0xfff8:uw // Number of 8-command blocks // Initialize common DAP read header // mov (8) MRF_READ_HEADER_SRC<1>:ud r0.0<8;8,1>:ud shl (1) MRF_READ_HEADER_SRC.2<1>:ud StartingMB<0;1,0>:uw 6:uw // Byte-aligned offset being read // Initialize Inter DAP write header mov (8) MRF_INTER_WRITE_HEADER<1>:ud r0.0<8;8,1>:ud (f0.0) jmpi (1) SetHWScoreboard_MBAFF_Remainder // Jump if TatalMB < 8 //------------------------------------------------------------------------ // Command buffer parsing loop // Each loop will handle 8 commands //------------------------------------------------------------------------ // SetHWScoreboard_MBAFF_Loop: // Load block 0 (Commands 0/1) mov (8) MRF_READ_HEADER0.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud send (16) CMD_BUFFER_W(0)<1> MRF_READ_HEADER0 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Load block 1 (Commands 2/3) mov (8) MRF_READ_HEADER1.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) MRF_READ_HEADER1.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 128:ud // Point to next 2-command block send (16) CMD_BUFFER_W(4)<1> MRF_READ_HEADER1 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Load block 2 (Commands 4/5) mov (8) MRF_READ_HEADER2.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) MRF_READ_HEADER2.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 256:ud // Point to next 2-command block send (16) CMD_BUFFER_W(8)<1> MRF_READ_HEADER2 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Load block 3 (Commands 6/7) mov (8) MRF_READ_HEADER3.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) MRF_READ_HEADER3.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 384:ud // Point to next 2-command block send (16) CMD_BUFFER_W(12)<1> MRF_READ_HEADER3 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Start parsing commands $for(0; <16; 2) { // Adjust MB Y origin for field MBs // mov (2) TEMP_FD_X_W<1>:uw CMD_BUFFER_B(%1,20)<2;2,1> // Initialize temp (X,Y) location and.nz.f0.1 (8) NULLREG CMD_BUFFER_D(%1,4)<0;1,0> IS_BOT_FD:ud // Is it a "Bottom Field MB"? and.nz.f0.0 (8) NULLREG CMD_BUFFER_D(%1,4)<0;1,0> IS_FIELD_MB:ud // Is it a "Field MB"? mul (8) acc0<1>:w CMD_BUFFER_B(%1,21)<0;1,0> 2:w (-f0.1) mov (1) TEMP_FD_Y_W<1>:w acc0<0;1,0>:w (f0.1) add (1) TEMP_FD_Y_W<1>:w acc0<0;1,0>:w 1:w (-f0.0) mov (1) TEMP_FD_Y_W<1>:w CMD_BUFFER_B(%1,21)<0;1,0> // Discard field MB Y origin handling and.nz.f0.0 (8) NULLREG CMD_BUFFER_D(%1,4)<0;1,0> IS_INTRA_MB:ud // Is it an "Intra" MB? and.nz.f0.1 (8) NULLREG TEMP_FD_Y_W<0;1,0>:uw BIT0 // Is it "Bottom MB"? or (1) CMD_BUFFER_D(%1,2)<1> CMD_BUFFER_D(%1,2)<0;1,0> BIT21 // Set "Use Scoreboard" mov (2) CMD_BUFFER_W(%1,2)<1> TEMP_FD_X_W<2;2,1>:uw // Set scoreboard (X,Y) for inter MB (f0.0) jmpi (1) SET_SB_MBAFF_INTRA_%1 // Jump if intra MB. // Inter Macroblock // Output MEDIA_OBJECT command in raster scan order mul (16) acc0<1>:uw TEMP_FD_Y_W<0;1,0>:uw PicWidthMB<0;1,0>:uw // MB offset = Y*W add (16) acc0<1>:uw acc0<8;8,1>:uw TEMP_FD_X_W<0;1,0>:uw // MB offset = Y*W+X shl (1) MRF_INTER_WRITE_HEADER.2<1>:ud acc0.2<0;1,0>:uw 6:uw // Byte-aligned MB offset mov (16) MRF_INTER_WRITE_DATA0<1>:ud CMD_BUFFER_D(%1)<8;8,1> {Compr} // Copy entire command to inter buffer mov (16) CMD_BUFFER_D(%1)<1> 0:ud {Compr} // Clear original command send (16) NULLREGW MRF_INTER_WRITE_HEADER null:uw DAPWRITE MSG_LEN(2)+OWBWMSGDSC+OWORD_4+BI_CMD_BUFFER jmpi (1) NEXT_MB_MBAFF_%1 // Done for inter MB. Move to next MB. SET_SB_MBAFF_INTRA_%1: // Intra MB // and.nz.f0.0 (8) NULLREG CMD_BUFFER_D(%1,4)<0;1,0> IS_FIELD_MB:ud // Is it an "Field" MB? (f0.1) sel (2) MB_MASK_D<1>:ud BOT_FD_MASK1_D<2;2,1>:ud TOP_FD_MASK1_D<2;2,1>:ud // Assume field MB mov (1) TEMP_INTRA_FLAG_W<1>:uw CMD_BUFFER_W(%1,14)<0;1,0> // Don't want to alter original in-line data (f0.0) jmpi (1) SET_SB_MBAFF_%1 // Jump if it's really field MB // Frame MB // // Derive E' and.nz.f0.0 (8) NULLREG CMD_BUFFER_W(%1,14)<0;1,0> E_FLAG // Is "E" = 1 (f0.1) sel (2) MB_MASK_D<1>:ud BOT_FM_MASK1_D<2;2,1>:ud TOP_FM_MASK1_D<2;2,1>:ud and.z.f0.1 (8) NULLREG CMD_BUFFER_W(%1,14)<0;1,0> A_FLAG // "A" = 0? (f0.0) jmpi (1) SET_SB_MBAFF_%1 // If "E" flag = 1, skip the rest of derivation (f0.1) and.nz.f0.1 (8) NULLREG CMD_BUFFER_D(%1,4)<0;1,0> IS_INTRA8X8 (f0.1) and.nz.f0.1 (8) NULLREG CMD_BUFFER_W(%1,14)<0;1,0> F_FLAG (f0.1) or (1) TEMP_INTRA_FLAG_W<1>:uw CMD_BUFFER_W(%1,14)<0;1,0> E_FLAG SET_SB_MBAFF_%1: and.nz.f0.1 (16) NULLREGW TEMP_INTRA_FLAG_W<0;1,0>:uw MB_MASK_B<0;8,1>:ub shl (1) CMD_BUFFER_W(%1,2)<1> f0.1<0;1,0>:uw 12:w // Masks 0-3 and (1) CMD_BUFFER_W(%1,3)<1> f0.1<0;1,0>:uw 0xf000:uw // Masks 4-7 mov (2) CMD_BUFFER_B(%1,4)<2> TEMP_FD_X_B<4;2,2>:ub // Set scoreboard (X,Y) for intra MB NEXT_MB_MBAFF_%1: } add.z.f0.0 (1) TotalMB<1>:w TotalMB<0;1,0>:w -8:w // Update remaining number of 8-command blocks // Output modified intra commands // Write block 0 mov (8) MRF_INTRA_WRITE_HEADER.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud $for(0; <4; 2) { mov (16) MRF_CMD_BUF_D(%1)<1> CMD_BUFFER_D(%1)<8;8,1> {Compr} } send (16) NULLREGW MRF_INTRA_WRITE_HEADER null:uw DAPWRITE MSG_LEN(4)+OWBWMSGDSC+OWORD_8+BI_CMD_BUFFER // Write block 1 mov (8) m1.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) m1.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 128:ud // Point to next 2-command block mov (16) m2<1>:ud CMD_BUFFER_D(4)<8;8,1> {Compr} mov (16) m4<1>:ud CMD_BUFFER_D(6)<8;8,1> {Compr} send (16) NULLREGW m1 null:uw DAPWRITE MSG_LEN(4)+OWBWMSGDSC+OWORD_8+BI_CMD_BUFFER // Write block 2 add (1) MRF_INTRA_WRITE_HEADER.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 256:ud // Point to next 2-command block $for(0; <4; 2) { mov (16) MRF_CMD_BUF_D(%1)<1> CMD_BUFFER_D(%1+8)<8;8,1> {Compr} } send (16) NULLREGW MRF_INTRA_WRITE_HEADER null:uw DAPWRITE MSG_LEN(4)+OWBWMSGDSC+OWORD_8+BI_CMD_BUFFER // Write block 3 add (1) m1.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 384:ud // Point to next 2-command block mov (16) m2<1>:ud CMD_BUFFER_D(12)<8;8,1> {Compr} mov (16) m4<1>:ud CMD_BUFFER_D(14)<8;8,1> {Compr} send (16) NULLREGW m1 null:uw DAPWRITE MSG_LEN(4)+OWBWMSGDSC+OWORD_8+BI_CMD_BUFFER // Update message header for next DAP read add (1) MRF_READ_HEADER_SRC.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 512:ud // Point to next block of 8-commands cmp.z.f0.1 (1) NULLREG RemainderMB<0;1,0>:w 0:uw // Check if remaining MB = 0 (-f0.0) jmpi (1) SetHWScoreboard_MBAFF_Loop // Continue if more command blocks remain SetHWScoreboard_MBAFF_Remainder: // f0.1 should have been set to indicate if RemainderMB = 0 // (f0.1) jmpi (1) SetHWScoreboard_MBAFF_Done // Stop if all commands have been updated // Blindly load next 8 commands anyway // // Load block 0 (Commands 0/1) mov (8) MRF_READ_HEADER0.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud send (16) CMD_BUFFER_W(0)<1> MRF_READ_HEADER0 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Load block 1 (Commands 2/3) mov (8) MRF_READ_HEADER1.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) MRF_READ_HEADER1.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 128:ud // Point to next 2-command block send (16) CMD_BUFFER_W(4)<1> MRF_READ_HEADER1 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Load block 2 (Commands 4/5) mov (8) MRF_READ_HEADER2.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) MRF_READ_HEADER2.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 256:ud // Point to next 2-command block send (16) CMD_BUFFER_W(8)<1> MRF_READ_HEADER2 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Load block 3 (Commands 6/7) mov (8) MRF_READ_HEADER3.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud add (1) MRF_READ_HEADER3.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 384:ud // Point to next 2-command block send (16) CMD_BUFFER_W(12)<1> MRF_READ_HEADER3 null:uw DAPREAD RESP_LEN(4)+OWBRMSGDSC_SC+OWORD_8+BI_CMD_BUFFER // Initialize necessary pointers mov (1) a0.1<1>:ud ((CMD_BUFFER_REG_OFF+1)*0x10000+CMD_BUFFER_REG_OFF)*32 // a0.2:w points to command buffer (first half) // a0.3:w points to command buffer (second half) // Initialize Inter DAP write header mov (8) MRF_INTER_WRITE_HEADER<1>:ud r0.0<8;8,1>:ud SetHWScoreboard_MBAFF_Remainder_Loop: // Adjust MB Y origin for field MBs // mov (2) TEMP_FD_X_W<1>:uw r[a0.2,5*4]<2;2,1>:ub // Initialize temp (X,Y) location and.nz.f0.1 (8) NULLREG r[a0.2,4*4]<0;1,0>:ud IS_BOT_FD:ud // Is it a "Bottom Field MB"? and.nz.f0.0 (8) NULLREG r[a0.2,4*4]<0;1,0>:ud IS_FIELD_MB:ud // Is it a "Field MB"? mul (8) acc0<1>:w r[a0.2,21]<0;1,0>:ub 2:w (-f0.1) mov (1) TEMP_FD_Y_W<1>:w acc0<0;1,0>:w (f0.1) add (1) TEMP_FD_Y_W<1>:w acc0<0;1,0>:w 1:w (-f0.0) mov (1) TEMP_FD_Y_W<1>:w r[a0.2,5*4+1]<0;1,0>:ub // Discard field MB Y origin handling and.nz.f0.0 (8) NULLREG r[a0.2,4*4]<0;1,0>:ud IS_INTRA_MB:ud // Is it an "Intra" MB? add.z.f0.1 (1) RemainderMB<1>:w RemainderMB<0;1,0>:w -1:w // Decrement MB # or (1) r[a0.2,2*4]<1>:ud r[a0.2,2*4]<0;1,0>:ud BIT21:ud // Set "Use Scoreboard" mov (2) r[a0.2,2*2]<1>:uw TEMP_FD_X_W<2;2,1>:uw // Set scoreboard (X,Y) for inter MB (f0.0) jmpi (1) SET_SB_MBAFF_REM_INTRA // Jump if intra MB. // Inter Macroblock // Output MEDIA_OBJECT command in raster scan order mul (16) acc0<1>:uw TEMP_FD_Y_W<0;1,0>:uw PicWidthMB<0;1,0>:uw // MB offset = Y*W add (16) acc0<1>:uw acc0<8;8,1>:uw TEMP_FD_X_W<0;1,0>:uw // MB offset = Y*W+X shl (1) MRF_INTER_WRITE_HEADER.2<1>:ud acc0.2<0;1,0>:uw 6:uw // Byte-aligned MB offset mov (16) MRF_INTER_WRITE_DATA0<1>:ud r[a0.2]<8;8,1>:ud {Compr} // Copy entire command to inter buffer mov (16) r[a0.2]<1>:ud 0:ud {Compr} // Clear original command send (16) NULLREGW MRF_INTER_WRITE_HEADER null:uw DAPWRITE MSG_LEN(2)+OWBWMSGDSC+OWORD_4+BI_CMD_BUFFER jmpi (1) Output_MBAFF_Remainder_Intra // Done for inter MB. Move to dump intra MB. SET_SB_MBAFF_REM_INTRA: // Intra MB // and.nz.f0.1 (8) NULLREG TEMP_FD_Y_W<0;1,0>:uw BIT0:ud // Is it "Bottom MB"? and.nz.f0.0 (8) NULLREG r[a0.2,4*4]<0;1,0>:ud IS_FIELD_MB:ud // Is it "Field MB"? mov (1) TEMP_INTRA_FLAG_W<1>:uw r[a0.2,14*2]<0;1,0>:uw // Don't want to alter original in-line data (f0.1) sel (2) MB_MASK_D<1>:ud BOT_FD_MASK1_D<2;2,1>:ud TOP_FD_MASK1_D<2;2,1>:ud // Assume field MB (f0.0) jmpi (1) SET_SB_MBAFF_REM // Jump if it's really field MB // Frame MB // // Derive E' and.nz.f0.0 (8) NULLREG r[a0.2,14*2]<0;1,0>:uw E_FLAG // Is "E" = 1 (f0.1) sel (2) MB_MASK_D<1>:ud BOT_FM_MASK1_D<2;2,1>:ud TOP_FM_MASK1_D<2;2,1>:ud and.z.f0.1 (8) NULLREG r[a0.2,14*2]<0;1,0>:uw A_FLAG // "A" = 0? (f0.0) jmpi (1) SET_SB_MBAFF_REM // If "E" flag = 1, skip the rest of derivation (f0.1) and.nz.f0.1 (8) NULLREG r[a0.2,4*4]<0;1,0>:ud IS_INTRA8X8 (f0.1) and.nz.f0.1 (8) NULLREG r[a0.2,14*2]<0;1,0>:uw F_FLAG (f0.1) or (1) TEMP_INTRA_FLAG_W<1>:uw r[a0.2,14*2]<0;1,0>:uw E_FLAG SET_SB_MBAFF_REM: and.nz.f0.0 (16) NULLREGW TEMP_INTRA_FLAG_W<0;1,0>:uw MB_MASK_B<0;8,1>:ub add.z.f0.1 (1) RemainderMB<1>:w RemainderMB<0;1,0>:w 0:w // Check remaining MB # shl (1) r[a0.2,2*2]<1>:uw f0.0<0;1,0>:uw 12:w // Masks 0-3 and (1) r[a0.2,3*2]<1>:uw f0.0<0;1,0>:uw 0xf000:uw // Masks 4-7 mov (2) r[a0.2,4*1]<2>:ub TEMP_FD_X_B<4;2,2>:ub // Set scoreboard (X,Y) for intra MB Output_MBAFF_Remainder_Intra: // Intra MB command always output mov (8) MRF_INTRA_WRITE_HEADER.0<1>:ud MRF_READ_HEADER_SRC.0<8;8,1>:ud mov (16) MRF_CMD_BUF_D(0)<1> r[a0.2]<8;8,1>:ud {Compr} // Copy entire command to intra buffer send (16) NULLREGW MRF_INTRA_WRITE_HEADER null:uw DAPWRITE MSG_LEN(2)+OWBWMSGDSC+OWORD_4+BI_CMD_BUFFER add (1) MRF_READ_HEADER_SRC.2<1>:ud MRF_READ_HEADER_SRC.2<0;1,0>:ud 64:ud // Point to next command add (1) a0.1<1>:ud a0.1<0;1,0>:ud 0x00400040:ud // Update pointers (-f0.1) jmpi (1) SetHWScoreboard_MBAFF_Remainder_Loop // All MBs have been decoded. Terminate the thread now // SetHWScoreboard_MBAFF_Done: END_THREAD #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif // End of SetHWScoreboard_MBAFF intel-driver-1.3.0/src/shaders/h264/mc/SetHWScoreboard_header.inc000066400000000000000000000124531231401140700244200ustar00rootroot00000000000000/* * Common header file for both SetHWScoreboard and SetHWScoreboard_MBAFF kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__SETHWSCOREBOARD_HEADER__) // Make sure this file is only included once #define __SETHWSCOREBOARD_HEADER__ // Module name: SetHWScoreboard_header.inc // // Common header file for both SetHWScoreboard and SetHWScoreboard_MBAFF kernels // #define BI_CMD_BUF 0 // Binding table index for command buffer // GRF r1 map // // For use by setting HW scoreboard kernel for MBAFF picture // // CURBE data #define TOP_FM_MASK1_D r1.0 // Bit mask for first half of top frame MB SB mask #define TOP_FM_MASK1_B r1.0 // Bit mask for first half of top frame MB SB mask #define TOP_FM_MASK2_D r1.1 // Bit mask for second half of top frame MB SB mask #define TOP_FM_MASK2_B r1.4 // Bit mask for second half of top frame MB SB mask #define BOT_FM_MASK1_D r1.2 // Bit mask for first half of bottom frame MB SB mask #define BOT_FM_MASK1_B r1.8 // Bit mask for first half of bottom frame MB SB mask #define BOT_FM_MASK2_D r1.3 // Bit mask for second half of bottom frame MB SB mask #define BOT_FM_MASK2_B r1.12 // Bit mask for second half of bottom frame MB SB mask #define TOP_FD_MASK1_D r1.4 // Bit mask for first half of top field MB SB mask #define TOP_FD_MASK1_B r1.16 // Bit mask for first half of top field MB SB mask #define TOP_FD_MASK2_D r1.5 // Bit mask for second half of top field MB SB mask #define TOP_FD_MASK2_B r1.20 // Bit mask for second half of top field MB SB mask #define BOT_FD_MASK1_D r1.6 // Bit mask for first half of bottom field MB SB mask #define BOT_FD_MASK1_B r1.24 // Bit mask for first half of bottom field MB SB mask #define BOT_FD_MASK2_D r1.7 // Bit mask for second half of bottom field MB SB mask #define BOT_FD_MASK2_B r1.28 // Bit mask for second half of bottom field MB SB mask // For use by setting HW scoreboard kernel for non-MBAFF picture #define MB_SHIFT_MASK_W r1.0 // :w type. Shift values for two parts of the MB SB mask #define MB_SHIFT_MASK_B r1.0 // :b type. Shift values for two parts of the MB SB mask // GRF r2 map // // In-line data // #define INLINE_REG_OFFSET 1 #define INLINE_REG r2 #define StartingMB INLINE_REG.0 // :uw type. Starting MB number #define TotalMB INLINE_REG.1 // :uw type. Total number of MB to be processed #define PicWidthMB INLINE_REG.2 // :uw type. Picture width in MB // GRF r3 map // // Temporary variables // #define RemainderMB r3.0 // :uw type. Remainder of MB (<16) to be processed #define TEMP_FD_X_W r3.2 // :w type. Temporary variable for field MB X origin in MBAFF picture #define TEMP_FD_X_B r3.4 // :b type. Temporary variable for field MB X origin in MBAFF picture #define TEMP_FD_Y_W r3.3 // :w type. Temporary variable for field MB Y origin in MBAFF picture #define TEMP_FD_Y_B r3.6 // :b type. Temporary variable for field MB Y origin in MBAFF picture #define TEMP_INTRA_FLAG_W r3.4 // :uw type. Temporary intra available flag #define MB_MASK_D r3.4 // :ud type. Bit masks for MBAFF MB #define MB_MASK_B r3.16 // :ub type. Bit masks for MBAFF MB #define MRF_READ_HEADER_SRC r63 // MEDIA_OBJECT_EX Command map // // In DW1 of each MEDIA_OBJECT_EX command (VFE DWORD) #define CUR_X 0 // Byte 0 #define CUR_Y 0 // Byte 2 // In DW2 of each MEDIA_OBJECT_EX command #define USE_SCOREBOARD BIT21 // In DW4 of each MEDIA_OBJECT_EX command #define F_FLAG BIT4 #define IS_INTRA_MB BIT13 #define IS_FIELD_MB BIT14 #define IS_INTRA8X8 BIT15 #define IS_BOT_FD BIT24 // In DW7 of each MEDIA_OBJECT_EX command #define A_FLAG BIT0 #define B_FLAG BIT1 #define C_FLAG BIT2 #define D_FLAG BIT3 #define E_FLAG BIT4 #define CMD_BUFFER_REG_OFF 4 .declare CMD_BUFFER_D Base=GRF(4) ElementSize=4 SrcRegion=REGION(8,1) Type=ud // Command buffer (32 GRF) .declare CMD_BUFFER_W Base=GRF(4) ElementSize=2 SrcRegion=REGION(16,1) Type=uw // Command buffer (32 GRF) .declare CMD_BUFFER_B Base=GRF(4) ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Command buffer (32 GRF) #define MRF_READ_HEADER m1 #define MRF_READ_HEADER0 m1 #define MRF_READ_HEADER1 m2 #define MRF_READ_HEADER2 m3 #define MRF_READ_HEADER3 m4 #define MRF_INTER_WRITE_HEADER m5 #define MRF_INTER_WRITE_DATA0 m6 #define MRF_INTER_WRITE_DATA1 m7 #define MRF_WRITE_HEADER m11 #define MRF_INTRA_WRITE_HEADER m11 #define MRF_CMD_BUF_REG_OFF 12 .declare MRF_CMD_BUF_D Base=m12 ElementSize=4 SrcRegion=REGION(8,1) Type=ud // Command buffer stored in MRF .declare MRF_CMD_BUF_W Base=m12 ElementSize=2 SrcRegion=REGION(16,1) Type=uw // Command buffer stored in MRF .declare MRF_CMD_BUF_B Base=m12 ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Command buffer stored in MRF #define BI_CMD_BUFFER 0 #define OWBRMSGDSC_SC 0x02088000 // OWORD Block Read Message Descriptor, reading from sampler cache = A. #define OWBWMSGDSC 0x02080000 // OWORD Block Write Message Descriptor #define OWORD_1 0x000 #define OWORD_2 0x200 #define OWORD_4 0x300 #define OWORD_8 0x400 // End of SETHWSCOREBOARD_HEADER #endif // !defined(__SETHWSCOREBOARD_HEADER__) intel-driver-1.3.0/src/shaders/h264/mc/SetupForHWMC.asm000066400000000000000000000016531231401140700223470ustar00rootroot00000000000000/* * Initial setup for running HWMC kernels in HWMC-Only decoding mode * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: SetupForHWMC.asm // // Initial setup for running HWMC kernels in HWMC-Only decoding mode // #include "header.inc" #include "intra_Header.inc" #if !defined(__SETUPFORHWMC__) // Make sure the following are only included once #define __SETUPFORHWMC__ .reg_count_total 64 .reg_count_payload 2 // // Now, begin source code.... // .code #endif // !defined(__SETUPFORHWMC__) mov (8) MSGSRC<1>:ud r0.0<8;8,1>:ud // Initialize message header payload with R0 shl (2) I_ORIX<1>:uw ORIX<2;2,1>:ub 4:w // Convert MB origin to pixel unit // End of SetupForHWMC intel-driver-1.3.0/src/shaders/h264/mc/add_Error_16x16_Y.asm000066400000000000000000000027601231401140700231570ustar00rootroot00000000000000/* * Add macroblock correction Y data blocks to predicted picture * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: add_Error_16x16_Y.asm // // Add macroblock correction Y data blocks to predicted picture // // Every line of predicted Y data is added to Y error data if CBP bit is set mov (1) PERROR_UD<1>:ud 0x10001*ERRBUF*GRFWIB+0x00100000:ud // Pointers to first and second row of error block and.z.f0.1 (1) NULLREG REG_CBPCY CBP_Y_MASK (f0.1) jmpi (1) End_add_Error_16x16_Y // Skip all blocks // Block Y0 // $for(0,0; <8; 2,1) { add.sat (16) DEC_Y(%1)<2> r[PERROR,%2*GRFWIB]REGION(8,1):w PRED_Y(%1)REGION(8,2) {Compr} } // Block Y1 // $for(0,0; <8; 2,1) { add.sat (16) DEC_Y(%1,16)<2> r[PERROR,%2*GRFWIB+0x80]REGION(8,1):w PRED_Y(%1,16)REGION(8,2) {Compr} } // Block Y2 // $for(8,0; <16; 2,1) { add.sat (16) DEC_Y(%1)<2> r[PERROR,%2*GRFWIB+0x100]REGION(8,1):w PRED_Y(%1)REGION(8,2) {Compr} } // Block Y3 // $for(8,0; <16; 2,1) { add.sat (16) DEC_Y(%1,16)<2> r[PERROR,%2*GRFWIB+0x180]REGION(8,1):w PRED_Y(%1,16)REGION(8,2) {Compr} } End_add_Error_16x16_Y: add (1) PERROR_UD<1>:ud PERROR_UD:ud 0x01800180:ud // Pointers to Y3 error block // End of add_Error_16x16_Y intel-driver-1.3.0/src/shaders/h264/mc/add_Error_UV.asm000066400000000000000000000021521231401140700224270ustar00rootroot00000000000000/* * Add macroblock correction UV data blocks to predicted picture * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__ADD_ERROR_UV__) // Make sure this is only included once #define __ADD_ERROR_UV__ // Module name: add_Error_UV.asm // // Add macroblock correction UV data blocks to predicted picture // PERROR points to error block Y3 after decoding Y component // Update address register used in instruction compression // // U component // add (1) PERROR1<1>:w PERROR:w 0x00010:w // Pointers to next error row $for(0,0; <8; 2,1) { add.sat (16) DEC_UV(%1)<4> r[PERROR,%2*GRFWIB+0x80]REGION(8,1):w PRED_UV(%1)REGION(8,4) {Compr} } // V component // $for(0,0; <8; 2,1) { add.sat (16) DEC_UV(%1,2)<4> r[PERROR,%2*GRFWIB+0x100]REGION(8,1):w PRED_UV(%1,2)REGION(8,4) {Compr} } // End of add_Error_UV #endif // !defined(__ADD_ERROR_UV__) intel-driver-1.3.0/src/shaders/h264/mc/avc_mc.g4b000066400000000000000000010640451231401140700212520ustar00rootroot00000000000000 { 0x00600001, 0x27c00021, 0x008d0000, 0x00000000 }, { 0x00200009, 0x27fa3e29, 0x00450064, 0x00040004 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000d4 }, { 0x00000005, 0x220e3e2c, 0x00000070, 0x000f000f }, { 0x00000001, 0x26a00221, 0x00009c38, 0x00000000 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006a0 }, { 0x00a02001, 0x24000229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x24400229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x24800229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x24c00229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x25000229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x25400229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x25800229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x25c00229, 0x00b10624, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000001, 0x22080060, 0x00000000, 0x06440640 }, { 0x00a02001, 0x24000229, 0x00009003, 0x00000000 }, { 0x00a02001, 0x24400229, 0x0000900b, 0x00000000 }, { 0x00a02001, 0x24800229, 0x00009013, 0x00000000 }, { 0x00a02001, 0x24c00229, 0x0000901b, 0x00000000 }, { 0x00a02001, 0x25000229, 0x00009023, 0x00000000 }, { 0x00a02001, 0x25400229, 0x0000902b, 0x00000000 }, { 0x00a02001, 0x25800229, 0x00009033, 0x00000000 }, { 0x00a02001, 0x25c00229, 0x0000903b, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000072 }, { 0x02600005, 0x20000c20, 0x0000006c, 0x00000002 }, { 0x00600005, 0x24000c20, 0x0000006c, 0x00000011 }, { 0x01600007, 0x20000c00, 0x028d0400, 0x00000011 }, { 0x00780001, 0x26240169, 0x00000000, 0x80808080 }, { 0x00780001, 0x66430231, 0x028d0624, 0x00000000 }, { 0x00780001, 0x66630231, 0x028d062c, 0x00000000 }, { 0x00780001, 0x26240231, 0x00cf0643, 0x00000000 }, { 0x00780001, 0x262c0231, 0x00cf0663, 0x00000000 }, { 0x00800040, 0x25e04629, 0x00cf0643, 0x00b10624 }, { 0x00600040, 0x25e02529, 0x008d05e0, 0x008d05f0 }, { 0x00400040, 0x25e02529, 0x006905e0, 0x006905e8 }, { 0x00200040, 0x25e02529, 0x004505e0, 0x004505e4 }, { 0x00a02040, 0x2400252c, 0x000005e0, 0x000005e2 }, { 0x00a02040, 0x24003d8c, 0x00b10400, 0x00100010 }, { 0x00a02008, 0x24003d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x24403d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x24803d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x24c03d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x25003d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x25403d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x25803d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x25c03d89, 0x00b10400, 0x00050005 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000044 }, { 0x00600041, 0x26806e2d, 0x008d062c, 0x89abcdef }, { 0x00600041, 0x26906e2d, 0x008d0623, 0xfedcba98 }, { 0x00600041, 0x26a06e2d, 0x00cf0663, 0x89abcdef }, { 0x00600041, 0x26b06e2d, 0x00cf0643, 0x0fedcba9 }, { 0x00000041, 0x26be3e2d, 0x00000623, 0xfff8fff8 }, { 0x00802040, 0x268035ad, 0x008d4680, 0x008d0690 }, { 0x00802040, 0x268035ad, 0x008d0680, 0x008d0688 }, { 0x00802040, 0x268035ad, 0x008d0680, 0x008d0684 }, { 0x00802040, 0x268035ad, 0x008d0680, 0x008d0682 }, { 0x00800001, 0x240001ec, 0x00000000, 0x00200020 }, { 0x00200048, 0x24003dac, 0x00a00680, 0x00050005 }, { 0x00200008, 0x26e03d8d, 0x00450400, 0x00060006 }, { 0x00800001, 0x240001ec, 0x00000000, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x00000633, 0x00100010 }, { 0x00800048, 0x26c03e2d, 0x0000067f, 0x00100010 }, { 0x00800048, 0x272055ad, 0x000006e0, 0x00b10040 }, { 0x00600041, 0x268055ad, 0x000006e2, 0x00ae0040 }, { 0x00600041, 0x26a055ad, 0x000006e2, 0x00ae0041 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b00680 }, { 0x80a02008, 0x44003d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b00682 }, { 0x80a02008, 0x44403d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b00684 }, { 0x80a02008, 0x44803d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b00686 }, { 0x80a02008, 0x44c03d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b00688 }, { 0x80a02008, 0x45003d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b0068a }, { 0x80a02008, 0x45403d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b0068c }, { 0x80a02008, 0x45803d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b0068e }, { 0x80a02008, 0x45c03d91, 0x00b10400, 0x00050005 }, { 0x00000001, 0x22040060, 0x00000000, 0x00900080 }, { 0x01000005, 0x20000c20, 0x02000068, 0x00003c00 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000020 }, { 0x80802040, 0x440045b1, 0x008d8800, 0x00ae0400 }, { 0x80802040, 0x444045b1, 0x008d8820, 0x00ae0440 }, { 0x80802040, 0x448045b1, 0x008d8840, 0x00ae0480 }, { 0x80802040, 0x44c045b1, 0x008d8860, 0x00ae04c0 }, { 0x80802040, 0x441045b1, 0x008d8880, 0x00ae0410 }, { 0x80802040, 0x445045b1, 0x008d88a0, 0x00ae0450 }, { 0x80802040, 0x449045b1, 0x008d88c0, 0x00ae0490 }, { 0x80802040, 0x44d045b1, 0x008d88e0, 0x00ae04d0 }, { 0x80802040, 0x450045b1, 0x008d8900, 0x00ae0500 }, { 0x80802040, 0x454045b1, 0x008d8920, 0x00ae0540 }, { 0x80802040, 0x458045b1, 0x008d8940, 0x00ae0580 }, { 0x80802040, 0x45c045b1, 0x008d8960, 0x00ae05c0 }, { 0x80802040, 0x451045b1, 0x008d8980, 0x00ae0510 }, { 0x80802040, 0x455045b1, 0x008d89a0, 0x00ae0550 }, { 0x80802040, 0x459045b1, 0x008d89c0, 0x00ae0590 }, { 0x80802040, 0x45d045b1, 0x008d89e0, 0x00ae05d0 }, { 0x00000040, 0x22040c00, 0x00000204, 0x01800180 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000e2 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x27800021, 0x00000780, 0x00000000 }, { 0x00000001, 0x27a00021, 0x000007a0, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00200440, 0x27c055a5, 0x004507fa, 0x0045002a }, { 0x00000801, 0x27c80061, 0x00000000, 0x0000001b }, { 0x00000040, 0x22000d20, 0x00000062, 0x02186000 }, { 0x01600031, 0x26200021, 0x408d07c0, 0x00000200 }, { 0x00000440, 0x27c43ca5, 0x000007c4, 0x00010001 }, { 0x00000801, 0x27c80061, 0x00000000, 0x000f0003 }, { 0x00000040, 0x22000c00, 0x00000200, 0x00100000 }, { 0x02600031, 0x26400021, 0x408d07c0, 0x00000200 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00000008, 0x27fc3dad, 0x000007fc, 0x00010001 }, { 0x00200440, 0x27c055a5, 0x004507fa, 0x0045002a }, { 0x00000801, 0x27c80061, 0x00000000, 0x00000013 }, { 0x00000040, 0x22000c00, 0x00000200, 0xefffc001 }, { 0x01600031, 0x26200021, 0x408d07c0, 0x00000200 }, { 0x00000440, 0x27c43ca5, 0x000007c4, 0x00010001 }, { 0x00000801, 0x27c80061, 0x00000000, 0x00070003 }, { 0x05600031, 0x26400021, 0x408d07c0, 0x00000200 }, { 0x00000008, 0x220e3e2c, 0x0000006c, 0x00060006 }, { 0x00000001, 0x26a002a5, 0x00009c3c, 0x00000000 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006a0 }, { 0x02600005, 0x20000c20, 0x0000006c, 0x00000002 }, { 0x00780001, 0x26240169, 0x00000000, 0x80808080 }, { 0x02400005, 0x20000c20, 0x0200006c, 0x00000001 }, { 0x00560001, 0x46420129, 0x02690624, 0x00000000 }, { 0x02400005, 0x20000c20, 0x0200006c, 0x00000010 }, { 0x00560001, 0x46520129, 0x0269062c, 0x00000000 }, { 0x00780001, 0x26240129, 0x00ae0642, 0x00000000 }, { 0x00800040, 0x24004629, 0x00b10624, 0x00650642 }, { 0x00600040, 0x24002529, 0x00650400, 0x00650404 }, { 0x00600040, 0x25202529, 0x00050400, 0x00050404 }, { 0x00600040, 0x25702529, 0x00050408, 0x0005040c }, { 0x00560001, 0x26240169, 0x00000000, 0x80808080 }, { 0x00460001, 0x26240129, 0x028a0652, 0x00000000 }, { 0x00560001, 0x46520129, 0x02690624, 0x00000000 }, { 0x02400005, 0x20000c20, 0x0200006c, 0x00000001 }, { 0x00560001, 0x46420169, 0x02000000, 0x80808080 }, { 0x00460001, 0x46420129, 0x0069062c, 0x00000000 }, { 0x00560001, 0x262c0129, 0x008a0642, 0x00000000 }, { 0x00600040, 0x24004629, 0x008d0624, 0x00650652 }, { 0x00600040, 0x24104629, 0x00650642, 0x008d062c }, { 0x00600040, 0x24002529, 0x00650400, 0x00650404 }, { 0x00600040, 0x25302529, 0x00050408, 0x0005040c }, { 0x00600040, 0x25602529, 0x00050400, 0x00050404 }, { 0x00a02040, 0x24003d2c, 0x00b10520, 0x00040004 }, { 0x00a02008, 0x24003d89, 0x00b10400, 0x00030003 }, { 0x00a02008, 0x24403d89, 0x00b10400, 0x00030003 }, { 0x00a02040, 0x24003d2c, 0x00b10560, 0x00040004 }, { 0x00a02008, 0x24803d89, 0x00b10400, 0x00030003 }, { 0x00a02008, 0x24c03d89, 0x00b10400, 0x00030003 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x22080060, 0x00000000, 0x06440640 }, { 0x00a02001, 0x24000229, 0x00059002, 0x00000000 }, { 0x00a02001, 0x24400229, 0x0005900a, 0x00000000 }, { 0x00a02001, 0x24800229, 0x00059012, 0x00000000 }, { 0x00a02001, 0x24c00229, 0x0005901a, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000003c }, { 0x00a02001, 0x24000229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x24400229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x24800229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x24c00229, 0x00b10624, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000032 }, { 0x00600041, 0x26806e2d, 0x008d062c, 0x44332211 }, { 0x00600041, 0x26906e2d, 0x008d0622, 0xffeeddcc }, { 0x00600041, 0x26a06e2d, 0x00650652, 0x44332211 }, { 0x00600041, 0x26b06e2d, 0x00650642, 0x00ffeedd }, { 0x00200041, 0x26bc3e2d, 0x00450622, 0xfffcfffc }, { 0x00802040, 0x268035ad, 0x008d0680, 0x008d0690 }, { 0x00802040, 0x268035ad, 0x008d0680, 0x008d0688 }, { 0x00802040, 0x268035ad, 0x008d0680, 0x008d0684 }, { 0x00800001, 0x240001ec, 0x00000000, 0x00200020 }, { 0x00400048, 0x24003dac, 0x00a50680, 0x00220022 }, { 0x00400008, 0x26e03d8d, 0x00690400, 0x00060006 }, { 0x00800001, 0x240001ec, 0x00000000, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x00050632, 0x00100010 }, { 0x00800048, 0x26c03e2d, 0x0005065e, 0x00100010 }, { 0x00800048, 0x272055ad, 0x000506e0, 0x00240044 }, { 0x00600041, 0x268055ad, 0x000506e4, 0x00440044 }, { 0x00600041, 0x26a055ad, 0x000506e4, 0x00440045 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00050680 }, { 0x80a02008, 0x44003d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00050684 }, { 0x80a02008, 0x44403d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00050688 }, { 0x80a02008, 0x44803d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x0005068c }, { 0x80a02008, 0x44c03d91, 0x00b10400, 0x00050005 }, { 0x00000040, 0x22063d8c, 0x00000204, 0x00100010 }, { 0x80802040, 0x640045b1, 0x008d8880, 0x00cf0400 }, { 0x80802040, 0x644045b1, 0x008d88a0, 0x00cf0440 }, { 0x80802040, 0x648045b1, 0x008d88c0, 0x00cf0480 }, { 0x80802040, 0x64c045b1, 0x008d88e0, 0x00cf04c0 }, { 0x80802040, 0x640245b1, 0x008d8900, 0x00cf0402 }, { 0x80802040, 0x644245b1, 0x008d8920, 0x00cf0442 }, { 0x80802040, 0x648245b1, 0x008d8940, 0x00cf0482 }, { 0x80802040, 0x64c245b1, 0x008d8960, 0x00cf04c2 }, { 0x00000401, 0x27c80061, 0x00000000, 0x0007000f }, { 0x00200801, 0x27c001a1, 0x004507fa, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00000200, 0x08004000 }, { 0x00800001, 0x20400232, 0x00d20400, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20420, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20440, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d20460, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d20480, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d204a0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d204c0, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d204e0, 0x00000000 }, { 0x01600031, 0x27a00021, 0x508d07c0, 0x00000200 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00000401, 0x27c80061, 0x00000000, 0x000f000f }, { 0x00200801, 0x27c001a1, 0x004507fa, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00000200, 0x0ff04000 }, { 0x00000001, 0x22080060, 0x00000000, 0x04400400 }, { 0x00a02001, 0x20400232, 0x00d29000, 0x00000000 }, { 0x00a02001, 0x20500232, 0x00d29020, 0x00000000 }, { 0x00a02001, 0x20800232, 0x00d29080, 0x00000000 }, { 0x00a02001, 0x20900232, 0x00d290a0, 0x00000000 }, { 0x00a02001, 0x20c00232, 0x00d29100, 0x00000000 }, { 0x00a02001, 0x20d00232, 0x00d29120, 0x00000000 }, { 0x00a02001, 0x21000232, 0x00d29180, 0x00000000 }, { 0x00a02001, 0x21100232, 0x00d291a0, 0x00000000 }, { 0x01600031, 0x27800021, 0x508d07c0, 0x00000200 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00600001, 0x27c00021, 0x008d0000, 0x00000000 }, { 0x00200009, 0x27fa3e29, 0x00450064, 0x00040004 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff04 }, { 0x00000001, 0x220401ec, 0x00000000, 0x00800080 }, { 0x00000001, 0x22080060, 0x00000000, 0x04100400 }, { 0x00200008, 0x27006e2d, 0x0000006c, 0x00000040 }, { 0x00400001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x272001a9, 0x00b10620, 0x00000000 }, { 0x02600005, 0x20001c20, 0x0000006c, 0x00000008 }, { 0x00110001, 0x27230231, 0x00000624, 0x00000000 }, { 0x00600001, 0x27420231, 0x00cf0643, 0x00000000 }, { 0x00110001, 0x27410231, 0x00000643, 0x00000000 }, { 0x00240001, 0x27400231, 0x00000623, 0x00000000 }, { 0x02000005, 0x20001c20, 0x0200006c, 0x00000002 }, { 0x00010001, 0x27400231, 0x02000624, 0x00000000 }, { 0x02000005, 0x20001c20, 0x0200006c, 0x00000001 }, { 0x00110001, 0x27420231, 0x02000623, 0x00000000 }, { 0x00000005, 0x26803e2d, 0x00000070, 0x000f000f }, { 0x00000001, 0x270801ad, 0x00000700, 0x00000000 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000084 }, { 0x00000040, 0x22043d8c, 0x00000204, 0x00800080 }, { 0x00800001, 0x27200231, 0x00b10628, 0x00000000 }, { 0x02600005, 0x20001c20, 0x0200006c, 0x00000004 }, { 0x00680001, 0x272c0231, 0x028d0634, 0x00000000 }, { 0x00780001, 0x272c0231, 0x02000633, 0x00000000 }, { 0x00400001, 0x27420231, 0x00a0040e, 0x00000000 }, { 0x00400001, 0x27460231, 0x00a0044e, 0x00000000 }, { 0x00200001, 0x27400231, 0x0000062b, 0x00000000 }, { 0x02000005, 0x20001c20, 0x0200006c, 0x00000002 }, { 0x00010001, 0x27400231, 0x0200062c, 0x00000000 }, { 0x00110001, 0x27410231, 0x0200040e, 0x00000000 }, { 0x00000008, 0x26803e2d, 0x00000070, 0x00040004 }, { 0x00200040, 0x22083d8c, 0x00450208, 0x00800080 }, { 0x00000006, 0x27083dad, 0x00000700, 0x00010001 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000064 }, { 0x00000040, 0x22043d8c, 0x00000204, 0x00800080 }, { 0x00a02001, 0xb3800231, 0x00d20400, 0x00000000 }, { 0x00a02001, 0xb3a00231, 0x00d20480, 0x00000000 }, { 0x00a02001, 0xb3c00231, 0x00d20440, 0x00000000 }, { 0x00a02001, 0xb3e00231, 0x00d204c0, 0x00000000 }, { 0x02000005, 0x20001c20, 0x00000060, 0x00000002 }, { 0x01000005, 0x20001c20, 0x0200006c, 0x00000001 }, { 0x01010005, 0x20001c20, 0x00000060, 0x00004000 }, { 0x02010005, 0x20001c20, 0x02000060, 0x00000010 }, { 0x00030001, 0x27230231, 0x0000065f, 0x00000000 }, { 0x00030220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02600005, 0x20001c20, 0x0000006c, 0x00000001 }, { 0x00460001, 0x27200231, 0x0069065c, 0x00000000 }, { 0x00110001, 0x27230231, 0x00000458, 0x00000000 }, { 0x00600001, 0x27240231, 0x008d0458, 0x00000000 }, { 0x00600001, 0x272c0231, 0x008d0478, 0x00000000 }, { 0x00600001, 0x27420231, 0x00cf0663, 0x00000000 }, { 0x00000001, 0x27400231, 0x00000458, 0x00000000 }, { 0x00010001, 0x27410231, 0x0000065f, 0x00000000 }, { 0x00110001, 0x27410231, 0x00000663, 0x00000000 }, { 0x02000005, 0x20001c20, 0x0200006c, 0x00000010 }, { 0x00110001, 0x27420231, 0x0200065f, 0x00000000 }, { 0x00000005, 0x26803e2d, 0x00000071, 0x000f000f }, { 0x00000006, 0x27083dad, 0x00000702, 0x00020002 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000040, 0x22043d8c, 0x00000204, 0x00800080 }, { 0x00400001, 0x27200231, 0x0069045c, 0x00000000 }, { 0x00600001, 0x27240231, 0x008d0478, 0x00000000 }, { 0x00800001, 0x272c0231, 0x0000047f, 0x00000000 }, { 0x00400001, 0x27420231, 0x00a0048e, 0x00000000 }, { 0x00400001, 0x27460231, 0x00a004ce, 0x00000000 }, { 0x00000001, 0x27400231, 0x00000478, 0x00000000 }, { 0x00000001, 0x27410231, 0x0000045f, 0x00000000 }, { 0x00000008, 0x26803e2d, 0x00000071, 0x00040004 }, { 0x00200040, 0x22083d8c, 0x00450208, 0x00800080 }, { 0x00000006, 0x27083dad, 0x00000700, 0x00030003 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00a02001, 0xb3800231, 0x00d20480, 0x00000000 }, { 0x00a02001, 0xb3a00231, 0x00d20500, 0x00000000 }, { 0x00a02001, 0xb3c00231, 0x00d204c0, 0x00000000 }, { 0x00a02001, 0xb3e00231, 0x00d20540, 0x00000000 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000100 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffe74 }, { 0x00000001, 0x27800021, 0x00000780, 0x00000000 }, { 0x00000001, 0x27a00021, 0x000007a0, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00000001, 0x27340231, 0x00000733, 0x00000000 }, { 0x00600001, 0x274a0231, 0x00000749, 0x00000000 }, { 0x00800040, 0x24003e2c, 0x00b10723, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10724, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10725, 0x00010001 }, { 0x00800008, 0x26c03d8d, 0x008d0400, 0x00020002 }, { 0x00800040, 0x24003e2c, 0x00b10740, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10741, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10742, 0x00010001 }, { 0x00800008, 0x26a03d8d, 0x008d0400, 0x00020002 }, { 0x00800001, 0x27240231, 0x00d206c0, 0x00000000 }, { 0x00600001, 0x27400231, 0x00ae06a2, 0x00000000 }, { 0x00000001, 0x27230231, 0x000006a0, 0x00000000 }, { 0x00000005, 0x220e3dac, 0x00000680, 0x000f000f }, { 0x00000001, 0x26a00221, 0x00009c2c, 0x00000000 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006a0 }, { 0x80800040, 0xd00045b1, 0x00b18800, 0x000d0724 }, { 0x80800040, 0xd02045b1, 0x00b18820, 0x000d0724 }, { 0x80800040, 0xd04045b1, 0x00b18840, 0x000d0724 }, { 0x80800040, 0xd06045b1, 0x00b18860, 0x000d0724 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x80800040, 0xd00045b1, 0x00b18800, 0x002c0740 }, { 0x80800040, 0xd02045b1, 0x00b18820, 0x002c0742 }, { 0x80800040, 0xd04045b1, 0x00b18840, 0x002c0744 }, { 0x80800040, 0xd06045b1, 0x00b18860, 0x002c0746 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x02802005, 0x20003da0, 0x00000708, 0x00020002 }, { 0x02600005, 0x20003da0, 0x02000708, 0x00010001 }, { 0x009a0001, 0x27200169, 0x00000000, 0x80808080 }, { 0x00780001, 0x27400231, 0x028d0724, 0x00000000 }, { 0x00780001, 0x27240231, 0x008d0740, 0x00000000 }, { 0x00600040, 0x25e04629, 0x008d0724, 0x008d0740 }, { 0x00400040, 0x25e02529, 0x006905e0, 0x006905e8 }, { 0x00200040, 0x25e02529, 0x004505e0, 0x004505e4 }, { 0x00800040, 0x2400252c, 0x000005e0, 0x000005e2 }, { 0x00800040, 0x24003d8c, 0x008d0400, 0x00080008 }, { 0x00800008, 0x26803d8d, 0x008d0400, 0x00040004 }, { 0x80800040, 0xd00035b1, 0x00b18800, 0x00b10680 }, { 0x80800040, 0xd02035b1, 0x00b18820, 0x00b10680 }, { 0x80800040, 0xd04035b1, 0x00b18840, 0x00b10680 }, { 0x80800040, 0xd06035b1, 0x00b18860, 0x00b10680 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00600001, 0x27340231, 0x008d0733, 0x00000000 }, { 0x00800040, 0x24003e2c, 0x00b10726, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10725, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10724, 0x00010001 }, { 0x00800008, 0x26803d8d, 0x00b10400, 0x00020002 }, { 0x80800040, 0xd00035b1, 0x00b18800, 0x002d0680 }, { 0x80800040, 0xd02035b1, 0x00b18820, 0x002d0684 }, { 0x80800040, 0xd04035b1, 0x00b18840, 0x002d0688 }, { 0x80800040, 0xd06035b1, 0x00b18860, 0x002d068c }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00400009, 0x26c05421, 0x00000744, 0x00690050 }, { 0x00400009, 0x26d05421, 0x00000740, 0x00690050 }, { 0x00600001, 0x26a00231, 0x00cf06c3, 0x00000000 }, { 0x00800001, 0x26a80231, 0x00b10723, 0x00000000 }, { 0x00800040, 0x24003e2c, 0x00b106a2, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b106a1, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b106a0, 0x00010001 }, { 0x00800008, 0x26a03d8d, 0x00b10400, 0x00020002 }, { 0x00200040, 0x220c3eac, 0x00450056, 0x06a006a0 }, { 0x80800040, 0xd06035b1, 0x01ed9800, 0x00b18860 }, { 0x80800040, 0xd04035b1, 0x01ed9804, 0x00b18840 }, { 0x80800040, 0xd02035b1, 0x01ed9808, 0x00b18820 }, { 0x80800040, 0xd00035b1, 0x01ed980c, 0x00b18800 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00400009, 0x26c05421, 0x00000744, 0x00690050 }, { 0x00400009, 0x26d05421, 0x00000740, 0x00690050 }, { 0x00600001, 0x26a00231, 0x00cf06c3, 0x00000000 }, { 0x00800001, 0x26a80231, 0x00b10723, 0x00000000 }, { 0x00800042, 0x25c04629, 0x00b106a8, 0x00b106a9 }, { 0x00800040, 0x24003e2c, 0x00b106a3, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b106a2, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b106a1, 0x00010001 }, { 0x00800008, 0x26c03d8d, 0x008d0400, 0x00020002 }, { 0x00600001, 0x26a00231, 0x00ae06c0, 0x00000000 }, { 0x00600001, 0x46a60231, 0x00ae06cc, 0x00000000 }, { 0x00600001, 0x46a70231, 0x00ae05c0, 0x00000000 }, { 0x00200040, 0x220c3eac, 0x00450036, 0x06a006a0 }, { 0x80800040, 0xd0603631, 0x01ee9800, 0x00b18860 }, { 0x80800040, 0xd0403631, 0x01ee9802, 0x00b18840 }, { 0x80800040, 0xd0203631, 0x01ee9804, 0x00b18820 }, { 0x80800040, 0xd0003631, 0x01ee9806, 0x00b18800 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00400009, 0x26c05421, 0x00000744, 0x00690050 }, { 0x00400009, 0x26d05421, 0x00000740, 0x00690050 }, { 0x00600001, 0x26a00231, 0x00ab06c3, 0x00000000 }, { 0x00800001, 0x26a80231, 0x00b10723, 0x00000000 }, { 0x00800040, 0x24003e2c, 0x00b106a2, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b106a1, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b106a0, 0x00010001 }, { 0x00800008, 0x25c03d89, 0x008d0400, 0x00020002 }, { 0x00800042, 0x26a0462d, 0x00b106a0, 0x00b106a1 }, { 0x00600001, 0x46a10231, 0x00ae05c0, 0x00000000 }, { 0x00600001, 0x26b00231, 0x00ae05d0, 0x00000000 }, { 0x00200040, 0x220c3eac, 0x00450056, 0x06a006a0 }, { 0x80800040, 0xd0603631, 0x01ed9800, 0x00b18860 }, { 0x80800040, 0xd0403631, 0x01ed9804, 0x00b18840 }, { 0x80800040, 0xd0203631, 0x01ed9808, 0x00b18820 }, { 0x80800040, 0xd0003631, 0x01ed980c, 0x00b18800 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00800042, 0x25c04629, 0x00b10724, 0x00b10725 }, { 0x00800040, 0x24003e2c, 0x00b10726, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10725, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10724, 0x00010001 }, { 0x00800008, 0x25e03d89, 0x002d0400, 0x00020002 }, { 0x80800040, 0xd0003531, 0x00ad05c0, 0x00b18800 }, { 0x80800040, 0xd0203531, 0x00ad05c2, 0x00b18820 }, { 0x80800040, 0xd0403531, 0x00ad05c4, 0x00b18840 }, { 0x80800040, 0xd0603531, 0x00ad05c6, 0x00b18860 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00600001, 0x27480231, 0x00000747, 0x00000000 }, { 0x00800042, 0x25c04629, 0x00b10740, 0x00b10741 }, { 0x00800040, 0x24003e2c, 0x00b10742, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10741, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10740, 0x00010001 }, { 0x00800008, 0x25e03d89, 0x002d0400, 0x00020002 }, { 0x00800001, 0x45c10231, 0x00d205e0, 0x00000000 }, { 0x80800040, 0xd0003631, 0x004d05c0, 0x00b18800 }, { 0x80800040, 0xd0203631, 0x004d05c4, 0x00b18820 }, { 0x80800040, 0xd0403631, 0x004d05c8, 0x00b18840 }, { 0x80800040, 0xd0603631, 0x004d05cc, 0x00b18860 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00000401, 0x27c80061, 0x00000000, 0x000f000f }, { 0x00200801, 0x27c001a1, 0x004507fa, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00000200, 0x0ff04000 }, { 0x00800001, 0x20400232, 0x00cd0400, 0x00000000 }, { 0x00800001, 0x20500232, 0x00cd0408, 0x00000000 }, { 0x00800001, 0x20600232, 0x00cd0410, 0x00000000 }, { 0x00800001, 0x20700232, 0x00cd0418, 0x00000000 }, { 0x00800001, 0x20800232, 0x00cd0440, 0x00000000 }, { 0x00800001, 0x20900232, 0x00cd0448, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00cd0450, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00cd0458, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00cd0480, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00cd0488, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00cd0490, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00cd0498, 0x00000000 }, { 0x00800001, 0x21000232, 0x00cd04c0, 0x00000000 }, { 0x00800001, 0x21100232, 0x00cd04c8, 0x00000000 }, { 0x00800001, 0x21200232, 0x00cd04d0, 0x00000000 }, { 0x00800001, 0x21300232, 0x00cd04d8, 0x00000000 }, { 0x01600031, 0x27800021, 0x508d07c0, 0x00000200 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00600001, 0x27c00021, 0x008d0000, 0x00000000 }, { 0x00200009, 0x27fa3e29, 0x00450064, 0x00040004 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffd34 }, { 0x00000001, 0x220401ec, 0x00000000, 0x00800080 }, { 0x00000001, 0x220601ec, 0x00000000, 0x04000400 }, { 0x00200008, 0x27006e2d, 0x0000006c, 0x00000040 }, { 0x02600005, 0x20003e20, 0x0000006c, 0x00040004 }, { 0x00780001, 0x26340231, 0x00000633, 0x00000000 }, { 0x00800001, 0x27200231, 0x00b10620, 0x00000000 }, { 0x00600001, 0x27400231, 0x00cf0643, 0x00000000 }, { 0x00400008, 0x26806e2d, 0x00240070, 0x00004040 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000006a }, { 0x00000040, 0x22043d8c, 0x00000204, 0x00800080 }, { 0x00000006, 0x27003dad, 0x00000700, 0x00010001 }, { 0x00800001, 0x27200231, 0x00b10628, 0x00000000 }, { 0x00400001, 0x27400231, 0x00808c26, 0x00000000 }, { 0x00400001, 0x27440231, 0x00808c66, 0x00000000 }, { 0x00400008, 0x26806e2d, 0x00240072, 0x00004040 }, { 0x00000040, 0x22063d8c, 0x00000206, 0x00800080 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000058 }, { 0x00000040, 0x22043d8c, 0x00000204, 0x00800080 }, { 0x00000006, 0x27003dad, 0x00000702, 0x00020002 }, { 0x00800001, 0xaf800231, 0x00d28f80, 0x00000000 }, { 0x00800001, 0xaf900231, 0x00d28fa0, 0x00000000 }, { 0x00800001, 0xafc00231, 0x00d28fc0, 0x00000000 }, { 0x00800001, 0xafd00231, 0x00d28fe0, 0x00000000 }, { 0x00800001, 0xafa00231, 0x00d28c00, 0x00000000 }, { 0x00800001, 0xafb00231, 0x00d28c20, 0x00000000 }, { 0x00800001, 0xafe00231, 0x00d28c40, 0x00000000 }, { 0x00800001, 0xaff00231, 0x00d28c60, 0x00000000 }, { 0x00400001, 0x27200231, 0x0069065c, 0x00000000 }, { 0x00600001, 0x27240231, 0x00a98fcc, 0x00000000 }, { 0x00600001, 0x272c0231, 0x00a98fec, 0x00000000 }, { 0x00600001, 0x27340231, 0x00008fff, 0x00000000 }, { 0x00800001, 0x2620012d, 0x00b10720, 0x00000000 }, { 0x00600001, 0x27400231, 0x00cf0663, 0x00000000 }, { 0x00400008, 0x26806e2d, 0x00240074, 0x00004040 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000032 }, { 0x00000040, 0x22043d8c, 0x00000204, 0x00800080 }, { 0x00000006, 0x27003dad, 0x00000700, 0x00010001 }, { 0x00800001, 0x27200231, 0x00b10628, 0x00000000 }, { 0x00600001, 0x27300231, 0x008d0638, 0x00000000 }, { 0x00400001, 0x27400231, 0x00808c26, 0x00000000 }, { 0x00400001, 0x27440231, 0x00808c66, 0x00000000 }, { 0x00400008, 0x26806e2d, 0x00240076, 0x00004040 }, { 0x00000040, 0x22063d8c, 0x00000206, 0x00800080 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x00800001, 0xaf800231, 0x00d28f80, 0x00000000 }, { 0x00800001, 0xaf900231, 0x00d28fa0, 0x00000000 }, { 0x00800001, 0xafc00231, 0x00d28fc0, 0x00000000 }, { 0x00800001, 0xafd00231, 0x00d28fe0, 0x00000000 }, { 0x00800001, 0xafa00231, 0x00d28c00, 0x00000000 }, { 0x00800001, 0xafb00231, 0x00d28c20, 0x00000000 }, { 0x00800001, 0xafe00231, 0x00d28c40, 0x00000000 }, { 0x00800001, 0xaff00231, 0x00d28c60, 0x00000000 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000e0 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffcce }, { 0x00000001, 0x27800021, 0x00000780, 0x00000000 }, { 0x00000001, 0x27a00021, 0x000007a0, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00600001, 0x27800231, 0x008d0740, 0x00000000 }, { 0x00400005, 0x22083dac, 0x00690680, 0x000f000f }, { 0x00400040, 0x26a04625, 0x01e09020, 0x00690058 }, { 0x00000001, 0x26d001ad, 0x00000700, 0x00000000 }, { 0x00000040, 0x27e41c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006a0 }, { 0x80600040, 0xcc0035b1, 0x00898800, 0x008d0760 }, { 0x80600040, 0xcc1035b1, 0x00898820, 0x008d0770 }, { 0x00800001, 0x27200231, 0x008d0724, 0x00000000 }, { 0x00400001, 0x27400231, 0x00808c06, 0x00000000 }, { 0x00000006, 0x26d03dad, 0x00000700, 0x00010001 }, { 0x00000040, 0x27e41c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006a4 }, { 0x80600040, 0xcc2035b1, 0x00898808, 0x008d0760 }, { 0x80600040, 0xcc3035b1, 0x00898828, 0x008d0770 }, { 0x00000001, 0x27230231, 0x00000783, 0x00000000 }, { 0x00400001, 0x27240231, 0x008a8c18, 0x00000000 }, { 0x00400001, 0x27280231, 0x008a8c38, 0x00000000 }, { 0x00400001, 0x272c0231, 0x00008c3e, 0x00000000 }, { 0x00400001, 0x27400231, 0x00690784, 0x00000000 }, { 0x00000006, 0x26d03dad, 0x00000700, 0x00020002 }, { 0x00000040, 0x27e41c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006a8 }, { 0x80600040, 0xcc4035b1, 0x00898840, 0x008d0760 }, { 0x80600040, 0xcc5035b1, 0x00898860, 0x008d0770 }, { 0x00800001, 0x27200231, 0x008d0724, 0x00000000 }, { 0x00600001, 0x27280231, 0x00000727, 0x00000000 }, { 0x00400001, 0x27400231, 0x00808c46, 0x00000000 }, { 0x00000006, 0x26d03dad, 0x00000700, 0x00030003 }, { 0x00000040, 0x27e41c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006ac }, { 0x80600040, 0xcc6035b1, 0x00898848, 0x008d0760 }, { 0x80600040, 0xcc7035b1, 0x00898868, 0x008d0770 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00800001, 0x2760022d, 0x00090724, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00800001, 0x2760022d, 0x00280740, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x02802005, 0x20003da0, 0x000006d0, 0x00020002 }, { 0x02802005, 0x20003da0, 0x020006d0, 0x00010001 }, { 0x009a0001, 0x27200169, 0x00000000, 0x80808080 }, { 0x00780001, 0x27400231, 0x028d0724, 0x00000000 }, { 0x00780001, 0x27240231, 0x008d0740, 0x00000000 }, { 0x00400040, 0x25e04629, 0x00690724, 0x00690740 }, { 0x00200040, 0x25e02529, 0x004505e0, 0x004505e4 }, { 0x00800040, 0x2400252c, 0x000005e0, 0x000005e2 }, { 0x00800040, 0x24003d8c, 0x008d0400, 0x00040004 }, { 0x00800008, 0x27603d8d, 0x008d0400, 0x00030003 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00600001, 0x26c00231, 0x008d0724, 0x00000000 }, { 0x00400001, 0x26c80231, 0x0069072b, 0x00000000 }, { 0x00600040, 0x24003e2c, 0x008d06c2, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d06c1, 0x00020002 }, { 0x00600048, 0x25e03e29, 0x008d06c0, 0x00010001 }, { 0x00800008, 0x27603d2d, 0x002905e0, 0x00020002 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00400009, 0x26e05421, 0x00000740, 0x00690050 }, { 0x00600001, 0x26c40231, 0x008d0723, 0x00000000 }, { 0x00400001, 0x26c00231, 0x00ab06e3, 0x00000000 }, { 0x00600040, 0x24003e2c, 0x008d06c2, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d06c1, 0x00020002 }, { 0x00600048, 0x26c03e2d, 0x008d06c0, 0x00010001 }, { 0x00400040, 0x22083eac, 0x00690054, 0x06c006c0 }, { 0x00800008, 0x27603dad, 0x01e99000, 0x00020002 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00400009, 0x26e05421, 0x00000740, 0x00690050 }, { 0x00600001, 0x26c40231, 0x008d0723, 0x00000000 }, { 0x00400001, 0x26c00231, 0x00ab06e3, 0x00000000 }, { 0x00600042, 0x25c04629, 0x008d06c4, 0x008d06c5 }, { 0x00600040, 0x24003e2c, 0x008d06c3, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d06c2, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d06c1, 0x00010001 }, { 0x00600008, 0x26c03d8d, 0x008d0400, 0x00020002 }, { 0x00400001, 0x46c401ad, 0x006906c4, 0x00000000 }, { 0x00400001, 0x46c6012d, 0x006905c0, 0x00000000 }, { 0x00400040, 0x22083eac, 0x00690054, 0x06c006c0 }, { 0x00800001, 0x276001ad, 0x01ea9000, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00400009, 0x26e05421, 0x00000740, 0x00690050 }, { 0x00600001, 0x26c40231, 0x008d0723, 0x00000000 }, { 0x00400001, 0x26c00231, 0x00ab06e3, 0x00000000 }, { 0x00600042, 0x25c04629, 0x008d06c0, 0x008d06c1 }, { 0x00600040, 0x24003e2c, 0x008d06c2, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d06c1, 0x00020002 }, { 0x00600048, 0x26e03e2d, 0x008d06c0, 0x00010001 }, { 0x00400008, 0x46c23dad, 0x006906e0, 0x00020002 }, { 0x00200008, 0x26d03dad, 0x004506e8, 0x00020002 }, { 0x00400001, 0x46c0012d, 0x006905c0, 0x00000000 }, { 0x00400009, 0x22083eac, 0x00690054, 0x00010001 }, { 0x00400040, 0x22083d8c, 0x00690208, 0x06c006c0 }, { 0x00800001, 0x276001ad, 0x01e99000, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00600042, 0x45c04629, 0x008d0724, 0x008d0725 }, { 0x00600040, 0x24003e2c, 0x008d0726, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d0725, 0x00020002 }, { 0x00600048, 0x25e03e29, 0x008d0724, 0x00010001 }, { 0x00600008, 0x45c23d29, 0x008d05e0, 0x00020002 }, { 0x00800001, 0x2760012d, 0x002a05c0, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00600001, 0x27440231, 0x00000743, 0x00000000 }, { 0x00600042, 0x45c04629, 0x008d0740, 0x008d0741 }, { 0x00600040, 0x24003e2c, 0x008d0742, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d0741, 0x00020002 }, { 0x00600048, 0x25e03e29, 0x008d0740, 0x00010001 }, { 0x00600008, 0x45c23d29, 0x008d05e0, 0x00020002 }, { 0x00800001, 0x2760012d, 0x004905c0, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00000401, 0x27c80061, 0x00000000, 0x000f000f }, { 0x00200801, 0x27c001a1, 0x004507fa, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00000200, 0x0ff04000 }, { 0x00800001, 0x20400232, 0x00a90400, 0x00000000 }, { 0x00800001, 0x20500232, 0x00a90404, 0x00000000 }, { 0x00800001, 0x20600232, 0x00a90408, 0x00000000 }, { 0x00800001, 0x20700232, 0x00a9040c, 0x00000000 }, { 0x00800001, 0x20800232, 0x00a90440, 0x00000000 }, { 0x00800001, 0x20900232, 0x00a90444, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00a90448, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00a9044c, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00a90480, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00a90484, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00a90488, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00a9048c, 0x00000000 }, { 0x00800001, 0x21000232, 0x00a904c0, 0x00000000 }, { 0x00800001, 0x21100232, 0x00a904c4, 0x00000000 }, { 0x00800001, 0x21200232, 0x00a904c8, 0x00000000 }, { 0x00800001, 0x21300232, 0x00a904cc, 0x00000000 }, { 0x01600031, 0x27800021, 0x508d07c0, 0x00000200 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00021, 0x008d0000, 0x00000000 }, { 0x00200009, 0x27fa3e29, 0x00450064, 0x00040004 }, { 0x00000401, 0x27c80061, 0x00000000, 0x000f000f }, { 0x00200809, 0x27c03e21, 0x00450064, 0x00040004 }, { 0x00000040, 0x22000d20, 0x00000062, 0x1218a000 }, { 0x00a02401, 0x20400232, 0x00b10080, 0x00000000 }, { 0x00a02801, 0x20500232, 0x00b10090, 0x00000000 }, { 0x00a02401, 0x20800232, 0x00b100c0, 0x00000000 }, { 0x00a02801, 0x20900232, 0x00b100d0, 0x00000000 }, { 0x00a02401, 0x20c00232, 0x00b10100, 0x00000000 }, { 0x00a02801, 0x20d00232, 0x00b10110, 0x00000000 }, { 0x00a02401, 0x21000232, 0x00b10140, 0x00000000 }, { 0x00a02801, 0x21100232, 0x00b10150, 0x00000000 }, { 0x01600031, 0x27800021, 0x508d07c0, 0x00000200 }, { 0x00000401, 0x20280062, 0x00000000, 0x0007000f }, { 0x0000080c, 0x20243c22, 0x000007c4, 0x00010001 }, { 0x00000040, 0x22001c00, 0x00000200, 0xf8000001 }, { 0x00800001, 0x40400232, 0x00b10180, 0x00000000 }, { 0x00800001, 0x40410232, 0x00b101c0, 0x00000000 }, { 0x00800001, 0x40600232, 0x00b10190, 0x00000000 }, { 0x00800001, 0x40610232, 0x00b101d0, 0x00000000 }, { 0x00800001, 0x40800232, 0x00b101a0, 0x00000000 }, { 0x00800001, 0x40810232, 0x00b101e0, 0x00000000 }, { 0x00800001, 0x40a00232, 0x00b101b0, 0x00000000 }, { 0x00800001, 0x40a10232, 0x00b101f0, 0x00000000 }, { 0x01600031, 0x27a00001, 0x508d0000, 0x00000200 }, { 0x00000001, 0x27800021, 0x00000780, 0x00000000 }, { 0x00000001, 0x27a00021, 0x000007a0, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0000, 0x00000000 }, { 0x00000005, 0x20203e2d, 0x00000061, 0x001f001f }, { 0x00200009, 0x20643e2d, 0x00450064, 0x00040004 }, { 0x00000001, 0x203a01ed, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000020, 0x00160016 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x01200010, 0x20003e2c, 0x0200006c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000024 }, { 0x00800009, 0x25403dad, 0x00050064, 0x00020002 }, { 0x00000001, 0x203a01ed, 0x00000000, 0x00180018 }, { 0x00200040, 0x45483dad, 0x00660548, 0x00100010 }, { 0x00200040, 0x45523dad, 0x00660552, 0x00100010 }, { 0x00400040, 0x25583dad, 0x00690558, 0x00100010 }, { 0x00800040, 0x208035ad, 0x00b10080, 0x00b10540 }, { 0x00600040, 0x45403dad, 0x00ae0540, 0x00200020 }, { 0x00800040, 0x20a035ad, 0x00b100a0, 0x00b10540 }, { 0x00600040, 0x45423dad, 0x00ae0542, 0x00200020 }, { 0x00800040, 0x20e035ad, 0x00b100e0, 0x00b10540 }, { 0x00600040, 0x45403dad, 0x00ae0540, 0xffe0ffe0 }, { 0x00800040, 0x20c035ad, 0x00b100c0, 0x00b10540 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000014 }, { 0x06600010, 0x20003dac, 0x02000020, 0x00030003 }, { 0x00000001, 0x206c0171, 0x00000000, 0x00000000 }, { 0x00610001, 0x208000a5, 0x02050080, 0x00000000 }, { 0x00610001, 0x212000a5, 0x02090100, 0x00000000 }, { 0x00410001, 0x211000a5, 0x02690100, 0x00000000 }, { 0x00200009, 0x25403dad, 0x00450064, 0x00020002 }, { 0x00800040, 0x208035ad, 0x00b10080, 0x00050540 }, { 0x00200040, 0x40883dad, 0x00660088, 0x00200020 }, { 0x00200040, 0x40923dad, 0x00660092, 0x00200020 }, { 0x00400040, 0x20983dad, 0x00690098, 0x00200020 }, { 0x00200401, 0x22080060, 0x00000000, 0x03400140 }, { 0x00000c01, 0x220c0060, 0x00000000, 0x04400080 }, { 0x00000801, 0x22040060, 0x00000000, 0x01000070 }, { 0x00000001, 0x20200169, 0x00000000, 0x00000000 }, { 0x0000000c, 0x2458262d, 0x0000006d, 0x00000020 }, { 0x00000001, 0x210e0169, 0x00000000, 0x00010001 }, { 0x00000005, 0x24583dad, 0x00000458, 0x00030003 }, { 0x01000010, 0x200035ac, 0x0000010e, 0x00000458 }, { 0x00010220, 0x34001c00, 0x00001400, 0x000002fe }, { 0x01000010, 0x20003dac, 0x0200010e, 0x00010001 }, { 0x00010401, 0x24540061, 0x02000000, 0x06c00640 }, { 0x00010805, 0x245a3e2d, 0x02008800, 0x007f007f }, { 0x00110401, 0x24540061, 0x02000000, 0x04800780 }, { 0x00110805, 0x245a3e2d, 0x02008804, 0x007f007f }, { 0x0000000c, 0x211e362d, 0x0000006c, 0x00000020 }, { 0x00000040, 0x20780d21, 0x0000045a, 0x0208a002 }, { 0x02000005, 0x20003dac, 0x0200011e, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000001be }, { 0x01000005, 0x20003dac, 0x00009800, 0x00030003 }, { 0x00200005, 0x24443dad, 0x00459800, 0x00030003 }, { 0x0020000c, 0x24403dad, 0x00459800, 0x00020002 }, { 0x01600006, 0x20003dac, 0x02000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00010040, 0x22000c20, 0x02000078, 0x00400000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00700000 }, { 0x00310040, 0x20401da5, 0x02450440, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x000c000c }, { 0x00010040, 0x20401da5, 0x02000440, 0xfffffffe }, { 0x00010001, 0x204401a5, 0x02000442, 0x00000000 }, { 0x00010001, 0x20480061, 0x02000000, 0x0007000c }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00010040, 0x22000c20, 0x02000078, 0x00200000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00400000 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00110040, 0x20441da5, 0x02000442, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x000c0007 }, { 0x00010001, 0x20480061, 0x02000000, 0x00070007 }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x0020040c, 0x24403dad, 0x00459800, 0x00030003 }, { 0x00200805, 0x24483dad, 0x00459800, 0x00070007 }, { 0x01600006, 0x20003dac, 0x0000044a, 0x00000000 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00000009, 0x20403ca5, 0x00000040, 0x00010001 }, { 0x00010040, 0x22000c20, 0x00000078, 0x00200010 }, { 0x00110040, 0x22000c20, 0x00000078, 0x00300010 }, { 0x00010001, 0x20480061, 0x00000000, 0x00030009 }, { 0x00110001, 0x20480061, 0x00000000, 0x00040009 }, { 0x02600031, 0x27000021, 0x408d0040, 0x00000200 }, { 0x01000005, 0x20003dac, 0x00009800, 0x00030003 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00600001, 0x26220231, 0x008d05c0, 0x00000000 }, { 0x00600401, 0x26120231, 0x008d05b8, 0x00000000 }, { 0x00600801, 0x26020231, 0x008d05b0, 0x00000000 }, { 0x00600401, 0x25f20231, 0x008d05a8, 0x00000000 }, { 0x00600801, 0x25e20231, 0x008d05a0, 0x00000000 }, { 0x00600401, 0x25d20231, 0x008d0598, 0x00000000 }, { 0x00600801, 0x25c20231, 0x008d0590, 0x00000000 }, { 0x00600401, 0x25b20231, 0x008d0588, 0x00000000 }, { 0x00600801, 0x25a20231, 0x008d0580, 0x00000000 }, { 0x00600401, 0x25920231, 0x008d0578, 0x00000000 }, { 0x00600801, 0x25820231, 0x008d0570, 0x00000000 }, { 0x00600001, 0x25720231, 0x008d0568, 0x00000000 }, { 0x00600001, 0x25620231, 0x008d0560, 0x00000000 }, { 0x00110001, 0x220001ec, 0x02000000, 0x05820582 }, { 0x00010001, 0x220001ec, 0x02000000, 0x05620562 }, { 0x00000001, 0x220e0128, 0x00000454, 0x00000000 }, { 0x01800006, 0x200035ac, 0x02000446, 0x00000444 }, { 0x00810001, 0xbc000229, 0x02ad8000, 0x00000000 }, { 0x00810001, 0xbc200229, 0x02ad8020, 0x00000000 }, { 0x00810001, 0xbc400229, 0x02ad8040, 0x00000000 }, { 0x00810001, 0xbc600229, 0x02ad8060, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000012a }, { 0x00600001, 0x2024018d, 0x008d0200, 0x00000000 }, { 0x01000041, 0x245e35ad, 0x00000446, 0x00000444 }, { 0x00000040, 0x22022d08, 0x00000200, 0x00100010 }, { 0x02000005, 0x20003db0, 0x0200045e, 0x00010001 }, { 0x00200040, 0x22042d08, 0x00450200, 0x00200020 }, { 0x00400001, 0x244c0109, 0x00690200, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000066 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000064 }, { 0x00000040, 0x22003d08, 0x00000200, 0xffdeffde }, { 0x00000440, 0x22023d08, 0x00000202, 0xffeeffee }, { 0x00000801, 0x220c0060, 0x00000000, 0x04a00480 }, { 0x01000010, 0x20003db0, 0x0000045e, 0x00040004 }, { 0x00a02040, 0x2400462c, 0x00ad8000, 0x00ad8005 }, { 0x00a02048, 0x24003e2c, 0x00ad8001, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8002, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8003, 0x00140014 }, { 0x00a02048, 0xb8003e2d, 0x00ad8004, 0xfffbfffb }, { 0x00a02040, 0x2400462c, 0x00ad8040, 0x00ad8045 }, { 0x00a02048, 0x24003e2c, 0x00ad8041, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8042, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8043, 0x00140014 }, { 0x00a02048, 0xb8403e2d, 0x00ad8044, 0xfffbfffb }, { 0x00a02040, 0x2400462c, 0x00ad8080, 0x00ad8085 }, { 0x00a02048, 0x24003e2c, 0x00ad8081, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8082, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8083, 0x00140014 }, { 0x00a02048, 0xb8803e2d, 0x00ad8084, 0xfffbfffb }, { 0x00600040, 0x2400462c, 0x008d80c0, 0x008d80c5 }, { 0x00600048, 0x24003e2c, 0x008d80c1, 0xfffbfffb }, { 0x00600048, 0x24003e2c, 0x008d80c2, 0x00140014 }, { 0x00600048, 0x24003e2c, 0x008d80c3, 0x00140014 }, { 0x00600048, 0xb8c03e2d, 0x008d80c4, 0xfffbfffb }, { 0x00000401, 0x22000060, 0x00000000, 0x04a00480 }, { 0x00000c01, 0x22040060, 0x00000000, 0x04a00490 }, { 0x00010802, 0x220c2d28, 0x00000454, 0x04800480 }, { 0x00a02040, 0x24003dac, 0x00b18000, 0x02000200 }, { 0x00800048, 0x24003dac, 0x01ed8800, 0xfffbfffb }, { 0x00800048, 0x24203dac, 0x01ed8820, 0xfffbfffb }, { 0x00a02048, 0x24003dac, 0x00b18020, 0x00140014 }, { 0x00800048, 0x24003dac, 0x01ed8820, 0x00140014 }, { 0x00800048, 0x24203dac, 0x01ed8840, 0x00140014 }, { 0x00a02048, 0x24003dac, 0x00b18040, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed8840, 0x00010001 }, { 0x00800048, 0x24203dac, 0x01ed8860, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x000a000a }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x000a000a }, { 0x00a02040, 0x24003dac, 0x00b18040, 0x02000200 }, { 0x00800048, 0x24003dac, 0x01ed8840, 0xfffbfffb }, { 0x00800048, 0x24203dac, 0x01ed8860, 0xfffbfffb }, { 0x00a02048, 0x24003dac, 0x00b18060, 0x00140014 }, { 0x00800048, 0x24003dac, 0x01ed8860, 0x00140014 }, { 0x00800048, 0x24203dac, 0x01ed8880, 0x00140014 }, { 0x00a02048, 0x24003dac, 0x00b18080, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed8880, 0x00010001 }, { 0x00800048, 0x24203dac, 0x01ed88a0, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x000a000a }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x000a000a }, { 0x00010220, 0x34001c00, 0x00001400, 0x000000b4 }, { 0x01000010, 0x20003db0, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000004c }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000004a }, { 0x00400040, 0x22003d28, 0x0069044c, 0xfffefffe }, { 0x03400010, 0x20003dac, 0x00000446, 0x00020002 }, { 0x01000010, 0x20003db0, 0x02000444, 0x00020002 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00100010 }, { 0x01000010, 0x20003dac, 0x00000446, 0x00000000 }, { 0x00010002, 0x220c2d28, 0x02000454, 0x04800480 }, { 0x00800040, 0x24003e2c, 0x01ed8000, 0x00100010 }, { 0x00800040, 0x24203e2c, 0x01ed8020, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8001, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8021, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8002, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8022, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8003, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8023, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8004, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8024, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8005, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8025, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x00050005 }, { 0x00800040, 0x24003e2c, 0x01ed8040, 0x00100010 }, { 0x00800040, 0x24203e2c, 0x01ed8060, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8041, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8061, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8042, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8062, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8043, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8063, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8044, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8064, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8045, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8065, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x00050005 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000005c }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000062 }, { 0x01000010, 0x20003db0, 0x00000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000042 }, { 0x00200401, 0x22000128, 0x0066044c, 0x00000000 }, { 0x00200c01, 0x22040128, 0x0045044e, 0x00000000 }, { 0x00000801, 0x220c0128, 0x00000454, 0x00000000 }, { 0x03400010, 0x20003dac, 0x02000444, 0x00020002 }, { 0x01000010, 0x20003dac, 0x00000444, 0x00000000 }, { 0x00410040, 0x22002d08, 0x02690200, 0x00010001 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00110001, 0x220c0168, 0x02000000, 0x04800480 }, { 0x00a02040, 0x24003e2c, 0x00ad83e0, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8be0, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8800, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8800, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8820, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8020, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8820, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8840, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x00050005 }, { 0x00a02040, 0x24003e2c, 0x00ad8020, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8820, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8840, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8040, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8840, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8860, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8060, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8860, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8880, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x00050005 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001c }, { 0x00200401, 0x22000128, 0x0045044c, 0x00000000 }, { 0x00000801, 0x220c0128, 0x00000454, 0x00000000 }, { 0x01200010, 0x20003dac, 0x00000444, 0x00030003 }, { 0x01200010, 0x20003dac, 0x02000446, 0x00030003 }, { 0x00210040, 0x22002d08, 0x00450200, 0x00010001 }, { 0x00210040, 0x22002d08, 0x02450200, 0x00100010 }, { 0x00800001, 0xb8000229, 0x01ed8000, 0x00000000 }, { 0x00800001, 0xb8200229, 0x01ed8020, 0x00000000 }, { 0x00800001, 0xb8400229, 0x01ed8040, 0x00000000 }, { 0x00800001, 0xb8600229, 0x01ed8060, 0x00000000 }, { 0x80800042, 0xd8004631, 0x00d29800, 0x00d20480 }, { 0x80800042, 0xd8204631, 0x00d29820, 0x00d204a0 }, { 0x80800042, 0xd8404631, 0x00d29840, 0x00d204c0 }, { 0x80800042, 0xd8604631, 0x00d29860, 0x00d204e0 }, { 0x00600001, 0x220001ac, 0x008d0024, 0x00000000 }, { 0x00200040, 0x244c3dad, 0x00450448, 0xfff8fff8 }, { 0x00000401, 0x220001ec, 0x00000000, 0x07000700 }, { 0x00000c01, 0x220201e8, 0x00000000, 0x07100710 }, { 0x00000801, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00000441, 0x254635ad, 0x00000448, 0x0000044a }, { 0x00000c41, 0x254025ad, 0x0000444c, 0x0000444e }, { 0x00000c41, 0x254225ad, 0x00000448, 0x0000444e }, { 0x00000841, 0x254435ad, 0x0000444c, 0x0000044a }, { 0x00200040, 0x244c3d09, 0x00450200, 0x00100010 }, { 0x00800041, 0x24002628, 0x00ad8000, 0x00000540 }, { 0x00800041, 0x24202628, 0x00ad8020, 0x00000540 }, { 0x00800048, 0x24002628, 0x00ad8002, 0x00000542 }, { 0x00800048, 0x24202628, 0x00ad8022, 0x00000542 }, { 0x00200001, 0x22000128, 0x0045044c, 0x00000000 }, { 0x00800048, 0x24002628, 0x01ed8000, 0x00000544 }, { 0x00800048, 0x24202628, 0x01ed8020, 0x00000544 }, { 0x00800048, 0xbc002629, 0x01ed8002, 0x00000546 }, { 0x00801048, 0xbc202629, 0x01ed8022, 0x00000546 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000126 }, { 0x00000001, 0x20220169, 0x00000000, 0x00040004 }, { 0x00200005, 0x24443dad, 0x00459800, 0x00030003 }, { 0x0020000c, 0x24403dad, 0x00459800, 0x00020002 }, { 0x01600006, 0x20003dac, 0x02000446, 0x00000000 }, { 0x00010040, 0x22000c20, 0x02000078, 0x00200000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00500000 }, { 0x00310040, 0x20401da5, 0x02450440, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x00080008 }, { 0x00010040, 0x20401da5, 0x02000440, 0xfffffffe }, { 0x00010001, 0x204401a5, 0x02000442, 0x00000000 }, { 0x00010001, 0x20480061, 0x02000000, 0x00030008 }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000040, 0x22000c20, 0x00000078, 0x00100010 }, { 0x0020040c, 0x24403dad, 0x00459800, 0x00030003 }, { 0x00200805, 0x24483dad, 0x00459800, 0x00070007 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00000009, 0x20403ca5, 0x00000040, 0x00010001 }, { 0x00000001, 0x20480061, 0x00000000, 0x00020005 }, { 0x02600031, 0x27000021, 0x408d0040, 0x00000200 }, { 0x00110001, 0x220001ec, 0x02000000, 0x05820582 }, { 0x00010001, 0x220001ec, 0x02000000, 0x05620562 }, { 0x00000001, 0x220e0128, 0x00000454, 0x00000000 }, { 0x01800006, 0x200035ac, 0x02000446, 0x00000444 }, { 0x00410001, 0xbc000229, 0x02698000, 0x00000000 }, { 0x00410001, 0xbc100229, 0x02698010, 0x00000000 }, { 0x00410001, 0xbc200229, 0x02698020, 0x00000000 }, { 0x00410001, 0xbc300229, 0x02698030, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000be }, { 0x00600001, 0x2024018d, 0x008d0200, 0x00000000 }, { 0x01000041, 0x245e35ad, 0x00000446, 0x00000444 }, { 0x02000005, 0x20003db0, 0x0200045e, 0x00010001 }, { 0x00000040, 0x22022d08, 0x00000200, 0x00100010 }, { 0x00200040, 0x22042d08, 0x00450200, 0x00200020 }, { 0x00400001, 0x244c0109, 0x00690200, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000044 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000042 }, { 0x00000040, 0x22003d08, 0x00000200, 0xffdeffde }, { 0x00000440, 0x22023d08, 0x00000202, 0xffeeffee }, { 0x00000801, 0x220c0060, 0x00000000, 0x04d004c0 }, { 0x01000010, 0x20003db0, 0x0000045e, 0x00040004 }, { 0x00802040, 0x2400462c, 0x00a98000, 0x00a98005 }, { 0x00802048, 0x24003e2c, 0x00a98001, 0xfffbfffb }, { 0x00802048, 0x24003e2c, 0x00a98002, 0x00140014 }, { 0x00802048, 0x24003e2c, 0x00a98003, 0x00140014 }, { 0x00802048, 0xb8003e2d, 0x00a98004, 0xfffbfffb }, { 0x00802040, 0x2400462c, 0x00a98040, 0x00a98045 }, { 0x00802048, 0x24003e2c, 0x00a98041, 0xfffbfffb }, { 0x00802048, 0x24003e2c, 0x00a98042, 0x00140014 }, { 0x00802048, 0x24003e2c, 0x00a98043, 0x00140014 }, { 0x00802048, 0xb8203e2d, 0x00a98044, 0xfffbfffb }, { 0x00400040, 0x2400462c, 0x00698080, 0x00698085 }, { 0x00400048, 0x24003e2c, 0x00698081, 0xfffbfffb }, { 0x00400048, 0x24003e2c, 0x00698082, 0x00140014 }, { 0x00400048, 0x24003e2c, 0x00698083, 0x00140014 }, { 0x00400048, 0xb8403e2d, 0x00698084, 0xfffbfffb }, { 0x00000401, 0x220c0060, 0x00000000, 0x04e004d0 }, { 0x00000c01, 0x22000060, 0x00000000, 0x04d004c8 }, { 0x00000c01, 0x22040060, 0x00000000, 0x04e004d8 }, { 0x00000801, 0x22080060, 0x00000000, 0x04f004e8 }, { 0x00800040, 0x24003dac, 0x00b104c0, 0x02000200 }, { 0x00800048, 0x24003dac, 0x00b104e0, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed9800, 0x00140014 }, { 0x00010001, 0x220c0168, 0x00000000, 0x05400540 }, { 0x00110001, 0x220c0168, 0x00000000, 0x04c004c0 }, { 0x00800048, 0x24003dac, 0x01e98000, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01e98020, 0x00010001 }, { 0x00800048, 0x24003dac, 0x01e98800, 0x00140014 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x000a000a }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000060 }, { 0x01000010, 0x20003db0, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000022 }, { 0x00400040, 0x22003d28, 0x0069044c, 0xfffefffe }, { 0x03400010, 0x20003dac, 0x00000446, 0x00020002 }, { 0x01000010, 0x20003db0, 0x02000444, 0x00020002 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00100010 }, { 0x01000010, 0x20003dac, 0x00000446, 0x00000000 }, { 0x00010001, 0x220e0168, 0x02000000, 0x05400540 }, { 0x00110001, 0x220e0168, 0x02000000, 0x04c004c0 }, { 0x00800040, 0x24003e2c, 0x01e98000, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01e98001, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e98002, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98003, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98004, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e98005, 0x00010001 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00050005 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000036 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000036 }, { 0x01000010, 0x20003db0, 0x00000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x03600010, 0x20003dac, 0x02000444, 0x00020002 }, { 0x00400401, 0x22000128, 0x0069044c, 0x00000000 }, { 0x00400840, 0x22083d2c, 0x0069044c, 0x00100010 }, { 0x00610040, 0x22002d08, 0x02690200, 0x00010001 }, { 0x01000010, 0x20003dac, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00800040, 0x24003e2c, 0x01e983e0, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01e98000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98020, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e993e0, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e99000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e99020, 0x00010001 }, { 0x00000001, 0x220e0168, 0x00000000, 0x05400540 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00110001, 0x220e0168, 0x02000000, 0x04c004c0 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00050005 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000e }, { 0x00400001, 0x22000128, 0x0069044c, 0x00000000 }, { 0x01400010, 0x20003dac, 0x00000444, 0x00030003 }, { 0x01400010, 0x20003dac, 0x02000446, 0x00030003 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00010001 }, { 0x00410040, 0x22002d08, 0x02690200, 0x00100010 }, { 0x00800001, 0x25400229, 0x01e98000, 0x00000000 }, { 0x80800042, 0x45404631, 0x00d20540, 0x00d204c0 }, { 0x00000001, 0x220c0128, 0x00000454, 0x00000000 }, { 0x00400001, 0xd8000231, 0x008a0540, 0x00000000 }, { 0x00400001, 0xd8100231, 0x008a0548, 0x00000000 }, { 0x00400001, 0xd8200231, 0x008a0550, 0x00000000 }, { 0x00400001, 0xd8300231, 0x008a0558, 0x00000000 }, { 0x00600001, 0x220001ac, 0x008d0024, 0x00000000 }, { 0x00200040, 0x244c3dad, 0x00450448, 0xfff8fff8 }, { 0x00000401, 0x220001ec, 0x00000000, 0x07000700 }, { 0x00000801, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00000441, 0x254635ad, 0x00000448, 0x0000044a }, { 0x00000c41, 0x254025ad, 0x0000444c, 0x0000444e }, { 0x00000c41, 0x254225ad, 0x00000448, 0x0000444e }, { 0x00000841, 0x254435ad, 0x0000444c, 0x0000044a }, { 0x00600041, 0x24002628, 0x00898000, 0x00000540 }, { 0x00600048, 0x24002628, 0x00898002, 0x00000542 }, { 0x00600048, 0x24002628, 0x00898008, 0x00000544 }, { 0x00600048, 0x2540262d, 0x0089800a, 0x00000546 }, { 0x00400401, 0xbc0001a9, 0x00690540, 0x00000000 }, { 0x00400801, 0xbc1001a9, 0x00690548, 0x00000000 }, { 0x01000010, 0x20003d2c, 0x00000022, 0x00030003 }, { 0x01000040, 0x20223d29, 0x02000022, 0xffffffff }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0x00080008 }, { 0x00110040, 0x24540c21, 0x00000454, 0x00080008 }, { 0x00010040, 0x24540c21, 0x00000454, 0x00180038 }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffee6 }, { 0x01800010, 0x20003dac, 0x0200010e, 0x00010001 }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0xffe0ffe0 }, { 0x00010001, 0x24540061, 0x02000000, 0x06c00640 }, { 0x00110001, 0x24540061, 0x02000000, 0x04800780 }, { 0x00000001, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00800040, 0x24003dac, 0x00b19c00, 0x00200020 }, { 0x00800040, 0x24203dac, 0x00b19c20, 0x00200020 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00060006 }, { 0x8080000c, 0xdc203d91, 0x00b10420, 0x00060006 }, { 0x02000040, 0x210e3d29, 0x0200010e, 0xffffffff }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0x00040004 }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffcf8 }, { 0x01000005, 0x25643e2d, 0x00000060, 0x00c000c0 }, { 0x01000010, 0x20003dac, 0x02000458, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x01000010, 0x20003dac, 0x00000458, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00a02001, 0x46400231, 0x00d20780, 0x00000000 }, { 0x00a02001, 0x46800231, 0x00d207c0, 0x00000000 }, { 0x00a02001, 0x46c00231, 0x00d20480, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000007e }, { 0x80a02042, 0x46404631, 0x00d20640, 0x00d20780 }, { 0x80a02042, 0x46804631, 0x00d20680, 0x00d207c0 }, { 0x80a02042, 0x46c04631, 0x00d206c0, 0x00d20480 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000076 }, { 0x01000010, 0x20003dac, 0x02000564, 0x00800080 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000000e }, { 0x01000010, 0x20003dac, 0x00000458, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0xffffffe4 }, { 0x00200401, 0x256801ed, 0x00000000, 0x00200020 }, { 0x00200801, 0x256c01ed, 0x00000000, 0x00060006 }, { 0x00400001, 0x258001ed, 0x00000000, 0x00000000 }, { 0x00600001, 0x45a001ad, 0x00058c00, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000028 }, { 0x02600005, 0x20006e28, 0x02008c0c, 0x88848421 }, { 0x0220000c, 0x25663dad, 0x00000458, 0x00010001 }, { 0x0000000c, 0x25643dad, 0x00000564, 0x00060006 }, { 0x00310001, 0x25c401ad, 0x00000458, 0x00000000 }, { 0x00210001, 0x25c00061, 0x00000000, 0x00010001 }, { 0x00310040, 0x25c03dad, 0x004545c4, 0x00010001 }, { 0x00610001, 0x25a00061, 0x02000000, 0x00000080 }, { 0x00710001, 0x45a002ad, 0x02ae8c00, 0x00000000 }, { 0x00710001, 0x45a202ad, 0x02ae8c01, 0x00000000 }, { 0x00800041, 0x25a035ad, 0x00b105a0, 0x000905c0 }, { 0x01200010, 0x20003e2c, 0x0245006e, 0x00000000 }, { 0x00310009, 0x244c45ad, 0x02000564, 0x0045006e }, { 0x00210001, 0x244c01ed, 0x02000000, 0x00000000 }, { 0x0031000c, 0x244c3dad, 0x0245044c, 0x00010001 }, { 0x00200009, 0x256835ad, 0x0045044c, 0x00000566 }, { 0x00210040, 0x256835ad, 0x02450568, 0x00000566 }, { 0x00200040, 0x256c362d, 0x0045006e, 0x00000566 }, { 0x00400040, 0x240035ac, 0x00ab05a2, 0x00ab05a6 }, { 0x00400040, 0x2400358c, 0x00690400, 0x00000566 }, { 0x0040000c, 0x2580358d, 0x00690400, 0x00000566 }, { 0x00800041, 0x2400362c, 0x00d20640, 0x000005a0 }, { 0x00800041, 0x2420362c, 0x00d20660, 0x000005a0 }, { 0x00800048, 0x2400362c, 0x00d20780, 0x000005a4 }, { 0x00800048, 0x2420362c, 0x00d207a0, 0x000005a4 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00000568 }, { 0x00800040, 0x2420358c, 0x00b10420, 0x00000568 }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056c }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056c }, { 0x80800040, 0x464035b1, 0x00b104c0, 0x00000580 }, { 0x80800040, 0x466035b1, 0x00b104e0, 0x00000580 }, { 0x00800041, 0x2400362c, 0x00d20680, 0x000005a0 }, { 0x00800041, 0x2420362c, 0x00d206a0, 0x000005a0 }, { 0x00800048, 0x2400362c, 0x00d207c0, 0x000005a4 }, { 0x00800048, 0x2420362c, 0x00d207e0, 0x000005a4 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00000568 }, { 0x00800040, 0x2420358c, 0x00b10420, 0x00000568 }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056c }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056c }, { 0x80800040, 0x468035b1, 0x00b104c0, 0x00000580 }, { 0x80800040, 0x46a035b1, 0x00b104e0, 0x00000580 }, { 0x00800041, 0x2400362c, 0x00d206c0, 0x000705a8 }, { 0x00800041, 0x2420362c, 0x00d206e0, 0x000705a8 }, { 0x00800048, 0x2400362c, 0x00d20480, 0x000705ac }, { 0x00800048, 0x2420362c, 0x00d204a0, 0x000705ac }, { 0x00800040, 0x2400358c, 0x00b10400, 0x0000056a }, { 0x00800040, 0x2420358c, 0x00b10420, 0x0000056a }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056e }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056e }, { 0x80800040, 0x46c035b1, 0x00b104c0, 0x00050582 }, { 0x80800040, 0x46e035b1, 0x00b104e0, 0x00050582 }, { 0x01800005, 0x20003d2c, 0x02000020, 0x00020002 }, { 0x80800040, 0xd00045b1, 0x00b19000, 0x00d20640 }, { 0x80800040, 0xd02045b1, 0x00b19020, 0x00d20660 }, { 0x80800040, 0xd04045b1, 0x00b19040, 0x00d20680 }, { 0x80800040, 0xd06045b1, 0x00b19060, 0x00d206a0 }, { 0x00000040, 0x22083d8c, 0x00000208, 0x00800080 }, { 0x80400040, 0xd40045b1, 0x00699400, 0x00ab06c0 }, { 0x80400040, 0xd48045b1, 0x00699480, 0x00ab06c2 }, { 0x80400040, 0xd42045b1, 0x00699420, 0x00ab06e0 }, { 0x80400040, 0xd4a045b1, 0x006994a0, 0x00ab06e2 }, { 0x80400040, 0xd41045b1, 0x00699410, 0x00ab06d0 }, { 0x80400040, 0xd49045b1, 0x00699490, 0x00ab06d2 }, { 0x80400040, 0xd43045b1, 0x00699430, 0x00ab06f0 }, { 0x80400040, 0xd4b045b1, 0x006994b0, 0x00ab06f2 }, { 0x00000040, 0x220a3d8c, 0x0000020a, 0x00080008 }, { 0x00110040, 0x220a3d8c, 0x0200020a, 0x00300030 }, { 0x01000010, 0x20003d2c, 0x02000020, 0x00060006 }, { 0x00000040, 0x20203d29, 0x00000020, 0x00020002 }, { 0x00000040, 0x22040c00, 0x00000204, 0x00100001 }, { 0x00000040, 0x220c358c, 0x0000020c, 0x0000003a }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffc36 }, { 0x00000001, 0x220001ec, 0x00000000, 0x01400140 }, { 0x00000001, 0x220201ec, 0x00000000, 0x01c001c0 }, { 0x00800401, 0x20400236, 0x01ee8000, 0x00000000 }, { 0x00800801, 0x20500236, 0x01ee8010, 0x00000000 }, { 0x00800401, 0x20600236, 0x01ee8020, 0x00000000 }, { 0x00800801, 0x20700236, 0x01ee8030, 0x00000000 }, { 0x00800401, 0x20800236, 0x01ee8040, 0x00000000 }, { 0x00800801, 0x20900236, 0x01ee8050, 0x00000000 }, { 0x00800401, 0x20a00236, 0x01ee8060, 0x00000000 }, { 0x00800801, 0x20b00236, 0x01ee8070, 0x00000000 }, { 0x00800401, 0x20c00236, 0x01ee8100, 0x00000000 }, { 0x00800801, 0x20d00236, 0x01ee8110, 0x00000000 }, { 0x00800401, 0x20e00236, 0x01ee8120, 0x00000000 }, { 0x00800801, 0x20f00236, 0x01ee8130, 0x00000000 }, { 0x00800401, 0x21000236, 0x01ee8140, 0x00000000 }, { 0x00800801, 0x21100236, 0x01ee8150, 0x00000000 }, { 0x00800401, 0x21200236, 0x01ee8160, 0x00000000 }, { 0x00800801, 0x21300236, 0x01ee8170, 0x00000000 }, { 0x00200401, 0x204001a5, 0x00450064, 0x00000000 }, { 0x00000801, 0x20480061, 0x00000000, 0x000f000f }, { 0x01600031, 0x21401c21, 0x508d0040, 0x1218a000 }, { 0x00000001, 0x220001ec, 0x00000000, 0x03400340 }, { 0x00800401, 0x41600236, 0x00d28000, 0x00000000 }, { 0x00800801, 0x41610236, 0x00d28080, 0x00000000 }, { 0x00800401, 0x41800236, 0x00d28020, 0x00000000 }, { 0x00800801, 0x41810236, 0x00d280a0, 0x00000000 }, { 0x00800401, 0x41a00236, 0x00d28040, 0x00000000 }, { 0x00800801, 0x41a10236, 0x00d280c0, 0x00000000 }, { 0x00800401, 0x41c00236, 0x00d28060, 0x00000000 }, { 0x00800801, 0x41c10236, 0x00d280e0, 0x00000000 }, { 0x0000040c, 0x20443ca5, 0x00000044, 0x00010001 }, { 0x00000801, 0x20480061, 0x00000000, 0x0007000f }, { 0x0a600031, 0x21601c21, 0x508d0040, 0x0a18a001 }, { 0x00000001, 0x21400021, 0x00000140, 0x00000000 }, { 0x00000001, 0x21600021, 0x00000160, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00600001, 0x20400021, 0x008d0000, 0x00000000 }, { 0x00000005, 0x20203e2d, 0x00000061, 0x001f001f }, { 0x00200009, 0x20643e2d, 0x00450064, 0x00040004 }, { 0x00000001, 0x203a01ed, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000020, 0x00160016 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x01200010, 0x20003e2c, 0x0200006c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000024 }, { 0x00800009, 0x25403dad, 0x00050064, 0x00020002 }, { 0x00000001, 0x203a01ed, 0x00000000, 0x00180018 }, { 0x00200040, 0x45483dad, 0x00660548, 0x00100010 }, { 0x00200040, 0x45523dad, 0x00660552, 0x00100010 }, { 0x00400040, 0x25583dad, 0x00690558, 0x00100010 }, { 0x00800040, 0x208035ad, 0x00b10080, 0x00b10540 }, { 0x00600040, 0x45403dad, 0x00ae0540, 0x00200020 }, { 0x00800040, 0x20a035ad, 0x00b100a0, 0x00b10540 }, { 0x00600040, 0x45423dad, 0x00ae0542, 0x00200020 }, { 0x00800040, 0x20e035ad, 0x00b100e0, 0x00b10540 }, { 0x00600040, 0x45403dad, 0x00ae0540, 0xffe0ffe0 }, { 0x00800040, 0x20c035ad, 0x00b100c0, 0x00b10540 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000014 }, { 0x06600010, 0x20003dac, 0x02000020, 0x00030003 }, { 0x00000001, 0x206c0171, 0x00000000, 0x00000000 }, { 0x00610001, 0x208000a5, 0x02050080, 0x00000000 }, { 0x00610001, 0x212000a5, 0x02090100, 0x00000000 }, { 0x00410001, 0x211000a5, 0x02690100, 0x00000000 }, { 0x00200009, 0x25403dad, 0x00450064, 0x00020002 }, { 0x00800040, 0x208035ad, 0x00b10080, 0x00050540 }, { 0x00200040, 0x40883dad, 0x00660088, 0x00200020 }, { 0x00200040, 0x40923dad, 0x00660092, 0x00200020 }, { 0x00400040, 0x20983dad, 0x00690098, 0x00200020 }, { 0x00200401, 0x22080060, 0x00000000, 0x03400140 }, { 0x00000c01, 0x220c0060, 0x00000000, 0x04400080 }, { 0x00000801, 0x22040060, 0x00000000, 0x01000070 }, { 0x00000005, 0x203e2e29, 0x00000063, 0x00010001 }, { 0x00000001, 0x20200169, 0x00000000, 0x00000000 }, { 0x0000000c, 0x2458262d, 0x0000006d, 0x00000020 }, { 0x00000001, 0x210e0169, 0x00000000, 0x00010001 }, { 0x00000005, 0x24583dad, 0x00000458, 0x00030003 }, { 0x01000010, 0x200035ac, 0x0000010e, 0x00000458 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000316 }, { 0x01000010, 0x20003dac, 0x0200010e, 0x00010001 }, { 0x00010401, 0x24540061, 0x02000000, 0x06c00640 }, { 0x00010805, 0x245a3e2d, 0x02008800, 0x007f007f }, { 0x00110401, 0x24540061, 0x02000000, 0x04800780 }, { 0x00110805, 0x245a3e2d, 0x02008804, 0x007f007f }, { 0x00010005, 0x245c3e2d, 0x02008800, 0x00800080 }, { 0x00110005, 0x245c3e2d, 0x02008804, 0x00800080 }, { 0x00000009, 0x245c3dad, 0x0000045c, 0x00010001 }, { 0x0000000c, 0x211e362d, 0x0000006c, 0x00000020 }, { 0x00000040, 0x240035ac, 0x0000003e, 0x0000045c }, { 0x01000010, 0x20003d8c, 0x00210400, 0x00010001 }, { 0x01000010, 0x20003d8c, 0x02210400, 0x01000100 }, { 0x00000001, 0x203c01ed, 0x00000000, 0x00000000 }, { 0x00010001, 0x203c01ed, 0x00000000, 0x00020002 }, { 0x00010001, 0x203c01ed, 0x02000000, 0xfffefffe }, { 0x00000040, 0x20780d21, 0x0000045a, 0x0208e602 }, { 0x00000040, 0x20782421, 0x00000078, 0x0000045c }, { 0x02000005, 0x20003dac, 0x0200011e, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000001c0 }, { 0x01000005, 0x20003dac, 0x00009800, 0x00030003 }, { 0x00200005, 0x24443dad, 0x00459800, 0x00030003 }, { 0x0020000c, 0x24403dad, 0x00459800, 0x00020002 }, { 0x01600006, 0x20003dac, 0x02000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00010040, 0x22000c20, 0x02000078, 0x00400000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00700000 }, { 0x00310040, 0x20401da5, 0x02450440, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x000c000c }, { 0x00010040, 0x20401da5, 0x02000440, 0xfffffffe }, { 0x00010001, 0x204401a5, 0x02000442, 0x00000000 }, { 0x00010001, 0x20480061, 0x02000000, 0x0007000c }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00010040, 0x22000c20, 0x02000078, 0x00200000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00400000 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00110040, 0x20441da5, 0x02000442, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x000c0007 }, { 0x00010001, 0x20480061, 0x02000000, 0x00070007 }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000040, 0xb80235ad, 0x00009802, 0x0000003c }, { 0x0020040c, 0x24403dad, 0x00459800, 0x00030003 }, { 0x00200805, 0x24483dad, 0x00459800, 0x00070007 }, { 0x01600006, 0x20003dac, 0x0000044a, 0x00000000 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00000009, 0x20403ca5, 0x00000040, 0x00010001 }, { 0x00010040, 0x22000c20, 0x00000078, 0x00200010 }, { 0x00110040, 0x22000c20, 0x00000078, 0x00300010 }, { 0x00010001, 0x20480061, 0x00000000, 0x00030009 }, { 0x00110001, 0x20480061, 0x00000000, 0x00040009 }, { 0x02600031, 0x27000021, 0x408d0040, 0x00000200 }, { 0x01000005, 0x20003dac, 0x00009800, 0x00030003 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00600001, 0x26220231, 0x008d05c0, 0x00000000 }, { 0x00600401, 0x26120231, 0x008d05b8, 0x00000000 }, { 0x00600801, 0x26020231, 0x008d05b0, 0x00000000 }, { 0x00600401, 0x25f20231, 0x008d05a8, 0x00000000 }, { 0x00600801, 0x25e20231, 0x008d05a0, 0x00000000 }, { 0x00600401, 0x25d20231, 0x008d0598, 0x00000000 }, { 0x00600801, 0x25c20231, 0x008d0590, 0x00000000 }, { 0x00600401, 0x25b20231, 0x008d0588, 0x00000000 }, { 0x00600801, 0x25a20231, 0x008d0580, 0x00000000 }, { 0x00600401, 0x25920231, 0x008d0578, 0x00000000 }, { 0x00600801, 0x25820231, 0x008d0570, 0x00000000 }, { 0x00600001, 0x25720231, 0x008d0568, 0x00000000 }, { 0x00600001, 0x25620231, 0x008d0560, 0x00000000 }, { 0x00110001, 0x220001ec, 0x02000000, 0x05820582 }, { 0x00010001, 0x220001ec, 0x02000000, 0x05620562 }, { 0x00000001, 0x220e0128, 0x00000454, 0x00000000 }, { 0x01800006, 0x200035ac, 0x02000446, 0x00000444 }, { 0x00810001, 0xbc000229, 0x02ad8000, 0x00000000 }, { 0x00810001, 0xbc200229, 0x02ad8020, 0x00000000 }, { 0x00810001, 0xbc400229, 0x02ad8040, 0x00000000 }, { 0x00810001, 0xbc600229, 0x02ad8060, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000012a }, { 0x00600001, 0x2024018d, 0x008d0200, 0x00000000 }, { 0x01000041, 0x245e35ad, 0x00000446, 0x00000444 }, { 0x00000040, 0x22022d08, 0x00000200, 0x00100010 }, { 0x02000005, 0x20003db0, 0x0200045e, 0x00010001 }, { 0x00200040, 0x22042d08, 0x00450200, 0x00200020 }, { 0x00400001, 0x244c0109, 0x00690200, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000066 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000064 }, { 0x00000040, 0x22003d08, 0x00000200, 0xffdeffde }, { 0x00000440, 0x22023d08, 0x00000202, 0xffeeffee }, { 0x00000801, 0x220c0060, 0x00000000, 0x04a00480 }, { 0x01000010, 0x20003db0, 0x0000045e, 0x00040004 }, { 0x00a02040, 0x2400462c, 0x00ad8000, 0x00ad8005 }, { 0x00a02048, 0x24003e2c, 0x00ad8001, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8002, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8003, 0x00140014 }, { 0x00a02048, 0xb8003e2d, 0x00ad8004, 0xfffbfffb }, { 0x00a02040, 0x2400462c, 0x00ad8040, 0x00ad8045 }, { 0x00a02048, 0x24003e2c, 0x00ad8041, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8042, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8043, 0x00140014 }, { 0x00a02048, 0xb8403e2d, 0x00ad8044, 0xfffbfffb }, { 0x00a02040, 0x2400462c, 0x00ad8080, 0x00ad8085 }, { 0x00a02048, 0x24003e2c, 0x00ad8081, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8082, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8083, 0x00140014 }, { 0x00a02048, 0xb8803e2d, 0x00ad8084, 0xfffbfffb }, { 0x00600040, 0x2400462c, 0x008d80c0, 0x008d80c5 }, { 0x00600048, 0x24003e2c, 0x008d80c1, 0xfffbfffb }, { 0x00600048, 0x24003e2c, 0x008d80c2, 0x00140014 }, { 0x00600048, 0x24003e2c, 0x008d80c3, 0x00140014 }, { 0x00600048, 0xb8c03e2d, 0x008d80c4, 0xfffbfffb }, { 0x00000401, 0x22000060, 0x00000000, 0x04a00480 }, { 0x00000c01, 0x22040060, 0x00000000, 0x04a00490 }, { 0x00010802, 0x220c2d28, 0x00000454, 0x04800480 }, { 0x00a02040, 0x24003dac, 0x00b18000, 0x02000200 }, { 0x00800048, 0x24003dac, 0x01ed8800, 0xfffbfffb }, { 0x00800048, 0x24203dac, 0x01ed8820, 0xfffbfffb }, { 0x00a02048, 0x24003dac, 0x00b18020, 0x00140014 }, { 0x00800048, 0x24003dac, 0x01ed8820, 0x00140014 }, { 0x00800048, 0x24203dac, 0x01ed8840, 0x00140014 }, { 0x00a02048, 0x24003dac, 0x00b18040, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed8840, 0x00010001 }, { 0x00800048, 0x24203dac, 0x01ed8860, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x000a000a }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x000a000a }, { 0x00a02040, 0x24003dac, 0x00b18040, 0x02000200 }, { 0x00800048, 0x24003dac, 0x01ed8840, 0xfffbfffb }, { 0x00800048, 0x24203dac, 0x01ed8860, 0xfffbfffb }, { 0x00a02048, 0x24003dac, 0x00b18060, 0x00140014 }, { 0x00800048, 0x24003dac, 0x01ed8860, 0x00140014 }, { 0x00800048, 0x24203dac, 0x01ed8880, 0x00140014 }, { 0x00a02048, 0x24003dac, 0x00b18080, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed8880, 0x00010001 }, { 0x00800048, 0x24203dac, 0x01ed88a0, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x000a000a }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x000a000a }, { 0x00010220, 0x34001c00, 0x00001400, 0x000000b4 }, { 0x01000010, 0x20003db0, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000004c }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000004a }, { 0x00400040, 0x22003d28, 0x0069044c, 0xfffefffe }, { 0x03400010, 0x20003dac, 0x00000446, 0x00020002 }, { 0x01000010, 0x20003db0, 0x02000444, 0x00020002 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00100010 }, { 0x01000010, 0x20003dac, 0x00000446, 0x00000000 }, { 0x00010002, 0x220c2d28, 0x02000454, 0x04800480 }, { 0x00800040, 0x24003e2c, 0x01ed8000, 0x00100010 }, { 0x00800040, 0x24203e2c, 0x01ed8020, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8001, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8021, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8002, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8022, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8003, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8023, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8004, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8024, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8005, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8025, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x00050005 }, { 0x00800040, 0x24003e2c, 0x01ed8040, 0x00100010 }, { 0x00800040, 0x24203e2c, 0x01ed8060, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8041, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8061, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8042, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8062, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8043, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8063, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8044, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8064, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8045, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8065, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x00050005 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000005c }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000062 }, { 0x01000010, 0x20003db0, 0x00000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000042 }, { 0x00200401, 0x22000128, 0x0066044c, 0x00000000 }, { 0x00200c01, 0x22040128, 0x0045044e, 0x00000000 }, { 0x00000801, 0x220c0128, 0x00000454, 0x00000000 }, { 0x03400010, 0x20003dac, 0x02000444, 0x00020002 }, { 0x01000010, 0x20003dac, 0x00000444, 0x00000000 }, { 0x00410040, 0x22002d08, 0x02690200, 0x00010001 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00110001, 0x220c0168, 0x02000000, 0x04800480 }, { 0x00a02040, 0x24003e2c, 0x00ad83e0, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8be0, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8800, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8800, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8820, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8020, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8820, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8840, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x00050005 }, { 0x00a02040, 0x24003e2c, 0x00ad8020, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8820, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8840, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8040, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8840, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8860, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8060, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8860, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8880, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x00050005 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001c }, { 0x00200401, 0x22000128, 0x0045044c, 0x00000000 }, { 0x00000801, 0x220c0128, 0x00000454, 0x00000000 }, { 0x01200010, 0x20003dac, 0x00000444, 0x00030003 }, { 0x01200010, 0x20003dac, 0x02000446, 0x00030003 }, { 0x00210040, 0x22002d08, 0x00450200, 0x00010001 }, { 0x00210040, 0x22002d08, 0x02450200, 0x00100010 }, { 0x00800001, 0xb8000229, 0x01ed8000, 0x00000000 }, { 0x00800001, 0xb8200229, 0x01ed8020, 0x00000000 }, { 0x00800001, 0xb8400229, 0x01ed8040, 0x00000000 }, { 0x00800001, 0xb8600229, 0x01ed8060, 0x00000000 }, { 0x80800042, 0xd8004631, 0x00d29800, 0x00d20480 }, { 0x80800042, 0xd8204631, 0x00d29820, 0x00d204a0 }, { 0x80800042, 0xd8404631, 0x00d29840, 0x00d204c0 }, { 0x80800042, 0xd8604631, 0x00d29860, 0x00d204e0 }, { 0x00600001, 0x220001ac, 0x008d0024, 0x00000000 }, { 0x00200040, 0x244c3dad, 0x00450448, 0xfff8fff8 }, { 0x00000401, 0x220001ec, 0x00000000, 0x07000700 }, { 0x00000c01, 0x220201e8, 0x00000000, 0x07100710 }, { 0x00000801, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00000441, 0x254635ad, 0x00000448, 0x0000044a }, { 0x00000c41, 0x254025ad, 0x0000444c, 0x0000444e }, { 0x00000c41, 0x254225ad, 0x00000448, 0x0000444e }, { 0x00000841, 0x254435ad, 0x0000444c, 0x0000044a }, { 0x00200040, 0x244c3d09, 0x00450200, 0x00100010 }, { 0x00800041, 0x24002628, 0x00ad8000, 0x00000540 }, { 0x00800041, 0x24202628, 0x00ad8020, 0x00000540 }, { 0x00800048, 0x24002628, 0x00ad8002, 0x00000542 }, { 0x00800048, 0x24202628, 0x00ad8022, 0x00000542 }, { 0x00200001, 0x22000128, 0x0045044c, 0x00000000 }, { 0x00800048, 0x24002628, 0x01ed8000, 0x00000544 }, { 0x00800048, 0x24202628, 0x01ed8020, 0x00000544 }, { 0x00800048, 0xbc002629, 0x01ed8002, 0x00000546 }, { 0x00801048, 0xbc202629, 0x01ed8022, 0x00000546 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000128 }, { 0x00000001, 0x20220169, 0x00000000, 0x00040004 }, { 0x00200005, 0x24443dad, 0x00459800, 0x00030003 }, { 0x0020000c, 0x24403dad, 0x00459800, 0x00020002 }, { 0x01600006, 0x20003dac, 0x02000446, 0x00000000 }, { 0x00010040, 0x22000c20, 0x02000078, 0x00200000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00500000 }, { 0x00310040, 0x20401da5, 0x02450440, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x00080008 }, { 0x00010040, 0x20401da5, 0x02000440, 0xfffffffe }, { 0x00010001, 0x204401a5, 0x02000442, 0x00000000 }, { 0x00010001, 0x20480061, 0x02000000, 0x00030008 }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000040, 0xb80235ad, 0x00009802, 0x0000003c }, { 0x00000040, 0x22000c20, 0x00000078, 0x00100010 }, { 0x0020040c, 0x24403dad, 0x00459800, 0x00030003 }, { 0x00200805, 0x24483dad, 0x00459800, 0x00070007 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00000009, 0x20403ca5, 0x00000040, 0x00010001 }, { 0x00000001, 0x20480061, 0x00000000, 0x00020005 }, { 0x02600031, 0x27000021, 0x408d0040, 0x00000200 }, { 0x00110001, 0x220001ec, 0x02000000, 0x05820582 }, { 0x00010001, 0x220001ec, 0x02000000, 0x05620562 }, { 0x00000001, 0x220e0128, 0x00000454, 0x00000000 }, { 0x01800006, 0x200035ac, 0x02000446, 0x00000444 }, { 0x00410001, 0xbc000229, 0x02698000, 0x00000000 }, { 0x00410001, 0xbc100229, 0x02698010, 0x00000000 }, { 0x00410001, 0xbc200229, 0x02698020, 0x00000000 }, { 0x00410001, 0xbc300229, 0x02698030, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000be }, { 0x00600001, 0x2024018d, 0x008d0200, 0x00000000 }, { 0x01000041, 0x245e35ad, 0x00000446, 0x00000444 }, { 0x02000005, 0x20003db0, 0x0200045e, 0x00010001 }, { 0x00000040, 0x22022d08, 0x00000200, 0x00100010 }, { 0x00200040, 0x22042d08, 0x00450200, 0x00200020 }, { 0x00400001, 0x244c0109, 0x00690200, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000044 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000042 }, { 0x00000040, 0x22003d08, 0x00000200, 0xffdeffde }, { 0x00000440, 0x22023d08, 0x00000202, 0xffeeffee }, { 0x00000801, 0x220c0060, 0x00000000, 0x04d004c0 }, { 0x01000010, 0x20003db0, 0x0000045e, 0x00040004 }, { 0x00802040, 0x2400462c, 0x00a98000, 0x00a98005 }, { 0x00802048, 0x24003e2c, 0x00a98001, 0xfffbfffb }, { 0x00802048, 0x24003e2c, 0x00a98002, 0x00140014 }, { 0x00802048, 0x24003e2c, 0x00a98003, 0x00140014 }, { 0x00802048, 0xb8003e2d, 0x00a98004, 0xfffbfffb }, { 0x00802040, 0x2400462c, 0x00a98040, 0x00a98045 }, { 0x00802048, 0x24003e2c, 0x00a98041, 0xfffbfffb }, { 0x00802048, 0x24003e2c, 0x00a98042, 0x00140014 }, { 0x00802048, 0x24003e2c, 0x00a98043, 0x00140014 }, { 0x00802048, 0xb8203e2d, 0x00a98044, 0xfffbfffb }, { 0x00400040, 0x2400462c, 0x00698080, 0x00698085 }, { 0x00400048, 0x24003e2c, 0x00698081, 0xfffbfffb }, { 0x00400048, 0x24003e2c, 0x00698082, 0x00140014 }, { 0x00400048, 0x24003e2c, 0x00698083, 0x00140014 }, { 0x00400048, 0xb8403e2d, 0x00698084, 0xfffbfffb }, { 0x00000401, 0x220c0060, 0x00000000, 0x04e004d0 }, { 0x00000c01, 0x22000060, 0x00000000, 0x04d004c8 }, { 0x00000c01, 0x22040060, 0x00000000, 0x04e004d8 }, { 0x00000801, 0x22080060, 0x00000000, 0x04f004e8 }, { 0x00800040, 0x24003dac, 0x00b104c0, 0x02000200 }, { 0x00800048, 0x24003dac, 0x00b104e0, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed9800, 0x00140014 }, { 0x00010001, 0x220c0168, 0x00000000, 0x05400540 }, { 0x00110001, 0x220c0168, 0x00000000, 0x04c004c0 }, { 0x00800048, 0x24003dac, 0x01e98000, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01e98020, 0x00010001 }, { 0x00800048, 0x24003dac, 0x01e98800, 0x00140014 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x000a000a }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000060 }, { 0x01000010, 0x20003db0, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000022 }, { 0x00400040, 0x22003d28, 0x0069044c, 0xfffefffe }, { 0x03400010, 0x20003dac, 0x00000446, 0x00020002 }, { 0x01000010, 0x20003db0, 0x02000444, 0x00020002 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00100010 }, { 0x01000010, 0x20003dac, 0x00000446, 0x00000000 }, { 0x00010001, 0x220e0168, 0x02000000, 0x05400540 }, { 0x00110001, 0x220e0168, 0x02000000, 0x04c004c0 }, { 0x00800040, 0x24003e2c, 0x01e98000, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01e98001, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e98002, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98003, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98004, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e98005, 0x00010001 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00050005 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000036 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000036 }, { 0x01000010, 0x20003db0, 0x00000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x03600010, 0x20003dac, 0x02000444, 0x00020002 }, { 0x00400401, 0x22000128, 0x0069044c, 0x00000000 }, { 0x00400840, 0x22083d2c, 0x0069044c, 0x00100010 }, { 0x00610040, 0x22002d08, 0x02690200, 0x00010001 }, { 0x01000010, 0x20003dac, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00800040, 0x24003e2c, 0x01e983e0, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01e98000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98020, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e993e0, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e99000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e99020, 0x00010001 }, { 0x00000001, 0x220e0168, 0x00000000, 0x05400540 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00110001, 0x220e0168, 0x02000000, 0x04c004c0 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00050005 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000e }, { 0x00400001, 0x22000128, 0x0069044c, 0x00000000 }, { 0x01400010, 0x20003dac, 0x00000444, 0x00030003 }, { 0x01400010, 0x20003dac, 0x02000446, 0x00030003 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00010001 }, { 0x00410040, 0x22002d08, 0x02690200, 0x00100010 }, { 0x00800001, 0x25400229, 0x01e98000, 0x00000000 }, { 0x80800042, 0x45404631, 0x00d20540, 0x00d204c0 }, { 0x00000001, 0x220c0128, 0x00000454, 0x00000000 }, { 0x00400001, 0xd8000231, 0x008a0540, 0x00000000 }, { 0x00400001, 0xd8100231, 0x008a0548, 0x00000000 }, { 0x00400001, 0xd8200231, 0x008a0550, 0x00000000 }, { 0x00400001, 0xd8300231, 0x008a0558, 0x00000000 }, { 0x00600001, 0x220001ac, 0x008d0024, 0x00000000 }, { 0x00200040, 0x244c3dad, 0x00450448, 0xfff8fff8 }, { 0x00000401, 0x220001ec, 0x00000000, 0x07000700 }, { 0x00000801, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00000441, 0x254635ad, 0x00000448, 0x0000044a }, { 0x00000c41, 0x254025ad, 0x0000444c, 0x0000444e }, { 0x00000c41, 0x254225ad, 0x00000448, 0x0000444e }, { 0x00000841, 0x254435ad, 0x0000444c, 0x0000044a }, { 0x00600041, 0x24002628, 0x00898000, 0x00000540 }, { 0x00600048, 0x24002628, 0x00898002, 0x00000542 }, { 0x00600048, 0x24002628, 0x00898008, 0x00000544 }, { 0x00600048, 0x2540262d, 0x0089800a, 0x00000546 }, { 0x00400401, 0xbc0001a9, 0x00690540, 0x00000000 }, { 0x00400801, 0xbc1001a9, 0x00690548, 0x00000000 }, { 0x01000010, 0x20003d2c, 0x00000022, 0x00030003 }, { 0x01000040, 0x20223d29, 0x02000022, 0xffffffff }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0x00080008 }, { 0x00110040, 0x24540c21, 0x00000454, 0x00080008 }, { 0x00010040, 0x24540c21, 0x00000454, 0x00180038 }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffee4 }, { 0x01800010, 0x20003dac, 0x0200010e, 0x00010001 }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0xffe0ffe0 }, { 0x00010001, 0x24540061, 0x02000000, 0x06c00640 }, { 0x00110001, 0x24540061, 0x02000000, 0x04800780 }, { 0x00000001, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00800040, 0x24003dac, 0x00b19c00, 0x00200020 }, { 0x00800040, 0x24203dac, 0x00b19c20, 0x00200020 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00060006 }, { 0x8080000c, 0xdc203d91, 0x00b10420, 0x00060006 }, { 0x02000040, 0x210e3d29, 0x0200010e, 0xffffffff }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0x00040004 }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffce0 }, { 0x01000005, 0x25643e2d, 0x00000060, 0x00c000c0 }, { 0x01000010, 0x20003dac, 0x02000458, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x01000010, 0x20003dac, 0x00000458, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00a02001, 0x46400231, 0x00d20780, 0x00000000 }, { 0x00a02001, 0x46800231, 0x00d207c0, 0x00000000 }, { 0x00a02001, 0x46c00231, 0x00d20480, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000007e }, { 0x80a02042, 0x46404631, 0x00d20640, 0x00d20780 }, { 0x80a02042, 0x46804631, 0x00d20680, 0x00d207c0 }, { 0x80a02042, 0x46c04631, 0x00d206c0, 0x00d20480 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000076 }, { 0x01000010, 0x20003dac, 0x02000564, 0x00800080 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000000e }, { 0x01000010, 0x20003dac, 0x00000458, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0xffffffe4 }, { 0x00200401, 0x256801ed, 0x00000000, 0x00200020 }, { 0x00200801, 0x256c01ed, 0x00000000, 0x00060006 }, { 0x00400001, 0x258001ed, 0x00000000, 0x00000000 }, { 0x00600001, 0x45a001ad, 0x00058c00, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000028 }, { 0x02600005, 0x20006e28, 0x02008c0c, 0x88848421 }, { 0x0220000c, 0x25663dad, 0x00000458, 0x00010001 }, { 0x0000000c, 0x25643dad, 0x00000564, 0x00060006 }, { 0x00310001, 0x25c401ad, 0x00000458, 0x00000000 }, { 0x00210001, 0x25c00061, 0x00000000, 0x00010001 }, { 0x00310040, 0x25c03dad, 0x004545c4, 0x00010001 }, { 0x00610001, 0x25a00061, 0x02000000, 0x00000080 }, { 0x00710001, 0x45a002ad, 0x02ae8c00, 0x00000000 }, { 0x00710001, 0x45a202ad, 0x02ae8c01, 0x00000000 }, { 0x00800041, 0x25a035ad, 0x00b105a0, 0x000905c0 }, { 0x01200010, 0x20003e2c, 0x0245006e, 0x00000000 }, { 0x00310009, 0x244c45ad, 0x02000564, 0x0045006e }, { 0x00210001, 0x244c01ed, 0x02000000, 0x00000000 }, { 0x0031000c, 0x244c3dad, 0x0245044c, 0x00010001 }, { 0x00200009, 0x256835ad, 0x0045044c, 0x00000566 }, { 0x00210040, 0x256835ad, 0x02450568, 0x00000566 }, { 0x00200040, 0x256c362d, 0x0045006e, 0x00000566 }, { 0x00400040, 0x240035ac, 0x00ab05a2, 0x00ab05a6 }, { 0x00400040, 0x2400358c, 0x00690400, 0x00000566 }, { 0x0040000c, 0x2580358d, 0x00690400, 0x00000566 }, { 0x00800041, 0x2400362c, 0x00d20640, 0x000005a0 }, { 0x00800041, 0x2420362c, 0x00d20660, 0x000005a0 }, { 0x00800048, 0x2400362c, 0x00d20780, 0x000005a4 }, { 0x00800048, 0x2420362c, 0x00d207a0, 0x000005a4 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00000568 }, { 0x00800040, 0x2420358c, 0x00b10420, 0x00000568 }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056c }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056c }, { 0x80800040, 0x464035b1, 0x00b104c0, 0x00000580 }, { 0x80800040, 0x466035b1, 0x00b104e0, 0x00000580 }, { 0x00800041, 0x2400362c, 0x00d20680, 0x000005a0 }, { 0x00800041, 0x2420362c, 0x00d206a0, 0x000005a0 }, { 0x00800048, 0x2400362c, 0x00d207c0, 0x000005a4 }, { 0x00800048, 0x2420362c, 0x00d207e0, 0x000005a4 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00000568 }, { 0x00800040, 0x2420358c, 0x00b10420, 0x00000568 }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056c }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056c }, { 0x80800040, 0x468035b1, 0x00b104c0, 0x00000580 }, { 0x80800040, 0x46a035b1, 0x00b104e0, 0x00000580 }, { 0x00800041, 0x2400362c, 0x00d206c0, 0x000705a8 }, { 0x00800041, 0x2420362c, 0x00d206e0, 0x000705a8 }, { 0x00800048, 0x2400362c, 0x00d20480, 0x000705ac }, { 0x00800048, 0x2420362c, 0x00d204a0, 0x000705ac }, { 0x00800040, 0x2400358c, 0x00b10400, 0x0000056a }, { 0x00800040, 0x2420358c, 0x00b10420, 0x0000056a }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056e }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056e }, { 0x80800040, 0x46c035b1, 0x00b104c0, 0x00050582 }, { 0x80800040, 0x46e035b1, 0x00b104e0, 0x00050582 }, { 0x01800005, 0x20003d2c, 0x02000020, 0x00020002 }, { 0x80800040, 0xd00045b1, 0x00b19000, 0x00d20640 }, { 0x80800040, 0xd02045b1, 0x00b19020, 0x00d20660 }, { 0x80800040, 0xd04045b1, 0x00b19040, 0x00d20680 }, { 0x80800040, 0xd06045b1, 0x00b19060, 0x00d206a0 }, { 0x00000040, 0x22083d8c, 0x00000208, 0x00800080 }, { 0x80400040, 0xd40045b1, 0x00699400, 0x00ab06c0 }, { 0x80400040, 0xd48045b1, 0x00699480, 0x00ab06c2 }, { 0x80400040, 0xd42045b1, 0x00699420, 0x00ab06e0 }, { 0x80400040, 0xd4a045b1, 0x006994a0, 0x00ab06e2 }, { 0x80400040, 0xd41045b1, 0x00699410, 0x00ab06d0 }, { 0x80400040, 0xd49045b1, 0x00699490, 0x00ab06d2 }, { 0x80400040, 0xd43045b1, 0x00699430, 0x00ab06f0 }, { 0x80400040, 0xd4b045b1, 0x006994b0, 0x00ab06f2 }, { 0x00000040, 0x220a3d8c, 0x0000020a, 0x00080008 }, { 0x00110040, 0x220a3d8c, 0x0200020a, 0x00300030 }, { 0x01000010, 0x20003d2c, 0x02000020, 0x00060006 }, { 0x00000040, 0x20203d29, 0x00000020, 0x00020002 }, { 0x00000040, 0x22040c00, 0x00000204, 0x00100001 }, { 0x00000040, 0x220c358c, 0x0000020c, 0x0000003a }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffc1e }, { 0x00000001, 0x220001ec, 0x00000000, 0x01400140 }, { 0x00000001, 0x220201ec, 0x00000000, 0x01c001c0 }, { 0x00800401, 0x20400236, 0x01ee8000, 0x00000000 }, { 0x00800801, 0x20500236, 0x01ee8010, 0x00000000 }, { 0x00800401, 0x20600236, 0x01ee8020, 0x00000000 }, { 0x00800801, 0x20700236, 0x01ee8030, 0x00000000 }, { 0x00800401, 0x20800236, 0x01ee8040, 0x00000000 }, { 0x00800801, 0x20900236, 0x01ee8050, 0x00000000 }, { 0x00800401, 0x20a00236, 0x01ee8060, 0x00000000 }, { 0x00800801, 0x20b00236, 0x01ee8070, 0x00000000 }, { 0x00800401, 0x20c00236, 0x01ee8100, 0x00000000 }, { 0x00800801, 0x20d00236, 0x01ee8110, 0x00000000 }, { 0x00800401, 0x20e00236, 0x01ee8120, 0x00000000 }, { 0x00800801, 0x20f00236, 0x01ee8130, 0x00000000 }, { 0x00800401, 0x21000236, 0x01ee8140, 0x00000000 }, { 0x00800801, 0x21100236, 0x01ee8150, 0x00000000 }, { 0x00800401, 0x21200236, 0x01ee8160, 0x00000000 }, { 0x00800801, 0x21300236, 0x01ee8170, 0x00000000 }, { 0x00000040, 0x22000d20, 0x00000062, 0x1218a600 }, { 0x00200401, 0x204001a5, 0x00450064, 0x00000000 }, { 0x00000801, 0x20480061, 0x00000000, 0x000f000f }, { 0x01600031, 0x21400021, 0x508d0040, 0x00000200 }, { 0x00000001, 0x220001ec, 0x00000000, 0x03400340 }, { 0x00800401, 0x41600236, 0x00d28000, 0x00000000 }, { 0x00800801, 0x41610236, 0x00d28080, 0x00000000 }, { 0x00800401, 0x41800236, 0x00d28020, 0x00000000 }, { 0x00800801, 0x41810236, 0x00d280a0, 0x00000000 }, { 0x00800401, 0x41a00236, 0x00d28040, 0x00000000 }, { 0x00800801, 0x41a10236, 0x00d280c0, 0x00000000 }, { 0x00800401, 0x41c00236, 0x00d28060, 0x00000000 }, { 0x00800801, 0x41c10236, 0x00d280e0, 0x00000000 }, { 0x00000040, 0x22000d20, 0x00000062, 0x0a18a601 }, { 0x0000040c, 0x20443ca5, 0x00000044, 0x00010001 }, { 0x00000801, 0x20480061, 0x00000000, 0x0007000f }, { 0x0a600031, 0x21600021, 0x508d0040, 0x00000200 }, { 0x00000001, 0x21400021, 0x00000140, 0x00000000 }, { 0x00000001, 0x21600021, 0x00000160, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0000, 0x00000000 }, { 0x00000005, 0x20203e2d, 0x00000061, 0x001f001f }, { 0x00200009, 0x20643e2d, 0x00450064, 0x00040004 }, { 0x00000001, 0x203a01ed, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000020, 0x00160016 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x01200010, 0x20003e2c, 0x0200006c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000024 }, { 0x00800009, 0x25403dad, 0x00050064, 0x00020002 }, { 0x00000001, 0x203a01ed, 0x00000000, 0x00180018 }, { 0x00200040, 0x45483dad, 0x00660548, 0x00100010 }, { 0x00200040, 0x45523dad, 0x00660552, 0x00100010 }, { 0x00400040, 0x25583dad, 0x00690558, 0x00100010 }, { 0x00800040, 0x208035ad, 0x00b10080, 0x00b10540 }, { 0x00600040, 0x45403dad, 0x00ae0540, 0x00200020 }, { 0x00800040, 0x20a035ad, 0x00b100a0, 0x00b10540 }, { 0x00600040, 0x45423dad, 0x00ae0542, 0x00200020 }, { 0x00800040, 0x20e035ad, 0x00b100e0, 0x00b10540 }, { 0x00600040, 0x45403dad, 0x00ae0540, 0xffe0ffe0 }, { 0x00800040, 0x20c035ad, 0x00b100c0, 0x00b10540 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000014 }, { 0x06600010, 0x20003dac, 0x02000020, 0x00030003 }, { 0x00000001, 0x206c0171, 0x00000000, 0x00000000 }, { 0x00610001, 0x208000a5, 0x02050080, 0x00000000 }, { 0x00610001, 0x212000a5, 0x02090100, 0x00000000 }, { 0x00410001, 0x211000a5, 0x02690100, 0x00000000 }, { 0x00200009, 0x25403dad, 0x00450064, 0x00020002 }, { 0x00800040, 0x208035ad, 0x00b10080, 0x00050540 }, { 0x00200040, 0x40883dad, 0x00660088, 0x00200020 }, { 0x00200040, 0x40923dad, 0x00660092, 0x00200020 }, { 0x00400040, 0x20983dad, 0x00690098, 0x00200020 }, { 0x00200401, 0x22080060, 0x00000000, 0x03400140 }, { 0x00000c01, 0x220c0060, 0x00000000, 0x04400080 }, { 0x00000801, 0x22040060, 0x00000000, 0x01000070 }, { 0x02000005, 0x20002e28, 0x00000061, 0x00400040 }, { 0x00010005, 0x203e2e29, 0x00000063, 0x00010001 }, { 0x00110001, 0x203e0169, 0x00000000, 0x00030003 }, { 0x00000001, 0x20200169, 0x00000000, 0x00000000 }, { 0x0000000c, 0x2458262d, 0x0000006d, 0x00000020 }, { 0x00000001, 0x210e0169, 0x00000000, 0x00010001 }, { 0x00000005, 0x24583dad, 0x00000458, 0x00030003 }, { 0x01000010, 0x200035ac, 0x0000010e, 0x00000458 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000031a }, { 0x01000010, 0x20003dac, 0x0200010e, 0x00010001 }, { 0x00010401, 0x24540061, 0x02000000, 0x06c00640 }, { 0x00010805, 0x245a3e2d, 0x02008800, 0x007f007f }, { 0x00110401, 0x24540061, 0x02000000, 0x04800780 }, { 0x00110805, 0x245a3e2d, 0x02008804, 0x007f007f }, { 0x00010005, 0x245c3e2d, 0x02008800, 0x00800080 }, { 0x00110005, 0x245c3e2d, 0x02008804, 0x00800080 }, { 0x00000009, 0x245c3dad, 0x0000045c, 0x00010001 }, { 0x0000000c, 0x211e362d, 0x0000006c, 0x00000020 }, { 0x00000040, 0x240035ac, 0x0000003e, 0x0000045c }, { 0x01000010, 0x20003d8c, 0x00210400, 0x00010001 }, { 0x01000010, 0x20003d8c, 0x02210400, 0x01000100 }, { 0x00000001, 0x203c01ed, 0x00000000, 0x00000000 }, { 0x00010001, 0x203c01ed, 0x00000000, 0x00020002 }, { 0x00010001, 0x203c01ed, 0x02000000, 0xfffefffe }, { 0x02000005, 0x20002e28, 0x00000061, 0x00400040 }, { 0x00010040, 0x244c0d21, 0x0000045a, 0x0208e602 }, { 0x00110040, 0x20780d21, 0x0000045a, 0x0208a002 }, { 0x00010040, 0x20782421, 0x0000044c, 0x0000045c }, { 0x02000005, 0x20003dac, 0x0200011e, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000001c0 }, { 0x01000005, 0x20003dac, 0x00009800, 0x00030003 }, { 0x00200005, 0x24443dad, 0x00459800, 0x00030003 }, { 0x0020000c, 0x24403dad, 0x00459800, 0x00020002 }, { 0x01600006, 0x20003dac, 0x02000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00010040, 0x22000c20, 0x02000078, 0x00400000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00700000 }, { 0x00310040, 0x20401da5, 0x02450440, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x000c000c }, { 0x00010040, 0x20401da5, 0x02000440, 0xfffffffe }, { 0x00010001, 0x204401a5, 0x02000442, 0x00000000 }, { 0x00010001, 0x20480061, 0x02000000, 0x0007000c }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00010040, 0x22000c20, 0x02000078, 0x00200000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00400000 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00110040, 0x20441da5, 0x02000442, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x000c0007 }, { 0x00010001, 0x20480061, 0x02000000, 0x00070007 }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000040, 0xb80235ad, 0x00009802, 0x0000003c }, { 0x0020040c, 0x24403dad, 0x00459800, 0x00030003 }, { 0x00200805, 0x24483dad, 0x00459800, 0x00070007 }, { 0x01600006, 0x20003dac, 0x0000044a, 0x00000000 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00000009, 0x20403ca5, 0x00000040, 0x00010001 }, { 0x00010040, 0x22000c20, 0x00000078, 0x00200010 }, { 0x00110040, 0x22000c20, 0x00000078, 0x00300010 }, { 0x00010001, 0x20480061, 0x00000000, 0x00030009 }, { 0x00110001, 0x20480061, 0x00000000, 0x00040009 }, { 0x02600031, 0x27000021, 0x408d0040, 0x00000200 }, { 0x01000005, 0x20003dac, 0x00009800, 0x00030003 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00600001, 0x26220231, 0x008d05c0, 0x00000000 }, { 0x00600401, 0x26120231, 0x008d05b8, 0x00000000 }, { 0x00600801, 0x26020231, 0x008d05b0, 0x00000000 }, { 0x00600401, 0x25f20231, 0x008d05a8, 0x00000000 }, { 0x00600801, 0x25e20231, 0x008d05a0, 0x00000000 }, { 0x00600401, 0x25d20231, 0x008d0598, 0x00000000 }, { 0x00600801, 0x25c20231, 0x008d0590, 0x00000000 }, { 0x00600401, 0x25b20231, 0x008d0588, 0x00000000 }, { 0x00600801, 0x25a20231, 0x008d0580, 0x00000000 }, { 0x00600401, 0x25920231, 0x008d0578, 0x00000000 }, { 0x00600801, 0x25820231, 0x008d0570, 0x00000000 }, { 0x00600001, 0x25720231, 0x008d0568, 0x00000000 }, { 0x00600001, 0x25620231, 0x008d0560, 0x00000000 }, { 0x00110001, 0x220001ec, 0x02000000, 0x05820582 }, { 0x00010001, 0x220001ec, 0x02000000, 0x05620562 }, { 0x00000001, 0x220e0128, 0x00000454, 0x00000000 }, { 0x01800006, 0x200035ac, 0x02000446, 0x00000444 }, { 0x00810001, 0xbc000229, 0x02ad8000, 0x00000000 }, { 0x00810001, 0xbc200229, 0x02ad8020, 0x00000000 }, { 0x00810001, 0xbc400229, 0x02ad8040, 0x00000000 }, { 0x00810001, 0xbc600229, 0x02ad8060, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000012a }, { 0x00600001, 0x2024018d, 0x008d0200, 0x00000000 }, { 0x01000041, 0x245e35ad, 0x00000446, 0x00000444 }, { 0x00000040, 0x22022d08, 0x00000200, 0x00100010 }, { 0x02000005, 0x20003db0, 0x0200045e, 0x00010001 }, { 0x00200040, 0x22042d08, 0x00450200, 0x00200020 }, { 0x00400001, 0x244c0109, 0x00690200, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000066 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000064 }, { 0x00000040, 0x22003d08, 0x00000200, 0xffdeffde }, { 0x00000440, 0x22023d08, 0x00000202, 0xffeeffee }, { 0x00000801, 0x220c0060, 0x00000000, 0x04a00480 }, { 0x01000010, 0x20003db0, 0x0000045e, 0x00040004 }, { 0x00a02040, 0x2400462c, 0x00ad8000, 0x00ad8005 }, { 0x00a02048, 0x24003e2c, 0x00ad8001, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8002, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8003, 0x00140014 }, { 0x00a02048, 0xb8003e2d, 0x00ad8004, 0xfffbfffb }, { 0x00a02040, 0x2400462c, 0x00ad8040, 0x00ad8045 }, { 0x00a02048, 0x24003e2c, 0x00ad8041, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8042, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8043, 0x00140014 }, { 0x00a02048, 0xb8403e2d, 0x00ad8044, 0xfffbfffb }, { 0x00a02040, 0x2400462c, 0x00ad8080, 0x00ad8085 }, { 0x00a02048, 0x24003e2c, 0x00ad8081, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8082, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8083, 0x00140014 }, { 0x00a02048, 0xb8803e2d, 0x00ad8084, 0xfffbfffb }, { 0x00600040, 0x2400462c, 0x008d80c0, 0x008d80c5 }, { 0x00600048, 0x24003e2c, 0x008d80c1, 0xfffbfffb }, { 0x00600048, 0x24003e2c, 0x008d80c2, 0x00140014 }, { 0x00600048, 0x24003e2c, 0x008d80c3, 0x00140014 }, { 0x00600048, 0xb8c03e2d, 0x008d80c4, 0xfffbfffb }, { 0x00000401, 0x22000060, 0x00000000, 0x04a00480 }, { 0x00000c01, 0x22040060, 0x00000000, 0x04a00490 }, { 0x00010802, 0x220c2d28, 0x00000454, 0x04800480 }, { 0x00a02040, 0x24003dac, 0x00b18000, 0x02000200 }, { 0x00800048, 0x24003dac, 0x01ed8800, 0xfffbfffb }, { 0x00800048, 0x24203dac, 0x01ed8820, 0xfffbfffb }, { 0x00a02048, 0x24003dac, 0x00b18020, 0x00140014 }, { 0x00800048, 0x24003dac, 0x01ed8820, 0x00140014 }, { 0x00800048, 0x24203dac, 0x01ed8840, 0x00140014 }, { 0x00a02048, 0x24003dac, 0x00b18040, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed8840, 0x00010001 }, { 0x00800048, 0x24203dac, 0x01ed8860, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x000a000a }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x000a000a }, { 0x00a02040, 0x24003dac, 0x00b18040, 0x02000200 }, { 0x00800048, 0x24003dac, 0x01ed8840, 0xfffbfffb }, { 0x00800048, 0x24203dac, 0x01ed8860, 0xfffbfffb }, { 0x00a02048, 0x24003dac, 0x00b18060, 0x00140014 }, { 0x00800048, 0x24003dac, 0x01ed8860, 0x00140014 }, { 0x00800048, 0x24203dac, 0x01ed8880, 0x00140014 }, { 0x00a02048, 0x24003dac, 0x00b18080, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed8880, 0x00010001 }, { 0x00800048, 0x24203dac, 0x01ed88a0, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x000a000a }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x000a000a }, { 0x00010220, 0x34001c00, 0x00001400, 0x000000b4 }, { 0x01000010, 0x20003db0, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000004c }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000004a }, { 0x00400040, 0x22003d28, 0x0069044c, 0xfffefffe }, { 0x03400010, 0x20003dac, 0x00000446, 0x00020002 }, { 0x01000010, 0x20003db0, 0x02000444, 0x00020002 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00100010 }, { 0x01000010, 0x20003dac, 0x00000446, 0x00000000 }, { 0x00010002, 0x220c2d28, 0x02000454, 0x04800480 }, { 0x00800040, 0x24003e2c, 0x01ed8000, 0x00100010 }, { 0x00800040, 0x24203e2c, 0x01ed8020, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8001, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8021, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8002, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8022, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8003, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8023, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8004, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8024, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8005, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8025, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x00050005 }, { 0x00800040, 0x24003e2c, 0x01ed8040, 0x00100010 }, { 0x00800040, 0x24203e2c, 0x01ed8060, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8041, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8061, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8042, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8062, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8043, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8063, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8044, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8064, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8045, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8065, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x00050005 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000005c }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000062 }, { 0x01000010, 0x20003db0, 0x00000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000042 }, { 0x00200401, 0x22000128, 0x0066044c, 0x00000000 }, { 0x00200c01, 0x22040128, 0x0045044e, 0x00000000 }, { 0x00000801, 0x220c0128, 0x00000454, 0x00000000 }, { 0x03400010, 0x20003dac, 0x02000444, 0x00020002 }, { 0x01000010, 0x20003dac, 0x00000444, 0x00000000 }, { 0x00410040, 0x22002d08, 0x02690200, 0x00010001 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00110001, 0x220c0168, 0x02000000, 0x04800480 }, { 0x00a02040, 0x24003e2c, 0x00ad83e0, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8be0, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8800, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8800, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8820, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8020, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8820, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8840, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x00050005 }, { 0x00a02040, 0x24003e2c, 0x00ad8020, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8820, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8840, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8040, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8840, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8860, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8060, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8860, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8880, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x00050005 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001c }, { 0x00200401, 0x22000128, 0x0045044c, 0x00000000 }, { 0x00000801, 0x220c0128, 0x00000454, 0x00000000 }, { 0x01200010, 0x20003dac, 0x00000444, 0x00030003 }, { 0x01200010, 0x20003dac, 0x02000446, 0x00030003 }, { 0x00210040, 0x22002d08, 0x00450200, 0x00010001 }, { 0x00210040, 0x22002d08, 0x02450200, 0x00100010 }, { 0x00800001, 0xb8000229, 0x01ed8000, 0x00000000 }, { 0x00800001, 0xb8200229, 0x01ed8020, 0x00000000 }, { 0x00800001, 0xb8400229, 0x01ed8040, 0x00000000 }, { 0x00800001, 0xb8600229, 0x01ed8060, 0x00000000 }, { 0x80800042, 0xd8004631, 0x00d29800, 0x00d20480 }, { 0x80800042, 0xd8204631, 0x00d29820, 0x00d204a0 }, { 0x80800042, 0xd8404631, 0x00d29840, 0x00d204c0 }, { 0x80800042, 0xd8604631, 0x00d29860, 0x00d204e0 }, { 0x00600001, 0x220001ac, 0x008d0024, 0x00000000 }, { 0x00200040, 0x244c3dad, 0x00450448, 0xfff8fff8 }, { 0x00000401, 0x220001ec, 0x00000000, 0x07000700 }, { 0x00000c01, 0x220201e8, 0x00000000, 0x07100710 }, { 0x00000801, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00000441, 0x254635ad, 0x00000448, 0x0000044a }, { 0x00000c41, 0x254025ad, 0x0000444c, 0x0000444e }, { 0x00000c41, 0x254225ad, 0x00000448, 0x0000444e }, { 0x00000841, 0x254435ad, 0x0000444c, 0x0000044a }, { 0x00200040, 0x244c3d09, 0x00450200, 0x00100010 }, { 0x00800041, 0x24002628, 0x00ad8000, 0x00000540 }, { 0x00800041, 0x24202628, 0x00ad8020, 0x00000540 }, { 0x00800048, 0x24002628, 0x00ad8002, 0x00000542 }, { 0x00800048, 0x24202628, 0x00ad8022, 0x00000542 }, { 0x00200001, 0x22000128, 0x0045044c, 0x00000000 }, { 0x00800048, 0x24002628, 0x01ed8000, 0x00000544 }, { 0x00800048, 0x24202628, 0x01ed8020, 0x00000544 }, { 0x00800048, 0xbc002629, 0x01ed8002, 0x00000546 }, { 0x00801048, 0xbc202629, 0x01ed8022, 0x00000546 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000128 }, { 0x00000001, 0x20220169, 0x00000000, 0x00040004 }, { 0x00200005, 0x24443dad, 0x00459800, 0x00030003 }, { 0x0020000c, 0x24403dad, 0x00459800, 0x00020002 }, { 0x01600006, 0x20003dac, 0x02000446, 0x00000000 }, { 0x00010040, 0x22000c20, 0x02000078, 0x00200000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00500000 }, { 0x00310040, 0x20401da5, 0x02450440, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x00080008 }, { 0x00010040, 0x20401da5, 0x02000440, 0xfffffffe }, { 0x00010001, 0x204401a5, 0x02000442, 0x00000000 }, { 0x00010001, 0x20480061, 0x02000000, 0x00030008 }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000040, 0xb80235ad, 0x00009802, 0x0000003c }, { 0x00000040, 0x22000c20, 0x00000078, 0x00100010 }, { 0x0020040c, 0x24403dad, 0x00459800, 0x00030003 }, { 0x00200805, 0x24483dad, 0x00459800, 0x00070007 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00000009, 0x20403ca5, 0x00000040, 0x00010001 }, { 0x00000001, 0x20480061, 0x00000000, 0x00020005 }, { 0x02600031, 0x27000021, 0x408d0040, 0x00000200 }, { 0x00110001, 0x220001ec, 0x02000000, 0x05820582 }, { 0x00010001, 0x220001ec, 0x02000000, 0x05620562 }, { 0x00000001, 0x220e0128, 0x00000454, 0x00000000 }, { 0x01800006, 0x200035ac, 0x02000446, 0x00000444 }, { 0x00410001, 0xbc000229, 0x02698000, 0x00000000 }, { 0x00410001, 0xbc100229, 0x02698010, 0x00000000 }, { 0x00410001, 0xbc200229, 0x02698020, 0x00000000 }, { 0x00410001, 0xbc300229, 0x02698030, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000be }, { 0x00600001, 0x2024018d, 0x008d0200, 0x00000000 }, { 0x01000041, 0x245e35ad, 0x00000446, 0x00000444 }, { 0x02000005, 0x20003db0, 0x0200045e, 0x00010001 }, { 0x00000040, 0x22022d08, 0x00000200, 0x00100010 }, { 0x00200040, 0x22042d08, 0x00450200, 0x00200020 }, { 0x00400001, 0x244c0109, 0x00690200, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000044 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000042 }, { 0x00000040, 0x22003d08, 0x00000200, 0xffdeffde }, { 0x00000440, 0x22023d08, 0x00000202, 0xffeeffee }, { 0x00000801, 0x220c0060, 0x00000000, 0x04d004c0 }, { 0x01000010, 0x20003db0, 0x0000045e, 0x00040004 }, { 0x00802040, 0x2400462c, 0x00a98000, 0x00a98005 }, { 0x00802048, 0x24003e2c, 0x00a98001, 0xfffbfffb }, { 0x00802048, 0x24003e2c, 0x00a98002, 0x00140014 }, { 0x00802048, 0x24003e2c, 0x00a98003, 0x00140014 }, { 0x00802048, 0xb8003e2d, 0x00a98004, 0xfffbfffb }, { 0x00802040, 0x2400462c, 0x00a98040, 0x00a98045 }, { 0x00802048, 0x24003e2c, 0x00a98041, 0xfffbfffb }, { 0x00802048, 0x24003e2c, 0x00a98042, 0x00140014 }, { 0x00802048, 0x24003e2c, 0x00a98043, 0x00140014 }, { 0x00802048, 0xb8203e2d, 0x00a98044, 0xfffbfffb }, { 0x00400040, 0x2400462c, 0x00698080, 0x00698085 }, { 0x00400048, 0x24003e2c, 0x00698081, 0xfffbfffb }, { 0x00400048, 0x24003e2c, 0x00698082, 0x00140014 }, { 0x00400048, 0x24003e2c, 0x00698083, 0x00140014 }, { 0x00400048, 0xb8403e2d, 0x00698084, 0xfffbfffb }, { 0x00000401, 0x220c0060, 0x00000000, 0x04e004d0 }, { 0x00000c01, 0x22000060, 0x00000000, 0x04d004c8 }, { 0x00000c01, 0x22040060, 0x00000000, 0x04e004d8 }, { 0x00000801, 0x22080060, 0x00000000, 0x04f004e8 }, { 0x00800040, 0x24003dac, 0x00b104c0, 0x02000200 }, { 0x00800048, 0x24003dac, 0x00b104e0, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed9800, 0x00140014 }, { 0x00010001, 0x220c0168, 0x00000000, 0x05400540 }, { 0x00110001, 0x220c0168, 0x00000000, 0x04c004c0 }, { 0x00800048, 0x24003dac, 0x01e98000, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01e98020, 0x00010001 }, { 0x00800048, 0x24003dac, 0x01e98800, 0x00140014 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x000a000a }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000060 }, { 0x01000010, 0x20003db0, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000022 }, { 0x00400040, 0x22003d28, 0x0069044c, 0xfffefffe }, { 0x03400010, 0x20003dac, 0x00000446, 0x00020002 }, { 0x01000010, 0x20003db0, 0x02000444, 0x00020002 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00100010 }, { 0x01000010, 0x20003dac, 0x00000446, 0x00000000 }, { 0x00010001, 0x220e0168, 0x02000000, 0x05400540 }, { 0x00110001, 0x220e0168, 0x02000000, 0x04c004c0 }, { 0x00800040, 0x24003e2c, 0x01e98000, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01e98001, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e98002, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98003, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98004, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e98005, 0x00010001 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00050005 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000036 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000036 }, { 0x01000010, 0x20003db0, 0x00000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x03600010, 0x20003dac, 0x02000444, 0x00020002 }, { 0x00400401, 0x22000128, 0x0069044c, 0x00000000 }, { 0x00400840, 0x22083d2c, 0x0069044c, 0x00100010 }, { 0x00610040, 0x22002d08, 0x02690200, 0x00010001 }, { 0x01000010, 0x20003dac, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00800040, 0x24003e2c, 0x01e983e0, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01e98000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98020, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e993e0, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e99000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e99020, 0x00010001 }, { 0x00000001, 0x220e0168, 0x00000000, 0x05400540 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00110001, 0x220e0168, 0x02000000, 0x04c004c0 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00050005 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000e }, { 0x00400001, 0x22000128, 0x0069044c, 0x00000000 }, { 0x01400010, 0x20003dac, 0x00000444, 0x00030003 }, { 0x01400010, 0x20003dac, 0x02000446, 0x00030003 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00010001 }, { 0x00410040, 0x22002d08, 0x02690200, 0x00100010 }, { 0x00800001, 0x25400229, 0x01e98000, 0x00000000 }, { 0x80800042, 0x45404631, 0x00d20540, 0x00d204c0 }, { 0x00000001, 0x220c0128, 0x00000454, 0x00000000 }, { 0x00400001, 0xd8000231, 0x008a0540, 0x00000000 }, { 0x00400001, 0xd8100231, 0x008a0548, 0x00000000 }, { 0x00400001, 0xd8200231, 0x008a0550, 0x00000000 }, { 0x00400001, 0xd8300231, 0x008a0558, 0x00000000 }, { 0x00600001, 0x220001ac, 0x008d0024, 0x00000000 }, { 0x00200040, 0x244c3dad, 0x00450448, 0xfff8fff8 }, { 0x00000401, 0x220001ec, 0x00000000, 0x07000700 }, { 0x00000801, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00000441, 0x254635ad, 0x00000448, 0x0000044a }, { 0x00000c41, 0x254025ad, 0x0000444c, 0x0000444e }, { 0x00000c41, 0x254225ad, 0x00000448, 0x0000444e }, { 0x00000841, 0x254435ad, 0x0000444c, 0x0000044a }, { 0x00600041, 0x24002628, 0x00898000, 0x00000540 }, { 0x00600048, 0x24002628, 0x00898002, 0x00000542 }, { 0x00600048, 0x24002628, 0x00898008, 0x00000544 }, { 0x00600048, 0x2540262d, 0x0089800a, 0x00000546 }, { 0x00400401, 0xbc0001a9, 0x00690540, 0x00000000 }, { 0x00400801, 0xbc1001a9, 0x00690548, 0x00000000 }, { 0x01000010, 0x20003d2c, 0x00000022, 0x00030003 }, { 0x01000040, 0x20223d29, 0x02000022, 0xffffffff }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0x00080008 }, { 0x00110040, 0x24540c21, 0x00000454, 0x00080008 }, { 0x00010040, 0x24540c21, 0x00000454, 0x00180038 }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffee4 }, { 0x01800010, 0x20003dac, 0x0200010e, 0x00010001 }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0xffe0ffe0 }, { 0x00010001, 0x24540061, 0x02000000, 0x06c00640 }, { 0x00110001, 0x24540061, 0x02000000, 0x04800780 }, { 0x00000001, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00800040, 0x24003dac, 0x00b19c00, 0x00200020 }, { 0x00800040, 0x24203dac, 0x00b19c20, 0x00200020 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00060006 }, { 0x8080000c, 0xdc203d91, 0x00b10420, 0x00060006 }, { 0x02000040, 0x210e3d29, 0x0200010e, 0xffffffff }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0x00040004 }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffcdc }, { 0x01000005, 0x25643e2d, 0x00000060, 0x00c000c0 }, { 0x01000010, 0x20003dac, 0x02000458, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x01000010, 0x20003dac, 0x00000458, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00a02001, 0x46400231, 0x00d20780, 0x00000000 }, { 0x00a02001, 0x46800231, 0x00d207c0, 0x00000000 }, { 0x00a02001, 0x46c00231, 0x00d20480, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000007e }, { 0x80a02042, 0x46404631, 0x00d20640, 0x00d20780 }, { 0x80a02042, 0x46804631, 0x00d20680, 0x00d207c0 }, { 0x80a02042, 0x46c04631, 0x00d206c0, 0x00d20480 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000076 }, { 0x01000010, 0x20003dac, 0x02000564, 0x00800080 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000000e }, { 0x01000010, 0x20003dac, 0x00000458, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0xffffffe4 }, { 0x00200401, 0x256801ed, 0x00000000, 0x00200020 }, { 0x00200801, 0x256c01ed, 0x00000000, 0x00060006 }, { 0x00400001, 0x258001ed, 0x00000000, 0x00000000 }, { 0x00600001, 0x45a001ad, 0x00058c00, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000028 }, { 0x02600005, 0x20006e28, 0x02008c0c, 0x88848421 }, { 0x0220000c, 0x25663dad, 0x00000458, 0x00010001 }, { 0x0000000c, 0x25643dad, 0x00000564, 0x00060006 }, { 0x00310001, 0x25c401ad, 0x00000458, 0x00000000 }, { 0x00210001, 0x25c00061, 0x00000000, 0x00010001 }, { 0x00310040, 0x25c03dad, 0x004545c4, 0x00010001 }, { 0x00610001, 0x25a00061, 0x02000000, 0x00000080 }, { 0x00710001, 0x45a002ad, 0x02ae8c00, 0x00000000 }, { 0x00710001, 0x45a202ad, 0x02ae8c01, 0x00000000 }, { 0x00800041, 0x25a035ad, 0x00b105a0, 0x000905c0 }, { 0x01200010, 0x20003e2c, 0x0245006e, 0x00000000 }, { 0x00310009, 0x244c45ad, 0x02000564, 0x0045006e }, { 0x00210001, 0x244c01ed, 0x02000000, 0x00000000 }, { 0x0031000c, 0x244c3dad, 0x0245044c, 0x00010001 }, { 0x00200009, 0x256835ad, 0x0045044c, 0x00000566 }, { 0x00210040, 0x256835ad, 0x02450568, 0x00000566 }, { 0x00200040, 0x256c362d, 0x0045006e, 0x00000566 }, { 0x00400040, 0x240035ac, 0x00ab05a2, 0x00ab05a6 }, { 0x00400040, 0x2400358c, 0x00690400, 0x00000566 }, { 0x0040000c, 0x2580358d, 0x00690400, 0x00000566 }, { 0x00800041, 0x2400362c, 0x00d20640, 0x000005a0 }, { 0x00800041, 0x2420362c, 0x00d20660, 0x000005a0 }, { 0x00800048, 0x2400362c, 0x00d20780, 0x000005a4 }, { 0x00800048, 0x2420362c, 0x00d207a0, 0x000005a4 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00000568 }, { 0x00800040, 0x2420358c, 0x00b10420, 0x00000568 }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056c }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056c }, { 0x80800040, 0x464035b1, 0x00b104c0, 0x00000580 }, { 0x80800040, 0x466035b1, 0x00b104e0, 0x00000580 }, { 0x00800041, 0x2400362c, 0x00d20680, 0x000005a0 }, { 0x00800041, 0x2420362c, 0x00d206a0, 0x000005a0 }, { 0x00800048, 0x2400362c, 0x00d207c0, 0x000005a4 }, { 0x00800048, 0x2420362c, 0x00d207e0, 0x000005a4 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00000568 }, { 0x00800040, 0x2420358c, 0x00b10420, 0x00000568 }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056c }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056c }, { 0x80800040, 0x468035b1, 0x00b104c0, 0x00000580 }, { 0x80800040, 0x46a035b1, 0x00b104e0, 0x00000580 }, { 0x00800041, 0x2400362c, 0x00d206c0, 0x000705a8 }, { 0x00800041, 0x2420362c, 0x00d206e0, 0x000705a8 }, { 0x00800048, 0x2400362c, 0x00d20480, 0x000705ac }, { 0x00800048, 0x2420362c, 0x00d204a0, 0x000705ac }, { 0x00800040, 0x2400358c, 0x00b10400, 0x0000056a }, { 0x00800040, 0x2420358c, 0x00b10420, 0x0000056a }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056e }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056e }, { 0x80800040, 0x46c035b1, 0x00b104c0, 0x00050582 }, { 0x80800040, 0x46e035b1, 0x00b104e0, 0x00050582 }, { 0x01800005, 0x20003d2c, 0x02000020, 0x00020002 }, { 0x80800040, 0xd00045b1, 0x00b19000, 0x00d20640 }, { 0x80800040, 0xd02045b1, 0x00b19020, 0x00d20660 }, { 0x80800040, 0xd04045b1, 0x00b19040, 0x00d20680 }, { 0x80800040, 0xd06045b1, 0x00b19060, 0x00d206a0 }, { 0x00000040, 0x22083d8c, 0x00000208, 0x00800080 }, { 0x80400040, 0xd40045b1, 0x00699400, 0x00ab06c0 }, { 0x80400040, 0xd48045b1, 0x00699480, 0x00ab06c2 }, { 0x80400040, 0xd42045b1, 0x00699420, 0x00ab06e0 }, { 0x80400040, 0xd4a045b1, 0x006994a0, 0x00ab06e2 }, { 0x80400040, 0xd41045b1, 0x00699410, 0x00ab06d0 }, { 0x80400040, 0xd49045b1, 0x00699490, 0x00ab06d2 }, { 0x80400040, 0xd43045b1, 0x00699430, 0x00ab06f0 }, { 0x80400040, 0xd4b045b1, 0x006994b0, 0x00ab06f2 }, { 0x00000040, 0x220a3d8c, 0x0000020a, 0x00080008 }, { 0x00110040, 0x220a3d8c, 0x0200020a, 0x00300030 }, { 0x01000010, 0x20003d2c, 0x02000020, 0x00060006 }, { 0x00000040, 0x20203d29, 0x00000020, 0x00020002 }, { 0x00000040, 0x22040c00, 0x00000204, 0x00100001 }, { 0x00000040, 0x220c358c, 0x0000020c, 0x0000003a }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffc1a }, { 0x00000001, 0x220001ec, 0x00000000, 0x01400140 }, { 0x00000001, 0x220201ec, 0x00000000, 0x01c001c0 }, { 0x00800401, 0x20400236, 0x01ee8000, 0x00000000 }, { 0x00800801, 0x20500236, 0x01ee8010, 0x00000000 }, { 0x00800401, 0x20600236, 0x01ee8020, 0x00000000 }, { 0x00800801, 0x20700236, 0x01ee8030, 0x00000000 }, { 0x00800401, 0x20800236, 0x01ee8040, 0x00000000 }, { 0x00800801, 0x20900236, 0x01ee8050, 0x00000000 }, { 0x00800401, 0x20a00236, 0x01ee8060, 0x00000000 }, { 0x00800801, 0x20b00236, 0x01ee8070, 0x00000000 }, { 0x00800401, 0x20c00236, 0x01ee8100, 0x00000000 }, { 0x00800801, 0x20d00236, 0x01ee8110, 0x00000000 }, { 0x00800401, 0x20e00236, 0x01ee8120, 0x00000000 }, { 0x00800801, 0x20f00236, 0x01ee8130, 0x00000000 }, { 0x00800401, 0x21000236, 0x01ee8140, 0x00000000 }, { 0x00800801, 0x21100236, 0x01ee8150, 0x00000000 }, { 0x00800401, 0x21200236, 0x01ee8160, 0x00000000 }, { 0x00800801, 0x21300236, 0x01ee8170, 0x00000000 }, { 0x00000040, 0x22000d20, 0x00000062, 0x1218a000 }, { 0x00200401, 0x204001a5, 0x00450064, 0x00000000 }, { 0x00000801, 0x20480061, 0x00000000, 0x000f000f }, { 0x01600031, 0x21400021, 0x508d0040, 0x00000200 }, { 0x00000001, 0x220001ec, 0x00000000, 0x03400340 }, { 0x00800401, 0x41600236, 0x00d28000, 0x00000000 }, { 0x00800801, 0x41610236, 0x00d28080, 0x00000000 }, { 0x00800401, 0x41800236, 0x00d28020, 0x00000000 }, { 0x00800801, 0x41810236, 0x00d280a0, 0x00000000 }, { 0x00800401, 0x41a00236, 0x00d28040, 0x00000000 }, { 0x00800801, 0x41a10236, 0x00d280c0, 0x00000000 }, { 0x00800401, 0x41c00236, 0x00d28060, 0x00000000 }, { 0x00800801, 0x41c10236, 0x00d280e0, 0x00000000 }, { 0x00000040, 0x22000d20, 0x00000062, 0x0a18a001 }, { 0x0000040c, 0x20443ca5, 0x00000044, 0x00010001 }, { 0x00000801, 0x20480061, 0x00000000, 0x0007000f }, { 0x0a600031, 0x21600021, 0x508d0040, 0x00000200 }, { 0x00000001, 0x21400021, 0x00000140, 0x00000000 }, { 0x00000001, 0x21600021, 0x00000160, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x01000005, 0x20602d29, 0x02000042, 0x00070007 }, { 0x01000005, 0x20422d29, 0x00000042, 0xfff8fff8 }, { 0x00000001, 0x202001e9, 0x00000000, 0x100c100c }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00000009, 0x27e82d21, 0x00000040, 0x00060006 }, { 0x00600001, 0x20a00022, 0x008d0000, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000100 }, { 0x00600001, 0x20200022, 0x008d07e0, 0x00000000 }, { 0x01800031, 0x20801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20400022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20480c22, 0x000007e8, 0x00000080 }, { 0x02800031, 0x21001d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20600022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20680c22, 0x000007e8, 0x00000100 }, { 0x03800031, 0x21801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20800022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20880c22, 0x000007e8, 0x00000180 }, { 0x04800031, 0x22001d09, 0x408d0000, 0x02488400 }, { 0x02600005, 0x20000c20, 0x02000090, 0x00002000 }, { 0x00000006, 0x20880c21, 0x00000088, 0x00200000 }, { 0x00200009, 0x20845529, 0x0000009c, 0x00450020 }, { 0x00200001, 0x40840231, 0x00450094, 0x00000000 }, { 0x00310001, 0x20840229, 0x02450094, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00000095, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00000094 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0080, 0x00000000 }, { 0x00802001, 0x20800061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x020000d0, 0x00002000 }, { 0x00000006, 0x20c80c21, 0x000000c8, 0x00200000 }, { 0x00200009, 0x20c45529, 0x000000dc, 0x00450020 }, { 0x00200001, 0x40c40231, 0x004500d4, 0x00000000 }, { 0x00310001, 0x20c40229, 0x024500d4, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x000000d5, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x000000d4 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x02000110, 0x00002000 }, { 0x00000006, 0x21080c21, 0x00000108, 0x00200000 }, { 0x00200009, 0x21045529, 0x0000011c, 0x00450020 }, { 0x00200001, 0x41040231, 0x00450114, 0x00000000 }, { 0x00310001, 0x21040229, 0x02450114, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00000115, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00000114 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x21000061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x02000150, 0x00002000 }, { 0x00000006, 0x21480c21, 0x00000148, 0x00200000 }, { 0x00200009, 0x21445529, 0x0000015c, 0x00450020 }, { 0x00200001, 0x41440231, 0x00450154, 0x00000000 }, { 0x00310001, 0x21440229, 0x02450154, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00000155, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00000154 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0140, 0x00000000 }, { 0x00802001, 0x21400061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x02000190, 0x00002000 }, { 0x00000006, 0x21880c21, 0x00000188, 0x00200000 }, { 0x00200009, 0x21845529, 0x0000019c, 0x00450020 }, { 0x00200001, 0x41840231, 0x00450194, 0x00000000 }, { 0x00310001, 0x21840229, 0x02450194, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00000195, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00000194 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0180, 0x00000000 }, { 0x00802001, 0x21800061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x020001d0, 0x00002000 }, { 0x00000006, 0x21c80c21, 0x000001c8, 0x00200000 }, { 0x00200009, 0x21c45529, 0x000001dc, 0x00450020 }, { 0x00200001, 0x41c40231, 0x004501d4, 0x00000000 }, { 0x00310001, 0x21c40229, 0x024501d4, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x000001d5, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x000001d4 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d01c0, 0x00000000 }, { 0x00802001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x02000210, 0x00002000 }, { 0x00000006, 0x22080c21, 0x00000208, 0x00200000 }, { 0x00200009, 0x22045529, 0x0000021c, 0x00450020 }, { 0x00200001, 0x42040231, 0x00450214, 0x00000000 }, { 0x00310001, 0x22040229, 0x02450214, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00000215, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00000214 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0200, 0x00000000 }, { 0x00802001, 0x22000061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x02000250, 0x00002000 }, { 0x00000006, 0x22480c21, 0x00000248, 0x00200000 }, { 0x00200009, 0x22445529, 0x0000025c, 0x00450020 }, { 0x00200001, 0x42440231, 0x00450254, 0x00000000 }, { 0x00310001, 0x22440229, 0x02450254, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00000255, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00000254 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0240, 0x00000000 }, { 0x00802001, 0x22400061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x01000040, 0x20423dad, 0x00000042, 0xfff8fff8 }, { 0x00600001, 0x21600022, 0x008d07e0, 0x00000000 }, { 0x00802001, 0x21800022, 0x008d0080, 0x00000000 }, { 0x00802001, 0x21c00022, 0x008d00c0, 0x00000000 }, { 0x0b800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00600001, 0x20200022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20280c22, 0x000007e8, 0x00000080 }, { 0x00802001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0140, 0x00000000 }, { 0x01800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00000040, 0x21680c22, 0x000007e8, 0x00000100 }, { 0x00802001, 0x21800022, 0x008d0180, 0x00000000 }, { 0x00802001, 0x21c00022, 0x008d01c0, 0x00000000 }, { 0x0b800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00000040, 0x20280c22, 0x000007e8, 0x00000180 }, { 0x00802001, 0x20400022, 0x008d0200, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0240, 0x00000000 }, { 0x01800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00000040, 0x27e80c21, 0x000007e8, 0x00000200 }, { 0x01000010, 0x20002da0, 0x02000060, 0x00000000 }, { 0x00110220, 0x34001c00, 0x00001400, 0xffffff00 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000040 }, { 0x00600001, 0x20200022, 0x008d07e0, 0x00000000 }, { 0x01800031, 0x20801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20400022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20480c22, 0x000007e8, 0x00000080 }, { 0x02800031, 0x21001d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20600022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20680c22, 0x000007e8, 0x00000100 }, { 0x03800031, 0x21801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20800022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20880c22, 0x000007e8, 0x00000180 }, { 0x04800031, 0x22001d09, 0x408d0000, 0x02488400 }, { 0x00000001, 0x220400e0, 0x00000000, 0x00a00080 }, { 0x00600001, 0x20a00022, 0x008d0000, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02008810, 0x00002000 }, { 0x01000040, 0x20603dad, 0x00000060, 0xffffffff }, { 0x00000006, 0xa8080c21, 0x00008808, 0x00200000 }, { 0x00200009, 0xa8045529, 0x0000881c, 0x00450020 }, { 0x00200001, 0xc8040231, 0x00458814, 0x00000000 }, { 0x00310001, 0xa8040229, 0x02458814, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00008815, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00008814 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d8800, 0x00000000 }, { 0x00802001, 0xa8000061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00600001, 0x21600022, 0x008d07e0, 0x00000000 }, { 0x00802001, 0x21800022, 0x008d8800, 0x00000000 }, { 0x0b800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000040, 0x27e80c21, 0x000007e8, 0x00000040 }, { 0x00000040, 0x22040c00, 0x00000204, 0x00400040 }, { 0x00110220, 0x34001c00, 0x00001400, 0xffffffda }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x01000005, 0x20602d29, 0x02000042, 0x00070007 }, { 0x01000005, 0x20422d29, 0x00000042, 0xfff8fff8 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00000009, 0x27e82d21, 0x00000040, 0x00060006 }, { 0x00600001, 0x20a00022, 0x008d0000, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000260 }, { 0x00600001, 0x20200022, 0x008d07e0, 0x00000000 }, { 0x01800031, 0x20801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20400022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20480c22, 0x000007e8, 0x00000080 }, { 0x02800031, 0x21001d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20600022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20680c22, 0x000007e8, 0x00000100 }, { 0x03800031, 0x21801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20800022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20880c22, 0x000007e8, 0x00000180 }, { 0x04800031, 0x22001d09, 0x408d0000, 0x02488400 }, { 0x00200001, 0x20640229, 0x00450094, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02000090, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00000090, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00000095, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00000095, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00000090, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x20881c21, 0x00000088, 0x00200000 }, { 0x00200001, 0x20840129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0080, 0x00000000 }, { 0x00802001, 0x20800061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x00000090, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x0000009c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000009c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200009c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02000090, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200009c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200009c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x20843d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x20862d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x40840231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x004500d4, 0x00000000 }, { 0x02600005, 0x20000c20, 0x020000d0, 0x01000000 }, { 0x02600005, 0x20000c20, 0x000000d0, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x000000d5, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x000000d5, 0x00000000 }, { 0x02600005, 0x20000c20, 0x000000d0, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x20c81c21, 0x000000c8, 0x00200000 }, { 0x00200001, 0x20c40129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x000000d0, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x000000dc, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x000000dc, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x020000dc, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x020000d0, 0x00008000 }, { 0x02610005, 0x20001d20, 0x020000dc, 0x00000010 }, { 0x00010006, 0x20681d29, 0x020000dc, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x20c43d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x20c62d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x40c40231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x00450114, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02000110, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00000110, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00000115, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00000115, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00000110, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x21081c21, 0x00000108, 0x00200000 }, { 0x00200001, 0x21040129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x21000061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x00000110, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x0000011c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000011c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200011c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02000110, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200011c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200011c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x21043d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x21062d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x41040231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x00450154, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02000150, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00000150, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00000155, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00000155, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00000150, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x21481c21, 0x00000148, 0x00200000 }, { 0x00200001, 0x21440129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0140, 0x00000000 }, { 0x00802001, 0x21400061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x00000150, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x0000015c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000015c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200015c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02000150, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200015c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200015c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x21443d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x21462d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x41440231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x00450194, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02000190, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00000190, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00000195, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00000195, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00000190, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x21881c21, 0x00000188, 0x00200000 }, { 0x00200001, 0x21840129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0180, 0x00000000 }, { 0x00802001, 0x21800061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x00000190, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x0000019c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000019c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200019c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02000190, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200019c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200019c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x21843d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x21862d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x41840231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x004501d4, 0x00000000 }, { 0x02600005, 0x20000c20, 0x020001d0, 0x01000000 }, { 0x02600005, 0x20000c20, 0x000001d0, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x000001d5, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x000001d5, 0x00000000 }, { 0x02600005, 0x20000c20, 0x000001d0, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x21c81c21, 0x000001c8, 0x00200000 }, { 0x00200001, 0x21c40129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d01c0, 0x00000000 }, { 0x00802001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x000001d0, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x000001dc, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x000001dc, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x020001dc, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x020001d0, 0x00008000 }, { 0x02610005, 0x20001d20, 0x020001dc, 0x00000010 }, { 0x00010006, 0x20681d29, 0x020001dc, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x21c43d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x21c62d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x41c40231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x00450214, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02000210, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00000210, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00000215, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00000215, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00000210, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x22081c21, 0x00000208, 0x00200000 }, { 0x00200001, 0x22040129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0200, 0x00000000 }, { 0x00802001, 0x22000061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x00000210, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x0000021c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000021c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200021c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02000210, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200021c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200021c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x22043d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x22062d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x42040231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x00450254, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02000250, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00000250, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00000255, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00000255, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00000250, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x22481c21, 0x00000248, 0x00200000 }, { 0x00200001, 0x22440129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0240, 0x00000000 }, { 0x00802001, 0x22400061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x00000250, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x0000025c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000025c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200025c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02000250, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200025c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200025c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x22443d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x22462d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x42440231, 0x00660064, 0x00000000 }, { 0x01000040, 0x20423dad, 0x00000042, 0xfff8fff8 }, { 0x00600001, 0x21600022, 0x008d07e0, 0x00000000 }, { 0x00802001, 0x21800022, 0x008d0080, 0x00000000 }, { 0x00802001, 0x21c00022, 0x008d00c0, 0x00000000 }, { 0x0b800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00600001, 0x20200022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20280c22, 0x000007e8, 0x00000080 }, { 0x00802001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0140, 0x00000000 }, { 0x01800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00000040, 0x21680c22, 0x000007e8, 0x00000100 }, { 0x00802001, 0x21800022, 0x008d0180, 0x00000000 }, { 0x00802001, 0x21c00022, 0x008d01c0, 0x00000000 }, { 0x0b800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00000040, 0x20280c22, 0x000007e8, 0x00000180 }, { 0x00802001, 0x20400022, 0x008d0200, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0240, 0x00000000 }, { 0x01800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00000040, 0x27e80c21, 0x000007e8, 0x00000200 }, { 0x01000010, 0x20002da0, 0x02000060, 0x00000000 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffda0 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000006e }, { 0x00600001, 0x20200022, 0x008d07e0, 0x00000000 }, { 0x01800031, 0x20801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20400022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20480c22, 0x000007e8, 0x00000080 }, { 0x02800031, 0x21001d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20600022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20680c22, 0x000007e8, 0x00000100 }, { 0x03800031, 0x21801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20800022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20880c22, 0x000007e8, 0x00000180 }, { 0x04800031, 0x22001d09, 0x408d0000, 0x02488400 }, { 0x00000001, 0x220400e0, 0x00000000, 0x00a00080 }, { 0x00600001, 0x20a00022, 0x008d0000, 0x00000000 }, { 0x00200001, 0x20640229, 0x00458814, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02008810, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00008810, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00008815, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00008815, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00008810, 0x00002000 }, { 0x01000040, 0x20603dad, 0x02000060, 0xffffffff }, { 0x00000006, 0xa8080c21, 0x00008808, 0x00200000 }, { 0x00200001, 0xa8040129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d8800, 0x00000000 }, { 0x00802001, 0xa8000061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000022 }, { 0x02600005, 0x20000d20, 0x02000066, 0x00000001 }, { 0x02600005, 0x20000c20, 0x00008810, 0x00004000 }, { 0x00000001, 0x20680129, 0x0000881c, 0x00000000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000881c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200881c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02008810, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200881c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200881c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x00000068, 0x000d0070 }, { 0x01000040, 0x20603dad, 0x02000060, 0x00000000 }, { 0x00000009, 0xa8043d09, 0x00000600, 0x000c000c }, { 0x00000005, 0xa8062d09, 0x00000600, 0xf000f000 }, { 0x00200001, 0xc8040231, 0x00660064, 0x00000000 }, { 0x00600001, 0x21600022, 0x008d07e0, 0x00000000 }, { 0x00802001, 0x21800022, 0x008d8800, 0x00000000 }, { 0x0b800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000040, 0x27e80c21, 0x000007e8, 0x00000040 }, { 0x00000040, 0x22040c00, 0x00000204, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0xffffffac }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00a02001, 0x20400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x206601ed, 0x00000000, 0x00030003 }, { 0x00000009, 0x20663dad, 0x00000066, 0x000a000a }, { 0x00000008, 0x22403dad, 0x00000026, 0x00010001 }, { 0x00000041, 0x224235ad, 0x00000020, 0x00000022 }, { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, { 0x00000001, 0x203c0022, 0x00000018, 0x00000000 }, { 0x00000001, 0x203f01f2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c00e2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c010a, 0x00000e00, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0020, 0x00000000 }, { 0x00400001, 0x205401ed, 0x00000000, 0x00000000 }, { 0x00200040, 0x20583dad, 0x00450020, 0xffffffff }, { 0x00000001, 0x22000060, 0x00000000, 0x06080000 }, { 0x00600001, 0x26000021, 0x008d0000, 0x00000000 }, { 0x00000001, 0x26140061, 0x00000000, 0x00c00400 }, { 0x00000001, 0x26100169, 0x00000000, 0x12121212 }, { 0x07600031, 0x26201c21, 0x308d0600, 0x02000000 }, { 0x00000001, 0x22a00169, 0x00000000, 0x01400140 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00200020 }, { 0x00000001, 0x203801e2, 0x00000000, 0x00010001 }, { 0x00800001, 0x204001ae, 0x00b10020, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x000002a0, 0x00010001 }, { 0x00800031, 0x20000128, 0x608d07e0, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x22a00169, 0x00000000, 0x00000000 }, { 0x00000001, 0x22600169, 0x00000000, 0x00020002 }, { 0x00200401, 0x208000e5, 0x00000000, 0x00000000 }, { 0x00000c01, 0x208800e5, 0x00000000, 0xffffffc6 }, { 0x00000801, 0x208c00e5, 0x00000000, 0xffffffca }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00100010 }, { 0x00000001, 0x206001ed, 0x00000000, 0x00020002 }, { 0x00000001, 0x206201ad, 0x0000005a, 0x00000000 }, { 0x00000001, 0x20a001ed, 0x00000000, 0x00000000 }, { 0x00200001, 0x228001ed, 0x00000000, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21000061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21400061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21800061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21c00061, 0x00000000, 0x00ff00ff }, { 0x00000041, 0x22083dac, 0x00000056, 0x00040004 }, { 0x05000010, 0x200035ac, 0x02000280, 0x00000240 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x01000010, 0x20002d28, 0x000090c2, 0x00000000 }, { 0x03000010, 0x200035ac, 0x02000054, 0x00000058 }, { 0x00000041, 0x22a03dad, 0x00000056, 0x00040004 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffff4 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00200001, 0xb0c00229, 0x00450054, 0x00000000 }, { 0x00200040, 0x22803dad, 0x00450280, 0x00010001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x20380122, 0x00000260, 0x00000000 }, { 0x00800001, 0x204001ae, 0x00b10040, 0x00000000 }, { 0x00000008, 0x20003d2a, 0x000002a0, 0x00010001 }, { 0x00000040, 0x22602d29, 0x00000260, 0x00020002 }, { 0x00800031, 0x20000008, 0x608d0000, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x04200010, 0x200035ac, 0x00450054, 0x00450060 }, { 0x00010040, 0x20a03dad, 0x02000056, 0x00010001 }, { 0x05200010, 0x200035ac, 0x02450280, 0x00450240 }, { 0x00000001, 0x240001ec, 0x00000000, 0x00040004 }, { 0x00000048, 0x22083dac, 0x00000056, 0x00040004 }, { 0x00200040, 0x205455ad, 0x00450054, 0x00450034 }, { 0x02000010, 0x20003d8c, 0x00000600, 0x00010001 }, { 0x00000041, 0x220e3d8c, 0x00000602, 0x00040004 }, { 0x00010041, 0x22083dac, 0x000000a0, 0x00040004 }, { 0x00010401, 0x205601ad, 0x000000a0, 0x00000000 }, { 0x00010840, 0x20543d2d, 0x000090c0, 0x00010001 }, { 0x00000220, 0x34001400, 0x00001400, 0x00009c80 }, { 0x01000010, 0x20003dac, 0x02000280, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000006 }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffff6 }, { 0x05000010, 0x200035ac, 0x00000240, 0x00000026 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffffc }, { 0x07600031, 0x20001c20, 0x30000000, 0x02000001 }, { 0x01600031, 0x20001c24, 0x708d0000, 0x82000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00600009, 0x25c03dad, 0x00050034, 0x00040004 }, { 0x00000001, 0x220801ec, 0x00000000, 0x02400240 }, { 0x00000041, 0x20263d29, 0x00000036, 0x00040004 }, { 0x00000041, 0x25e435a1, 0x00000020, 0x00000036 }, { 0x00000040, 0x25e43421, 0x000005e4, 0x00000034 }, { 0x00000041, 0x27e82c21, 0x000005e4, 0x00400040 }, { 0x01600031, 0x22401c21, 0x408d07e0, 0x02885800 }, { 0x01800005, 0x20002d28, 0x02b19040, 0xffffffff }, { 0x02000005, 0x20003e2c, 0x00009030, 0x00010001 }, { 0x00000040, 0x25c43dad, 0x000005c4, 0xfffcfffc }, { 0x00000001, 0x25e20129, 0x00000036, 0x00000000 }, { 0x000b0220, 0x34001c00, 0x02001400, 0x00000178 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000176 }, { 0x00000040, 0x25ca3dad, 0x000005ca, 0xfffcfffc }, { 0x00200401, 0x27e001a1, 0x004505c0, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f000f }, { 0x00000001, 0x22000060, 0x00000000, 0x0288a001 }, { 0x01600031, 0x20c00021, 0x408d07e0, 0x00000200 }, { 0x00200401, 0x27e001a1, 0x004505c8, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00000001, 0x22000060, 0x00000000, 0x02286003 }, { 0x03600031, 0x20800021, 0x408d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00a900c0, 0x00000000 }, { 0x00800801, 0x23900231, 0x00a90100, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00a90140, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00a90180, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00a900c4, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00a90104, 0x00000000 }, { 0x00800401, 0x23e00231, 0x00a90144, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00a90184, 0x00000000 }, { 0x00800401, 0x24000231, 0x00a900c8, 0x00000000 }, { 0x00800801, 0x24100231, 0x00a90108, 0x00000000 }, { 0x00800401, 0x24200231, 0x00a90148, 0x00000000 }, { 0x00800801, 0x24300231, 0x00a90188, 0x00000000 }, { 0x00800401, 0x24400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x24500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x24600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x24700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x20c00231, 0x00cf0380, 0x00000000 }, { 0x00800801, 0x20d00231, 0x00cf0381, 0x00000000 }, { 0x00800401, 0x20e00231, 0x00cf0382, 0x00000000 }, { 0x00800801, 0x20f00231, 0x00cf0383, 0x00000000 }, { 0x00800401, 0x21000231, 0x00cf03c0, 0x00000000 }, { 0x00800801, 0x21100231, 0x00cf03c1, 0x00000000 }, { 0x00800401, 0x21200231, 0x00cf03c2, 0x00000000 }, { 0x00800801, 0x21300231, 0x00cf03c3, 0x00000000 }, { 0x00800401, 0x21400231, 0x00cf0400, 0x00000000 }, { 0x00800801, 0x21500231, 0x00cf0401, 0x00000000 }, { 0x00800401, 0x21600231, 0x00cf0402, 0x00000000 }, { 0x00800801, 0x21700231, 0x00cf0403, 0x00000000 }, { 0x00800401, 0x21800231, 0x00cf0440, 0x00000000 }, { 0x00800801, 0x21900231, 0x00cf0441, 0x00000000 }, { 0x00800401, 0x21a00231, 0x00cf0442, 0x00000000 }, { 0x00800801, 0x21b00231, 0x00cf0443, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00400040 }, { 0x00000008, 0x25e83e2d, 0x00009080, 0x00020002 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x00459080, 0x00000000 }, { 0x00200c01, 0x25d80129, 0x00459050, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699060, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000134 }, { 0x00000008, 0x25e83e2d, 0x00009084, 0x00020002 }, { 0x00200401, 0x25d0022d, 0x00459084, 0x00000000 }, { 0x00000801, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00c000c0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00000401, 0x25d80129, 0x00009040, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699064, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000011e }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00100010 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01000100 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01400140 }, { 0x00000401, 0x25d80129, 0x00009042, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699068, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000110 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01400140 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01800180 }, { 0x00000401, 0x25d80129, 0x00009044, 0x00000000 }, { 0x00400801, 0x25d40231, 0x0069906c, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000102 }, { 0x00200401, 0x27e001a1, 0x004505c4, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f0003 }, { 0x00800401, 0x23400231, 0x00a90040, 0x00000000 }, { 0x00800801, 0x23500231, 0x00a90044, 0x00000000 }, { 0x00800401, 0x23600231, 0x00a90048, 0x00000000 }, { 0x00800801, 0x23700231, 0x00a9004c, 0x00000000 }, { 0x00800001, 0x20400232, 0x002b0340, 0x00000000 }, { 0x00800001, 0x20500232, 0x002b0350, 0x00000000 }, { 0x00800001, 0x20600232, 0x002b0360, 0x00000000 }, { 0x00800001, 0x20700232, 0x002b0370, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x06082003 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00a900c0, 0x00000000 }, { 0x00800801, 0x23900231, 0x00a90100, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00a90140, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00a90180, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00a900c4, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00a90104, 0x00000000 }, { 0x00800401, 0x23e00231, 0x00a90144, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00a90184, 0x00000000 }, { 0x00800401, 0x24000231, 0x00a900c8, 0x00000000 }, { 0x00800801, 0x24100231, 0x00a90108, 0x00000000 }, { 0x00800401, 0x24200231, 0x00a90148, 0x00000000 }, { 0x00800801, 0x24300231, 0x00a90188, 0x00000000 }, { 0x00800401, 0x24400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x24500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x24600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x24700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x20c00231, 0x00cf0380, 0x00000000 }, { 0x00800801, 0x20d00231, 0x00cf0381, 0x00000000 }, { 0x00800401, 0x20e00231, 0x00cf0382, 0x00000000 }, { 0x00800801, 0x20f00231, 0x00cf0383, 0x00000000 }, { 0x00800401, 0x21000231, 0x00cf03c0, 0x00000000 }, { 0x00800801, 0x21100231, 0x00cf03c1, 0x00000000 }, { 0x00800401, 0x21200231, 0x00cf03c2, 0x00000000 }, { 0x00800801, 0x21300231, 0x00cf03c3, 0x00000000 }, { 0x00800401, 0x21400231, 0x00cf0400, 0x00000000 }, { 0x00800801, 0x21500231, 0x00cf0401, 0x00000000 }, { 0x00800401, 0x21600231, 0x00cf0402, 0x00000000 }, { 0x00800801, 0x21700231, 0x00cf0403, 0x00000000 }, { 0x00800401, 0x21800231, 0x00cf0440, 0x00000000 }, { 0x00800801, 0x21900231, 0x00cf0441, 0x00000000 }, { 0x00800401, 0x21a00231, 0x00cf0442, 0x00000000 }, { 0x00800801, 0x21b00231, 0x00cf0443, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00800080 }, { 0x00000008, 0x25e83e2d, 0x00009082, 0x00020002 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00800080 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x00459082, 0x00000000 }, { 0x00200c01, 0x25d80129, 0x00459054, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699070, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000096 }, { 0x00000008, 0x25e83e2d, 0x00009084, 0x00020002 }, { 0x00200401, 0x25d0022d, 0x00459084, 0x00000000 }, { 0x00000801, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00c000c0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00000401, 0x25d80129, 0x00009046, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699074, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000080 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00100010 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01000100 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01400140 }, { 0x00000401, 0x25d80129, 0x00009048, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699078, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000072 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01400140 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01800180 }, { 0x00000401, 0x25d80129, 0x0000904a, 0x00000000 }, { 0x00400801, 0x25d40231, 0x0069907c, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000064 }, { 0x00200401, 0x27e001a1, 0x004505c0, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20400022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x20c00022, 0x008d0140, 0x00000000 }, { 0x00802001, 0x21000022, 0x008d0180, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x12082003 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x00200401, 0x27e001a1, 0x004505c8, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00802001, 0x20400022, 0x008d0080, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x0618a003 }, { 0x01600031, 0x26400021, 0x508d07e0, 0x00000200 }, { 0x00800401, 0x23400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x23500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x23600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x23700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x23800231, 0x00cf0340, 0x00000000 }, { 0x00800801, 0x23900231, 0x00cf0341, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00cf0342, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00cf0343, 0x00000000 }, { 0x00802001, 0x202000a2, 0x008d0380, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x06080020 }, { 0x00600001, 0x26400021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00000440, 0x27e03da1, 0x000005c0, 0x000c000c }, { 0x00000c01, 0x27e401a1, 0x000005c2, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f0003 }, { 0x02600031, 0x23401c25, 0x408d07e0, 0x02286003 }, { 0x00800401, 0x23800231, 0x00cf0340, 0x00000000 }, { 0x00800801, 0x23900231, 0x00cf0341, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00cf0342, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00cf0343, 0x00000000 }, { 0x00802001, 0x202000a2, 0x008d0380, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x06080020 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00800040, 0x2400462d, 0x00b19c00, 0x00b1d830 }, { 0x00800040, 0x2340462d, 0x00b19820, 0x00b1d830 }, { 0x00800040, 0x2360462d, 0x00b19c10, 0x00b1dc00 }, { 0x05810010, 0x200035ac, 0x008d2400, 0x000005d0 }, { 0x05810010, 0x200035ac, 0x008d2340, 0x000005d2 }, { 0x05810010, 0x200035ac, 0x008d2360, 0x000005d2 }, { 0x00818022, 0x34001c00, 0x00001400, 0x000000ca }, { 0x00800040, 0x2440462d, 0x00b19810, 0x00b1d830 }, { 0x00800040, 0x2460462d, 0x00b19c20, 0x00b1dc00 }, { 0x00800201, 0x24a00129, 0x00b19820, 0x00000000 }, { 0x00818022, 0x34001c00, 0x02001400, 0x00000066 }, { 0x05800010, 0x200035ac, 0x028d2400, 0x000005e8 }, { 0x00800040, 0x2520462d, 0x00b19830, 0x00b19820 }, { 0x00800040, 0x2540462d, 0x00b19c00, 0x00b19c10 }, { 0x00000201, 0x26000108, 0x00000602, 0x00000000 }, { 0x05810010, 0x200035ac, 0x028d2440, 0x000005d2 }, { 0x05810010, 0x200035ac, 0x008d2460, 0x000005d2 }, { 0x00818022, 0x34001c00, 0x02001400, 0x0000001e }, { 0x00800040, 0x2560462d, 0x00b19810, 0x00b19800 }, { 0x00800040, 0x238045ad, 0x008d0520, 0x00b19c00 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00040004 }, { 0x00800040, 0x23a0458d, 0x00b10400, 0x00b19810 }, { 0x00800048, 0x24003dac, 0x008d0560, 0x00020002 }, { 0x80800008, 0x43c03d91, 0x00b10400, 0x00030003 }, { 0x00800040, 0x24003dac, 0x00b103a0, 0xfffefffe }, { 0x80800008, 0x43603d91, 0x00b10400, 0x00020002 }, { 0x00800040, 0x2400362c, 0x00b19c10, 0x00b10380 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00b103a0 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00030003 }, { 0x00800001, 0xb8100231, 0x00ae03c0, 0x00000000 }, { 0x00800001, 0xb8200231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0xb8300231, 0x00ae0340, 0x00000000 }, { 0x00808024, 0x34001c00, 0x00001400, 0x0001000e }, { 0x00800040, 0x2400362c, 0x00b19820, 0x008d0520 }, { 0x00800040, 0x2400458c, 0x00b10400, 0x00b19c10 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00020002 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00020002 }, { 0x00800001, 0xb8300231, 0x00ae0340, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00818022, 0x34001c00, 0x00001400, 0x0000001e }, { 0x00800040, 0x2580462d, 0x00b19c20, 0x00b19c30 }, { 0x00800040, 0x238045ad, 0x008d0540, 0x008d04b0 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00040004 }, { 0x00800040, 0x23a0458d, 0x00b10400, 0x00b19c20 }, { 0x00800048, 0x24003dac, 0x008d0580, 0x00020002 }, { 0x80800008, 0x43c03d91, 0x00b10400, 0x00030003 }, { 0x00800040, 0x24003dac, 0x00b103a0, 0xfffefffe }, { 0x80800008, 0x43603d91, 0x00b10400, 0x00020002 }, { 0x00800040, 0x2400362c, 0x008d04a0, 0x00b10380 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00b103a0 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00030003 }, { 0x00800001, 0xbc200231, 0x00ae03c0, 0x00000000 }, { 0x00800001, 0xbc100231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0xbc000231, 0x00ae0340, 0x00000000 }, { 0x00808024, 0x34001c00, 0x00001400, 0x0001000e }, { 0x00800040, 0x2400362c, 0x008d04a0, 0x008d0540 }, { 0x00800040, 0x2400458c, 0x00b10400, 0x00b19c10 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00020002 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00020002 }, { 0x00800001, 0xbc000231, 0x00ae0340, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00808024, 0x34001c00, 0x00001400, 0x0001005c }, { 0x00800201, 0x23e0022d, 0x002805d4, 0x00000000 }, { 0x00800201, 0x23c0022d, 0x002805d4, 0x00000000 }, { 0x05800010, 0x200035ac, 0x008d2440, 0x000005d2 }, { 0x05800010, 0x200035ac, 0x028d2460, 0x000005d2 }, { 0x00800040, 0x24003e2c, 0x00b19820, 0x00040004 }, { 0x00800048, 0x24003dac, 0x008d0400, 0x00040004 }, { 0x00800040, 0x2400458c, 0x00b10400, 0x00b1dc10 }, { 0x00800008, 0x23403d8d, 0x00b10400, 0x00030003 }, { 0x00810040, 0x23e03dad, 0x008d03e0, 0x00010001 }, { 0x00200201, 0x25ec018d, 0x00450600, 0x00000000 }, { 0x00810040, 0x23e03dad, 0x028d03e0, 0x00010001 }, { 0x03800010, 0x200035ac, 0x008d0340, 0x008d03e0 }, { 0x05800010, 0x200035ac, 0x028d0340, 0x008d43e0 }, { 0x00800042, 0x24c0462d, 0x00b19830, 0x00b19c00 }, { 0x00810001, 0x234001ad, 0x008d03e0, 0x00000000 }, { 0x00810001, 0x234001ad, 0x028d43e0, 0x00000000 }, { 0x00200201, 0x260001ac, 0x004505ec, 0x00000000 }, { 0x80800040, 0x43603631, 0x00b19830, 0x008d0340 }, { 0x80800040, 0x43403631, 0x00b19c00, 0x008d4340 }, { 0x00800001, 0xb8300231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0xbc000231, 0x00ae0340, 0x00000000 }, { 0x00818022, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00800040, 0x2400362c, 0x00b19810, 0x008d04c0 }, { 0x00800048, 0x24003e2c, 0x00b19820, 0xfffefffe }, { 0x00800008, 0x23603d8d, 0x00b10400, 0x00010001 }, { 0x03800010, 0x200035ac, 0x008d0360, 0x008d03c0 }, { 0x05800010, 0x200035ac, 0x028d0360, 0x008d43c0 }, { 0x00810001, 0x236001ad, 0x008d03c0, 0x00000000 }, { 0x00810001, 0x236001ad, 0x028d43c0, 0x00000000 }, { 0x00000201, 0x260201ac, 0x000005ee, 0x00000000 }, { 0x80800040, 0x43603631, 0x00b19820, 0x008d0360 }, { 0x00800001, 0xb8200231, 0x00ae0360, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00818022, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00800040, 0x2400362c, 0x00b19c20, 0x008d04c0 }, { 0x00800048, 0x24003e2c, 0x00b19c10, 0xfffefffe }, { 0x00800008, 0x23603d8d, 0x00b10400, 0x00010001 }, { 0x03800010, 0x200035ac, 0x008d0360, 0x008d03c0 }, { 0x05800010, 0x200035ac, 0x028d0360, 0x008d43c0 }, { 0x00810001, 0x236001ad, 0x008d03c0, 0x00000000 }, { 0x00810001, 0x236001ad, 0x028d43c0, 0x00000000 }, { 0x80800040, 0x43603631, 0x00b19c10, 0x008d0360 }, { 0x00800001, 0xbc100231, 0x00ae0360, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007c0, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00a02001, 0x20400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x206601ed, 0x00000000, 0x00030003 }, { 0x00000009, 0x20663dad, 0x00000066, 0x000a000a }, { 0x00000001, 0x206801ed, 0x00000000, 0x01400140 }, { 0x00000001, 0x22600169, 0x00000000, 0x00030003 }, { 0x00000008, 0x22403dad, 0x00000026, 0x00010001 }, { 0x00000041, 0x224235ad, 0x00000020, 0x00000022 }, { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, { 0x00000001, 0x203c0022, 0x00000018, 0x00000000 }, { 0x00000001, 0x203f01f2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c00e2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c010a, 0x00000e00, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0020, 0x00000000 }, { 0x00400001, 0x205401ed, 0x00000000, 0x00000000 }, { 0x00200040, 0x20583dad, 0x00450020, 0xffffffff }, { 0x00000001, 0x22000060, 0x00000000, 0x06080000 }, { 0x00600001, 0x26000021, 0x008d0000, 0x00000000 }, { 0x00000001, 0x26140061, 0x00000000, 0x00c00400 }, { 0x00000001, 0x26100169, 0x00000000, 0x12121212 }, { 0x07600031, 0x26201c21, 0x308d0600, 0x02000000 }, { 0x00200401, 0x208000e5, 0x00000000, 0x00000000 }, { 0x00000c01, 0x208800e5, 0x00000000, 0xffffffc4 }, { 0x00000801, 0x208c00e5, 0x00000000, 0xffffffc8 }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00100010 }, { 0x00000001, 0x206001ed, 0x00000000, 0x00020002 }, { 0x00000001, 0x206201ad, 0x0000005a, 0x00000000 }, { 0x00000001, 0x20a001ed, 0x00000000, 0x00000000 }, { 0x00200001, 0x228001ed, 0x00000000, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21000061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21400061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21800061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21c00061, 0x00000000, 0x00ff00ff }, { 0x00000041, 0x22083dac, 0x00000056, 0x00040004 }, { 0x05000010, 0x200035ac, 0x02000280, 0x00000240 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x01000010, 0x20002d28, 0x000090c2, 0x00000000 }, { 0x03000010, 0x200035ac, 0x02000054, 0x00000058 }, { 0x00800001, 0x240001ac, 0x00000068, 0x00000000 }, { 0x00000048, 0x22a03dad, 0x00000056, 0x00040004 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffff2 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00200001, 0xb0c00229, 0x00450054, 0x00000000 }, { 0x00200040, 0x22803dad, 0x00450280, 0x00010001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x20380122, 0x00000260, 0x00000000 }, { 0x00800001, 0x204001ae, 0x00b10040, 0x00000000 }, { 0x00000008, 0x20003d2a, 0x000002a0, 0x00010001 }, { 0x00000040, 0x22602d29, 0x00000260, 0x00020002 }, { 0x00800031, 0x20000008, 0x608d0000, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x04200010, 0x200035ac, 0x00450054, 0x00450060 }, { 0x00010040, 0x20a03dad, 0x02000056, 0x00010001 }, { 0x05200010, 0x200035ac, 0x02450280, 0x00450240 }, { 0x00000001, 0x240001ec, 0x00000000, 0x00040004 }, { 0x00000048, 0x22083dac, 0x00000056, 0x00040004 }, { 0x00200040, 0x205455ad, 0x00450054, 0x00450034 }, { 0x02000010, 0x20003d8c, 0x00000600, 0x00010001 }, { 0x00000041, 0x220e3d8c, 0x00000602, 0x00040004 }, { 0x00010041, 0x22083dac, 0x000000a0, 0x00040004 }, { 0x00010401, 0x205601ad, 0x000000a0, 0x00000000 }, { 0x00010840, 0x20543d2d, 0x000090c0, 0x00010001 }, { 0x00000220, 0x34001400, 0x00001400, 0x00009c80 }, { 0x01000010, 0x20003dac, 0x02000280, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00600401, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000c01, 0x26140061, 0x00000000, 0x01800000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000801, 0x26100169, 0x00000000, 0x12121212 }, { 0x00000040, 0x2078252d, 0x00000026, 0x00004280 }, { 0x00400001, 0x26000231, 0x00000078, 0x00000000 }, { 0x00600031, 0x26201c21, 0x308d0600, 0x02000002 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffffe8 }, { 0x07600031, 0x20001c20, 0x30000000, 0x02000001 }, { 0x01600031, 0x20001c24, 0x708d0000, 0x82000012 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00600009, 0x25c03dad, 0x00050034, 0x00040004 }, { 0x00000001, 0x220801ec, 0x00000000, 0x02400240 }, { 0x00000041, 0x25e435a1, 0x00000020, 0x00000036 }, { 0x00000040, 0x25e43421, 0x000005e4, 0x00000034 }, { 0x00000041, 0x27e82c21, 0x000005e4, 0x00400040 }, { 0x00000001, 0x240001ec, 0x00000000, 0x01400140 }, { 0x00000048, 0x20263dad, 0x00000036, 0x00040004 }, { 0x00000040, 0x25c43dad, 0x000005c4, 0xfffcfffc }, { 0x00000040, 0x25ca3dad, 0x000005ca, 0xfffcfffc }, { 0x00800001, 0x2220022d, 0x000d002c, 0x00000000 }, { 0x00600040, 0x22303dad, 0x008d0230, 0x00080008 }, { 0x01600031, 0x22401c21, 0x408d07e0, 0x02885800 }, { 0x01800005, 0x20002d28, 0x02b19040, 0xffffffff }, { 0x02000005, 0x20003e2c, 0x00009030, 0x00010001 }, { 0x00000001, 0x25e20129, 0x00000036, 0x00000000 }, { 0x000b0220, 0x34001c00, 0x02001400, 0x00000126 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000124 }, { 0x00000401, 0x27e001a1, 0x000005c0, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00000001, 0x22000060, 0x00000000, 0x0248a002 }, { 0x02600031, 0x20c00021, 0x408d07e0, 0x00000200 }, { 0x00000401, 0x27e001a1, 0x000005c8, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005ca, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0001000f }, { 0x00000001, 0x22000060, 0x00000000, 0x02186004 }, { 0x02600031, 0x20800021, 0x408d07e0, 0x00000200 }, { 0x00800001, 0x2380012d, 0x008900c0, 0x00000000 }, { 0x00800001, 0x23a0012d, 0x00890100, 0x00000000 }, { 0x00800001, 0x23c0012d, 0x008900c8, 0x00000000 }, { 0x00800001, 0x23e0012d, 0x00890108, 0x00000000 }, { 0x00600401, 0x20c001a9, 0x00ab0380, 0x00000000 }, { 0x00600801, 0x20d001a9, 0x00ab0382, 0x00000000 }, { 0x00600401, 0x20e001a9, 0x00ab0384, 0x00000000 }, { 0x00600801, 0x20f001a9, 0x00ab0386, 0x00000000 }, { 0x00600401, 0x210001a9, 0x00ab03c0, 0x00000000 }, { 0x00600801, 0x211001a9, 0x00ab03c2, 0x00000000 }, { 0x00600401, 0x212001a9, 0x00ab03c4, 0x00000000 }, { 0x00600801, 0x213001a9, 0x00ab03c6, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00400040 }, { 0x00800008, 0x2340352d, 0x00009050, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x00009052, 0x008d0220 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000020 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x004590c0, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990a0, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000fc }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00410041 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c100c1 }, { 0x00200401, 0x25d0022d, 0x004590c8, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990b0, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000ee }, { 0x00800008, 0x2340352d, 0x00009042, 0x008d0220 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e000e0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00200401, 0x25d0022d, 0x004590c4, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990a4, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x00000001, 0x260201e8, 0x00000000, 0x00000000 }, { 0x00000401, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000801, 0x25d80109, 0x00000600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000d8 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e100e1 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01010101 }, { 0x00200401, 0x25d0022d, 0x004590cc, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990b4, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000ca }, { 0x00000401, 0x27e001a1, 0x000005c4, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c6, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x00070003 }, { 0x00600401, 0x2340012d, 0x00890040, 0x00000000 }, { 0x00600801, 0x2350012d, 0x00890048, 0x00000000 }, { 0x00600001, 0x204001aa, 0x00270340, 0x00000000 }, { 0x00600001, 0x205001aa, 0x00270350, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x04082004 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x00800001, 0x2380012d, 0x008900c0, 0x00000000 }, { 0x00800001, 0x23a0012d, 0x00890100, 0x00000000 }, { 0x00800001, 0x23c0012d, 0x008900c8, 0x00000000 }, { 0x00800001, 0x23e0012d, 0x00890108, 0x00000000 }, { 0x00600401, 0x20c001a9, 0x00ab0380, 0x00000000 }, { 0x00600801, 0x20d001a9, 0x00ab0382, 0x00000000 }, { 0x00600401, 0x20e001a9, 0x00ab0384, 0x00000000 }, { 0x00600801, 0x20f001a9, 0x00ab0386, 0x00000000 }, { 0x00600401, 0x210001a9, 0x00ab03c0, 0x00000000 }, { 0x00600801, 0x211001a9, 0x00ab03c2, 0x00000000 }, { 0x00600401, 0x212001a9, 0x00ab03c4, 0x00000000 }, { 0x00600801, 0x213001a9, 0x00ab03c6, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00800080 }, { 0x00800008, 0x2340352d, 0x00009054, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x00009056, 0x008d0220 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000020 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00800080 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x004590c2, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990a8, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00810081 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c100c1 }, { 0x00200401, 0x25d0022d, 0x004590ca, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990b8, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000078 }, { 0x00800008, 0x2340352d, 0x00009048, 0x008d0220 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e000e0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00200401, 0x25d0022d, 0x004590c4, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990ac, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x00000001, 0x260201e8, 0x00000000, 0x00000000 }, { 0x00000401, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000801, 0x25d80109, 0x00000600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000062 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e100e1 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01010101 }, { 0x00200401, 0x25d0022d, 0x004590cc, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990bc, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000054 }, { 0x00000401, 0x27e001a1, 0x000005c0, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00802001, 0x20400022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x0a082004 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x00000401, 0x27e001a1, 0x000005c8, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005ca, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0001000f }, { 0x00600001, 0x20400022, 0x008d0080, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x0418a004 }, { 0x01600031, 0x26400021, 0x508d07e0, 0x00000200 }, { 0x00600401, 0x2340012d, 0x008500cc, 0x00000000 }, { 0x00600801, 0x2350012d, 0x0085010c, 0x00000000 }, { 0x00800001, 0x236001ad, 0x002e0340, 0x00000000 }, { 0x00600001, 0x202000a2, 0x008d0360, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x04080020 }, { 0x00600001, 0x26400021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00000440, 0x27e03da1, 0x000005c0, 0x000c000c }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x00070003 }, { 0x02600031, 0x23401c25, 0x408d07e0, 0x02186004 }, { 0x00800001, 0x236001ad, 0x002e0340, 0x00000000 }, { 0x00600001, 0x202000a2, 0x008d0360, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x04080020 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00600040, 0x2400462d, 0x00ae9c00, 0x00aed810 }, { 0x00600040, 0x2340462d, 0x00ae9800, 0x00aed810 }, { 0x00600040, 0x2360462d, 0x00ae9c10, 0x00aedc00 }, { 0x05810010, 0x200035ac, 0x008d2400, 0x000005d0 }, { 0x05810010, 0x200035ac, 0x008d2340, 0x000005d2 }, { 0x05810010, 0x200035ac, 0x008d2360, 0x000005d2 }, { 0x00618022, 0x34001c00, 0x00001400, 0x00000038 }, { 0x00618022, 0x34001c00, 0x02001400, 0x00000016 }, { 0x00600040, 0x24003e2c, 0x00ae9c10, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x00ae9800, 0x00020002 }, { 0x00600040, 0x2400458c, 0x008d0400, 0x00ae9810 }, { 0x80600008, 0x43403d91, 0x008d0400, 0x00020002 }, { 0x00600040, 0x24003e2c, 0x00ae9800, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x00ae9c10, 0x00020002 }, { 0x00600040, 0x2400458c, 0x008d0400, 0x00ae9c00 }, { 0x80600008, 0x43603d91, 0x008d0400, 0x00020002 }, { 0x00600001, 0xd8100231, 0x00ae0340, 0x00000000 }, { 0x00600001, 0xdc000231, 0x00ae0360, 0x00000000 }, { 0x00608024, 0x34001c00, 0x00001400, 0x00010020 }, { 0x00600201, 0x2400022c, 0x002405d4, 0x00000000 }, { 0x00600040, 0x23e03d8d, 0x008d0400, 0x00010001 }, { 0x00600040, 0x24003e2c, 0x00ae9800, 0x00040004 }, { 0x00600048, 0x24003dac, 0x008d0400, 0x00040004 }, { 0x00600040, 0x2400458c, 0x008d0400, 0x00aedc10 }, { 0x00600008, 0x23403d8d, 0x008d0400, 0x00030003 }, { 0x03600010, 0x200035ac, 0x008d0340, 0x008d03e0 }, { 0x05600010, 0x200035ac, 0x028d0340, 0x008d43e0 }, { 0x00610001, 0x234001ad, 0x008d03e0, 0x00000000 }, { 0x00610001, 0x234001ad, 0x028d43e0, 0x00000000 }, { 0x80600040, 0x43603631, 0x00ae9810, 0x008d0340 }, { 0x80600040, 0x43403631, 0x00ae9c00, 0x008d4340 }, { 0x00600001, 0xd8100231, 0x00ae0360, 0x00000000 }, { 0x00600001, 0xdc000231, 0x00ae0340, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007c0, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00a02001, 0x20400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x206601ed, 0x00000000, 0x00030003 }, { 0x00000009, 0x20663dad, 0x00000066, 0x000a000a }, { 0x00000008, 0x22403dad, 0x00000026, 0x00010001 }, { 0x00000041, 0x224235ad, 0x00000020, 0x00000022 }, { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, { 0x00000001, 0x203c0022, 0x00000018, 0x00000000 }, { 0x00000001, 0x203f01f2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c00e2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c010a, 0x00000e00, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0020, 0x00000000 }, { 0x00400001, 0x205401ed, 0x00000000, 0x00000000 }, { 0x00200040, 0x20583dad, 0x00450020, 0xffffffff }, { 0x00000001, 0x22000060, 0x00000000, 0x06080000 }, { 0x00600001, 0x26000021, 0x008d0000, 0x00000000 }, { 0x00000001, 0x26140061, 0x00000000, 0x00c00400 }, { 0x00000001, 0x26100169, 0x00000000, 0x12121212 }, { 0x07600031, 0x26201c21, 0x308d0600, 0x02000000 }, { 0x00000001, 0x22a00169, 0x00000000, 0x01400140 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00200020 }, { 0x00000001, 0x203801e2, 0x00000000, 0x00010001 }, { 0x00800001, 0x204001ae, 0x00b10020, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x000002a0, 0x00010001 }, { 0x00800031, 0x20000128, 0x608d07e0, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x22a00169, 0x00000000, 0x00000000 }, { 0x00000001, 0x22600169, 0x00000000, 0x00020002 }, { 0x00200401, 0x208000e5, 0x00000000, 0x00000000 }, { 0x00000c01, 0x208800e5, 0x00000000, 0xffffffc6 }, { 0x00000801, 0x208c00e5, 0x00000000, 0xffffffca }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00100010 }, { 0x00000001, 0x206001ed, 0x00000000, 0x00020002 }, { 0x00000001, 0x206201ad, 0x0000005a, 0x00000000 }, { 0x00000001, 0x20a001ed, 0x00000000, 0x00000000 }, { 0x00200001, 0x228001ed, 0x00000000, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21000061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21400061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21800061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21c00061, 0x00000000, 0x00ff00ff }, { 0x00000041, 0x22083dac, 0x00000056, 0x00040004 }, { 0x05000010, 0x200035ac, 0x02000280, 0x00000240 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x01000010, 0x20002d28, 0x000090c2, 0x00000000 }, { 0x03000010, 0x200035ac, 0x02000054, 0x00000058 }, { 0x00000041, 0x22a03dad, 0x00000056, 0x00040004 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffff4 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00200001, 0xb0c00229, 0x00450054, 0x00000000 }, { 0x00200040, 0x22803dad, 0x00450280, 0x00010001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x20380122, 0x00000260, 0x00000000 }, { 0x00800001, 0x204001ae, 0x00b10040, 0x00000000 }, { 0x00000008, 0x20003d2a, 0x000002a0, 0x00010001 }, { 0x00000040, 0x22602d29, 0x00000260, 0x00020002 }, { 0x00800031, 0x20000008, 0x608d0000, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x04200010, 0x200035ac, 0x00450054, 0x00450060 }, { 0x00010040, 0x20a03dad, 0x02000056, 0x00010001 }, { 0x05200010, 0x200035ac, 0x02450280, 0x00450240 }, { 0x00000001, 0x240001ec, 0x00000000, 0x00040004 }, { 0x00000048, 0x22083dac, 0x00000056, 0x00040004 }, { 0x00200040, 0x205455ad, 0x00450054, 0x00450034 }, { 0x02000010, 0x20003d8c, 0x00000600, 0x00010001 }, { 0x00000041, 0x220e3d8c, 0x00000602, 0x00040004 }, { 0x00010041, 0x22083dac, 0x000000a0, 0x00040004 }, { 0x00010401, 0x205601ad, 0x000000a0, 0x00000000 }, { 0x00010840, 0x20543d2d, 0x000090c0, 0x00010001 }, { 0x00000220, 0x34001400, 0x00001400, 0x00009c80 }, { 0x01000010, 0x20003dac, 0x02000280, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000006 }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffff6 }, { 0x05000010, 0x200035ac, 0x00000240, 0x00000026 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffffc }, { 0x07600031, 0x20001c20, 0x30000000, 0x02000001 }, { 0x01600031, 0x20001c24, 0x708d0000, 0x82000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00600009, 0x25c03dad, 0x00050034, 0x00040004 }, { 0x00000001, 0x220801ec, 0x00000000, 0x02400240 }, { 0x00000041, 0x20263d29, 0x00000036, 0x00040004 }, { 0x00000041, 0x25e435a1, 0x00000020, 0x00000036 }, { 0x00000040, 0x25e43421, 0x000005e4, 0x00000034 }, { 0x00000041, 0x27e82c21, 0x000005e4, 0x00400040 }, { 0x01600031, 0x22401c21, 0x408d07e0, 0x02885800 }, { 0x01800005, 0x20002d28, 0x02b19040, 0xffffffff }, { 0x02000005, 0x20003e2c, 0x00009030, 0x00010001 }, { 0x00000040, 0x25c43dad, 0x000005c4, 0xfffcfffc }, { 0x00000001, 0x25e20129, 0x00000036, 0x00000000 }, { 0x000b0220, 0x34001c00, 0x02001400, 0x0000018c }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000018a }, { 0x00000040, 0x25ca3dad, 0x000005ca, 0xfffcfffc }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c0, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f000f }, { 0x00010001, 0x22000060, 0x02000000, 0x0288e701 }, { 0x00110001, 0x22000060, 0x02000000, 0x0288e601 }, { 0x01600031, 0x20c00021, 0x408d07e0, 0x00000200 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c8, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00010001, 0x22000060, 0x02000000, 0x02286703 }, { 0x00110001, 0x22000060, 0x02000000, 0x02286603 }, { 0x03600031, 0x20800021, 0x408d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00a900c0, 0x00000000 }, { 0x00800801, 0x23900231, 0x00a90100, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00a90140, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00a90180, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00a900c4, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00a90104, 0x00000000 }, { 0x00800401, 0x23e00231, 0x00a90144, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00a90184, 0x00000000 }, { 0x00800401, 0x24000231, 0x00a900c8, 0x00000000 }, { 0x00800801, 0x24100231, 0x00a90108, 0x00000000 }, { 0x00800401, 0x24200231, 0x00a90148, 0x00000000 }, { 0x00800801, 0x24300231, 0x00a90188, 0x00000000 }, { 0x00800401, 0x24400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x24500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x24600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x24700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x20c00231, 0x00cf0380, 0x00000000 }, { 0x00800801, 0x20d00231, 0x00cf0381, 0x00000000 }, { 0x00800401, 0x20e00231, 0x00cf0382, 0x00000000 }, { 0x00800801, 0x20f00231, 0x00cf0383, 0x00000000 }, { 0x00800401, 0x21000231, 0x00cf03c0, 0x00000000 }, { 0x00800801, 0x21100231, 0x00cf03c1, 0x00000000 }, { 0x00800401, 0x21200231, 0x00cf03c2, 0x00000000 }, { 0x00800801, 0x21300231, 0x00cf03c3, 0x00000000 }, { 0x00800401, 0x21400231, 0x00cf0400, 0x00000000 }, { 0x00800801, 0x21500231, 0x00cf0401, 0x00000000 }, { 0x00800401, 0x21600231, 0x00cf0402, 0x00000000 }, { 0x00800801, 0x21700231, 0x00cf0403, 0x00000000 }, { 0x00800401, 0x21800231, 0x00cf0440, 0x00000000 }, { 0x00800801, 0x21900231, 0x00cf0441, 0x00000000 }, { 0x00800401, 0x21a00231, 0x00cf0442, 0x00000000 }, { 0x00800801, 0x21b00231, 0x00cf0443, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00400040 }, { 0x00000008, 0x25e83e2d, 0x00009080, 0x00020002 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x00459080, 0x00000000 }, { 0x00200c01, 0x25d80129, 0x00459050, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699060, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffb8c }, { 0x00000008, 0x25e83e2d, 0x00009084, 0x00020002 }, { 0x00200401, 0x25d0022d, 0x00459084, 0x00000000 }, { 0x00000801, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00c000c0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00000401, 0x25d80129, 0x00009040, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699064, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffb76 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00100010 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01000100 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01400140 }, { 0x00000401, 0x25d80129, 0x00009042, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699068, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffb68 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01400140 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01800180 }, { 0x00000401, 0x25d80129, 0x00009044, 0x00000000 }, { 0x00400801, 0x25d40231, 0x0069906c, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffb5a }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c4, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f0003 }, { 0x00800401, 0x23400231, 0x00a90040, 0x00000000 }, { 0x00800801, 0x23500231, 0x00a90044, 0x00000000 }, { 0x00800401, 0x23600231, 0x00a90048, 0x00000000 }, { 0x00800801, 0x23700231, 0x00a9004c, 0x00000000 }, { 0x00800001, 0x20400232, 0x002b0340, 0x00000000 }, { 0x00800001, 0x20500232, 0x002b0350, 0x00000000 }, { 0x00800001, 0x20600232, 0x002b0360, 0x00000000 }, { 0x00800001, 0x20700232, 0x002b0370, 0x00000000 }, { 0x00010001, 0x22000060, 0x02000000, 0x06082703 }, { 0x00110001, 0x22000060, 0x02000000, 0x06082603 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00a900c0, 0x00000000 }, { 0x00800801, 0x23900231, 0x00a90100, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00a90140, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00a90180, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00a900c4, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00a90104, 0x00000000 }, { 0x00800401, 0x23e00231, 0x00a90144, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00a90184, 0x00000000 }, { 0x00800401, 0x24000231, 0x00a900c8, 0x00000000 }, { 0x00800801, 0x24100231, 0x00a90108, 0x00000000 }, { 0x00800401, 0x24200231, 0x00a90148, 0x00000000 }, { 0x00800801, 0x24300231, 0x00a90188, 0x00000000 }, { 0x00800401, 0x24400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x24500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x24600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x24700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x20c00231, 0x00cf0380, 0x00000000 }, { 0x00800801, 0x20d00231, 0x00cf0381, 0x00000000 }, { 0x00800401, 0x20e00231, 0x00cf0382, 0x00000000 }, { 0x00800801, 0x20f00231, 0x00cf0383, 0x00000000 }, { 0x00800401, 0x21000231, 0x00cf03c0, 0x00000000 }, { 0x00800801, 0x21100231, 0x00cf03c1, 0x00000000 }, { 0x00800401, 0x21200231, 0x00cf03c2, 0x00000000 }, { 0x00800801, 0x21300231, 0x00cf03c3, 0x00000000 }, { 0x00800401, 0x21400231, 0x00cf0400, 0x00000000 }, { 0x00800801, 0x21500231, 0x00cf0401, 0x00000000 }, { 0x00800401, 0x21600231, 0x00cf0402, 0x00000000 }, { 0x00800801, 0x21700231, 0x00cf0403, 0x00000000 }, { 0x00800401, 0x21800231, 0x00cf0440, 0x00000000 }, { 0x00800801, 0x21900231, 0x00cf0441, 0x00000000 }, { 0x00800401, 0x21a00231, 0x00cf0442, 0x00000000 }, { 0x00800801, 0x21b00231, 0x00cf0443, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00800080 }, { 0x00000008, 0x25e83e2d, 0x00009082, 0x00020002 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00800080 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x00459082, 0x00000000 }, { 0x00200c01, 0x25d80129, 0x00459054, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699070, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffaea }, { 0x00000008, 0x25e83e2d, 0x00009084, 0x00020002 }, { 0x00200401, 0x25d0022d, 0x00459084, 0x00000000 }, { 0x00000801, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00c000c0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00000401, 0x25d80129, 0x00009046, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699074, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffad4 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00100010 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01000100 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01400140 }, { 0x00000401, 0x25d80129, 0x00009048, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699078, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffac6 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01400140 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01800180 }, { 0x00000401, 0x25d80129, 0x0000904a, 0x00000000 }, { 0x00400801, 0x25d40231, 0x0069907c, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffab8 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c0, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20400022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x20c00022, 0x008d0140, 0x00000000 }, { 0x00802001, 0x21000022, 0x008d0180, 0x00000000 }, { 0x00010001, 0x22000060, 0x02000000, 0x12082703 }, { 0x00110001, 0x22000060, 0x02000000, 0x12082603 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c8, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00802001, 0x20400022, 0x008d0080, 0x00000000 }, { 0x00010001, 0x22000060, 0x02000000, 0x0618a703 }, { 0x00110001, 0x22000060, 0x02000000, 0x0618a603 }, { 0x01600031, 0x26400021, 0x508d07e0, 0x00000200 }, { 0x00800401, 0x23400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x23500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x23600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x23700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x23800231, 0x00cf0340, 0x00000000 }, { 0x00800801, 0x23900231, 0x00cf0341, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00cf0342, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00cf0343, 0x00000000 }, { 0x00802001, 0x202000a2, 0x008d0380, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x06080020 }, { 0x00600001, 0x26400021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000440, 0x27e03da1, 0x000005c0, 0x000c000c }, { 0x00000c01, 0x27e401a1, 0x000005c2, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f0003 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x02286003 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x00008024, 0x34001c00, 0x00001400, 0x00010008 }, { 0x00010001, 0x22000060, 0x02000000, 0x02286703 }, { 0x00110001, 0x22000060, 0x02000000, 0x02286603 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x02600031, 0x23400025, 0x408d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00cf0340, 0x00000000 }, { 0x00800801, 0x23900231, 0x00cf0341, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00cf0342, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00cf0343, 0x00000000 }, { 0x00802001, 0x202000a2, 0x008d0380, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x06080020 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00a02001, 0x20400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x206601ed, 0x00000000, 0x00030003 }, { 0x00000009, 0x20663dad, 0x00000066, 0x000a000a }, { 0x00000001, 0x206801ed, 0x00000000, 0x01400140 }, { 0x00000001, 0x22600169, 0x00000000, 0x00030003 }, { 0x00000008, 0x22403dad, 0x00000026, 0x00010001 }, { 0x00000041, 0x224235ad, 0x00000020, 0x00000022 }, { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, { 0x00000001, 0x203c0022, 0x00000018, 0x00000000 }, { 0x00000001, 0x203f01f2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c00e2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c010a, 0x00000e00, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0020, 0x00000000 }, { 0x00400001, 0x205401ed, 0x00000000, 0x00000000 }, { 0x00200040, 0x20583dad, 0x00450020, 0xffffffff }, { 0x00000001, 0x22000060, 0x00000000, 0x06080000 }, { 0x00600001, 0x26000021, 0x008d0000, 0x00000000 }, { 0x00000001, 0x26140061, 0x00000000, 0x00c00400 }, { 0x00000001, 0x26100169, 0x00000000, 0x12121212 }, { 0x07600031, 0x26201c21, 0x308d0600, 0x02000000 }, { 0x00200401, 0x208000e5, 0x00000000, 0x00000000 }, { 0x00000c01, 0x208800e5, 0x00000000, 0xffffffc4 }, { 0x00000801, 0x208c00e5, 0x00000000, 0xffffffc8 }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00100010 }, { 0x00000001, 0x206001ed, 0x00000000, 0x00020002 }, { 0x00000001, 0x206201ad, 0x0000005a, 0x00000000 }, { 0x00000001, 0x20a001ed, 0x00000000, 0x00000000 }, { 0x00200001, 0x228001ed, 0x00000000, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21000061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21400061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21800061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21c00061, 0x00000000, 0x00ff00ff }, { 0x00000041, 0x22083dac, 0x00000056, 0x00040004 }, { 0x05000010, 0x200035ac, 0x02000280, 0x00000240 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x01000010, 0x20002d28, 0x000090c2, 0x00000000 }, { 0x03000010, 0x200035ac, 0x02000054, 0x00000058 }, { 0x00800001, 0x240001ac, 0x00000068, 0x00000000 }, { 0x00000048, 0x22a03dad, 0x00000056, 0x00040004 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffff2 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00200001, 0xb0c00229, 0x00450054, 0x00000000 }, { 0x00200040, 0x22803dad, 0x00450280, 0x00010001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x20380122, 0x00000260, 0x00000000 }, { 0x00800001, 0x204001ae, 0x00b10040, 0x00000000 }, { 0x00000008, 0x20003d2a, 0x000002a0, 0x00010001 }, { 0x00000040, 0x22602d29, 0x00000260, 0x00020002 }, { 0x00800031, 0x20000008, 0x608d0000, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x04200010, 0x200035ac, 0x00450054, 0x00450060 }, { 0x00010040, 0x20a03dad, 0x02000056, 0x00010001 }, { 0x05200010, 0x200035ac, 0x02450280, 0x00450240 }, { 0x00000001, 0x240001ec, 0x00000000, 0x00040004 }, { 0x00000048, 0x22083dac, 0x00000056, 0x00040004 }, { 0x00200040, 0x205455ad, 0x00450054, 0x00450034 }, { 0x02000010, 0x20003d8c, 0x00000600, 0x00010001 }, { 0x00000041, 0x220e3d8c, 0x00000602, 0x00040004 }, { 0x00010041, 0x22083dac, 0x000000a0, 0x00040004 }, { 0x00010401, 0x205601ad, 0x000000a0, 0x00000000 }, { 0x00010840, 0x20543d2d, 0x000090c0, 0x00010001 }, { 0x00000220, 0x34001400, 0x00001400, 0x00009c80 }, { 0x01000010, 0x20003dac, 0x02000280, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00600401, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000c01, 0x26140061, 0x00000000, 0x01800000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000801, 0x26100169, 0x00000000, 0x12121212 }, { 0x00000040, 0x2078252d, 0x00000026, 0x00004280 }, { 0x00400001, 0x26000231, 0x00000078, 0x00000000 }, { 0x00600031, 0x26201c21, 0x308d0600, 0x02000002 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffffe8 }, { 0x07600031, 0x20001c20, 0x30000000, 0x02000001 }, { 0x01600031, 0x20001c24, 0x708d0000, 0x82000012 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00600009, 0x25c03dad, 0x00050034, 0x00040004 }, { 0x00000001, 0x220801ec, 0x00000000, 0x02400240 }, { 0x00000041, 0x25e435a1, 0x00000020, 0x00000036 }, { 0x00000040, 0x25e43421, 0x000005e4, 0x00000034 }, { 0x00000041, 0x27e82c21, 0x000005e4, 0x00400040 }, { 0x00000001, 0x240001ec, 0x00000000, 0x01400140 }, { 0x00000048, 0x20263dad, 0x00000036, 0x00040004 }, { 0x00000040, 0x25c43dad, 0x000005c4, 0xfffcfffc }, { 0x00000040, 0x25ca3dad, 0x000005ca, 0xfffcfffc }, { 0x00800001, 0x2220022d, 0x000d002c, 0x00000000 }, { 0x00600040, 0x22303dad, 0x008d0230, 0x00080008 }, { 0x01600031, 0x22401c21, 0x408d07e0, 0x02885800 }, { 0x01800005, 0x20002d28, 0x02b19040, 0xffffffff }, { 0x02000005, 0x20003e2c, 0x00009030, 0x00010001 }, { 0x00000001, 0x25e20129, 0x00000036, 0x00000000 }, { 0x000b0220, 0x34001c00, 0x02001400, 0x0000013a }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000138 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c0, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00010001, 0x22000060, 0x02000000, 0x0248e702 }, { 0x00110001, 0x22000060, 0x02000000, 0x0248e602 }, { 0x02600031, 0x20c00021, 0x408d07e0, 0x00000200 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c8, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005ca, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0001000f }, { 0x00010001, 0x22000060, 0x02000000, 0x02186704 }, { 0x00110001, 0x22000060, 0x02000000, 0x02186604 }, { 0x02600031, 0x20800021, 0x408d07e0, 0x00000200 }, { 0x00800001, 0x2380012d, 0x008900c0, 0x00000000 }, { 0x00800001, 0x23a0012d, 0x00890100, 0x00000000 }, { 0x00800001, 0x23c0012d, 0x008900c8, 0x00000000 }, { 0x00800001, 0x23e0012d, 0x00890108, 0x00000000 }, { 0x00600401, 0x20c001a9, 0x00ab0380, 0x00000000 }, { 0x00600801, 0x20d001a9, 0x00ab0382, 0x00000000 }, { 0x00600401, 0x20e001a9, 0x00ab0384, 0x00000000 }, { 0x00600801, 0x20f001a9, 0x00ab0386, 0x00000000 }, { 0x00600401, 0x210001a9, 0x00ab03c0, 0x00000000 }, { 0x00600801, 0x211001a9, 0x00ab03c2, 0x00000000 }, { 0x00600401, 0x212001a9, 0x00ab03c4, 0x00000000 }, { 0x00600801, 0x213001a9, 0x00ab03c6, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00400040 }, { 0x00800008, 0x2340352d, 0x00009050, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x00009052, 0x008d0220 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000020 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x004590c0, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990a0, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffc0c }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00410041 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c100c1 }, { 0x00200401, 0x25d0022d, 0x004590c8, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990b0, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffbfe }, { 0x00800008, 0x2340352d, 0x00009042, 0x008d0220 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e000e0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00200401, 0x25d0022d, 0x004590c4, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990a4, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x00000001, 0x260201e8, 0x00000000, 0x00000000 }, { 0x00000401, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000801, 0x25d80109, 0x00000600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffbe8 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e100e1 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01010101 }, { 0x00200401, 0x25d0022d, 0x004590cc, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990b4, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffbda }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c4, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c6, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x00070003 }, { 0x00600401, 0x2340012d, 0x00890040, 0x00000000 }, { 0x00600801, 0x2350012d, 0x00890048, 0x00000000 }, { 0x00600001, 0x204001aa, 0x00270340, 0x00000000 }, { 0x00600001, 0x205001aa, 0x00270350, 0x00000000 }, { 0x00010001, 0x22000060, 0x02000000, 0x04082704 }, { 0x00110001, 0x22000060, 0x02000000, 0x04082604 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x00800001, 0x2380012d, 0x008900c0, 0x00000000 }, { 0x00800001, 0x23a0012d, 0x00890100, 0x00000000 }, { 0x00800001, 0x23c0012d, 0x008900c8, 0x00000000 }, { 0x00800001, 0x23e0012d, 0x00890108, 0x00000000 }, { 0x00600401, 0x20c001a9, 0x00ab0380, 0x00000000 }, { 0x00600801, 0x20d001a9, 0x00ab0382, 0x00000000 }, { 0x00600401, 0x20e001a9, 0x00ab0384, 0x00000000 }, { 0x00600801, 0x20f001a9, 0x00ab0386, 0x00000000 }, { 0x00600401, 0x210001a9, 0x00ab03c0, 0x00000000 }, { 0x00600801, 0x211001a9, 0x00ab03c2, 0x00000000 }, { 0x00600401, 0x212001a9, 0x00ab03c4, 0x00000000 }, { 0x00600801, 0x213001a9, 0x00ab03c6, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00800080 }, { 0x00800008, 0x2340352d, 0x00009054, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x00009056, 0x008d0220 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000020 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00800080 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x004590c2, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990a8, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffb92 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00810081 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c100c1 }, { 0x00200401, 0x25d0022d, 0x004590ca, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990b8, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffb84 }, { 0x00800008, 0x2340352d, 0x00009048, 0x008d0220 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e000e0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00200401, 0x25d0022d, 0x004590c4, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990ac, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x00000001, 0x260201e8, 0x00000000, 0x00000000 }, { 0x00000401, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000801, 0x25d80109, 0x00000600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffb6e }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e100e1 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01010101 }, { 0x00200401, 0x25d0022d, 0x004590cc, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990bc, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffb60 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c0, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00802001, 0x20400022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0100, 0x00000000 }, { 0x00010001, 0x22000060, 0x02000000, 0x0a082704 }, { 0x00110001, 0x22000060, 0x02000000, 0x0a082604 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c8, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005ca, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0001000f }, { 0x00600001, 0x20400022, 0x008d0080, 0x00000000 }, { 0x00010001, 0x22000060, 0x02000000, 0x0418a704 }, { 0x00110001, 0x22000060, 0x02000000, 0x0418a604 }, { 0x01600031, 0x26400021, 0x508d07e0, 0x00000200 }, { 0x00600401, 0x2340012d, 0x008500cc, 0x00000000 }, { 0x00600801, 0x2350012d, 0x0085010c, 0x00000000 }, { 0x00800001, 0x236001ad, 0x002e0340, 0x00000000 }, { 0x00600001, 0x202000a2, 0x008d0360, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x04080020 }, { 0x00600001, 0x26400021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000440, 0x27e03da1, 0x000005c0, 0x000c000c }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x00070003 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x02186004 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x00008024, 0x34001c00, 0x00001400, 0x00010008 }, { 0x00010001, 0x22000060, 0x02000000, 0x02186704 }, { 0x00110001, 0x22000060, 0x02000000, 0x02186604 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x02600031, 0x23400025, 0x408d07e0, 0x00000200 }, { 0x00800001, 0x236001ad, 0x002e0340, 0x00000000 }, { 0x00600001, 0x202000a2, 0x008d0360, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x04080020 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00a02001, 0x20400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x206601ed, 0x00000000, 0x00010001 }, { 0x00000009, 0x20663dad, 0x00000066, 0x000a000a }, { 0x00000001, 0x22600169, 0x00000000, 0x00010001 }, { 0x00000008, 0x22403dad, 0x00000026, 0x00010001 }, { 0x00000041, 0x224235ad, 0x00000020, 0x00000022 }, { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, { 0x00000001, 0x203c0022, 0x00000018, 0x00000000 }, { 0x00000001, 0x203f01f2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c00e2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c010a, 0x00000e00, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0020, 0x00000000 }, { 0x00400001, 0x205401ed, 0x00000000, 0x00000000 }, { 0x00200040, 0x20583dad, 0x00450020, 0xffffffff }, { 0x00000001, 0x22000060, 0x00000000, 0x06080000 }, { 0x00600001, 0x26000021, 0x008d0000, 0x00000000 }, { 0x00000001, 0x26140061, 0x00000000, 0x00c00400 }, { 0x00000001, 0x26100169, 0x00000000, 0x12121212 }, { 0x07600031, 0x26201c21, 0x308d0600, 0x02000000 }, { 0x00000001, 0x22a00169, 0x00000000, 0x01400140 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00200020 }, { 0x00000001, 0x203801e2, 0x00000000, 0x00010001 }, { 0x00800001, 0x204001ae, 0x00b10020, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x000002a0, 0x00010001 }, { 0x00800031, 0x20000128, 0x608d07e0, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x22a00169, 0x00000000, 0x00000000 }, { 0x00000001, 0x22600169, 0x00000000, 0x00020002 }, { 0x00200401, 0x208000e5, 0x00000000, 0x00000000 }, { 0x00000c01, 0x208800e5, 0x00000000, 0xffffffc6 }, { 0x00000801, 0x208c00e5, 0x00000000, 0xffffffca }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00100010 }, { 0x00000001, 0x206001ed, 0x00000000, 0x00020002 }, { 0x00000001, 0x206201ad, 0x0000005a, 0x00000000 }, { 0x00000001, 0x20a001ed, 0x00000000, 0x00000000 }, { 0x00200001, 0x228001ed, 0x00000000, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21000061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21400061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21800061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21c00061, 0x00000000, 0x00ff00ff }, { 0x00000041, 0x22083dac, 0x00000056, 0x00040004 }, { 0x05000010, 0x200035ac, 0x02000280, 0x00000240 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x01000010, 0x20002d28, 0x000090c2, 0x00000000 }, { 0x03000010, 0x200035ac, 0x02000054, 0x00000058 }, { 0x00000041, 0x22a03dad, 0x00000056, 0x00040004 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffff4 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00200001, 0xb0c00229, 0x00450054, 0x00000000 }, { 0x00200040, 0x22803dad, 0x00450280, 0x00010001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x20380122, 0x00000260, 0x00000000 }, { 0x00800001, 0x204001ae, 0x00b10040, 0x00000000 }, { 0x00000008, 0x20003d2a, 0x000002a0, 0x00010001 }, { 0x00000040, 0x22602d29, 0x00000260, 0x00020002 }, { 0x00800031, 0x20000008, 0x608d0000, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x04200010, 0x200035ac, 0x00450054, 0x00450060 }, { 0x00010040, 0x20a03dad, 0x02000056, 0x00010001 }, { 0x05200010, 0x200035ac, 0x02450280, 0x00450240 }, { 0x00000001, 0x240001ec, 0x00000000, 0x00040004 }, { 0x00000048, 0x22083dac, 0x00000056, 0x00040004 }, { 0x00200040, 0x205455ad, 0x00450054, 0x00450034 }, { 0x02000010, 0x20003d8c, 0x00000600, 0x00010001 }, { 0x00000041, 0x220e3d8c, 0x00000602, 0x00040004 }, { 0x00010041, 0x22083dac, 0x000000a0, 0x00040004 }, { 0x00010401, 0x205601ad, 0x000000a0, 0x00000000 }, { 0x00010840, 0x20543d2d, 0x000090c0, 0x00010001 }, { 0x00000220, 0x34001400, 0x00001400, 0x00009c80 }, { 0x01000010, 0x20003dac, 0x02000280, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000006 }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffff6 }, { 0x05000010, 0x200035ac, 0x00000240, 0x00000026 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffffc }, { 0x07600031, 0x20001c20, 0x30000000, 0x02000001 }, { 0x01600031, 0x20001c24, 0x708d0000, 0x82000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00400441, 0x45c03dad, 0x00000034, 0x00100010 }, { 0x00400841, 0x45c23dad, 0x00000036, 0x00200020 }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00000001, 0x25e20129, 0x00000036, 0x00000000 }, { 0x00000041, 0x25e435a1, 0x00000020, 0x00000036 }, { 0x00000040, 0x25e43421, 0x000005e4, 0x00000034 }, { 0x00000041, 0x25e42c21, 0x000005e4, 0x00800080 }, { 0x00000040, 0x25c43dad, 0x000005c4, 0xfffcfffc }, { 0x00000040, 0x25ca3dad, 0x000005ca, 0xfffcfffc }, { 0x00000005, 0x202a3dad, 0x0000002a, 0xfffdfffd }, { 0x02000005, 0x20002d2c, 0x0200002a, 0x00020002 }, { 0x00000001, 0x27e80021, 0x000005e4, 0x00000000 }, { 0x00010040, 0x27e83c21, 0x020007e8, 0x00400040 }, { 0x01600031, 0x22401c21, 0x408d07e0, 0x02885800 }, { 0x00000001, 0x220801ec, 0x00000000, 0x02400240 }, { 0x01800005, 0x20002d28, 0x02b19040, 0xffffffff }, { 0x02000005, 0x20003e2c, 0x00009030, 0x00010001 }, { 0x00000005, 0x25ec2e29, 0x00009002, 0x000a000a }, { 0x00000005, 0x25ea2e29, 0x00009002, 0x00060006 }, { 0x000b0220, 0x34001c00, 0x02001400, 0x00000252 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000250 }, { 0x01000010, 0x20003d2c, 0x000005ec, 0x00080008 }, { 0x00000005, 0x25e03d8d, 0x00000600, 0x00010001 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a5, 0x004505c0, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f000f }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x0288a001 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x0288e701 }, { 0x00110001, 0x22000060, 0x02000000, 0x0288e601 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x20c00021, 0x408d07e0, 0x00000200 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c4, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f0003 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x02286003 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x02286703 }, { 0x00110001, 0x22000060, 0x02000000, 0x02286603 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x02600031, 0x23400025, 0x408d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00a900c0, 0x00000000 }, { 0x00800801, 0x23900231, 0x00a90100, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00a90140, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00a90180, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00a900c4, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00a90104, 0x00000000 }, { 0x00800401, 0x23e00231, 0x00a90144, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00a90184, 0x00000000 }, { 0x00800401, 0x24000231, 0x00a900c8, 0x00000000 }, { 0x00800801, 0x24100231, 0x00a90108, 0x00000000 }, { 0x00800401, 0x24200231, 0x00a90148, 0x00000000 }, { 0x00800801, 0x24300231, 0x00a90188, 0x00000000 }, { 0x00800401, 0x24400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x24500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x24600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x24700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x20c00231, 0x00cf0380, 0x00000000 }, { 0x00800801, 0x20d00231, 0x00cf0381, 0x00000000 }, { 0x00800401, 0x20e00231, 0x00cf0382, 0x00000000 }, { 0x00800801, 0x20f00231, 0x00cf0383, 0x00000000 }, { 0x00800401, 0x21000231, 0x00cf03c0, 0x00000000 }, { 0x00800801, 0x21100231, 0x00cf03c1, 0x00000000 }, { 0x00800401, 0x21200231, 0x00cf03c2, 0x00000000 }, { 0x00800801, 0x21300231, 0x00cf03c3, 0x00000000 }, { 0x00800401, 0x21400231, 0x00cf0400, 0x00000000 }, { 0x00800801, 0x21500231, 0x00cf0401, 0x00000000 }, { 0x00800401, 0x21600231, 0x00cf0402, 0x00000000 }, { 0x00800801, 0x21700231, 0x00cf0403, 0x00000000 }, { 0x00800401, 0x21800231, 0x00cf0440, 0x00000000 }, { 0x00800801, 0x21900231, 0x00cf0441, 0x00000000 }, { 0x00800401, 0x21a00231, 0x00cf0442, 0x00000000 }, { 0x00800801, 0x21b00231, 0x00cf0443, 0x00000000 }, { 0x00800401, 0x20400231, 0x00cf0340, 0x00000000 }, { 0x00800801, 0x20500231, 0x00cf0341, 0x00000000 }, { 0x00800401, 0x20600231, 0x00cf0342, 0x00000000 }, { 0x00800801, 0x20700231, 0x00cf0343, 0x00000000 }, { 0x01600010, 0x20003d2c, 0x000005ea, 0x00040004 }, { 0x01600010, 0x20003d2c, 0x020005ea, 0x00020002 }, { 0x00800001, 0x21c00229, 0x00009080, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00009081, 0x00000000 }, { 0x00800001, 0x22000229, 0x00289060, 0x00000000 }, { 0x00610401, 0x41c00229, 0x00009080, 0x00000000 }, { 0x00610801, 0x41c20229, 0x00009090, 0x00000000 }, { 0x00610401, 0x41e00229, 0x00009081, 0x00000000 }, { 0x00610801, 0x41e20229, 0x00009091, 0x00000000 }, { 0x00610401, 0x42000229, 0x00249060, 0x00000000 }, { 0x00610801, 0x42020229, 0x00249098, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00400040 }, { 0x00610401, 0x21c00229, 0x02009080, 0x00000000 }, { 0x00610801, 0x21d00229, 0x02009090, 0x00000000 }, { 0x00610401, 0x21e00229, 0x02009081, 0x00000000 }, { 0x00610801, 0x21f00229, 0x02009091, 0x00000000 }, { 0x00610401, 0x22000229, 0x02249060, 0x00000000 }, { 0x00610801, 0x22100229, 0x02249098, 0x00000000 }, { 0x00800008, 0x25a03d29, 0x008d01c0, 0x00020002 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200001, 0x25d80129, 0x00459050, 0x00000000 }, { 0x00800040, 0x25a03d29, 0x00b105a0, 0x00020002 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001b4 }, { 0x00800008, 0x25a03e29, 0x00009084, 0x00020002 }, { 0x00800001, 0x21c00229, 0x00009084, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00009085, 0x00000000 }, { 0x00000001, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00800040, 0x25a03d29, 0x00b105a0, 0x00020002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00c000c0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00000001, 0x25d80129, 0x00009040, 0x00000000 }, { 0x00800001, 0x22000229, 0x00289064, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000019c }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00100010 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01000100 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01400140 }, { 0x00000001, 0x25d80129, 0x00009042, 0x00000000 }, { 0x00800001, 0x22000229, 0x00289068, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000018e }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01400140 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01800180 }, { 0x00000001, 0x25d80129, 0x00009044, 0x00000000 }, { 0x00800001, 0x22000229, 0x0028906c, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000180 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c4, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f0003 }, { 0x00800401, 0x23400231, 0x00a90040, 0x00000000 }, { 0x00800801, 0x23500231, 0x00a90044, 0x00000000 }, { 0x00800401, 0x23600231, 0x00a90048, 0x00000000 }, { 0x00800801, 0x23700231, 0x00a9004c, 0x00000000 }, { 0x00800001, 0x20400232, 0x002b0340, 0x00000000 }, { 0x00800001, 0x20500232, 0x002b0350, 0x00000000 }, { 0x00800001, 0x20600232, 0x002b0360, 0x00000000 }, { 0x00800001, 0x20700232, 0x002b0370, 0x00000000 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x06082003 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x06082703 }, { 0x00110001, 0x22000060, 0x02000000, 0x06082603 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c8, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x22000060, 0x00000000, 0x02286003 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x01000005, 0x20003dac, 0x020005e0, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000006 }, { 0x00000440, 0x27e43ca5, 0x000007e4, 0xfffcfffc }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00000040, 0x22000c00, 0x00000200, 0x00200000 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000c }, { 0x0000000c, 0x27e43da5, 0x000005c2, 0x00010001 }, { 0x00010001, 0x22000060, 0x02000000, 0x02286703 }, { 0x00110001, 0x22000060, 0x02000000, 0x02286603 }, { 0x00000040, 0x27e43ca5, 0x000007e4, 0xfffcfffc }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x20400021, 0x408d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00a900c0, 0x00000000 }, { 0x00800801, 0x23900231, 0x00a90100, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00a90140, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00a90180, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00a900c4, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00a90104, 0x00000000 }, { 0x00800401, 0x23e00231, 0x00a90144, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00a90184, 0x00000000 }, { 0x00800401, 0x24000231, 0x00a900c8, 0x00000000 }, { 0x00800801, 0x24100231, 0x00a90108, 0x00000000 }, { 0x00800401, 0x24200231, 0x00a90148, 0x00000000 }, { 0x00800801, 0x24300231, 0x00a90188, 0x00000000 }, { 0x00800401, 0x24400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x24500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x24600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x24700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x20c00231, 0x00cf0380, 0x00000000 }, { 0x00800801, 0x20d00231, 0x00cf0381, 0x00000000 }, { 0x00800401, 0x20e00231, 0x00cf0382, 0x00000000 }, { 0x00800801, 0x20f00231, 0x00cf0383, 0x00000000 }, { 0x00800401, 0x21000231, 0x00cf03c0, 0x00000000 }, { 0x00800801, 0x21100231, 0x00cf03c1, 0x00000000 }, { 0x00800401, 0x21200231, 0x00cf03c2, 0x00000000 }, { 0x00800801, 0x21300231, 0x00cf03c3, 0x00000000 }, { 0x00800401, 0x21400231, 0x00cf0400, 0x00000000 }, { 0x00800801, 0x21500231, 0x00cf0401, 0x00000000 }, { 0x00800401, 0x21600231, 0x00cf0402, 0x00000000 }, { 0x00800801, 0x21700231, 0x00cf0403, 0x00000000 }, { 0x00800401, 0x21800231, 0x00cf0440, 0x00000000 }, { 0x00800801, 0x21900231, 0x00cf0441, 0x00000000 }, { 0x00800401, 0x21a00231, 0x00cf0442, 0x00000000 }, { 0x00800801, 0x21b00231, 0x00cf0443, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00800080 }, { 0x00000001, 0x260201ac, 0x000005e0, 0x00000000 }, { 0x00800008, 0x25a03e29, 0x00009082, 0x00020002 }, { 0x00200001, 0x25d80129, 0x00459054, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00009082, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00009083, 0x00000000 }, { 0x00800001, 0x22000229, 0x00289070, 0x00000000 }, { 0x00800040, 0x25a03d29, 0x00b105a0, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000050 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000a }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000d4 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000044 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x05000500 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x05400540 }, { 0x00800001, 0x25000129, 0x00ad0040, 0x00000000 }, { 0x00800001, 0x25200129, 0x00ad0080, 0x00000000 }, { 0x00800001, 0x25400129, 0x00ad00c0, 0x00000000 }, { 0x00800001, 0x25600129, 0x00ad0100, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000c2 }, { 0x00600001, 0x20600129, 0x008d0510, 0x00000000 }, { 0x00600001, 0x20800129, 0x008d0520, 0x00000000 }, { 0x00600001, 0x20a00129, 0x008d0530, 0x00000000 }, { 0x00600001, 0x20c00129, 0x008d0540, 0x00000000 }, { 0x00600001, 0x20e00129, 0x008d0550, 0x00000000 }, { 0x00600001, 0x21000129, 0x008d0560, 0x00000000 }, { 0x00800008, 0x25a03e29, 0x00009092, 0x00020002 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x05000500 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x05400540 }, { 0x00800001, 0x25000129, 0x00ad0050, 0x00000000 }, { 0x00800001, 0x25200129, 0x00ad0090, 0x00000000 }, { 0x00800001, 0x25400129, 0x00ad00d0, 0x00000000 }, { 0x00800001, 0x25600129, 0x00ad0110, 0x00000000 }, { 0x00200001, 0x25d80129, 0x0045905c, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00009092, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00009093, 0x00000000 }, { 0x00800001, 0x22000229, 0x0028909c, 0x00000000 }, { 0x00800040, 0x25a03d29, 0x00b105a0, 0x00020002 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000009a }, { 0x00600001, 0x20700129, 0x008d0510, 0x00000000 }, { 0x00600001, 0x20900129, 0x008d0520, 0x00000000 }, { 0x00600001, 0x20b00129, 0x008d0530, 0x00000000 }, { 0x00600001, 0x20d00129, 0x008d0540, 0x00000000 }, { 0x00600001, 0x20f00129, 0x008d0550, 0x00000000 }, { 0x00600001, 0x21100129, 0x008d0560, 0x00000000 }, { 0x00800008, 0x25a03e29, 0x00009084, 0x00020002 }, { 0x00800001, 0x21c00229, 0x00009084, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00009085, 0x00000000 }, { 0x00000001, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00800040, 0x25a03d29, 0x00b105a0, 0x00020002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00c000c0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00000001, 0x25d80129, 0x00009046, 0x00000000 }, { 0x00800001, 0x22000229, 0x00289074, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000076 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00100010 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01000100 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01400140 }, { 0x00000001, 0x25d80129, 0x00009048, 0x00000000 }, { 0x00800001, 0x22000229, 0x00289078, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000068 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01400140 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01800180 }, { 0x00000001, 0x25d80129, 0x0000904a, 0x00000000 }, { 0x00800001, 0x22000229, 0x0028907c, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000005a }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c0, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20400022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x20c00022, 0x008d0140, 0x00000000 }, { 0x00802001, 0x21000022, 0x008d0180, 0x00000000 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x12082003 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x12082703 }, { 0x00110001, 0x22000060, 0x02000000, 0x12082603 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x01800005, 0x20003dac, 0x020005e0, 0x00010001 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c8, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00812001, 0x20400022, 0x028d0040, 0x00000000 }, { 0x00912001, 0x20400022, 0x028d0080, 0x00000000 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x0618a003 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000c }, { 0x0000000c, 0x27e43da5, 0x000005c2, 0x00010001 }, { 0x00010001, 0x22000060, 0x02000000, 0x0618a703 }, { 0x00110001, 0x22000060, 0x02000000, 0x0618a603 }, { 0x00000040, 0x27e43ca5, 0x000007e4, 0xfffcfffc }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x26400021, 0x508d07e0, 0x00000200 }, { 0x01000005, 0x20003dac, 0x0000002a, 0x00020002 }, { 0x00000006, 0x202a3dad, 0x0000002a, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffd94 }, { 0x00600001, 0x26400021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00800040, 0x2400462d, 0x00b19c00, 0x00b1d830 }, { 0x00800040, 0x2340462d, 0x00b19820, 0x00b1d830 }, { 0x00800040, 0x2360462d, 0x00b19c10, 0x00b1dc00 }, { 0x05810010, 0x200025ac, 0x008d2400, 0x008d01c0 }, { 0x05810010, 0x200025ac, 0x008d2340, 0x008d01e0 }, { 0x05810010, 0x200025ac, 0x008d2360, 0x008d01e0 }, { 0x00818022, 0x34001c00, 0x00001400, 0x000000c8 }, { 0x00800040, 0x2440462d, 0x00b19810, 0x00b1d830 }, { 0x00800040, 0x2460462d, 0x00b19c20, 0x00b1dc00 }, { 0x00800201, 0x24a00129, 0x00b19820, 0x00000000 }, { 0x00818022, 0x34001c00, 0x02001400, 0x00000066 }, { 0x05800010, 0x200025ac, 0x028d2400, 0x008d05a0 }, { 0x00800040, 0x2520462d, 0x00b19830, 0x00b19820 }, { 0x00800040, 0x2540462d, 0x00b19c00, 0x00b19c10 }, { 0x00000201, 0x26000108, 0x00000602, 0x00000000 }, { 0x05810010, 0x200025ac, 0x028d2440, 0x008d01e0 }, { 0x05810010, 0x200025ac, 0x008d2460, 0x008d01e0 }, { 0x00818022, 0x34001c00, 0x02001400, 0x0000001e }, { 0x00800040, 0x2560462d, 0x00b19810, 0x00b19800 }, { 0x00800040, 0x238045ad, 0x008d0520, 0x00b19c00 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00040004 }, { 0x00800040, 0x23a0458d, 0x00b10400, 0x00b19810 }, { 0x00800048, 0x24003dac, 0x008d0560, 0x00020002 }, { 0x80800008, 0x43c03d91, 0x00b10400, 0x00030003 }, { 0x00800040, 0x24003dac, 0x00b103a0, 0xfffefffe }, { 0x80800008, 0x43603d91, 0x00b10400, 0x00020002 }, { 0x00800040, 0x2400362c, 0x00b19c10, 0x00b10380 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00b103a0 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00030003 }, { 0x00800001, 0xb8100231, 0x00ae03c0, 0x00000000 }, { 0x00800001, 0xb8200231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0xb8300231, 0x00ae0340, 0x00000000 }, { 0x00808024, 0x34001c00, 0x00001400, 0x0001000e }, { 0x00800040, 0x2400362c, 0x00b19820, 0x008d0520 }, { 0x00800040, 0x2400458c, 0x00b10400, 0x00b19c10 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00020002 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00020002 }, { 0x00800001, 0xb8300231, 0x00ae0340, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00818022, 0x34001c00, 0x00001400, 0x0000001e }, { 0x00800040, 0x2580462d, 0x00b19c20, 0x00b19c30 }, { 0x00800040, 0x238045ad, 0x008d0540, 0x008d04b0 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00040004 }, { 0x00800040, 0x23a0458d, 0x00b10400, 0x00b19c20 }, { 0x00800048, 0x24003dac, 0x008d0580, 0x00020002 }, { 0x80800008, 0x43c03d91, 0x00b10400, 0x00030003 }, { 0x00800040, 0x24003dac, 0x00b103a0, 0xfffefffe }, { 0x80800008, 0x43603d91, 0x00b10400, 0x00020002 }, { 0x00800040, 0x2400362c, 0x008d04a0, 0x00b10380 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00b103a0 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00030003 }, { 0x00800001, 0xbc200231, 0x00ae03c0, 0x00000000 }, { 0x00800001, 0xbc100231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0xbc000231, 0x00ae0340, 0x00000000 }, { 0x00808024, 0x34001c00, 0x00001400, 0x0001000e }, { 0x00800040, 0x2400362c, 0x008d04a0, 0x008d0540 }, { 0x00800040, 0x2400458c, 0x00b10400, 0x00b19c10 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00020002 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00020002 }, { 0x00800001, 0xbc000231, 0x00ae0340, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00808024, 0x34001c00, 0x00001400, 0x0001005a }, { 0x00800001, 0x23e0012d, 0x008d0200, 0x00000000 }, { 0x05800010, 0x200025ac, 0x008d2440, 0x008d01e0 }, { 0x05800010, 0x200025ac, 0x028d2460, 0x008d01e0 }, { 0x00800040, 0x24003e2c, 0x00b19820, 0x00040004 }, { 0x00800048, 0x24003dac, 0x008d0400, 0x00040004 }, { 0x00800040, 0x2400458c, 0x00b10400, 0x00b1dc10 }, { 0x00800008, 0x23403d8d, 0x00b10400, 0x00030003 }, { 0x00810040, 0x23e03dad, 0x008d03e0, 0x00010001 }, { 0x00200201, 0x25ec018d, 0x00450600, 0x00000000 }, { 0x00810040, 0x23e03dad, 0x028d03e0, 0x00010001 }, { 0x03800010, 0x200035ac, 0x008d0340, 0x008d03e0 }, { 0x05800010, 0x200035ac, 0x028d0340, 0x008d43e0 }, { 0x00800042, 0x24c0462d, 0x00b19830, 0x00b19c00 }, { 0x00810001, 0x234001ad, 0x008d03e0, 0x00000000 }, { 0x00810001, 0x234001ad, 0x028d43e0, 0x00000000 }, { 0x00200201, 0x260001ac, 0x004505ec, 0x00000000 }, { 0x80800040, 0x43603631, 0x00b19830, 0x008d0340 }, { 0x80800040, 0x43403631, 0x00b19c00, 0x008d4340 }, { 0x00800001, 0xb8300231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0xbc000231, 0x00ae0340, 0x00000000 }, { 0x00818022, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00800040, 0x2400362c, 0x00b19810, 0x008d04c0 }, { 0x00800048, 0x24003e2c, 0x00b19820, 0xfffefffe }, { 0x00800008, 0x23603d8d, 0x00b10400, 0x00010001 }, { 0x03800010, 0x200025ac, 0x008d0360, 0x008d0200 }, { 0x05800010, 0x200025ac, 0x028d0360, 0x008d4200 }, { 0x00810001, 0x2360012d, 0x008d0200, 0x00000000 }, { 0x00810001, 0x2360012d, 0x028d4200, 0x00000000 }, { 0x00000201, 0x260201ac, 0x000005ee, 0x00000000 }, { 0x80800040, 0x43603631, 0x00b19820, 0x008d0360 }, { 0x00800001, 0xb8200231, 0x00ae0360, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00818022, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00800040, 0x2400362c, 0x00b19c20, 0x008d04c0 }, { 0x00800048, 0x24003e2c, 0x00b19c10, 0xfffefffe }, { 0x00800008, 0x23603d8d, 0x00b10400, 0x00010001 }, { 0x03800010, 0x200025ac, 0x008d0360, 0x008d0200 }, { 0x05800010, 0x200025ac, 0x028d0360, 0x008d4200 }, { 0x00810001, 0x2360012d, 0x008d0200, 0x00000000 }, { 0x00810001, 0x2360012d, 0x028d4200, 0x00000000 }, { 0x80800040, 0x43603631, 0x00b19c10, 0x008d0360 }, { 0x00800001, 0xbc100231, 0x00ae0360, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007c0, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00a02001, 0x20400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x206601ed, 0x00000000, 0x00010001 }, { 0x00000009, 0x20663dad, 0x00000066, 0x000a000a }, { 0x00000001, 0x206801ed, 0x00000000, 0x01400140 }, { 0x00000001, 0x22600169, 0x00000000, 0x00030003 }, { 0x00000008, 0x22403dad, 0x00000026, 0x00010001 }, { 0x00000041, 0x224235ad, 0x00000020, 0x00000022 }, { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, { 0x00000001, 0x203c0022, 0x00000018, 0x00000000 }, { 0x00000001, 0x203f01f2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c00e2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c010a, 0x00000e00, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0020, 0x00000000 }, { 0x00400001, 0x205401ed, 0x00000000, 0x00000000 }, { 0x00200040, 0x20583dad, 0x00450020, 0xffffffff }, { 0x00000001, 0x22000060, 0x00000000, 0x06080000 }, { 0x00600001, 0x26000021, 0x008d0000, 0x00000000 }, { 0x00000001, 0x26140061, 0x00000000, 0x00c00400 }, { 0x00000001, 0x26100169, 0x00000000, 0x12121212 }, { 0x07600031, 0x26201c21, 0x308d0600, 0x02000000 }, { 0x00200401, 0x208000e5, 0x00000000, 0x00000000 }, { 0x00000c01, 0x208800e5, 0x00000000, 0xffffffc4 }, { 0x00000801, 0x208c00e5, 0x00000000, 0xffffffc8 }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00100010 }, { 0x00000001, 0x206001ed, 0x00000000, 0x00020002 }, { 0x00000001, 0x206201ad, 0x0000005a, 0x00000000 }, { 0x00000001, 0x20a001ed, 0x00000000, 0x00000000 }, { 0x00200001, 0x228001ed, 0x00000000, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21000061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21400061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21800061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21c00061, 0x00000000, 0x00ff00ff }, { 0x00000041, 0x22083dac, 0x00000056, 0x00040004 }, { 0x05000010, 0x200035ac, 0x02000280, 0x00000240 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x01000010, 0x20002d28, 0x000090c2, 0x00000000 }, { 0x03000010, 0x200035ac, 0x02000054, 0x00000058 }, { 0x00800001, 0x240001ac, 0x00000068, 0x00000000 }, { 0x00000048, 0x22a03dad, 0x00000056, 0x00040004 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffff2 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00200001, 0xb0c00229, 0x00450054, 0x00000000 }, { 0x00200040, 0x22803dad, 0x00450280, 0x00010001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x20380122, 0x00000260, 0x00000000 }, { 0x00800001, 0x204001ae, 0x00b10040, 0x00000000 }, { 0x00000008, 0x20003d2a, 0x000002a0, 0x00010001 }, { 0x00000040, 0x22602d29, 0x00000260, 0x00020002 }, { 0x00800031, 0x20000008, 0x608d0000, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x04200010, 0x200035ac, 0x00450054, 0x00450060 }, { 0x00010040, 0x20a03dad, 0x02000056, 0x00010001 }, { 0x05200010, 0x200035ac, 0x02450280, 0x00450240 }, { 0x00000001, 0x240001ec, 0x00000000, 0x00040004 }, { 0x00000048, 0x22083dac, 0x00000056, 0x00040004 }, { 0x00200040, 0x205455ad, 0x00450054, 0x00450034 }, { 0x02000010, 0x20003d8c, 0x00000600, 0x00010001 }, { 0x00000041, 0x220e3d8c, 0x00000602, 0x00040004 }, { 0x00010041, 0x22083dac, 0x000000a0, 0x00040004 }, { 0x00010401, 0x205601ad, 0x000000a0, 0x00000000 }, { 0x00010840, 0x20543d2d, 0x000090c0, 0x00010001 }, { 0x00000220, 0x34001400, 0x00001400, 0x00009c80 }, { 0x01000010, 0x20003dac, 0x02000280, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00600401, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000c01, 0x26140061, 0x00000000, 0x01800000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000801, 0x26100169, 0x00000000, 0x12121212 }, { 0x00000040, 0x2078252d, 0x00000026, 0x00004280 }, { 0x00400001, 0x26000231, 0x00000078, 0x00000000 }, { 0x00600031, 0x26201c21, 0x308d0600, 0x02000002 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffffe8 }, { 0x07600031, 0x20001c20, 0x30000000, 0x02000001 }, { 0x01600031, 0x20001c24, 0x708d0000, 0x82000012 }, { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00400441, 0x45c03dad, 0x00000034, 0x00100010 }, { 0x00400841, 0x45c23dad, 0x00000036, 0x00200020 }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00000001, 0x25e20129, 0x00000036, 0x00000000 }, { 0x00000041, 0x25e435a1, 0x00000020, 0x00000036 }, { 0x00000040, 0x25e43421, 0x000005e4, 0x00000034 }, { 0x00000041, 0x25e42c21, 0x000005e4, 0x00800080 }, { 0x00000040, 0x25c43dad, 0x000005c4, 0xfffcfffc }, { 0x00000040, 0x25ca3dad, 0x000005ca, 0xfffcfffc }, { 0x00000005, 0x202a3dad, 0x0000002a, 0xfffdfffd }, { 0x00800001, 0x2220022d, 0x000d002c, 0x00000000 }, { 0x00600040, 0x22303dad, 0x008d0230, 0x00080008 }, { 0x02000005, 0x20002d2c, 0x0200002a, 0x00020002 }, { 0x00000001, 0x27e80021, 0x000005e4, 0x00000000 }, { 0x00010040, 0x27e83c21, 0x020007e8, 0x00400040 }, { 0x01600031, 0x22401c21, 0x408d07e0, 0x02885800 }, { 0x00000001, 0x220801ec, 0x00000000, 0x02400240 }, { 0x01800005, 0x20002d28, 0x02b19040, 0xffffffff }, { 0x02000005, 0x20003e2c, 0x00009030, 0x00010001 }, { 0x00000005, 0x25ec2e29, 0x00009002, 0x000a000a }, { 0x00000005, 0x25ea2e29, 0x00009002, 0x00060006 }, { 0x000b0220, 0x34001c00, 0x02001400, 0x00000252 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000250 }, { 0x01000010, 0x20003d2c, 0x000005ec, 0x00080008 }, { 0x00000005, 0x25e03d8d, 0x00000600, 0x00010001 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c0, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x0248a002 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x0248e702 }, { 0x00110001, 0x22000060, 0x02000000, 0x0248e602 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x02600031, 0x20c00021, 0x408d07e0, 0x00000200 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c4, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c6, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x00070003 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x02186004 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x02186704 }, { 0x00110001, 0x22000060, 0x02000000, 0x02186604 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x02600031, 0x23400025, 0x408d07e0, 0x00000200 }, { 0x00800001, 0x2380012d, 0x008900c0, 0x00000000 }, { 0x00800001, 0x23a0012d, 0x00890100, 0x00000000 }, { 0x00800001, 0x23c0012d, 0x008900c8, 0x00000000 }, { 0x00800001, 0x23e0012d, 0x00890108, 0x00000000 }, { 0x00600401, 0x20c001a9, 0x00ab0380, 0x00000000 }, { 0x00600801, 0x20d001a9, 0x00ab0382, 0x00000000 }, { 0x00600401, 0x20e001a9, 0x00ab0384, 0x00000000 }, { 0x00600801, 0x20f001a9, 0x00ab0386, 0x00000000 }, { 0x00600401, 0x210001a9, 0x00ab03c0, 0x00000000 }, { 0x00600801, 0x211001a9, 0x00ab03c2, 0x00000000 }, { 0x00600401, 0x212001a9, 0x00ab03c4, 0x00000000 }, { 0x00600801, 0x213001a9, 0x00ab03c6, 0x00000000 }, { 0x00800001, 0x204001a9, 0x002e0340, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00400040 }, { 0x01000010, 0x20003d2c, 0x020005ea, 0x00040004 }, { 0x00800008, 0x2340352d, 0x00009050, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x00009052, 0x008d0220 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000006a }, { 0x01000010, 0x20003d2c, 0x000005ea, 0x00020002 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x02600005, 0x20003dac, 0x00650340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02650360, 0x00010001 }, { 0x00400401, 0x41c00229, 0x000090c0, 0x00000000 }, { 0x00400801, 0x41c20229, 0x000090e0, 0x00000000 }, { 0x00400401, 0x41e00229, 0x000090c1, 0x00000000 }, { 0x00400801, 0x41e20229, 0x000090e1, 0x00000000 }, { 0x00400401, 0x42000229, 0x006990a0, 0x00000000 }, { 0x00400801, 0x42020229, 0x006990e8, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000012 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00400401, 0x21c00229, 0x000090c0, 0x00000000 }, { 0x00400801, 0x21c80229, 0x000090e0, 0x00000000 }, { 0x00400401, 0x21e00229, 0x000090c1, 0x00000000 }, { 0x00400801, 0x21e80229, 0x000090e1, 0x00000000 }, { 0x00400401, 0x22000229, 0x006990a0, 0x00000000 }, { 0x00400801, 0x22080229, 0x006990e8, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000a }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00600001, 0x21c00229, 0x000090c0, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090c1, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490a0, 0x00000000 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001c8 }, { 0x01400010, 0x20003d2c, 0x000005ea, 0x00040004 }, { 0x01400010, 0x20003d2c, 0x020005ea, 0x00020002 }, { 0x00600001, 0x21c00229, 0x000090c8, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090c9, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490b0, 0x00000000 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00410041 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c100c1 }, { 0x00410401, 0x41c00229, 0x000090c8, 0x00000000 }, { 0x00410801, 0x41c20229, 0x000090f0, 0x00000000 }, { 0x00410401, 0x41e00229, 0x000090c9, 0x00000000 }, { 0x00410801, 0x41e20229, 0x000090f1, 0x00000000 }, { 0x00410401, 0x42000229, 0x006990b0, 0x00000000 }, { 0x00410801, 0x42020229, 0x006990f8, 0x00000000 }, { 0x00410401, 0x21c00229, 0x020090c8, 0x00000000 }, { 0x00410801, 0x21c80229, 0x020090f0, 0x00000000 }, { 0x00410401, 0x21e00229, 0x020090c9, 0x00000000 }, { 0x00410801, 0x21e80229, 0x020090f1, 0x00000000 }, { 0x00410401, 0x22000229, 0x026990b0, 0x00000000 }, { 0x00410801, 0x22080229, 0x026990f8, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000019c }, { 0x00800008, 0x2340352d, 0x00009042, 0x008d0220 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e000e0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00600001, 0x21c00229, 0x000090c4, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090c5, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490a4, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x00000001, 0x260201e8, 0x00000000, 0x00000000 }, { 0x00000401, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000801, 0x25d80109, 0x00000600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000184 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e100e1 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01010101 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00600001, 0x21c00229, 0x000090cc, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090cd, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490b4, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000174 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c4, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c6, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x00070003 }, { 0x00600401, 0x2340012d, 0x00890040, 0x00000000 }, { 0x00600801, 0x2350012d, 0x00890048, 0x00000000 }, { 0x00600001, 0x204001aa, 0x00270340, 0x00000000 }, { 0x00600001, 0x205001aa, 0x00270350, 0x00000000 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x04082004 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x04082704 }, { 0x00110001, 0x22000060, 0x02000000, 0x04082604 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c8, 0x00000000 }, { 0x00000c0c, 0x27e43da5, 0x000005ca, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0001000f }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x22000060, 0x00000000, 0x02186004 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x01000005, 0x20003dac, 0x020005e0, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000006 }, { 0x00000440, 0x27e43ca5, 0x000007e4, 0xfffefffe }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00000040, 0x22000c00, 0x00000200, 0x00100000 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000c }, { 0x0000000c, 0x27e43da5, 0x000005c2, 0x00020002 }, { 0x00010001, 0x22000060, 0x02000000, 0x02186704 }, { 0x00110001, 0x22000060, 0x02000000, 0x02186604 }, { 0x00000040, 0x27e43ca5, 0x000007e4, 0xfffefffe }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x02600031, 0x20400021, 0x408d07e0, 0x00000200 }, { 0x00800001, 0x2380012d, 0x008900c0, 0x00000000 }, { 0x00800001, 0x23a0012d, 0x00890100, 0x00000000 }, { 0x00800001, 0x23c0012d, 0x008900c8, 0x00000000 }, { 0x00800001, 0x23e0012d, 0x00890108, 0x00000000 }, { 0x00600401, 0x20c001a9, 0x00ab0380, 0x00000000 }, { 0x00600801, 0x20d001a9, 0x00ab0382, 0x00000000 }, { 0x00600401, 0x20e001a9, 0x00ab0384, 0x00000000 }, { 0x00600801, 0x20f001a9, 0x00ab0386, 0x00000000 }, { 0x00600401, 0x210001a9, 0x00ab03c0, 0x00000000 }, { 0x00600801, 0x211001a9, 0x00ab03c2, 0x00000000 }, { 0x00600401, 0x212001a9, 0x00ab03c4, 0x00000000 }, { 0x00600801, 0x213001a9, 0x00ab03c6, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00800080 }, { 0x00000001, 0x260201ac, 0x000005e0, 0x00000000 }, { 0x00800008, 0x2340352d, 0x00009054, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x00009056, 0x008d0220 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000084 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000026 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00600001, 0x21c00229, 0x000090c2, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090c3, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490a8, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000f0 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00410041 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c100c1 }, { 0x00600001, 0x21c00229, 0x000090ca, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090cb, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490b8, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000e0 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000005c }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x05000500 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x05200520 }, { 0x00800001, 0x25000129, 0x00ad0040, 0x00000000 }, { 0x00800001, 0x25200129, 0x00ad00c0, 0x00000000 }, { 0x00600001, 0x21c00229, 0x000090c2, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090c3, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490a8, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000c6 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x05010501 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x05210521 }, { 0x00600001, 0x21c00229, 0x000090ca, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090cb, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490b8, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000b6 }, { 0x00800008, 0x2340352d, 0x0000905c, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x0000905e, 0x008d0220 }, { 0x00600001, 0x20600129, 0x008d0510, 0x00000000 }, { 0x00600001, 0x20c00129, 0x008d0520, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x05000500 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x05200520 }, { 0x00800001, 0x25000129, 0x00ad0050, 0x00000000 }, { 0x00800001, 0x25200129, 0x00ad00d0, 0x00000000 }, { 0x00600001, 0x21c00229, 0x000090e2, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090e3, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490ec, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000096 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x05010501 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x05210521 }, { 0x00600001, 0x21c00229, 0x000090f2, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090f3, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490fc, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00600001, 0x20700129, 0x008d0510, 0x00000000 }, { 0x00600001, 0x20d00129, 0x008d0520, 0x00000000 }, { 0x00800008, 0x2340352d, 0x00009048, 0x008d0220 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e000e0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00600001, 0x21c00229, 0x000090c4, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090c5, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490ac, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x00000001, 0x260201e8, 0x00000000, 0x00000000 }, { 0x00000401, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000801, 0x25d80109, 0x00000600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000006a }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e100e1 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01010101 }, { 0x00600001, 0x21c00229, 0x000090cc, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090cd, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490bc, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000005a }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c0, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00802001, 0x20400022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0100, 0x00000000 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x0a082004 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x0a082704 }, { 0x00110001, 0x22000060, 0x02000000, 0x0a082604 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x01600005, 0x20003dac, 0x020005e0, 0x00010001 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c8, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005ca, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0001000f }, { 0x00610001, 0x20400022, 0x028d0040, 0x00000000 }, { 0x00710001, 0x20400022, 0x028d0060, 0x00000000 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x0418a004 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000c }, { 0x0000000c, 0x27e43da5, 0x000005c2, 0x00020002 }, { 0x00010001, 0x22000060, 0x02000000, 0x0418a704 }, { 0x00110001, 0x22000060, 0x02000000, 0x0418a604 }, { 0x00000040, 0x27e43ca5, 0x000007e4, 0xfffefffe }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x26400021, 0x508d07e0, 0x00000200 }, { 0x01000005, 0x20003dac, 0x0000002a, 0x00020002 }, { 0x00000006, 0x202a3dad, 0x0000002a, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffd94 }, { 0x00600001, 0x26400021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00600040, 0x2400462d, 0x00ae9c00, 0x00aed810 }, { 0x00600040, 0x2340462d, 0x00ae9800, 0x00aed810 }, { 0x00600040, 0x2360462d, 0x00ae9c10, 0x00aedc00 }, { 0x05810010, 0x200025ac, 0x008d2400, 0x008d01c0 }, { 0x05810010, 0x200025ac, 0x008d2340, 0x008d01e0 }, { 0x05810010, 0x200025ac, 0x008d2360, 0x008d01e0 }, { 0x00618022, 0x34001c00, 0x00001400, 0x00000036 }, { 0x00618022, 0x34001c00, 0x02001400, 0x00000016 }, { 0x00600040, 0x24003e2c, 0x00ae9c10, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x00ae9800, 0x00020002 }, { 0x00600040, 0x2400458c, 0x008d0400, 0x00ae9810 }, { 0x80600008, 0x43403d91, 0x008d0400, 0x00020002 }, { 0x00600040, 0x24003e2c, 0x00ae9800, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x00ae9c10, 0x00020002 }, { 0x00600040, 0x2400458c, 0x008d0400, 0x00ae9c00 }, { 0x80600008, 0x43603d91, 0x008d0400, 0x00020002 }, { 0x00600001, 0xd8100231, 0x00ae0340, 0x00000000 }, { 0x00600001, 0xdc000231, 0x00ae0360, 0x00000000 }, { 0x00608024, 0x34001c00, 0x00001400, 0x0001001e }, { 0x00600040, 0x23e03d2d, 0x008d0200, 0x00010001 }, { 0x00600040, 0x24003e2c, 0x00ae9800, 0x00040004 }, { 0x00600048, 0x24003dac, 0x008d0400, 0x00040004 }, { 0x00600040, 0x2400458c, 0x008d0400, 0x00aedc10 }, { 0x00600008, 0x23403d8d, 0x008d0400, 0x00030003 }, { 0x03600010, 0x200035ac, 0x008d0340, 0x008d03e0 }, { 0x05600010, 0x200035ac, 0x028d0340, 0x008d43e0 }, { 0x00610001, 0x234001ad, 0x008d03e0, 0x00000000 }, { 0x00610001, 0x234001ad, 0x028d43e0, 0x00000000 }, { 0x80600040, 0x43603631, 0x00ae9810, 0x008d0340 }, { 0x80600040, 0x43403631, 0x00ae9c00, 0x008d4340 }, { 0x00600001, 0xd8100231, 0x00ae0360, 0x00000000 }, { 0x00600001, 0xdc000231, 0x00ae0340, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007c0, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/h264/mc/avc_mc.g4b.gen5000066400000000000000000010640451231401140700221070ustar00rootroot00000000000000 { 0x00600001, 0x27c00021, 0x008d0000, 0x00000000 }, { 0x00200009, 0x27fa3e29, 0x00450064, 0x00040004 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000d4 }, { 0x00000005, 0x220e3e2c, 0x00000070, 0x000f000f }, { 0x00000001, 0x26a00221, 0x00009c38, 0x00000000 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006a0 }, { 0x00a02001, 0x24000229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x24400229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x24800229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x24c00229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x25000229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x25400229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x25800229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x25c00229, 0x00b10624, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000001, 0x22080060, 0x00000000, 0x06440640 }, { 0x00a02001, 0x24000229, 0x00009003, 0x00000000 }, { 0x00a02001, 0x24400229, 0x0000900b, 0x00000000 }, { 0x00a02001, 0x24800229, 0x00009013, 0x00000000 }, { 0x00a02001, 0x24c00229, 0x0000901b, 0x00000000 }, { 0x00a02001, 0x25000229, 0x00009023, 0x00000000 }, { 0x00a02001, 0x25400229, 0x0000902b, 0x00000000 }, { 0x00a02001, 0x25800229, 0x00009033, 0x00000000 }, { 0x00a02001, 0x25c00229, 0x0000903b, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000072 }, { 0x02600005, 0x20000c20, 0x0000006c, 0x00000002 }, { 0x00600005, 0x24000c20, 0x0000006c, 0x00000011 }, { 0x01600007, 0x20000c00, 0x028d0400, 0x00000011 }, { 0x00780001, 0x26240169, 0x00000000, 0x80808080 }, { 0x00780001, 0x66430231, 0x028d0624, 0x00000000 }, { 0x00780001, 0x66630231, 0x028d062c, 0x00000000 }, { 0x00780001, 0x26240231, 0x00cf0643, 0x00000000 }, { 0x00780001, 0x262c0231, 0x00cf0663, 0x00000000 }, { 0x00800040, 0x25e04629, 0x00cf0643, 0x00b10624 }, { 0x00600040, 0x25e02529, 0x008d05e0, 0x008d05f0 }, { 0x00400040, 0x25e02529, 0x006905e0, 0x006905e8 }, { 0x00200040, 0x25e02529, 0x004505e0, 0x004505e4 }, { 0x00a02040, 0x2400252c, 0x000005e0, 0x000005e2 }, { 0x00a02040, 0x24003d8c, 0x00b10400, 0x00100010 }, { 0x00a02008, 0x24003d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x24403d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x24803d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x24c03d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x25003d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x25403d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x25803d89, 0x00b10400, 0x00050005 }, { 0x00a02008, 0x25c03d89, 0x00b10400, 0x00050005 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000044 }, { 0x00600041, 0x26806e2d, 0x008d062c, 0x89abcdef }, { 0x00600041, 0x26906e2d, 0x008d0623, 0xfedcba98 }, { 0x00600041, 0x26a06e2d, 0x00cf0663, 0x89abcdef }, { 0x00600041, 0x26b06e2d, 0x00cf0643, 0x0fedcba9 }, { 0x00000041, 0x26be3e2d, 0x00000623, 0xfff8fff8 }, { 0x00802040, 0x268035ad, 0x008d4680, 0x008d0690 }, { 0x00802040, 0x268035ad, 0x008d0680, 0x008d0688 }, { 0x00802040, 0x268035ad, 0x008d0680, 0x008d0684 }, { 0x00802040, 0x268035ad, 0x008d0680, 0x008d0682 }, { 0x00800001, 0x240001ec, 0x00000000, 0x00200020 }, { 0x00200048, 0x24003dac, 0x00a00680, 0x00050005 }, { 0x00200008, 0x26e03d8d, 0x00450400, 0x00060006 }, { 0x00800001, 0x240001ec, 0x00000000, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x00000633, 0x00100010 }, { 0x00800048, 0x26c03e2d, 0x0000067f, 0x00100010 }, { 0x00800048, 0x272055ad, 0x000006e0, 0x00b10040 }, { 0x00600041, 0x268055ad, 0x000006e2, 0x00ae0040 }, { 0x00600041, 0x26a055ad, 0x000006e2, 0x00ae0041 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b00680 }, { 0x80a02008, 0x44003d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b00682 }, { 0x80a02008, 0x44403d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b00684 }, { 0x80a02008, 0x44803d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b00686 }, { 0x80a02008, 0x44c03d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b00688 }, { 0x80a02008, 0x45003d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b0068a }, { 0x80a02008, 0x45403d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b0068c }, { 0x80a02008, 0x45803d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00b0068e }, { 0x80a02008, 0x45c03d91, 0x00b10400, 0x00050005 }, { 0x00000001, 0x22040060, 0x00000000, 0x00900080 }, { 0x01000005, 0x20000c20, 0x02000068, 0x00003c00 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000020 }, { 0x80802040, 0x440045b1, 0x008d8800, 0x00ae0400 }, { 0x80802040, 0x444045b1, 0x008d8820, 0x00ae0440 }, { 0x80802040, 0x448045b1, 0x008d8840, 0x00ae0480 }, { 0x80802040, 0x44c045b1, 0x008d8860, 0x00ae04c0 }, { 0x80802040, 0x441045b1, 0x008d8880, 0x00ae0410 }, { 0x80802040, 0x445045b1, 0x008d88a0, 0x00ae0450 }, { 0x80802040, 0x449045b1, 0x008d88c0, 0x00ae0490 }, { 0x80802040, 0x44d045b1, 0x008d88e0, 0x00ae04d0 }, { 0x80802040, 0x450045b1, 0x008d8900, 0x00ae0500 }, { 0x80802040, 0x454045b1, 0x008d8920, 0x00ae0540 }, { 0x80802040, 0x458045b1, 0x008d8940, 0x00ae0580 }, { 0x80802040, 0x45c045b1, 0x008d8960, 0x00ae05c0 }, { 0x80802040, 0x451045b1, 0x008d8980, 0x00ae0510 }, { 0x80802040, 0x455045b1, 0x008d89a0, 0x00ae0550 }, { 0x80802040, 0x459045b1, 0x008d89c0, 0x00ae0590 }, { 0x80802040, 0x45d045b1, 0x008d89e0, 0x00ae05d0 }, { 0x00000040, 0x22040c00, 0x00000204, 0x01800180 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000e2 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x27800021, 0x00000780, 0x00000000 }, { 0x00000001, 0x27a00021, 0x000007a0, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00200440, 0x27c055a5, 0x004507fa, 0x0045002a }, { 0x00000801, 0x27c80061, 0x00000000, 0x0000001b }, { 0x00000040, 0x22000d20, 0x00000062, 0x02186000 }, { 0x01600031, 0x26200021, 0x408d07c0, 0x00000200 }, { 0x00000440, 0x27c43ca5, 0x000007c4, 0x00010001 }, { 0x00000801, 0x27c80061, 0x00000000, 0x000f0003 }, { 0x00000040, 0x22000c00, 0x00000200, 0x00100000 }, { 0x02600031, 0x26400021, 0x408d07c0, 0x00000200 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00000008, 0x27fc3dad, 0x000007fc, 0x00010001 }, { 0x00200440, 0x27c055a5, 0x004507fa, 0x0045002a }, { 0x00000801, 0x27c80061, 0x00000000, 0x00000013 }, { 0x00000040, 0x22000c00, 0x00000200, 0xefffc001 }, { 0x01600031, 0x26200021, 0x408d07c0, 0x00000200 }, { 0x00000440, 0x27c43ca5, 0x000007c4, 0x00010001 }, { 0x00000801, 0x27c80061, 0x00000000, 0x00070003 }, { 0x05600031, 0x26400021, 0x408d07c0, 0x00000200 }, { 0x00000008, 0x220e3e2c, 0x0000006c, 0x00060006 }, { 0x00000001, 0x26a002a5, 0x00009c3c, 0x00000000 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006a0 }, { 0x02600005, 0x20000c20, 0x0000006c, 0x00000002 }, { 0x00780001, 0x26240169, 0x00000000, 0x80808080 }, { 0x02400005, 0x20000c20, 0x0200006c, 0x00000001 }, { 0x00560001, 0x46420129, 0x02690624, 0x00000000 }, { 0x02400005, 0x20000c20, 0x0200006c, 0x00000010 }, { 0x00560001, 0x46520129, 0x0269062c, 0x00000000 }, { 0x00780001, 0x26240129, 0x00ae0642, 0x00000000 }, { 0x00800040, 0x24004629, 0x00b10624, 0x00650642 }, { 0x00600040, 0x24002529, 0x00650400, 0x00650404 }, { 0x00600040, 0x25202529, 0x00050400, 0x00050404 }, { 0x00600040, 0x25702529, 0x00050408, 0x0005040c }, { 0x00560001, 0x26240169, 0x00000000, 0x80808080 }, { 0x00460001, 0x26240129, 0x028a0652, 0x00000000 }, { 0x00560001, 0x46520129, 0x02690624, 0x00000000 }, { 0x02400005, 0x20000c20, 0x0200006c, 0x00000001 }, { 0x00560001, 0x46420169, 0x02000000, 0x80808080 }, { 0x00460001, 0x46420129, 0x0069062c, 0x00000000 }, { 0x00560001, 0x262c0129, 0x008a0642, 0x00000000 }, { 0x00600040, 0x24004629, 0x008d0624, 0x00650652 }, { 0x00600040, 0x24104629, 0x00650642, 0x008d062c }, { 0x00600040, 0x24002529, 0x00650400, 0x00650404 }, { 0x00600040, 0x25302529, 0x00050408, 0x0005040c }, { 0x00600040, 0x25602529, 0x00050400, 0x00050404 }, { 0x00a02040, 0x24003d2c, 0x00b10520, 0x00040004 }, { 0x00a02008, 0x24003d89, 0x00b10400, 0x00030003 }, { 0x00a02008, 0x24403d89, 0x00b10400, 0x00030003 }, { 0x00a02040, 0x24003d2c, 0x00b10560, 0x00040004 }, { 0x00a02008, 0x24803d89, 0x00b10400, 0x00030003 }, { 0x00a02008, 0x24c03d89, 0x00b10400, 0x00030003 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x22080060, 0x00000000, 0x06440640 }, { 0x00a02001, 0x24000229, 0x00059002, 0x00000000 }, { 0x00a02001, 0x24400229, 0x0005900a, 0x00000000 }, { 0x00a02001, 0x24800229, 0x00059012, 0x00000000 }, { 0x00a02001, 0x24c00229, 0x0005901a, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000003c }, { 0x00a02001, 0x24000229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x24400229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x24800229, 0x00b10624, 0x00000000 }, { 0x00a02001, 0x24c00229, 0x00b10624, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000032 }, { 0x00600041, 0x26806e2d, 0x008d062c, 0x44332211 }, { 0x00600041, 0x26906e2d, 0x008d0622, 0xffeeddcc }, { 0x00600041, 0x26a06e2d, 0x00650652, 0x44332211 }, { 0x00600041, 0x26b06e2d, 0x00650642, 0x00ffeedd }, { 0x00200041, 0x26bc3e2d, 0x00450622, 0xfffcfffc }, { 0x00802040, 0x268035ad, 0x008d0680, 0x008d0690 }, { 0x00802040, 0x268035ad, 0x008d0680, 0x008d0688 }, { 0x00802040, 0x268035ad, 0x008d0680, 0x008d0684 }, { 0x00800001, 0x240001ec, 0x00000000, 0x00200020 }, { 0x00400048, 0x24003dac, 0x00a50680, 0x00220022 }, { 0x00400008, 0x26e03d8d, 0x00690400, 0x00060006 }, { 0x00800001, 0x240001ec, 0x00000000, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x00050632, 0x00100010 }, { 0x00800048, 0x26c03e2d, 0x0005065e, 0x00100010 }, { 0x00800048, 0x272055ad, 0x000506e0, 0x00240044 }, { 0x00600041, 0x268055ad, 0x000506e4, 0x00440044 }, { 0x00600041, 0x26a055ad, 0x000506e4, 0x00440045 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00050680 }, { 0x80a02008, 0x44003d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00050684 }, { 0x80a02008, 0x44403d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x00050688 }, { 0x80a02008, 0x44803d91, 0x00b10400, 0x00050005 }, { 0x00a02040, 0x240035ac, 0x00b10720, 0x0005068c }, { 0x80a02008, 0x44c03d91, 0x00b10400, 0x00050005 }, { 0x00000040, 0x22063d8c, 0x00000204, 0x00100010 }, { 0x80802040, 0x640045b1, 0x008d8880, 0x00cf0400 }, { 0x80802040, 0x644045b1, 0x008d88a0, 0x00cf0440 }, { 0x80802040, 0x648045b1, 0x008d88c0, 0x00cf0480 }, { 0x80802040, 0x64c045b1, 0x008d88e0, 0x00cf04c0 }, { 0x80802040, 0x640245b1, 0x008d8900, 0x00cf0402 }, { 0x80802040, 0x644245b1, 0x008d8920, 0x00cf0442 }, { 0x80802040, 0x648245b1, 0x008d8940, 0x00cf0482 }, { 0x80802040, 0x64c245b1, 0x008d8960, 0x00cf04c2 }, { 0x00000401, 0x27c80061, 0x00000000, 0x0007000f }, { 0x00200801, 0x27c001a1, 0x004507fa, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00000200, 0x08004000 }, { 0x00800001, 0x20400232, 0x00d20400, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20420, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20440, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d20460, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d20480, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d204a0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d204c0, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d204e0, 0x00000000 }, { 0x01600031, 0x27a00021, 0x508d07c0, 0x00000200 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00000401, 0x27c80061, 0x00000000, 0x000f000f }, { 0x00200801, 0x27c001a1, 0x004507fa, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00000200, 0x0ff04000 }, { 0x00000001, 0x22080060, 0x00000000, 0x04400400 }, { 0x00a02001, 0x20400232, 0x00d29000, 0x00000000 }, { 0x00a02001, 0x20500232, 0x00d29020, 0x00000000 }, { 0x00a02001, 0x20800232, 0x00d29080, 0x00000000 }, { 0x00a02001, 0x20900232, 0x00d290a0, 0x00000000 }, { 0x00a02001, 0x20c00232, 0x00d29100, 0x00000000 }, { 0x00a02001, 0x20d00232, 0x00d29120, 0x00000000 }, { 0x00a02001, 0x21000232, 0x00d29180, 0x00000000 }, { 0x00a02001, 0x21100232, 0x00d291a0, 0x00000000 }, { 0x01600031, 0x27800021, 0x508d07c0, 0x00000200 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00600001, 0x27c00021, 0x008d0000, 0x00000000 }, { 0x00200009, 0x27fa3e29, 0x00450064, 0x00040004 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff04 }, { 0x00000001, 0x220401ec, 0x00000000, 0x00800080 }, { 0x00000001, 0x22080060, 0x00000000, 0x04100400 }, { 0x00200008, 0x27006e2d, 0x0000006c, 0x00000040 }, { 0x00400001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x272001a9, 0x00b10620, 0x00000000 }, { 0x02600005, 0x20001c20, 0x0000006c, 0x00000008 }, { 0x00110001, 0x27230231, 0x00000624, 0x00000000 }, { 0x00600001, 0x27420231, 0x00cf0643, 0x00000000 }, { 0x00110001, 0x27410231, 0x00000643, 0x00000000 }, { 0x00240001, 0x27400231, 0x00000623, 0x00000000 }, { 0x02000005, 0x20001c20, 0x0200006c, 0x00000002 }, { 0x00010001, 0x27400231, 0x02000624, 0x00000000 }, { 0x02000005, 0x20001c20, 0x0200006c, 0x00000001 }, { 0x00110001, 0x27420231, 0x02000623, 0x00000000 }, { 0x00000005, 0x26803e2d, 0x00000070, 0x000f000f }, { 0x00000001, 0x270801ad, 0x00000700, 0x00000000 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000084 }, { 0x00000040, 0x22043d8c, 0x00000204, 0x00800080 }, { 0x00800001, 0x27200231, 0x00b10628, 0x00000000 }, { 0x02600005, 0x20001c20, 0x0200006c, 0x00000004 }, { 0x00680001, 0x272c0231, 0x028d0634, 0x00000000 }, { 0x00780001, 0x272c0231, 0x02000633, 0x00000000 }, { 0x00400001, 0x27420231, 0x00a0040e, 0x00000000 }, { 0x00400001, 0x27460231, 0x00a0044e, 0x00000000 }, { 0x00200001, 0x27400231, 0x0000062b, 0x00000000 }, { 0x02000005, 0x20001c20, 0x0200006c, 0x00000002 }, { 0x00010001, 0x27400231, 0x0200062c, 0x00000000 }, { 0x00110001, 0x27410231, 0x0200040e, 0x00000000 }, { 0x00000008, 0x26803e2d, 0x00000070, 0x00040004 }, { 0x00200040, 0x22083d8c, 0x00450208, 0x00800080 }, { 0x00000006, 0x27083dad, 0x00000700, 0x00010001 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000064 }, { 0x00000040, 0x22043d8c, 0x00000204, 0x00800080 }, { 0x00a02001, 0xb3800231, 0x00d20400, 0x00000000 }, { 0x00a02001, 0xb3a00231, 0x00d20480, 0x00000000 }, { 0x00a02001, 0xb3c00231, 0x00d20440, 0x00000000 }, { 0x00a02001, 0xb3e00231, 0x00d204c0, 0x00000000 }, { 0x02000005, 0x20001c20, 0x00000060, 0x00000002 }, { 0x01000005, 0x20001c20, 0x0200006c, 0x00000001 }, { 0x01010005, 0x20001c20, 0x00000060, 0x00004000 }, { 0x02010005, 0x20001c20, 0x02000060, 0x00000010 }, { 0x00030001, 0x27230231, 0x0000065f, 0x00000000 }, { 0x00030220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02600005, 0x20001c20, 0x0000006c, 0x00000001 }, { 0x00460001, 0x27200231, 0x0069065c, 0x00000000 }, { 0x00110001, 0x27230231, 0x00000458, 0x00000000 }, { 0x00600001, 0x27240231, 0x008d0458, 0x00000000 }, { 0x00600001, 0x272c0231, 0x008d0478, 0x00000000 }, { 0x00600001, 0x27420231, 0x00cf0663, 0x00000000 }, { 0x00000001, 0x27400231, 0x00000458, 0x00000000 }, { 0x00010001, 0x27410231, 0x0000065f, 0x00000000 }, { 0x00110001, 0x27410231, 0x00000663, 0x00000000 }, { 0x02000005, 0x20001c20, 0x0200006c, 0x00000010 }, { 0x00110001, 0x27420231, 0x0200065f, 0x00000000 }, { 0x00000005, 0x26803e2d, 0x00000071, 0x000f000f }, { 0x00000006, 0x27083dad, 0x00000702, 0x00020002 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000040, 0x22043d8c, 0x00000204, 0x00800080 }, { 0x00400001, 0x27200231, 0x0069045c, 0x00000000 }, { 0x00600001, 0x27240231, 0x008d0478, 0x00000000 }, { 0x00800001, 0x272c0231, 0x0000047f, 0x00000000 }, { 0x00400001, 0x27420231, 0x00a0048e, 0x00000000 }, { 0x00400001, 0x27460231, 0x00a004ce, 0x00000000 }, { 0x00000001, 0x27400231, 0x00000478, 0x00000000 }, { 0x00000001, 0x27410231, 0x0000045f, 0x00000000 }, { 0x00000008, 0x26803e2d, 0x00000071, 0x00040004 }, { 0x00200040, 0x22083d8c, 0x00450208, 0x00800080 }, { 0x00000006, 0x27083dad, 0x00000700, 0x00030003 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00a02001, 0xb3800231, 0x00d20480, 0x00000000 }, { 0x00a02001, 0xb3a00231, 0x00d20500, 0x00000000 }, { 0x00a02001, 0xb3c00231, 0x00d204c0, 0x00000000 }, { 0x00a02001, 0xb3e00231, 0x00d20540, 0x00000000 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000100 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffe74 }, { 0x00000001, 0x27800021, 0x00000780, 0x00000000 }, { 0x00000001, 0x27a00021, 0x000007a0, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00000001, 0x27340231, 0x00000733, 0x00000000 }, { 0x00600001, 0x274a0231, 0x00000749, 0x00000000 }, { 0x00800040, 0x24003e2c, 0x00b10723, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10724, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10725, 0x00010001 }, { 0x00800008, 0x26c03d8d, 0x008d0400, 0x00020002 }, { 0x00800040, 0x24003e2c, 0x00b10740, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10741, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10742, 0x00010001 }, { 0x00800008, 0x26a03d8d, 0x008d0400, 0x00020002 }, { 0x00800001, 0x27240231, 0x00d206c0, 0x00000000 }, { 0x00600001, 0x27400231, 0x00ae06a2, 0x00000000 }, { 0x00000001, 0x27230231, 0x000006a0, 0x00000000 }, { 0x00000005, 0x220e3dac, 0x00000680, 0x000f000f }, { 0x00000001, 0x26a00221, 0x00009c2c, 0x00000000 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006a0 }, { 0x80800040, 0xd00045b1, 0x00b18800, 0x000d0724 }, { 0x80800040, 0xd02045b1, 0x00b18820, 0x000d0724 }, { 0x80800040, 0xd04045b1, 0x00b18840, 0x000d0724 }, { 0x80800040, 0xd06045b1, 0x00b18860, 0x000d0724 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x80800040, 0xd00045b1, 0x00b18800, 0x002c0740 }, { 0x80800040, 0xd02045b1, 0x00b18820, 0x002c0742 }, { 0x80800040, 0xd04045b1, 0x00b18840, 0x002c0744 }, { 0x80800040, 0xd06045b1, 0x00b18860, 0x002c0746 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x02802005, 0x20003da0, 0x00000708, 0x00020002 }, { 0x02600005, 0x20003da0, 0x02000708, 0x00010001 }, { 0x009a0001, 0x27200169, 0x00000000, 0x80808080 }, { 0x00780001, 0x27400231, 0x028d0724, 0x00000000 }, { 0x00780001, 0x27240231, 0x008d0740, 0x00000000 }, { 0x00600040, 0x25e04629, 0x008d0724, 0x008d0740 }, { 0x00400040, 0x25e02529, 0x006905e0, 0x006905e8 }, { 0x00200040, 0x25e02529, 0x004505e0, 0x004505e4 }, { 0x00800040, 0x2400252c, 0x000005e0, 0x000005e2 }, { 0x00800040, 0x24003d8c, 0x008d0400, 0x00080008 }, { 0x00800008, 0x26803d8d, 0x008d0400, 0x00040004 }, { 0x80800040, 0xd00035b1, 0x00b18800, 0x00b10680 }, { 0x80800040, 0xd02035b1, 0x00b18820, 0x00b10680 }, { 0x80800040, 0xd04035b1, 0x00b18840, 0x00b10680 }, { 0x80800040, 0xd06035b1, 0x00b18860, 0x00b10680 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00600001, 0x27340231, 0x008d0733, 0x00000000 }, { 0x00800040, 0x24003e2c, 0x00b10726, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10725, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10724, 0x00010001 }, { 0x00800008, 0x26803d8d, 0x00b10400, 0x00020002 }, { 0x80800040, 0xd00035b1, 0x00b18800, 0x002d0680 }, { 0x80800040, 0xd02035b1, 0x00b18820, 0x002d0684 }, { 0x80800040, 0xd04035b1, 0x00b18840, 0x002d0688 }, { 0x80800040, 0xd06035b1, 0x00b18860, 0x002d068c }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00400009, 0x26c05421, 0x00000744, 0x00690050 }, { 0x00400009, 0x26d05421, 0x00000740, 0x00690050 }, { 0x00600001, 0x26a00231, 0x00cf06c3, 0x00000000 }, { 0x00800001, 0x26a80231, 0x00b10723, 0x00000000 }, { 0x00800040, 0x24003e2c, 0x00b106a2, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b106a1, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b106a0, 0x00010001 }, { 0x00800008, 0x26a03d8d, 0x00b10400, 0x00020002 }, { 0x00200040, 0x220c3eac, 0x00450056, 0x06a006a0 }, { 0x80800040, 0xd06035b1, 0x01ed9800, 0x00b18860 }, { 0x80800040, 0xd04035b1, 0x01ed9804, 0x00b18840 }, { 0x80800040, 0xd02035b1, 0x01ed9808, 0x00b18820 }, { 0x80800040, 0xd00035b1, 0x01ed980c, 0x00b18800 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00400009, 0x26c05421, 0x00000744, 0x00690050 }, { 0x00400009, 0x26d05421, 0x00000740, 0x00690050 }, { 0x00600001, 0x26a00231, 0x00cf06c3, 0x00000000 }, { 0x00800001, 0x26a80231, 0x00b10723, 0x00000000 }, { 0x00800042, 0x25c04629, 0x00b106a8, 0x00b106a9 }, { 0x00800040, 0x24003e2c, 0x00b106a3, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b106a2, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b106a1, 0x00010001 }, { 0x00800008, 0x26c03d8d, 0x008d0400, 0x00020002 }, { 0x00600001, 0x26a00231, 0x00ae06c0, 0x00000000 }, { 0x00600001, 0x46a60231, 0x00ae06cc, 0x00000000 }, { 0x00600001, 0x46a70231, 0x00ae05c0, 0x00000000 }, { 0x00200040, 0x220c3eac, 0x00450036, 0x06a006a0 }, { 0x80800040, 0xd0603631, 0x01ee9800, 0x00b18860 }, { 0x80800040, 0xd0403631, 0x01ee9802, 0x00b18840 }, { 0x80800040, 0xd0203631, 0x01ee9804, 0x00b18820 }, { 0x80800040, 0xd0003631, 0x01ee9806, 0x00b18800 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00400009, 0x26c05421, 0x00000744, 0x00690050 }, { 0x00400009, 0x26d05421, 0x00000740, 0x00690050 }, { 0x00600001, 0x26a00231, 0x00ab06c3, 0x00000000 }, { 0x00800001, 0x26a80231, 0x00b10723, 0x00000000 }, { 0x00800040, 0x24003e2c, 0x00b106a2, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b106a1, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b106a0, 0x00010001 }, { 0x00800008, 0x25c03d89, 0x008d0400, 0x00020002 }, { 0x00800042, 0x26a0462d, 0x00b106a0, 0x00b106a1 }, { 0x00600001, 0x46a10231, 0x00ae05c0, 0x00000000 }, { 0x00600001, 0x26b00231, 0x00ae05d0, 0x00000000 }, { 0x00200040, 0x220c3eac, 0x00450056, 0x06a006a0 }, { 0x80800040, 0xd0603631, 0x01ed9800, 0x00b18860 }, { 0x80800040, 0xd0403631, 0x01ed9804, 0x00b18840 }, { 0x80800040, 0xd0203631, 0x01ed9808, 0x00b18820 }, { 0x80800040, 0xd0003631, 0x01ed980c, 0x00b18800 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00800042, 0x25c04629, 0x00b10724, 0x00b10725 }, { 0x00800040, 0x24003e2c, 0x00b10726, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10725, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10724, 0x00010001 }, { 0x00800008, 0x25e03d89, 0x002d0400, 0x00020002 }, { 0x80800040, 0xd0003531, 0x00ad05c0, 0x00b18800 }, { 0x80800040, 0xd0203531, 0x00ad05c2, 0x00b18820 }, { 0x80800040, 0xd0403531, 0x00ad05c4, 0x00b18840 }, { 0x80800040, 0xd0603531, 0x00ad05c6, 0x00b18860 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00600001, 0x27480231, 0x00000747, 0x00000000 }, { 0x00800042, 0x25c04629, 0x00b10740, 0x00b10741 }, { 0x00800040, 0x24003e2c, 0x00b10742, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10741, 0x00020002 }, { 0x00800048, 0x24003e2c, 0x00b10740, 0x00010001 }, { 0x00800008, 0x25e03d89, 0x002d0400, 0x00020002 }, { 0x00800001, 0x45c10231, 0x00d205e0, 0x00000000 }, { 0x80800040, 0xd0003631, 0x004d05c0, 0x00b18800 }, { 0x80800040, 0xd0203631, 0x004d05c4, 0x00b18820 }, { 0x80800040, 0xd0403631, 0x004d05c8, 0x00b18840 }, { 0x80800040, 0xd0603631, 0x004d05cc, 0x00b18860 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00000401, 0x27c80061, 0x00000000, 0x000f000f }, { 0x00200801, 0x27c001a1, 0x004507fa, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00000200, 0x0ff04000 }, { 0x00800001, 0x20400232, 0x00cd0400, 0x00000000 }, { 0x00800001, 0x20500232, 0x00cd0408, 0x00000000 }, { 0x00800001, 0x20600232, 0x00cd0410, 0x00000000 }, { 0x00800001, 0x20700232, 0x00cd0418, 0x00000000 }, { 0x00800001, 0x20800232, 0x00cd0440, 0x00000000 }, { 0x00800001, 0x20900232, 0x00cd0448, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00cd0450, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00cd0458, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00cd0480, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00cd0488, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00cd0490, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00cd0498, 0x00000000 }, { 0x00800001, 0x21000232, 0x00cd04c0, 0x00000000 }, { 0x00800001, 0x21100232, 0x00cd04c8, 0x00000000 }, { 0x00800001, 0x21200232, 0x00cd04d0, 0x00000000 }, { 0x00800001, 0x21300232, 0x00cd04d8, 0x00000000 }, { 0x01600031, 0x27800021, 0x508d07c0, 0x00000200 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00600001, 0x27c00021, 0x008d0000, 0x00000000 }, { 0x00200009, 0x27fa3e29, 0x00450064, 0x00040004 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffd34 }, { 0x00000001, 0x220401ec, 0x00000000, 0x00800080 }, { 0x00000001, 0x220601ec, 0x00000000, 0x04000400 }, { 0x00200008, 0x27006e2d, 0x0000006c, 0x00000040 }, { 0x02600005, 0x20003e20, 0x0000006c, 0x00040004 }, { 0x00780001, 0x26340231, 0x00000633, 0x00000000 }, { 0x00800001, 0x27200231, 0x00b10620, 0x00000000 }, { 0x00600001, 0x27400231, 0x00cf0643, 0x00000000 }, { 0x00400008, 0x26806e2d, 0x00240070, 0x00004040 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000006a }, { 0x00000040, 0x22043d8c, 0x00000204, 0x00800080 }, { 0x00000006, 0x27003dad, 0x00000700, 0x00010001 }, { 0x00800001, 0x27200231, 0x00b10628, 0x00000000 }, { 0x00400001, 0x27400231, 0x00808c26, 0x00000000 }, { 0x00400001, 0x27440231, 0x00808c66, 0x00000000 }, { 0x00400008, 0x26806e2d, 0x00240072, 0x00004040 }, { 0x00000040, 0x22063d8c, 0x00000206, 0x00800080 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000058 }, { 0x00000040, 0x22043d8c, 0x00000204, 0x00800080 }, { 0x00000006, 0x27003dad, 0x00000702, 0x00020002 }, { 0x00800001, 0xaf800231, 0x00d28f80, 0x00000000 }, { 0x00800001, 0xaf900231, 0x00d28fa0, 0x00000000 }, { 0x00800001, 0xafc00231, 0x00d28fc0, 0x00000000 }, { 0x00800001, 0xafd00231, 0x00d28fe0, 0x00000000 }, { 0x00800001, 0xafa00231, 0x00d28c00, 0x00000000 }, { 0x00800001, 0xafb00231, 0x00d28c20, 0x00000000 }, { 0x00800001, 0xafe00231, 0x00d28c40, 0x00000000 }, { 0x00800001, 0xaff00231, 0x00d28c60, 0x00000000 }, { 0x00400001, 0x27200231, 0x0069065c, 0x00000000 }, { 0x00600001, 0x27240231, 0x00a98fcc, 0x00000000 }, { 0x00600001, 0x272c0231, 0x00a98fec, 0x00000000 }, { 0x00600001, 0x27340231, 0x00008fff, 0x00000000 }, { 0x00800001, 0x2620012d, 0x00b10720, 0x00000000 }, { 0x00600001, 0x27400231, 0x00cf0663, 0x00000000 }, { 0x00400008, 0x26806e2d, 0x00240074, 0x00004040 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000032 }, { 0x00000040, 0x22043d8c, 0x00000204, 0x00800080 }, { 0x00000006, 0x27003dad, 0x00000700, 0x00010001 }, { 0x00800001, 0x27200231, 0x00b10628, 0x00000000 }, { 0x00600001, 0x27300231, 0x008d0638, 0x00000000 }, { 0x00400001, 0x27400231, 0x00808c26, 0x00000000 }, { 0x00400001, 0x27440231, 0x00808c66, 0x00000000 }, { 0x00400008, 0x26806e2d, 0x00240076, 0x00004040 }, { 0x00000040, 0x22063d8c, 0x00000206, 0x00800080 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x00800001, 0xaf800231, 0x00d28f80, 0x00000000 }, { 0x00800001, 0xaf900231, 0x00d28fa0, 0x00000000 }, { 0x00800001, 0xafc00231, 0x00d28fc0, 0x00000000 }, { 0x00800001, 0xafd00231, 0x00d28fe0, 0x00000000 }, { 0x00800001, 0xafa00231, 0x00d28c00, 0x00000000 }, { 0x00800001, 0xafb00231, 0x00d28c20, 0x00000000 }, { 0x00800001, 0xafe00231, 0x00d28c40, 0x00000000 }, { 0x00800001, 0xaff00231, 0x00d28c60, 0x00000000 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000e0 }, { 0x00000040, 0x27e01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffcce }, { 0x00000001, 0x27800021, 0x00000780, 0x00000000 }, { 0x00000001, 0x27a00021, 0x000007a0, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00600001, 0x27800231, 0x008d0740, 0x00000000 }, { 0x00400005, 0x22083dac, 0x00690680, 0x000f000f }, { 0x00400040, 0x26a04625, 0x01e09020, 0x00690058 }, { 0x00000001, 0x26d001ad, 0x00000700, 0x00000000 }, { 0x00000040, 0x27e41c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006a0 }, { 0x80600040, 0xcc0035b1, 0x00898800, 0x008d0760 }, { 0x80600040, 0xcc1035b1, 0x00898820, 0x008d0770 }, { 0x00800001, 0x27200231, 0x008d0724, 0x00000000 }, { 0x00400001, 0x27400231, 0x00808c06, 0x00000000 }, { 0x00000006, 0x26d03dad, 0x00000700, 0x00010001 }, { 0x00000040, 0x27e41c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006a4 }, { 0x80600040, 0xcc2035b1, 0x00898808, 0x008d0760 }, { 0x80600040, 0xcc3035b1, 0x00898828, 0x008d0770 }, { 0x00000001, 0x27230231, 0x00000783, 0x00000000 }, { 0x00400001, 0x27240231, 0x008a8c18, 0x00000000 }, { 0x00400001, 0x27280231, 0x008a8c38, 0x00000000 }, { 0x00400001, 0x272c0231, 0x00008c3e, 0x00000000 }, { 0x00400001, 0x27400231, 0x00690784, 0x00000000 }, { 0x00000006, 0x26d03dad, 0x00000700, 0x00020002 }, { 0x00000040, 0x27e41c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006a8 }, { 0x80600040, 0xcc4035b1, 0x00898840, 0x008d0760 }, { 0x80600040, 0xcc5035b1, 0x00898860, 0x008d0770 }, { 0x00800001, 0x27200231, 0x008d0724, 0x00000000 }, { 0x00600001, 0x27280231, 0x00000727, 0x00000000 }, { 0x00400001, 0x27400231, 0x00808c46, 0x00000000 }, { 0x00000006, 0x26d03dad, 0x00000700, 0x00030003 }, { 0x00000040, 0x27e41c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001400, 0x00001400, 0x000006ac }, { 0x80600040, 0xcc6035b1, 0x00898848, 0x008d0760 }, { 0x80600040, 0xcc7035b1, 0x00898868, 0x008d0770 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x00800001, 0x2760022d, 0x00090724, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00800001, 0x2760022d, 0x00280740, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x02802005, 0x20003da0, 0x000006d0, 0x00020002 }, { 0x02802005, 0x20003da0, 0x020006d0, 0x00010001 }, { 0x009a0001, 0x27200169, 0x00000000, 0x80808080 }, { 0x00780001, 0x27400231, 0x028d0724, 0x00000000 }, { 0x00780001, 0x27240231, 0x008d0740, 0x00000000 }, { 0x00400040, 0x25e04629, 0x00690724, 0x00690740 }, { 0x00200040, 0x25e02529, 0x004505e0, 0x004505e4 }, { 0x00800040, 0x2400252c, 0x000005e0, 0x000005e2 }, { 0x00800040, 0x24003d8c, 0x008d0400, 0x00040004 }, { 0x00800008, 0x27603d8d, 0x008d0400, 0x00030003 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00600001, 0x26c00231, 0x008d0724, 0x00000000 }, { 0x00400001, 0x26c80231, 0x0069072b, 0x00000000 }, { 0x00600040, 0x24003e2c, 0x008d06c2, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d06c1, 0x00020002 }, { 0x00600048, 0x25e03e29, 0x008d06c0, 0x00010001 }, { 0x00800008, 0x27603d2d, 0x002905e0, 0x00020002 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00400009, 0x26e05421, 0x00000740, 0x00690050 }, { 0x00600001, 0x26c40231, 0x008d0723, 0x00000000 }, { 0x00400001, 0x26c00231, 0x00ab06e3, 0x00000000 }, { 0x00600040, 0x24003e2c, 0x008d06c2, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d06c1, 0x00020002 }, { 0x00600048, 0x26c03e2d, 0x008d06c0, 0x00010001 }, { 0x00400040, 0x22083eac, 0x00690054, 0x06c006c0 }, { 0x00800008, 0x27603dad, 0x01e99000, 0x00020002 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00400009, 0x26e05421, 0x00000740, 0x00690050 }, { 0x00600001, 0x26c40231, 0x008d0723, 0x00000000 }, { 0x00400001, 0x26c00231, 0x00ab06e3, 0x00000000 }, { 0x00600042, 0x25c04629, 0x008d06c4, 0x008d06c5 }, { 0x00600040, 0x24003e2c, 0x008d06c3, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d06c2, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d06c1, 0x00010001 }, { 0x00600008, 0x26c03d8d, 0x008d0400, 0x00020002 }, { 0x00400001, 0x46c401ad, 0x006906c4, 0x00000000 }, { 0x00400001, 0x46c6012d, 0x006905c0, 0x00000000 }, { 0x00400040, 0x22083eac, 0x00690054, 0x06c006c0 }, { 0x00800001, 0x276001ad, 0x01ea9000, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00400009, 0x26e05421, 0x00000740, 0x00690050 }, { 0x00600001, 0x26c40231, 0x008d0723, 0x00000000 }, { 0x00400001, 0x26c00231, 0x00ab06e3, 0x00000000 }, { 0x00600042, 0x25c04629, 0x008d06c0, 0x008d06c1 }, { 0x00600040, 0x24003e2c, 0x008d06c2, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d06c1, 0x00020002 }, { 0x00600048, 0x26e03e2d, 0x008d06c0, 0x00010001 }, { 0x00400008, 0x46c23dad, 0x006906e0, 0x00020002 }, { 0x00200008, 0x26d03dad, 0x004506e8, 0x00020002 }, { 0x00400001, 0x46c0012d, 0x006905c0, 0x00000000 }, { 0x00400009, 0x22083eac, 0x00690054, 0x00010001 }, { 0x00400040, 0x22083d8c, 0x00690208, 0x06c006c0 }, { 0x00800001, 0x276001ad, 0x01e99000, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00600042, 0x45c04629, 0x008d0724, 0x008d0725 }, { 0x00600040, 0x24003e2c, 0x008d0726, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d0725, 0x00020002 }, { 0x00600048, 0x25e03e29, 0x008d0724, 0x00010001 }, { 0x00600008, 0x45c23d29, 0x008d05e0, 0x00020002 }, { 0x00800001, 0x2760012d, 0x002a05c0, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00600001, 0x27440231, 0x00000743, 0x00000000 }, { 0x00600042, 0x45c04629, 0x008d0740, 0x008d0741 }, { 0x00600040, 0x24003e2c, 0x008d0742, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x008d0741, 0x00020002 }, { 0x00600048, 0x25e03e29, 0x008d0740, 0x00010001 }, { 0x00600008, 0x45c23d29, 0x008d05e0, 0x00020002 }, { 0x00800001, 0x2760012d, 0x004905c0, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007e4, 0x00000000 }, { 0x00000401, 0x27c80061, 0x00000000, 0x000f000f }, { 0x00200801, 0x27c001a1, 0x004507fa, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00000200, 0x0ff04000 }, { 0x00800001, 0x20400232, 0x00a90400, 0x00000000 }, { 0x00800001, 0x20500232, 0x00a90404, 0x00000000 }, { 0x00800001, 0x20600232, 0x00a90408, 0x00000000 }, { 0x00800001, 0x20700232, 0x00a9040c, 0x00000000 }, { 0x00800001, 0x20800232, 0x00a90440, 0x00000000 }, { 0x00800001, 0x20900232, 0x00a90444, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00a90448, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00a9044c, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00a90480, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00a90484, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00a90488, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00a9048c, 0x00000000 }, { 0x00800001, 0x21000232, 0x00a904c0, 0x00000000 }, { 0x00800001, 0x21100232, 0x00a904c4, 0x00000000 }, { 0x00800001, 0x21200232, 0x00a904c8, 0x00000000 }, { 0x00800001, 0x21300232, 0x00a904cc, 0x00000000 }, { 0x01600031, 0x27800021, 0x508d07c0, 0x00000200 }, { 0x00000001, 0x34000020, 0x000007e0, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00021, 0x008d0000, 0x00000000 }, { 0x00200009, 0x27fa3e29, 0x00450064, 0x00040004 }, { 0x00000401, 0x27c80061, 0x00000000, 0x000f000f }, { 0x00200809, 0x27c03e21, 0x00450064, 0x00040004 }, { 0x00000040, 0x22000d20, 0x00000062, 0x1218a000 }, { 0x00a02401, 0x20400232, 0x00b10080, 0x00000000 }, { 0x00a02801, 0x20500232, 0x00b10090, 0x00000000 }, { 0x00a02401, 0x20800232, 0x00b100c0, 0x00000000 }, { 0x00a02801, 0x20900232, 0x00b100d0, 0x00000000 }, { 0x00a02401, 0x20c00232, 0x00b10100, 0x00000000 }, { 0x00a02801, 0x20d00232, 0x00b10110, 0x00000000 }, { 0x00a02401, 0x21000232, 0x00b10140, 0x00000000 }, { 0x00a02801, 0x21100232, 0x00b10150, 0x00000000 }, { 0x01600031, 0x27800021, 0x508d07c0, 0x00000200 }, { 0x00000401, 0x20280062, 0x00000000, 0x0007000f }, { 0x0000080c, 0x20243c22, 0x000007c4, 0x00010001 }, { 0x00000040, 0x22001c00, 0x00000200, 0xf8000001 }, { 0x00800001, 0x40400232, 0x00b10180, 0x00000000 }, { 0x00800001, 0x40410232, 0x00b101c0, 0x00000000 }, { 0x00800001, 0x40600232, 0x00b10190, 0x00000000 }, { 0x00800001, 0x40610232, 0x00b101d0, 0x00000000 }, { 0x00800001, 0x40800232, 0x00b101a0, 0x00000000 }, { 0x00800001, 0x40810232, 0x00b101e0, 0x00000000 }, { 0x00800001, 0x40a00232, 0x00b101b0, 0x00000000 }, { 0x00800001, 0x40a10232, 0x00b101f0, 0x00000000 }, { 0x01600031, 0x27a00001, 0x508d0000, 0x00000200 }, { 0x00000001, 0x27800021, 0x00000780, 0x00000000 }, { 0x00000001, 0x27a00021, 0x000007a0, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0000, 0x00000000 }, { 0x00000005, 0x20203e2d, 0x00000061, 0x001f001f }, { 0x00200009, 0x20643e2d, 0x00450064, 0x00040004 }, { 0x00000001, 0x203a01ed, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000020, 0x00160016 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x01200010, 0x20003e2c, 0x0200006c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000024 }, { 0x00800009, 0x25403dad, 0x00050064, 0x00020002 }, { 0x00000001, 0x203a01ed, 0x00000000, 0x00180018 }, { 0x00200040, 0x45483dad, 0x00660548, 0x00100010 }, { 0x00200040, 0x45523dad, 0x00660552, 0x00100010 }, { 0x00400040, 0x25583dad, 0x00690558, 0x00100010 }, { 0x00800040, 0x208035ad, 0x00b10080, 0x00b10540 }, { 0x00600040, 0x45403dad, 0x00ae0540, 0x00200020 }, { 0x00800040, 0x20a035ad, 0x00b100a0, 0x00b10540 }, { 0x00600040, 0x45423dad, 0x00ae0542, 0x00200020 }, { 0x00800040, 0x20e035ad, 0x00b100e0, 0x00b10540 }, { 0x00600040, 0x45403dad, 0x00ae0540, 0xffe0ffe0 }, { 0x00800040, 0x20c035ad, 0x00b100c0, 0x00b10540 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000014 }, { 0x06600010, 0x20003dac, 0x02000020, 0x00030003 }, { 0x00000001, 0x206c0171, 0x00000000, 0x00000000 }, { 0x00610001, 0x208000a5, 0x02050080, 0x00000000 }, { 0x00610001, 0x212000a5, 0x02090100, 0x00000000 }, { 0x00410001, 0x211000a5, 0x02690100, 0x00000000 }, { 0x00200009, 0x25403dad, 0x00450064, 0x00020002 }, { 0x00800040, 0x208035ad, 0x00b10080, 0x00050540 }, { 0x00200040, 0x40883dad, 0x00660088, 0x00200020 }, { 0x00200040, 0x40923dad, 0x00660092, 0x00200020 }, { 0x00400040, 0x20983dad, 0x00690098, 0x00200020 }, { 0x00200401, 0x22080060, 0x00000000, 0x03400140 }, { 0x00000c01, 0x220c0060, 0x00000000, 0x04400080 }, { 0x00000801, 0x22040060, 0x00000000, 0x01000070 }, { 0x00000001, 0x20200169, 0x00000000, 0x00000000 }, { 0x0000000c, 0x2458262d, 0x0000006d, 0x00000020 }, { 0x00000001, 0x210e0169, 0x00000000, 0x00010001 }, { 0x00000005, 0x24583dad, 0x00000458, 0x00030003 }, { 0x01000010, 0x200035ac, 0x0000010e, 0x00000458 }, { 0x00010220, 0x34001c00, 0x00001400, 0x000002fe }, { 0x01000010, 0x20003dac, 0x0200010e, 0x00010001 }, { 0x00010401, 0x24540061, 0x02000000, 0x06c00640 }, { 0x00010805, 0x245a3e2d, 0x02008800, 0x007f007f }, { 0x00110401, 0x24540061, 0x02000000, 0x04800780 }, { 0x00110805, 0x245a3e2d, 0x02008804, 0x007f007f }, { 0x0000000c, 0x211e362d, 0x0000006c, 0x00000020 }, { 0x00000040, 0x20780d21, 0x0000045a, 0x0208a002 }, { 0x02000005, 0x20003dac, 0x0200011e, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000001be }, { 0x01000005, 0x20003dac, 0x00009800, 0x00030003 }, { 0x00200005, 0x24443dad, 0x00459800, 0x00030003 }, { 0x0020000c, 0x24403dad, 0x00459800, 0x00020002 }, { 0x01600006, 0x20003dac, 0x02000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00010040, 0x22000c20, 0x02000078, 0x00400000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00700000 }, { 0x00310040, 0x20401da5, 0x02450440, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x000c000c }, { 0x00010040, 0x20401da5, 0x02000440, 0xfffffffe }, { 0x00010001, 0x204401a5, 0x02000442, 0x00000000 }, { 0x00010001, 0x20480061, 0x02000000, 0x0007000c }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00010040, 0x22000c20, 0x02000078, 0x00200000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00400000 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00110040, 0x20441da5, 0x02000442, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x000c0007 }, { 0x00010001, 0x20480061, 0x02000000, 0x00070007 }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x0020040c, 0x24403dad, 0x00459800, 0x00030003 }, { 0x00200805, 0x24483dad, 0x00459800, 0x00070007 }, { 0x01600006, 0x20003dac, 0x0000044a, 0x00000000 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00000009, 0x20403ca5, 0x00000040, 0x00010001 }, { 0x00010040, 0x22000c20, 0x00000078, 0x00200010 }, { 0x00110040, 0x22000c20, 0x00000078, 0x00300010 }, { 0x00010001, 0x20480061, 0x00000000, 0x00030009 }, { 0x00110001, 0x20480061, 0x00000000, 0x00040009 }, { 0x02600031, 0x27000021, 0x408d0040, 0x00000200 }, { 0x01000005, 0x20003dac, 0x00009800, 0x00030003 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00600001, 0x26220231, 0x008d05c0, 0x00000000 }, { 0x00600401, 0x26120231, 0x008d05b8, 0x00000000 }, { 0x00600801, 0x26020231, 0x008d05b0, 0x00000000 }, { 0x00600401, 0x25f20231, 0x008d05a8, 0x00000000 }, { 0x00600801, 0x25e20231, 0x008d05a0, 0x00000000 }, { 0x00600401, 0x25d20231, 0x008d0598, 0x00000000 }, { 0x00600801, 0x25c20231, 0x008d0590, 0x00000000 }, { 0x00600401, 0x25b20231, 0x008d0588, 0x00000000 }, { 0x00600801, 0x25a20231, 0x008d0580, 0x00000000 }, { 0x00600401, 0x25920231, 0x008d0578, 0x00000000 }, { 0x00600801, 0x25820231, 0x008d0570, 0x00000000 }, { 0x00600001, 0x25720231, 0x008d0568, 0x00000000 }, { 0x00600001, 0x25620231, 0x008d0560, 0x00000000 }, { 0x00110001, 0x220001ec, 0x02000000, 0x05820582 }, { 0x00010001, 0x220001ec, 0x02000000, 0x05620562 }, { 0x00000001, 0x220e0128, 0x00000454, 0x00000000 }, { 0x01800006, 0x200035ac, 0x02000446, 0x00000444 }, { 0x00810001, 0xbc000229, 0x02ad8000, 0x00000000 }, { 0x00810001, 0xbc200229, 0x02ad8020, 0x00000000 }, { 0x00810001, 0xbc400229, 0x02ad8040, 0x00000000 }, { 0x00810001, 0xbc600229, 0x02ad8060, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000012a }, { 0x00600001, 0x2024018d, 0x008d0200, 0x00000000 }, { 0x01000041, 0x245e35ad, 0x00000446, 0x00000444 }, { 0x00000040, 0x22022d08, 0x00000200, 0x00100010 }, { 0x02000005, 0x20003db0, 0x0200045e, 0x00010001 }, { 0x00200040, 0x22042d08, 0x00450200, 0x00200020 }, { 0x00400001, 0x244c0109, 0x00690200, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000066 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000064 }, { 0x00000040, 0x22003d08, 0x00000200, 0xffdeffde }, { 0x00000440, 0x22023d08, 0x00000202, 0xffeeffee }, { 0x00000801, 0x220c0060, 0x00000000, 0x04a00480 }, { 0x01000010, 0x20003db0, 0x0000045e, 0x00040004 }, { 0x00a02040, 0x2400462c, 0x00ad8000, 0x00ad8005 }, { 0x00a02048, 0x24003e2c, 0x00ad8001, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8002, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8003, 0x00140014 }, { 0x00a02048, 0xb8003e2d, 0x00ad8004, 0xfffbfffb }, { 0x00a02040, 0x2400462c, 0x00ad8040, 0x00ad8045 }, { 0x00a02048, 0x24003e2c, 0x00ad8041, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8042, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8043, 0x00140014 }, { 0x00a02048, 0xb8403e2d, 0x00ad8044, 0xfffbfffb }, { 0x00a02040, 0x2400462c, 0x00ad8080, 0x00ad8085 }, { 0x00a02048, 0x24003e2c, 0x00ad8081, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8082, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8083, 0x00140014 }, { 0x00a02048, 0xb8803e2d, 0x00ad8084, 0xfffbfffb }, { 0x00600040, 0x2400462c, 0x008d80c0, 0x008d80c5 }, { 0x00600048, 0x24003e2c, 0x008d80c1, 0xfffbfffb }, { 0x00600048, 0x24003e2c, 0x008d80c2, 0x00140014 }, { 0x00600048, 0x24003e2c, 0x008d80c3, 0x00140014 }, { 0x00600048, 0xb8c03e2d, 0x008d80c4, 0xfffbfffb }, { 0x00000401, 0x22000060, 0x00000000, 0x04a00480 }, { 0x00000c01, 0x22040060, 0x00000000, 0x04a00490 }, { 0x00010802, 0x220c2d28, 0x00000454, 0x04800480 }, { 0x00a02040, 0x24003dac, 0x00b18000, 0x02000200 }, { 0x00800048, 0x24003dac, 0x01ed8800, 0xfffbfffb }, { 0x00800048, 0x24203dac, 0x01ed8820, 0xfffbfffb }, { 0x00a02048, 0x24003dac, 0x00b18020, 0x00140014 }, { 0x00800048, 0x24003dac, 0x01ed8820, 0x00140014 }, { 0x00800048, 0x24203dac, 0x01ed8840, 0x00140014 }, { 0x00a02048, 0x24003dac, 0x00b18040, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed8840, 0x00010001 }, { 0x00800048, 0x24203dac, 0x01ed8860, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x000a000a }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x000a000a }, { 0x00a02040, 0x24003dac, 0x00b18040, 0x02000200 }, { 0x00800048, 0x24003dac, 0x01ed8840, 0xfffbfffb }, { 0x00800048, 0x24203dac, 0x01ed8860, 0xfffbfffb }, { 0x00a02048, 0x24003dac, 0x00b18060, 0x00140014 }, { 0x00800048, 0x24003dac, 0x01ed8860, 0x00140014 }, { 0x00800048, 0x24203dac, 0x01ed8880, 0x00140014 }, { 0x00a02048, 0x24003dac, 0x00b18080, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed8880, 0x00010001 }, { 0x00800048, 0x24203dac, 0x01ed88a0, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x000a000a }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x000a000a }, { 0x00010220, 0x34001c00, 0x00001400, 0x000000b4 }, { 0x01000010, 0x20003db0, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000004c }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000004a }, { 0x00400040, 0x22003d28, 0x0069044c, 0xfffefffe }, { 0x03400010, 0x20003dac, 0x00000446, 0x00020002 }, { 0x01000010, 0x20003db0, 0x02000444, 0x00020002 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00100010 }, { 0x01000010, 0x20003dac, 0x00000446, 0x00000000 }, { 0x00010002, 0x220c2d28, 0x02000454, 0x04800480 }, { 0x00800040, 0x24003e2c, 0x01ed8000, 0x00100010 }, { 0x00800040, 0x24203e2c, 0x01ed8020, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8001, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8021, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8002, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8022, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8003, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8023, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8004, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8024, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8005, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8025, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x00050005 }, { 0x00800040, 0x24003e2c, 0x01ed8040, 0x00100010 }, { 0x00800040, 0x24203e2c, 0x01ed8060, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8041, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8061, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8042, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8062, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8043, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8063, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8044, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8064, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8045, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8065, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x00050005 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000005c }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000062 }, { 0x01000010, 0x20003db0, 0x00000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000042 }, { 0x00200401, 0x22000128, 0x0066044c, 0x00000000 }, { 0x00200c01, 0x22040128, 0x0045044e, 0x00000000 }, { 0x00000801, 0x220c0128, 0x00000454, 0x00000000 }, { 0x03400010, 0x20003dac, 0x02000444, 0x00020002 }, { 0x01000010, 0x20003dac, 0x00000444, 0x00000000 }, { 0x00410040, 0x22002d08, 0x02690200, 0x00010001 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00110001, 0x220c0168, 0x02000000, 0x04800480 }, { 0x00a02040, 0x24003e2c, 0x00ad83e0, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8be0, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8800, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8800, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8820, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8020, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8820, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8840, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x00050005 }, { 0x00a02040, 0x24003e2c, 0x00ad8020, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8820, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8840, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8040, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8840, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8860, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8060, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8860, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8880, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x00050005 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001c }, { 0x00200401, 0x22000128, 0x0045044c, 0x00000000 }, { 0x00000801, 0x220c0128, 0x00000454, 0x00000000 }, { 0x01200010, 0x20003dac, 0x00000444, 0x00030003 }, { 0x01200010, 0x20003dac, 0x02000446, 0x00030003 }, { 0x00210040, 0x22002d08, 0x00450200, 0x00010001 }, { 0x00210040, 0x22002d08, 0x02450200, 0x00100010 }, { 0x00800001, 0xb8000229, 0x01ed8000, 0x00000000 }, { 0x00800001, 0xb8200229, 0x01ed8020, 0x00000000 }, { 0x00800001, 0xb8400229, 0x01ed8040, 0x00000000 }, { 0x00800001, 0xb8600229, 0x01ed8060, 0x00000000 }, { 0x80800042, 0xd8004631, 0x00d29800, 0x00d20480 }, { 0x80800042, 0xd8204631, 0x00d29820, 0x00d204a0 }, { 0x80800042, 0xd8404631, 0x00d29840, 0x00d204c0 }, { 0x80800042, 0xd8604631, 0x00d29860, 0x00d204e0 }, { 0x00600001, 0x220001ac, 0x008d0024, 0x00000000 }, { 0x00200040, 0x244c3dad, 0x00450448, 0xfff8fff8 }, { 0x00000401, 0x220001ec, 0x00000000, 0x07000700 }, { 0x00000c01, 0x220201e8, 0x00000000, 0x07100710 }, { 0x00000801, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00000441, 0x254635ad, 0x00000448, 0x0000044a }, { 0x00000c41, 0x254025ad, 0x0000444c, 0x0000444e }, { 0x00000c41, 0x254225ad, 0x00000448, 0x0000444e }, { 0x00000841, 0x254435ad, 0x0000444c, 0x0000044a }, { 0x00200040, 0x244c3d09, 0x00450200, 0x00100010 }, { 0x00800041, 0x24002628, 0x00ad8000, 0x00000540 }, { 0x00800041, 0x24202628, 0x00ad8020, 0x00000540 }, { 0x00800048, 0x24002628, 0x00ad8002, 0x00000542 }, { 0x00800048, 0x24202628, 0x00ad8022, 0x00000542 }, { 0x00200001, 0x22000128, 0x0045044c, 0x00000000 }, { 0x00800048, 0x24002628, 0x01ed8000, 0x00000544 }, { 0x00800048, 0x24202628, 0x01ed8020, 0x00000544 }, { 0x00800048, 0xbc002629, 0x01ed8002, 0x00000546 }, { 0x00801048, 0xbc202629, 0x01ed8022, 0x00000546 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000126 }, { 0x00000001, 0x20220169, 0x00000000, 0x00040004 }, { 0x00200005, 0x24443dad, 0x00459800, 0x00030003 }, { 0x0020000c, 0x24403dad, 0x00459800, 0x00020002 }, { 0x01600006, 0x20003dac, 0x02000446, 0x00000000 }, { 0x00010040, 0x22000c20, 0x02000078, 0x00200000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00500000 }, { 0x00310040, 0x20401da5, 0x02450440, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x00080008 }, { 0x00010040, 0x20401da5, 0x02000440, 0xfffffffe }, { 0x00010001, 0x204401a5, 0x02000442, 0x00000000 }, { 0x00010001, 0x20480061, 0x02000000, 0x00030008 }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000040, 0x22000c20, 0x00000078, 0x00100010 }, { 0x0020040c, 0x24403dad, 0x00459800, 0x00030003 }, { 0x00200805, 0x24483dad, 0x00459800, 0x00070007 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00000009, 0x20403ca5, 0x00000040, 0x00010001 }, { 0x00000001, 0x20480061, 0x00000000, 0x00020005 }, { 0x02600031, 0x27000021, 0x408d0040, 0x00000200 }, { 0x00110001, 0x220001ec, 0x02000000, 0x05820582 }, { 0x00010001, 0x220001ec, 0x02000000, 0x05620562 }, { 0x00000001, 0x220e0128, 0x00000454, 0x00000000 }, { 0x01800006, 0x200035ac, 0x02000446, 0x00000444 }, { 0x00410001, 0xbc000229, 0x02698000, 0x00000000 }, { 0x00410001, 0xbc100229, 0x02698010, 0x00000000 }, { 0x00410001, 0xbc200229, 0x02698020, 0x00000000 }, { 0x00410001, 0xbc300229, 0x02698030, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000be }, { 0x00600001, 0x2024018d, 0x008d0200, 0x00000000 }, { 0x01000041, 0x245e35ad, 0x00000446, 0x00000444 }, { 0x02000005, 0x20003db0, 0x0200045e, 0x00010001 }, { 0x00000040, 0x22022d08, 0x00000200, 0x00100010 }, { 0x00200040, 0x22042d08, 0x00450200, 0x00200020 }, { 0x00400001, 0x244c0109, 0x00690200, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000044 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000042 }, { 0x00000040, 0x22003d08, 0x00000200, 0xffdeffde }, { 0x00000440, 0x22023d08, 0x00000202, 0xffeeffee }, { 0x00000801, 0x220c0060, 0x00000000, 0x04d004c0 }, { 0x01000010, 0x20003db0, 0x0000045e, 0x00040004 }, { 0x00802040, 0x2400462c, 0x00a98000, 0x00a98005 }, { 0x00802048, 0x24003e2c, 0x00a98001, 0xfffbfffb }, { 0x00802048, 0x24003e2c, 0x00a98002, 0x00140014 }, { 0x00802048, 0x24003e2c, 0x00a98003, 0x00140014 }, { 0x00802048, 0xb8003e2d, 0x00a98004, 0xfffbfffb }, { 0x00802040, 0x2400462c, 0x00a98040, 0x00a98045 }, { 0x00802048, 0x24003e2c, 0x00a98041, 0xfffbfffb }, { 0x00802048, 0x24003e2c, 0x00a98042, 0x00140014 }, { 0x00802048, 0x24003e2c, 0x00a98043, 0x00140014 }, { 0x00802048, 0xb8203e2d, 0x00a98044, 0xfffbfffb }, { 0x00400040, 0x2400462c, 0x00698080, 0x00698085 }, { 0x00400048, 0x24003e2c, 0x00698081, 0xfffbfffb }, { 0x00400048, 0x24003e2c, 0x00698082, 0x00140014 }, { 0x00400048, 0x24003e2c, 0x00698083, 0x00140014 }, { 0x00400048, 0xb8403e2d, 0x00698084, 0xfffbfffb }, { 0x00000401, 0x220c0060, 0x00000000, 0x04e004d0 }, { 0x00000c01, 0x22000060, 0x00000000, 0x04d004c8 }, { 0x00000c01, 0x22040060, 0x00000000, 0x04e004d8 }, { 0x00000801, 0x22080060, 0x00000000, 0x04f004e8 }, { 0x00800040, 0x24003dac, 0x00b104c0, 0x02000200 }, { 0x00800048, 0x24003dac, 0x00b104e0, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed9800, 0x00140014 }, { 0x00010001, 0x220c0168, 0x00000000, 0x05400540 }, { 0x00110001, 0x220c0168, 0x00000000, 0x04c004c0 }, { 0x00800048, 0x24003dac, 0x01e98000, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01e98020, 0x00010001 }, { 0x00800048, 0x24003dac, 0x01e98800, 0x00140014 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x000a000a }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000060 }, { 0x01000010, 0x20003db0, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000022 }, { 0x00400040, 0x22003d28, 0x0069044c, 0xfffefffe }, { 0x03400010, 0x20003dac, 0x00000446, 0x00020002 }, { 0x01000010, 0x20003db0, 0x02000444, 0x00020002 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00100010 }, { 0x01000010, 0x20003dac, 0x00000446, 0x00000000 }, { 0x00010001, 0x220e0168, 0x02000000, 0x05400540 }, { 0x00110001, 0x220e0168, 0x02000000, 0x04c004c0 }, { 0x00800040, 0x24003e2c, 0x01e98000, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01e98001, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e98002, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98003, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98004, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e98005, 0x00010001 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00050005 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000036 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000036 }, { 0x01000010, 0x20003db0, 0x00000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x03600010, 0x20003dac, 0x02000444, 0x00020002 }, { 0x00400401, 0x22000128, 0x0069044c, 0x00000000 }, { 0x00400840, 0x22083d2c, 0x0069044c, 0x00100010 }, { 0x00610040, 0x22002d08, 0x02690200, 0x00010001 }, { 0x01000010, 0x20003dac, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00800040, 0x24003e2c, 0x01e983e0, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01e98000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98020, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e993e0, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e99000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e99020, 0x00010001 }, { 0x00000001, 0x220e0168, 0x00000000, 0x05400540 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00110001, 0x220e0168, 0x02000000, 0x04c004c0 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00050005 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000e }, { 0x00400001, 0x22000128, 0x0069044c, 0x00000000 }, { 0x01400010, 0x20003dac, 0x00000444, 0x00030003 }, { 0x01400010, 0x20003dac, 0x02000446, 0x00030003 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00010001 }, { 0x00410040, 0x22002d08, 0x02690200, 0x00100010 }, { 0x00800001, 0x25400229, 0x01e98000, 0x00000000 }, { 0x80800042, 0x45404631, 0x00d20540, 0x00d204c0 }, { 0x00000001, 0x220c0128, 0x00000454, 0x00000000 }, { 0x00400001, 0xd8000231, 0x008a0540, 0x00000000 }, { 0x00400001, 0xd8100231, 0x008a0548, 0x00000000 }, { 0x00400001, 0xd8200231, 0x008a0550, 0x00000000 }, { 0x00400001, 0xd8300231, 0x008a0558, 0x00000000 }, { 0x00600001, 0x220001ac, 0x008d0024, 0x00000000 }, { 0x00200040, 0x244c3dad, 0x00450448, 0xfff8fff8 }, { 0x00000401, 0x220001ec, 0x00000000, 0x07000700 }, { 0x00000801, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00000441, 0x254635ad, 0x00000448, 0x0000044a }, { 0x00000c41, 0x254025ad, 0x0000444c, 0x0000444e }, { 0x00000c41, 0x254225ad, 0x00000448, 0x0000444e }, { 0x00000841, 0x254435ad, 0x0000444c, 0x0000044a }, { 0x00600041, 0x24002628, 0x00898000, 0x00000540 }, { 0x00600048, 0x24002628, 0x00898002, 0x00000542 }, { 0x00600048, 0x24002628, 0x00898008, 0x00000544 }, { 0x00600048, 0x2540262d, 0x0089800a, 0x00000546 }, { 0x00400401, 0xbc0001a9, 0x00690540, 0x00000000 }, { 0x00400801, 0xbc1001a9, 0x00690548, 0x00000000 }, { 0x01000010, 0x20003d2c, 0x00000022, 0x00030003 }, { 0x01000040, 0x20223d29, 0x02000022, 0xffffffff }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0x00080008 }, { 0x00110040, 0x24540c21, 0x00000454, 0x00080008 }, { 0x00010040, 0x24540c21, 0x00000454, 0x00180038 }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffee6 }, { 0x01800010, 0x20003dac, 0x0200010e, 0x00010001 }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0xffe0ffe0 }, { 0x00010001, 0x24540061, 0x02000000, 0x06c00640 }, { 0x00110001, 0x24540061, 0x02000000, 0x04800780 }, { 0x00000001, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00800040, 0x24003dac, 0x00b19c00, 0x00200020 }, { 0x00800040, 0x24203dac, 0x00b19c20, 0x00200020 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00060006 }, { 0x8080000c, 0xdc203d91, 0x00b10420, 0x00060006 }, { 0x02000040, 0x210e3d29, 0x0200010e, 0xffffffff }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0x00040004 }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffcf8 }, { 0x01000005, 0x25643e2d, 0x00000060, 0x00c000c0 }, { 0x01000010, 0x20003dac, 0x02000458, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x01000010, 0x20003dac, 0x00000458, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00a02001, 0x46400231, 0x00d20780, 0x00000000 }, { 0x00a02001, 0x46800231, 0x00d207c0, 0x00000000 }, { 0x00a02001, 0x46c00231, 0x00d20480, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000007e }, { 0x80a02042, 0x46404631, 0x00d20640, 0x00d20780 }, { 0x80a02042, 0x46804631, 0x00d20680, 0x00d207c0 }, { 0x80a02042, 0x46c04631, 0x00d206c0, 0x00d20480 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000076 }, { 0x01000010, 0x20003dac, 0x02000564, 0x00800080 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000000e }, { 0x01000010, 0x20003dac, 0x00000458, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0xffffffe4 }, { 0x00200401, 0x256801ed, 0x00000000, 0x00200020 }, { 0x00200801, 0x256c01ed, 0x00000000, 0x00060006 }, { 0x00400001, 0x258001ed, 0x00000000, 0x00000000 }, { 0x00600001, 0x45a001ad, 0x00058c00, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000028 }, { 0x02600005, 0x20006e28, 0x02008c0c, 0x88848421 }, { 0x0220000c, 0x25663dad, 0x00000458, 0x00010001 }, { 0x0000000c, 0x25643dad, 0x00000564, 0x00060006 }, { 0x00310001, 0x25c401ad, 0x00000458, 0x00000000 }, { 0x00210001, 0x25c00061, 0x00000000, 0x00010001 }, { 0x00310040, 0x25c03dad, 0x004545c4, 0x00010001 }, { 0x00610001, 0x25a00061, 0x02000000, 0x00000080 }, { 0x00710001, 0x45a002ad, 0x02ae8c00, 0x00000000 }, { 0x00710001, 0x45a202ad, 0x02ae8c01, 0x00000000 }, { 0x00800041, 0x25a035ad, 0x00b105a0, 0x000905c0 }, { 0x01200010, 0x20003e2c, 0x0245006e, 0x00000000 }, { 0x00310009, 0x244c45ad, 0x02000564, 0x0045006e }, { 0x00210001, 0x244c01ed, 0x02000000, 0x00000000 }, { 0x0031000c, 0x244c3dad, 0x0245044c, 0x00010001 }, { 0x00200009, 0x256835ad, 0x0045044c, 0x00000566 }, { 0x00210040, 0x256835ad, 0x02450568, 0x00000566 }, { 0x00200040, 0x256c362d, 0x0045006e, 0x00000566 }, { 0x00400040, 0x240035ac, 0x00ab05a2, 0x00ab05a6 }, { 0x00400040, 0x2400358c, 0x00690400, 0x00000566 }, { 0x0040000c, 0x2580358d, 0x00690400, 0x00000566 }, { 0x00800041, 0x2400362c, 0x00d20640, 0x000005a0 }, { 0x00800041, 0x2420362c, 0x00d20660, 0x000005a0 }, { 0x00800048, 0x2400362c, 0x00d20780, 0x000005a4 }, { 0x00800048, 0x2420362c, 0x00d207a0, 0x000005a4 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00000568 }, { 0x00800040, 0x2420358c, 0x00b10420, 0x00000568 }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056c }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056c }, { 0x80800040, 0x464035b1, 0x00b104c0, 0x00000580 }, { 0x80800040, 0x466035b1, 0x00b104e0, 0x00000580 }, { 0x00800041, 0x2400362c, 0x00d20680, 0x000005a0 }, { 0x00800041, 0x2420362c, 0x00d206a0, 0x000005a0 }, { 0x00800048, 0x2400362c, 0x00d207c0, 0x000005a4 }, { 0x00800048, 0x2420362c, 0x00d207e0, 0x000005a4 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00000568 }, { 0x00800040, 0x2420358c, 0x00b10420, 0x00000568 }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056c }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056c }, { 0x80800040, 0x468035b1, 0x00b104c0, 0x00000580 }, { 0x80800040, 0x46a035b1, 0x00b104e0, 0x00000580 }, { 0x00800041, 0x2400362c, 0x00d206c0, 0x000705a8 }, { 0x00800041, 0x2420362c, 0x00d206e0, 0x000705a8 }, { 0x00800048, 0x2400362c, 0x00d20480, 0x000705ac }, { 0x00800048, 0x2420362c, 0x00d204a0, 0x000705ac }, { 0x00800040, 0x2400358c, 0x00b10400, 0x0000056a }, { 0x00800040, 0x2420358c, 0x00b10420, 0x0000056a }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056e }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056e }, { 0x80800040, 0x46c035b1, 0x00b104c0, 0x00050582 }, { 0x80800040, 0x46e035b1, 0x00b104e0, 0x00050582 }, { 0x01800005, 0x20003d2c, 0x02000020, 0x00020002 }, { 0x80800040, 0xd00045b1, 0x00b19000, 0x00d20640 }, { 0x80800040, 0xd02045b1, 0x00b19020, 0x00d20660 }, { 0x80800040, 0xd04045b1, 0x00b19040, 0x00d20680 }, { 0x80800040, 0xd06045b1, 0x00b19060, 0x00d206a0 }, { 0x00000040, 0x22083d8c, 0x00000208, 0x00800080 }, { 0x80400040, 0xd40045b1, 0x00699400, 0x00ab06c0 }, { 0x80400040, 0xd48045b1, 0x00699480, 0x00ab06c2 }, { 0x80400040, 0xd42045b1, 0x00699420, 0x00ab06e0 }, { 0x80400040, 0xd4a045b1, 0x006994a0, 0x00ab06e2 }, { 0x80400040, 0xd41045b1, 0x00699410, 0x00ab06d0 }, { 0x80400040, 0xd49045b1, 0x00699490, 0x00ab06d2 }, { 0x80400040, 0xd43045b1, 0x00699430, 0x00ab06f0 }, { 0x80400040, 0xd4b045b1, 0x006994b0, 0x00ab06f2 }, { 0x00000040, 0x220a3d8c, 0x0000020a, 0x00080008 }, { 0x00110040, 0x220a3d8c, 0x0200020a, 0x00300030 }, { 0x01000010, 0x20003d2c, 0x02000020, 0x00060006 }, { 0x00000040, 0x20203d29, 0x00000020, 0x00020002 }, { 0x00000040, 0x22040c00, 0x00000204, 0x00100001 }, { 0x00000040, 0x220c358c, 0x0000020c, 0x0000003a }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffc36 }, { 0x00000001, 0x220001ec, 0x00000000, 0x01400140 }, { 0x00000001, 0x220201ec, 0x00000000, 0x01c001c0 }, { 0x00800401, 0x20400236, 0x01ee8000, 0x00000000 }, { 0x00800801, 0x20500236, 0x01ee8010, 0x00000000 }, { 0x00800401, 0x20600236, 0x01ee8020, 0x00000000 }, { 0x00800801, 0x20700236, 0x01ee8030, 0x00000000 }, { 0x00800401, 0x20800236, 0x01ee8040, 0x00000000 }, { 0x00800801, 0x20900236, 0x01ee8050, 0x00000000 }, { 0x00800401, 0x20a00236, 0x01ee8060, 0x00000000 }, { 0x00800801, 0x20b00236, 0x01ee8070, 0x00000000 }, { 0x00800401, 0x20c00236, 0x01ee8100, 0x00000000 }, { 0x00800801, 0x20d00236, 0x01ee8110, 0x00000000 }, { 0x00800401, 0x20e00236, 0x01ee8120, 0x00000000 }, { 0x00800801, 0x20f00236, 0x01ee8130, 0x00000000 }, { 0x00800401, 0x21000236, 0x01ee8140, 0x00000000 }, { 0x00800801, 0x21100236, 0x01ee8150, 0x00000000 }, { 0x00800401, 0x21200236, 0x01ee8160, 0x00000000 }, { 0x00800801, 0x21300236, 0x01ee8170, 0x00000000 }, { 0x00200401, 0x204001a5, 0x00450064, 0x00000000 }, { 0x00000801, 0x20480061, 0x00000000, 0x000f000f }, { 0x01600031, 0x21401c21, 0x508d0040, 0x1218a000 }, { 0x00000001, 0x220001ec, 0x00000000, 0x03400340 }, { 0x00800401, 0x41600236, 0x00d28000, 0x00000000 }, { 0x00800801, 0x41610236, 0x00d28080, 0x00000000 }, { 0x00800401, 0x41800236, 0x00d28020, 0x00000000 }, { 0x00800801, 0x41810236, 0x00d280a0, 0x00000000 }, { 0x00800401, 0x41a00236, 0x00d28040, 0x00000000 }, { 0x00800801, 0x41a10236, 0x00d280c0, 0x00000000 }, { 0x00800401, 0x41c00236, 0x00d28060, 0x00000000 }, { 0x00800801, 0x41c10236, 0x00d280e0, 0x00000000 }, { 0x0000040c, 0x20443ca5, 0x00000044, 0x00010001 }, { 0x00000801, 0x20480061, 0x00000000, 0x0007000f }, { 0x0a600031, 0x21601c21, 0x508d0040, 0x0a18a001 }, { 0x00000001, 0x21400021, 0x00000140, 0x00000000 }, { 0x00000001, 0x21600021, 0x00000160, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x00600001, 0x20400021, 0x008d0000, 0x00000000 }, { 0x00000005, 0x20203e2d, 0x00000061, 0x001f001f }, { 0x00200009, 0x20643e2d, 0x00450064, 0x00040004 }, { 0x00000001, 0x203a01ed, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000020, 0x00160016 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x01200010, 0x20003e2c, 0x0200006c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000024 }, { 0x00800009, 0x25403dad, 0x00050064, 0x00020002 }, { 0x00000001, 0x203a01ed, 0x00000000, 0x00180018 }, { 0x00200040, 0x45483dad, 0x00660548, 0x00100010 }, { 0x00200040, 0x45523dad, 0x00660552, 0x00100010 }, { 0x00400040, 0x25583dad, 0x00690558, 0x00100010 }, { 0x00800040, 0x208035ad, 0x00b10080, 0x00b10540 }, { 0x00600040, 0x45403dad, 0x00ae0540, 0x00200020 }, { 0x00800040, 0x20a035ad, 0x00b100a0, 0x00b10540 }, { 0x00600040, 0x45423dad, 0x00ae0542, 0x00200020 }, { 0x00800040, 0x20e035ad, 0x00b100e0, 0x00b10540 }, { 0x00600040, 0x45403dad, 0x00ae0540, 0xffe0ffe0 }, { 0x00800040, 0x20c035ad, 0x00b100c0, 0x00b10540 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000014 }, { 0x06600010, 0x20003dac, 0x02000020, 0x00030003 }, { 0x00000001, 0x206c0171, 0x00000000, 0x00000000 }, { 0x00610001, 0x208000a5, 0x02050080, 0x00000000 }, { 0x00610001, 0x212000a5, 0x02090100, 0x00000000 }, { 0x00410001, 0x211000a5, 0x02690100, 0x00000000 }, { 0x00200009, 0x25403dad, 0x00450064, 0x00020002 }, { 0x00800040, 0x208035ad, 0x00b10080, 0x00050540 }, { 0x00200040, 0x40883dad, 0x00660088, 0x00200020 }, { 0x00200040, 0x40923dad, 0x00660092, 0x00200020 }, { 0x00400040, 0x20983dad, 0x00690098, 0x00200020 }, { 0x00200401, 0x22080060, 0x00000000, 0x03400140 }, { 0x00000c01, 0x220c0060, 0x00000000, 0x04400080 }, { 0x00000801, 0x22040060, 0x00000000, 0x01000070 }, { 0x00000005, 0x203e2e29, 0x00000063, 0x00010001 }, { 0x00000001, 0x20200169, 0x00000000, 0x00000000 }, { 0x0000000c, 0x2458262d, 0x0000006d, 0x00000020 }, { 0x00000001, 0x210e0169, 0x00000000, 0x00010001 }, { 0x00000005, 0x24583dad, 0x00000458, 0x00030003 }, { 0x01000010, 0x200035ac, 0x0000010e, 0x00000458 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000316 }, { 0x01000010, 0x20003dac, 0x0200010e, 0x00010001 }, { 0x00010401, 0x24540061, 0x02000000, 0x06c00640 }, { 0x00010805, 0x245a3e2d, 0x02008800, 0x007f007f }, { 0x00110401, 0x24540061, 0x02000000, 0x04800780 }, { 0x00110805, 0x245a3e2d, 0x02008804, 0x007f007f }, { 0x00010005, 0x245c3e2d, 0x02008800, 0x00800080 }, { 0x00110005, 0x245c3e2d, 0x02008804, 0x00800080 }, { 0x00000009, 0x245c3dad, 0x0000045c, 0x00010001 }, { 0x0000000c, 0x211e362d, 0x0000006c, 0x00000020 }, { 0x00000040, 0x240035ac, 0x0000003e, 0x0000045c }, { 0x01000010, 0x20003d8c, 0x00210400, 0x00010001 }, { 0x01000010, 0x20003d8c, 0x02210400, 0x01000100 }, { 0x00000001, 0x203c01ed, 0x00000000, 0x00000000 }, { 0x00010001, 0x203c01ed, 0x00000000, 0x00020002 }, { 0x00010001, 0x203c01ed, 0x02000000, 0xfffefffe }, { 0x00000040, 0x20780d21, 0x0000045a, 0x0208e602 }, { 0x00000040, 0x20782421, 0x00000078, 0x0000045c }, { 0x02000005, 0x20003dac, 0x0200011e, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000001c0 }, { 0x01000005, 0x20003dac, 0x00009800, 0x00030003 }, { 0x00200005, 0x24443dad, 0x00459800, 0x00030003 }, { 0x0020000c, 0x24403dad, 0x00459800, 0x00020002 }, { 0x01600006, 0x20003dac, 0x02000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00010040, 0x22000c20, 0x02000078, 0x00400000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00700000 }, { 0x00310040, 0x20401da5, 0x02450440, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x000c000c }, { 0x00010040, 0x20401da5, 0x02000440, 0xfffffffe }, { 0x00010001, 0x204401a5, 0x02000442, 0x00000000 }, { 0x00010001, 0x20480061, 0x02000000, 0x0007000c }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00010040, 0x22000c20, 0x02000078, 0x00200000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00400000 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00110040, 0x20441da5, 0x02000442, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x000c0007 }, { 0x00010001, 0x20480061, 0x02000000, 0x00070007 }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000040, 0xb80235ad, 0x00009802, 0x0000003c }, { 0x0020040c, 0x24403dad, 0x00459800, 0x00030003 }, { 0x00200805, 0x24483dad, 0x00459800, 0x00070007 }, { 0x01600006, 0x20003dac, 0x0000044a, 0x00000000 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00000009, 0x20403ca5, 0x00000040, 0x00010001 }, { 0x00010040, 0x22000c20, 0x00000078, 0x00200010 }, { 0x00110040, 0x22000c20, 0x00000078, 0x00300010 }, { 0x00010001, 0x20480061, 0x00000000, 0x00030009 }, { 0x00110001, 0x20480061, 0x00000000, 0x00040009 }, { 0x02600031, 0x27000021, 0x408d0040, 0x00000200 }, { 0x01000005, 0x20003dac, 0x00009800, 0x00030003 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00600001, 0x26220231, 0x008d05c0, 0x00000000 }, { 0x00600401, 0x26120231, 0x008d05b8, 0x00000000 }, { 0x00600801, 0x26020231, 0x008d05b0, 0x00000000 }, { 0x00600401, 0x25f20231, 0x008d05a8, 0x00000000 }, { 0x00600801, 0x25e20231, 0x008d05a0, 0x00000000 }, { 0x00600401, 0x25d20231, 0x008d0598, 0x00000000 }, { 0x00600801, 0x25c20231, 0x008d0590, 0x00000000 }, { 0x00600401, 0x25b20231, 0x008d0588, 0x00000000 }, { 0x00600801, 0x25a20231, 0x008d0580, 0x00000000 }, { 0x00600401, 0x25920231, 0x008d0578, 0x00000000 }, { 0x00600801, 0x25820231, 0x008d0570, 0x00000000 }, { 0x00600001, 0x25720231, 0x008d0568, 0x00000000 }, { 0x00600001, 0x25620231, 0x008d0560, 0x00000000 }, { 0x00110001, 0x220001ec, 0x02000000, 0x05820582 }, { 0x00010001, 0x220001ec, 0x02000000, 0x05620562 }, { 0x00000001, 0x220e0128, 0x00000454, 0x00000000 }, { 0x01800006, 0x200035ac, 0x02000446, 0x00000444 }, { 0x00810001, 0xbc000229, 0x02ad8000, 0x00000000 }, { 0x00810001, 0xbc200229, 0x02ad8020, 0x00000000 }, { 0x00810001, 0xbc400229, 0x02ad8040, 0x00000000 }, { 0x00810001, 0xbc600229, 0x02ad8060, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000012a }, { 0x00600001, 0x2024018d, 0x008d0200, 0x00000000 }, { 0x01000041, 0x245e35ad, 0x00000446, 0x00000444 }, { 0x00000040, 0x22022d08, 0x00000200, 0x00100010 }, { 0x02000005, 0x20003db0, 0x0200045e, 0x00010001 }, { 0x00200040, 0x22042d08, 0x00450200, 0x00200020 }, { 0x00400001, 0x244c0109, 0x00690200, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000066 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000064 }, { 0x00000040, 0x22003d08, 0x00000200, 0xffdeffde }, { 0x00000440, 0x22023d08, 0x00000202, 0xffeeffee }, { 0x00000801, 0x220c0060, 0x00000000, 0x04a00480 }, { 0x01000010, 0x20003db0, 0x0000045e, 0x00040004 }, { 0x00a02040, 0x2400462c, 0x00ad8000, 0x00ad8005 }, { 0x00a02048, 0x24003e2c, 0x00ad8001, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8002, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8003, 0x00140014 }, { 0x00a02048, 0xb8003e2d, 0x00ad8004, 0xfffbfffb }, { 0x00a02040, 0x2400462c, 0x00ad8040, 0x00ad8045 }, { 0x00a02048, 0x24003e2c, 0x00ad8041, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8042, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8043, 0x00140014 }, { 0x00a02048, 0xb8403e2d, 0x00ad8044, 0xfffbfffb }, { 0x00a02040, 0x2400462c, 0x00ad8080, 0x00ad8085 }, { 0x00a02048, 0x24003e2c, 0x00ad8081, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8082, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8083, 0x00140014 }, { 0x00a02048, 0xb8803e2d, 0x00ad8084, 0xfffbfffb }, { 0x00600040, 0x2400462c, 0x008d80c0, 0x008d80c5 }, { 0x00600048, 0x24003e2c, 0x008d80c1, 0xfffbfffb }, { 0x00600048, 0x24003e2c, 0x008d80c2, 0x00140014 }, { 0x00600048, 0x24003e2c, 0x008d80c3, 0x00140014 }, { 0x00600048, 0xb8c03e2d, 0x008d80c4, 0xfffbfffb }, { 0x00000401, 0x22000060, 0x00000000, 0x04a00480 }, { 0x00000c01, 0x22040060, 0x00000000, 0x04a00490 }, { 0x00010802, 0x220c2d28, 0x00000454, 0x04800480 }, { 0x00a02040, 0x24003dac, 0x00b18000, 0x02000200 }, { 0x00800048, 0x24003dac, 0x01ed8800, 0xfffbfffb }, { 0x00800048, 0x24203dac, 0x01ed8820, 0xfffbfffb }, { 0x00a02048, 0x24003dac, 0x00b18020, 0x00140014 }, { 0x00800048, 0x24003dac, 0x01ed8820, 0x00140014 }, { 0x00800048, 0x24203dac, 0x01ed8840, 0x00140014 }, { 0x00a02048, 0x24003dac, 0x00b18040, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed8840, 0x00010001 }, { 0x00800048, 0x24203dac, 0x01ed8860, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x000a000a }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x000a000a }, { 0x00a02040, 0x24003dac, 0x00b18040, 0x02000200 }, { 0x00800048, 0x24003dac, 0x01ed8840, 0xfffbfffb }, { 0x00800048, 0x24203dac, 0x01ed8860, 0xfffbfffb }, { 0x00a02048, 0x24003dac, 0x00b18060, 0x00140014 }, { 0x00800048, 0x24003dac, 0x01ed8860, 0x00140014 }, { 0x00800048, 0x24203dac, 0x01ed8880, 0x00140014 }, { 0x00a02048, 0x24003dac, 0x00b18080, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed8880, 0x00010001 }, { 0x00800048, 0x24203dac, 0x01ed88a0, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x000a000a }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x000a000a }, { 0x00010220, 0x34001c00, 0x00001400, 0x000000b4 }, { 0x01000010, 0x20003db0, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000004c }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000004a }, { 0x00400040, 0x22003d28, 0x0069044c, 0xfffefffe }, { 0x03400010, 0x20003dac, 0x00000446, 0x00020002 }, { 0x01000010, 0x20003db0, 0x02000444, 0x00020002 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00100010 }, { 0x01000010, 0x20003dac, 0x00000446, 0x00000000 }, { 0x00010002, 0x220c2d28, 0x02000454, 0x04800480 }, { 0x00800040, 0x24003e2c, 0x01ed8000, 0x00100010 }, { 0x00800040, 0x24203e2c, 0x01ed8020, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8001, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8021, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8002, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8022, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8003, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8023, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8004, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8024, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8005, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8025, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x00050005 }, { 0x00800040, 0x24003e2c, 0x01ed8040, 0x00100010 }, { 0x00800040, 0x24203e2c, 0x01ed8060, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8041, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8061, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8042, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8062, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8043, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8063, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8044, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8064, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8045, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8065, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x00050005 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000005c }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000062 }, { 0x01000010, 0x20003db0, 0x00000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000042 }, { 0x00200401, 0x22000128, 0x0066044c, 0x00000000 }, { 0x00200c01, 0x22040128, 0x0045044e, 0x00000000 }, { 0x00000801, 0x220c0128, 0x00000454, 0x00000000 }, { 0x03400010, 0x20003dac, 0x02000444, 0x00020002 }, { 0x01000010, 0x20003dac, 0x00000444, 0x00000000 }, { 0x00410040, 0x22002d08, 0x02690200, 0x00010001 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00110001, 0x220c0168, 0x02000000, 0x04800480 }, { 0x00a02040, 0x24003e2c, 0x00ad83e0, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8be0, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8800, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8800, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8820, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8020, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8820, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8840, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x00050005 }, { 0x00a02040, 0x24003e2c, 0x00ad8020, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8820, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8840, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8040, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8840, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8860, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8060, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8860, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8880, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x00050005 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001c }, { 0x00200401, 0x22000128, 0x0045044c, 0x00000000 }, { 0x00000801, 0x220c0128, 0x00000454, 0x00000000 }, { 0x01200010, 0x20003dac, 0x00000444, 0x00030003 }, { 0x01200010, 0x20003dac, 0x02000446, 0x00030003 }, { 0x00210040, 0x22002d08, 0x00450200, 0x00010001 }, { 0x00210040, 0x22002d08, 0x02450200, 0x00100010 }, { 0x00800001, 0xb8000229, 0x01ed8000, 0x00000000 }, { 0x00800001, 0xb8200229, 0x01ed8020, 0x00000000 }, { 0x00800001, 0xb8400229, 0x01ed8040, 0x00000000 }, { 0x00800001, 0xb8600229, 0x01ed8060, 0x00000000 }, { 0x80800042, 0xd8004631, 0x00d29800, 0x00d20480 }, { 0x80800042, 0xd8204631, 0x00d29820, 0x00d204a0 }, { 0x80800042, 0xd8404631, 0x00d29840, 0x00d204c0 }, { 0x80800042, 0xd8604631, 0x00d29860, 0x00d204e0 }, { 0x00600001, 0x220001ac, 0x008d0024, 0x00000000 }, { 0x00200040, 0x244c3dad, 0x00450448, 0xfff8fff8 }, { 0x00000401, 0x220001ec, 0x00000000, 0x07000700 }, { 0x00000c01, 0x220201e8, 0x00000000, 0x07100710 }, { 0x00000801, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00000441, 0x254635ad, 0x00000448, 0x0000044a }, { 0x00000c41, 0x254025ad, 0x0000444c, 0x0000444e }, { 0x00000c41, 0x254225ad, 0x00000448, 0x0000444e }, { 0x00000841, 0x254435ad, 0x0000444c, 0x0000044a }, { 0x00200040, 0x244c3d09, 0x00450200, 0x00100010 }, { 0x00800041, 0x24002628, 0x00ad8000, 0x00000540 }, { 0x00800041, 0x24202628, 0x00ad8020, 0x00000540 }, { 0x00800048, 0x24002628, 0x00ad8002, 0x00000542 }, { 0x00800048, 0x24202628, 0x00ad8022, 0x00000542 }, { 0x00200001, 0x22000128, 0x0045044c, 0x00000000 }, { 0x00800048, 0x24002628, 0x01ed8000, 0x00000544 }, { 0x00800048, 0x24202628, 0x01ed8020, 0x00000544 }, { 0x00800048, 0xbc002629, 0x01ed8002, 0x00000546 }, { 0x00801048, 0xbc202629, 0x01ed8022, 0x00000546 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000128 }, { 0x00000001, 0x20220169, 0x00000000, 0x00040004 }, { 0x00200005, 0x24443dad, 0x00459800, 0x00030003 }, { 0x0020000c, 0x24403dad, 0x00459800, 0x00020002 }, { 0x01600006, 0x20003dac, 0x02000446, 0x00000000 }, { 0x00010040, 0x22000c20, 0x02000078, 0x00200000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00500000 }, { 0x00310040, 0x20401da5, 0x02450440, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x00080008 }, { 0x00010040, 0x20401da5, 0x02000440, 0xfffffffe }, { 0x00010001, 0x204401a5, 0x02000442, 0x00000000 }, { 0x00010001, 0x20480061, 0x02000000, 0x00030008 }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000040, 0xb80235ad, 0x00009802, 0x0000003c }, { 0x00000040, 0x22000c20, 0x00000078, 0x00100010 }, { 0x0020040c, 0x24403dad, 0x00459800, 0x00030003 }, { 0x00200805, 0x24483dad, 0x00459800, 0x00070007 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00000009, 0x20403ca5, 0x00000040, 0x00010001 }, { 0x00000001, 0x20480061, 0x00000000, 0x00020005 }, { 0x02600031, 0x27000021, 0x408d0040, 0x00000200 }, { 0x00110001, 0x220001ec, 0x02000000, 0x05820582 }, { 0x00010001, 0x220001ec, 0x02000000, 0x05620562 }, { 0x00000001, 0x220e0128, 0x00000454, 0x00000000 }, { 0x01800006, 0x200035ac, 0x02000446, 0x00000444 }, { 0x00410001, 0xbc000229, 0x02698000, 0x00000000 }, { 0x00410001, 0xbc100229, 0x02698010, 0x00000000 }, { 0x00410001, 0xbc200229, 0x02698020, 0x00000000 }, { 0x00410001, 0xbc300229, 0x02698030, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000be }, { 0x00600001, 0x2024018d, 0x008d0200, 0x00000000 }, { 0x01000041, 0x245e35ad, 0x00000446, 0x00000444 }, { 0x02000005, 0x20003db0, 0x0200045e, 0x00010001 }, { 0x00000040, 0x22022d08, 0x00000200, 0x00100010 }, { 0x00200040, 0x22042d08, 0x00450200, 0x00200020 }, { 0x00400001, 0x244c0109, 0x00690200, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000044 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000042 }, { 0x00000040, 0x22003d08, 0x00000200, 0xffdeffde }, { 0x00000440, 0x22023d08, 0x00000202, 0xffeeffee }, { 0x00000801, 0x220c0060, 0x00000000, 0x04d004c0 }, { 0x01000010, 0x20003db0, 0x0000045e, 0x00040004 }, { 0x00802040, 0x2400462c, 0x00a98000, 0x00a98005 }, { 0x00802048, 0x24003e2c, 0x00a98001, 0xfffbfffb }, { 0x00802048, 0x24003e2c, 0x00a98002, 0x00140014 }, { 0x00802048, 0x24003e2c, 0x00a98003, 0x00140014 }, { 0x00802048, 0xb8003e2d, 0x00a98004, 0xfffbfffb }, { 0x00802040, 0x2400462c, 0x00a98040, 0x00a98045 }, { 0x00802048, 0x24003e2c, 0x00a98041, 0xfffbfffb }, { 0x00802048, 0x24003e2c, 0x00a98042, 0x00140014 }, { 0x00802048, 0x24003e2c, 0x00a98043, 0x00140014 }, { 0x00802048, 0xb8203e2d, 0x00a98044, 0xfffbfffb }, { 0x00400040, 0x2400462c, 0x00698080, 0x00698085 }, { 0x00400048, 0x24003e2c, 0x00698081, 0xfffbfffb }, { 0x00400048, 0x24003e2c, 0x00698082, 0x00140014 }, { 0x00400048, 0x24003e2c, 0x00698083, 0x00140014 }, { 0x00400048, 0xb8403e2d, 0x00698084, 0xfffbfffb }, { 0x00000401, 0x220c0060, 0x00000000, 0x04e004d0 }, { 0x00000c01, 0x22000060, 0x00000000, 0x04d004c8 }, { 0x00000c01, 0x22040060, 0x00000000, 0x04e004d8 }, { 0x00000801, 0x22080060, 0x00000000, 0x04f004e8 }, { 0x00800040, 0x24003dac, 0x00b104c0, 0x02000200 }, { 0x00800048, 0x24003dac, 0x00b104e0, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed9800, 0x00140014 }, { 0x00010001, 0x220c0168, 0x00000000, 0x05400540 }, { 0x00110001, 0x220c0168, 0x00000000, 0x04c004c0 }, { 0x00800048, 0x24003dac, 0x01e98000, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01e98020, 0x00010001 }, { 0x00800048, 0x24003dac, 0x01e98800, 0x00140014 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x000a000a }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000060 }, { 0x01000010, 0x20003db0, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000022 }, { 0x00400040, 0x22003d28, 0x0069044c, 0xfffefffe }, { 0x03400010, 0x20003dac, 0x00000446, 0x00020002 }, { 0x01000010, 0x20003db0, 0x02000444, 0x00020002 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00100010 }, { 0x01000010, 0x20003dac, 0x00000446, 0x00000000 }, { 0x00010001, 0x220e0168, 0x02000000, 0x05400540 }, { 0x00110001, 0x220e0168, 0x02000000, 0x04c004c0 }, { 0x00800040, 0x24003e2c, 0x01e98000, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01e98001, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e98002, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98003, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98004, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e98005, 0x00010001 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00050005 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000036 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000036 }, { 0x01000010, 0x20003db0, 0x00000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x03600010, 0x20003dac, 0x02000444, 0x00020002 }, { 0x00400401, 0x22000128, 0x0069044c, 0x00000000 }, { 0x00400840, 0x22083d2c, 0x0069044c, 0x00100010 }, { 0x00610040, 0x22002d08, 0x02690200, 0x00010001 }, { 0x01000010, 0x20003dac, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00800040, 0x24003e2c, 0x01e983e0, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01e98000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98020, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e993e0, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e99000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e99020, 0x00010001 }, { 0x00000001, 0x220e0168, 0x00000000, 0x05400540 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00110001, 0x220e0168, 0x02000000, 0x04c004c0 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00050005 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000e }, { 0x00400001, 0x22000128, 0x0069044c, 0x00000000 }, { 0x01400010, 0x20003dac, 0x00000444, 0x00030003 }, { 0x01400010, 0x20003dac, 0x02000446, 0x00030003 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00010001 }, { 0x00410040, 0x22002d08, 0x02690200, 0x00100010 }, { 0x00800001, 0x25400229, 0x01e98000, 0x00000000 }, { 0x80800042, 0x45404631, 0x00d20540, 0x00d204c0 }, { 0x00000001, 0x220c0128, 0x00000454, 0x00000000 }, { 0x00400001, 0xd8000231, 0x008a0540, 0x00000000 }, { 0x00400001, 0xd8100231, 0x008a0548, 0x00000000 }, { 0x00400001, 0xd8200231, 0x008a0550, 0x00000000 }, { 0x00400001, 0xd8300231, 0x008a0558, 0x00000000 }, { 0x00600001, 0x220001ac, 0x008d0024, 0x00000000 }, { 0x00200040, 0x244c3dad, 0x00450448, 0xfff8fff8 }, { 0x00000401, 0x220001ec, 0x00000000, 0x07000700 }, { 0x00000801, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00000441, 0x254635ad, 0x00000448, 0x0000044a }, { 0x00000c41, 0x254025ad, 0x0000444c, 0x0000444e }, { 0x00000c41, 0x254225ad, 0x00000448, 0x0000444e }, { 0x00000841, 0x254435ad, 0x0000444c, 0x0000044a }, { 0x00600041, 0x24002628, 0x00898000, 0x00000540 }, { 0x00600048, 0x24002628, 0x00898002, 0x00000542 }, { 0x00600048, 0x24002628, 0x00898008, 0x00000544 }, { 0x00600048, 0x2540262d, 0x0089800a, 0x00000546 }, { 0x00400401, 0xbc0001a9, 0x00690540, 0x00000000 }, { 0x00400801, 0xbc1001a9, 0x00690548, 0x00000000 }, { 0x01000010, 0x20003d2c, 0x00000022, 0x00030003 }, { 0x01000040, 0x20223d29, 0x02000022, 0xffffffff }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0x00080008 }, { 0x00110040, 0x24540c21, 0x00000454, 0x00080008 }, { 0x00010040, 0x24540c21, 0x00000454, 0x00180038 }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffee4 }, { 0x01800010, 0x20003dac, 0x0200010e, 0x00010001 }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0xffe0ffe0 }, { 0x00010001, 0x24540061, 0x02000000, 0x06c00640 }, { 0x00110001, 0x24540061, 0x02000000, 0x04800780 }, { 0x00000001, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00800040, 0x24003dac, 0x00b19c00, 0x00200020 }, { 0x00800040, 0x24203dac, 0x00b19c20, 0x00200020 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00060006 }, { 0x8080000c, 0xdc203d91, 0x00b10420, 0x00060006 }, { 0x02000040, 0x210e3d29, 0x0200010e, 0xffffffff }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0x00040004 }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffce0 }, { 0x01000005, 0x25643e2d, 0x00000060, 0x00c000c0 }, { 0x01000010, 0x20003dac, 0x02000458, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x01000010, 0x20003dac, 0x00000458, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00a02001, 0x46400231, 0x00d20780, 0x00000000 }, { 0x00a02001, 0x46800231, 0x00d207c0, 0x00000000 }, { 0x00a02001, 0x46c00231, 0x00d20480, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000007e }, { 0x80a02042, 0x46404631, 0x00d20640, 0x00d20780 }, { 0x80a02042, 0x46804631, 0x00d20680, 0x00d207c0 }, { 0x80a02042, 0x46c04631, 0x00d206c0, 0x00d20480 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000076 }, { 0x01000010, 0x20003dac, 0x02000564, 0x00800080 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000000e }, { 0x01000010, 0x20003dac, 0x00000458, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0xffffffe4 }, { 0x00200401, 0x256801ed, 0x00000000, 0x00200020 }, { 0x00200801, 0x256c01ed, 0x00000000, 0x00060006 }, { 0x00400001, 0x258001ed, 0x00000000, 0x00000000 }, { 0x00600001, 0x45a001ad, 0x00058c00, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000028 }, { 0x02600005, 0x20006e28, 0x02008c0c, 0x88848421 }, { 0x0220000c, 0x25663dad, 0x00000458, 0x00010001 }, { 0x0000000c, 0x25643dad, 0x00000564, 0x00060006 }, { 0x00310001, 0x25c401ad, 0x00000458, 0x00000000 }, { 0x00210001, 0x25c00061, 0x00000000, 0x00010001 }, { 0x00310040, 0x25c03dad, 0x004545c4, 0x00010001 }, { 0x00610001, 0x25a00061, 0x02000000, 0x00000080 }, { 0x00710001, 0x45a002ad, 0x02ae8c00, 0x00000000 }, { 0x00710001, 0x45a202ad, 0x02ae8c01, 0x00000000 }, { 0x00800041, 0x25a035ad, 0x00b105a0, 0x000905c0 }, { 0x01200010, 0x20003e2c, 0x0245006e, 0x00000000 }, { 0x00310009, 0x244c45ad, 0x02000564, 0x0045006e }, { 0x00210001, 0x244c01ed, 0x02000000, 0x00000000 }, { 0x0031000c, 0x244c3dad, 0x0245044c, 0x00010001 }, { 0x00200009, 0x256835ad, 0x0045044c, 0x00000566 }, { 0x00210040, 0x256835ad, 0x02450568, 0x00000566 }, { 0x00200040, 0x256c362d, 0x0045006e, 0x00000566 }, { 0x00400040, 0x240035ac, 0x00ab05a2, 0x00ab05a6 }, { 0x00400040, 0x2400358c, 0x00690400, 0x00000566 }, { 0x0040000c, 0x2580358d, 0x00690400, 0x00000566 }, { 0x00800041, 0x2400362c, 0x00d20640, 0x000005a0 }, { 0x00800041, 0x2420362c, 0x00d20660, 0x000005a0 }, { 0x00800048, 0x2400362c, 0x00d20780, 0x000005a4 }, { 0x00800048, 0x2420362c, 0x00d207a0, 0x000005a4 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00000568 }, { 0x00800040, 0x2420358c, 0x00b10420, 0x00000568 }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056c }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056c }, { 0x80800040, 0x464035b1, 0x00b104c0, 0x00000580 }, { 0x80800040, 0x466035b1, 0x00b104e0, 0x00000580 }, { 0x00800041, 0x2400362c, 0x00d20680, 0x000005a0 }, { 0x00800041, 0x2420362c, 0x00d206a0, 0x000005a0 }, { 0x00800048, 0x2400362c, 0x00d207c0, 0x000005a4 }, { 0x00800048, 0x2420362c, 0x00d207e0, 0x000005a4 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00000568 }, { 0x00800040, 0x2420358c, 0x00b10420, 0x00000568 }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056c }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056c }, { 0x80800040, 0x468035b1, 0x00b104c0, 0x00000580 }, { 0x80800040, 0x46a035b1, 0x00b104e0, 0x00000580 }, { 0x00800041, 0x2400362c, 0x00d206c0, 0x000705a8 }, { 0x00800041, 0x2420362c, 0x00d206e0, 0x000705a8 }, { 0x00800048, 0x2400362c, 0x00d20480, 0x000705ac }, { 0x00800048, 0x2420362c, 0x00d204a0, 0x000705ac }, { 0x00800040, 0x2400358c, 0x00b10400, 0x0000056a }, { 0x00800040, 0x2420358c, 0x00b10420, 0x0000056a }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056e }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056e }, { 0x80800040, 0x46c035b1, 0x00b104c0, 0x00050582 }, { 0x80800040, 0x46e035b1, 0x00b104e0, 0x00050582 }, { 0x01800005, 0x20003d2c, 0x02000020, 0x00020002 }, { 0x80800040, 0xd00045b1, 0x00b19000, 0x00d20640 }, { 0x80800040, 0xd02045b1, 0x00b19020, 0x00d20660 }, { 0x80800040, 0xd04045b1, 0x00b19040, 0x00d20680 }, { 0x80800040, 0xd06045b1, 0x00b19060, 0x00d206a0 }, { 0x00000040, 0x22083d8c, 0x00000208, 0x00800080 }, { 0x80400040, 0xd40045b1, 0x00699400, 0x00ab06c0 }, { 0x80400040, 0xd48045b1, 0x00699480, 0x00ab06c2 }, { 0x80400040, 0xd42045b1, 0x00699420, 0x00ab06e0 }, { 0x80400040, 0xd4a045b1, 0x006994a0, 0x00ab06e2 }, { 0x80400040, 0xd41045b1, 0x00699410, 0x00ab06d0 }, { 0x80400040, 0xd49045b1, 0x00699490, 0x00ab06d2 }, { 0x80400040, 0xd43045b1, 0x00699430, 0x00ab06f0 }, { 0x80400040, 0xd4b045b1, 0x006994b0, 0x00ab06f2 }, { 0x00000040, 0x220a3d8c, 0x0000020a, 0x00080008 }, { 0x00110040, 0x220a3d8c, 0x0200020a, 0x00300030 }, { 0x01000010, 0x20003d2c, 0x02000020, 0x00060006 }, { 0x00000040, 0x20203d29, 0x00000020, 0x00020002 }, { 0x00000040, 0x22040c00, 0x00000204, 0x00100001 }, { 0x00000040, 0x220c358c, 0x0000020c, 0x0000003a }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffc1e }, { 0x00000001, 0x220001ec, 0x00000000, 0x01400140 }, { 0x00000001, 0x220201ec, 0x00000000, 0x01c001c0 }, { 0x00800401, 0x20400236, 0x01ee8000, 0x00000000 }, { 0x00800801, 0x20500236, 0x01ee8010, 0x00000000 }, { 0x00800401, 0x20600236, 0x01ee8020, 0x00000000 }, { 0x00800801, 0x20700236, 0x01ee8030, 0x00000000 }, { 0x00800401, 0x20800236, 0x01ee8040, 0x00000000 }, { 0x00800801, 0x20900236, 0x01ee8050, 0x00000000 }, { 0x00800401, 0x20a00236, 0x01ee8060, 0x00000000 }, { 0x00800801, 0x20b00236, 0x01ee8070, 0x00000000 }, { 0x00800401, 0x20c00236, 0x01ee8100, 0x00000000 }, { 0x00800801, 0x20d00236, 0x01ee8110, 0x00000000 }, { 0x00800401, 0x20e00236, 0x01ee8120, 0x00000000 }, { 0x00800801, 0x20f00236, 0x01ee8130, 0x00000000 }, { 0x00800401, 0x21000236, 0x01ee8140, 0x00000000 }, { 0x00800801, 0x21100236, 0x01ee8150, 0x00000000 }, { 0x00800401, 0x21200236, 0x01ee8160, 0x00000000 }, { 0x00800801, 0x21300236, 0x01ee8170, 0x00000000 }, { 0x00000040, 0x22000d20, 0x00000062, 0x1218a600 }, { 0x00200401, 0x204001a5, 0x00450064, 0x00000000 }, { 0x00000801, 0x20480061, 0x00000000, 0x000f000f }, { 0x01600031, 0x21400021, 0x508d0040, 0x00000200 }, { 0x00000001, 0x220001ec, 0x00000000, 0x03400340 }, { 0x00800401, 0x41600236, 0x00d28000, 0x00000000 }, { 0x00800801, 0x41610236, 0x00d28080, 0x00000000 }, { 0x00800401, 0x41800236, 0x00d28020, 0x00000000 }, { 0x00800801, 0x41810236, 0x00d280a0, 0x00000000 }, { 0x00800401, 0x41a00236, 0x00d28040, 0x00000000 }, { 0x00800801, 0x41a10236, 0x00d280c0, 0x00000000 }, { 0x00800401, 0x41c00236, 0x00d28060, 0x00000000 }, { 0x00800801, 0x41c10236, 0x00d280e0, 0x00000000 }, { 0x00000040, 0x22000d20, 0x00000062, 0x0a18a601 }, { 0x0000040c, 0x20443ca5, 0x00000044, 0x00010001 }, { 0x00000801, 0x20480061, 0x00000000, 0x0007000f }, { 0x0a600031, 0x21600021, 0x508d0040, 0x00000200 }, { 0x00000001, 0x21400021, 0x00000140, 0x00000000 }, { 0x00000001, 0x21600021, 0x00000160, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0000, 0x00000000 }, { 0x00000005, 0x20203e2d, 0x00000061, 0x001f001f }, { 0x00200009, 0x20643e2d, 0x00450064, 0x00040004 }, { 0x00000001, 0x203a01ed, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000020, 0x00160016 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x01200010, 0x20003e2c, 0x0200006c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000024 }, { 0x00800009, 0x25403dad, 0x00050064, 0x00020002 }, { 0x00000001, 0x203a01ed, 0x00000000, 0x00180018 }, { 0x00200040, 0x45483dad, 0x00660548, 0x00100010 }, { 0x00200040, 0x45523dad, 0x00660552, 0x00100010 }, { 0x00400040, 0x25583dad, 0x00690558, 0x00100010 }, { 0x00800040, 0x208035ad, 0x00b10080, 0x00b10540 }, { 0x00600040, 0x45403dad, 0x00ae0540, 0x00200020 }, { 0x00800040, 0x20a035ad, 0x00b100a0, 0x00b10540 }, { 0x00600040, 0x45423dad, 0x00ae0542, 0x00200020 }, { 0x00800040, 0x20e035ad, 0x00b100e0, 0x00b10540 }, { 0x00600040, 0x45403dad, 0x00ae0540, 0xffe0ffe0 }, { 0x00800040, 0x20c035ad, 0x00b100c0, 0x00b10540 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000014 }, { 0x06600010, 0x20003dac, 0x02000020, 0x00030003 }, { 0x00000001, 0x206c0171, 0x00000000, 0x00000000 }, { 0x00610001, 0x208000a5, 0x02050080, 0x00000000 }, { 0x00610001, 0x212000a5, 0x02090100, 0x00000000 }, { 0x00410001, 0x211000a5, 0x02690100, 0x00000000 }, { 0x00200009, 0x25403dad, 0x00450064, 0x00020002 }, { 0x00800040, 0x208035ad, 0x00b10080, 0x00050540 }, { 0x00200040, 0x40883dad, 0x00660088, 0x00200020 }, { 0x00200040, 0x40923dad, 0x00660092, 0x00200020 }, { 0x00400040, 0x20983dad, 0x00690098, 0x00200020 }, { 0x00200401, 0x22080060, 0x00000000, 0x03400140 }, { 0x00000c01, 0x220c0060, 0x00000000, 0x04400080 }, { 0x00000801, 0x22040060, 0x00000000, 0x01000070 }, { 0x02000005, 0x20002e28, 0x00000061, 0x00400040 }, { 0x00010005, 0x203e2e29, 0x00000063, 0x00010001 }, { 0x00110001, 0x203e0169, 0x00000000, 0x00030003 }, { 0x00000001, 0x20200169, 0x00000000, 0x00000000 }, { 0x0000000c, 0x2458262d, 0x0000006d, 0x00000020 }, { 0x00000001, 0x210e0169, 0x00000000, 0x00010001 }, { 0x00000005, 0x24583dad, 0x00000458, 0x00030003 }, { 0x01000010, 0x200035ac, 0x0000010e, 0x00000458 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000031a }, { 0x01000010, 0x20003dac, 0x0200010e, 0x00010001 }, { 0x00010401, 0x24540061, 0x02000000, 0x06c00640 }, { 0x00010805, 0x245a3e2d, 0x02008800, 0x007f007f }, { 0x00110401, 0x24540061, 0x02000000, 0x04800780 }, { 0x00110805, 0x245a3e2d, 0x02008804, 0x007f007f }, { 0x00010005, 0x245c3e2d, 0x02008800, 0x00800080 }, { 0x00110005, 0x245c3e2d, 0x02008804, 0x00800080 }, { 0x00000009, 0x245c3dad, 0x0000045c, 0x00010001 }, { 0x0000000c, 0x211e362d, 0x0000006c, 0x00000020 }, { 0x00000040, 0x240035ac, 0x0000003e, 0x0000045c }, { 0x01000010, 0x20003d8c, 0x00210400, 0x00010001 }, { 0x01000010, 0x20003d8c, 0x02210400, 0x01000100 }, { 0x00000001, 0x203c01ed, 0x00000000, 0x00000000 }, { 0x00010001, 0x203c01ed, 0x00000000, 0x00020002 }, { 0x00010001, 0x203c01ed, 0x02000000, 0xfffefffe }, { 0x02000005, 0x20002e28, 0x00000061, 0x00400040 }, { 0x00010040, 0x244c0d21, 0x0000045a, 0x0208e602 }, { 0x00110040, 0x20780d21, 0x0000045a, 0x0208a002 }, { 0x00010040, 0x20782421, 0x0000044c, 0x0000045c }, { 0x02000005, 0x20003dac, 0x0200011e, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000001c0 }, { 0x01000005, 0x20003dac, 0x00009800, 0x00030003 }, { 0x00200005, 0x24443dad, 0x00459800, 0x00030003 }, { 0x0020000c, 0x24403dad, 0x00459800, 0x00020002 }, { 0x01600006, 0x20003dac, 0x02000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00010040, 0x22000c20, 0x02000078, 0x00400000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00700000 }, { 0x00310040, 0x20401da5, 0x02450440, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x000c000c }, { 0x00010040, 0x20401da5, 0x02000440, 0xfffffffe }, { 0x00010001, 0x204401a5, 0x02000442, 0x00000000 }, { 0x00010001, 0x20480061, 0x02000000, 0x0007000c }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00010040, 0x22000c20, 0x02000078, 0x00200000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00400000 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00110040, 0x20441da5, 0x02000442, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x000c0007 }, { 0x00010001, 0x20480061, 0x02000000, 0x00070007 }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000040, 0xb80235ad, 0x00009802, 0x0000003c }, { 0x0020040c, 0x24403dad, 0x00459800, 0x00030003 }, { 0x00200805, 0x24483dad, 0x00459800, 0x00070007 }, { 0x01600006, 0x20003dac, 0x0000044a, 0x00000000 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00000009, 0x20403ca5, 0x00000040, 0x00010001 }, { 0x00010040, 0x22000c20, 0x00000078, 0x00200010 }, { 0x00110040, 0x22000c20, 0x00000078, 0x00300010 }, { 0x00010001, 0x20480061, 0x00000000, 0x00030009 }, { 0x00110001, 0x20480061, 0x00000000, 0x00040009 }, { 0x02600031, 0x27000021, 0x408d0040, 0x00000200 }, { 0x01000005, 0x20003dac, 0x00009800, 0x00030003 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00600001, 0x26220231, 0x008d05c0, 0x00000000 }, { 0x00600401, 0x26120231, 0x008d05b8, 0x00000000 }, { 0x00600801, 0x26020231, 0x008d05b0, 0x00000000 }, { 0x00600401, 0x25f20231, 0x008d05a8, 0x00000000 }, { 0x00600801, 0x25e20231, 0x008d05a0, 0x00000000 }, { 0x00600401, 0x25d20231, 0x008d0598, 0x00000000 }, { 0x00600801, 0x25c20231, 0x008d0590, 0x00000000 }, { 0x00600401, 0x25b20231, 0x008d0588, 0x00000000 }, { 0x00600801, 0x25a20231, 0x008d0580, 0x00000000 }, { 0x00600401, 0x25920231, 0x008d0578, 0x00000000 }, { 0x00600801, 0x25820231, 0x008d0570, 0x00000000 }, { 0x00600001, 0x25720231, 0x008d0568, 0x00000000 }, { 0x00600001, 0x25620231, 0x008d0560, 0x00000000 }, { 0x00110001, 0x220001ec, 0x02000000, 0x05820582 }, { 0x00010001, 0x220001ec, 0x02000000, 0x05620562 }, { 0x00000001, 0x220e0128, 0x00000454, 0x00000000 }, { 0x01800006, 0x200035ac, 0x02000446, 0x00000444 }, { 0x00810001, 0xbc000229, 0x02ad8000, 0x00000000 }, { 0x00810001, 0xbc200229, 0x02ad8020, 0x00000000 }, { 0x00810001, 0xbc400229, 0x02ad8040, 0x00000000 }, { 0x00810001, 0xbc600229, 0x02ad8060, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000012a }, { 0x00600001, 0x2024018d, 0x008d0200, 0x00000000 }, { 0x01000041, 0x245e35ad, 0x00000446, 0x00000444 }, { 0x00000040, 0x22022d08, 0x00000200, 0x00100010 }, { 0x02000005, 0x20003db0, 0x0200045e, 0x00010001 }, { 0x00200040, 0x22042d08, 0x00450200, 0x00200020 }, { 0x00400001, 0x244c0109, 0x00690200, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000066 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000064 }, { 0x00000040, 0x22003d08, 0x00000200, 0xffdeffde }, { 0x00000440, 0x22023d08, 0x00000202, 0xffeeffee }, { 0x00000801, 0x220c0060, 0x00000000, 0x04a00480 }, { 0x01000010, 0x20003db0, 0x0000045e, 0x00040004 }, { 0x00a02040, 0x2400462c, 0x00ad8000, 0x00ad8005 }, { 0x00a02048, 0x24003e2c, 0x00ad8001, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8002, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8003, 0x00140014 }, { 0x00a02048, 0xb8003e2d, 0x00ad8004, 0xfffbfffb }, { 0x00a02040, 0x2400462c, 0x00ad8040, 0x00ad8045 }, { 0x00a02048, 0x24003e2c, 0x00ad8041, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8042, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8043, 0x00140014 }, { 0x00a02048, 0xb8403e2d, 0x00ad8044, 0xfffbfffb }, { 0x00a02040, 0x2400462c, 0x00ad8080, 0x00ad8085 }, { 0x00a02048, 0x24003e2c, 0x00ad8081, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8082, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8083, 0x00140014 }, { 0x00a02048, 0xb8803e2d, 0x00ad8084, 0xfffbfffb }, { 0x00600040, 0x2400462c, 0x008d80c0, 0x008d80c5 }, { 0x00600048, 0x24003e2c, 0x008d80c1, 0xfffbfffb }, { 0x00600048, 0x24003e2c, 0x008d80c2, 0x00140014 }, { 0x00600048, 0x24003e2c, 0x008d80c3, 0x00140014 }, { 0x00600048, 0xb8c03e2d, 0x008d80c4, 0xfffbfffb }, { 0x00000401, 0x22000060, 0x00000000, 0x04a00480 }, { 0x00000c01, 0x22040060, 0x00000000, 0x04a00490 }, { 0x00010802, 0x220c2d28, 0x00000454, 0x04800480 }, { 0x00a02040, 0x24003dac, 0x00b18000, 0x02000200 }, { 0x00800048, 0x24003dac, 0x01ed8800, 0xfffbfffb }, { 0x00800048, 0x24203dac, 0x01ed8820, 0xfffbfffb }, { 0x00a02048, 0x24003dac, 0x00b18020, 0x00140014 }, { 0x00800048, 0x24003dac, 0x01ed8820, 0x00140014 }, { 0x00800048, 0x24203dac, 0x01ed8840, 0x00140014 }, { 0x00a02048, 0x24003dac, 0x00b18040, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed8840, 0x00010001 }, { 0x00800048, 0x24203dac, 0x01ed8860, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x000a000a }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x000a000a }, { 0x00a02040, 0x24003dac, 0x00b18040, 0x02000200 }, { 0x00800048, 0x24003dac, 0x01ed8840, 0xfffbfffb }, { 0x00800048, 0x24203dac, 0x01ed8860, 0xfffbfffb }, { 0x00a02048, 0x24003dac, 0x00b18060, 0x00140014 }, { 0x00800048, 0x24003dac, 0x01ed8860, 0x00140014 }, { 0x00800048, 0x24203dac, 0x01ed8880, 0x00140014 }, { 0x00a02048, 0x24003dac, 0x00b18080, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed8880, 0x00010001 }, { 0x00800048, 0x24203dac, 0x01ed88a0, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x000a000a }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x000a000a }, { 0x00010220, 0x34001c00, 0x00001400, 0x000000b4 }, { 0x01000010, 0x20003db0, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000004c }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000004a }, { 0x00400040, 0x22003d28, 0x0069044c, 0xfffefffe }, { 0x03400010, 0x20003dac, 0x00000446, 0x00020002 }, { 0x01000010, 0x20003db0, 0x02000444, 0x00020002 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00100010 }, { 0x01000010, 0x20003dac, 0x00000446, 0x00000000 }, { 0x00010002, 0x220c2d28, 0x02000454, 0x04800480 }, { 0x00800040, 0x24003e2c, 0x01ed8000, 0x00100010 }, { 0x00800040, 0x24203e2c, 0x01ed8020, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8001, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8021, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8002, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8022, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8003, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8023, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8004, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8024, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8005, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8025, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x00050005 }, { 0x00800040, 0x24003e2c, 0x01ed8040, 0x00100010 }, { 0x00800040, 0x24203e2c, 0x01ed8060, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8041, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8061, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8042, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8062, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8043, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8063, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8044, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8064, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8045, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8065, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x00050005 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000005c }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000062 }, { 0x01000010, 0x20003db0, 0x00000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000042 }, { 0x00200401, 0x22000128, 0x0066044c, 0x00000000 }, { 0x00200c01, 0x22040128, 0x0045044e, 0x00000000 }, { 0x00000801, 0x220c0128, 0x00000454, 0x00000000 }, { 0x03400010, 0x20003dac, 0x02000444, 0x00020002 }, { 0x01000010, 0x20003dac, 0x00000444, 0x00000000 }, { 0x00410040, 0x22002d08, 0x02690200, 0x00010001 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00110001, 0x220c0168, 0x02000000, 0x04800480 }, { 0x00a02040, 0x24003e2c, 0x00ad83e0, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8be0, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8800, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8800, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8820, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8020, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8820, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8840, 0x00010001 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8203d91, 0x00b10420, 0x00050005 }, { 0x00a02040, 0x24003e2c, 0x00ad8020, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01ed8820, 0xfffbfffb }, { 0x00800048, 0x24203e2c, 0x01ed8840, 0xfffbfffb }, { 0x00a02048, 0x24003e2c, 0x00ad8040, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01ed8840, 0x00140014 }, { 0x00800048, 0x24203e2c, 0x01ed8860, 0x00140014 }, { 0x00a02048, 0x24003e2c, 0x00ad8060, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01ed8860, 0x00010001 }, { 0x00800048, 0x24203e2c, 0x01ed8880, 0x00010001 }, { 0x8080000c, 0xd8403d91, 0x00b10400, 0x00050005 }, { 0x8080100c, 0xd8603d91, 0x00b10420, 0x00050005 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001c }, { 0x00200401, 0x22000128, 0x0045044c, 0x00000000 }, { 0x00000801, 0x220c0128, 0x00000454, 0x00000000 }, { 0x01200010, 0x20003dac, 0x00000444, 0x00030003 }, { 0x01200010, 0x20003dac, 0x02000446, 0x00030003 }, { 0x00210040, 0x22002d08, 0x00450200, 0x00010001 }, { 0x00210040, 0x22002d08, 0x02450200, 0x00100010 }, { 0x00800001, 0xb8000229, 0x01ed8000, 0x00000000 }, { 0x00800001, 0xb8200229, 0x01ed8020, 0x00000000 }, { 0x00800001, 0xb8400229, 0x01ed8040, 0x00000000 }, { 0x00800001, 0xb8600229, 0x01ed8060, 0x00000000 }, { 0x80800042, 0xd8004631, 0x00d29800, 0x00d20480 }, { 0x80800042, 0xd8204631, 0x00d29820, 0x00d204a0 }, { 0x80800042, 0xd8404631, 0x00d29840, 0x00d204c0 }, { 0x80800042, 0xd8604631, 0x00d29860, 0x00d204e0 }, { 0x00600001, 0x220001ac, 0x008d0024, 0x00000000 }, { 0x00200040, 0x244c3dad, 0x00450448, 0xfff8fff8 }, { 0x00000401, 0x220001ec, 0x00000000, 0x07000700 }, { 0x00000c01, 0x220201e8, 0x00000000, 0x07100710 }, { 0x00000801, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00000441, 0x254635ad, 0x00000448, 0x0000044a }, { 0x00000c41, 0x254025ad, 0x0000444c, 0x0000444e }, { 0x00000c41, 0x254225ad, 0x00000448, 0x0000444e }, { 0x00000841, 0x254435ad, 0x0000444c, 0x0000044a }, { 0x00200040, 0x244c3d09, 0x00450200, 0x00100010 }, { 0x00800041, 0x24002628, 0x00ad8000, 0x00000540 }, { 0x00800041, 0x24202628, 0x00ad8020, 0x00000540 }, { 0x00800048, 0x24002628, 0x00ad8002, 0x00000542 }, { 0x00800048, 0x24202628, 0x00ad8022, 0x00000542 }, { 0x00200001, 0x22000128, 0x0045044c, 0x00000000 }, { 0x00800048, 0x24002628, 0x01ed8000, 0x00000544 }, { 0x00800048, 0x24202628, 0x01ed8020, 0x00000544 }, { 0x00800048, 0xbc002629, 0x01ed8002, 0x00000546 }, { 0x00801048, 0xbc202629, 0x01ed8022, 0x00000546 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000128 }, { 0x00000001, 0x20220169, 0x00000000, 0x00040004 }, { 0x00200005, 0x24443dad, 0x00459800, 0x00030003 }, { 0x0020000c, 0x24403dad, 0x00459800, 0x00020002 }, { 0x01600006, 0x20003dac, 0x02000446, 0x00000000 }, { 0x00010040, 0x22000c20, 0x02000078, 0x00200000 }, { 0x00110040, 0x22000c20, 0x02000078, 0x00500000 }, { 0x00310040, 0x20401da5, 0x02450440, 0xfffffffe }, { 0x00110001, 0x20480061, 0x02000000, 0x00080008 }, { 0x00010040, 0x20401da5, 0x02000440, 0xfffffffe }, { 0x00010001, 0x204401a5, 0x02000442, 0x00000000 }, { 0x00010001, 0x20480061, 0x02000000, 0x00030008 }, { 0x01600031, 0x25600021, 0x408d0040, 0x00000200 }, { 0x00000040, 0xb80235ad, 0x00009802, 0x0000003c }, { 0x00000040, 0x22000c20, 0x00000078, 0x00100010 }, { 0x0020040c, 0x24403dad, 0x00459800, 0x00030003 }, { 0x00200805, 0x24483dad, 0x00459800, 0x00070007 }, { 0x00200001, 0x204001a5, 0x00450440, 0x00000000 }, { 0x00000009, 0x20403ca5, 0x00000040, 0x00010001 }, { 0x00000001, 0x20480061, 0x00000000, 0x00020005 }, { 0x02600031, 0x27000021, 0x408d0040, 0x00000200 }, { 0x00110001, 0x220001ec, 0x02000000, 0x05820582 }, { 0x00010001, 0x220001ec, 0x02000000, 0x05620562 }, { 0x00000001, 0x220e0128, 0x00000454, 0x00000000 }, { 0x01800006, 0x200035ac, 0x02000446, 0x00000444 }, { 0x00410001, 0xbc000229, 0x02698000, 0x00000000 }, { 0x00410001, 0xbc100229, 0x02698010, 0x00000000 }, { 0x00410001, 0xbc200229, 0x02698020, 0x00000000 }, { 0x00410001, 0xbc300229, 0x02698030, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000be }, { 0x00600001, 0x2024018d, 0x008d0200, 0x00000000 }, { 0x01000041, 0x245e35ad, 0x00000446, 0x00000444 }, { 0x02000005, 0x20003db0, 0x0200045e, 0x00010001 }, { 0x00000040, 0x22022d08, 0x00000200, 0x00100010 }, { 0x00200040, 0x22042d08, 0x00450200, 0x00200020 }, { 0x00400001, 0x244c0109, 0x00690200, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000044 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000042 }, { 0x00000040, 0x22003d08, 0x00000200, 0xffdeffde }, { 0x00000440, 0x22023d08, 0x00000202, 0xffeeffee }, { 0x00000801, 0x220c0060, 0x00000000, 0x04d004c0 }, { 0x01000010, 0x20003db0, 0x0000045e, 0x00040004 }, { 0x00802040, 0x2400462c, 0x00a98000, 0x00a98005 }, { 0x00802048, 0x24003e2c, 0x00a98001, 0xfffbfffb }, { 0x00802048, 0x24003e2c, 0x00a98002, 0x00140014 }, { 0x00802048, 0x24003e2c, 0x00a98003, 0x00140014 }, { 0x00802048, 0xb8003e2d, 0x00a98004, 0xfffbfffb }, { 0x00802040, 0x2400462c, 0x00a98040, 0x00a98045 }, { 0x00802048, 0x24003e2c, 0x00a98041, 0xfffbfffb }, { 0x00802048, 0x24003e2c, 0x00a98042, 0x00140014 }, { 0x00802048, 0x24003e2c, 0x00a98043, 0x00140014 }, { 0x00802048, 0xb8203e2d, 0x00a98044, 0xfffbfffb }, { 0x00400040, 0x2400462c, 0x00698080, 0x00698085 }, { 0x00400048, 0x24003e2c, 0x00698081, 0xfffbfffb }, { 0x00400048, 0x24003e2c, 0x00698082, 0x00140014 }, { 0x00400048, 0x24003e2c, 0x00698083, 0x00140014 }, { 0x00400048, 0xb8403e2d, 0x00698084, 0xfffbfffb }, { 0x00000401, 0x220c0060, 0x00000000, 0x04e004d0 }, { 0x00000c01, 0x22000060, 0x00000000, 0x04d004c8 }, { 0x00000c01, 0x22040060, 0x00000000, 0x04e004d8 }, { 0x00000801, 0x22080060, 0x00000000, 0x04f004e8 }, { 0x00800040, 0x24003dac, 0x00b104c0, 0x02000200 }, { 0x00800048, 0x24003dac, 0x00b104e0, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01ed9800, 0x00140014 }, { 0x00010001, 0x220c0168, 0x00000000, 0x05400540 }, { 0x00110001, 0x220c0168, 0x00000000, 0x04c004c0 }, { 0x00800048, 0x24003dac, 0x01e98000, 0xfffbfffb }, { 0x00800048, 0x24003dac, 0x01e98020, 0x00010001 }, { 0x00800048, 0x24003dac, 0x01e98800, 0x00140014 }, { 0x8080000c, 0xd8003d91, 0x00b10400, 0x000a000a }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000060 }, { 0x01000010, 0x20003db0, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000022 }, { 0x00400040, 0x22003d28, 0x0069044c, 0xfffefffe }, { 0x03400010, 0x20003dac, 0x00000446, 0x00020002 }, { 0x01000010, 0x20003db0, 0x02000444, 0x00020002 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00100010 }, { 0x01000010, 0x20003dac, 0x00000446, 0x00000000 }, { 0x00010001, 0x220e0168, 0x02000000, 0x05400540 }, { 0x00110001, 0x220e0168, 0x02000000, 0x04c004c0 }, { 0x00800040, 0x24003e2c, 0x01e98000, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01e98001, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e98002, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98003, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98004, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e98005, 0x00010001 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00050005 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000036 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000036 }, { 0x01000010, 0x20003db0, 0x00000446, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x03600010, 0x20003dac, 0x02000444, 0x00020002 }, { 0x00400401, 0x22000128, 0x0069044c, 0x00000000 }, { 0x00400840, 0x22083d2c, 0x0069044c, 0x00100010 }, { 0x00610040, 0x22002d08, 0x02690200, 0x00010001 }, { 0x01000010, 0x20003dac, 0x00000444, 0x00000000 }, { 0x01000010, 0x20003db0, 0x02000446, 0x00020002 }, { 0x00800040, 0x24003e2c, 0x01e983e0, 0x00100010 }, { 0x00800048, 0x24003e2c, 0x01e98000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e98020, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e993e0, 0xfffbfffb }, { 0x00800048, 0x24003e2c, 0x01e99000, 0x00140014 }, { 0x00800048, 0x24003e2c, 0x01e99020, 0x00010001 }, { 0x00000001, 0x220e0168, 0x00000000, 0x05400540 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00110001, 0x220e0168, 0x02000000, 0x04c004c0 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00050005 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000e }, { 0x00400001, 0x22000128, 0x0069044c, 0x00000000 }, { 0x01400010, 0x20003dac, 0x00000444, 0x00030003 }, { 0x01400010, 0x20003dac, 0x02000446, 0x00030003 }, { 0x00410040, 0x22002d08, 0x00690200, 0x00010001 }, { 0x00410040, 0x22002d08, 0x02690200, 0x00100010 }, { 0x00800001, 0x25400229, 0x01e98000, 0x00000000 }, { 0x80800042, 0x45404631, 0x00d20540, 0x00d204c0 }, { 0x00000001, 0x220c0128, 0x00000454, 0x00000000 }, { 0x00400001, 0xd8000231, 0x008a0540, 0x00000000 }, { 0x00400001, 0xd8100231, 0x008a0548, 0x00000000 }, { 0x00400001, 0xd8200231, 0x008a0550, 0x00000000 }, { 0x00400001, 0xd8300231, 0x008a0558, 0x00000000 }, { 0x00600001, 0x220001ac, 0x008d0024, 0x00000000 }, { 0x00200040, 0x244c3dad, 0x00450448, 0xfff8fff8 }, { 0x00000401, 0x220001ec, 0x00000000, 0x07000700 }, { 0x00000801, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00000441, 0x254635ad, 0x00000448, 0x0000044a }, { 0x00000c41, 0x254025ad, 0x0000444c, 0x0000444e }, { 0x00000c41, 0x254225ad, 0x00000448, 0x0000444e }, { 0x00000841, 0x254435ad, 0x0000444c, 0x0000044a }, { 0x00600041, 0x24002628, 0x00898000, 0x00000540 }, { 0x00600048, 0x24002628, 0x00898002, 0x00000542 }, { 0x00600048, 0x24002628, 0x00898008, 0x00000544 }, { 0x00600048, 0x2540262d, 0x0089800a, 0x00000546 }, { 0x00400401, 0xbc0001a9, 0x00690540, 0x00000000 }, { 0x00400801, 0xbc1001a9, 0x00690548, 0x00000000 }, { 0x01000010, 0x20003d2c, 0x00000022, 0x00030003 }, { 0x01000040, 0x20223d29, 0x02000022, 0xffffffff }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0x00080008 }, { 0x00110040, 0x24540c21, 0x00000454, 0x00080008 }, { 0x00010040, 0x24540c21, 0x00000454, 0x00180038 }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffee4 }, { 0x01800010, 0x20003dac, 0x0200010e, 0x00010001 }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0xffe0ffe0 }, { 0x00010001, 0x24540061, 0x02000000, 0x06c00640 }, { 0x00110001, 0x24540061, 0x02000000, 0x04800780 }, { 0x00000001, 0x220e0128, 0x00000456, 0x00000000 }, { 0x00800040, 0x24003dac, 0x00b19c00, 0x00200020 }, { 0x00800040, 0x24203dac, 0x00b19c20, 0x00200020 }, { 0x8080000c, 0xdc003d91, 0x00b10400, 0x00060006 }, { 0x8080000c, 0xdc203d91, 0x00b10420, 0x00060006 }, { 0x02000040, 0x210e3d29, 0x0200010e, 0xffffffff }, { 0x00000040, 0x220c3d8c, 0x0000020c, 0x00040004 }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffcdc }, { 0x01000005, 0x25643e2d, 0x00000060, 0x00c000c0 }, { 0x01000010, 0x20003dac, 0x02000458, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x01000010, 0x20003dac, 0x00000458, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00a02001, 0x46400231, 0x00d20780, 0x00000000 }, { 0x00a02001, 0x46800231, 0x00d207c0, 0x00000000 }, { 0x00a02001, 0x46c00231, 0x00d20480, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000007e }, { 0x80a02042, 0x46404631, 0x00d20640, 0x00d20780 }, { 0x80a02042, 0x46804631, 0x00d20680, 0x00d207c0 }, { 0x80a02042, 0x46c04631, 0x00d206c0, 0x00d20480 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000076 }, { 0x01000010, 0x20003dac, 0x02000564, 0x00800080 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000000e }, { 0x01000010, 0x20003dac, 0x00000458, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0xffffffe4 }, { 0x00200401, 0x256801ed, 0x00000000, 0x00200020 }, { 0x00200801, 0x256c01ed, 0x00000000, 0x00060006 }, { 0x00400001, 0x258001ed, 0x00000000, 0x00000000 }, { 0x00600001, 0x45a001ad, 0x00058c00, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000028 }, { 0x02600005, 0x20006e28, 0x02008c0c, 0x88848421 }, { 0x0220000c, 0x25663dad, 0x00000458, 0x00010001 }, { 0x0000000c, 0x25643dad, 0x00000564, 0x00060006 }, { 0x00310001, 0x25c401ad, 0x00000458, 0x00000000 }, { 0x00210001, 0x25c00061, 0x00000000, 0x00010001 }, { 0x00310040, 0x25c03dad, 0x004545c4, 0x00010001 }, { 0x00610001, 0x25a00061, 0x02000000, 0x00000080 }, { 0x00710001, 0x45a002ad, 0x02ae8c00, 0x00000000 }, { 0x00710001, 0x45a202ad, 0x02ae8c01, 0x00000000 }, { 0x00800041, 0x25a035ad, 0x00b105a0, 0x000905c0 }, { 0x01200010, 0x20003e2c, 0x0245006e, 0x00000000 }, { 0x00310009, 0x244c45ad, 0x02000564, 0x0045006e }, { 0x00210001, 0x244c01ed, 0x02000000, 0x00000000 }, { 0x0031000c, 0x244c3dad, 0x0245044c, 0x00010001 }, { 0x00200009, 0x256835ad, 0x0045044c, 0x00000566 }, { 0x00210040, 0x256835ad, 0x02450568, 0x00000566 }, { 0x00200040, 0x256c362d, 0x0045006e, 0x00000566 }, { 0x00400040, 0x240035ac, 0x00ab05a2, 0x00ab05a6 }, { 0x00400040, 0x2400358c, 0x00690400, 0x00000566 }, { 0x0040000c, 0x2580358d, 0x00690400, 0x00000566 }, { 0x00800041, 0x2400362c, 0x00d20640, 0x000005a0 }, { 0x00800041, 0x2420362c, 0x00d20660, 0x000005a0 }, { 0x00800048, 0x2400362c, 0x00d20780, 0x000005a4 }, { 0x00800048, 0x2420362c, 0x00d207a0, 0x000005a4 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00000568 }, { 0x00800040, 0x2420358c, 0x00b10420, 0x00000568 }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056c }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056c }, { 0x80800040, 0x464035b1, 0x00b104c0, 0x00000580 }, { 0x80800040, 0x466035b1, 0x00b104e0, 0x00000580 }, { 0x00800041, 0x2400362c, 0x00d20680, 0x000005a0 }, { 0x00800041, 0x2420362c, 0x00d206a0, 0x000005a0 }, { 0x00800048, 0x2400362c, 0x00d207c0, 0x000005a4 }, { 0x00800048, 0x2420362c, 0x00d207e0, 0x000005a4 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00000568 }, { 0x00800040, 0x2420358c, 0x00b10420, 0x00000568 }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056c }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056c }, { 0x80800040, 0x468035b1, 0x00b104c0, 0x00000580 }, { 0x80800040, 0x46a035b1, 0x00b104e0, 0x00000580 }, { 0x00800041, 0x2400362c, 0x00d206c0, 0x000705a8 }, { 0x00800041, 0x2420362c, 0x00d206e0, 0x000705a8 }, { 0x00800048, 0x2400362c, 0x00d20480, 0x000705ac }, { 0x00800048, 0x2420362c, 0x00d204a0, 0x000705ac }, { 0x00800040, 0x2400358c, 0x00b10400, 0x0000056a }, { 0x00800040, 0x2420358c, 0x00b10420, 0x0000056a }, { 0x0080000c, 0x24c0358d, 0x00b10400, 0x0000056e }, { 0x0080000c, 0x24e0358d, 0x00b10420, 0x0000056e }, { 0x80800040, 0x46c035b1, 0x00b104c0, 0x00050582 }, { 0x80800040, 0x46e035b1, 0x00b104e0, 0x00050582 }, { 0x01800005, 0x20003d2c, 0x02000020, 0x00020002 }, { 0x80800040, 0xd00045b1, 0x00b19000, 0x00d20640 }, { 0x80800040, 0xd02045b1, 0x00b19020, 0x00d20660 }, { 0x80800040, 0xd04045b1, 0x00b19040, 0x00d20680 }, { 0x80800040, 0xd06045b1, 0x00b19060, 0x00d206a0 }, { 0x00000040, 0x22083d8c, 0x00000208, 0x00800080 }, { 0x80400040, 0xd40045b1, 0x00699400, 0x00ab06c0 }, { 0x80400040, 0xd48045b1, 0x00699480, 0x00ab06c2 }, { 0x80400040, 0xd42045b1, 0x00699420, 0x00ab06e0 }, { 0x80400040, 0xd4a045b1, 0x006994a0, 0x00ab06e2 }, { 0x80400040, 0xd41045b1, 0x00699410, 0x00ab06d0 }, { 0x80400040, 0xd49045b1, 0x00699490, 0x00ab06d2 }, { 0x80400040, 0xd43045b1, 0x00699430, 0x00ab06f0 }, { 0x80400040, 0xd4b045b1, 0x006994b0, 0x00ab06f2 }, { 0x00000040, 0x220a3d8c, 0x0000020a, 0x00080008 }, { 0x00110040, 0x220a3d8c, 0x0200020a, 0x00300030 }, { 0x01000010, 0x20003d2c, 0x02000020, 0x00060006 }, { 0x00000040, 0x20203d29, 0x00000020, 0x00020002 }, { 0x00000040, 0x22040c00, 0x00000204, 0x00100001 }, { 0x00000040, 0x220c358c, 0x0000020c, 0x0000003a }, { 0x00110220, 0x34001c00, 0x02001400, 0xfffffc1a }, { 0x00000001, 0x220001ec, 0x00000000, 0x01400140 }, { 0x00000001, 0x220201ec, 0x00000000, 0x01c001c0 }, { 0x00800401, 0x20400236, 0x01ee8000, 0x00000000 }, { 0x00800801, 0x20500236, 0x01ee8010, 0x00000000 }, { 0x00800401, 0x20600236, 0x01ee8020, 0x00000000 }, { 0x00800801, 0x20700236, 0x01ee8030, 0x00000000 }, { 0x00800401, 0x20800236, 0x01ee8040, 0x00000000 }, { 0x00800801, 0x20900236, 0x01ee8050, 0x00000000 }, { 0x00800401, 0x20a00236, 0x01ee8060, 0x00000000 }, { 0x00800801, 0x20b00236, 0x01ee8070, 0x00000000 }, { 0x00800401, 0x20c00236, 0x01ee8100, 0x00000000 }, { 0x00800801, 0x20d00236, 0x01ee8110, 0x00000000 }, { 0x00800401, 0x20e00236, 0x01ee8120, 0x00000000 }, { 0x00800801, 0x20f00236, 0x01ee8130, 0x00000000 }, { 0x00800401, 0x21000236, 0x01ee8140, 0x00000000 }, { 0x00800801, 0x21100236, 0x01ee8150, 0x00000000 }, { 0x00800401, 0x21200236, 0x01ee8160, 0x00000000 }, { 0x00800801, 0x21300236, 0x01ee8170, 0x00000000 }, { 0x00000040, 0x22000d20, 0x00000062, 0x1218a000 }, { 0x00200401, 0x204001a5, 0x00450064, 0x00000000 }, { 0x00000801, 0x20480061, 0x00000000, 0x000f000f }, { 0x01600031, 0x21400021, 0x508d0040, 0x00000200 }, { 0x00000001, 0x220001ec, 0x00000000, 0x03400340 }, { 0x00800401, 0x41600236, 0x00d28000, 0x00000000 }, { 0x00800801, 0x41610236, 0x00d28080, 0x00000000 }, { 0x00800401, 0x41800236, 0x00d28020, 0x00000000 }, { 0x00800801, 0x41810236, 0x00d280a0, 0x00000000 }, { 0x00800401, 0x41a00236, 0x00d28040, 0x00000000 }, { 0x00800801, 0x41a10236, 0x00d280c0, 0x00000000 }, { 0x00800401, 0x41c00236, 0x00d28060, 0x00000000 }, { 0x00800801, 0x41c10236, 0x00d280e0, 0x00000000 }, { 0x00000040, 0x22000d20, 0x00000062, 0x0a18a001 }, { 0x0000040c, 0x20443ca5, 0x00000044, 0x00010001 }, { 0x00000801, 0x20480061, 0x00000000, 0x0007000f }, { 0x0a600031, 0x21600021, 0x508d0040, 0x00000200 }, { 0x00000001, 0x21400021, 0x00000140, 0x00000000 }, { 0x00000001, 0x21600021, 0x00000160, 0x00000000 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x01000005, 0x20602d29, 0x02000042, 0x00070007 }, { 0x01000005, 0x20422d29, 0x00000042, 0xfff8fff8 }, { 0x00000001, 0x202001e9, 0x00000000, 0x100c100c }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00000009, 0x27e82d21, 0x00000040, 0x00060006 }, { 0x00600001, 0x20a00022, 0x008d0000, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000100 }, { 0x00600001, 0x20200022, 0x008d07e0, 0x00000000 }, { 0x01800031, 0x20801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20400022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20480c22, 0x000007e8, 0x00000080 }, { 0x02800031, 0x21001d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20600022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20680c22, 0x000007e8, 0x00000100 }, { 0x03800031, 0x21801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20800022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20880c22, 0x000007e8, 0x00000180 }, { 0x04800031, 0x22001d09, 0x408d0000, 0x02488400 }, { 0x02600005, 0x20000c20, 0x02000090, 0x00002000 }, { 0x00000006, 0x20880c21, 0x00000088, 0x00200000 }, { 0x00200009, 0x20845529, 0x0000009c, 0x00450020 }, { 0x00200001, 0x40840231, 0x00450094, 0x00000000 }, { 0x00310001, 0x20840229, 0x02450094, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00000095, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00000094 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0080, 0x00000000 }, { 0x00802001, 0x20800061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x020000d0, 0x00002000 }, { 0x00000006, 0x20c80c21, 0x000000c8, 0x00200000 }, { 0x00200009, 0x20c45529, 0x000000dc, 0x00450020 }, { 0x00200001, 0x40c40231, 0x004500d4, 0x00000000 }, { 0x00310001, 0x20c40229, 0x024500d4, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x000000d5, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x000000d4 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x02000110, 0x00002000 }, { 0x00000006, 0x21080c21, 0x00000108, 0x00200000 }, { 0x00200009, 0x21045529, 0x0000011c, 0x00450020 }, { 0x00200001, 0x41040231, 0x00450114, 0x00000000 }, { 0x00310001, 0x21040229, 0x02450114, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00000115, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00000114 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x21000061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x02000150, 0x00002000 }, { 0x00000006, 0x21480c21, 0x00000148, 0x00200000 }, { 0x00200009, 0x21445529, 0x0000015c, 0x00450020 }, { 0x00200001, 0x41440231, 0x00450154, 0x00000000 }, { 0x00310001, 0x21440229, 0x02450154, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00000155, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00000154 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0140, 0x00000000 }, { 0x00802001, 0x21400061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x02000190, 0x00002000 }, { 0x00000006, 0x21880c21, 0x00000188, 0x00200000 }, { 0x00200009, 0x21845529, 0x0000019c, 0x00450020 }, { 0x00200001, 0x41840231, 0x00450194, 0x00000000 }, { 0x00310001, 0x21840229, 0x02450194, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00000195, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00000194 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0180, 0x00000000 }, { 0x00802001, 0x21800061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x020001d0, 0x00002000 }, { 0x00000006, 0x21c80c21, 0x000001c8, 0x00200000 }, { 0x00200009, 0x21c45529, 0x000001dc, 0x00450020 }, { 0x00200001, 0x41c40231, 0x004501d4, 0x00000000 }, { 0x00310001, 0x21c40229, 0x024501d4, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x000001d5, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x000001d4 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d01c0, 0x00000000 }, { 0x00802001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x02000210, 0x00002000 }, { 0x00000006, 0x22080c21, 0x00000208, 0x00200000 }, { 0x00200009, 0x22045529, 0x0000021c, 0x00450020 }, { 0x00200001, 0x42040231, 0x00450214, 0x00000000 }, { 0x00310001, 0x22040229, 0x02450214, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00000215, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00000214 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0200, 0x00000000 }, { 0x00802001, 0x22000061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x02600005, 0x20000c20, 0x02000250, 0x00002000 }, { 0x00000006, 0x22480c21, 0x00000248, 0x00200000 }, { 0x00200009, 0x22445529, 0x0000025c, 0x00450020 }, { 0x00200001, 0x42440231, 0x00450254, 0x00000000 }, { 0x00310001, 0x22440229, 0x02450254, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00000255, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00000254 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0240, 0x00000000 }, { 0x00802001, 0x22400061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x01000040, 0x20423dad, 0x00000042, 0xfff8fff8 }, { 0x00600001, 0x21600022, 0x008d07e0, 0x00000000 }, { 0x00802001, 0x21800022, 0x008d0080, 0x00000000 }, { 0x00802001, 0x21c00022, 0x008d00c0, 0x00000000 }, { 0x0b800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00600001, 0x20200022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20280c22, 0x000007e8, 0x00000080 }, { 0x00802001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0140, 0x00000000 }, { 0x01800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00000040, 0x21680c22, 0x000007e8, 0x00000100 }, { 0x00802001, 0x21800022, 0x008d0180, 0x00000000 }, { 0x00802001, 0x21c00022, 0x008d01c0, 0x00000000 }, { 0x0b800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00000040, 0x20280c22, 0x000007e8, 0x00000180 }, { 0x00802001, 0x20400022, 0x008d0200, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0240, 0x00000000 }, { 0x01800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00000040, 0x27e80c21, 0x000007e8, 0x00000200 }, { 0x01000010, 0x20002da0, 0x02000060, 0x00000000 }, { 0x00110220, 0x34001c00, 0x00001400, 0xffffff00 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000040 }, { 0x00600001, 0x20200022, 0x008d07e0, 0x00000000 }, { 0x01800031, 0x20801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20400022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20480c22, 0x000007e8, 0x00000080 }, { 0x02800031, 0x21001d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20600022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20680c22, 0x000007e8, 0x00000100 }, { 0x03800031, 0x21801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20800022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20880c22, 0x000007e8, 0x00000180 }, { 0x04800031, 0x22001d09, 0x408d0000, 0x02488400 }, { 0x00000001, 0x220400e0, 0x00000000, 0x00a00080 }, { 0x00600001, 0x20a00022, 0x008d0000, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02008810, 0x00002000 }, { 0x01000040, 0x20603dad, 0x00000060, 0xffffffff }, { 0x00000006, 0xa8080c21, 0x00008808, 0x00200000 }, { 0x00200009, 0xa8045529, 0x0000881c, 0x00450020 }, { 0x00200001, 0xc8040231, 0x00458814, 0x00000000 }, { 0x00310001, 0xa8040229, 0x02458814, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000c }, { 0x00800041, 0x24002628, 0x00008815, 0x00000044 }, { 0x00800040, 0x24004508, 0x008d0400, 0x00008814 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d8800, 0x00000000 }, { 0x00802001, 0xa8000061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00600001, 0x21600022, 0x008d07e0, 0x00000000 }, { 0x00802001, 0x21800022, 0x008d8800, 0x00000000 }, { 0x0b800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000040, 0x27e80c21, 0x000007e8, 0x00000040 }, { 0x00000040, 0x22040c00, 0x00000204, 0x00400040 }, { 0x00110220, 0x34001c00, 0x00001400, 0xffffffda }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x01000005, 0x20602d29, 0x02000042, 0x00070007 }, { 0x01000005, 0x20422d29, 0x00000042, 0xfff8fff8 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00000009, 0x27e82d21, 0x00000040, 0x00060006 }, { 0x00600001, 0x20a00022, 0x008d0000, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000260 }, { 0x00600001, 0x20200022, 0x008d07e0, 0x00000000 }, { 0x01800031, 0x20801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20400022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20480c22, 0x000007e8, 0x00000080 }, { 0x02800031, 0x21001d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20600022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20680c22, 0x000007e8, 0x00000100 }, { 0x03800031, 0x21801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20800022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20880c22, 0x000007e8, 0x00000180 }, { 0x04800031, 0x22001d09, 0x408d0000, 0x02488400 }, { 0x00200001, 0x20640229, 0x00450094, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02000090, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00000090, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00000095, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00000095, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00000090, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x20881c21, 0x00000088, 0x00200000 }, { 0x00200001, 0x20840129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0080, 0x00000000 }, { 0x00802001, 0x20800061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x00000090, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x0000009c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000009c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200009c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02000090, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200009c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200009c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x20843d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x20862d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x40840231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x004500d4, 0x00000000 }, { 0x02600005, 0x20000c20, 0x020000d0, 0x01000000 }, { 0x02600005, 0x20000c20, 0x000000d0, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x000000d5, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x000000d5, 0x00000000 }, { 0x02600005, 0x20000c20, 0x000000d0, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x20c81c21, 0x000000c8, 0x00200000 }, { 0x00200001, 0x20c40129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x000000d0, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x000000dc, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x000000dc, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x020000dc, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x020000d0, 0x00008000 }, { 0x02610005, 0x20001d20, 0x020000dc, 0x00000010 }, { 0x00010006, 0x20681d29, 0x020000dc, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x20c43d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x20c62d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x40c40231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x00450114, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02000110, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00000110, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00000115, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00000115, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00000110, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x21081c21, 0x00000108, 0x00200000 }, { 0x00200001, 0x21040129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x21000061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x00000110, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x0000011c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000011c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200011c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02000110, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200011c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200011c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x21043d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x21062d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x41040231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x00450154, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02000150, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00000150, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00000155, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00000155, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00000150, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x21481c21, 0x00000148, 0x00200000 }, { 0x00200001, 0x21440129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0140, 0x00000000 }, { 0x00802001, 0x21400061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x00000150, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x0000015c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000015c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200015c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02000150, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200015c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200015c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x21443d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x21462d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x41440231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x00450194, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02000190, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00000190, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00000195, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00000195, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00000190, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x21881c21, 0x00000188, 0x00200000 }, { 0x00200001, 0x21840129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0180, 0x00000000 }, { 0x00802001, 0x21800061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x00000190, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x0000019c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000019c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200019c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02000190, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200019c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200019c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x21843d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x21862d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x41840231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x004501d4, 0x00000000 }, { 0x02600005, 0x20000c20, 0x020001d0, 0x01000000 }, { 0x02600005, 0x20000c20, 0x000001d0, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x000001d5, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x000001d5, 0x00000000 }, { 0x02600005, 0x20000c20, 0x000001d0, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x21c81c21, 0x000001c8, 0x00200000 }, { 0x00200001, 0x21c40129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d01c0, 0x00000000 }, { 0x00802001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x000001d0, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x000001dc, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x000001dc, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x020001dc, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x020001d0, 0x00008000 }, { 0x02610005, 0x20001d20, 0x020001dc, 0x00000010 }, { 0x00010006, 0x20681d29, 0x020001dc, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x21c43d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x21c62d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x41c40231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x00450214, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02000210, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00000210, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00000215, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00000215, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00000210, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x22081c21, 0x00000208, 0x00200000 }, { 0x00200001, 0x22040129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0200, 0x00000000 }, { 0x00802001, 0x22000061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x00000210, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x0000021c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000021c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200021c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02000210, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200021c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200021c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x22043d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x22062d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x42040231, 0x00660064, 0x00000000 }, { 0x00200001, 0x20640229, 0x00450254, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02000250, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00000250, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00000255, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00000255, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00000250, 0x00002000 }, { 0x02600005, 0x20001d20, 0x02000066, 0x00000001 }, { 0x00000006, 0x22481c21, 0x00000248, 0x00200000 }, { 0x00200001, 0x22440129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d0240, 0x00000000 }, { 0x00802001, 0x22400061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x02600005, 0x20000c20, 0x00000250, 0x00004000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00000001, 0x20680129, 0x0000025c, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000025c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200025c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02000250, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200025c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200025c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x02000068, 0x000d0070 }, { 0x00000009, 0x22443d09, 0x00000602, 0x000c000c }, { 0x00000005, 0x22462d09, 0x00000602, 0xf000f000 }, { 0x00200001, 0x42440231, 0x00660064, 0x00000000 }, { 0x01000040, 0x20423dad, 0x00000042, 0xfff8fff8 }, { 0x00600001, 0x21600022, 0x008d07e0, 0x00000000 }, { 0x00802001, 0x21800022, 0x008d0080, 0x00000000 }, { 0x00802001, 0x21c00022, 0x008d00c0, 0x00000000 }, { 0x0b800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00600001, 0x20200022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20280c22, 0x000007e8, 0x00000080 }, { 0x00802001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0140, 0x00000000 }, { 0x01800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00000040, 0x21680c22, 0x000007e8, 0x00000100 }, { 0x00802001, 0x21800022, 0x008d0180, 0x00000000 }, { 0x00802001, 0x21c00022, 0x008d01c0, 0x00000000 }, { 0x0b800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00000040, 0x20280c22, 0x000007e8, 0x00000180 }, { 0x00802001, 0x20400022, 0x008d0200, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0240, 0x00000000 }, { 0x01800031, 0x20001d0c, 0x508d0000, 0x0a080400 }, { 0x00000040, 0x27e80c21, 0x000007e8, 0x00000200 }, { 0x01000010, 0x20002da0, 0x02000060, 0x00000000 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffda0 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000006e }, { 0x00600001, 0x20200022, 0x008d07e0, 0x00000000 }, { 0x01800031, 0x20801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20400022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20480c22, 0x000007e8, 0x00000080 }, { 0x02800031, 0x21001d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20600022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20680c22, 0x000007e8, 0x00000100 }, { 0x03800031, 0x21801d09, 0x408d0000, 0x02488400 }, { 0x00600001, 0x20800022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20880c22, 0x000007e8, 0x00000180 }, { 0x04800031, 0x22001d09, 0x408d0000, 0x02488400 }, { 0x00000001, 0x220400e0, 0x00000000, 0x00a00080 }, { 0x00600001, 0x20a00022, 0x008d0000, 0x00000000 }, { 0x00200001, 0x20640229, 0x00458814, 0x00000000 }, { 0x02600005, 0x20000c20, 0x02008810, 0x01000000 }, { 0x02600005, 0x20000c20, 0x00008810, 0x00004000 }, { 0x00600041, 0x24003e2c, 0x00008815, 0x00020002 }, { 0x00110001, 0x2066018d, 0x02000400, 0x00000000 }, { 0x00010040, 0x20663d8d, 0x02000400, 0x00010001 }, { 0x00110001, 0x2066022d, 0x00008815, 0x00000000 }, { 0x02600005, 0x20000c20, 0x00008810, 0x00002000 }, { 0x01000040, 0x20603dad, 0x02000060, 0xffffffff }, { 0x00000006, 0xa8080c21, 0x00008808, 0x00200000 }, { 0x00200001, 0xa8040129, 0x00450064, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00800041, 0x24002528, 0x00000066, 0x00000044 }, { 0x00800040, 0x24002508, 0x008d0400, 0x00000064 }, { 0x00000009, 0x20a82d02, 0x00000404, 0x00060006 }, { 0x00802001, 0x20c00022, 0x008d8800, 0x00000000 }, { 0x00802001, 0xa8000061, 0x00000000, 0x00000000 }, { 0x05800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000022 }, { 0x02600005, 0x20000d20, 0x02000066, 0x00000001 }, { 0x02600005, 0x20000c20, 0x00008810, 0x00004000 }, { 0x00000001, 0x20680129, 0x0000881c, 0x00000000 }, { 0x00210002, 0x20700421, 0x02450038, 0x00450030 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x02600005, 0x20001d20, 0x0000881c, 0x00000010 }, { 0x00210002, 0x20700421, 0x02450028, 0x00450020 }, { 0x01600005, 0x20001d20, 0x0200881c, 0x00000001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000006 }, { 0x02610005, 0x20001c20, 0x02008810, 0x00008000 }, { 0x02610005, 0x20001d20, 0x0200881c, 0x00000010 }, { 0x00010006, 0x20681d29, 0x0200881c, 0x00000010 }, { 0x02800005, 0x2000452c, 0x00000068, 0x000d0070 }, { 0x01000040, 0x20603dad, 0x02000060, 0x00000000 }, { 0x00000009, 0xa8043d09, 0x00000600, 0x000c000c }, { 0x00000005, 0xa8062d09, 0x00000600, 0xf000f000 }, { 0x00200001, 0xc8040231, 0x00660064, 0x00000000 }, { 0x00600001, 0x21600022, 0x008d07e0, 0x00000000 }, { 0x00802001, 0x21800022, 0x008d8800, 0x00000000 }, { 0x0b800031, 0x20001d0c, 0x508d0000, 0x06080300 }, { 0x00000040, 0x27e80c21, 0x000007e8, 0x00000040 }, { 0x00000040, 0x22040c00, 0x00000204, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0xffffffac }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x01600031, 0x20001c20, 0x708d0000, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00a02001, 0x20400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x206601ed, 0x00000000, 0x00030003 }, { 0x00000009, 0x20663dad, 0x00000066, 0x000a000a }, { 0x00000008, 0x22403dad, 0x00000026, 0x00010001 }, { 0x00000041, 0x224235ad, 0x00000020, 0x00000022 }, { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, { 0x00000001, 0x203c0022, 0x00000018, 0x00000000 }, { 0x00000001, 0x203f01f2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c00e2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c010a, 0x00000e00, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0020, 0x00000000 }, { 0x00400001, 0x205401ed, 0x00000000, 0x00000000 }, { 0x00200040, 0x20583dad, 0x00450020, 0xffffffff }, { 0x00000001, 0x22000060, 0x00000000, 0x06080000 }, { 0x00600001, 0x26000021, 0x008d0000, 0x00000000 }, { 0x00000001, 0x26140061, 0x00000000, 0x00c00400 }, { 0x00000001, 0x26100169, 0x00000000, 0x12121212 }, { 0x07600031, 0x26201c21, 0x308d0600, 0x02000000 }, { 0x00000001, 0x22a00169, 0x00000000, 0x01400140 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00200020 }, { 0x00000001, 0x203801e2, 0x00000000, 0x00010001 }, { 0x00800001, 0x204001ae, 0x00b10020, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x000002a0, 0x00010001 }, { 0x00800031, 0x20000128, 0x608d07e0, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x22a00169, 0x00000000, 0x00000000 }, { 0x00000001, 0x22600169, 0x00000000, 0x00020002 }, { 0x00200401, 0x208000e5, 0x00000000, 0x00000000 }, { 0x00000c01, 0x208800e5, 0x00000000, 0xffffffc6 }, { 0x00000801, 0x208c00e5, 0x00000000, 0xffffffca }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00100010 }, { 0x00000001, 0x206001ed, 0x00000000, 0x00020002 }, { 0x00000001, 0x206201ad, 0x0000005a, 0x00000000 }, { 0x00000001, 0x20a001ed, 0x00000000, 0x00000000 }, { 0x00200001, 0x228001ed, 0x00000000, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21000061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21400061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21800061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21c00061, 0x00000000, 0x00ff00ff }, { 0x00000041, 0x22083dac, 0x00000056, 0x00040004 }, { 0x05000010, 0x200035ac, 0x02000280, 0x00000240 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x01000010, 0x20002d28, 0x000090c2, 0x00000000 }, { 0x03000010, 0x200035ac, 0x02000054, 0x00000058 }, { 0x00000041, 0x22a03dad, 0x00000056, 0x00040004 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffff4 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00200001, 0xb0c00229, 0x00450054, 0x00000000 }, { 0x00200040, 0x22803dad, 0x00450280, 0x00010001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x20380122, 0x00000260, 0x00000000 }, { 0x00800001, 0x204001ae, 0x00b10040, 0x00000000 }, { 0x00000008, 0x20003d2a, 0x000002a0, 0x00010001 }, { 0x00000040, 0x22602d29, 0x00000260, 0x00020002 }, { 0x00800031, 0x20000008, 0x608d0000, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x04200010, 0x200035ac, 0x00450054, 0x00450060 }, { 0x00010040, 0x20a03dad, 0x02000056, 0x00010001 }, { 0x05200010, 0x200035ac, 0x02450280, 0x00450240 }, { 0x00000001, 0x240001ec, 0x00000000, 0x00040004 }, { 0x00000048, 0x22083dac, 0x00000056, 0x00040004 }, { 0x00200040, 0x205455ad, 0x00450054, 0x00450034 }, { 0x02000010, 0x20003d8c, 0x00000600, 0x00010001 }, { 0x00000041, 0x220e3d8c, 0x00000602, 0x00040004 }, { 0x00010041, 0x22083dac, 0x000000a0, 0x00040004 }, { 0x00010401, 0x205601ad, 0x000000a0, 0x00000000 }, { 0x00010840, 0x20543d2d, 0x000090c0, 0x00010001 }, { 0x00000220, 0x34001400, 0x00001400, 0x00009c80 }, { 0x01000010, 0x20003dac, 0x02000280, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000006 }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffff6 }, { 0x05000010, 0x200035ac, 0x00000240, 0x00000026 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffffc }, { 0x07600031, 0x20001c20, 0x30000000, 0x02000001 }, { 0x01600031, 0x20001c24, 0x708d0000, 0x82000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00600009, 0x25c03dad, 0x00050034, 0x00040004 }, { 0x00000001, 0x220801ec, 0x00000000, 0x02400240 }, { 0x00000041, 0x20263d29, 0x00000036, 0x00040004 }, { 0x00000041, 0x25e435a1, 0x00000020, 0x00000036 }, { 0x00000040, 0x25e43421, 0x000005e4, 0x00000034 }, { 0x00000041, 0x27e82c21, 0x000005e4, 0x00400040 }, { 0x01600031, 0x22401c21, 0x408d07e0, 0x02885800 }, { 0x01800005, 0x20002d28, 0x02b19040, 0xffffffff }, { 0x02000005, 0x20003e2c, 0x00009030, 0x00010001 }, { 0x00000040, 0x25c43dad, 0x000005c4, 0xfffcfffc }, { 0x00000001, 0x25e20129, 0x00000036, 0x00000000 }, { 0x000b0220, 0x34001c00, 0x02001400, 0x00000178 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000176 }, { 0x00000040, 0x25ca3dad, 0x000005ca, 0xfffcfffc }, { 0x00200401, 0x27e001a1, 0x004505c0, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f000f }, { 0x00000001, 0x22000060, 0x00000000, 0x0288a001 }, { 0x01600031, 0x20c00021, 0x408d07e0, 0x00000200 }, { 0x00200401, 0x27e001a1, 0x004505c8, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00000001, 0x22000060, 0x00000000, 0x02286003 }, { 0x03600031, 0x20800021, 0x408d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00a900c0, 0x00000000 }, { 0x00800801, 0x23900231, 0x00a90100, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00a90140, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00a90180, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00a900c4, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00a90104, 0x00000000 }, { 0x00800401, 0x23e00231, 0x00a90144, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00a90184, 0x00000000 }, { 0x00800401, 0x24000231, 0x00a900c8, 0x00000000 }, { 0x00800801, 0x24100231, 0x00a90108, 0x00000000 }, { 0x00800401, 0x24200231, 0x00a90148, 0x00000000 }, { 0x00800801, 0x24300231, 0x00a90188, 0x00000000 }, { 0x00800401, 0x24400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x24500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x24600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x24700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x20c00231, 0x00cf0380, 0x00000000 }, { 0x00800801, 0x20d00231, 0x00cf0381, 0x00000000 }, { 0x00800401, 0x20e00231, 0x00cf0382, 0x00000000 }, { 0x00800801, 0x20f00231, 0x00cf0383, 0x00000000 }, { 0x00800401, 0x21000231, 0x00cf03c0, 0x00000000 }, { 0x00800801, 0x21100231, 0x00cf03c1, 0x00000000 }, { 0x00800401, 0x21200231, 0x00cf03c2, 0x00000000 }, { 0x00800801, 0x21300231, 0x00cf03c3, 0x00000000 }, { 0x00800401, 0x21400231, 0x00cf0400, 0x00000000 }, { 0x00800801, 0x21500231, 0x00cf0401, 0x00000000 }, { 0x00800401, 0x21600231, 0x00cf0402, 0x00000000 }, { 0x00800801, 0x21700231, 0x00cf0403, 0x00000000 }, { 0x00800401, 0x21800231, 0x00cf0440, 0x00000000 }, { 0x00800801, 0x21900231, 0x00cf0441, 0x00000000 }, { 0x00800401, 0x21a00231, 0x00cf0442, 0x00000000 }, { 0x00800801, 0x21b00231, 0x00cf0443, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00400040 }, { 0x00000008, 0x25e83e2d, 0x00009080, 0x00020002 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x00459080, 0x00000000 }, { 0x00200c01, 0x25d80129, 0x00459050, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699060, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000134 }, { 0x00000008, 0x25e83e2d, 0x00009084, 0x00020002 }, { 0x00200401, 0x25d0022d, 0x00459084, 0x00000000 }, { 0x00000801, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00c000c0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00000401, 0x25d80129, 0x00009040, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699064, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000011e }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00100010 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01000100 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01400140 }, { 0x00000401, 0x25d80129, 0x00009042, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699068, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000110 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01400140 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01800180 }, { 0x00000401, 0x25d80129, 0x00009044, 0x00000000 }, { 0x00400801, 0x25d40231, 0x0069906c, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000102 }, { 0x00200401, 0x27e001a1, 0x004505c4, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f0003 }, { 0x00800401, 0x23400231, 0x00a90040, 0x00000000 }, { 0x00800801, 0x23500231, 0x00a90044, 0x00000000 }, { 0x00800401, 0x23600231, 0x00a90048, 0x00000000 }, { 0x00800801, 0x23700231, 0x00a9004c, 0x00000000 }, { 0x00800001, 0x20400232, 0x002b0340, 0x00000000 }, { 0x00800001, 0x20500232, 0x002b0350, 0x00000000 }, { 0x00800001, 0x20600232, 0x002b0360, 0x00000000 }, { 0x00800001, 0x20700232, 0x002b0370, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x06082003 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00a900c0, 0x00000000 }, { 0x00800801, 0x23900231, 0x00a90100, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00a90140, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00a90180, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00a900c4, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00a90104, 0x00000000 }, { 0x00800401, 0x23e00231, 0x00a90144, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00a90184, 0x00000000 }, { 0x00800401, 0x24000231, 0x00a900c8, 0x00000000 }, { 0x00800801, 0x24100231, 0x00a90108, 0x00000000 }, { 0x00800401, 0x24200231, 0x00a90148, 0x00000000 }, { 0x00800801, 0x24300231, 0x00a90188, 0x00000000 }, { 0x00800401, 0x24400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x24500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x24600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x24700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x20c00231, 0x00cf0380, 0x00000000 }, { 0x00800801, 0x20d00231, 0x00cf0381, 0x00000000 }, { 0x00800401, 0x20e00231, 0x00cf0382, 0x00000000 }, { 0x00800801, 0x20f00231, 0x00cf0383, 0x00000000 }, { 0x00800401, 0x21000231, 0x00cf03c0, 0x00000000 }, { 0x00800801, 0x21100231, 0x00cf03c1, 0x00000000 }, { 0x00800401, 0x21200231, 0x00cf03c2, 0x00000000 }, { 0x00800801, 0x21300231, 0x00cf03c3, 0x00000000 }, { 0x00800401, 0x21400231, 0x00cf0400, 0x00000000 }, { 0x00800801, 0x21500231, 0x00cf0401, 0x00000000 }, { 0x00800401, 0x21600231, 0x00cf0402, 0x00000000 }, { 0x00800801, 0x21700231, 0x00cf0403, 0x00000000 }, { 0x00800401, 0x21800231, 0x00cf0440, 0x00000000 }, { 0x00800801, 0x21900231, 0x00cf0441, 0x00000000 }, { 0x00800401, 0x21a00231, 0x00cf0442, 0x00000000 }, { 0x00800801, 0x21b00231, 0x00cf0443, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00800080 }, { 0x00000008, 0x25e83e2d, 0x00009082, 0x00020002 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00800080 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x00459082, 0x00000000 }, { 0x00200c01, 0x25d80129, 0x00459054, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699070, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000096 }, { 0x00000008, 0x25e83e2d, 0x00009084, 0x00020002 }, { 0x00200401, 0x25d0022d, 0x00459084, 0x00000000 }, { 0x00000801, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00c000c0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00000401, 0x25d80129, 0x00009046, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699074, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000080 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00100010 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01000100 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01400140 }, { 0x00000401, 0x25d80129, 0x00009048, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699078, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000072 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01400140 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01800180 }, { 0x00000401, 0x25d80129, 0x0000904a, 0x00000000 }, { 0x00400801, 0x25d40231, 0x0069907c, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000064 }, { 0x00200401, 0x27e001a1, 0x004505c0, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20400022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x20c00022, 0x008d0140, 0x00000000 }, { 0x00802001, 0x21000022, 0x008d0180, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x12082003 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x00200401, 0x27e001a1, 0x004505c8, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00802001, 0x20400022, 0x008d0080, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x0618a003 }, { 0x01600031, 0x26400021, 0x508d07e0, 0x00000200 }, { 0x00800401, 0x23400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x23500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x23600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x23700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x23800231, 0x00cf0340, 0x00000000 }, { 0x00800801, 0x23900231, 0x00cf0341, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00cf0342, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00cf0343, 0x00000000 }, { 0x00802001, 0x202000a2, 0x008d0380, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x06080020 }, { 0x00600001, 0x26400021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00000440, 0x27e03da1, 0x000005c0, 0x000c000c }, { 0x00000c01, 0x27e401a1, 0x000005c2, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f0003 }, { 0x02600031, 0x23401c25, 0x408d07e0, 0x02286003 }, { 0x00800401, 0x23800231, 0x00cf0340, 0x00000000 }, { 0x00800801, 0x23900231, 0x00cf0341, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00cf0342, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00cf0343, 0x00000000 }, { 0x00802001, 0x202000a2, 0x008d0380, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x06080020 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00800040, 0x2400462d, 0x00b19c00, 0x00b1d830 }, { 0x00800040, 0x2340462d, 0x00b19820, 0x00b1d830 }, { 0x00800040, 0x2360462d, 0x00b19c10, 0x00b1dc00 }, { 0x05810010, 0x200035ac, 0x008d2400, 0x000005d0 }, { 0x05810010, 0x200035ac, 0x008d2340, 0x000005d2 }, { 0x05810010, 0x200035ac, 0x008d2360, 0x000005d2 }, { 0x00818022, 0x34001c00, 0x00001400, 0x000000ca }, { 0x00800040, 0x2440462d, 0x00b19810, 0x00b1d830 }, { 0x00800040, 0x2460462d, 0x00b19c20, 0x00b1dc00 }, { 0x00800201, 0x24a00129, 0x00b19820, 0x00000000 }, { 0x00818022, 0x34001c00, 0x02001400, 0x00000066 }, { 0x05800010, 0x200035ac, 0x028d2400, 0x000005e8 }, { 0x00800040, 0x2520462d, 0x00b19830, 0x00b19820 }, { 0x00800040, 0x2540462d, 0x00b19c00, 0x00b19c10 }, { 0x00000201, 0x26000108, 0x00000602, 0x00000000 }, { 0x05810010, 0x200035ac, 0x028d2440, 0x000005d2 }, { 0x05810010, 0x200035ac, 0x008d2460, 0x000005d2 }, { 0x00818022, 0x34001c00, 0x02001400, 0x0000001e }, { 0x00800040, 0x2560462d, 0x00b19810, 0x00b19800 }, { 0x00800040, 0x238045ad, 0x008d0520, 0x00b19c00 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00040004 }, { 0x00800040, 0x23a0458d, 0x00b10400, 0x00b19810 }, { 0x00800048, 0x24003dac, 0x008d0560, 0x00020002 }, { 0x80800008, 0x43c03d91, 0x00b10400, 0x00030003 }, { 0x00800040, 0x24003dac, 0x00b103a0, 0xfffefffe }, { 0x80800008, 0x43603d91, 0x00b10400, 0x00020002 }, { 0x00800040, 0x2400362c, 0x00b19c10, 0x00b10380 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00b103a0 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00030003 }, { 0x00800001, 0xb8100231, 0x00ae03c0, 0x00000000 }, { 0x00800001, 0xb8200231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0xb8300231, 0x00ae0340, 0x00000000 }, { 0x00808024, 0x34001c00, 0x00001400, 0x0001000e }, { 0x00800040, 0x2400362c, 0x00b19820, 0x008d0520 }, { 0x00800040, 0x2400458c, 0x00b10400, 0x00b19c10 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00020002 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00020002 }, { 0x00800001, 0xb8300231, 0x00ae0340, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00818022, 0x34001c00, 0x00001400, 0x0000001e }, { 0x00800040, 0x2580462d, 0x00b19c20, 0x00b19c30 }, { 0x00800040, 0x238045ad, 0x008d0540, 0x008d04b0 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00040004 }, { 0x00800040, 0x23a0458d, 0x00b10400, 0x00b19c20 }, { 0x00800048, 0x24003dac, 0x008d0580, 0x00020002 }, { 0x80800008, 0x43c03d91, 0x00b10400, 0x00030003 }, { 0x00800040, 0x24003dac, 0x00b103a0, 0xfffefffe }, { 0x80800008, 0x43603d91, 0x00b10400, 0x00020002 }, { 0x00800040, 0x2400362c, 0x008d04a0, 0x00b10380 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00b103a0 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00030003 }, { 0x00800001, 0xbc200231, 0x00ae03c0, 0x00000000 }, { 0x00800001, 0xbc100231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0xbc000231, 0x00ae0340, 0x00000000 }, { 0x00808024, 0x34001c00, 0x00001400, 0x0001000e }, { 0x00800040, 0x2400362c, 0x008d04a0, 0x008d0540 }, { 0x00800040, 0x2400458c, 0x00b10400, 0x00b19c10 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00020002 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00020002 }, { 0x00800001, 0xbc000231, 0x00ae0340, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00808024, 0x34001c00, 0x00001400, 0x0001005c }, { 0x00800201, 0x23e0022d, 0x002805d4, 0x00000000 }, { 0x00800201, 0x23c0022d, 0x002805d4, 0x00000000 }, { 0x05800010, 0x200035ac, 0x008d2440, 0x000005d2 }, { 0x05800010, 0x200035ac, 0x028d2460, 0x000005d2 }, { 0x00800040, 0x24003e2c, 0x00b19820, 0x00040004 }, { 0x00800048, 0x24003dac, 0x008d0400, 0x00040004 }, { 0x00800040, 0x2400458c, 0x00b10400, 0x00b1dc10 }, { 0x00800008, 0x23403d8d, 0x00b10400, 0x00030003 }, { 0x00810040, 0x23e03dad, 0x008d03e0, 0x00010001 }, { 0x00200201, 0x25ec018d, 0x00450600, 0x00000000 }, { 0x00810040, 0x23e03dad, 0x028d03e0, 0x00010001 }, { 0x03800010, 0x200035ac, 0x008d0340, 0x008d03e0 }, { 0x05800010, 0x200035ac, 0x028d0340, 0x008d43e0 }, { 0x00800042, 0x24c0462d, 0x00b19830, 0x00b19c00 }, { 0x00810001, 0x234001ad, 0x008d03e0, 0x00000000 }, { 0x00810001, 0x234001ad, 0x028d43e0, 0x00000000 }, { 0x00200201, 0x260001ac, 0x004505ec, 0x00000000 }, { 0x80800040, 0x43603631, 0x00b19830, 0x008d0340 }, { 0x80800040, 0x43403631, 0x00b19c00, 0x008d4340 }, { 0x00800001, 0xb8300231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0xbc000231, 0x00ae0340, 0x00000000 }, { 0x00818022, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00800040, 0x2400362c, 0x00b19810, 0x008d04c0 }, { 0x00800048, 0x24003e2c, 0x00b19820, 0xfffefffe }, { 0x00800008, 0x23603d8d, 0x00b10400, 0x00010001 }, { 0x03800010, 0x200035ac, 0x008d0360, 0x008d03c0 }, { 0x05800010, 0x200035ac, 0x028d0360, 0x008d43c0 }, { 0x00810001, 0x236001ad, 0x008d03c0, 0x00000000 }, { 0x00810001, 0x236001ad, 0x028d43c0, 0x00000000 }, { 0x00000201, 0x260201ac, 0x000005ee, 0x00000000 }, { 0x80800040, 0x43603631, 0x00b19820, 0x008d0360 }, { 0x00800001, 0xb8200231, 0x00ae0360, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00818022, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00800040, 0x2400362c, 0x00b19c20, 0x008d04c0 }, { 0x00800048, 0x24003e2c, 0x00b19c10, 0xfffefffe }, { 0x00800008, 0x23603d8d, 0x00b10400, 0x00010001 }, { 0x03800010, 0x200035ac, 0x008d0360, 0x008d03c0 }, { 0x05800010, 0x200035ac, 0x028d0360, 0x008d43c0 }, { 0x00810001, 0x236001ad, 0x008d03c0, 0x00000000 }, { 0x00810001, 0x236001ad, 0x028d43c0, 0x00000000 }, { 0x80800040, 0x43603631, 0x00b19c10, 0x008d0360 }, { 0x00800001, 0xbc100231, 0x00ae0360, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007c0, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00a02001, 0x20400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x206601ed, 0x00000000, 0x00030003 }, { 0x00000009, 0x20663dad, 0x00000066, 0x000a000a }, { 0x00000001, 0x206801ed, 0x00000000, 0x01400140 }, { 0x00000001, 0x22600169, 0x00000000, 0x00030003 }, { 0x00000008, 0x22403dad, 0x00000026, 0x00010001 }, { 0x00000041, 0x224235ad, 0x00000020, 0x00000022 }, { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, { 0x00000001, 0x203c0022, 0x00000018, 0x00000000 }, { 0x00000001, 0x203f01f2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c00e2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c010a, 0x00000e00, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0020, 0x00000000 }, { 0x00400001, 0x205401ed, 0x00000000, 0x00000000 }, { 0x00200040, 0x20583dad, 0x00450020, 0xffffffff }, { 0x00000001, 0x22000060, 0x00000000, 0x06080000 }, { 0x00600001, 0x26000021, 0x008d0000, 0x00000000 }, { 0x00000001, 0x26140061, 0x00000000, 0x00c00400 }, { 0x00000001, 0x26100169, 0x00000000, 0x12121212 }, { 0x07600031, 0x26201c21, 0x308d0600, 0x02000000 }, { 0x00200401, 0x208000e5, 0x00000000, 0x00000000 }, { 0x00000c01, 0x208800e5, 0x00000000, 0xffffffc4 }, { 0x00000801, 0x208c00e5, 0x00000000, 0xffffffc8 }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00100010 }, { 0x00000001, 0x206001ed, 0x00000000, 0x00020002 }, { 0x00000001, 0x206201ad, 0x0000005a, 0x00000000 }, { 0x00000001, 0x20a001ed, 0x00000000, 0x00000000 }, { 0x00200001, 0x228001ed, 0x00000000, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21000061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21400061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21800061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21c00061, 0x00000000, 0x00ff00ff }, { 0x00000041, 0x22083dac, 0x00000056, 0x00040004 }, { 0x05000010, 0x200035ac, 0x02000280, 0x00000240 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x01000010, 0x20002d28, 0x000090c2, 0x00000000 }, { 0x03000010, 0x200035ac, 0x02000054, 0x00000058 }, { 0x00800001, 0x240001ac, 0x00000068, 0x00000000 }, { 0x00000048, 0x22a03dad, 0x00000056, 0x00040004 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffff2 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00200001, 0xb0c00229, 0x00450054, 0x00000000 }, { 0x00200040, 0x22803dad, 0x00450280, 0x00010001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x20380122, 0x00000260, 0x00000000 }, { 0x00800001, 0x204001ae, 0x00b10040, 0x00000000 }, { 0x00000008, 0x20003d2a, 0x000002a0, 0x00010001 }, { 0x00000040, 0x22602d29, 0x00000260, 0x00020002 }, { 0x00800031, 0x20000008, 0x608d0000, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x04200010, 0x200035ac, 0x00450054, 0x00450060 }, { 0x00010040, 0x20a03dad, 0x02000056, 0x00010001 }, { 0x05200010, 0x200035ac, 0x02450280, 0x00450240 }, { 0x00000001, 0x240001ec, 0x00000000, 0x00040004 }, { 0x00000048, 0x22083dac, 0x00000056, 0x00040004 }, { 0x00200040, 0x205455ad, 0x00450054, 0x00450034 }, { 0x02000010, 0x20003d8c, 0x00000600, 0x00010001 }, { 0x00000041, 0x220e3d8c, 0x00000602, 0x00040004 }, { 0x00010041, 0x22083dac, 0x000000a0, 0x00040004 }, { 0x00010401, 0x205601ad, 0x000000a0, 0x00000000 }, { 0x00010840, 0x20543d2d, 0x000090c0, 0x00010001 }, { 0x00000220, 0x34001400, 0x00001400, 0x00009c80 }, { 0x01000010, 0x20003dac, 0x02000280, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00600401, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000c01, 0x26140061, 0x00000000, 0x01800000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000801, 0x26100169, 0x00000000, 0x12121212 }, { 0x00000040, 0x2078252d, 0x00000026, 0x00004280 }, { 0x00400001, 0x26000231, 0x00000078, 0x00000000 }, { 0x00600031, 0x26201c21, 0x308d0600, 0x02000002 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffffe8 }, { 0x07600031, 0x20001c20, 0x30000000, 0x02000001 }, { 0x01600031, 0x20001c24, 0x708d0000, 0x82000012 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00600009, 0x25c03dad, 0x00050034, 0x00040004 }, { 0x00000001, 0x220801ec, 0x00000000, 0x02400240 }, { 0x00000041, 0x25e435a1, 0x00000020, 0x00000036 }, { 0x00000040, 0x25e43421, 0x000005e4, 0x00000034 }, { 0x00000041, 0x27e82c21, 0x000005e4, 0x00400040 }, { 0x00000001, 0x240001ec, 0x00000000, 0x01400140 }, { 0x00000048, 0x20263dad, 0x00000036, 0x00040004 }, { 0x00000040, 0x25c43dad, 0x000005c4, 0xfffcfffc }, { 0x00000040, 0x25ca3dad, 0x000005ca, 0xfffcfffc }, { 0x00800001, 0x2220022d, 0x000d002c, 0x00000000 }, { 0x00600040, 0x22303dad, 0x008d0230, 0x00080008 }, { 0x01600031, 0x22401c21, 0x408d07e0, 0x02885800 }, { 0x01800005, 0x20002d28, 0x02b19040, 0xffffffff }, { 0x02000005, 0x20003e2c, 0x00009030, 0x00010001 }, { 0x00000001, 0x25e20129, 0x00000036, 0x00000000 }, { 0x000b0220, 0x34001c00, 0x02001400, 0x00000126 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000124 }, { 0x00000401, 0x27e001a1, 0x000005c0, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00000001, 0x22000060, 0x00000000, 0x0248a002 }, { 0x02600031, 0x20c00021, 0x408d07e0, 0x00000200 }, { 0x00000401, 0x27e001a1, 0x000005c8, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005ca, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0001000f }, { 0x00000001, 0x22000060, 0x00000000, 0x02186004 }, { 0x02600031, 0x20800021, 0x408d07e0, 0x00000200 }, { 0x00800001, 0x2380012d, 0x008900c0, 0x00000000 }, { 0x00800001, 0x23a0012d, 0x00890100, 0x00000000 }, { 0x00800001, 0x23c0012d, 0x008900c8, 0x00000000 }, { 0x00800001, 0x23e0012d, 0x00890108, 0x00000000 }, { 0x00600401, 0x20c001a9, 0x00ab0380, 0x00000000 }, { 0x00600801, 0x20d001a9, 0x00ab0382, 0x00000000 }, { 0x00600401, 0x20e001a9, 0x00ab0384, 0x00000000 }, { 0x00600801, 0x20f001a9, 0x00ab0386, 0x00000000 }, { 0x00600401, 0x210001a9, 0x00ab03c0, 0x00000000 }, { 0x00600801, 0x211001a9, 0x00ab03c2, 0x00000000 }, { 0x00600401, 0x212001a9, 0x00ab03c4, 0x00000000 }, { 0x00600801, 0x213001a9, 0x00ab03c6, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00400040 }, { 0x00800008, 0x2340352d, 0x00009050, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x00009052, 0x008d0220 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000020 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x004590c0, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990a0, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000fc }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00410041 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c100c1 }, { 0x00200401, 0x25d0022d, 0x004590c8, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990b0, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000ee }, { 0x00800008, 0x2340352d, 0x00009042, 0x008d0220 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e000e0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00200401, 0x25d0022d, 0x004590c4, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990a4, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x00000001, 0x260201e8, 0x00000000, 0x00000000 }, { 0x00000401, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000801, 0x25d80109, 0x00000600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000d8 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e100e1 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01010101 }, { 0x00200401, 0x25d0022d, 0x004590cc, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990b4, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000ca }, { 0x00000401, 0x27e001a1, 0x000005c4, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c6, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x00070003 }, { 0x00600401, 0x2340012d, 0x00890040, 0x00000000 }, { 0x00600801, 0x2350012d, 0x00890048, 0x00000000 }, { 0x00600001, 0x204001aa, 0x00270340, 0x00000000 }, { 0x00600001, 0x205001aa, 0x00270350, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x04082004 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x00800001, 0x2380012d, 0x008900c0, 0x00000000 }, { 0x00800001, 0x23a0012d, 0x00890100, 0x00000000 }, { 0x00800001, 0x23c0012d, 0x008900c8, 0x00000000 }, { 0x00800001, 0x23e0012d, 0x00890108, 0x00000000 }, { 0x00600401, 0x20c001a9, 0x00ab0380, 0x00000000 }, { 0x00600801, 0x20d001a9, 0x00ab0382, 0x00000000 }, { 0x00600401, 0x20e001a9, 0x00ab0384, 0x00000000 }, { 0x00600801, 0x20f001a9, 0x00ab0386, 0x00000000 }, { 0x00600401, 0x210001a9, 0x00ab03c0, 0x00000000 }, { 0x00600801, 0x211001a9, 0x00ab03c2, 0x00000000 }, { 0x00600401, 0x212001a9, 0x00ab03c4, 0x00000000 }, { 0x00600801, 0x213001a9, 0x00ab03c6, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00800080 }, { 0x00800008, 0x2340352d, 0x00009054, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x00009056, 0x008d0220 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000020 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00800080 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x004590c2, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990a8, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00810081 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c100c1 }, { 0x00200401, 0x25d0022d, 0x004590ca, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990b8, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000078 }, { 0x00800008, 0x2340352d, 0x00009048, 0x008d0220 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e000e0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00200401, 0x25d0022d, 0x004590c4, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990ac, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x00000001, 0x260201e8, 0x00000000, 0x00000000 }, { 0x00000401, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000801, 0x25d80109, 0x00000600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000062 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e100e1 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01010101 }, { 0x00200401, 0x25d0022d, 0x004590cc, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990bc, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000054 }, { 0x00000401, 0x27e001a1, 0x000005c0, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00802001, 0x20400022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x0a082004 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x00000401, 0x27e001a1, 0x000005c8, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005ca, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0001000f }, { 0x00600001, 0x20400022, 0x008d0080, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x0418a004 }, { 0x01600031, 0x26400021, 0x508d07e0, 0x00000200 }, { 0x00600401, 0x2340012d, 0x008500cc, 0x00000000 }, { 0x00600801, 0x2350012d, 0x0085010c, 0x00000000 }, { 0x00800001, 0x236001ad, 0x002e0340, 0x00000000 }, { 0x00600001, 0x202000a2, 0x008d0360, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x04080020 }, { 0x00600001, 0x26400021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00000440, 0x27e03da1, 0x000005c0, 0x000c000c }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x00070003 }, { 0x02600031, 0x23401c25, 0x408d07e0, 0x02186004 }, { 0x00800001, 0x236001ad, 0x002e0340, 0x00000000 }, { 0x00600001, 0x202000a2, 0x008d0360, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x04080020 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00600040, 0x2400462d, 0x00ae9c00, 0x00aed810 }, { 0x00600040, 0x2340462d, 0x00ae9800, 0x00aed810 }, { 0x00600040, 0x2360462d, 0x00ae9c10, 0x00aedc00 }, { 0x05810010, 0x200035ac, 0x008d2400, 0x000005d0 }, { 0x05810010, 0x200035ac, 0x008d2340, 0x000005d2 }, { 0x05810010, 0x200035ac, 0x008d2360, 0x000005d2 }, { 0x00618022, 0x34001c00, 0x00001400, 0x00000038 }, { 0x00618022, 0x34001c00, 0x02001400, 0x00000016 }, { 0x00600040, 0x24003e2c, 0x00ae9c10, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x00ae9800, 0x00020002 }, { 0x00600040, 0x2400458c, 0x008d0400, 0x00ae9810 }, { 0x80600008, 0x43403d91, 0x008d0400, 0x00020002 }, { 0x00600040, 0x24003e2c, 0x00ae9800, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x00ae9c10, 0x00020002 }, { 0x00600040, 0x2400458c, 0x008d0400, 0x00ae9c00 }, { 0x80600008, 0x43603d91, 0x008d0400, 0x00020002 }, { 0x00600001, 0xd8100231, 0x00ae0340, 0x00000000 }, { 0x00600001, 0xdc000231, 0x00ae0360, 0x00000000 }, { 0x00608024, 0x34001c00, 0x00001400, 0x00010020 }, { 0x00600201, 0x2400022c, 0x002405d4, 0x00000000 }, { 0x00600040, 0x23e03d8d, 0x008d0400, 0x00010001 }, { 0x00600040, 0x24003e2c, 0x00ae9800, 0x00040004 }, { 0x00600048, 0x24003dac, 0x008d0400, 0x00040004 }, { 0x00600040, 0x2400458c, 0x008d0400, 0x00aedc10 }, { 0x00600008, 0x23403d8d, 0x008d0400, 0x00030003 }, { 0x03600010, 0x200035ac, 0x008d0340, 0x008d03e0 }, { 0x05600010, 0x200035ac, 0x028d0340, 0x008d43e0 }, { 0x00610001, 0x234001ad, 0x008d03e0, 0x00000000 }, { 0x00610001, 0x234001ad, 0x028d43e0, 0x00000000 }, { 0x80600040, 0x43603631, 0x00ae9810, 0x008d0340 }, { 0x80600040, 0x43403631, 0x00ae9c00, 0x008d4340 }, { 0x00600001, 0xd8100231, 0x00ae0360, 0x00000000 }, { 0x00600001, 0xdc000231, 0x00ae0340, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007c0, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00a02001, 0x20400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x206601ed, 0x00000000, 0x00030003 }, { 0x00000009, 0x20663dad, 0x00000066, 0x000a000a }, { 0x00000008, 0x22403dad, 0x00000026, 0x00010001 }, { 0x00000041, 0x224235ad, 0x00000020, 0x00000022 }, { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, { 0x00000001, 0x203c0022, 0x00000018, 0x00000000 }, { 0x00000001, 0x203f01f2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c00e2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c010a, 0x00000e00, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0020, 0x00000000 }, { 0x00400001, 0x205401ed, 0x00000000, 0x00000000 }, { 0x00200040, 0x20583dad, 0x00450020, 0xffffffff }, { 0x00000001, 0x22000060, 0x00000000, 0x06080000 }, { 0x00600001, 0x26000021, 0x008d0000, 0x00000000 }, { 0x00000001, 0x26140061, 0x00000000, 0x00c00400 }, { 0x00000001, 0x26100169, 0x00000000, 0x12121212 }, { 0x07600031, 0x26201c21, 0x308d0600, 0x02000000 }, { 0x00000001, 0x22a00169, 0x00000000, 0x01400140 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00200020 }, { 0x00000001, 0x203801e2, 0x00000000, 0x00010001 }, { 0x00800001, 0x204001ae, 0x00b10020, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x000002a0, 0x00010001 }, { 0x00800031, 0x20000128, 0x608d07e0, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x22a00169, 0x00000000, 0x00000000 }, { 0x00000001, 0x22600169, 0x00000000, 0x00020002 }, { 0x00200401, 0x208000e5, 0x00000000, 0x00000000 }, { 0x00000c01, 0x208800e5, 0x00000000, 0xffffffc6 }, { 0x00000801, 0x208c00e5, 0x00000000, 0xffffffca }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00100010 }, { 0x00000001, 0x206001ed, 0x00000000, 0x00020002 }, { 0x00000001, 0x206201ad, 0x0000005a, 0x00000000 }, { 0x00000001, 0x20a001ed, 0x00000000, 0x00000000 }, { 0x00200001, 0x228001ed, 0x00000000, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21000061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21400061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21800061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21c00061, 0x00000000, 0x00ff00ff }, { 0x00000041, 0x22083dac, 0x00000056, 0x00040004 }, { 0x05000010, 0x200035ac, 0x02000280, 0x00000240 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x01000010, 0x20002d28, 0x000090c2, 0x00000000 }, { 0x03000010, 0x200035ac, 0x02000054, 0x00000058 }, { 0x00000041, 0x22a03dad, 0x00000056, 0x00040004 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffff4 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00200001, 0xb0c00229, 0x00450054, 0x00000000 }, { 0x00200040, 0x22803dad, 0x00450280, 0x00010001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x20380122, 0x00000260, 0x00000000 }, { 0x00800001, 0x204001ae, 0x00b10040, 0x00000000 }, { 0x00000008, 0x20003d2a, 0x000002a0, 0x00010001 }, { 0x00000040, 0x22602d29, 0x00000260, 0x00020002 }, { 0x00800031, 0x20000008, 0x608d0000, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x04200010, 0x200035ac, 0x00450054, 0x00450060 }, { 0x00010040, 0x20a03dad, 0x02000056, 0x00010001 }, { 0x05200010, 0x200035ac, 0x02450280, 0x00450240 }, { 0x00000001, 0x240001ec, 0x00000000, 0x00040004 }, { 0x00000048, 0x22083dac, 0x00000056, 0x00040004 }, { 0x00200040, 0x205455ad, 0x00450054, 0x00450034 }, { 0x02000010, 0x20003d8c, 0x00000600, 0x00010001 }, { 0x00000041, 0x220e3d8c, 0x00000602, 0x00040004 }, { 0x00010041, 0x22083dac, 0x000000a0, 0x00040004 }, { 0x00010401, 0x205601ad, 0x000000a0, 0x00000000 }, { 0x00010840, 0x20543d2d, 0x000090c0, 0x00010001 }, { 0x00000220, 0x34001400, 0x00001400, 0x00009c80 }, { 0x01000010, 0x20003dac, 0x02000280, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000006 }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffff6 }, { 0x05000010, 0x200035ac, 0x00000240, 0x00000026 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffffc }, { 0x07600031, 0x20001c20, 0x30000000, 0x02000001 }, { 0x01600031, 0x20001c24, 0x708d0000, 0x82000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00600009, 0x25c03dad, 0x00050034, 0x00040004 }, { 0x00000001, 0x220801ec, 0x00000000, 0x02400240 }, { 0x00000041, 0x20263d29, 0x00000036, 0x00040004 }, { 0x00000041, 0x25e435a1, 0x00000020, 0x00000036 }, { 0x00000040, 0x25e43421, 0x000005e4, 0x00000034 }, { 0x00000041, 0x27e82c21, 0x000005e4, 0x00400040 }, { 0x01600031, 0x22401c21, 0x408d07e0, 0x02885800 }, { 0x01800005, 0x20002d28, 0x02b19040, 0xffffffff }, { 0x02000005, 0x20003e2c, 0x00009030, 0x00010001 }, { 0x00000040, 0x25c43dad, 0x000005c4, 0xfffcfffc }, { 0x00000001, 0x25e20129, 0x00000036, 0x00000000 }, { 0x000b0220, 0x34001c00, 0x02001400, 0x0000018c }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000018a }, { 0x00000040, 0x25ca3dad, 0x000005ca, 0xfffcfffc }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c0, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f000f }, { 0x00010001, 0x22000060, 0x02000000, 0x0288e701 }, { 0x00110001, 0x22000060, 0x02000000, 0x0288e601 }, { 0x01600031, 0x20c00021, 0x408d07e0, 0x00000200 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c8, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00010001, 0x22000060, 0x02000000, 0x02286703 }, { 0x00110001, 0x22000060, 0x02000000, 0x02286603 }, { 0x03600031, 0x20800021, 0x408d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00a900c0, 0x00000000 }, { 0x00800801, 0x23900231, 0x00a90100, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00a90140, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00a90180, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00a900c4, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00a90104, 0x00000000 }, { 0x00800401, 0x23e00231, 0x00a90144, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00a90184, 0x00000000 }, { 0x00800401, 0x24000231, 0x00a900c8, 0x00000000 }, { 0x00800801, 0x24100231, 0x00a90108, 0x00000000 }, { 0x00800401, 0x24200231, 0x00a90148, 0x00000000 }, { 0x00800801, 0x24300231, 0x00a90188, 0x00000000 }, { 0x00800401, 0x24400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x24500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x24600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x24700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x20c00231, 0x00cf0380, 0x00000000 }, { 0x00800801, 0x20d00231, 0x00cf0381, 0x00000000 }, { 0x00800401, 0x20e00231, 0x00cf0382, 0x00000000 }, { 0x00800801, 0x20f00231, 0x00cf0383, 0x00000000 }, { 0x00800401, 0x21000231, 0x00cf03c0, 0x00000000 }, { 0x00800801, 0x21100231, 0x00cf03c1, 0x00000000 }, { 0x00800401, 0x21200231, 0x00cf03c2, 0x00000000 }, { 0x00800801, 0x21300231, 0x00cf03c3, 0x00000000 }, { 0x00800401, 0x21400231, 0x00cf0400, 0x00000000 }, { 0x00800801, 0x21500231, 0x00cf0401, 0x00000000 }, { 0x00800401, 0x21600231, 0x00cf0402, 0x00000000 }, { 0x00800801, 0x21700231, 0x00cf0403, 0x00000000 }, { 0x00800401, 0x21800231, 0x00cf0440, 0x00000000 }, { 0x00800801, 0x21900231, 0x00cf0441, 0x00000000 }, { 0x00800401, 0x21a00231, 0x00cf0442, 0x00000000 }, { 0x00800801, 0x21b00231, 0x00cf0443, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00400040 }, { 0x00000008, 0x25e83e2d, 0x00009080, 0x00020002 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x00459080, 0x00000000 }, { 0x00200c01, 0x25d80129, 0x00459050, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699060, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffb8c }, { 0x00000008, 0x25e83e2d, 0x00009084, 0x00020002 }, { 0x00200401, 0x25d0022d, 0x00459084, 0x00000000 }, { 0x00000801, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00c000c0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00000401, 0x25d80129, 0x00009040, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699064, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffb76 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00100010 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01000100 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01400140 }, { 0x00000401, 0x25d80129, 0x00009042, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699068, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffb68 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01400140 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01800180 }, { 0x00000401, 0x25d80129, 0x00009044, 0x00000000 }, { 0x00400801, 0x25d40231, 0x0069906c, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffb5a }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c4, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f0003 }, { 0x00800401, 0x23400231, 0x00a90040, 0x00000000 }, { 0x00800801, 0x23500231, 0x00a90044, 0x00000000 }, { 0x00800401, 0x23600231, 0x00a90048, 0x00000000 }, { 0x00800801, 0x23700231, 0x00a9004c, 0x00000000 }, { 0x00800001, 0x20400232, 0x002b0340, 0x00000000 }, { 0x00800001, 0x20500232, 0x002b0350, 0x00000000 }, { 0x00800001, 0x20600232, 0x002b0360, 0x00000000 }, { 0x00800001, 0x20700232, 0x002b0370, 0x00000000 }, { 0x00010001, 0x22000060, 0x02000000, 0x06082703 }, { 0x00110001, 0x22000060, 0x02000000, 0x06082603 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00a900c0, 0x00000000 }, { 0x00800801, 0x23900231, 0x00a90100, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00a90140, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00a90180, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00a900c4, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00a90104, 0x00000000 }, { 0x00800401, 0x23e00231, 0x00a90144, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00a90184, 0x00000000 }, { 0x00800401, 0x24000231, 0x00a900c8, 0x00000000 }, { 0x00800801, 0x24100231, 0x00a90108, 0x00000000 }, { 0x00800401, 0x24200231, 0x00a90148, 0x00000000 }, { 0x00800801, 0x24300231, 0x00a90188, 0x00000000 }, { 0x00800401, 0x24400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x24500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x24600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x24700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x20c00231, 0x00cf0380, 0x00000000 }, { 0x00800801, 0x20d00231, 0x00cf0381, 0x00000000 }, { 0x00800401, 0x20e00231, 0x00cf0382, 0x00000000 }, { 0x00800801, 0x20f00231, 0x00cf0383, 0x00000000 }, { 0x00800401, 0x21000231, 0x00cf03c0, 0x00000000 }, { 0x00800801, 0x21100231, 0x00cf03c1, 0x00000000 }, { 0x00800401, 0x21200231, 0x00cf03c2, 0x00000000 }, { 0x00800801, 0x21300231, 0x00cf03c3, 0x00000000 }, { 0x00800401, 0x21400231, 0x00cf0400, 0x00000000 }, { 0x00800801, 0x21500231, 0x00cf0401, 0x00000000 }, { 0x00800401, 0x21600231, 0x00cf0402, 0x00000000 }, { 0x00800801, 0x21700231, 0x00cf0403, 0x00000000 }, { 0x00800401, 0x21800231, 0x00cf0440, 0x00000000 }, { 0x00800801, 0x21900231, 0x00cf0441, 0x00000000 }, { 0x00800401, 0x21a00231, 0x00cf0442, 0x00000000 }, { 0x00800801, 0x21b00231, 0x00cf0443, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00800080 }, { 0x00000008, 0x25e83e2d, 0x00009082, 0x00020002 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00800080 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x00459082, 0x00000000 }, { 0x00200c01, 0x25d80129, 0x00459054, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699070, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffaea }, { 0x00000008, 0x25e83e2d, 0x00009084, 0x00020002 }, { 0x00200401, 0x25d0022d, 0x00459084, 0x00000000 }, { 0x00000801, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000040, 0x25e83dad, 0x000005e8, 0x00020002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00c000c0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00000401, 0x25d80129, 0x00009046, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699074, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffad4 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00100010 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01000100 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01400140 }, { 0x00000401, 0x25d80129, 0x00009048, 0x00000000 }, { 0x00400801, 0x25d40231, 0x00699078, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffac6 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01400140 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01800180 }, { 0x00000401, 0x25d80129, 0x0000904a, 0x00000000 }, { 0x00400801, 0x25d40231, 0x0069907c, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0xfffffab8 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c0, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20400022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x20c00022, 0x008d0140, 0x00000000 }, { 0x00802001, 0x21000022, 0x008d0180, 0x00000000 }, { 0x00010001, 0x22000060, 0x02000000, 0x12082703 }, { 0x00110001, 0x22000060, 0x02000000, 0x12082603 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c8, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00802001, 0x20400022, 0x008d0080, 0x00000000 }, { 0x00010001, 0x22000060, 0x02000000, 0x0618a703 }, { 0x00110001, 0x22000060, 0x02000000, 0x0618a603 }, { 0x01600031, 0x26400021, 0x508d07e0, 0x00000200 }, { 0x00800401, 0x23400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x23500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x23600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x23700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x23800231, 0x00cf0340, 0x00000000 }, { 0x00800801, 0x23900231, 0x00cf0341, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00cf0342, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00cf0343, 0x00000000 }, { 0x00802001, 0x202000a2, 0x008d0380, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x06080020 }, { 0x00600001, 0x26400021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000440, 0x27e03da1, 0x000005c0, 0x000c000c }, { 0x00000c01, 0x27e401a1, 0x000005c2, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f0003 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x02286003 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x00008024, 0x34001c00, 0x00001400, 0x00010008 }, { 0x00010001, 0x22000060, 0x02000000, 0x02286703 }, { 0x00110001, 0x22000060, 0x02000000, 0x02286603 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x02600031, 0x23400025, 0x408d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00cf0340, 0x00000000 }, { 0x00800801, 0x23900231, 0x00cf0341, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00cf0342, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00cf0343, 0x00000000 }, { 0x00802001, 0x202000a2, 0x008d0380, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x06080020 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00a02001, 0x20400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x206601ed, 0x00000000, 0x00030003 }, { 0x00000009, 0x20663dad, 0x00000066, 0x000a000a }, { 0x00000001, 0x206801ed, 0x00000000, 0x01400140 }, { 0x00000001, 0x22600169, 0x00000000, 0x00030003 }, { 0x00000008, 0x22403dad, 0x00000026, 0x00010001 }, { 0x00000041, 0x224235ad, 0x00000020, 0x00000022 }, { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, { 0x00000001, 0x203c0022, 0x00000018, 0x00000000 }, { 0x00000001, 0x203f01f2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c00e2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c010a, 0x00000e00, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0020, 0x00000000 }, { 0x00400001, 0x205401ed, 0x00000000, 0x00000000 }, { 0x00200040, 0x20583dad, 0x00450020, 0xffffffff }, { 0x00000001, 0x22000060, 0x00000000, 0x06080000 }, { 0x00600001, 0x26000021, 0x008d0000, 0x00000000 }, { 0x00000001, 0x26140061, 0x00000000, 0x00c00400 }, { 0x00000001, 0x26100169, 0x00000000, 0x12121212 }, { 0x07600031, 0x26201c21, 0x308d0600, 0x02000000 }, { 0x00200401, 0x208000e5, 0x00000000, 0x00000000 }, { 0x00000c01, 0x208800e5, 0x00000000, 0xffffffc4 }, { 0x00000801, 0x208c00e5, 0x00000000, 0xffffffc8 }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00100010 }, { 0x00000001, 0x206001ed, 0x00000000, 0x00020002 }, { 0x00000001, 0x206201ad, 0x0000005a, 0x00000000 }, { 0x00000001, 0x20a001ed, 0x00000000, 0x00000000 }, { 0x00200001, 0x228001ed, 0x00000000, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21000061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21400061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21800061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21c00061, 0x00000000, 0x00ff00ff }, { 0x00000041, 0x22083dac, 0x00000056, 0x00040004 }, { 0x05000010, 0x200035ac, 0x02000280, 0x00000240 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x01000010, 0x20002d28, 0x000090c2, 0x00000000 }, { 0x03000010, 0x200035ac, 0x02000054, 0x00000058 }, { 0x00800001, 0x240001ac, 0x00000068, 0x00000000 }, { 0x00000048, 0x22a03dad, 0x00000056, 0x00040004 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffff2 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00200001, 0xb0c00229, 0x00450054, 0x00000000 }, { 0x00200040, 0x22803dad, 0x00450280, 0x00010001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x20380122, 0x00000260, 0x00000000 }, { 0x00800001, 0x204001ae, 0x00b10040, 0x00000000 }, { 0x00000008, 0x20003d2a, 0x000002a0, 0x00010001 }, { 0x00000040, 0x22602d29, 0x00000260, 0x00020002 }, { 0x00800031, 0x20000008, 0x608d0000, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x04200010, 0x200035ac, 0x00450054, 0x00450060 }, { 0x00010040, 0x20a03dad, 0x02000056, 0x00010001 }, { 0x05200010, 0x200035ac, 0x02450280, 0x00450240 }, { 0x00000001, 0x240001ec, 0x00000000, 0x00040004 }, { 0x00000048, 0x22083dac, 0x00000056, 0x00040004 }, { 0x00200040, 0x205455ad, 0x00450054, 0x00450034 }, { 0x02000010, 0x20003d8c, 0x00000600, 0x00010001 }, { 0x00000041, 0x220e3d8c, 0x00000602, 0x00040004 }, { 0x00010041, 0x22083dac, 0x000000a0, 0x00040004 }, { 0x00010401, 0x205601ad, 0x000000a0, 0x00000000 }, { 0x00010840, 0x20543d2d, 0x000090c0, 0x00010001 }, { 0x00000220, 0x34001400, 0x00001400, 0x00009c80 }, { 0x01000010, 0x20003dac, 0x02000280, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00600401, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000c01, 0x26140061, 0x00000000, 0x01800000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000801, 0x26100169, 0x00000000, 0x12121212 }, { 0x00000040, 0x2078252d, 0x00000026, 0x00004280 }, { 0x00400001, 0x26000231, 0x00000078, 0x00000000 }, { 0x00600031, 0x26201c21, 0x308d0600, 0x02000002 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffffe8 }, { 0x07600031, 0x20001c20, 0x30000000, 0x02000001 }, { 0x01600031, 0x20001c24, 0x708d0000, 0x82000012 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00600009, 0x25c03dad, 0x00050034, 0x00040004 }, { 0x00000001, 0x220801ec, 0x00000000, 0x02400240 }, { 0x00000041, 0x25e435a1, 0x00000020, 0x00000036 }, { 0x00000040, 0x25e43421, 0x000005e4, 0x00000034 }, { 0x00000041, 0x27e82c21, 0x000005e4, 0x00400040 }, { 0x00000001, 0x240001ec, 0x00000000, 0x01400140 }, { 0x00000048, 0x20263dad, 0x00000036, 0x00040004 }, { 0x00000040, 0x25c43dad, 0x000005c4, 0xfffcfffc }, { 0x00000040, 0x25ca3dad, 0x000005ca, 0xfffcfffc }, { 0x00800001, 0x2220022d, 0x000d002c, 0x00000000 }, { 0x00600040, 0x22303dad, 0x008d0230, 0x00080008 }, { 0x01600031, 0x22401c21, 0x408d07e0, 0x02885800 }, { 0x01800005, 0x20002d28, 0x02b19040, 0xffffffff }, { 0x02000005, 0x20003e2c, 0x00009030, 0x00010001 }, { 0x00000001, 0x25e20129, 0x00000036, 0x00000000 }, { 0x000b0220, 0x34001c00, 0x02001400, 0x0000013a }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000138 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c0, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00010001, 0x22000060, 0x02000000, 0x0248e702 }, { 0x00110001, 0x22000060, 0x02000000, 0x0248e602 }, { 0x02600031, 0x20c00021, 0x408d07e0, 0x00000200 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c8, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005ca, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0001000f }, { 0x00010001, 0x22000060, 0x02000000, 0x02186704 }, { 0x00110001, 0x22000060, 0x02000000, 0x02186604 }, { 0x02600031, 0x20800021, 0x408d07e0, 0x00000200 }, { 0x00800001, 0x2380012d, 0x008900c0, 0x00000000 }, { 0x00800001, 0x23a0012d, 0x00890100, 0x00000000 }, { 0x00800001, 0x23c0012d, 0x008900c8, 0x00000000 }, { 0x00800001, 0x23e0012d, 0x00890108, 0x00000000 }, { 0x00600401, 0x20c001a9, 0x00ab0380, 0x00000000 }, { 0x00600801, 0x20d001a9, 0x00ab0382, 0x00000000 }, { 0x00600401, 0x20e001a9, 0x00ab0384, 0x00000000 }, { 0x00600801, 0x20f001a9, 0x00ab0386, 0x00000000 }, { 0x00600401, 0x210001a9, 0x00ab03c0, 0x00000000 }, { 0x00600801, 0x211001a9, 0x00ab03c2, 0x00000000 }, { 0x00600401, 0x212001a9, 0x00ab03c4, 0x00000000 }, { 0x00600801, 0x213001a9, 0x00ab03c6, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00400040 }, { 0x00800008, 0x2340352d, 0x00009050, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x00009052, 0x008d0220 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000020 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x004590c0, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990a0, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffc0c }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00410041 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c100c1 }, { 0x00200401, 0x25d0022d, 0x004590c8, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990b0, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffbfe }, { 0x00800008, 0x2340352d, 0x00009042, 0x008d0220 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e000e0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00200401, 0x25d0022d, 0x004590c4, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990a4, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x00000001, 0x260201e8, 0x00000000, 0x00000000 }, { 0x00000401, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000801, 0x25d80109, 0x00000600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffbe8 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e100e1 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01010101 }, { 0x00200401, 0x25d0022d, 0x004590cc, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990b4, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffbda }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c4, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c6, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x00070003 }, { 0x00600401, 0x2340012d, 0x00890040, 0x00000000 }, { 0x00600801, 0x2350012d, 0x00890048, 0x00000000 }, { 0x00600001, 0x204001aa, 0x00270340, 0x00000000 }, { 0x00600001, 0x205001aa, 0x00270350, 0x00000000 }, { 0x00010001, 0x22000060, 0x02000000, 0x04082704 }, { 0x00110001, 0x22000060, 0x02000000, 0x04082604 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x00800001, 0x2380012d, 0x008900c0, 0x00000000 }, { 0x00800001, 0x23a0012d, 0x00890100, 0x00000000 }, { 0x00800001, 0x23c0012d, 0x008900c8, 0x00000000 }, { 0x00800001, 0x23e0012d, 0x00890108, 0x00000000 }, { 0x00600401, 0x20c001a9, 0x00ab0380, 0x00000000 }, { 0x00600801, 0x20d001a9, 0x00ab0382, 0x00000000 }, { 0x00600401, 0x20e001a9, 0x00ab0384, 0x00000000 }, { 0x00600801, 0x20f001a9, 0x00ab0386, 0x00000000 }, { 0x00600401, 0x210001a9, 0x00ab03c0, 0x00000000 }, { 0x00600801, 0x211001a9, 0x00ab03c2, 0x00000000 }, { 0x00600401, 0x212001a9, 0x00ab03c4, 0x00000000 }, { 0x00600801, 0x213001a9, 0x00ab03c6, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00800080 }, { 0x00800008, 0x2340352d, 0x00009054, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x00009056, 0x008d0220 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000020 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00800080 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200401, 0x25d0022d, 0x004590c2, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990a8, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffb92 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00810081 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c100c1 }, { 0x00200401, 0x25d0022d, 0x004590ca, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990b8, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffb84 }, { 0x00800008, 0x2340352d, 0x00009048, 0x008d0220 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e000e0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00200401, 0x25d0022d, 0x004590c4, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990ac, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x00000001, 0x260201e8, 0x00000000, 0x00000000 }, { 0x00000401, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000801, 0x25d80109, 0x00000600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffb6e }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e100e1 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01010101 }, { 0x00200401, 0x25d0022d, 0x004590cc, 0x00000000 }, { 0x00400801, 0x25d40231, 0x006990bc, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffb60 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c0, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00802001, 0x20400022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0100, 0x00000000 }, { 0x00010001, 0x22000060, 0x02000000, 0x0a082704 }, { 0x00110001, 0x22000060, 0x02000000, 0x0a082604 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c8, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005ca, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0001000f }, { 0x00600001, 0x20400022, 0x008d0080, 0x00000000 }, { 0x00010001, 0x22000060, 0x02000000, 0x0418a704 }, { 0x00110001, 0x22000060, 0x02000000, 0x0418a604 }, { 0x01600031, 0x26400021, 0x508d07e0, 0x00000200 }, { 0x00600401, 0x2340012d, 0x008500cc, 0x00000000 }, { 0x00600801, 0x2350012d, 0x0085010c, 0x00000000 }, { 0x00800001, 0x236001ad, 0x002e0340, 0x00000000 }, { 0x00600001, 0x202000a2, 0x008d0360, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x04080020 }, { 0x00600001, 0x26400021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000440, 0x27e03da1, 0x000005c0, 0x000c000c }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x00070003 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x02186004 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x00008024, 0x34001c00, 0x00001400, 0x00010008 }, { 0x00010001, 0x22000060, 0x02000000, 0x02186704 }, { 0x00110001, 0x22000060, 0x02000000, 0x02186604 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x02600031, 0x23400025, 0x408d07e0, 0x00000200 }, { 0x00800001, 0x236001ad, 0x002e0340, 0x00000000 }, { 0x00600001, 0x202000a2, 0x008d0360, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x00000026, 0x00010001 }, { 0x00800031, 0x20001d28, 0x608d07e0, 0x04080020 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00a02001, 0x20400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x206601ed, 0x00000000, 0x00010001 }, { 0x00000009, 0x20663dad, 0x00000066, 0x000a000a }, { 0x00000001, 0x22600169, 0x00000000, 0x00010001 }, { 0x00000008, 0x22403dad, 0x00000026, 0x00010001 }, { 0x00000041, 0x224235ad, 0x00000020, 0x00000022 }, { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, { 0x00000001, 0x203c0022, 0x00000018, 0x00000000 }, { 0x00000001, 0x203f01f2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c00e2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c010a, 0x00000e00, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0020, 0x00000000 }, { 0x00400001, 0x205401ed, 0x00000000, 0x00000000 }, { 0x00200040, 0x20583dad, 0x00450020, 0xffffffff }, { 0x00000001, 0x22000060, 0x00000000, 0x06080000 }, { 0x00600001, 0x26000021, 0x008d0000, 0x00000000 }, { 0x00000001, 0x26140061, 0x00000000, 0x00c00400 }, { 0x00000001, 0x26100169, 0x00000000, 0x12121212 }, { 0x07600031, 0x26201c21, 0x308d0600, 0x02000000 }, { 0x00000001, 0x22a00169, 0x00000000, 0x01400140 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00200020 }, { 0x00000001, 0x203801e2, 0x00000000, 0x00010001 }, { 0x00800001, 0x204001ae, 0x00b10020, 0x00000000 }, { 0x00000008, 0x27e03d29, 0x000002a0, 0x00010001 }, { 0x00800031, 0x20000128, 0x608d07e0, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x22a00169, 0x00000000, 0x00000000 }, { 0x00000001, 0x22600169, 0x00000000, 0x00020002 }, { 0x00200401, 0x208000e5, 0x00000000, 0x00000000 }, { 0x00000c01, 0x208800e5, 0x00000000, 0xffffffc6 }, { 0x00000801, 0x208c00e5, 0x00000000, 0xffffffca }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00100010 }, { 0x00000001, 0x206001ed, 0x00000000, 0x00020002 }, { 0x00000001, 0x206201ad, 0x0000005a, 0x00000000 }, { 0x00000001, 0x20a001ed, 0x00000000, 0x00000000 }, { 0x00200001, 0x228001ed, 0x00000000, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21000061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21400061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21800061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21c00061, 0x00000000, 0x00ff00ff }, { 0x00000041, 0x22083dac, 0x00000056, 0x00040004 }, { 0x05000010, 0x200035ac, 0x02000280, 0x00000240 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x01000010, 0x20002d28, 0x000090c2, 0x00000000 }, { 0x03000010, 0x200035ac, 0x02000054, 0x00000058 }, { 0x00000041, 0x22a03dad, 0x00000056, 0x00040004 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffff4 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00200001, 0xb0c00229, 0x00450054, 0x00000000 }, { 0x00200040, 0x22803dad, 0x00450280, 0x00010001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x20380122, 0x00000260, 0x00000000 }, { 0x00800001, 0x204001ae, 0x00b10040, 0x00000000 }, { 0x00000008, 0x20003d2a, 0x000002a0, 0x00010001 }, { 0x00000040, 0x22602d29, 0x00000260, 0x00020002 }, { 0x00800031, 0x20000008, 0x608d0000, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x04200010, 0x200035ac, 0x00450054, 0x00450060 }, { 0x00010040, 0x20a03dad, 0x02000056, 0x00010001 }, { 0x05200010, 0x200035ac, 0x02450280, 0x00450240 }, { 0x00000001, 0x240001ec, 0x00000000, 0x00040004 }, { 0x00000048, 0x22083dac, 0x00000056, 0x00040004 }, { 0x00200040, 0x205455ad, 0x00450054, 0x00450034 }, { 0x02000010, 0x20003d8c, 0x00000600, 0x00010001 }, { 0x00000041, 0x220e3d8c, 0x00000602, 0x00040004 }, { 0x00010041, 0x22083dac, 0x000000a0, 0x00040004 }, { 0x00010401, 0x205601ad, 0x000000a0, 0x00000000 }, { 0x00010840, 0x20543d2d, 0x000090c0, 0x00010001 }, { 0x00000220, 0x34001400, 0x00001400, 0x00009c80 }, { 0x01000010, 0x20003dac, 0x02000280, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000006 }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffff6 }, { 0x05000010, 0x200035ac, 0x00000240, 0x00000026 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffffc }, { 0x07600031, 0x20001c20, 0x30000000, 0x02000001 }, { 0x01600031, 0x20001c24, 0x708d0000, 0x82000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00400441, 0x45c03dad, 0x00000034, 0x00100010 }, { 0x00400841, 0x45c23dad, 0x00000036, 0x00200020 }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00000001, 0x25e20129, 0x00000036, 0x00000000 }, { 0x00000041, 0x25e435a1, 0x00000020, 0x00000036 }, { 0x00000040, 0x25e43421, 0x000005e4, 0x00000034 }, { 0x00000041, 0x25e42c21, 0x000005e4, 0x00800080 }, { 0x00000040, 0x25c43dad, 0x000005c4, 0xfffcfffc }, { 0x00000040, 0x25ca3dad, 0x000005ca, 0xfffcfffc }, { 0x00000005, 0x202a3dad, 0x0000002a, 0xfffdfffd }, { 0x02000005, 0x20002d2c, 0x0200002a, 0x00020002 }, { 0x00000001, 0x27e80021, 0x000005e4, 0x00000000 }, { 0x00010040, 0x27e83c21, 0x020007e8, 0x00400040 }, { 0x01600031, 0x22401c21, 0x408d07e0, 0x02885800 }, { 0x00000001, 0x220801ec, 0x00000000, 0x02400240 }, { 0x01800005, 0x20002d28, 0x02b19040, 0xffffffff }, { 0x02000005, 0x20003e2c, 0x00009030, 0x00010001 }, { 0x00000005, 0x25ec2e29, 0x00009002, 0x000a000a }, { 0x00000005, 0x25ea2e29, 0x00009002, 0x00060006 }, { 0x000b0220, 0x34001c00, 0x02001400, 0x00000252 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000250 }, { 0x01000010, 0x20003d2c, 0x000005ec, 0x00080008 }, { 0x00000005, 0x25e03d8d, 0x00000600, 0x00010001 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a5, 0x004505c0, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f000f }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x0288a001 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x0288e701 }, { 0x00110001, 0x22000060, 0x02000000, 0x0288e601 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x20c00021, 0x408d07e0, 0x00000200 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c4, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f0003 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x02286003 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x02286703 }, { 0x00110001, 0x22000060, 0x02000000, 0x02286603 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x02600031, 0x23400025, 0x408d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00a900c0, 0x00000000 }, { 0x00800801, 0x23900231, 0x00a90100, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00a90140, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00a90180, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00a900c4, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00a90104, 0x00000000 }, { 0x00800401, 0x23e00231, 0x00a90144, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00a90184, 0x00000000 }, { 0x00800401, 0x24000231, 0x00a900c8, 0x00000000 }, { 0x00800801, 0x24100231, 0x00a90108, 0x00000000 }, { 0x00800401, 0x24200231, 0x00a90148, 0x00000000 }, { 0x00800801, 0x24300231, 0x00a90188, 0x00000000 }, { 0x00800401, 0x24400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x24500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x24600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x24700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x20c00231, 0x00cf0380, 0x00000000 }, { 0x00800801, 0x20d00231, 0x00cf0381, 0x00000000 }, { 0x00800401, 0x20e00231, 0x00cf0382, 0x00000000 }, { 0x00800801, 0x20f00231, 0x00cf0383, 0x00000000 }, { 0x00800401, 0x21000231, 0x00cf03c0, 0x00000000 }, { 0x00800801, 0x21100231, 0x00cf03c1, 0x00000000 }, { 0x00800401, 0x21200231, 0x00cf03c2, 0x00000000 }, { 0x00800801, 0x21300231, 0x00cf03c3, 0x00000000 }, { 0x00800401, 0x21400231, 0x00cf0400, 0x00000000 }, { 0x00800801, 0x21500231, 0x00cf0401, 0x00000000 }, { 0x00800401, 0x21600231, 0x00cf0402, 0x00000000 }, { 0x00800801, 0x21700231, 0x00cf0403, 0x00000000 }, { 0x00800401, 0x21800231, 0x00cf0440, 0x00000000 }, { 0x00800801, 0x21900231, 0x00cf0441, 0x00000000 }, { 0x00800401, 0x21a00231, 0x00cf0442, 0x00000000 }, { 0x00800801, 0x21b00231, 0x00cf0443, 0x00000000 }, { 0x00800401, 0x20400231, 0x00cf0340, 0x00000000 }, { 0x00800801, 0x20500231, 0x00cf0341, 0x00000000 }, { 0x00800401, 0x20600231, 0x00cf0342, 0x00000000 }, { 0x00800801, 0x20700231, 0x00cf0343, 0x00000000 }, { 0x01600010, 0x20003d2c, 0x000005ea, 0x00040004 }, { 0x01600010, 0x20003d2c, 0x020005ea, 0x00020002 }, { 0x00800001, 0x21c00229, 0x00009080, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00009081, 0x00000000 }, { 0x00800001, 0x22000229, 0x00289060, 0x00000000 }, { 0x00610401, 0x41c00229, 0x00009080, 0x00000000 }, { 0x00610801, 0x41c20229, 0x00009090, 0x00000000 }, { 0x00610401, 0x41e00229, 0x00009081, 0x00000000 }, { 0x00610801, 0x41e20229, 0x00009091, 0x00000000 }, { 0x00610401, 0x42000229, 0x00249060, 0x00000000 }, { 0x00610801, 0x42020229, 0x00249098, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00400040 }, { 0x00610401, 0x21c00229, 0x02009080, 0x00000000 }, { 0x00610801, 0x21d00229, 0x02009090, 0x00000000 }, { 0x00610401, 0x21e00229, 0x02009081, 0x00000000 }, { 0x00610801, 0x21f00229, 0x02009091, 0x00000000 }, { 0x00610401, 0x22000229, 0x02249060, 0x00000000 }, { 0x00610801, 0x22100229, 0x02249098, 0x00000000 }, { 0x00800008, 0x25a03d29, 0x008d01c0, 0x00020002 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200001, 0x25d80129, 0x00459050, 0x00000000 }, { 0x00800040, 0x25a03d29, 0x00b105a0, 0x00020002 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001b4 }, { 0x00800008, 0x25a03e29, 0x00009084, 0x00020002 }, { 0x00800001, 0x21c00229, 0x00009084, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00009085, 0x00000000 }, { 0x00000001, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00800040, 0x25a03d29, 0x00b105a0, 0x00020002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00c000c0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00000001, 0x25d80129, 0x00009040, 0x00000000 }, { 0x00800001, 0x22000229, 0x00289064, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000019c }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00100010 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01000100 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01400140 }, { 0x00000001, 0x25d80129, 0x00009042, 0x00000000 }, { 0x00800001, 0x22000229, 0x00289068, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000018e }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01400140 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01800180 }, { 0x00000001, 0x25d80129, 0x00009044, 0x00000000 }, { 0x00800001, 0x22000229, 0x0028906c, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000180 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c4, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f0003 }, { 0x00800401, 0x23400231, 0x00a90040, 0x00000000 }, { 0x00800801, 0x23500231, 0x00a90044, 0x00000000 }, { 0x00800401, 0x23600231, 0x00a90048, 0x00000000 }, { 0x00800801, 0x23700231, 0x00a9004c, 0x00000000 }, { 0x00800001, 0x20400232, 0x002b0340, 0x00000000 }, { 0x00800001, 0x20500232, 0x002b0350, 0x00000000 }, { 0x00800001, 0x20600232, 0x002b0360, 0x00000000 }, { 0x00800001, 0x20700232, 0x002b0370, 0x00000000 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x06082003 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x06082703 }, { 0x00110001, 0x22000060, 0x02000000, 0x06082603 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c8, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x22000060, 0x00000000, 0x02286003 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x01000005, 0x20003dac, 0x020005e0, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000006 }, { 0x00000440, 0x27e43ca5, 0x000007e4, 0xfffcfffc }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00000040, 0x22000c00, 0x00000200, 0x00200000 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000c }, { 0x0000000c, 0x27e43da5, 0x000005c2, 0x00010001 }, { 0x00010001, 0x22000060, 0x02000000, 0x02286703 }, { 0x00110001, 0x22000060, 0x02000000, 0x02286603 }, { 0x00000040, 0x27e43ca5, 0x000007e4, 0xfffcfffc }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x20400021, 0x408d07e0, 0x00000200 }, { 0x00800401, 0x23800231, 0x00a900c0, 0x00000000 }, { 0x00800801, 0x23900231, 0x00a90100, 0x00000000 }, { 0x00800401, 0x23a00231, 0x00a90140, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00a90180, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00a900c4, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00a90104, 0x00000000 }, { 0x00800401, 0x23e00231, 0x00a90144, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00a90184, 0x00000000 }, { 0x00800401, 0x24000231, 0x00a900c8, 0x00000000 }, { 0x00800801, 0x24100231, 0x00a90108, 0x00000000 }, { 0x00800401, 0x24200231, 0x00a90148, 0x00000000 }, { 0x00800801, 0x24300231, 0x00a90188, 0x00000000 }, { 0x00800401, 0x24400231, 0x00a900cc, 0x00000000 }, { 0x00800801, 0x24500231, 0x00a9010c, 0x00000000 }, { 0x00800401, 0x24600231, 0x00a9014c, 0x00000000 }, { 0x00800801, 0x24700231, 0x00a9018c, 0x00000000 }, { 0x00800401, 0x20c00231, 0x00cf0380, 0x00000000 }, { 0x00800801, 0x20d00231, 0x00cf0381, 0x00000000 }, { 0x00800401, 0x20e00231, 0x00cf0382, 0x00000000 }, { 0x00800801, 0x20f00231, 0x00cf0383, 0x00000000 }, { 0x00800401, 0x21000231, 0x00cf03c0, 0x00000000 }, { 0x00800801, 0x21100231, 0x00cf03c1, 0x00000000 }, { 0x00800401, 0x21200231, 0x00cf03c2, 0x00000000 }, { 0x00800801, 0x21300231, 0x00cf03c3, 0x00000000 }, { 0x00800401, 0x21400231, 0x00cf0400, 0x00000000 }, { 0x00800801, 0x21500231, 0x00cf0401, 0x00000000 }, { 0x00800401, 0x21600231, 0x00cf0402, 0x00000000 }, { 0x00800801, 0x21700231, 0x00cf0403, 0x00000000 }, { 0x00800401, 0x21800231, 0x00cf0440, 0x00000000 }, { 0x00800801, 0x21900231, 0x00cf0441, 0x00000000 }, { 0x00800401, 0x21a00231, 0x00cf0442, 0x00000000 }, { 0x00800801, 0x21b00231, 0x00cf0443, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00800080 }, { 0x00000001, 0x260201ac, 0x000005e0, 0x00000000 }, { 0x00800008, 0x25a03e29, 0x00009082, 0x00020002 }, { 0x00200001, 0x25d80129, 0x00459054, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00009082, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00009083, 0x00000000 }, { 0x00800001, 0x22000229, 0x00289070, 0x00000000 }, { 0x00800040, 0x25a03d29, 0x00b105a0, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000050 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000000a }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000d4 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000044 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x05000500 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x05400540 }, { 0x00800001, 0x25000129, 0x00ad0040, 0x00000000 }, { 0x00800001, 0x25200129, 0x00ad0080, 0x00000000 }, { 0x00800001, 0x25400129, 0x00ad00c0, 0x00000000 }, { 0x00800001, 0x25600129, 0x00ad0100, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000c2 }, { 0x00600001, 0x20600129, 0x008d0510, 0x00000000 }, { 0x00600001, 0x20800129, 0x008d0520, 0x00000000 }, { 0x00600001, 0x20a00129, 0x008d0530, 0x00000000 }, { 0x00600001, 0x20c00129, 0x008d0540, 0x00000000 }, { 0x00600001, 0x20e00129, 0x008d0550, 0x00000000 }, { 0x00600001, 0x21000129, 0x008d0560, 0x00000000 }, { 0x00800008, 0x25a03e29, 0x00009092, 0x00020002 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x05000500 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x05400540 }, { 0x00800001, 0x25000129, 0x00ad0050, 0x00000000 }, { 0x00800001, 0x25200129, 0x00ad0090, 0x00000000 }, { 0x00800001, 0x25400129, 0x00ad00d0, 0x00000000 }, { 0x00800001, 0x25600129, 0x00ad0110, 0x00000000 }, { 0x00200001, 0x25d80129, 0x0045905c, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00009092, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00009093, 0x00000000 }, { 0x00800001, 0x22000229, 0x0028909c, 0x00000000 }, { 0x00800040, 0x25a03d29, 0x00b105a0, 0x00020002 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000009a }, { 0x00600001, 0x20700129, 0x008d0510, 0x00000000 }, { 0x00600001, 0x20900129, 0x008d0520, 0x00000000 }, { 0x00600001, 0x20b00129, 0x008d0530, 0x00000000 }, { 0x00600001, 0x20d00129, 0x008d0540, 0x00000000 }, { 0x00600001, 0x20f00129, 0x008d0550, 0x00000000 }, { 0x00600001, 0x21100129, 0x008d0560, 0x00000000 }, { 0x00800008, 0x25a03e29, 0x00009084, 0x00020002 }, { 0x00800001, 0x21c00229, 0x00009084, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00009085, 0x00000000 }, { 0x00000001, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00800040, 0x25a03d29, 0x00b105a0, 0x00020002 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00c000c0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00000001, 0x25d80129, 0x00009046, 0x00000000 }, { 0x00800001, 0x22000229, 0x00289074, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000076 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00100010 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01000100 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01400140 }, { 0x00000001, 0x25d80129, 0x00009048, 0x00000000 }, { 0x00800001, 0x22000229, 0x00289078, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000068 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00200020 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x01400140 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01800180 }, { 0x00000001, 0x25d80129, 0x0000904a, 0x00000000 }, { 0x00800001, 0x22000229, 0x0028907c, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00110220, 0x34001c00, 0x00001400, 0x0000005a }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c0, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20400022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0100, 0x00000000 }, { 0x00802001, 0x20c00022, 0x008d0140, 0x00000000 }, { 0x00802001, 0x21000022, 0x008d0180, 0x00000000 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x12082003 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x12082703 }, { 0x00110001, 0x22000060, 0x02000000, 0x12082603 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x01800005, 0x20003dac, 0x020005e0, 0x00010001 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x00200401, 0x27e001a1, 0x004505c8, 0x00000000 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00812001, 0x20400022, 0x028d0040, 0x00000000 }, { 0x00912001, 0x20400022, 0x028d0080, 0x00000000 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x0618a003 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00100010 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000c }, { 0x0000000c, 0x27e43da5, 0x000005c2, 0x00010001 }, { 0x00010001, 0x22000060, 0x02000000, 0x0618a703 }, { 0x00110001, 0x22000060, 0x02000000, 0x0618a603 }, { 0x00000040, 0x27e43ca5, 0x000007e4, 0xfffcfffc }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x26400021, 0x508d07e0, 0x00000200 }, { 0x01000005, 0x20003dac, 0x0000002a, 0x00020002 }, { 0x00000006, 0x202a3dad, 0x0000002a, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffd94 }, { 0x00600001, 0x26400021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00800040, 0x2400462d, 0x00b19c00, 0x00b1d830 }, { 0x00800040, 0x2340462d, 0x00b19820, 0x00b1d830 }, { 0x00800040, 0x2360462d, 0x00b19c10, 0x00b1dc00 }, { 0x05810010, 0x200025ac, 0x008d2400, 0x008d01c0 }, { 0x05810010, 0x200025ac, 0x008d2340, 0x008d01e0 }, { 0x05810010, 0x200025ac, 0x008d2360, 0x008d01e0 }, { 0x00818022, 0x34001c00, 0x00001400, 0x000000c8 }, { 0x00800040, 0x2440462d, 0x00b19810, 0x00b1d830 }, { 0x00800040, 0x2460462d, 0x00b19c20, 0x00b1dc00 }, { 0x00800201, 0x24a00129, 0x00b19820, 0x00000000 }, { 0x00818022, 0x34001c00, 0x02001400, 0x00000066 }, { 0x05800010, 0x200025ac, 0x028d2400, 0x008d05a0 }, { 0x00800040, 0x2520462d, 0x00b19830, 0x00b19820 }, { 0x00800040, 0x2540462d, 0x00b19c00, 0x00b19c10 }, { 0x00000201, 0x26000108, 0x00000602, 0x00000000 }, { 0x05810010, 0x200025ac, 0x028d2440, 0x008d01e0 }, { 0x05810010, 0x200025ac, 0x008d2460, 0x008d01e0 }, { 0x00818022, 0x34001c00, 0x02001400, 0x0000001e }, { 0x00800040, 0x2560462d, 0x00b19810, 0x00b19800 }, { 0x00800040, 0x238045ad, 0x008d0520, 0x00b19c00 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00040004 }, { 0x00800040, 0x23a0458d, 0x00b10400, 0x00b19810 }, { 0x00800048, 0x24003dac, 0x008d0560, 0x00020002 }, { 0x80800008, 0x43c03d91, 0x00b10400, 0x00030003 }, { 0x00800040, 0x24003dac, 0x00b103a0, 0xfffefffe }, { 0x80800008, 0x43603d91, 0x00b10400, 0x00020002 }, { 0x00800040, 0x2400362c, 0x00b19c10, 0x00b10380 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00b103a0 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00030003 }, { 0x00800001, 0xb8100231, 0x00ae03c0, 0x00000000 }, { 0x00800001, 0xb8200231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0xb8300231, 0x00ae0340, 0x00000000 }, { 0x00808024, 0x34001c00, 0x00001400, 0x0001000e }, { 0x00800040, 0x2400362c, 0x00b19820, 0x008d0520 }, { 0x00800040, 0x2400458c, 0x00b10400, 0x00b19c10 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00020002 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00020002 }, { 0x00800001, 0xb8300231, 0x00ae0340, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00818022, 0x34001c00, 0x00001400, 0x0000001e }, { 0x00800040, 0x2580462d, 0x00b19c20, 0x00b19c30 }, { 0x00800040, 0x238045ad, 0x008d0540, 0x008d04b0 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00040004 }, { 0x00800040, 0x23a0458d, 0x00b10400, 0x00b19c20 }, { 0x00800048, 0x24003dac, 0x008d0580, 0x00020002 }, { 0x80800008, 0x43c03d91, 0x00b10400, 0x00030003 }, { 0x00800040, 0x24003dac, 0x00b103a0, 0xfffefffe }, { 0x80800008, 0x43603d91, 0x00b10400, 0x00020002 }, { 0x00800040, 0x2400362c, 0x008d04a0, 0x00b10380 }, { 0x00800040, 0x2400358c, 0x00b10400, 0x00b103a0 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00030003 }, { 0x00800001, 0xbc200231, 0x00ae03c0, 0x00000000 }, { 0x00800001, 0xbc100231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0xbc000231, 0x00ae0340, 0x00000000 }, { 0x00808024, 0x34001c00, 0x00001400, 0x0001000e }, { 0x00800040, 0x2400362c, 0x008d04a0, 0x008d0540 }, { 0x00800040, 0x2400458c, 0x00b10400, 0x00b19c10 }, { 0x00800040, 0x24003d8c, 0x00b10400, 0x00020002 }, { 0x80800008, 0x43403d91, 0x00b10400, 0x00020002 }, { 0x00800001, 0xbc000231, 0x00ae0340, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00808024, 0x34001c00, 0x00001400, 0x0001005a }, { 0x00800001, 0x23e0012d, 0x008d0200, 0x00000000 }, { 0x05800010, 0x200025ac, 0x008d2440, 0x008d01e0 }, { 0x05800010, 0x200025ac, 0x028d2460, 0x008d01e0 }, { 0x00800040, 0x24003e2c, 0x00b19820, 0x00040004 }, { 0x00800048, 0x24003dac, 0x008d0400, 0x00040004 }, { 0x00800040, 0x2400458c, 0x00b10400, 0x00b1dc10 }, { 0x00800008, 0x23403d8d, 0x00b10400, 0x00030003 }, { 0x00810040, 0x23e03dad, 0x008d03e0, 0x00010001 }, { 0x00200201, 0x25ec018d, 0x00450600, 0x00000000 }, { 0x00810040, 0x23e03dad, 0x028d03e0, 0x00010001 }, { 0x03800010, 0x200035ac, 0x008d0340, 0x008d03e0 }, { 0x05800010, 0x200035ac, 0x028d0340, 0x008d43e0 }, { 0x00800042, 0x24c0462d, 0x00b19830, 0x00b19c00 }, { 0x00810001, 0x234001ad, 0x008d03e0, 0x00000000 }, { 0x00810001, 0x234001ad, 0x028d43e0, 0x00000000 }, { 0x00200201, 0x260001ac, 0x004505ec, 0x00000000 }, { 0x80800040, 0x43603631, 0x00b19830, 0x008d0340 }, { 0x80800040, 0x43403631, 0x00b19c00, 0x008d4340 }, { 0x00800001, 0xb8300231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0xbc000231, 0x00ae0340, 0x00000000 }, { 0x00818022, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00800040, 0x2400362c, 0x00b19810, 0x008d04c0 }, { 0x00800048, 0x24003e2c, 0x00b19820, 0xfffefffe }, { 0x00800008, 0x23603d8d, 0x00b10400, 0x00010001 }, { 0x03800010, 0x200025ac, 0x008d0360, 0x008d0200 }, { 0x05800010, 0x200025ac, 0x028d0360, 0x008d4200 }, { 0x00810001, 0x2360012d, 0x008d0200, 0x00000000 }, { 0x00810001, 0x2360012d, 0x028d4200, 0x00000000 }, { 0x00000201, 0x260201ac, 0x000005ee, 0x00000000 }, { 0x80800040, 0x43603631, 0x00b19820, 0x008d0360 }, { 0x00800001, 0xb8200231, 0x00ae0360, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00818022, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00800040, 0x2400362c, 0x00b19c20, 0x008d04c0 }, { 0x00800048, 0x24003e2c, 0x00b19c10, 0xfffefffe }, { 0x00800008, 0x23603d8d, 0x00b10400, 0x00010001 }, { 0x03800010, 0x200025ac, 0x008d0360, 0x008d0200 }, { 0x05800010, 0x200025ac, 0x028d0360, 0x008d4200 }, { 0x00810001, 0x2360012d, 0x008d0200, 0x00000000 }, { 0x00810001, 0x2360012d, 0x028d4200, 0x00000000 }, { 0x80800040, 0x43603631, 0x00b19c10, 0x008d0360 }, { 0x00800001, 0xbc100231, 0x00ae0360, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007c0, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00a02001, 0x20400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x206601ed, 0x00000000, 0x00010001 }, { 0x00000009, 0x20663dad, 0x00000066, 0x000a000a }, { 0x00000001, 0x206801ed, 0x00000000, 0x01400140 }, { 0x00000001, 0x22600169, 0x00000000, 0x00030003 }, { 0x00000008, 0x22403dad, 0x00000026, 0x00010001 }, { 0x00000041, 0x224235ad, 0x00000020, 0x00000022 }, { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, { 0x00000001, 0x203c0022, 0x00000018, 0x00000000 }, { 0x00000001, 0x203f01f2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c00e2, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c010a, 0x00000e00, 0x00000000 }, { 0x00600001, 0x20400021, 0x008d0020, 0x00000000 }, { 0x00400001, 0x205401ed, 0x00000000, 0x00000000 }, { 0x00200040, 0x20583dad, 0x00450020, 0xffffffff }, { 0x00000001, 0x22000060, 0x00000000, 0x06080000 }, { 0x00600001, 0x26000021, 0x008d0000, 0x00000000 }, { 0x00000001, 0x26140061, 0x00000000, 0x00c00400 }, { 0x00000001, 0x26100169, 0x00000000, 0x12121212 }, { 0x07600031, 0x26201c21, 0x308d0600, 0x02000000 }, { 0x00200401, 0x208000e5, 0x00000000, 0x00000000 }, { 0x00000c01, 0x208800e5, 0x00000000, 0xffffffc4 }, { 0x00000801, 0x208c00e5, 0x00000000, 0xffffffc8 }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d07e0, 0x00000000 }, { 0x00000040, 0x20283c22, 0x00000008, 0x00100010 }, { 0x00000001, 0x206001ed, 0x00000000, 0x00020002 }, { 0x00000001, 0x206201ad, 0x0000005a, 0x00000000 }, { 0x00000001, 0x20a001ed, 0x00000000, 0x00000000 }, { 0x00200001, 0x228001ed, 0x00000000, 0x00000000 }, { 0x00802001, 0x20c00061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21000061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21400061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21800061, 0x00000000, 0x00ff00ff }, { 0x00802001, 0x21c00061, 0x00000000, 0x00ff00ff }, { 0x00000041, 0x22083dac, 0x00000056, 0x00040004 }, { 0x05000010, 0x200035ac, 0x02000280, 0x00000240 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000004 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x01000010, 0x20002d28, 0x000090c2, 0x00000000 }, { 0x03000010, 0x200035ac, 0x02000054, 0x00000058 }, { 0x00800001, 0x240001ac, 0x00000068, 0x00000000 }, { 0x00000048, 0x22a03dad, 0x00000056, 0x00040004 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffff2 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00200001, 0xb0c00229, 0x00450054, 0x00000000 }, { 0x00200040, 0x22803dad, 0x00450280, 0x00010001 }, { 0x00000001, 0x20300022, 0x00000010, 0x00000000 }, { 0x00000001, 0x20380122, 0x00000260, 0x00000000 }, { 0x00800001, 0x204001ae, 0x00b10040, 0x00000000 }, { 0x00000008, 0x20003d2a, 0x000002a0, 0x00010001 }, { 0x00000040, 0x22602d29, 0x00000260, 0x00020002 }, { 0x00800031, 0x20000008, 0x608d0000, 0x00000200 }, { 0x00000006, 0x203025a2, 0x00000066, 0x000002a0 }, { 0x01600031, 0x20001c00, 0x708d0000, 0x02000001 }, { 0x04200010, 0x200035ac, 0x00450054, 0x00450060 }, { 0x00010040, 0x20a03dad, 0x02000056, 0x00010001 }, { 0x05200010, 0x200035ac, 0x02450280, 0x00450240 }, { 0x00000001, 0x240001ec, 0x00000000, 0x00040004 }, { 0x00000048, 0x22083dac, 0x00000056, 0x00040004 }, { 0x00200040, 0x205455ad, 0x00450054, 0x00450034 }, { 0x02000010, 0x20003d8c, 0x00000600, 0x00010001 }, { 0x00000041, 0x220e3d8c, 0x00000602, 0x00040004 }, { 0x00010041, 0x22083dac, 0x000000a0, 0x00040004 }, { 0x00010401, 0x205601ad, 0x000000a0, 0x00000000 }, { 0x00010840, 0x20543d2d, 0x000090c0, 0x00010001 }, { 0x00000220, 0x34001400, 0x00001400, 0x00009c80 }, { 0x01000010, 0x20003dac, 0x02000280, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000014 }, { 0x00000030, 0x32000084, 0x00001200, 0x00000000 }, { 0x00000040, 0x22803dad, 0x00000280, 0xffffffff }, { 0x00600401, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000c01, 0x26140061, 0x00000000, 0x01800000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000801, 0x26100169, 0x00000000, 0x12121212 }, { 0x00000040, 0x2078252d, 0x00000026, 0x00004280 }, { 0x00400001, 0x26000231, 0x00000078, 0x00000000 }, { 0x00600031, 0x26201c21, 0x308d0600, 0x02000002 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffffe8 }, { 0x07600031, 0x20001c20, 0x30000000, 0x02000001 }, { 0x01600031, 0x20001c24, 0x708d0000, 0x82000012 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0000, 0x00000000 }, { 0x00400441, 0x45c03dad, 0x00000034, 0x00100010 }, { 0x00400841, 0x45c23dad, 0x00000036, 0x00200020 }, { 0x00200001, 0x260001ec, 0x00000000, 0x00000000 }, { 0x00000001, 0x25e20129, 0x00000036, 0x00000000 }, { 0x00000041, 0x25e435a1, 0x00000020, 0x00000036 }, { 0x00000040, 0x25e43421, 0x000005e4, 0x00000034 }, { 0x00000041, 0x25e42c21, 0x000005e4, 0x00800080 }, { 0x00000040, 0x25c43dad, 0x000005c4, 0xfffcfffc }, { 0x00000040, 0x25ca3dad, 0x000005ca, 0xfffcfffc }, { 0x00000005, 0x202a3dad, 0x0000002a, 0xfffdfffd }, { 0x00800001, 0x2220022d, 0x000d002c, 0x00000000 }, { 0x00600040, 0x22303dad, 0x008d0230, 0x00080008 }, { 0x02000005, 0x20002d2c, 0x0200002a, 0x00020002 }, { 0x00000001, 0x27e80021, 0x000005e4, 0x00000000 }, { 0x00010040, 0x27e83c21, 0x020007e8, 0x00400040 }, { 0x01600031, 0x22401c21, 0x408d07e0, 0x02885800 }, { 0x00000001, 0x220801ec, 0x00000000, 0x02400240 }, { 0x01800005, 0x20002d28, 0x02b19040, 0xffffffff }, { 0x02000005, 0x20003e2c, 0x00009030, 0x00010001 }, { 0x00000005, 0x25ec2e29, 0x00009002, 0x000a000a }, { 0x00000005, 0x25ea2e29, 0x00009002, 0x00060006 }, { 0x000b0220, 0x34001c00, 0x02001400, 0x00000252 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000250 }, { 0x01000010, 0x20003d2c, 0x000005ec, 0x00080008 }, { 0x00000005, 0x25e03d8d, 0x00000600, 0x00010001 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c0, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x0248a002 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x0248e702 }, { 0x00110001, 0x22000060, 0x02000000, 0x0248e602 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x02600031, 0x20c00021, 0x408d07e0, 0x00000200 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c4, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c6, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x00070003 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x02186004 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x02186704 }, { 0x00110001, 0x22000060, 0x02000000, 0x02186604 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x02600031, 0x23400025, 0x408d07e0, 0x00000200 }, { 0x00800001, 0x2380012d, 0x008900c0, 0x00000000 }, { 0x00800001, 0x23a0012d, 0x00890100, 0x00000000 }, { 0x00800001, 0x23c0012d, 0x008900c8, 0x00000000 }, { 0x00800001, 0x23e0012d, 0x00890108, 0x00000000 }, { 0x00600401, 0x20c001a9, 0x00ab0380, 0x00000000 }, { 0x00600801, 0x20d001a9, 0x00ab0382, 0x00000000 }, { 0x00600401, 0x20e001a9, 0x00ab0384, 0x00000000 }, { 0x00600801, 0x20f001a9, 0x00ab0386, 0x00000000 }, { 0x00600401, 0x210001a9, 0x00ab03c0, 0x00000000 }, { 0x00600801, 0x211001a9, 0x00ab03c2, 0x00000000 }, { 0x00600401, 0x212001a9, 0x00ab03c4, 0x00000000 }, { 0x00600801, 0x213001a9, 0x00ab03c6, 0x00000000 }, { 0x00800001, 0x204001a9, 0x002e0340, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00400040 }, { 0x01000010, 0x20003d2c, 0x020005ea, 0x00040004 }, { 0x00800008, 0x2340352d, 0x00009050, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x00009052, 0x008d0220 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000006a }, { 0x01000010, 0x20003d2c, 0x000005ea, 0x00020002 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x02600005, 0x20003dac, 0x00650340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02650360, 0x00010001 }, { 0x00400401, 0x41c00229, 0x000090c0, 0x00000000 }, { 0x00400801, 0x41c20229, 0x000090e0, 0x00000000 }, { 0x00400401, 0x41e00229, 0x000090c1, 0x00000000 }, { 0x00400801, 0x41e20229, 0x000090e1, 0x00000000 }, { 0x00400401, 0x42000229, 0x006990a0, 0x00000000 }, { 0x00400801, 0x42020229, 0x006990e8, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000001e }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000012 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00400401, 0x21c00229, 0x000090c0, 0x00000000 }, { 0x00400801, 0x21c80229, 0x000090e0, 0x00000000 }, { 0x00400401, 0x21e00229, 0x000090c1, 0x00000000 }, { 0x00400801, 0x21e80229, 0x000090e1, 0x00000000 }, { 0x00400401, 0x22000229, 0x006990a0, 0x00000000 }, { 0x00400801, 0x22080229, 0x006990e8, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000a }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00600001, 0x21c00229, 0x000090c0, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090c1, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490a0, 0x00000000 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001c8 }, { 0x01400010, 0x20003d2c, 0x000005ea, 0x00040004 }, { 0x01400010, 0x20003d2c, 0x020005ea, 0x00020002 }, { 0x00600001, 0x21c00229, 0x000090c8, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090c9, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490b0, 0x00000000 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00410041 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c100c1 }, { 0x00410401, 0x41c00229, 0x000090c8, 0x00000000 }, { 0x00410801, 0x41c20229, 0x000090f0, 0x00000000 }, { 0x00410401, 0x41e00229, 0x000090c9, 0x00000000 }, { 0x00410801, 0x41e20229, 0x000090f1, 0x00000000 }, { 0x00410401, 0x42000229, 0x006990b0, 0x00000000 }, { 0x00410801, 0x42020229, 0x006990f8, 0x00000000 }, { 0x00410401, 0x21c00229, 0x020090c8, 0x00000000 }, { 0x00410801, 0x21c80229, 0x020090f0, 0x00000000 }, { 0x00410401, 0x21e00229, 0x020090c9, 0x00000000 }, { 0x00410801, 0x21e80229, 0x020090f1, 0x00000000 }, { 0x00410401, 0x22000229, 0x026990b0, 0x00000000 }, { 0x00410801, 0x22080229, 0x026990f8, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000019c }, { 0x00800008, 0x2340352d, 0x00009042, 0x008d0220 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e000e0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00600001, 0x21c00229, 0x000090c4, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090c5, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490a4, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x00000001, 0x260201e8, 0x00000000, 0x00000000 }, { 0x00000401, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000801, 0x25d80109, 0x00000600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000184 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e100e1 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01010101 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00600001, 0x21c00229, 0x000090cc, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090cd, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490b4, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000174 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c4, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c6, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x00070003 }, { 0x00600401, 0x2340012d, 0x00890040, 0x00000000 }, { 0x00600801, 0x2350012d, 0x00890048, 0x00000000 }, { 0x00600001, 0x204001aa, 0x00270340, 0x00000000 }, { 0x00600001, 0x205001aa, 0x00270350, 0x00000000 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x04082004 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x04082704 }, { 0x00110001, 0x22000060, 0x02000000, 0x04082604 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c8, 0x00000000 }, { 0x00000c0c, 0x27e43da5, 0x000005ca, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0001000f }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x22000060, 0x00000000, 0x02186004 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x01000005, 0x20003dac, 0x020005e0, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000006 }, { 0x00000440, 0x27e43ca5, 0x000007e4, 0xfffefffe }, { 0x00000801, 0x27e80061, 0x00000000, 0x0003000f }, { 0x00000040, 0x22000c00, 0x00000200, 0x00100000 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000c }, { 0x0000000c, 0x27e43da5, 0x000005c2, 0x00020002 }, { 0x00010001, 0x22000060, 0x02000000, 0x02186704 }, { 0x00110001, 0x22000060, 0x02000000, 0x02186604 }, { 0x00000040, 0x27e43ca5, 0x000007e4, 0xfffefffe }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x02600031, 0x20400021, 0x408d07e0, 0x00000200 }, { 0x00800001, 0x2380012d, 0x008900c0, 0x00000000 }, { 0x00800001, 0x23a0012d, 0x00890100, 0x00000000 }, { 0x00800001, 0x23c0012d, 0x008900c8, 0x00000000 }, { 0x00800001, 0x23e0012d, 0x00890108, 0x00000000 }, { 0x00600401, 0x20c001a9, 0x00ab0380, 0x00000000 }, { 0x00600801, 0x20d001a9, 0x00ab0382, 0x00000000 }, { 0x00600401, 0x20e001a9, 0x00ab0384, 0x00000000 }, { 0x00600801, 0x20f001a9, 0x00ab0386, 0x00000000 }, { 0x00600401, 0x210001a9, 0x00ab03c0, 0x00000000 }, { 0x00600801, 0x211001a9, 0x00ab03c2, 0x00000000 }, { 0x00600401, 0x212001a9, 0x00ab03c4, 0x00000000 }, { 0x00600801, 0x213001a9, 0x00ab03c6, 0x00000000 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00800080 }, { 0x00000001, 0x260201ac, 0x000005e0, 0x00000000 }, { 0x00800008, 0x2340352d, 0x00009054, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x00009056, 0x008d0220 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000084 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000026 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00400040 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c000c0 }, { 0x00600001, 0x21c00229, 0x000090c2, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090c3, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490a8, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000f0 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00410041 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x00c100c1 }, { 0x00600001, 0x21c00229, 0x000090ca, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090cb, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490b8, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000e0 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000005c }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x05000500 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x05200520 }, { 0x00800001, 0x25000129, 0x00ad0040, 0x00000000 }, { 0x00800001, 0x25200129, 0x00ad00c0, 0x00000000 }, { 0x00600001, 0x21c00229, 0x000090c2, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090c3, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490a8, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000c6 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x05010501 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x05210521 }, { 0x00600001, 0x21c00229, 0x000090ca, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090cb, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490b8, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000000b6 }, { 0x00800008, 0x2340352d, 0x0000905c, 0x008d0220 }, { 0x00800008, 0x2360352d, 0x0000905e, 0x008d0220 }, { 0x00600001, 0x20600129, 0x008d0510, 0x00000000 }, { 0x00600001, 0x20c00129, 0x008d0520, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x02600005, 0x20003dac, 0x02ae0360, 0x00010001 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x05000500 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x05200520 }, { 0x00800001, 0x25000129, 0x00ad0050, 0x00000000 }, { 0x00800001, 0x25200129, 0x00ad00d0, 0x00000000 }, { 0x00600001, 0x21c00229, 0x000090e2, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090e3, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490ec, 0x00000000 }, { 0x00200001, 0x25d80109, 0x00450600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000096 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x05010501 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x05210521 }, { 0x00600001, 0x21c00229, 0x000090f2, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090f3, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490fc, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00600001, 0x20700129, 0x008d0510, 0x00000000 }, { 0x00600001, 0x20d00129, 0x008d0520, 0x00000000 }, { 0x00800008, 0x2340352d, 0x00009048, 0x008d0220 }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e000e0 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01000100 }, { 0x00600001, 0x21c00229, 0x000090c4, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090c5, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490ac, 0x00000000 }, { 0x02600005, 0x20003dac, 0x00ae0340, 0x00010001 }, { 0x00000001, 0x260201e8, 0x00000000, 0x00000000 }, { 0x00000401, 0x25da01e9, 0x00000000, 0x00000000 }, { 0x00000801, 0x25d80109, 0x00000600, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000006a }, { 0x00000401, 0x220c01ec, 0x00000000, 0x00e100e1 }, { 0x00000801, 0x220e01ec, 0x00000000, 0x01010101 }, { 0x00600001, 0x21c00229, 0x000090cc, 0x00000000 }, { 0x00600001, 0x21e00229, 0x000090cd, 0x00000000 }, { 0x00600001, 0x22000229, 0x002490bc, 0x00000000 }, { 0x00200001, 0x26000128, 0x004505d8, 0x00000000 }, { 0x00000040, 0x27c01c01, 0x00001400, 0x00000020 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000005a }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c0, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005c2, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0007000f }, { 0x00802001, 0x20400022, 0x008d00c0, 0x00000000 }, { 0x00802001, 0x20800022, 0x008d0100, 0x00000000 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x0a082004 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000a }, { 0x00010001, 0x22000060, 0x02000000, 0x0a082704 }, { 0x00110001, 0x22000060, 0x02000000, 0x0a082604 }, { 0x0000000c, 0x27e43ca5, 0x000007e4, 0x00010001 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x20000020, 0x508d07e0, 0x00000200 }, { 0x01600005, 0x20003dac, 0x020005e0, 0x00010001 }, { 0x01000005, 0x20003e2c, 0x00009002, 0x00020002 }, { 0x00000401, 0x27e001a1, 0x000005c8, 0x00000000 }, { 0x00000c0c, 0x27e43da1, 0x000005ca, 0x00010001 }, { 0x00000801, 0x27e80061, 0x00000000, 0x0001000f }, { 0x00610001, 0x20400022, 0x028d0040, 0x00000000 }, { 0x00710001, 0x20400022, 0x028d0060, 0x00000000 }, { 0x02000005, 0x20003dac, 0x0200002a, 0x00020002 }, { 0x00018022, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x22000060, 0x00000000, 0x0418a004 }, { 0x00010040, 0x27e43ca5, 0x020007e4, 0x00080008 }, { 0x00008024, 0x34001c00, 0x00001400, 0x0001000c }, { 0x0000000c, 0x27e43da5, 0x000005c2, 0x00020002 }, { 0x00010001, 0x22000060, 0x02000000, 0x0418a704 }, { 0x00110001, 0x22000060, 0x02000000, 0x0418a604 }, { 0x00000040, 0x27e43ca5, 0x000007e4, 0xfffefffe }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x01600031, 0x26400021, 0x508d07e0, 0x00000200 }, { 0x01000005, 0x20003dac, 0x0000002a, 0x00020002 }, { 0x00000006, 0x202a3dad, 0x0000002a, 0x00020002 }, { 0x00010220, 0x34001c00, 0x00001400, 0xfffffd94 }, { 0x00600001, 0x26400021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x260001e1, 0x00000000, 0x00000000 }, { 0x00000009, 0x26143da1, 0x000005e2, 0x00120012 }, { 0x00000440, 0x26141c21, 0x00000614, 0x00020000 }, { 0x00000c01, 0x26120129, 0x0000000c, 0x00000000 }, { 0x00000c01, 0x26100169, 0x00000000, 0x12121212 }, { 0x00400801, 0x26000171, 0x00000000, 0xffffffff }, { 0x00600031, 0x20001c20, 0x308d0600, 0x82008002 }, { 0x00600040, 0x2400462d, 0x00ae9c00, 0x00aed810 }, { 0x00600040, 0x2340462d, 0x00ae9800, 0x00aed810 }, { 0x00600040, 0x2360462d, 0x00ae9c10, 0x00aedc00 }, { 0x05810010, 0x200025ac, 0x008d2400, 0x008d01c0 }, { 0x05810010, 0x200025ac, 0x008d2340, 0x008d01e0 }, { 0x05810010, 0x200025ac, 0x008d2360, 0x008d01e0 }, { 0x00618022, 0x34001c00, 0x00001400, 0x00000036 }, { 0x00618022, 0x34001c00, 0x02001400, 0x00000016 }, { 0x00600040, 0x24003e2c, 0x00ae9c10, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x00ae9800, 0x00020002 }, { 0x00600040, 0x2400458c, 0x008d0400, 0x00ae9810 }, { 0x80600008, 0x43403d91, 0x008d0400, 0x00020002 }, { 0x00600040, 0x24003e2c, 0x00ae9800, 0x00020002 }, { 0x00600048, 0x24003e2c, 0x00ae9c10, 0x00020002 }, { 0x00600040, 0x2400458c, 0x008d0400, 0x00ae9c00 }, { 0x80600008, 0x43603d91, 0x008d0400, 0x00020002 }, { 0x00600001, 0xd8100231, 0x00ae0340, 0x00000000 }, { 0x00600001, 0xdc000231, 0x00ae0360, 0x00000000 }, { 0x00608024, 0x34001c00, 0x00001400, 0x0001001e }, { 0x00600040, 0x23e03d2d, 0x008d0200, 0x00010001 }, { 0x00600040, 0x24003e2c, 0x00ae9800, 0x00040004 }, { 0x00600048, 0x24003dac, 0x008d0400, 0x00040004 }, { 0x00600040, 0x2400458c, 0x008d0400, 0x00aedc10 }, { 0x00600008, 0x23403d8d, 0x008d0400, 0x00030003 }, { 0x03600010, 0x200035ac, 0x008d0340, 0x008d03e0 }, { 0x05600010, 0x200035ac, 0x028d0340, 0x008d43e0 }, { 0x00610001, 0x234001ad, 0x008d03e0, 0x00000000 }, { 0x00610001, 0x234001ad, 0x028d43e0, 0x00000000 }, { 0x80600040, 0x43603631, 0x00ae9810, 0x008d0340 }, { 0x80600040, 0x43403631, 0x00ae9c00, 0x008d4340 }, { 0x00600001, 0xd8100231, 0x00ae0360, 0x00000000 }, { 0x00600001, 0xdc000231, 0x00ae0340, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00008025, 0x20000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x34000020, 0x000007c0, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/h264/mc/chromaMVAdjust.asm000066400000000000000000000013701231401140700230040ustar00rootroot00000000000000/* * Adjust chrom MV * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: ChromaMVAdjust.asm // // //#if !defined(__ChromaMVAdjust__) // Make sure this is only included once //#define __ChromaMVAdjust__ // Chroma MV adjustment add (1) acc0:w gPARITY:w gREFPARITY:w cmp.e.f0.0 (1) null:w acc0:w 0x1:w cmp.e.f0.1 (1) null:w acc0:w 0x100:w mov (1) gCHRMVADJ:w 0:w (f0.0) mov (1) gCHRMVADJ:w 2:w (f0.1) mov (1) gCHRMVADJ:w -2:w //#endif // !defined(__ChromaMVAdjust__) intel-driver-1.3.0/src/shaders/h264/mc/export.inc000066400000000000000000000301151231401140700214260ustar00rootroot00000000000000#define INTRA_16x16_IP 0 #define INTRA_16x16_VERTICAL_IP 14 #define INTRA_16x16_HORIZONTAL_IP 32 #define INTRA_16x16_DC_IP 52 #define INTRA_16x16_PLANE_IP 98 #define End_intra_Pred_16x16_Y_IP 166 #define End_add_Error_16x16_Y_IP 204 #define load_Intra_Ref_Y_IP 220 #define decode_Chroma_Intra_IP 238 #define INTRA_CHROMA_DC_IP 260 #define INTRA_CHROMA_HORIZONTAL_IP 320 #define INTRA_CHROMA_VERTICAL_IP 332 #define INTRA_Chroma_PLANE_IP 342 #define End_of_intra_Pred_Chroma_IP 392 #define save_16x16_Y_IP 436 #define INTRA_8x8_IP 464 #define INTRA_8x8_BLK2_IP 568 #define intra_Pred_8x8_Y_IP 640 #define INTRA_8X8_VERTICAL_IP 672 #define INTRA_8X8_HORIZONTAL_IP 682 #define INTRA_8X8_DC_IP 692 #define INTRA_8X8_DIAG_DOWN_LEFT_IP 724 #define INTRA_8X8_DIAG_DOWN_RIGHT_IP 744 #define INTRA_8X8_VERT_RIGHT_IP 772 #define INTRA_8X8_HOR_DOWN_IP 808 #define INTRA_8X8_VERT_LEFT_IP 842 #define INTRA_8X8_HOR_UP_IP 862 #define save_8x8_Y_IP 886 #define INTRA_4x4_IP 928 #define intra_Pred_4x4_Y_4_IP 1062 #define ADD_ERROR_SB0_IP 1074 #define ADD_ERROR_SB1_IP 1088 #define ADD_ERROR_SB2_IP 1108 #define ADD_ERROR_SB3_IP 1124 #define intra_Pred_4x4_Y_IP 1130 #define INTRA_4X4_VERTICAL_IP 1130 #define INTRA_4X4_HORIZONTAL_IP 1134 #define INTRA_4X4_DC_IP 1138 #define INTRA_4X4_DIAG_DOWN_LEFT_IP 1160 #define INTRA_4X4_DIAG_DOWN_RIGHT_IP 1174 #define INTRA_4X4_VERT_RIGHT_IP 1192 #define INTRA_4X4_HOR_DOWN_IP 1218 #define INTRA_4X4_VERT_LEFT_IP 1246 #define INTRA_4X4_HOR_UP_IP 1260 #define save_4x4_Y_IP 1276 #define INTRA_PCM_IP 1320 #define FRAME_MB_IP 1384 #define INIT_MBPARA_FRM_IP 1390 #define NOT_8x8_MODE_FRM_IP 1426 #define CONVERT_MVS_FRM_IP 1436 #define INIT_ADDRESS_REGS_FRM_IP 1446 #define LOOP_SUBMB_FRM_IP 1454 #define LOOP_DIR_FRM_IP 1460 #define LOADREF_MVXZERO_FRM_IP 1510 #define EXIT_LOADREF_Y_16x13_FRM_IP 1524 #define Interpolate_Y_8x8_Func_FRM_IP 1544 #define Interpolate_Y_8x8_Func2_FRM_IP 1574 #define Interpolate_Y_H_8x8_FRM_IP 1708 #define Interpolate_Y_V_8x8_FRM_IP 1790 #define VFILTER_8x8_FRM_IP 1812 #define Interpolate_Y_I_8x8_FRM_IP 1860 #define Average_8x8_FRM_IP 1880 #define Return_Interpolate_Y_8x8_FRM_IP 1888 #define Exit_Interpolate_Y_8x8_FRM_IP 1890 #define Interpolate_C_4x4_Func_FRM_IP 1890 #define PROCESS4x4_FRM_IP 1928 #define LOOP_SUBMBPT_FRM_IP 1930 #define Interpolate_Y_H_4x4_FRM_IP 2066 #define Interpolate_Y_V_4x4_FRM_IP 2108 #define VFILTER_4x4_FRM_IP 2142 #define Interpolate_Y_I_4x4_FRM_IP 2148 #define Average_4x4_FRM_IP 2160 #define Return_Interpolate_Y_4x4_FRM_IP 2162 #define Exit_Interpolate_Y_4x4_FRM_IP 2174 #define ROUND_SHIFT_C_FRM_IP 2222 #define LOOP_DIR_CONTINUE_FRM_IP 2230 #define Weighted_Prediction_FRM_IP 2236 #define DefaultWeightedPred_UniPred_FRM_IP 2244 #define DefaultWeightedPred_BiPred_FRM_IP 2256 #define WeightedPred_FRM_IP 2264 #define WeightedPred_Explicit_FRM_IP 2282 #define WeightedPred_LOOP_FRM_IP 2322 #define Return_WeightedPred_FRM_IP 2382 #define EXIT_LOOP_FRM_IP 2424 #define FIELD_MB_IP 2496 #define INIT_MBPARA_FLD_IP 2502 #define NOT_8x8_MODE_FLD_IP 2538 #define CONVERT_MVS_FLD_IP 2548 #define INIT_ADDRESS_REGS_FLD_IP 2558 #define LOOP_SUBMB_FLD_IP 2568 #define LOOP_DIR_FLD_IP 2574 #define LOADREF_MVXZERO_FLD_IP 2644 #define EXIT_LOADREF_Y_16x13_FLD_IP 2658 #define Interpolate_Y_8x8_Func_FLD_IP 2680 #define Interpolate_Y_8x8_Func2_FLD_IP 2710 #define Interpolate_Y_H_8x8_FLD_IP 2844 #define Interpolate_Y_V_8x8_FLD_IP 2926 #define VFILTER_8x8_FLD_IP 2948 #define Interpolate_Y_I_8x8_FLD_IP 2996 #define Average_8x8_FLD_IP 3016 #define Return_Interpolate_Y_8x8_FLD_IP 3024 #define Exit_Interpolate_Y_8x8_FLD_IP 3026 #define Interpolate_C_4x4_Func_FLD_IP 3026 #define PROCESS4x4_FLD_IP 3064 #define LOOP_SUBMBPT_FLD_IP 3066 #define Interpolate_Y_H_4x4_FLD_IP 3204 #define Interpolate_Y_V_4x4_FLD_IP 3246 #define VFILTER_4x4_FLD_IP 3280 #define Interpolate_Y_I_4x4_FLD_IP 3286 #define Average_4x4_FLD_IP 3298 #define Return_Interpolate_Y_4x4_FLD_IP 3300 #define Exit_Interpolate_Y_4x4_FLD_IP 3312 #define ROUND_SHIFT_C_FLD_IP 3360 #define LOOP_DIR_CONTINUE_FLD_IP 3368 #define Weighted_Prediction_FLD_IP 3374 #define DefaultWeightedPred_UniPred_FLD_IP 3382 #define DefaultWeightedPred_BiPred_FLD_IP 3394 #define WeightedPred_FLD_IP 3402 #define WeightedPred_Explicit_FLD_IP 3420 #define WeightedPred_LOOP_FLD_IP 3460 #define Return_WeightedPred_FLD_IP 3520 #define EXIT_LOOP_FLD_IP 3562 #define MBAFF_MB_IP 3640 #define INIT_MBPARA_MBF_IP 3646 #define NOT_8x8_MODE_MBF_IP 3682 #define CONVERT_MVS_MBF_IP 3692 #define INIT_ADDRESS_REGS_MBF_IP 3702 #define LOOP_SUBMB_MBF_IP 3716 #define LOOP_DIR_MBF_IP 3722 #define LOADREF_MVXZERO_MBF_IP 3796 #define EXIT_LOADREF_Y_16x13_MBF_IP 3810 #define Interpolate_Y_8x8_Func_MBF_IP 3832 #define Interpolate_Y_8x8_Func2_MBF_IP 3862 #define Interpolate_Y_H_8x8_MBF_IP 3996 #define Interpolate_Y_V_8x8_MBF_IP 4078 #define VFILTER_8x8_MBF_IP 4100 #define Interpolate_Y_I_8x8_MBF_IP 4148 #define Average_8x8_MBF_IP 4168 #define Return_Interpolate_Y_8x8_MBF_IP 4176 #define Exit_Interpolate_Y_8x8_MBF_IP 4178 #define Interpolate_C_4x4_Func_MBF_IP 4178 #define PROCESS4x4_MBF_IP 4216 #define LOOP_SUBMBPT_MBF_IP 4218 #define Interpolate_Y_H_4x4_MBF_IP 4356 #define Interpolate_Y_V_4x4_MBF_IP 4398 #define VFILTER_4x4_MBF_IP 4432 #define Interpolate_Y_I_4x4_MBF_IP 4438 #define Average_4x4_MBF_IP 4450 #define Return_Interpolate_Y_4x4_MBF_IP 4452 #define Exit_Interpolate_Y_4x4_MBF_IP 4464 #define ROUND_SHIFT_C_MBF_IP 4512 #define LOOP_DIR_CONTINUE_MBF_IP 4520 #define Weighted_Prediction_MBF_IP 4526 #define DefaultWeightedPred_UniPred_MBF_IP 4534 #define DefaultWeightedPred_BiPred_MBF_IP 4546 #define WeightedPred_MBF_IP 4554 #define WeightedPred_Explicit_MBF_IP 4572 #define WeightedPred_LOOP_MBF_IP 4612 #define Return_WeightedPred_MBF_IP 4672 #define EXIT_LOOP_MBF_IP 4714 #define SETHWSCOREBOARD_IP 4792 #define SetHWScoreboard_Loop_IP 4806 #define Parse_8_Loop_0_IP 4852 #define Parse_8_Loop_2_IP 4876 #define Parse_8_Loop_4_IP 4900 #define Parse_8_Loop_6_IP 4924 #define Parse_8_Loop_8_IP 4948 #define Parse_8_Loop_10_IP 4972 #define Parse_8_Loop_12_IP 4996 #define Parse_8_Loop_14_IP 5020 #define SetHWScoreboard_Remainder_IP 5062 #define SetHWScoreboard_Remainder_Loop_IP 5090 #define Output_Remainder_Intra_IP 5116 #define SetHWScoreboard_Done_IP 5128 #define SETHWSCOREBOARD_MBAFF_IP 5136 #define SetHWScoreboard_MBAFF_Loop_IP 5148 #define SET_SB_MBAFF_INTRA_0_IP 5208 #define SET_SB_MBAFF_0_IP 5230 #define NEXT_MB_MBAFF_0_IP 5238 #define SET_SB_MBAFF_INTRA_2_IP 5276 #define SET_SB_MBAFF_2_IP 5298 #define NEXT_MB_MBAFF_2_IP 5306 #define SET_SB_MBAFF_INTRA_4_IP 5344 #define SET_SB_MBAFF_4_IP 5366 #define NEXT_MB_MBAFF_4_IP 5374 #define SET_SB_MBAFF_INTRA_6_IP 5412 #define SET_SB_MBAFF_6_IP 5434 #define NEXT_MB_MBAFF_6_IP 5442 #define SET_SB_MBAFF_INTRA_8_IP 5480 #define SET_SB_MBAFF_8_IP 5502 #define NEXT_MB_MBAFF_8_IP 5510 #define SET_SB_MBAFF_INTRA_10_IP 5548 #define SET_SB_MBAFF_10_IP 5570 #define NEXT_MB_MBAFF_10_IP 5578 #define SET_SB_MBAFF_INTRA_12_IP 5616 #define SET_SB_MBAFF_12_IP 5638 #define NEXT_MB_MBAFF_12_IP 5646 #define SET_SB_MBAFF_INTRA_14_IP 5684 #define SET_SB_MBAFF_14_IP 5706 #define NEXT_MB_MBAFF_14_IP 5714 #define SetHWScoreboard_MBAFF_Remainder_IP 5756 #define SetHWScoreboard_MBAFF_Remainder_Loop_IP 5784 #define SET_SB_MBAFF_REM_INTRA_IP 5822 #define SET_SB_MBAFF_REM_IP 5846 #define Output_MBAFF_Remainder_Intra_IP 5856 #define SetHWScoreboard_MBAFF_Done_IP 5868 #define BSDRESET_IP 5870 #define DCRESETDUMMY_IP 5872 #define AVC_ILDB_ROOT_Y_ILDB_FRAME_IP 5880 #define SLEEP_ENTRY_Y_ILDB_FRAME_IP 5976 #define POST_SLEEP_Y_ILDB_FRAME_IP 5980 #define NEXT_MB_Y_ILDB_FRAME_IP 6010 #define ALL_SPAWNED_Y_ILDB_FRAME_IP 6034 #define ALL_DONE_Y_ILDB_FRAME_IP 6044 #define WAIT_FOR_UV_ILDB_FRAME_IP 6044 #define AVC_ILDB_CHILD_Y_ILDB_FRAME_IP 6056 #define WRITE_URB_Y_ILDB_FRAME_IP 6436 #define POST_ILDB_Y_ILDB_FRAME_IP 6444 #define READ_FOR_URB_Y_ILDB_FRAME_IP 6458 #define FILTER_Y_IP 6494 #define Y_ELSE3_IP 6560 #define Y_ENDIF3_IP 6574 #define Y_ELSE4_IP 6604 #define Y_ENDIF4_IP 6618 #define Y_ELSE2_IP 6618 #define Y_ENDIF6_IP 6684 #define Y_ENDIF7_IP 6706 #define Y_ENDIF2_IP 6710 #define Y_ENDIF1_IP 6710 #define AVC_ILDB_ROOT_UV_ILDB_FRAME_IP 6720 #define SLEEP_ENTRY_UV_ILDB_FRAME_IP 6798 #define POST_SLEEP_UV_ILDB_FRAME_IP 6802 #define NEXT_MB_UV_ILDB_FRAME_IP 6834 #define ALL_SPAWNED_UV_ILDB_FRAME_IP 6858 #define ALL_DONE_UV_ILDB_FRAME_IP 6882 #define AVC_ILDB_CHILD_UV_ILDB_FRAME_IP 6888 #define BYPASS_EXT_LEFT_EDGE_UV_ILDB_FRAME_IP 7008 #define BYPASS_EXT_TOP_EDGE_UV_ILDB_FRAME_IP 7126 #define WRITE_URB_UV_ILDB_FRAME_IP 7194 #define POST_ILDB_UV_ILDB_FRAME_IP 7202 #define READ_FOR_URB_UV_ILDB_FRAME_IP 7216 #define FILTER_UV_IP 7246 #define UV_ELSE2_IP 7282 #define UV_ENDIF2_IP 7314 #define UV_ENDIF1_IP 7314 #define AVC_ILDB_ROOT_Y_ILDB_FIELD_IP 7320 #define SLEEP_ENTRY_Y_ILDB_FIELD_IP 7416 #define POST_SLEEP_Y_ILDB_FIELD_IP 7420 #define NEXT_MB_Y_ILDB_FIELD_IP 7450 #define ALL_SPAWNED_Y_ILDB_FIELD_IP 7474 #define ALL_DONE_Y_ILDB_FIELD_IP 7484 #define WAIT_FOR_UV_ILDB_FIELD_IP 7484 #define AVC_ILDB_CHILD_Y_ILDB_FIELD_IP 7496 #define WRITE_URB_Y_ILDB_FIELD_IP 7896 #define POST_ILDB_Y_ILDB_FIELD_IP 7904 #define READ_FOR_URB_Y_ILDB_FIELD_IP 7918 #define ELSE_Y_4x16T_ILDB_FIELD_IP 7934 #define ENDIF_Y_4x16T_ILDB_FIELD_IP 7942 #define AVC_ILDB_ROOT_UV_ILDB_FIELD_IP 7976 #define SLEEP_ENTRY_UV_ILDB_FIELD_IP 8054 #define POST_SLEEP_UV_ILDB_FIELD_IP 8058 #define NEXT_MB_UV_ILDB_FIELD_IP 8090 #define ALL_SPAWNED_UV_ILDB_FIELD_IP 8114 #define ALL_DONE_UV_ILDB_FIELD_IP 8138 #define AVC_ILDB_CHILD_UV_ILDB_FIELD_IP 8144 #define BYPASS_EXT_LEFT_EDGE_UV_ILDB_FIELD_IP 8272 #define BYPASS_EXT_TOP_EDGE_UV_ILDB_FIELD_IP 8394 #define WRITE_URB_UV_ILDB_FIELD_IP 8470 #define POST_ILDB_UV_ILDB_FIELD_IP 8478 #define READ_FOR_URB_UV_ILDB_FIELD_IP 8492 #define ELSE_Y_2x8T_ILDB_FIELD_IP 8508 #define ENDIF_Y_2x8T_ILDB_FIELD_IP 8516 #define AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP 8544 #define SLEEP_ENTRY_Y_ILDB_MBAFF_IP 8642 #define POST_SLEEP_Y_ILDB_MBAFF_IP 8646 #define NEXT_MB_Y_ILDB_MBAFF_IP 8676 #define ALL_SPAWNED_Y_ILDB_MBAFF_IP 8700 #define ALL_DONE_Y_ILDB_MBAFF_IP 8710 #define WAIT_FOR_UV_ILDB_MBAFF_IP 8710 #define AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP 8720 #define RE_ENTRY_IP 8742 #define ELSE_Y_16x16T_ILDB_MBAFF_IP 8782 #define ENDIF_Y_16x16T_ILDB_MBAFF_IP 8792 #define ELSE_Y_4x16T_IP 8808 #define ENDIF_Y_4x16T_IP 8818 #define BYPASS_V1_Y_IP 8966 #define BYPASS_V2_Y_IP 8980 #define BYPASS_V3_Y_IP 8994 #define ELSE_Y_16x4T_IP 9024 #define ENDIF_Y_16x4T_IP 9034 #define NOT_DUAL_FIELD_IP 9060 #define ELSE_Y_16x4_IP 9060 #define ENDIF_Y_16x4_IP 9072 #define DUAL_FIELD_Y_IP 9168 #define H0_Y_DONE_IP 9236 #define ELSE_Y_16x16_IP 9310 #define ENDIF_Y_16x16_IP 9320 #define ELSE_Y_16x4_SAVE_IP 9342 #define ENDIF_Y_16x4_SAVE_IP 9354 #define SKIP_ILDB_IP 9356 #define POST_ILDB_IP 9364 #define FILTER_Y_MBAFF_IP 9378 #define MBAFF_Y_ELSE3_IP 9444 #define MBAFF_Y_ENDIF3_IP 9458 #define MBAFF_Y_ELSE4_IP 9488 #define MBAFF_Y_ENDIF4_IP 9502 #define MBAFF_Y_ELSE2_IP 9502 #define MBAFF_Y_ENDIF6_IP 9566 #define MBAFF_Y_ENDIF7_IP 9588 #define MBAFF_Y_ENDIF2_IP 9592 #define MBAFF_Y_ENDIF1_IP 9592 #define AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP 9600 #define SLEEP_ENTRY_UV_ILDB_MBAFF_IP 9678 #define POST_SLEEP_UV_ILDB_MBAFF_IP 9682 #define NEXT_MB_UV_ILDB_MBAFF_IP 9714 #define ALL_SPAWNED_UV_ILDB_MBAFF_IP 9738 #define ALL_DONE_UV_ILDB_MBAFF_IP 9762 #define AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP 9768 #define RE_ENTRY_UV_ILDB_MBAFF_IP 9794 #define ELSE_UV_8X8T_ILDB_MBAFF_IP 9836 #define ENDIF_UV_8X8T_ILDB_MBAFF_IP 9846 #define ELSE_Y_2x8T_ILDB_MBAFF_IP 9864 #define ENDIF_Y_2x8T_ILDB_MBAFF_IP 9874 #define V0_U_NEXT1_IP 9934 #define V0_U_NEXT2_IP 9954 #define V0_U_NEXT3_IP 9964 #define BYPASS_V0_UV_IP 10018 #define ELSE_UV_8X2T_IP 10082 #define ENDIF_UV_8X2T_IP 10092 #define NOT_DUAL_FIELD_UV_IP 10120 #define ELSE_UV_8X2_IP 10120 #define ENDIF_UV_8X2_IP 10132 #define DUAL_FIELD_UV_IP 10208 #define H0_UV_DONE_IP 10300 #define ELSE_UV_8X8_IP 10360 #define ENDIF_UV_8X8_IP 10370 #define ELSE_UV_8X2_SAVE_IP 10394 #define ENDIF_UV_8X2_SAVE_IP 10406 #define SKIP_ILDB_UV_ILDB_MBAFF_IP 10408 #define POST_ILDB_UV_ILDB_MBAFF_IP 10416 #define FILTER_UV_MBAFF_IP 10430 #define MBAFF_UV_ELSE2_IP 10466 #define MBAFF_UV_ENDIF2_IP 10496 #define MBAFF_UV_ENDIF1_IP 10496 #define AllAVC_END_IP 10500 intel-driver-1.3.0/src/shaders/h264/mc/export.inc.gen5000066400000000000000000000334121231401140700222660ustar00rootroot00000000000000#define INTRA_16x16_IP_GEN5 0 #define INTRA_16x16_VERTICAL_IP_GEN5 14 #define INTRA_16x16_HORIZONTAL_IP_GEN5 32 #define INTRA_16x16_DC_IP_GEN5 52 #define INTRA_16x16_PLANE_IP_GEN5 98 #define End_intra_Pred_16x16_Y_IP_GEN5 166 #define End_add_Error_16x16_Y_IP_GEN5 204 #define load_Intra_Ref_Y_IP_GEN5 220 #define decode_Chroma_Intra_IP_GEN5 238 #define INTRA_CHROMA_DC_IP_GEN5 260 #define INTRA_CHROMA_HORIZONTAL_IP_GEN5 320 #define INTRA_CHROMA_VERTICAL_IP_GEN5 332 #define INTRA_Chroma_PLANE_IP_GEN5 342 #define End_of_intra_Pred_Chroma_IP_GEN5 392 #define save_16x16_Y_IP_GEN5 436 #define INTRA_8x8_IP_GEN5 464 #define INTRA_8x8_BLK2_IP_GEN5 568 #define intra_Pred_8x8_Y_IP_GEN5 640 #define INTRA_8X8_VERTICAL_IP_GEN5 672 #define INTRA_8X8_HORIZONTAL_IP_GEN5 682 #define INTRA_8X8_DC_IP_GEN5 692 #define INTRA_8X8_DIAG_DOWN_LEFT_IP_GEN5 724 #define INTRA_8X8_DIAG_DOWN_RIGHT_IP_GEN5 744 #define INTRA_8X8_VERT_RIGHT_IP_GEN5 772 #define INTRA_8X8_HOR_DOWN_IP_GEN5 808 #define INTRA_8X8_VERT_LEFT_IP_GEN5 842 #define INTRA_8X8_HOR_UP_IP_GEN5 862 #define save_8x8_Y_IP_GEN5 886 #define INTRA_4x4_IP_GEN5 928 #define intra_Pred_4x4_Y_4_IP_GEN5 1062 #define ADD_ERROR_SB0_IP_GEN5 1074 #define ADD_ERROR_SB1_IP_GEN5 1088 #define ADD_ERROR_SB2_IP_GEN5 1108 #define ADD_ERROR_SB3_IP_GEN5 1124 #define intra_Pred_4x4_Y_IP_GEN5 1130 #define INTRA_4X4_VERTICAL_IP_GEN5 1130 #define INTRA_4X4_HORIZONTAL_IP_GEN5 1134 #define INTRA_4X4_DC_IP_GEN5 1138 #define INTRA_4X4_DIAG_DOWN_LEFT_IP_GEN5 1160 #define INTRA_4X4_DIAG_DOWN_RIGHT_IP_GEN5 1174 #define INTRA_4X4_VERT_RIGHT_IP_GEN5 1192 #define INTRA_4X4_HOR_DOWN_IP_GEN5 1218 #define INTRA_4X4_VERT_LEFT_IP_GEN5 1246 #define INTRA_4X4_HOR_UP_IP_GEN5 1260 #define save_4x4_Y_IP_GEN5 1276 #define INTRA_PCM_IP_GEN5 1320 #define FRAME_MB_IP_GEN5 1384 #define INIT_MBPARA_FRM_IP_GEN5 1390 #define NOT_8x8_MODE_FRM_IP_GEN5 1426 #define CONVERT_MVS_FRM_IP_GEN5 1436 #define INIT_ADDRESS_REGS_FRM_IP_GEN5 1446 #define LOOP_SUBMB_FRM_IP_GEN5 1454 #define LOOP_DIR_FRM_IP_GEN5 1460 #define LOADREF_MVXZERO_FRM_IP_GEN5 1510 #define EXIT_LOADREF_Y_16x13_FRM_IP_GEN5 1524 #define Interpolate_Y_8x8_Func_FRM_IP_GEN5 1544 #define Interpolate_Y_8x8_Func2_FRM_IP_GEN5 1574 #define Interpolate_Y_H_8x8_FRM_IP_GEN5 1708 #define Interpolate_Y_V_8x8_FRM_IP_GEN5 1790 #define VFILTER_8x8_FRM_IP_GEN5 1812 #define Interpolate_Y_I_8x8_FRM_IP_GEN5 1860 #define Average_8x8_FRM_IP_GEN5 1880 #define Return_Interpolate_Y_8x8_FRM_IP_GEN5 1888 #define Exit_Interpolate_Y_8x8_FRM_IP_GEN5 1890 #define Interpolate_C_4x4_Func_FRM_IP_GEN5 1890 #define PROCESS4x4_FRM_IP_GEN5 1928 #define LOOP_SUBMBPT_FRM_IP_GEN5 1930 #define Interpolate_Y_H_4x4_FRM_IP_GEN5 2066 #define Interpolate_Y_V_4x4_FRM_IP_GEN5 2108 #define VFILTER_4x4_FRM_IP_GEN5 2142 #define Interpolate_Y_I_4x4_FRM_IP_GEN5 2148 #define Average_4x4_FRM_IP_GEN5 2160 #define Return_Interpolate_Y_4x4_FRM_IP_GEN5 2162 #define Exit_Interpolate_Y_4x4_FRM_IP_GEN5 2174 #define ROUND_SHIFT_C_FRM_IP_GEN5 2222 #define LOOP_DIR_CONTINUE_FRM_IP_GEN5 2230 #define Weighted_Prediction_FRM_IP_GEN5 2236 #define DefaultWeightedPred_UniPred_FRM_IP_GEN5 2244 #define DefaultWeightedPred_BiPred_FRM_IP_GEN5 2256 #define WeightedPred_FRM_IP_GEN5 2264 #define WeightedPred_Explicit_FRM_IP_GEN5 2282 #define WeightedPred_LOOP_FRM_IP_GEN5 2322 #define Return_WeightedPred_FRM_IP_GEN5 2382 #define EXIT_LOOP_FRM_IP_GEN5 2424 #define FIELD_MB_IP_GEN5 2496 #define INIT_MBPARA_FLD_IP_GEN5 2502 #define NOT_8x8_MODE_FLD_IP_GEN5 2538 #define CONVERT_MVS_FLD_IP_GEN5 2548 #define INIT_ADDRESS_REGS_FLD_IP_GEN5 2558 #define LOOP_SUBMB_FLD_IP_GEN5 2568 #define LOOP_DIR_FLD_IP_GEN5 2574 #define LOADREF_MVXZERO_FLD_IP_GEN5 2644 #define EXIT_LOADREF_Y_16x13_FLD_IP_GEN5 2658 #define Interpolate_Y_8x8_Func_FLD_IP_GEN5 2680 #define Interpolate_Y_8x8_Func2_FLD_IP_GEN5 2710 #define Interpolate_Y_H_8x8_FLD_IP_GEN5 2844 #define Interpolate_Y_V_8x8_FLD_IP_GEN5 2926 #define VFILTER_8x8_FLD_IP_GEN5 2948 #define Interpolate_Y_I_8x8_FLD_IP_GEN5 2996 #define Average_8x8_FLD_IP_GEN5 3016 #define Return_Interpolate_Y_8x8_FLD_IP_GEN5 3024 #define Exit_Interpolate_Y_8x8_FLD_IP_GEN5 3026 #define Interpolate_C_4x4_Func_FLD_IP_GEN5 3026 #define PROCESS4x4_FLD_IP_GEN5 3064 #define LOOP_SUBMBPT_FLD_IP_GEN5 3066 #define Interpolate_Y_H_4x4_FLD_IP_GEN5 3204 #define Interpolate_Y_V_4x4_FLD_IP_GEN5 3246 #define VFILTER_4x4_FLD_IP_GEN5 3280 #define Interpolate_Y_I_4x4_FLD_IP_GEN5 3286 #define Average_4x4_FLD_IP_GEN5 3298 #define Return_Interpolate_Y_4x4_FLD_IP_GEN5 3300 #define Exit_Interpolate_Y_4x4_FLD_IP_GEN5 3312 #define ROUND_SHIFT_C_FLD_IP_GEN5 3360 #define LOOP_DIR_CONTINUE_FLD_IP_GEN5 3368 #define Weighted_Prediction_FLD_IP_GEN5 3374 #define DefaultWeightedPred_UniPred_FLD_IP_GEN5 3382 #define DefaultWeightedPred_BiPred_FLD_IP_GEN5 3394 #define WeightedPred_FLD_IP_GEN5 3402 #define WeightedPred_Explicit_FLD_IP_GEN5 3420 #define WeightedPred_LOOP_FLD_IP_GEN5 3460 #define Return_WeightedPred_FLD_IP_GEN5 3520 #define EXIT_LOOP_FLD_IP_GEN5 3562 #define MBAFF_MB_IP_GEN5 3640 #define INIT_MBPARA_MBF_IP_GEN5 3646 #define NOT_8x8_MODE_MBF_IP_GEN5 3682 #define CONVERT_MVS_MBF_IP_GEN5 3692 #define INIT_ADDRESS_REGS_MBF_IP_GEN5 3702 #define LOOP_SUBMB_MBF_IP_GEN5 3716 #define LOOP_DIR_MBF_IP_GEN5 3722 #define LOADREF_MVXZERO_MBF_IP_GEN5 3796 #define EXIT_LOADREF_Y_16x13_MBF_IP_GEN5 3810 #define Interpolate_Y_8x8_Func_MBF_IP_GEN5 3832 #define Interpolate_Y_8x8_Func2_MBF_IP_GEN5 3862 #define Interpolate_Y_H_8x8_MBF_IP_GEN5 3996 #define Interpolate_Y_V_8x8_MBF_IP_GEN5 4078 #define VFILTER_8x8_MBF_IP_GEN5 4100 #define Interpolate_Y_I_8x8_MBF_IP_GEN5 4148 #define Average_8x8_MBF_IP_GEN5 4168 #define Return_Interpolate_Y_8x8_MBF_IP_GEN5 4176 #define Exit_Interpolate_Y_8x8_MBF_IP_GEN5 4178 #define Interpolate_C_4x4_Func_MBF_IP_GEN5 4178 #define PROCESS4x4_MBF_IP_GEN5 4216 #define LOOP_SUBMBPT_MBF_IP_GEN5 4218 #define Interpolate_Y_H_4x4_MBF_IP_GEN5 4356 #define Interpolate_Y_V_4x4_MBF_IP_GEN5 4398 #define VFILTER_4x4_MBF_IP_GEN5 4432 #define Interpolate_Y_I_4x4_MBF_IP_GEN5 4438 #define Average_4x4_MBF_IP_GEN5 4450 #define Return_Interpolate_Y_4x4_MBF_IP_GEN5 4452 #define Exit_Interpolate_Y_4x4_MBF_IP_GEN5 4464 #define ROUND_SHIFT_C_MBF_IP_GEN5 4512 #define LOOP_DIR_CONTINUE_MBF_IP_GEN5 4520 #define Weighted_Prediction_MBF_IP_GEN5 4526 #define DefaultWeightedPred_UniPred_MBF_IP_GEN5 4534 #define DefaultWeightedPred_BiPred_MBF_IP_GEN5 4546 #define WeightedPred_MBF_IP_GEN5 4554 #define WeightedPred_Explicit_MBF_IP_GEN5 4572 #define WeightedPred_LOOP_MBF_IP_GEN5 4612 #define Return_WeightedPred_MBF_IP_GEN5 4672 #define EXIT_LOOP_MBF_IP_GEN5 4714 #define SETHWSCOREBOARD_IP_GEN5 4792 #define SetHWScoreboard_Loop_IP_GEN5 4806 #define Parse_8_Loop_0_IP_GEN5 4852 #define Parse_8_Loop_2_IP_GEN5 4876 #define Parse_8_Loop_4_IP_GEN5 4900 #define Parse_8_Loop_6_IP_GEN5 4924 #define Parse_8_Loop_8_IP_GEN5 4948 #define Parse_8_Loop_10_IP_GEN5 4972 #define Parse_8_Loop_12_IP_GEN5 4996 #define Parse_8_Loop_14_IP_GEN5 5020 #define SetHWScoreboard_Remainder_IP_GEN5 5062 #define SetHWScoreboard_Remainder_Loop_IP_GEN5 5090 #define Output_Remainder_Intra_IP_GEN5 5116 #define SetHWScoreboard_Done_IP_GEN5 5128 #define SETHWSCOREBOARD_MBAFF_IP_GEN5 5136 #define SetHWScoreboard_MBAFF_Loop_IP_GEN5 5148 #define SET_SB_MBAFF_INTRA_0_IP_GEN5 5208 #define SET_SB_MBAFF_0_IP_GEN5 5230 #define NEXT_MB_MBAFF_0_IP_GEN5 5238 #define SET_SB_MBAFF_INTRA_2_IP_GEN5 5276 #define SET_SB_MBAFF_2_IP_GEN5 5298 #define NEXT_MB_MBAFF_2_IP_GEN5 5306 #define SET_SB_MBAFF_INTRA_4_IP_GEN5 5344 #define SET_SB_MBAFF_4_IP_GEN5 5366 #define NEXT_MB_MBAFF_4_IP_GEN5 5374 #define SET_SB_MBAFF_INTRA_6_IP_GEN5 5412 #define SET_SB_MBAFF_6_IP_GEN5 5434 #define NEXT_MB_MBAFF_6_IP_GEN5 5442 #define SET_SB_MBAFF_INTRA_8_IP_GEN5 5480 #define SET_SB_MBAFF_8_IP_GEN5 5502 #define NEXT_MB_MBAFF_8_IP_GEN5 5510 #define SET_SB_MBAFF_INTRA_10_IP_GEN5 5548 #define SET_SB_MBAFF_10_IP_GEN5 5570 #define NEXT_MB_MBAFF_10_IP_GEN5 5578 #define SET_SB_MBAFF_INTRA_12_IP_GEN5 5616 #define SET_SB_MBAFF_12_IP_GEN5 5638 #define NEXT_MB_MBAFF_12_IP_GEN5 5646 #define SET_SB_MBAFF_INTRA_14_IP_GEN5 5684 #define SET_SB_MBAFF_14_IP_GEN5 5706 #define NEXT_MB_MBAFF_14_IP_GEN5 5714 #define SetHWScoreboard_MBAFF_Remainder_IP_GEN5 5756 #define SetHWScoreboard_MBAFF_Remainder_Loop_IP_GEN5 5784 #define SET_SB_MBAFF_REM_INTRA_IP_GEN5 5822 #define SET_SB_MBAFF_REM_IP_GEN5 5846 #define Output_MBAFF_Remainder_Intra_IP_GEN5 5856 #define SetHWScoreboard_MBAFF_Done_IP_GEN5 5868 #define BSDRESET_IP_GEN5 5870 #define DCRESETDUMMY_IP_GEN5 5872 #define AVC_ILDB_ROOT_Y_ILDB_FRAME_IP_GEN5 5880 #define SLEEP_ENTRY_Y_ILDB_FRAME_IP_GEN5 5976 #define POST_SLEEP_Y_ILDB_FRAME_IP_GEN5 5980 #define NEXT_MB_Y_ILDB_FRAME_IP_GEN5 6010 #define ALL_SPAWNED_Y_ILDB_FRAME_IP_GEN5 6034 #define ALL_DONE_Y_ILDB_FRAME_IP_GEN5 6044 #define WAIT_FOR_UV_ILDB_FRAME_IP_GEN5 6044 #define AVC_ILDB_CHILD_Y_ILDB_FRAME_IP_GEN5 6056 #define WRITE_URB_Y_ILDB_FRAME_IP_GEN5 6436 #define POST_ILDB_Y_ILDB_FRAME_IP_GEN5 6444 #define READ_FOR_URB_Y_ILDB_FRAME_IP_GEN5 6458 #define FILTER_Y_IP_GEN5 6494 #define Y_ELSE3_IP_GEN5 6560 #define Y_ENDIF3_IP_GEN5 6574 #define Y_ELSE4_IP_GEN5 6604 #define Y_ENDIF4_IP_GEN5 6618 #define Y_ELSE2_IP_GEN5 6618 #define Y_ENDIF6_IP_GEN5 6684 #define Y_ENDIF7_IP_GEN5 6706 #define Y_ENDIF2_IP_GEN5 6710 #define Y_ENDIF1_IP_GEN5 6710 #define AVC_ILDB_ROOT_UV_ILDB_FRAME_IP_GEN5 6720 #define SLEEP_ENTRY_UV_ILDB_FRAME_IP_GEN5 6798 #define POST_SLEEP_UV_ILDB_FRAME_IP_GEN5 6802 #define NEXT_MB_UV_ILDB_FRAME_IP_GEN5 6834 #define ALL_SPAWNED_UV_ILDB_FRAME_IP_GEN5 6858 #define ALL_DONE_UV_ILDB_FRAME_IP_GEN5 6882 #define AVC_ILDB_CHILD_UV_ILDB_FRAME_IP_GEN5 6888 #define BYPASS_EXT_LEFT_EDGE_UV_ILDB_FRAME_IP_GEN5 7008 #define BYPASS_EXT_TOP_EDGE_UV_ILDB_FRAME_IP_GEN5 7126 #define WRITE_URB_UV_ILDB_FRAME_IP_GEN5 7194 #define POST_ILDB_UV_ILDB_FRAME_IP_GEN5 7202 #define READ_FOR_URB_UV_ILDB_FRAME_IP_GEN5 7216 #define FILTER_UV_IP_GEN5 7246 #define UV_ELSE2_IP_GEN5 7282 #define UV_ENDIF2_IP_GEN5 7314 #define UV_ENDIF1_IP_GEN5 7314 #define AVC_ILDB_ROOT_Y_ILDB_FIELD_IP_GEN5 7320 #define SLEEP_ENTRY_Y_ILDB_FIELD_IP_GEN5 7416 #define POST_SLEEP_Y_ILDB_FIELD_IP_GEN5 7420 #define NEXT_MB_Y_ILDB_FIELD_IP_GEN5 7450 #define ALL_SPAWNED_Y_ILDB_FIELD_IP_GEN5 7474 #define ALL_DONE_Y_ILDB_FIELD_IP_GEN5 7484 #define WAIT_FOR_UV_ILDB_FIELD_IP_GEN5 7484 #define AVC_ILDB_CHILD_Y_ILDB_FIELD_IP_GEN5 7496 #define WRITE_URB_Y_ILDB_FIELD_IP_GEN5 7896 #define POST_ILDB_Y_ILDB_FIELD_IP_GEN5 7904 #define READ_FOR_URB_Y_ILDB_FIELD_IP_GEN5 7918 #define ELSE_Y_4x16T_ILDB_FIELD_IP_GEN5 7934 #define ENDIF_Y_4x16T_ILDB_FIELD_IP_GEN5 7942 #define AVC_ILDB_ROOT_UV_ILDB_FIELD_IP_GEN5 7976 #define SLEEP_ENTRY_UV_ILDB_FIELD_IP_GEN5 8054 #define POST_SLEEP_UV_ILDB_FIELD_IP_GEN5 8058 #define NEXT_MB_UV_ILDB_FIELD_IP_GEN5 8090 #define ALL_SPAWNED_UV_ILDB_FIELD_IP_GEN5 8114 #define ALL_DONE_UV_ILDB_FIELD_IP_GEN5 8138 #define AVC_ILDB_CHILD_UV_ILDB_FIELD_IP_GEN5 8144 #define BYPASS_EXT_LEFT_EDGE_UV_ILDB_FIELD_IP_GEN5 8272 #define BYPASS_EXT_TOP_EDGE_UV_ILDB_FIELD_IP_GEN5 8394 #define WRITE_URB_UV_ILDB_FIELD_IP_GEN5 8470 #define POST_ILDB_UV_ILDB_FIELD_IP_GEN5 8478 #define READ_FOR_URB_UV_ILDB_FIELD_IP_GEN5 8492 #define ELSE_Y_2x8T_ILDB_FIELD_IP_GEN5 8508 #define ENDIF_Y_2x8T_ILDB_FIELD_IP_GEN5 8516 #define AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP_GEN5 8544 #define SLEEP_ENTRY_Y_ILDB_MBAFF_IP_GEN5 8642 #define POST_SLEEP_Y_ILDB_MBAFF_IP_GEN5 8646 #define NEXT_MB_Y_ILDB_MBAFF_IP_GEN5 8676 #define ALL_SPAWNED_Y_ILDB_MBAFF_IP_GEN5 8700 #define ALL_DONE_Y_ILDB_MBAFF_IP_GEN5 8710 #define WAIT_FOR_UV_ILDB_MBAFF_IP_GEN5 8710 #define AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP_GEN5 8720 #define RE_ENTRY_IP_GEN5 8742 #define ELSE_Y_16x16T_ILDB_MBAFF_IP_GEN5 8782 #define ENDIF_Y_16x16T_ILDB_MBAFF_IP_GEN5 8792 #define ELSE_Y_4x16T_IP_GEN5 8808 #define ENDIF_Y_4x16T_IP_GEN5 8818 #define BYPASS_V1_Y_IP_GEN5 8966 #define BYPASS_V2_Y_IP_GEN5 8980 #define BYPASS_V3_Y_IP_GEN5 8994 #define ELSE_Y_16x4T_IP_GEN5 9024 #define ENDIF_Y_16x4T_IP_GEN5 9034 #define NOT_DUAL_FIELD_IP_GEN5 9060 #define ELSE_Y_16x4_IP_GEN5 9060 #define ENDIF_Y_16x4_IP_GEN5 9072 #define DUAL_FIELD_Y_IP_GEN5 9168 #define H0_Y_DONE_IP_GEN5 9236 #define ELSE_Y_16x16_IP_GEN5 9310 #define ENDIF_Y_16x16_IP_GEN5 9320 #define ELSE_Y_16x4_SAVE_IP_GEN5 9342 #define ENDIF_Y_16x4_SAVE_IP_GEN5 9354 #define SKIP_ILDB_IP_GEN5 9356 #define POST_ILDB_IP_GEN5 9364 #define FILTER_Y_MBAFF_IP_GEN5 9378 #define MBAFF_Y_ELSE3_IP_GEN5 9444 #define MBAFF_Y_ENDIF3_IP_GEN5 9458 #define MBAFF_Y_ELSE4_IP_GEN5 9488 #define MBAFF_Y_ENDIF4_IP_GEN5 9502 #define MBAFF_Y_ELSE2_IP_GEN5 9502 #define MBAFF_Y_ENDIF6_IP_GEN5 9566 #define MBAFF_Y_ENDIF7_IP_GEN5 9588 #define MBAFF_Y_ENDIF2_IP_GEN5 9592 #define MBAFF_Y_ENDIF1_IP_GEN5 9592 #define AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP_GEN5 9600 #define SLEEP_ENTRY_UV_ILDB_MBAFF_IP_GEN5 9678 #define POST_SLEEP_UV_ILDB_MBAFF_IP_GEN5 9682 #define NEXT_MB_UV_ILDB_MBAFF_IP_GEN5 9714 #define ALL_SPAWNED_UV_ILDB_MBAFF_IP_GEN5 9738 #define ALL_DONE_UV_ILDB_MBAFF_IP_GEN5 9762 #define AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP_GEN5 9768 #define RE_ENTRY_UV_ILDB_MBAFF_IP_GEN5 9794 #define ELSE_UV_8X8T_ILDB_MBAFF_IP_GEN5 9836 #define ENDIF_UV_8X8T_ILDB_MBAFF_IP_GEN5 9846 #define ELSE_Y_2x8T_ILDB_MBAFF_IP_GEN5 9864 #define ENDIF_Y_2x8T_ILDB_MBAFF_IP_GEN5 9874 #define V0_U_NEXT1_IP_GEN5 9934 #define V0_U_NEXT2_IP_GEN5 9954 #define V0_U_NEXT3_IP_GEN5 9964 #define BYPASS_V0_UV_IP_GEN5 10018 #define ELSE_UV_8X2T_IP_GEN5 10082 #define ENDIF_UV_8X2T_IP_GEN5 10092 #define NOT_DUAL_FIELD_UV_IP_GEN5 10120 #define ELSE_UV_8X2_IP_GEN5 10120 #define ENDIF_UV_8X2_IP_GEN5 10132 #define DUAL_FIELD_UV_IP_GEN5 10208 #define H0_UV_DONE_IP_GEN5 10300 #define ELSE_UV_8X8_IP_GEN5 10360 #define ENDIF_UV_8X8_IP_GEN5 10370 #define ELSE_UV_8X2_SAVE_IP_GEN5 10394 #define ENDIF_UV_8X2_SAVE_IP_GEN5 10406 #define SKIP_ILDB_UV_ILDB_MBAFF_IP_GEN5 10408 #define POST_ILDB_UV_ILDB_MBAFF_IP_GEN5 10416 #define FILTER_UV_MBAFF_IP_GEN5 10430 #define MBAFF_UV_ELSE2_IP_GEN5 10466 #define MBAFF_UV_ENDIF2_IP_GEN5 10496 #define MBAFF_UV_ENDIF1_IP_GEN5 10496 #define AllAVC_END_IP_GEN5 10500 intel-driver-1.3.0/src/shaders/h264/mc/header.inc000066400000000000000000000256271231401140700213510ustar00rootroot00000000000000/* * Common header file for all AVC MC kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__HEADER__) // Make sure this file is only included once #define __HEADER__ // Module name: header.inc // // Common header file for all AVC MC kernels // #ifndef COMBINED_KERNEL #ifdef DEV_CTG #define SW_SCOREBOARD // SW Scoreboard should be enabled for CTG and earlier #undef HW_SCOREBOARD // HW Scoreboard should be disabled for CTG and earlier #else #define HW_SCOREBOARD // HW Scoreboard should be enabled for ILK and beyond #undef SW_SCOREBOARD // SW Scoreboard should be disabled for ILK and beyond #endif // DEV_CTG #endif // COMBINED_KERNEL //#define MONO // Build Monochrome kernels // Surface state definition // #define DESTY 0 #define DESTUV 1 #define REFYFM0 2 #define REFYFM1 3 #define REFYFM2 4 #define REFYFM3 5 #define REFYFM4 6 #define REFYFM5 7 #define REFYFM6 8 #define REFYFM7 9 #define REFYFM8 10 #define REFYFM9 11 #define REFYFM10 12 #define REFYFM11 13 #define REFYFM12 14 #define REFYFM13 15 #define REFYFM14 16 #define REFYFM15 17 #define REFUVFM0 18 #define REFUVFM1 19 #define REFUVFM2 20 #define REFUVFM3 21 #define REFUVFM4 22 #define REFUVFM5 23 #define REFUVFM6 24 #define REFUVFM7 25 #define REFUVFM8 26 #define REFUVFM9 27 #define REFUVFM10 28 #define REFUVFM11 29 #define REFUVFM12 30 #define REFUVFM13 31 #define REFUVFM14 32 #define REFUVFM15 33 .default_execution_size (16) .default_register_type :ub // ----------- Common constant definitions ------------ // // Bit position constants // #define BIT0 0x01 #define BIT1 0x02 #define BIT2 0x04 #define BIT3 0x08 #define BIT4 0x10 #define BIT5 0x20 #define BIT6 0x40 #define BIT7 0x80 #define BIT8 0x0100 #define BIT9 0x0200 #define BIT10 0x0400 #define BIT11 0x0800 #define BIT12 0x1000 #define BIT13 0x2000 #define BIT14 0x4000 #define BIT15 0x8000 #define BIT16 0x00010000 #define BIT17 0x00020000 #define BIT18 0x00040000 #define BIT19 0x00080000 #define BIT20 0x00100000 #define BIT21 0x00200000 #define BIT22 0x00400000 #define BIT23 0x00800000 #define BIT24 0x01000000 #define BIT25 0x02000000 #define BIT26 0x04000000 #define BIT27 0x08000000 #define BIT28 0x10000000 #define BIT29 0x20000000 #define BIT30 0x40000000 #define BIT31 0x80000000 #define GRFWIB 32 // GRF register width in byte #define GRFWIW 16 // GRF register width in word #define GRFWID 8 // GRF register width in dword #define INST_SIZE 16 // Instruction size = 128b = 16 Bytes #define REGION(Width,HStride) #define NULLREG null<1>:ud #define NULLREGW null<1>:w #define TOP_FIELD 0 #define BOTTOM_FIELD 1 // M2 - M9 for date writing message payload .declare MSGPAYLOAD Base=m2 ElementSize=1 SrcRegion=REGION(16,1) Type=ub .declare MSGPAYLOADB Base=m2 ElementSize=1 SrcRegion=REGION(16,1) Type=ub .declare MSGPAYLOADW Base=m2 ElementSize=2 SrcRegion=REGION(16,1) Type=uw .declare MSGPAYLOADD Base=m2 ElementSize=4 SrcRegion=REGION(8,1) Type=ud // ----------- Common Message Descriptor ------------ // #ifdef DEV_ILK #define MSG_GW 0x03 // Message Gateway Extended Message Descriptor, #define DAPREAD 0x04 // Data Port Read Extended Message Descriptor, #define DAPWRITE 0x05 // Data Port Write Extended Message Descriptor, #define TS 0x07 // Thread Spawner Extended Message Descriptor #define TS_EOT 0x27 // End of Thread Extended Message Descriptor #define EOTMSGDSC 0x02000010 // End of Thread Message Descriptor, don't deference URB handle // Data Port Message Descriptor #define DWBRMSGDSC_RC 0x02086000 // DWORD Block Read Message Descriptor, reading from render cache = 6. #define DWBRMSGDSC_RC_TF 0x02086600 // DWORD Block Read Message Descriptor, reading from render cache = 6. #define DWBRMSGDSC_RC_BF 0x02086700 // DWORD Block Read Message Descriptor, reading from render cache = 6. #define DWBRMSGDSC_SC 0x0208A000 // DWORD Block Read Message Descriptor, reading from sampler cache = A. #define DWBRMSGDSC_SC_TF 0x0208E600 // DWORD Block Read Message Descriptor, reading top field from field mode sampler cache. #define DWBRMSGDSC_SC_BF 0x0208E700 // DWORD Block Read Message Descriptor, reading bottom field from field mode sampler cache. #define DWBWMSGDSC 0x02082000 // DWORD Block Write Message Descriptor #define DWBWMSGDSC_WC 0x0218A000 // DWORD Block Write Message Descriptor + write commit // Enable Write Commit writeback mesage #define ENWRCOM 0x00108000 // Enable "write commit" and set response length = 1 // Thread Spawner Message Descriptor #define TSMSGDSC 0x02000011 // Message Gateway Message Descriptors #define OGWMSGDSC 0x02000000 // OpenGateway Message Descriptor #define CGWMSGDSC 0x02000001 // CloseGateway Message Descriptor #define FWDMSGDSC 0x02000002 // ForwardMsg Message Descriptor #define NOTIFYMSG 0x00008000 // Send notification with ForwardMsg message #define RESP_LEN(len) 0x100000*len #define MSG_LEN(len) 0x2000000*len #else // Pre DEV_ILK #define MSG_GW #define DAPREAD #define DAPWRITE #define TS #define TS_EOT #define EOTMSGDSC 0x87100010 // End of Thread Message Descriptor, don't deference URB handle // Data Port Message Descriptor #define DWBRMSGDSC_RC 0x04106000 // DWORD Block Read Message Descriptor, reading from render cache = 6. #define DWBRMSGDSC_RC_TF 0x04106600 // DWORD Block Read Message Descriptor, reading from render cache = 6. #define DWBRMSGDSC_RC_BF 0x04106700 // DWORD Block Read Message Descriptor, reading from render cache = 6. #define DWBRMSGDSC_SC 0x0410A000 // DWORD Block Read Message Descriptor, reading from sampler cache = A. #define DWBRMSGDSC_SC_TF 0x0410A600 // DWORD Block Read Message Descriptor, reading top field from field mode sampler cache. #define DWBRMSGDSC_SC_BF 0x0410A700 // DWORD Block Read Message Descriptor, reading bottom field from field mode sampler cache. #define DWBWMSGDSC 0x05102000 // DWORD Block Write Message Descriptor #define DWBWMSGDSC_WC 0x0511A000 // DWORD Block Write Message Descriptor + write commit // Enable Write Commit writeback mesage #define ENWRCOM 0x00018000 // Enable "write commit" and set response length = 1 // Thread Spawner Message Descriptor #define TSMSGDSC 0x07100011 // Message Gateway Message Descriptors #define OGWMSGDSC 0x03100000 // OpenGateway Message Descriptor #define CGWMSGDSC 0x03100001 // CloseGateway Message Descriptor #define FWDMSGDSC 0x03100002 // ForwardMsg Message Descriptor #define NOTIFYMSG 0x00008000 // Send notification with ForwardMsg message #define ACKREQMSG 0x00014000 // Acknowledgement required so response length should be 1 #define RESP_LEN(len) 0x10000*len #define MSG_LEN(len) 0x100000*len #endif // DEV_ILK // Enable frame/field selection in message descriptor #define ENMSGDSCFM 0x400 // Enable MSGDSC to select frame surface #define ENMSGDSCTF 0x600 // Enable MSGDSC to select top field surface #define ENMSGDSCBF 0x700 // Enable MSGDSC to select bottom field surface // ----------- Message related register ------------ // #define MSGHDR m1 // Message Payload Header #define MSGHDRY m1 // Message Payload Header register for Y data #define MSGHDRY0 m1 // Message Payload Header register for Y data #define MSGHDRY1 m2 // Message Payload Header register for Y data #define MSGHDRY2 m3 // Message Payload Header register for Y data #define MSGHDRY3 m4 // Message Payload Header register for Y data #define MSGHDRUV m5 // Message Payload Header register for U/V data #define MSGSRC r62 // Message source register, should never be used for other purposes #define MSGDSC a0.0:ud // Message Descriptor register (type DWORD) #define MH_ORI MSGSRC.0 // DWORD block R/W message header block offset #define MH_ORIX MSGSRC.0 // DWORD block R/W message header X offset #define MH_ORIY MSGSRC.1 // DWORD block R/W message header Y offset #define MH_SIZE MSGSRC.2 // DWORD block R/W message header block width & height // Data necessary for kernel operations // // Address registers used as pointers // // Note: Please keep the register order as is since they are used in compressed instructions // #define PPREDBUF_Y a0.4 // Pointer to predicted Y picture #define PPREDBUF_Y1 a0.5 // Pointer to predicted Y picture for extended instruction #define PPREDBUF_UV a0.4 // Pointer to predicted U/V picture #define PPREDBUF_UV1 a0.5 // Pointer to predicted U/V picture for extended instruction #define PDECBUF a0.4 // Pointer to decoded picture data #define PDECBUF_UD a0.2 // Pointer to decoded picture data in DWORD unit // ----------- R63 is reserved for global variables ------------ // // Note: Don't program it with values other than what are defined here. #define G_REG r63 #define RETURN_REG G_REG.0 // Return pointer for all sub-routine calls (type DWORD) #define RETURN_REG1 G_REG.1 // Return pointer for second-level calls #define I_ORIX G_REG.13 // :uw, H. origin of the macroblock in pixel unit, don't overwrite in-line data #define I_ORIY G_REG.14 // :uw, V. origin of the macroblock in pixel unit, don't overwrite in-line data // Macros // // Note: For macros that require multiple line expansion, insert "\n" at the end of each line. // #define GRF(reg) r##reg #ifdef DEV_ILK #define END_THREAD send (8) NULLREG MSGHDR r0:ud TS_EOT EOTMSGDSC #else #define END_THREAD send (8) NULLREG MSGHDR r0:ud EOTMSGDSC #endif // DEV_ILK #define CALL(subFunc, skipInst) add (1) RETURN_REG<1>:ud ip:ud (1+skipInst)*INST_SIZE \n\ jmpi (1) subFunc #define CALL_1(subFunc, skipInst) add (1) RETURN_REG1<1>:ud ip:ud (1+skipInst)*INST_SIZE \n\ jmpi (1) subFunc #define RETURN mov (1) ip:ud RETURN_REG<0;1,0>:ud // Return to calling module #define RETURN_1 mov (1) ip:ud RETURN_REG1<0;1,0>:ud // Return to second-level calling module // To support iterative calling #ifdef SW_SCOREBOARD #ifdef DEV_CTG_A #define LEADING_THREAD 1 // For CTG A, no SRT is needed. Only PRT is necessary #else #define LEADING_THREAD 0 // For CTG B0 and beyond, PRT doesn't take into debug count #define DOUBLE_SB // Scoreboard size needs to be doubled #endif #ifdef DOUBLE_SB // Scoreboard size needs to be doubled #define SB_MASK 0x1ff // Scoreboard wrap-around mask (for 512 entries) #else #define SB_MASK 0xff // Scoreboard wrap-around mask (for 256 entries) #endif // defined(DOUBLE_SB) // Scoreboard related definitions #define TEMPX r50 #define TEMPY r51 #define DELTA r52 #define M05_STORE r0.13 // :uw, reuse r0.6:ud upper-word to store M0.5 header information for scoreboard #endif // SW_SCOREBOARD // End of header.inc #endif // !defined(__HEADER__) intel-driver-1.3.0/src/shaders/h264/mc/initialize_MBPara.asm000066400000000000000000000107361231401140700234460ustar00rootroot00000000000000/* * Initialize parameters * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: Initialize_MBPara.asm // //#if !defined(__INITIALIZE_MBPARA__) // Make sure this is only included once //#define __INITIALIZE_MBPARA__ // WA for weighted prediction - 2007/09/06 // shlee // mov (1) guwW128(0)<1> guwR1(0)<0;1,0> // Copy the unique number indicating weight/offset=(128,0) // MB Type Category // 1 B_L0_16x16 // 2 B_L1_16x16 // 3 B_Bi_16x16 // 4 B_L0_L0_16x8 // 5 B_L0_L0_8x16 // 6 B_L1_L1_16x8 // 7 B_L1_L1_8x16 // 8 B_L0_L1_16x8 // 9 B_L0_L1_8x16 // 10 B_L1_L0_16x8 // 11 B_L1_L0_8x16 // 12 B_L0_Bi_16x8 // 13 B_L0_Bi_8x16 // 14 B_L1_Bi_16x8 // 15 B_L1_Bi_8x16 // 16 B_Bi_L0_16x8 // 17 B_Bi_L0_8x16 // 18 B_Bi_L1_16x8 // 19 B_Bi_L1_8x16 // 20 B_Bi_Bi_16x8 // 21 B_Bi_Bi_8x16 // 22 B_8x8 // TODO: // Initialize interpolation area to eliminate uninitialized registers making the results of mac instructions XX. // This issue was reported by Sharath on 5/25/2006, and why multiplication by zero still yields XX has not been understood yet. #if 0 mov (16) gudINTPY0(0)<1> 0:ud {Compr} mov (16) gudINTPY0(2)<1> 0:ud {Compr} mov (16) gudINTPY1(0)<1> 0:ud {Compr} mov (16) gudINTPY1(2)<1> 0:ud {Compr} mov (16) gudINTPC0(0)<1> 0:ud {Compr} mov (16) gudINTPC1(0)<1> 0:ud {Compr} #endif mov (1) gMVSTEP:w 0:w // Address increament for MV read cmp.e.f0.0 (1) null:w gwMBTYPE<0;1,0> 22:w (-f0.0) jmpi INTERLABEL(NOT_8x8_MODE) //--- 8x8 mode // Starting address of error data blocks cmp.e.f0.1 (2) null<1>:w gSUBMB_SHAPE<0;1,0>:ub 0:w (f0.1) jmpi INTERLABEL(CONVERT_MVS) // Note: MVs and Weights/Offsets are already expanded by HW or driver // MV conversion - Convert each MV to absolute coord. (= MV + MB org. + block offset) shl (16) gwTEMP(0)<1> gX<0;2,1>:w 2:w // Convert MB origin to 1/4-pel unit mov (1) gMVSTEP:w 24:w // Address increament for MV read add (2) gwTEMP(0,4)<2> gwTEMP(0,4)<4;2,2> 16:w add (2) gwTEMP(0,9)<2> gwTEMP(0,9)<4;2,2> 16:w add (4) gwTEMP(0,12)<1> gwTEMP(0,12)<4;4,1> 16:w add (16) gMV<1>:w gMV<16;16,1>:w gwTEMP(0)<16;16,1> add (8) gwTEMP(0)<2> gwTEMP(0)<16;8,2> 32:w add (16) gwMV(1,0)<1> gwMV(1,0)<16;16,1> gwTEMP(0)<16;16,1> add (8) gwTEMP(0,1)<2> gwTEMP(0,1)<16;8,2> 32:w add (16) gwMV(3,0)<1> gwMV(3,0)<16;16,1> gwTEMP(0)<16;16,1> add (8) gwTEMP(0)<2> gwTEMP(0)<16;8,2> -32:w add (16) gwMV(2,0)<1> gwMV(2,0)<16;16,1> gwTEMP(0)<16;16,1> jmpi INTERLABEL(INIT_ADDRESS_REGS) INTERLABEL(NOT_8x8_MODE): //--- !8x8 mode (16x16, 16x8, 8x16) // MVs and Weights/Offsets are expanded cmp.le.f0.1 (8) null<1>:w gwMBTYPE<0;1,0> 3:w // Check 16x16 mov (1) gSUBMB_SHAPE:ub 0:uw // subMB shape (f0.1) mov (8) gMV<1>:d gMV<0;2,1>:d (f0.1) mov (8) gdWGT(1,0)<1> gWGT<0;4,1>:d (f0.1) mov (4) gdWGT(0,4)<1> gWGT<4;4,1>:d INTERLABEL(CONVERT_MVS): // MV conversion - Convert each MV to absolute coord. (= MV + MB org. + block offset) shl (2) gwTEMP(0)<1> gX<2;2,1>:w 2:w // Convert MB origin to 1/4-pel unit add (16) gMV<1>:w gMV<16;16,1>:w gwTEMP(0)<0;2,1> add (2) gwMV(0,4)<2> gwMV(0,4)<4;2,2> 32:w //{NoDDClr} add (2) gwMV(0,9)<2> gwMV(0,9)<4;2,2> 32:w //{NoDDChk,NoDDClr} add (4) gwMV(0,12)<1> gwMV(0,12)<4;4,1> 32:w //{NoDDChk} INTERLABEL(INIT_ADDRESS_REGS): // Initialize the address registers mov (2) pERRORYC:ud nOFFSET_ERROR:ud {NoDDClr} // Address of Y and C error blocks mov (1) pRECON_MV:ud nOFFSET_RECON_MV:ud {NoDDChk,NoDDClr} // Address of recon area and motion vectors mov (1) pWGT_BIDX:ud nOFFSET_WGT_BIDX:ud {NoDDChk} // Address of weights/offsets and binding tbl idx // Read the parity of the current field (gPARITY - 0:top, 1:bottom, 3:frame) // and set message descriptor for frame/field write #if defined(MBAFF) and.nz.f0.0 (1) null:uw gFIELDMBFLAG:ub nFIELDMB_MASK:uw (f0.0) and (1) gPARITY:uw gMBPARITY:ub nMBPARITY_MASK:uw (-f0.0) mov (1) gPARITY:uw 3:uw #elif defined(FIELD) and (1) gPARITY:uw gMBPARITY:ub nMBPARITY_MASK:uw #endif //#endif // !defined(__INITIALIZE_MBPARA__) intel-driver-1.3.0/src/shaders/h264/mc/inter_Header.inc000066400000000000000000000325321231401140700225030ustar00rootroot00000000000000/* * Header file for all AVC INTER prediction kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__INTER_HEADER__) // Make sure this file is only included once #define __INTER_HEADER__ // Module name: inter_header.inc // // Header file for all AVC INTER prediction kernels // #define INTER_KERNEL //------------------------------------------------------------------------------------------- // TODO: The followings will be merged with the above definitions later //------------------------------------------------------------------------------------------- //------------ Input parameters & bit masks // SW WA for weighted prediction - 2007/09/06 //.declare guwR1 Base=r1 ElementSize=2 Type=uw //.declare guwW128 Base=r63.13 ElementSize=2 Type=uw #ifdef DEV_ILK // #define SW_W_128 // Enable SW WA for special Weight=128 case. Can be commented to disable it #else // Pre DEV_ILK #define SW_W_128 // Enable SW WA for special Weight=128 case. #endif // DEV_ILK #ifdef SW_W_128 .declare gudW128 Base=r1.0 ElementSize=4 Type=ud #else #endif // SW_W_128 #define gORIX r3.4 // :ub, X origin #define gORIY r3.5 // :ub, Y origin #define gCBP r3.9 // :ub, CBP (0, 0, Y0, Y1, Y2, Y3, Cb, Cr) #define nCBPY_MASK 0x3c #define nCBPU_MASK 0x2 #define nCBPV_MASK 0x1 #define gFIELDFLAGS r3.1 // :uw - To compute message descriptor for write #define gMBTYPE r3.1 // :ub, MB type #define nMBTYPE_MASK 0x1f #define gFIELDMBFLAG r3.1 // :ub, Field MB flag #define nFIELDMB_MASK 0x40 #define gMBPARITY r3.3 // :ub, Bottom field flag #define nMBPARITY_MASK 0x01 #define gWPREDFLAG r3.0 // :ub, Weighted pred flag #define nWBIDIR_MASK 0xc0 #define gSUBMB_SHAPE r3.12 // :ub, Sub-MB shape #define gSUBMB_MODE r3.13 // :ub, Sub-MB prediction mode .declare guwSUBMB_SHAPE_MODE Base=r3.6 ElementSize=2 Type=uw #define gYWDENOM r3.14 // :ub, Luma log2 weight denom #define gCWDENOM r3.15 // :ub, Chroma log2 weight denom #define gADDR r3.24 // :ub, Register addresses of error data / MV .declare gubBIDX Base=r3.16 ElementSize=1 Type=ub #define gWGT r8 // Weights/offsets .declare gdWGT Base=r8 ElementSize=4 Type=d .declare gwWGT Base=r8 ElementSize=2 Type=w #define gMV r4 // MVs .declare gwMV Base=r4 ElementSize=2 Type=w .declare gdMV Base=r4 ElementSize=4 Type=d .declare gwERRORY Base=r10 ElementSize=2 Type=w // 16 GRFs .declare gubERRORY Base=r10 ElementSize=1 Type=ub .declare gwERRORC Base=r26 ElementSize=2 Type=w // 8 GRFs .declare gubERRORC Base=r26 ElementSize=2 Type=ub //------------ Address registers #define pMSGDSC a0.0 // ud: Must be the leading dword of the address register #define pREF a0.0 #define pBIDX a0.2 #define pWGT a0.3 #define pERRORYC a0.2 // :ud #define pERRORY a0.4 #define pERRORC a0.5 #define pMV a0.6 #define pWGT_BIDX a0.1 // :ud, WGT & BIDX #define pRECON_MV a0.3 // :ud, RECON & MV #define pREF0 a0.0 // :uw #define pREF0D a0.0 // :ud #define pREF1 a0.1 #define pREF2 a0.2 #define pREF2D a0.1 // :ud #define pREF3 a0.3 #define pREF4 a0.4 #define pREF4D a0.2 // :ud #define pREF5 a0.5 #define pREF6 a0.6 #define pREF6D a0.3 // :ud #define pREF7 a0.7 #define pRES a0.6 #define pRESD a0.3 // :ud #define pRESULT a0.7 #define p0 a0.0 #define p1 a0.1 //------------ Constants for static/inline/indirect #define nOFFSET_BIDX 112 // = 32*3+4*4 #define nOFFSET_WGT 256 // = 32*8 #define nOFFSET_WGT_BIDX 0x01000070 // = (256<<16)+112 #define nOFFSET_ERROR 0x03400140 // = (320+128*4)<<16+320=0x03400140 #define nOFFSET_ERRORY 0x0140 #define nOFFSET_ERRORC 0x0340 #define nOFFSET_MV 128 // = 32*4 #define nOFFSET_RECON_MV 0x04400080 // = (1088<<16)+128 // TODO: OFFSET_RECON is obsolete //------------ Constants for kernel internal variables #define nOFFSET_INTPY0 0x0640 // = 32*50 #define nOFFSET_INTPY1 0x0780 // = 32*60 #define nOFFSET_INTPC0 0x06c0 // = 32*54 #define nOFFSET_INTPC1 0x0480 // = 32*36 #define nOFFSET_INTP0 0x06c00640 #define nOFFSET_INTP1 0x04800780 #define nOFFSET_INTERIM 0x0480 // = 32*36 #define nOFFSET_INTERIM2 0x04A00480 // = ((32*37)<<16)|(32*36) #define nOFFSET_INTERIM3 0x04A00480 // = ((32*36+32)<<16)|(32*36) #define nOFFSET_INTERIM4 0x04A00490 // = ((32*37)<<16)|(32*36+16) #define nOFFSET_INTERIM4x4 0x04C0 // = 32*38 #define nOFFSET_INTERIM4x4_4 0x04E004D0 // = ((32*38+32)<<16)|(32*38+16) #define nOFFSET_INTERIM4x4_5 0x04D004C0 // = ((32*38+16)<<16)|(32*38) #define nOFFSET_INTERIM4x4_6 0x04E004C0 // = ((32*38+32)<<16)|(32*38) #define nOFFSET_INTERIM4x4_7 0x04D004C8 // = ((32*38+16)<<16)|(32*38+8) #define nOFFSET_INTERIM4x4_8 0x04E004D8 // = ((32*38+32)<<16)|(32*38+24) #define nOFFSET_INTERIM4x4_9 0x04F004E8 // = ((32*38+48)<<16)|(32*38+40) #define nOFFSET_RES 0x540 // = 32*42 #define nOFFSET_REF 0x560 // = 32*43 #define nOFFSET_REFC 0x700 // = 32*56 // Binding table index #define nBDIX_DESTY 0 #define nBDIX_DESTC 1 #define nBI_LC_DIFF 0x10 // Binding table index diff between luma and chroma #define nGRFWIB 32 #define nGRFHWIB 16 //------------ Regions .declare gudREF Base=r43 ElementSize=4 SrcRegion=<16;16,1> Type=ud .declare gubREF Base=r43 ElementSize=1 Type=ub .declare gudREFC Base=r56 ElementSize=4 SrcRegion=<16;16,1> Type=ud // 16x16 handling .declare gudREF21x21 Base=r58 ElementSize=4 SrcRegion=<16;16,1> Type=ud .declare gudREF18x10 Base=r66 ElementSize=4 SrcRegion=<16;16,1> Type=ud .declare gubREF18x10 Base=r66 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare gudREF16x16 Base=r38 ElementSize=4 Type=ud // 8 GRFs .declare gubREF16x16 Base=r38 ElementSize=1 Type=ub .declare gudREFC16x8 Base=r46 ElementSize=4 Type=ud // 4 GRFs .declare gubREFC16x8 Base=r46 ElementSize=1 Type=ub // TODO .declare gubAVG Base=r56 ElementSize=1 Type=ub .declare gubREFY_BWD Base=r64 ElementSize=1 Type=ub .declare gubREFC_BWD Base=r72 ElementSize=1 Type=ub .declare guwINTPY0 Base=r50 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare gudINTPY0 Base=r50 ElementSize=4 Type=ud .declare gubINTPY0 Base=r50 ElementSize=1 SrcRegion=<32;16,2> Type=ub .declare guwINTPY1 Base=r60 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare gudINTPY1 Base=r60 ElementSize=4 Type=ud .declare gubINTPY1 Base=r60 ElementSize=1 SrcRegion=<32;16,2> Type=ub .declare guwYPRED Base=r50 ElementSize=2 SrcRegion=<8;8,1> Type=uw .declare gubYPRED Base=r50 ElementSize=1 SrcRegion=<32;16,2> Type=ub .declare guwINTPC0 Base=r54 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare gwINTPC0 Base=r54 ElementSize=2 SrcRegion=<16;16,1> Type=w .declare gudINTPC0 Base=r54 ElementSize=4 Type=ud .declare gubINTPC0 Base=r54 ElementSize=1 SrcRegion=<32;16,2> Type=ub .declare guwINTPC1 Base=r36 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare gudINTPC1 Base=r36 ElementSize=4 Type=ud .declare gubINTPC1 Base=r36 ElementSize=1 SrcRegion=<32;16,2> Type=ub .declare guwCPRED Base=r54 ElementSize=2 SrcRegion=<16;8,2> Type=uw .declare gubCPRED Base=r54 ElementSize=1 SrcRegion=<32;8,4> Type=ub #define gINTERIM r36 .declare gubINTERIM_BUF Base=r36 ElementSize=1 SrcRegion=<32;16,2> Type=ub #define gINTERIM4x4 r38 .declare gubINTERIM4x4_BUF Base=r38 ElementSize=1 SrcRegion=<32;16,2> Type=ub .declare gwINTERIM4x4_BUF Base=r38 ElementSize=2 Type=w .declare gubINTERIM_BUF2 Base=r42 ElementSize=1 SrcRegion=<8;4,2> Type=ub .declare gwINTERIM_BUF2 Base=r42 ElementSize=2 SrcRegion=<16;16,1> Type=w .declare guwINTERIM_BUF2 Base=r42 ElementSize=2 Type=uw .declare gwINTERIM_BUF3 Base=r38 ElementSize=2 SrcRegion=<16;16,1> Type=w // 2 GRFs .declare gubINTERIM_BUF3 Base=r38 ElementSize=1 Type=ub .declare gwTEMP Base=r42 ElementSize=2 SrcRegion=<16;16,1> Type=w //------------ General registers #define gX r3.2 // w #define gY r3.3 // w #define gMSGDSC_R r3.6 // ud #define gMSGDSC_W r3.7 // ud #ifdef SW_W_128 .declare gwMBTYPE Base=r8.6 ElementSize=2 Type=w // Shared with gLOOP_SUBMB // TODO #define gLOOP_SUBMB r8.6 #define gLOOP_SUBMBPT r8.7 #define gLOOP_DIR r9.6 #define gLOOPCNT r9.7 // Loop counter for submodules #else .declare gwMBTYPE Base=r1.0 ElementSize=2 Type=w // Shared with gLOOP_SUBMB // TODO #define gLOOP_SUBMB r1.0 #define gLOOP_SUBMBPT r1.1 #define gLOOP_DIR r8.7 #define gLOOPCNT r9.7 // Loop counter for submodules #endif // SW_W_128 #define gW0 r34.6 // Temporary WORD #define gW1 r34.7 // Temporary WORD #define gW2 r34.8 // Temporary WORD #define gW3 r34.9 // Temporary WORD #define gD0 r34.3 // Temporary DWORD #define gW4 r34.15 // #define gMVX_INT r34.0 // :w #define gMVY_INT r34.1 // :w #define gMVX_FRAC r34.2 // :w #define gMVY_FRAC r34.3 // :w #define gMVX_FRACC r34.4 // :w #define gMVY_FRACC r34.5 // :w #define gpINTPY r34.10 #define gpINTPC r34.11 #define gpINTP r34.5 // DW #define gPREDFLAG r34.12 #define gBIDX r34.13 #define gREFPARITY r34.14 #define gCHRMVADJ r1.14 #define gPARITY r1.15 #define gCBP_MASK r1.1 #define gMVSTEP r1.13 #define gpADDR r1.2 // :uw (8 words) #define gSHAPETEMP r8.15 // :uw #define gCOEFA r42.0 #define gCOEFB r42.1 #define gCOEFC r42.2 #define gCOEFD r42.3 // Weighted prediction #define gPREDFLAG0 r46.0 #define gPREDFLAG1 r46.2 #define gWEIGHTFLAG r43.2 #define gBIPRED r43.3 #define gYADD r43.4 #define gCADD r43.5 #define gYSHIFT r43.6 #define gCSHIFT r43.7 #define gOFFSET r44.0 #define gUOFFSET r44.1 #define gVOFFSET r44.2 #define gWT0 r45.0 #define gO0 r45.1 #define gWT1 r45.2 #define gO1 r45.3 #define gUW0 r45.4 #define gUO0 r45.5 #define gUW1 r45.6 #define gUO1 r45.7 #define gVW0 r45.8 #define gVO0 r45.9 #define gVW1 r45.10 #define gVO1 r45.11 #define gWT0_D r45.0 #define gUW0_D r45.2 //------------ Message-related Registers & constants #define gMSGSRC r2 // Message Source #define mMSGHDR m1 #define mMSGHDRY m1 #define mMSGHDRC m2 #define mMSGHDR1 m1 #define mMSGHDR2 m2 #define mMSGHDR3 m3 #define mMSGHDR4 m4 #define mMSGHDRYW m1 #define mMSGHDRCW m10 #ifdef DEV_ILK // 0000 0100(read) 0001(msg len) xxxx(resp len) 1010 (sampler cache) xxxx (field/frame) xxxx xxxx (bidx) #define nDWBRMSGDSC_SC 0x0208A002 // DWORD Block Read Message Descriptor through Data Port, Sampler Cache #define nDWBRMSGDSC_SC_TF 0x0208E602 // DWORD Block Read Message Descriptor through Data Port, Sampler Cache #define nDWBRMSGDSC_SC_BF 0x0208E702 // DWORD Block Read Message Descriptor through Data Port, Sampler Cache // 0000 0101(write) 0001(msg len) xxxx(resp len) 0010 (render cache) xxxx (field/frame) xxxx xxxx (bidx) #define nDWBWMSGDSC 0x02082000 // DWORD Block Write Message Descriptor through Data Port, Render Cache #define nDWBWMSGDSC_TF 0x02082600 // DWORD Block Write Message Descriptor through Data Port, Render Cache #define nDWBWMSGDSC_BF 0x02082700 // DWORD Block Write Message Descriptor through Data Port, Render Cache #else // Pre DEV_ILK // 0000 0100(read) 0001(msg len) xxxx(resp len) 1010 (sampler cache) xxxx (field/frame) xxxx xxxx (bidx) #define nDWBRMSGDSC_SC 0x0410A002 // DWORD Block Read Message Descriptor through Data Port, Sampler Cache #define nDWBRMSGDSC_SC_TF 0x0410A602 // DWORD Block Read Message Descriptor through Data Port, Sampler Cache #define nDWBRMSGDSC_SC_BF 0x0410A702 // DWORD Block Read Message Descriptor through Data Port, Sampler Cache // 0000 0101(write) 0001(msg len) xxxx(resp len) 0010 (render cache) xxxx (field/frame) xxxx xxxx (bidx) #define nDWBWMSGDSC 0x05102000 // DWORD Block Write Message Descriptor through Data Port, Render Cache #define nDWBWMSGDSC_TF 0x05102600 // DWORD Block Write Message Descriptor through Data Port, Render Cache #define nDWBWMSGDSC_BF 0x05102700 // DWORD Block Write Message Descriptor through Data Port, Render Cache #endif // DEV_ILK #define nDWB_FIELD_MASK 0x0600 // message data payload .declare mbMSGPAYLOADY Base=m2 ElementSize=1 SrcRegion=REGION(16,1) Type=b .declare mbMSGPAYLOADC Base=m11 ElementSize=1 SrcRegion=REGION(16,1) Type=b // Destination registers for write commit #define gREG_WRITE_COMMIT_Y r10.0 #define gREG_WRITE_COMMIT_UV r11.0 #define RETURN_REG_INTER r1.5 // Return pointer for all sub-routine calls (type DWORD) #define CALL_INTER(subFunc, skipInst) add (1) RETURN_REG_INTER<1>:ud ip:ud 1+skipInst*INST_SIZE \n\ jmpi (1) subFunc #define RETURN_INTER mov (1) ip:ud RETURN_REG_INTER<0;1,0>:ud // Return to calling module // End of inter_header.inc #endif // !defined(__INTER_HEADER__) intel-driver-1.3.0/src/shaders/h264/mc/interpolate_C_2x2.asm000066400000000000000000000036721231401140700234070ustar00rootroot00000000000000/* * Interpolation kernel for chrominance 2x2 motion compensation * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: Interpolate_C_2x2.asm // // Interpolation kernel for chrominance 2x2 motion compensation // // $Revision: 8 $ // $Date: 10/09/06 4:00p $ // //#if !defined(__Interpolate_C_2x2__) // Make sure this is only included once //#define __Interpolate_C_2x2__ // (8-xFrac) and (8-yFrac) add (2) gW0<1>:w gMVX_FRACC<2;2,1>:w -0x08:w // Compute the GRF address of the starting position of the reference area mov (1) pREF0:w nOFFSET_REFC:w {NoDDClr} mov (1) pRESULT:uw gpINTPC:uw {NoDDChk} // gCOEFA = (8-xFrac)*(8-yFrac) // gCOEFB = xFrac*(8-yFrac) // gCOEFC = (8-xFrac)*yFrac // gCOEFD = xFrac*yFrac mul (1) gCOEFD:w gMVX_FRACC:w gMVY_FRACC:w {NoDDClr} mul (1) gCOEFA:w -gW0:w -gW1:uw {NoDDClr,NoDDChk} mul (1) gCOEFB:w gMVX_FRACC:w -gW1:uw {NoDDClr,NoDDChk} mul (1) gCOEFC:w -gW0:w gMVY_FRACC:w {NoDDChk} // (8-xFrac)*(8-yFrac)*A // --------------------- mul (8) acc0<1>:uw r[pREF0,0]<8;4,1>:ub gCOEFA:uw // xFrac*(8-yFrac)*B // ------------------- mac (8) acc0<1>:uw r[pREF0,2]<8;4,1>:ub gCOEFB:uw // (8-xFrac)*yFrac*C // ------------------- mac (8) acc0<1>:uw r[pREF0,8]<8;4,1>:ub gCOEFC:uw // xFrac*yFrac*D // ----------------- mac (8) gwINTERIM_BUF2(0)<1> r[pREF0,10]<8;4,1>:ub gCOEFD:uw mov (4) r[pRESULT]<1>:uw gwINTERIM_BUF2(0)<4;4,1> {NoDDClr} mov (4) r[pRESULT,16]<1>:uw gwINTERIM_BUF2(0,4)<4;4,1> {NoDDChk} //#endif // !defined(__Interpolate_C_2x2__) intel-driver-1.3.0/src/shaders/h264/mc/interpolate_C_4x4.asm000066400000000000000000000044421231401140700234070ustar00rootroot00000000000000/* * Interpolation kernel for chrominance 4x4 motion compensation * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: Interpolate_C_4x4_Func.asm // // Interpolation kernel for chrominance 4x4 motion compensation // // $Revision: 8 $ // $Date: 10/09/06 4:00p $ // //#if !defined(__Interpolate_C_4x4_Func__) // Make sure this is only included once //#define __Interpolate_C_4x4_Func__ INTERLABEL(Interpolate_C_4x4_Func): // (8-xFrac) and (8-yFrac) add (2) gW0<1>:w gMVX_FRACC<2;2,1>:w -0x08:w // Compute the GRF address of the starting position of the reference area mov (1) pREF0:w nOFFSET_REFC:w {NoDDClr} mov (1) pREF1:uw nOFFSET_REFC+16:w {NoDDChk,NoDDClr} mov (1) pRESULT:uw gpINTPC:uw {NoDDChk} // gCOEFA = (8-xFrac)*(8-yFrac) // gCOEFB = xFrac*(8-yFrac) // gCOEFC = (8-xFrac)*yFrac // gCOEFD = xFrac*yFrac mul (1) gCOEFD:w gMVX_FRACC:w gMVY_FRACC:w {NoDDClr} mul (1) gCOEFA:w -gW0:w -gW1:uw {NoDDClr,NoDDChk} mul (1) gCOEFB:w gMVX_FRACC:w -gW1:uw {NoDDClr,NoDDChk} mul (1) gCOEFC:w -gW0:w gMVY_FRACC:w {NoDDChk} add (2) gW0<1>:uw pREF0<2;2,1>:uw 16:w // (8-xFrac)*(8-yFrac)*A // --------------------- mul (16) acc0<1>:uw r[pREF0,0]<16;8,1>:ub gCOEFA:uw mul (16) acc1<1>:uw r[pREF0,nGRFWIB]<16;8,1>:ub gCOEFA:uw // xFrac*(8-yFrac)*B // ------------------- mac (16) acc0<1>:uw r[pREF0,2]<16;8,1>:ub gCOEFB:uw mac (16) acc1<1>:uw r[pREF0,nGRFWIB+2]<16;8,1>:ub gCOEFB:uw // (8-xFrac)*yFrac*C // ------------------- mov (2) pREF0<1>:uw gW0<2;2,1>:uw mac (16) acc0<1>:uw r[pREF0,0]<8,1>:ub gCOEFC:uw mac (16) acc1<1>:uw r[pREF0,nGRFWIB]<8,1>:ub gCOEFC:uw // xFrac*yFrac*D // ----------------- mac (16) r[pRESULT]<1>:uw r[pREF0,2]<8,1>:ub gCOEFD:uw mac (16) r[pRESULT,GRFWIB]<1>:uw r[pREF0,nGRFWIB+2]<8,1>:ub gCOEFD:uw {SecHalf} //#endif // !defined(__Interpolate_C_4x4_Func__) intel-driver-1.3.0/src/shaders/h264/mc/interpolate_Y_4x4.asm000066400000000000000000000174101231401140700234340ustar00rootroot00000000000000/* * Interpolation kernel for luminance motion compensation * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: Interpolate_Y_4x4.asm // // Interpolation kernel for luminance motion compensation // // $Revision: 10 $ // $Date: 10/09/06 4:00p $ // // Compute the GRF address of the starting position of the reference area #if 1 (-f0.1) mov (1) pREF:w nOFFSET_REF+2+nGRFWIB:w (f0.1) mov (1) pREF:w nOFFSET_REF+2:w mov (1) pRESULT:uw gpINTPY:uw #else mov (1) pREF:w nOFFSET_REF+2+nGRFWIB:w {NoDDClr} mov (1) pRESULT:uw gpINTPY:uw {NoDDChk} #endif /* * | | * - - 0 1 2 3 + - * 4 5 6 7 * 8 9 A B * C D E F * - - + - - - + - * | | */ // Case 0 or.z.f0.1 (16) null:w gMVY_FRAC<0;1,0>:w gMVX_FRAC<0;1,0>:w (f0.1) mov (4) r[pRESULT]<1>:uw r[pREF0]<4;4,1>:ub (f0.1) mov (4) r[pRESULT,16]<1>:uw r[pREF0,16]<4;4,1>:ub (f0.1) mov (4) r[pRESULT,32]<1>:uw r[pREF0,32]<4;4,1>:ub (f0.1) mov (4) r[pRESULT,48]<1>:uw r[pREF0,48]<4;4,1>:ub (f0.1) jmpi INTERLABEL(Exit_Interpolate_Y_4x4) // Store all address registers mov (8) gpADDR<1>:w a0<8;8,1>:w mul.z.f0.0 (1) gW4:w gMVY_FRAC:w gMVX_FRAC:w and.nz.f0.1 (1) null gW4:w 1:w add (1) pREF1:uw pREF0:uw nGRFWIB/2:uw add (2) pREF2<1>:uw pREF0<2;2,1>:uw nGRFWIB:uw mov (4) gW0<1>:uw pREF0<4;4,1>:uw (f0.0) jmpi INTERLABEL(Interpolate_Y_H_4x4) (f0.1) jmpi INTERLABEL(Interpolate_Y_H_4x4) //----------------------------------------------------------------------- // CASE: A69BE (H/V interpolation) //----------------------------------------------------------------------- // Compute interim horizontal intepolation add (1) pREF0<1>:uw pREF0<0;1,0>:uw -34:w add (1) pREF1<1>:uw pREF1<0;1,0>:uw -18:w {NoDDClr} mov (1) pRESD:ud nOFFSET_INTERIM4x4_5:ud {NoDDChk} // Case 69be // Check whether this position is 'A' cmp.e.f0.0 (1) null gW4:w 4:w $for(0;<2;1) { add (16) acc0<1>:w r[pREF0,nGRFWIB*2*%1]<16;4,1>:ub r[pREF0,nGRFWIB*2*%1+5]<16;4,1>:ub {Compr} mac (16) acc0<1>:w r[pREF0,nGRFWIB*2*%1+1]<16;4,1>:ub -5:w {Compr} mac (16) acc0<1>:w r[pREF0,nGRFWIB*2*%1+2]<16;4,1>:ub 20:w {Compr} mac (16) acc0<1>:w r[pREF0,nGRFWIB*2*%1+3]<16;4,1>:ub 20:w {Compr} mac (16) r[pRES,nGRFWIB*%1]<1>:w r[pREF0,nGRFWIB*2*%1+4]<16;4,1>:ub -5:w {Compr} } // last line add (4) acc0<1>:w r[pREF0,nGRFWIB*2*2]<4;4,1>:ub r[pREF0,nGRFWIB*2*2+5]<4;4,1>:ub mac (4) acc0<1>:w r[pREF0,nGRFWIB*2*2+1]<4;4,1>:ub -5:w mac (4) acc0<1>:w r[pREF0,nGRFWIB*2*2+2]<4;4,1>:ub 20:w mac (4) acc0<1>:w r[pREF0,nGRFWIB*2*2+3]<4;4,1>:ub 20:w mac (4) r[pRES,nGRFWIB*2]<1>:w r[pREF0,nGRFWIB*2*2+4]<4;4,1>:ub -5:w // Compute interim/output vertical interpolation mov (1) pREF6D:ud nOFFSET_INTERIM4x4_4:ud {NoDDClr} mov (1) pREF0D:ud nOFFSET_INTERIM4x4_7:ud {NoDDChk,NoDDClr} mov (1) pREF2D:ud nOFFSET_INTERIM4x4_8:ud {NoDDChk,NoDDClr} mov (1) pREF4D:ud nOFFSET_INTERIM4x4_9:ud {NoDDChk} add (16) acc0<1>:w gwINTERIM4x4_BUF(0)<16;16,1> 512:w mac (16) acc0<1>:w gwINTERIM4x4_BUF(1)<16;16,1> -5:w mac (16) acc0<1>:w r[pREF6,0]<8,1>:w 20:w (f0.0) mov (1) pRES:uw nOFFSET_RES:uw // Case a (-f0.0) mov (1) pRES:uw nOFFSET_INTERIM4x4:uw // Case 69be mac (16) acc0<1>:w r[pREF0,0]<4,1>:w -5:w mac (16) acc0<1>:w r[pREF0,nGRFWIB]<4,1>:w 1:w mac (16) acc0<1>:w r[pREF2,0]<4,1>:w 20:w asr.sat (16) r[pRES]<2>:ub acc0<16;16,1>:w 10:w (f0.0) jmpi INTERLABEL(Return_Interpolate_Y_4x4) INTERLABEL(Interpolate_Y_H_4x4): cmp.e.f0.0 (1) null gMVX_FRAC:w 0:w cmp.e.f0.1 (1) null gMVY_FRAC:w 2:w (f0.0) jmpi INTERLABEL(Interpolate_Y_V_4x4) (f0.1) jmpi INTERLABEL(Interpolate_Y_V_4x4) //----------------------------------------------------------------------- // CASE: 123567DEF (H interpolation) //----------------------------------------------------------------------- add (4) pREF0<1>:uw gW0<4;4,1>:uw -2:w cmp.g.f0.0 (4) null:w gMVY_FRAC<0;1,0>:w 2:w cmp.e.f0.1 (1) null gMVX_FRAC:w 2:w (f0.0) add (4) pREF0<1>:uw pREF0<4;4,1>:uw nGRFWIB/2:uw cmp.e.f0.0 (1) null:w gMVY_FRAC<0;1,0>:w 0:w (f0.1) mov (1) pRESULT:uw nOFFSET_RES:uw // Case 26E (-f0.1) mov (1) pRESULT:uw nOFFSET_INTERIM4x4:uw // Case 1357DF // Compute interim/output horizontal interpolation add (16) acc0<1>:w r[pREF0]<4,1>:ub 16:w mac (16) acc0<1>:w r[pREF0,1]<4,1>:ub -5:w mac (16) acc0<1>:w r[pREF0,2]<4,1>:ub 20:w mac (16) acc0<1>:w r[pREF0,3]<4,1>:ub 20:w mac (16) acc0<1>:w r[pREF0,4]<4,1>:ub -5:w mac (16) acc0<1>:w r[pREF0,5]<4,1>:ub 1:w asr.sat (16) r[pRESULT]<2>:ub acc0<16;16,1>:w 5:w (-f0.1) jmpi INTERLABEL(Interpolate_Y_V_4x4) (-f0.0) jmpi INTERLABEL(Average_4x4) jmpi INTERLABEL(Return_Interpolate_Y_4x4) INTERLABEL(Interpolate_Y_V_4x4): cmp.e.f0.0 (1) null gMVY_FRAC:w 0:w (f0.0) jmpi INTERLABEL(Interpolate_Y_I_4x4) //----------------------------------------------------------------------- // CASE: 48C59D7BF (V interpolation) //----------------------------------------------------------------------- cmp.g.f0.1 (8) null:w gMVX_FRAC<0;1,0>:w 2:w mov (4) pREF0<1>:uw gW0<4;4,1>:uw {NoDDClr} add (4) pREF4<1>:w gW0<4;4,1>:uw 16:w {NoDDChk} (f0.1) add (8) pREF0<1>:uw pREF0<4;4,1>:uw 1:uw cmp.e.f0.0 (1) null:w gMVX_FRAC<0;1,0>:w 0:w cmp.e.f0.1 (1) null gMVY_FRAC:w 2:w // Compute interim/output vertical interpolation add (16) acc0<1>:w r[pREF0,-nGRFWIB]<4,1>:ub 16:w mac (16) acc0<1>:w r[pREF0]<4,1>:ub 20:w mac (16) acc0<1>:w r[pREF0,nGRFWIB]<4,1>:ub -5:w mac (16) acc0<1>:w r[pREF4,-nGRFWIB]<4,1>:ub -5:w mac (16) acc0<1>:w r[pREF4]<4,1>:ub 20:w mac (16) acc0<1>:w r[pREF4,nGRFWIB]<4,1>:ub 1:w mov (1) pRESULT:uw nOFFSET_RES:uw (-f0.0) jmpi INTERLABEL(VFILTER_4x4) (-f0.1) mov (1) pRESULT:uw nOFFSET_INTERIM4x4:uw INTERLABEL(VFILTER_4x4): asr.sat (16) r[pRESULT]<2>:ub acc0<16;16,1>:w 5:w (-f0.0) jmpi INTERLABEL(Average_4x4) (f0.1) jmpi INTERLABEL(Return_Interpolate_Y_4x4 ) INTERLABEL(Interpolate_Y_I_4x4): //----------------------------------------------------------------------- // CASE: 134C (Integer position) //----------------------------------------------------------------------- mov (4) pREF0<1>:uw gW0<4;4,1>:uw cmp.e.f0.0 (4) null:w gMVX_FRAC<0;1,0>:w 3:w cmp.e.f0.1 (4) null:w gMVY_FRAC<0;1,0>:w 3:w (f0.0) add (4) pREF0<1>:uw pREF0<4;4,1>:uw 1:uw (f0.1) add (4) pREF0<1>:uw pREF0<4;4,1>:uw nGRFWIB/2:uw mov (16) guwINTERIM_BUF2(0)<1> r[pREF0]<4,1>:ub INTERLABEL(Average_4x4): //----------------------------------------------------------------------- // CASE: 13456789BCDEF (Average) //----------------------------------------------------------------------- // Average two interim results avg.sat (16) gubINTERIM_BUF2(0)<2> gubINTERIM_BUF2(0)<32;16,2> gINTERIM4x4<32;16,2>:ub INTERLABEL(Return_Interpolate_Y_4x4): // Move result mov (1) pRES:uw gpINTPY:uw mov (4) r[pRES,0]<2>:ub gubINTERIM_BUF2(0,0) mov (4) r[pRES,16]<2>:ub gubINTERIM_BUF2(0,8) mov (4) r[pRES,32]<2>:ub gubINTERIM_BUF2(0,16) mov (4) r[pRES,48]<2>:ub gubINTERIM_BUF2(0,24) // Restore all address registers mov (8) a0<1>:w gpADDR<8;8,1>:w INTERLABEL(Exit_Interpolate_Y_4x4): // end of file intel-driver-1.3.0/src/shaders/h264/mc/interpolate_Y_8x8.asm000066400000000000000000000254541231401140700234530ustar00rootroot00000000000000/* * Interpolation kernel for luminance motion compensation * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: Interpolate_Y_8x8.asm // // Interpolation kernel for luminance motion compensation // // $Revision: 13 $ // $Date: 10/09/06 4:00p $ // //--------------------------------------------------------------- // In: pMV => Source address of MV // In: gMVX_FRAC<2;2,1>:w => MV fractional components // In: f0.1 (1) => If 1, vertical MV is integer // In: gpINTPY:uw => Destination address for interpolated result // In: Reference area staring from R43 // If horizontal/vertical MVs are all integer, 8x8 pixels are on R43~R44 (2 GRFs) // If only horz MV is integer, 8x13 pixels are on R43~R46 (4 GRFs) // If only vert MV is integer, 13x8 pixels are on R43~R46 (4 GRFs) // If no MVs are integer, 13x13 pixels are on R43~R49 (7 GRFs) //--------------------------------------------------------------- INTERLABEL(Interpolate_Y_8x8_Func): // Check whether MVX is integer MV and.z.f0.0 (1) null:w r[pMV,0]<0;1,0>:w 0x3:w (-f0.0) jmpi (1) INTERLABEL(Interpolate_Y_8x8_Func2) // TODO: remove this back-to-back read - huge latency.. mov (8) gubREF(6,2)<1> gubREF(3,0)<8;8,1> mov (8) gubREF(5,18)<1> gubREF(2,24)<8;8,1> {NoDDClr} mov (8) gubREF(5,2)<1> gubREF(2,16)<8;8,1> {NoDDChk} mov (8) gubREF(4,18)<1> gubREF(2,8)<8;8,1> {NoDDClr} mov (8) gubREF(4,2)<1> gubREF(2,0)<8;8,1> {NoDDChk} mov (8) gubREF(3,18)<1> gubREF(1,24)<8;8,1> {NoDDClr} mov (8) gubREF(3,2)<1> gubREF(1,16)<8;8,1> {NoDDChk} mov (8) gubREF(2,18)<1> gubREF(1,8)<8;8,1> {NoDDClr} mov (8) gubREF(2,2)<1> gubREF(1,0)<8;8,1> {NoDDChk} mov (8) gubREF(1,18)<1> gubREF(0,24)<8;8,1> {NoDDClr} mov (8) gubREF(1,2)<1> gubREF(0,16)<8;8,1> {NoDDChk} mov (8) gubREF(0,18)<1> gubREF(0,8)<8;8,1> mov (8) gubREF(0,2)<1> gubREF(0,0)<8;8,1> INTERLABEL(Interpolate_Y_8x8_Func2): // Compute the GRF address of the starting position of the reference area (-f0.1) mov (1) pREF:w nOFFSET_REF+2+nGRFWIB:w (f0.1) mov (1) pREF:w nOFFSET_REF+2:w mov (1) pRESULT:uw gpINTPY:uw /* * | | * - - 0 1 2 3 + - * 4 5 6 7 * 8 9 A B * C D E F * - - + - - - + - * | | */ // Case 0 or.z.f0.1 (16) null:w gMVY_FRAC<0;1,0>:w gMVX_FRAC<0;1,0>:w (f0.1) mov (16) r[pRESULT]<1>:uw r[pREF]<16;8,1>:ub (f0.1) mov (16) r[pRESULT,nGRFWIB]<1>:uw r[pREF,nGRFWIB]<16;8,1>:ub (f0.1) mov (16) r[pRESULT,nGRFWIB*2]<1>:uw r[pREF,nGRFWIB*2]<16;8,1>:ub (f0.1) mov (16) r[pRESULT,nGRFWIB*3]<1>:uw r[pREF,nGRFWIB*3]<16;8,1>:ub (f0.1) jmpi INTERLABEL(Exit_Interpolate_Y_8x8) // Store all address registers mov (8) gpADDR<1>:w a0<8;8,1>:w mul.z.f0.0 (1) gW4:w gMVY_FRAC:w gMVX_FRAC:w add (1) pREF1:uw pREF0:uw nGRFWIB/2:uw and.nz.f0.1 (1) null gW4:w 1:w add (2) pREF2<1>:uw pREF0<2;2,1>:uw nGRFWIB:uw mov (4) gW0<1>:uw pREF0<4;4,1>:uw (f0.0) jmpi INTERLABEL(Interpolate_Y_H_8x8) (f0.1) jmpi INTERLABEL(Interpolate_Y_H_8x8) //----------------------------------------------------------------------- // CASE: A69BE (H/V interpolation) //----------------------------------------------------------------------- // Compute interim horizontal intepolation of 12 lines (not 9 lines) // add (1) pREF0<1>:ud pREF0<0;1,0>:ud 0xffeeffde:ud // (-18<<16)|(-34) add (1) pREF0<1>:uw pREF0<0;1,0>:uw -34:w add (1) pREF1<1>:uw pREF1<0;1,0>:uw -18:w {NoDDClr} mov (1) pRESD:ud nOFFSET_INTERIM3:ud {NoDDChk} // Check whether this position is 'A' cmp.e.f0.0 (1) null gW4:w 4:w $for(0;<6;2) { add (32) acc0<1>:w r[pREF,nGRFWIB*%1]<16;8,1>:ub r[pREF0,nGRFWIB*%1+5]<16;8,1>:ub {Compr} mac (32) acc0<1>:w r[pREF,nGRFWIB*%1+1]<16;8,1>:ub -5:w {Compr} mac (32) acc0<1>:w r[pREF,nGRFWIB*%1+2]<16;8,1>:ub 20:w {Compr} mac (32) acc0<1>:w r[pREF,nGRFWIB*%1+3]<16;8,1>:ub 20:w {Compr} mac (32) r[pRES,nGRFWIB*%1]<1>:w r[pREF,nGRFWIB*%1+4]<16;8,1>:ub -5:w {Compr} } // last line add (8) acc0<1>:w r[pREF,nGRFWIB*6]<8;8,1>:ub r[pREF,nGRFWIB*6+5]<8;8,1>:ub mac (8) acc0<1>:w r[pREF,nGRFWIB*6+1]<8;8,1>:ub -5:w mac (8) acc0<1>:w r[pREF,nGRFWIB*6+2]<8;8,1>:ub 20:w mac (8) acc0<1>:w r[pREF,nGRFWIB*6+3]<8;8,1>:ub 20:w mac (8) r[pRES,nGRFWIB*6]<1>:w r[pREF,nGRFWIB*6+4]<8;8,1>:ub -5:w // Compute interim/output vertical interpolation mov (1) pREF0:ud nOFFSET_INTERIM2:ud {NoDDClr} // set pREF0 and pREF1 at the same time mov (1) pREF2D:ud nOFFSET_INTERIM4:ud {NoDDChk,NoDDClr} // set pREF2 and pREF3 at the same time (f0.0) sel (1) pRES:uw gpINTPY:uw nOFFSET_INTERIM:uw {NoDDChk} // Case A vs. 69BE $for(0;<4;2) { add (32) acc0<1>:w r[pREF0,nGRFWIB*%1]<16;16,1>:w 512:w {Compr} mac (16) acc0<1>:w r[pREF2,nGRFWIB*%1]<8,1>:w -5:w mac (16) acc1<1>:w r[pREF2,nGRFWIB*%1+nGRFWIB]<8,1>:w -5:w mac (32) acc0<1>:w r[pREF0,nGRFWIB*%1+nGRFWIB]<16;16,1>:w 20:w {Compr} mac (16) acc0<1>:w r[pREF2,nGRFWIB*%1+nGRFWIB]<8,1>:w 20:w mac (16) acc1<1>:w r[pREF2,nGRFWIB*%1+nGRFWIB+nGRFWIB]<8,1>:w 20:w mac (32) acc0<1>:w r[pREF0,(2+%1)*nGRFWIB]<16;16,1>:w -5:w {Compr} mac (16) acc0<1>:w r[pREF2,(2+%1)*nGRFWIB]<8,1>:w 1:w mac (16) acc1<1>:w r[pREF2,(2+%1)*nGRFWIB+nGRFWIB]<8,1>:w 1:w asr.sat (16) r[pRES,nGRFWIB*%1]<2>:ub acc0<16;16,1>:w 10:w asr.sat (16) r[pRES,nGRFWIB*%1+nGRFWIB]<2>:ub acc1<16;16,1>:w 10:w {SecHalf} } (f0.0) jmpi INTERLABEL(Return_Interpolate_Y_8x8) INTERLABEL(Interpolate_Y_H_8x8): cmp.e.f0.0 (1) null gMVX_FRAC:w 0:w cmp.e.f0.1 (1) null gMVY_FRAC:w 2:w (f0.0) jmpi INTERLABEL(Interpolate_Y_V_8x8) (f0.1) jmpi INTERLABEL(Interpolate_Y_V_8x8) //----------------------------------------------------------------------- // CASE: 123567DEF (H interpolation) //----------------------------------------------------------------------- add (4) pREF0<1>:uw gW0<4;4,1>:uw -2:w cmp.g.f0.0 (4) null:w gMVY_FRAC<0;1,0>:w 2:w cmp.e.f0.1 (1) null gMVX_FRAC:w 2:w (f0.0) add (4) pREF0<1>:uw pREF0<4;4,1>:uw nGRFWIB/2:uw cmp.e.f0.0 (1) null:w gMVY_FRAC<0;1,0>:w 0:w (f0.1) sel (1) pRES:uw gpINTPY:uw nOFFSET_INTERIM:uw // Case 26E vs. 1357DF // Compute interim/output horizontal interpolation $for(0;<4;2) { add (16) acc0<1>:w r[pREF0,nGRFWIB*%1]<8,1>:ub 16:w add (16) acc1<1>:w r[pREF0,nGRFWIB*%1+nGRFWIB]<8,1>:ub 16:w mac (16) acc0<1>:w r[pREF0,nGRFWIB*%1+1]<8,1>:ub -5:w mac (16) acc1<1>:w r[pREF0,nGRFWIB*%1+1+nGRFWIB]<8,1>:ub -5:w mac (16) acc0<1>:w r[pREF0,nGRFWIB*%1+2]<8,1>:ub 20:w mac (16) acc1<1>:w r[pREF0,nGRFWIB*%1+2+nGRFWIB]<8,1>:ub 20:w mac (16) acc0<1>:w r[pREF0,nGRFWIB*%1+3]<8,1>:ub 20:w mac (16) acc1<1>:w r[pREF0,nGRFWIB*%1+3+nGRFWIB]<8,1>:ub 20:w mac (16) acc0<1>:w r[pREF0,nGRFWIB*%1+4]<8,1>:ub -5:w mac (16) acc1<1>:w r[pREF0,nGRFWIB*%1+4+nGRFWIB]<8,1>:ub -5:w mac (16) acc0<1>:w r[pREF0,nGRFWIB*%1+5]<8,1>:ub 1:w mac (16) acc1<1>:w r[pREF0,nGRFWIB*%1+5+nGRFWIB]<8,1>:ub 1:w asr.sat (16) r[pRES,nGRFWIB*%1]<2>:ub acc0<16;16,1>:w 5:w asr.sat (16) r[pRES,nGRFWIB*%1+nGRFWIB]<2>:ub acc1<16;16,1>:w 5:w {SecHalf} } (-f0.1) jmpi INTERLABEL(Interpolate_Y_V_8x8) (-f0.0) jmpi INTERLABEL(Average_8x8) jmpi INTERLABEL(Return_Interpolate_Y_8x8) INTERLABEL(Interpolate_Y_V_8x8): cmp.e.f0.0 (1) null gMVY_FRAC:w 0:w (f0.0) jmpi INTERLABEL(Interpolate_Y_I_8x8) //----------------------------------------------------------------------- // CASE: 48C59D7BF (V interpolation) //----------------------------------------------------------------------- mov (2) pREF0<1>:uw gW0<4;2,2>:uw {NoDDClr} mov (2) pREF2<1>:uw gW1<2;2,1>:uw {NoDDChk,NoDDClr} mov (1) pRES:uw gpINTPY:uw {NoDDChk} cmp.g.f0.1 (4) null:w gMVX_FRAC<0;1,0>:w 2:w cmp.e.f0.0 (1) null:w gMVX_FRAC<0;1,0>:w 0:w (f0.1) add (4) pREF0<1>:uw pREF0<4;4,1>:uw 1:uw cmp.e.f0.1 (1) null gMVY_FRAC:w 2:w (-f0.0) jmpi INTERLABEL(VFILTER_8x8) (-f0.1) mov (1) pRES:uw nOFFSET_INTERIM:uw INTERLABEL(VFILTER_8x8): // Compute interim/output vertical interpolation $for(0;<4;2) { add (32) acc0<1>:w r[pREF0,nGRFWIB*%1-nGRFWIB]<16;8,1>:ub 16:w {Compr} mac (16) acc0<1>:w r[pREF2,nGRFWIB*%1-nGRFWIB]<8,1>:ub -5:w mac (16) acc1<1>:w r[pREF2,nGRFWIB*%1]<8,1>:ub -5:w mac (32) acc0<1>:w r[pREF0,nGRFWIB*%1]<16;8,1>:ub 20:w {Compr} mac (16) acc0<1>:w r[pREF2,nGRFWIB*%1]<8,1>:ub 20:w mac (16) acc1<1>:w r[pREF2,nGRFWIB*%1+nGRFWIB]<8,1>:ub 20:w mac (32) acc0<1>:w r[pREF0,nGRFWIB*%1+nGRFWIB]<16;8,1>:ub -5:w {Compr} mac (16) acc0<1>:w r[pREF2,nGRFWIB*%1+nGRFWIB]<8,1>:ub 1:w mac (16) acc1<1>:w r[pREF2,nGRFWIB*%1+nGRFWIB+nGRFWIB]<8,1>:ub 1:w asr.sat (16) r[pRES,nGRFWIB*%1]<2>:ub acc0<16;16,1>:w 5:w asr.sat (16) r[pRES,nGRFWIB*%1+nGRFWIB]<2>:ub acc1<16;16,1>:w 5:w {SecHalf} } (-f0.0) jmpi INTERLABEL(Average_8x8) (f0.1) jmpi INTERLABEL(Return_Interpolate_Y_8x8) INTERLABEL(Interpolate_Y_I_8x8): //----------------------------------------------------------------------- // CASE: 134C (Integer position) //----------------------------------------------------------------------- mov (2) pREF0<1>:uw gW0<2;2,1>:uw {NoDDClr} mov (1) pRES:uw gpINTPY:uw {NoDDChk} cmp.e.f0.0 (2) null:w gMVX_FRAC<0;1,0>:w 3:w cmp.e.f0.1 (2) null:w gMVY_FRAC<0;1,0>:w 3:w (f0.0) add (2) pREF0<1>:uw pREF0<2;2,1>:uw 1:uw (f0.1) add (2) pREF0<1>:uw pREF0<2;2,1>:uw nGRFWIB/2:uw mov (16) r[pRES]<1>:uw r[pREF0]<8,1>:ub mov (16) r[pRES,nGRFWIB]<1>:uw r[pREF0,nGRFWIB]<8,1>:ub mov (16) r[pRES,nGRFWIB*2]<1>:uw r[pREF0,nGRFWIB*2]<8,1>:ub mov (16) r[pRES,nGRFWIB*3]<1>:uw r[pREF0,nGRFWIB*3]<8,1>:ub INTERLABEL(Average_8x8): //----------------------------------------------------------------------- // CASE: 13456789BCDEF (Average) //----------------------------------------------------------------------- // Average two interim results avg.sat (16) r[pRES,0]<2>:ub r[pRES,0]<32;16,2>:ub gubINTERIM_BUF(0) avg.sat (16) r[pRES,nGRFWIB]<2>:ub r[pRES,nGRFWIB]<32;16,2>:ub gubINTERIM_BUF(1) avg.sat (16) r[pRES,nGRFWIB*2]<2>:ub r[pRES,nGRFWIB*2]<32;16,2>:ub gubINTERIM_BUF(2) avg.sat (16) r[pRES,nGRFWIB*3]<2>:ub r[pRES,nGRFWIB*3]<32;16,2>:ub gubINTERIM_BUF(3) INTERLABEL(Return_Interpolate_Y_8x8): // Restore all address registers mov (8) a0<1>:w gpADDR<8;8,1>:w INTERLABEL(Exit_Interpolate_Y_8x8): // end of file intel-driver-1.3.0/src/shaders/h264/mc/intra_Header.inc000066400000000000000000000333271231401140700225020ustar00rootroot00000000000000/* * Header file for all AVC intra prediction kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__INTRA_HEADER__) // Make sure this file is only included once #define __INTRA_HEADER__ // Module name: intra_header.inc // // Header file for all AVC intra prediction kernels // // This header file defines everything that's specific to intra macroblock kernels // ----------- Various data buffers and pointers ------------ // // I_PCM data buffer // #define I_PCM_BUF_Y 4 #define I_PCM_BUF_UV 12 #define REG_I_PCM_BUF_Y r4 #define REG_I_PCM_BUF_UV r12 .declare I_PCM_Y Base=REG_I_PCM_BUF_Y ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8-bit I_PCM Y data .declare I_PCM_UV Base=REG_I_PCM_BUF_UV ElementSize=1 SrcRegion=REGION(16,1) Type=ub // 8-bit I_PCM U/V data // Intra macroblock error data blocks // #define ERRBUF 4 // Starting GRF index for error data #define REG_ERRBUF r4 .declare MBBLOCKW Base=REG_ERRBUF ElementSize=2 SrcRegion=REGION(16,1) Type=w // For 16-bit inter MB .declare MBBLOCKD Base=REG_ERRBUF ElementSize=2 SrcRegion=REGION(16,1) Type=uw // For use in "send" command #define PERROR a0.2 // Pointer to macroblock error data #define PERROR1 a0.3 // Pointer to macroblock error data used by instruction compression #define PERROR_UD a0.1 // Pointer to macroblock error data in DWORD unit // Intra macroblock reference data // #define REG_INTRA_REF_TOP r49 // Must be an odd numbered GRF register .declare INTRA_REF_TOP0 Base=REG_INTRA_REF_TOP ElementSize=1 SrcRegion=REGION(16,1) Type=ub .declare INTRA_REF_TOP Base=REG_INTRA_REF_TOP.4 ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Actual top row reference data start at offset 4 in BYTE .declare INTRA_REF_TOP_W Base=REG_INTRA_REF_TOP.2 ElementSize=2 SrcRegion=REGION(16,1) Type=uw // Actual top row reference data start at offset 2 in WORD .declare INTRA_REF_TOP_D Base=REG_INTRA_REF_TOP ElementSize=4 DstRegion=<1> Type=ud // Only used in "send" instruction #define INTRA_REF_LEFT_ID 50 #define REG_INTRA_REF_LEFT r50 .declare INTRA_REF_LEFT0 Base=REG_INTRA_REF_LEFT ElementSize=1 SrcRegion=REGION(8,4) Type=ub .declare INTRA_REF_LEFT Base=REG_INTRA_REF_LEFT.3 ElementSize=1 SrcRegion=REGION(8,4) Type=ub // Actual left column reference data are located at offset 3 in BYTE .declare INTRA_REF_LEFT_UV Base=REG_INTRA_REF_LEFT.2 ElementSize=1 SrcRegion=REGION(8,4) Type=ub // Actual left column U/V reference data are located at offset 2 in BYTE .declare INTRA_REF_LEFT_W Base=REG_INTRA_REF_LEFT.1 ElementSize=2 SrcRegion=REGION(8,2) Type=uw // Actual left column reference data are located at offset 1 in WORD .declare INTRA_REF_LEFT_D Base=REG_INTRA_REF_LEFT ElementSize=4 DstRegion=<1> Type=ud // Only used in "send" instruction #define PREF_LEFT a0.4 // Pointer to left reference data #define PREF_LEFT_UD a0.2 // Pointer in DWORD to left reference data #define INTRA_TEMP_0 52 #define INTRA_TEMP_1 53 #define INTRA_TEMP_2 54 #define INTRA_TEMP_3 55 #define INTRA_TEMP_4 56 #define INTRA_TEMP_5 57 #define INTRA_TEMP_6 58 #define REG_INTRA_TEMP_0 r52 #define REG_INTRA_TEMP_1 r53 #define REG_INTRA_TEMP_2 r54 #define REG_INTRA_TEMP_3 r55 #define REG_INTRA_TEMP_4 r56 #define REG_INTRA_TEMP_5 r57 #define REG_INTRA_TEMP_6 r58 #define REG_INTRA_TEMP_7 r59 #define REG_INTRA_TEMP_8 r60 // Destination registers for write commit #define REG_WRITE_COMMIT_Y r60.0 #define REG_WRITE_COMMIT_UV r61.0 // ----------- Various data buffers and pointers ------------ // R32 - R47 for predicted picture buffer (for both Y and U/V blocks) // #define PREDBUF 32 // Starting GRF index for predicted buffer #define REG_PREDBUF r32 .declare PRED_Y Base=REG_PREDBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted Y picture .declare PRED_YW Base=REG_PREDBUF ElementSize=2 SrcRegion=REGION(16,1) Type=uw // Predicted Y picture stored in WORD .declare PRED_Y_FM Base=REG_PREDBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted Y picture frame .declare PRED_Y_TF Base=REG_PREDBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted Y picture Top field .declare PRED_UV Base=REG_PREDBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted U/V picture .declare PRED_UVW Base=REG_PREDBUF ElementSize=2 SrcRegion=REGION(16,1) Type=uw // Predicted U/V picture stored in WORD .declare PRED_UV_FM Base=REG_PREDBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted U/V picture frame .declare PRED_UV_TF Base=REG_PREDBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted U/V picture top field .declare PRED_UV_BF Base=REG_PREDBUF.16 ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Predicted U/V picture bottom field // The same region will also be used as finally decoded Y blocks shared with U/V blocks // #define DECBUF 32 #define REG_DECBUF r32 .declare DEC_Y Base=REG_DECBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Decoded Y picture .declare DEC_UV Base=REG_DECBUF ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Decoded U/V P-/B-picture .declare DEC_UD Base=REG_DECBUF ElementSize=4 SrcRegion=REGION(8,1) Type=ud // Decoded buffer in UD type // Reference buffer for intra_NxN prediction // #define PRED_MODE REG_INTRA_TEMP_0 .declare REF_TOP0 Base=REG_INTRA_TEMP_5 ElementSize=1 SrcRegion=REGION(16,1) Type=ub .declare REF_TOP Base=REG_INTRA_TEMP_5.4 ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Actual top reference data start from offset 3,i.e. p[-1,-1] .declare REF_TOP_W Base=REG_INTRA_TEMP_5 ElementSize=2 SrcRegion=REGION(16,1) Type=uw .declare REF_TOP_D Base=REG_INTRA_TEMP_5 ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare REF_LEFT Base=REG_INTRA_TEMP_6 ElementSize=1 SrcRegion=REGION(16,1) Type=ub .declare REF_LEFT_D Base=REG_INTRA_TEMP_6 ElementSize=4 SrcRegion=REGION(8,1) Type=ud // For intra prediction plane mode // .declare H1 Base=REG_INTRA_TEMP_0 ElementSize=2 SrcRegion=REGION(8,1) Type=w // Make sure it's an even GRF .declare H2 Base=REG_INTRA_TEMP_0.8 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare V1 Base=REG_INTRA_TEMP_1 ElementSize=2 SrcRegion=REGION(8,1) Type=w // Make sure it's the following odd GRF .declare V2 Base=REG_INTRA_TEMP_1.8 ElementSize=2 SrcRegion=REGION(8,1) Type=w .declare CP Base=REG_INTRA_TEMP_2 ElementSize=2 SrcRegion=REGION(16,1) Type=w #define PINTRAPRED_Y a0.7 // Used as luma intra prediction mode pointer #define PINTRAPRED_UV a0.7 // Used as chroma intra prediction mode pointer #define PINTRA4X4_Y a0.4 // Used as luma intra_4x4 prediction mode pointer #define PBWDCOPY_4 a0.4 // a0.4 - a0.7 used in intra_4x4 prediction for moving data backward #define PBWDCOPY_8 a0.6 // a0.6 - a0.7 used in intra_8x8 prediction for moving data backward // For Intra_4x4 prediction mode // .declare INTRA_4X4_MODE Base=REG_INTRA_TEMP_1 ElementSize=4 SrcRegion=REGION(1,0) DstRegion=<1> Type=d // Actually only need 1 DWORD // ----------- Intra CURBE constants ------------ // #define REG_CURBE1 r1 #define REG_CURBE2 r2 #define INTRA_4X4_OFFSET 1*GRFWIB // 9 Bytes #define INTRA_8X8_OFFSET 1*GRFWIB+12 // 9 Bytes starting sub-register r1.3:ud #define INTRA_16X16_OFFSET 1*GRFWIB+24 // 4 Bytes starting sub-register r1.6:ud #define INTRA_CHROMA_OFFSET 1*GRFWIB+28 // 4 Bytes starting sub-register r1.7:ud #define TOP_REF_OFFSET REG_CURBE1.10 // r1.5:w // Constants used in plane intra prediction mode #define XY_3 REG_CURBE2.4 // Stored BYTE constants x-3 for x=0...7, i.e. -3,-2,...3,4 for U/V, need duplicate to every other byte #define XY_3_1 REG_CURBE2.5 // Stored BYTE constants x-3 for x=0...7, i.e. -3,-2,...3,4 for 2nd instruction in {Comp} #define XY_7 REG_CURBE2.0 // Stored BYTE constants x-7 for x=0...15, i.e. -7,-6,...7,8 for Y #define XY_7_1 REG_CURBE2.1 // Stored BYTE constants x-7 for x=0...15, i.e. -7,-6,...7,8 for 2nd instruction in {Comp} #define INV_SHIFT REG_CURBE2.16 #define INV_TRANS4 REG_CURBE2.20 // For reverse data transfer for intra_4x4 (0x00020406) #define INV_TRANS48 REG_CURBE2.22 // For reverse data transfer for intra_4x4 (0x0002) #define INV_TRANS8 REG_CURBE1.22 // For reverse data transfer for intra_8x8 (0x0001) #define INTRA_MODE REG_CURBE2.24 // Offset to intra_Pred_4x4_Y from each sub-block // ----------- In-line parameters ------------ // #define REG_INLINE r3 #define INLINE_DW0 REG_INLINE.0<0;1,0>:ud #define INLINE_DW1 REG_INLINE.1<0;1,0>:ud #define INLINE_DW2 REG_INLINE.2<0;1,0>:ud #define INLINE_DW3 REG_INLINE.3<0;1,0>:ud #define INLINE_DW4 REG_INLINE.4<0;1,0>:ud #define INLINE_DW5 REG_INLINE.5<0;1,0>:ud #define INLINE_DW6 REG_INLINE.6<0;1,0>:ud #define INLINE_DW7 REG_INLINE.7<0;1,0>:ud // Intra macroblock in-line data // // In-line DWORD 0 #define REG_MBAFF_FIELD REG_INLINE.1 // :uw, can be added directly to lower-word of MSGDSC #define MBAFF_FIELD BIT26+BIT25 // Bits 26:25 - MBAFF field macroblock flag // 00 = Current macroblock is not an MBAFF field macroblock // 11 = Current macroblock is an MBAFF field macroblock #define REG_FIELD_PARITY INLINE_DW0 #define FIELD_PARITY BIT24 // Bit 24 - Macroblock field parity flag // 0 = Current field is a top field // 1 = Current field is a bottom field #define REG_FIELD_MACROBLOCK_FLAG INLINE_DW0 #define FIELD_MACROBLOCK_FLAG BIT14 // Bit 14 - Field macroblock flag // 0 = Current macroblock is not a field macroblock // 1 = Current macroblock is a field macroblock #define REG_MACROBLOCK_TYPE INLINE_DW0 #define MACROBLOCK_TYPE BIT12+BIT11+BIT10+BIT9+BIT8 // Bit 12:8 - Intra macroblock flag #define REG_CHROMA_FORMAT_IDC INLINE_DW0 #define CHROMA_FORMAT_IDC BIT3+BIT2 // Bit 3:2 - Chroma format // 00 = Luma only (Monochrome) // 01 = YUV420 // 10 = YUV422 // 11 = YUV444 #define REG_MBAFF_PIC INLINE_DW0 #define MBAFF_PIC BIT1 // Bit 1 - MBAFF Frame picture // 0 = Not an MBAFF frame picture // 1 = An MBAFF frame picture #define REG_INTRA_PRED_8X8_BLK2_AVAIL_FLAG INLINE_DW0 #define INTRA_PRED_8X8_BLK2_AVAIL_FLAG BIT4 // Bit 4: Pixel available for block 2 in an intra_8x8 MB. // In-line DWORD 1 #define ORIX REG_INLINE.4 // :ub, H. origin of the macroblock in macroblock unit #define ORIY REG_INLINE.5 // :ub, V. origin of the macroblock in macroblock unit // In-line DWORD 2 #define REG_CBPCYB REG_INLINE.9 // :ub, Coded block pattern #define REG_CBPCY INLINE_DW2 // Bits 13:8 - Coded block pattern // reflect Y0, Y1, Y2, Y3, Cb4, Cr5 // Bit 13 - Y0 // Bit 12 - Y1 // Bit 11 - Y2 // Bit 10 - Y3 // Bit 9 - U4 // Bit 8 - V5 #define CBP_MASK 0x3F00:ud // Bit mask for all CBP bits #define CBP_Y_MASK 0x3C00:ud // Bit mask for CBP Y bits #define CBP_UV_MASK 0x0300:ud // Bit mask for CBP U/V bits #define CBP_Y0_MASK BIT13:ud // Bit mask for CBP Y0 bit #define CBP_Y1_MASK BIT12:ud // Bit mask for CBP Y1 bit #define CBP_Y2_MASK BIT11:ud // Bit mask for CBP Y2 bit #define CBP_Y3_MASK BIT10:ud // Bit mask for CBP Y3 bit #define CBP_U_MASK BIT9:ud // Bit mask for CBP U bit #define CBP_V_MASK BIT8:ud // Bit mask for CBP V bit // In-line DWORD 3 #define REG_INTRA_CHROMA_PRED_MODE REG_INLINE.12 // :ub - Intra chroma prediction mode #define INTRA_CHROMA_PRED_MODE BIT7+BIT6 // Bit 7:6 - Intra chroma prediction mode // 00 = Intra DC prediction // 01 = Intra horizontal prediction // 10 = Intra vertical prediction // 11 = Intra plane prediction #define INTRA_CHROMA_PRED_MODE_SHIFT 6 // Intra chroma prediction mode shift #define REG_INTRA_PRED_AVAIL_FLAG INLINE_DW3 #define INTRA_PRED_AVAIL_FLAG BIT4+BIT3+BIT2+BIT1+BIT0 // Bits 4:0 - Intra prediction available flag // Bit 0: Macroblock A (the left neighbor) entire or top half // Bit 1: Macroblock B (the upper neighbor) // Bit 2: Macroblock C (the above-right neighbor) // Bit 3: Macroblock D (the above-left neighbor) // Bit 4: Macroblock A (the left neighbor) bottom half // Each bit is defined below // 0 = The macroblock is not available for intra prediction // 1 = The macroblock is available for intra prediction #define INTRA_PRED_LEFT_TH_AVAIL_FLAG BIT0 // Bit 0: Macroblock A (the left neighbor) entire or top half #define INTRA_PRED_UP_AVAIL_FLAG BIT1 // Bit 1: Macroblock B (the upper neighbor) #define INTRA_PRED_UP_RIGHT_AVAIL_FLAG BIT2 // Bit 2: Macroblock C (the above-right neighbor) #define INTRA_PRED_UP_LEFT_AVAIL_FLAG BIT3 // Bit 3: Macroblock D (the above-left neighbor) #define INTRA_PRED_LEFT_BH_AVAIL_FLAG BIT4 // Bit 4: Macroblock A (the left neighbor) bottom half //#define INTRA_PRED_8X8_BLK2_AVAIL_FLAG BIT5 // Bit 5: Pixel available for block 2 in an intra_8x8 MB. #define REG_INTRA_PRED_AVAIL_FLAG_BYTE REG_INLINE.12 // Byte location of Intra_Pred_Avail_Flag #define REG_INTRA_PRED_AVAIL_FLAG_WORD REG_INLINE.6 // Word location of Intra_Pred_Avail_Flag .declare INTRA_PRED_MODE Base=REG_INLINE.16 ElementSize=1 SrcRegion=REGION(16,1) Type=ub // Intra prediction mode // End of intra_header.inc #endif // !defined(__INTRA_HEADER__) intel-driver-1.3.0/src/shaders/h264/mc/intra_Pred_4x4_Y_4.asm000066400000000000000000000250011231401140700234130ustar00rootroot00000000000000/* * Intra predict 4 Intra_4x4 luma blocks * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__INTRA_PRED_4X4_Y_4__) // Make sure this is only included once #define __INTRA_PRED_4X4_Y_4__ // Module name: intra_Pred_4x4_Y_4.asm // // Intra predict 4 Intra_4x4 luma blocks // //-------------------------------------------------------------------------- // Input data: // // REF_TOP: Top reference data stored in BYTE with p[-1,-1] at REF_TOP(0,-1) // REF_LEFT: Left reference data stored in BYTE with p[-1,0] at REF_LEFT(0,0) // PRED_MODE: Intra prediction mode stored in 4 words (4 LSB) // REG_INTRA_PRED_AVAIL: Top/Left available flag, (Bit0: Left, Bit1: Top) // //-------------------------------------------------------------------------- #undef INTRA_PRED_AVAIL #undef INTRA_REF #undef REF_LEFT_BACK #undef REF_TMP #undef REF_TMP1 #define INTRA_PRED_AVAIL REG_INTRA_TEMP_2.8 #define INTRA_REF REG_INTRA_TEMP_2 #define REF_LEFT_BACK REG_INTRA_TEMP_8 #define REF_TMP REG_INTRA_TEMP_3 #define REF_TMP1 REG_INTRA_TEMP_4 intra_Pred_4x4_Y_4: mov (8) REF_LEFT_BACK<1>:ub REF_LEFT(0)REGION(8,1) // Store left referece data // Set up pointers to each intra_4x4 prediction mode // and (4) PINTRA4X4_Y<1>:w PRED_MODE<4;4,1>:w 0x0F:w add (4) INTRA_4X4_MODE(0) r[PINTRA4X4_Y, INTRA_4X4_OFFSET]<1,0>:ub INTRA_MODE<4;4,1>:ub // Sub-block 0 ***************** mov (1) INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL<0;1,0>:w // Top/Left neighbor available flags CALL_1(INTRA_4X4_MODE(0),1) // Add error data to predicted intra data ADD_ERROR_SB0: add.sat (8) r[PPREDBUF_Y,PREDSUBBLK0]<2>:ub r[PERROR,ERRBLK0]<8;4,1>:w REG_INTRA_4X4_PRED<8;8,1>:w // Too bad indexed src can't add.sat (8) r[PPREDBUF_Y,PREDSUBBLK0+16]<2>:ub r[PERROR,ERRBLK0+32]<8;4,1>:w REG_INTRA_4X4_PRED.8<8;8,1>:w // cross 2 GRFs // Sub-block 1 ***************** mov (16) REF_TOP0(0)<1> REF_TOP0(0,4)REGION(8,1) // Top reference data mov (4) REF_LEFT(0)<1> r[PPREDBUF_Y,PREDSUBBLK0+6]<8;1,0>:ub // New left referece data from sub-block 0 or (1) INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL<0;1,0>:w 1:w // Left neighbor is available CALL_1(INTRA_4X4_MODE(0,1),1) // Add error data to predicted intra data ADD_ERROR_SB1: add.sat (8) r[PPREDBUF_Y,PREDSUBBLK1]<2>:ub r[PERROR,ERRBLK1]<8;4,1>:w REG_INTRA_4X4_PRED<8;8,1>:w // Too bad indexed src can't add.sat (8) r[PPREDBUF_Y,PREDSUBBLK1+16]<2>:ub r[PERROR,ERRBLK1+32]<8;4,1>:w REG_INTRA_4X4_PRED.8<8;8,1>:w // cross 2 GRFs // Sub-block 2 ***************** mov (1) REF_TOP0(0,3)<1> REF_LEFT_BACK.3<0;1,0>:ub // Top-left reference data from stored left referece data mov (4) REF_TOP0(0,4)<1> r[PPREDBUF_Y,PREDSUBBLK0+24]REGION(4,2):ub // Top reference data mov (4) REF_TOP0(0,8)<1> r[PPREDBUF_Y,PREDSUBBLK0+24+32]REGION(4,2):ub // Too bad indexed src can't cross 2 GRFs mov (4) REF_TOP0(0,12)<1> r[PPREDBUF_Y,PREDSUBBLK0+30+32]REGION(1,0):ub // Extended top-right reference data mov (4) REF_LEFT(0)<1> REF_LEFT_BACK.4<4;4,1>:ub // From stored left referece data or (1) INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL<0;1,0>:w 2:w // Top neighbor is available CALL_1(INTRA_4X4_MODE(0,2),1) // Add error data to predicted intra data ADD_ERROR_SB2: add.sat (8) r[PPREDBUF_Y,PREDSUBBLK2]<2>:ub r[PERROR,ERRBLK2]<8;4,1>:w REG_INTRA_4X4_PRED<8;8,1>:w // Too bad indexed src can't add.sat (8) r[PPREDBUF_Y,PREDSUBBLK2+16]<2>:ub r[PERROR,ERRBLK2+32]<8;4,1>:w REG_INTRA_4X4_PRED.8<8;8,1>:w // cross 2 GRFs // Sub-block 3 ***************** mov (16) REF_TOP0(0)<1> REF_TOP0(0,4)REGION(8,1) // Top reference data mov (8) REF_TOP0(0,8)<1> REF_TOP0(0,7)<0;1,0> // Extended top-right reference data mov (4) REF_LEFT(0)<1> r[PPREDBUF_Y,PREDSUBBLK2+6]<8;1,0>:ub // Left referece data from sub-block 0 or (1) INTRA_PRED_AVAIL<1>:w REG_INTRA_PRED_AVAIL<0;1,0>:w 3:w // Top/Left neighbor are available CALL_1(INTRA_4X4_MODE(0,3),1) // Add error data to predicted intra data ADD_ERROR_SB3: add.sat (8) r[PPREDBUF_Y,PREDSUBBLK3]<2>:ub r[PERROR,ERRBLK3]<8;4,1>:w REG_INTRA_4X4_PRED<8;8,1>:w // Too bad indexed src can't add.sat (8) r[PPREDBUF_Y,PREDSUBBLK3+16]<2>:ub r[PERROR,ERRBLK3+32]<8;4,1>:w REG_INTRA_4X4_PRED.8<8;8,1>:w // cross 2 GRFs RETURN //-------------------------------------------------------------------------- // Actual module that performs Intra_4x4 prediction and construction // // REF_TOP: Top reference data stored in BYTE with p[-1,-1] at REF_TOP(0,-1) // REF_LEFT: Left reference data stored in BYTE with p[-1,0] at REF_LEFT(0,0) // PINTRA4X4_Y: Intra prediction mode // INTRA_PRED_AVAIL: Top/Left available flag, (Bit0: Left, Bit1: Top) // // Output data: // // REG_INTRA_4X4_PRED: Predicted 4x4 block data stored in 1 GRF register //-------------------------------------------------------------------------- intra_Pred_4x4_Y: // Mode 0 INTRA_4X4_VERTICAL: mov (16) REG_INTRA_4X4_PRED<1>:w REF_TOP(0)<0;4,1> RETURN_1 // Mode 1 INTRA_4X4_HORIZONTAL: mov (16) REG_INTRA_4X4_PRED<1>:w REF_LEFT(0)<1;4,0> RETURN_1 // Mode 2 INTRA_4X4_DC: // Rearrange reference samples for unified DC prediction code // and.nz.f0.0 (16) NULLREG INTRA_PRED_AVAIL<0;1,0>:w 2:w {Compr} and.nz.f0.1 (16) NULLREG INTRA_PRED_AVAIL<0;1,0>:w 1:w {Compr} (-f0.0.any16h) mov (16) REF_TOP_W(0)<1> 0x8080:uw // Top macroblock not available for intra prediction (-f0.1.any8h) mov (8) REF_LEFT(0)<1> REF_TOP(0)REGION(8,1) // Left macroblock not available for intra prediction (-f0.0.any8h) mov (8) REF_TOP(0)<1> REF_LEFT(0)REGION(8,1) // Top macroblock not available for intra prediction // Perform DC prediction // add (4) PRED_YW(15)<1> REF_TOP(0)REGION(4,1) REF_LEFT(0)REGION(4,1) add (2) PRED_YW(15)<1> PRED_YW(15)REGION(2,1) PRED_YW(15,2)REGION(2,1) add (16) acc0<1>:w PRED_YW(15)REGION(1,0) PRED_YW(15,1)REGION(1,0) add (16) acc0<1>:w acc0:w 4:w shr (16) REG_INTRA_4X4_PRED<1>:w acc0:w 3:w RETURN_1 // Mode 3 INTRA_4X4_DIAG_DOWN_LEFT: mov (8) INTRA_REF<1>:ub REF_TOP(0)REGION(8,1) // Keep REF_TOP untouched for future use mov (4) INTRA_REF.8<1>:ub REF_TOP(0,7)REGION(4,1) // p[8,-1] = p[7,-1] add (8) acc0<1>:w INTRA_REF.2<8;8,1> 2:w // p[x+2]+2 mac (8) acc0<1>:w INTRA_REF.1<8;8,1> 2:w // 2*p[x+1]+p[x+2]+2 mac (8) PRED_YW(15)<1> INTRA_REF.0<8;8,1> 1:w // p[x]+2*p[x+1]+p[x+2]+2 shr (16) REG_INTRA_4X4_PRED<1>:w PRED_YW(15)<1;4,1> 2:w // (p[x]+2*p[x+1]+p[x+2]+2)>>2 RETURN_1 // Mode 4 INTRA_4X4_DIAG_DOWN_RIGHT: // Set inverse shift count shl (4) REF_TMP<1>:ud REF_LEFT_D(0)REGION(1,0) INV_SHIFT<4;4,1>:b mov (8) INTRA_REF.4<1>:ub REF_TOP(0,-1)REGION(8,1) // INTRA_REF holds all reference data mov (4) INTRA_REF<1>:ub REF_TMP.3<16;4,4>:ub add (8) acc0<1>:w INTRA_REF.2<8;8,1>:ub 2:w // p[x+2]+2 mac (8) acc0<1>:w INTRA_REF.1<8;8,1>:ub 2:w // 2*p[x+1]+p[x+2]+2 mac (8) INTRA_REF<1>:w INTRA_REF<8;8,1>:ub 1:w // p[x]+2*p[x+1]+p[x+2]+2 // Store data in reversed order add (4) PBWDCOPY_4<1>:w INV_TRANS4<4;4,1>:b INTRA_TEMP_2*GRFWIB:w // Must match with INTRA_REF shr (16) REG_INTRA_4X4_PRED<1>:w r[PBWDCOPY_4]<4,1>:w 2:w RETURN_1 // Mode 5 INTRA_4X4_VERT_RIGHT: // Set inverse shift count shl (4) REF_TMP<1>:ud REF_LEFT_D(0)REGION(1,0) INV_SHIFT<4;4,1>:b mov (8) INTRA_REF.4<1>:ub REF_TOP(0,-1)REGION(8,1) // INTRA_REF holds all reference data mov (4) INTRA_REF<1>:ub REF_TMP.3<16;4,4>:ub // Even rows avg (8) PRED_YW(14)<1> INTRA_REF.4<8;8,1> INTRA_REF.5<8;8,1> // avg(p[x-1],p[x]) // Odd rows add (8) acc0<1>:w INTRA_REF.3<8;8,1>:ub 2:w // p[x]+2 mac (8) acc0<1>:w INTRA_REF.2<8;8,1>:ub 2:w // 2*p[x-1]+p[x]+2 mac (8) acc0<1>:w INTRA_REF.1<8;8,1>:ub 1:w // p[x-2]+2*p[x-1]+p[x]+2 shr (8) INTRA_REF<1>:w acc0:w 2:w // (p[x-2]+2*p[x-1]+p[x]+2)>>2 mov (4) INTRA_REF.2<2>:w INTRA_REF.2<4;4,1>:w // Keep zVR = -2,-3 unchanged mov (4) INTRA_REF.3<2>:w PRED_YW(14)REGION(4,1) // Combining even rows add (4) PBWDCOPY_4<1>:w INV_TRANS4<4;4,1>:b INTRA_TEMP_2*GRFWIB:w // Must match with INTRA_REF mov (16) REG_INTRA_4X4_PRED<1>:w r[PBWDCOPY_4]<4,2>:w RETURN_1 // Mode 6 INTRA_4X4_HOR_DOWN: // Set inverse shift count shl (4) REF_TMP<1>:ud REF_LEFT_D(0)REGION(1,0) INV_SHIFT<4;4,1>:b mov (8) INTRA_REF.4<1>:ub REF_TOP(0,-1)REGION(8,1) // INTRA_REF holds all reference data mov (4) INTRA_REF<1>:ub REF_TMP.3<16;4,4>:ub // Even pixels avg (8) PRED_YW(14)<1> INTRA_REF<8;8,1> INTRA_REF.1<8;8,1> // avg(p[y-1],p[y]) // Odd pixels add (8) acc0<1>:w INTRA_REF.2<8;8,1>:ub 2:w // p[y]+2 mac (8) acc0<1>:w INTRA_REF.1<8;8,1>:ub 2:w // 2*p[y-1]+p[y]+2 mac (8) REF_TMP<1>:w INTRA_REF.0<8;8,1>:ub 1:w // p[y-2]+2*p[y-1]+p[y]+2 shr (4) INTRA_REF.1<2>:w REF_TMP<4;4,1>:w 2:w // (p[y-2]+2*p[y-1]+p[y]+2)>>2 shr (2) INTRA_REF.8<1>:w REF_TMP.4<2;2,1>:w 2:w // Keep zVR = -2,-3 unchanged mov (4) INTRA_REF.0<2>:w PRED_YW(14)REGION(4,1) // Combining even pixels shl (4) PBWDCOPY_4<1>:w INV_TRANS4<4;4,1>:b 1:w // Convert to WORD offset add (4) PBWDCOPY_4<1>:w PBWDCOPY_4<4;4,1>:w INTRA_TEMP_2*GRFWIB:w // Must match with INTRA_REF mov (16) REG_INTRA_4X4_PRED<1>:w r[PBWDCOPY_4]<4,1>:w RETURN_1 // Mode 7 INTRA_4X4_VERT_LEFT: // Even rows avg (8) PRED_YW(14)<2> REF_TOP(0)REGION(8,1) REF_TOP(0,1)REGION(8,1) // avg(p[x],p[x+1]) // Odd rows add (8) acc0<1>:w REF_TOP(0,2)REGION(8,1) 2:w // p[x+2]+2 mac (8) acc0<1>:w REF_TOP(0,1)REGION(8,1) 2:w // 2*p[x+1]+p[x+2]+2 mac (8) PRED_YW(15)<1> REF_TOP(0)REGION(8,1) 1:w // p[x]+2*p[x+1]+p[x+2]+2 shr (8) PRED_YW(14,1)<2> PRED_YW(15)REGION(8,1) 2:w mov (16) REG_INTRA_4X4_PRED<1>:w PRED_YW(14)<1;4,2> RETURN_1 // Mode 8 INTRA_4X4_HOR_UP: // Set extra left reference pixels for unified prediction mov (8) REF_LEFT(0,4)<1> REF_LEFT(0,3)REGION(1,0) // Copy p[-1,3] to p[-1,y],y=4...7 // Even pixels avg (8) PRED_YW(14)<2> REF_LEFT(0)REGION(8,1) REF_LEFT(0,1)REGION(8,1) // avg(p[y],p[y+1]) // Odd pixels add (8) acc0<1>:w REF_LEFT(0,2)REGION(8,1) 2:w // p[y+2]+2 mac (8) acc0<1>:w REF_LEFT(0,1)REGION(8,1) 2:w // 2*p[y+1]+p[y+2]+2 mac (8) PRED_YW(15)<1> REF_LEFT(0)REGION(8,1) 1:w // p[y]+2*p[y+1]+p[y+2]+2 shr (8) PRED_YW(14,1)<2> PRED_YW(15)REGION(8,1) 2:w // (p[y]+2*p[y+1]+p[y+2]+2)>>2 mov (16) REG_INTRA_4X4_PRED<1>:w PRED_YW(14)<2;4,1> RETURN_1 // End of intra_Pred_4x4_Y_4 #endif // !defined(__INTRA_PRED_4X4_Y_4__) intel-driver-1.3.0/src/shaders/h264/mc/intra_Pred_8x8_Y.asm000066400000000000000000000236031231401140700232060ustar00rootroot00000000000000/* * Intra predict 8X8 luma block * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__INTRA_PRED_8X8_Y__) // Make sure this is only included once #define __INTRA_PRED_8X8_Y__ // Module name: intra_Pred_8X8_Y.asm // // Intra predict 8X8 luma block // //-------------------------------------------------------------------------- // Input data: // // REF_TOP: Top reference data stored in BYTE with p[-1,-1] at REF_TOP(0,-1), p[-1,-1] and [15,-1] adjusted // REF_LEFT: Left reference data stored in BYTE with p[-1,0] at REF_LEFT(0,2), REF_LEFT(0,1) (p[-1,-1]) adjusted // PRED_MODE: Intra prediction mode stored in 4 LSBs // INTRA_PRED_AVAIL: Top/Left available flag, (Bit0: Left, Bit1: Top) // // Output data: // // REG_INTRA_8X8_PRED: Predicted 8X8 block data //-------------------------------------------------------------------------- #define INTRA_REF REG_INTRA_TEMP_1 #define REF_TMP REG_INTRA_TEMP_2 intra_Pred_8x8_Y: // Reference sample filtering // // Set up boundary pixels for unified filtering mov (1) REF_TOP(0,16)<1> REF_TOP(0,15)REGION(1,0) // p[16,-1] = p[15,-1] mov (8) REF_LEFT(0,2+8)<1> REF_LEFT(0,2+7)REGION(1,0) // p[-1,8] = p[-1,7] // Top reference sample filtering (!!Consider instruction compression later) add (16) acc0<1>:w REF_TOP(0,-1)REGION(16,1) 2:w // p[x-1,-1]+2 mac (16) acc0<1>:w REF_TOP(0)REGION(16,1) 2:w // p[x-1,-1]+2*p[x,-1]+2 mac (16) acc0<1>:w REF_TOP(0,1)REGION(16,1) 1:w // p[x-1,-1]+2*p[x,-1]+p[x+1,-1]+2 shr (16) REF_TMP<1>:w acc0:w 2:w // (p[x-1,-1]+2*p[x,-1]+p[x+1,-1]+2)>>2 // Left reference sample filtering add (16) acc0<1>:w REF_LEFT(0)REGION(16,1) 2:w // p[-1,y-1]+2 mac (16) acc0<1>:w REF_LEFT(0,1)REGION(16,1) 2:w // p[-1,y-1]+2*p[-1,y]+2 mac (16) acc0<1>:w REF_LEFT(0,2)REGION(16,1) 1:w // p[-1,y-1]+2*p[-1,y]+p[-1,y+1]+2 shr (16) INTRA_REF<1>:w acc0:w 2:w // (p[-1,y-1]+2*p[-1,y]+p[-1,y+1]+2)>>2 // Re-assign filtered reference samples mov (16) REF_TOP(0)<1> REF_TMP<32;16,2>:ub // p'[x,-1], x=0...15 mov (8) REF_LEFT(0)<1> INTRA_REF.2<16;8,2>:ub // p'[-1,y], y=0...7 mov (1) REF_TOP(0,-1)<1> INTRA_REF<0;1,0>:ub // p'[-1,-1] // Select intra_8x8 prediction mode // and (1) PINTRAPRED_Y<1>:w PRED_MODE<0;1,0>:w 0x0F:w // WA for "jmpi" restriction mov (1) REG_INTRA_TEMP_1<1>:ud r[PINTRAPRED_Y, INTRA_8X8_OFFSET]:ub jmpi (1) REG_INTRA_TEMP_1<0;1,0>:d // Mode 0 #define PTMP a0.6 #define PTMP_D a0.3 INTRA_8X8_VERTICAL: $for(0,0; <4; 1,32) { add.sat (16) r[PPREDBUF_Y,%2]<2>:ub r[PERROR,%2]<16;16,1>:w REF_TOP(0)<0;8,1> } RETURN // Mode 1 INTRA_8X8_HORIZONTAL: $for(0,0; <8; 2,32) { add.sat (16) r[PPREDBUF_Y,%2]<2>:ub r[PERROR,%2]<16;16,1>:w REF_LEFT(0,%1)<1;8,0> } RETURN // Mode 2 INTRA_8X8_DC: // Rearrange reference samples for unified DC prediction code // and.nz.f0.0 (16) NULLREG INTRA_PRED_AVAIL<0;1,0>:w 2:w // Top macroblock available for intra prediction? and.nz.f0.1 (8) NULLREG INTRA_PRED_AVAIL<0;1,0>:w 1:w // Left macroblock available for intra prediction? (-f0.0.any16h) mov (16) REF_TOP_W(0)<1> 0x8080:uw (-f0.1.any8h) mov (8) REF_LEFT(0)<1> REF_TOP(0)REGION(8,1) (-f0.0.any8h) mov (8) REF_TOP(0)<1> REF_LEFT(0)REGION(8,1) // Perform DC prediction // add (8) PRED_YW(15)<1> REF_TOP(0)REGION(8,1) REF_LEFT(0)REGION(8,1) add (4) PRED_YW(15)<1> PRED_YW(15)REGION(4,1) PRED_YW(15,4)REGION(4,1) add (2) PRED_YW(15)<1> PRED_YW(15)REGION(2,1) PRED_YW(15,2)REGION(2,1) add (16) acc0<1>:w PRED_YW(15)REGION(1,0) PRED_YW(15,1)REGION(1,0) add (16) acc0<1>:w acc0:w 8:w shr (16) REG_INTRA_TEMP_0<1>:w acc0:w 4:w // Add error block $for(0,0; <4; 1,32) { add.sat (16) r[PPREDBUF_Y,%2]<2>:ub r[PERROR,%2]<16;16,1>:w REG_INTRA_TEMP_0<16;16,1>:w } RETURN // Mode 3 INTRA_8X8_DIAG_DOWN_LEFT: mov (8) REF_TOP(0,16)<1> REF_TOP(0,15)REGION(8,1) // p[16,-1] = p[15,-1] add (16) acc0<1>:w REF_TOP(0,2)REGION(16,1) 2:w // p[x+2]+2 mac (16) acc0<1>:w REF_TOP(0,1)REGION(16,1) 2:w // 2*p[x+1]+p[x+2]+2 mac (16) acc0<1>:w REF_TOP(0)REGION(16,1) 1:w // p[x]+2*p[x+1]+p[x+2]+2 shr (16) REG_INTRA_TEMP_0<1>:w acc0<16;16,1>:w 2:w // (p[x]+2*p[x+1]+p[x+2]+2)>>2 // Add error block $for(0,0; <8; 2,32) { add.sat (16) r[PPREDBUF_Y,%2]<2>:ub r[PERROR,%2]<16;16,1>:w REG_INTRA_TEMP_0.%1<1;8,1>:w } RETURN // Mode 4 INTRA_8X8_DIAG_DOWN_RIGHT: #define INTRA_REF REG_INTRA_TEMP_1 #define REF_TMP REG_INTRA_TEMP_2 // Set inverse shift count shl (4) REF_TMP<1>:ud REF_LEFT_D(0,1)REGION(1,0) INV_SHIFT<4;4,1>:b // Reverse order bottom 4 pixels of left ref. shl (4) REF_TMP.4<1>:ud REF_LEFT_D(0)REGION(1,0) INV_SHIFT<4;4,1>:b // Reverse order top 4 pixels of left ref. mov (8) INTRA_REF<1>:ub REF_TMP.3<32;8,4>:ub mov (16) INTRA_REF.8<1>:ub REF_TOP(0,-1)REGION(16,1) // INTRA_REF holds all reference data add (16) acc0<1>:w INTRA_REF.2<16;16,1>:ub 2:w // p[x+2]+2 mac (16) acc0<1>:w INTRA_REF.1<16;16,1>:ub 2:w // 2*p[x+1]+p[x+2]+2 mac (16) acc0<1>:w INTRA_REF<16;16,1>:ub 1:w // p[x]+2*p[x+1]+p[x+2]+2 shr (16) INTRA_REF<1>:w acc0<16;16,1>:w 2:w // (p[x]+2*p[x+1]+p[x+2]+2)>>2 // Store data in reversed order add (2) PBWDCOPY_8<1>:w INV_TRANS48<2;2,1>:b INTRA_TEMP_1*GRFWIB:w // Must match with INTRA_REF // Add error block $for(0,96; <8; 2,-32) { add.sat (16) r[PPREDBUF_Y,%2]<2>:ub r[PBWDCOPY_8,%1*2]<8,1>:w r[PERROR,%2]<16;16,1>:w } RETURN // Mode 5 INTRA_8X8_VERT_RIGHT: #define INTRA_REF REG_INTRA_TEMP_1 #define REF_TMP REG_INTRA_TEMP_2 #define REF_TMP1 REG_INTRA_TEMP_3 // Set inverse shift count shl (4) REF_TMP<1>:ud REF_LEFT_D(0,1)REGION(1,0) INV_SHIFT<4;4,1>:b // Reverse order bottom 4 pixels of left ref. shl (4) REF_TMP.4<1>:ud REF_LEFT_D(0)REGION(1,0) INV_SHIFT<4;4,1>:b // Reverse order top 4 pixels of left ref. mov (8) INTRA_REF<1>:ub REF_TMP.3<32;8,4>:ub mov (16) INTRA_REF.8<1>:ub REF_TOP(0,-1)REGION(16,1) // INTRA_REF holds all reference data // Even rows avg (16) PRED_YW(14)<1> INTRA_REF.8<16;16,1> INTRA_REF.9<16;16,1> // avg(p[x-1],p[x]) // Odd rows add (16) acc0<1>:w INTRA_REF.3<16;16,1>:ub 2:w // p[x]+2 mac (16) acc0<1>:w INTRA_REF.2<16;16,1>:ub 2:w // 2*p[x-1]+p[x]+2 mac (16) acc0<1>:w INTRA_REF.1<16;16,1>:ub 1:w // p[x-2]+2*p[x-1]+p[x]+2 shr (16) REF_TMP<1>:w acc0:w 2:w // (p[x-2]+2*p[x-1]+p[x]+2)>>2 mov (8) INTRA_REF<1>:ub REF_TMP<16;8,2>:ub // Keep zVR = -1,-2,-3,-4,-5,-6,-7 sequencially mov (8) INTRA_REF.6<2>:ub REF_TMP.12<16;8,2>:ub // Keep zVR = -1,1,3,5,7,9,11,13 at even byte mov (8) INTRA_REF.7<2>:ub PRED_Y(14)REGION(8,2) // Combining zVR = 0,2,4,6,8,10,12,14 at odd byte add (2) PBWDCOPY_8<1>:w INV_TRANS8<2;2,1>:b INTRA_TEMP_1*GRFWIB:w // Must match with INTRA_REF // Add error block $for(0,96; <8; 2,-32) { add.sat (16) r[PPREDBUF_Y,%2]<2>:ub r[PBWDCOPY_8,%1]<8,2>:ub r[PERROR,%2]<16;16,1>:w } RETURN // Mode 6 INTRA_8X8_HOR_DOWN: // Set inverse shift count shl (4) REF_TMP<1>:ud REF_LEFT_D(0,1)REGION(1,0) INV_SHIFT<4;4,1>:b // Reverse order bottom 4 pixels of left ref. shl (4) REF_TMP.4<1>:ud REF_LEFT_D(0)REGION(1,0) INV_SHIFT<4;4,1>:b // Reverse order top 4 pixels of left ref. mov (8) INTRA_REF<1>:ub REF_TMP.3<16;4,4>:ub mov (16) INTRA_REF.8<1>:ub REF_TOP(0,-1)REGION(16,1) // INTRA_REF holds all reference data // Odd pixels add (16) acc0<1>:w INTRA_REF.2<16;16,1>:ub 2:w // p[y]+2 mac (16) acc0<1>:w INTRA_REF.1<16;16,1>:ub 2:w // 2*p[y-1]+p[y]+2 mac (16) acc0<1>:w INTRA_REF.0<16;16,1>:ub 1:w // p[y-2]+2*p[y-1]+p[y]+2 shr (16) PRED_YW(14)<1> acc0:w 2:w // (p[y-2]+2*p[y-1]+p[y]+2)>>2 // Even pixels avg (16) INTRA_REF<1>:w INTRA_REF<16;16,1>:ub INTRA_REF.1<16;16,1>:ub // avg(p[y-1],p[y]) mov (8) INTRA_REF.1<2>:ub PRED_Y(14)REGION(8,2) // Combining odd pixels to form byte type mov (8) INTRA_REF.16<1>:ub PRED_Y(14,16)REGION(8,2) // Keep zVR = -2,-3,-4,-5,-6,-7 unchanged // Now INTRA_REF.0 - INTRA_REF.21 contain predicted data add (2) PBWDCOPY_8<1>:w INV_TRANS48<2;2,1>:b INTRA_TEMP_1*GRFWIB:w // Must match with INTRA_REF // Add error block $for(0,96; <13; 4,-32) { add.sat (16) r[PPREDBUF_Y,%2]<2>:ub r[PBWDCOPY_8,%1]<8,1>:ub r[PERROR,%2]<16;16,1>:w } RETURN // Mode 7 INTRA_8X8_VERT_LEFT: // Even rows avg (16) PRED_YW(14)<1> REF_TOP(0)REGION(16,1) REF_TOP(0,1)REGION(16,1) // avg(p[x],p[x+1]) // Odd rows add (16) acc0<1>:w REF_TOP(0,2)REGION(16,1) 2:w // p[x+2]+2 mac (16) acc0<1>:w REF_TOP(0,1)REGION(16,1) 2:w // 2*p[x+1]+p[x+2]+2 mac (16) acc0<1>:w REF_TOP(0)REGION(16,1) 1:w // p[x]+2*p[x+1]+p[x+2]+2 shr (16) PRED_YW(15)<1> acc0<1;8,1>:w 2:w // (p[x]+2*p[x+1]+p[x+2]+2)>>2 // Add error block $for(0,0; <4; 1,32) { add.sat (16) r[PPREDBUF_Y,%2]<2>:ub PRED_YW(14,%1)<16;8,1> r[PERROR,%2]<16;16,1>:w } RETURN // Mode 8 INTRA_8X8_HOR_UP: // Set extra left reference pixels for unified prediction mov (8) REF_LEFT(0,8)<1> REF_LEFT(0,7)REGION(1,0) // Copy p[-1,7] to p[-1,y],y=8...15 // Even pixels avg (16) PRED_YW(14)<1> REF_LEFT(0)REGION(16,1) REF_LEFT(0,1)REGION(16,1) // avg(p[y],p[y+1]) // Odd pixels add (16) acc0<1>:w REF_LEFT(0,2)REGION(16,1) 2:w // p[y+2]+2 mac (16) acc0<1>:w REF_LEFT(0,1)REGION(16,1) 2:w // 2*p[y+1]+p[y+2]+2 mac (16) acc0<1>:w REF_LEFT(0)REGION(16,1) 1:w // p[y]+2*p[y+1]+p[y+2]+2 shr (16) PRED_YW(15)<1> acc0<1;8,1>:w 2:w // (p[y]+2*p[y+1]+p[y+2]+2)>>2 // Merge even/odd pixels // The predicted data need to be stored in byte type (22 bytes are required) mov (16) PRED_Y(14,1)<2> PRED_Y(15)REGION(16,2) // Add error block $for(0,0; <4; 1,32) { add.sat (16) r[PPREDBUF_Y,%2]<2>:ub PRED_Y(14,%1*4)<2;8,1> r[PERROR,%2]<16;16,1>:w } RETURN // End of intra_Pred_8X8_Y #endif // !defined(__INTRA_PRED_8X8_Y__) intel-driver-1.3.0/src/shaders/h264/mc/intra_Pred_Chroma.asm000066400000000000000000000154111231401140700234760ustar00rootroot00000000000000/* * Intra predict 8x8 chroma block * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__INTRA_PRED_CHROMA__) // Make sure this is only included once #define __INTRA_PRED_CHROMA__ // Module name: intra_Pred_Chroma.asm // // Intra predict 8x8 chroma block // shr (1) PINTRAPRED_UV<1>:w REG_INTRA_CHROMA_PRED_MODE<0;1,0>:ub INTRA_CHROMA_PRED_MODE_SHIFT:w // Bits 1:0 = intra chroma pred mode // WA for "jmpi" restriction mov (1) REG_INTRA_TEMP_1<1>:d r[PINTRAPRED_UV, INTRA_CHROMA_OFFSET]:b jmpi (1) REG_INTRA_TEMP_1<0;1,0>:d // Mode 0 INTRA_CHROMA_DC: and.nz.f0.0 (8) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_UP_AVAIL_FLAG:ud // Top macroblock available for intra prediction? // Calculate DC values for sub-block 0 and 3 // // Rearrange reference samples for unified DC prediction code // Need to check INTRA_PRED_LEFT_TH_AVAIL_FLAG for blk0 and INTRA_PRED_LEFT_BH_AVAIL_FLAG for blk3 // (-f0.0.any8h) mov (8) INTRA_REF_TOP_W(0)<1> 0x8080:uw // Up not available and.nz.f0.1 (4) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_LEFT_TH_AVAIL_FLAG:ud (-f0.1.any4h) mov (4) INTRA_REF_LEFT_W(0)<2> INTRA_REF_TOP_W(0)REGION(4,1) // Left top half macroblock not available for intra prediction and.nz.f0.1 (4) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_LEFT_BH_AVAIL_FLAG:ud (-f0.1.any4h) mov (4) INTRA_REF_LEFT_W(0,8)<2> INTRA_REF_TOP_W(0,4)REGION(4,1) // Left bottom half macroblock not available for intra prediction (-f0.0.any8h) mov (8) INTRA_REF_TOP_W(0)<1> INTRA_REF_LEFT_W(0)REGION(8,2) // Up not available // Calculate DC prediction // add (16) PRED_UVW(0)<1> INTRA_REF_TOP(0)REGION(16,1) INTRA_REF_LEFT_UV(0)<4;2,1> // Sum of top and left reference add (8) PRED_UVW(0)<1> PRED_UVW(0)<4;2,1> PRED_UVW(0,2)<4;2,1> // Sum of first half (blk #0) and second half (blk #3) add (8) PRED_UVW(9)<1> PRED_UVW(0)<0;2,1> PRED_UVW(0,2)<0;2,1> // Sum of blk #0 add (8) PRED_UVW(11,8)<1> PRED_UVW(0,4)<0;2,1> PRED_UVW(0,6)<0;2,1> // Sum of blk #3 // Calculate DC values for sub-block 1 and 2 // // Rearrange reference samples for unified DC prediction code // // Blk #2 (-f0.0.any4h) mov (4) INTRA_REF_TOP_W(0)<1> 0x8080:uw (f0.1.any4h) mov (4) INTRA_REF_TOP_W(0)<1> INTRA_REF_LEFT_W(0,8)REGION(4,2) // Always use available left reference (-f0.1.any4h) mov (4) INTRA_REF_LEFT_W(0,8)<2> INTRA_REF_TOP_W(0)REGION(4,1) // Blk #1 and.nz.f0.1 (4) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_LEFT_TH_AVAIL_FLAG:ud (-f0.1.any4h) mov (4) INTRA_REF_LEFT_W(0)<2> 0x8080:uw (f0.0.any4h) mov (4) INTRA_REF_LEFT_W(0)<2> INTRA_REF_TOP_W(0,4)REGION(4,1) // Always use available top reference (-f0.0.any4h) mov (4) INTRA_REF_TOP_W(0,4)<1> INTRA_REF_LEFT_W(0)REGION(4,2) // Calculate DC prediction // add (8) PRED_UVW(0)<1> INTRA_REF_TOP(0)REGION(8,1) INTRA_REF_LEFT_UV(0,16)<4;2,1> // Sum of top and left reference for blk #2 add (8) PRED_UVW(0,8)<1> INTRA_REF_LEFT_UV(0)<4;2,1> INTRA_REF_TOP(0,8)REGION(8,1) // Sum of top and left reference for blk #1 add (8) PRED_UVW(0)<1> PRED_UVW(0)<4;2,1> PRED_UVW(0,2)<4;2,1> // Sum of first half (blk #2) and second half (blk #1) add (8) PRED_UVW(9,8)<1> PRED_UVW(0,4)<0;2,1> PRED_UVW(0,6)<0;2,1> // Sum of blk #1 add (8) PRED_UVW(11)<1> PRED_UVW(0)<0;2,1> PRED_UVW(0,2)<0;2,1> // Sum of blk #2 // Now, PRED_UVW(9) holds sums for blks #0 and #1 and PRED_UVW(11) holds sums for blks #2 and #3 // add (32) acc0<1>:w PRED_UVW(9)REGION(16,1) 4:w {Compr} // Add rounder $for(0; <4; 2) { shr (32) PRED_UVW(%1)<1> acc0:w 3:w {Compr} } add (32) acc0<1>:w PRED_UVW(11)REGION(16,1) 4:w {Compr} // Add rounder $for(4; <8; 2) { shr (32) PRED_UVW(%1)<1> acc0:w 3:w {Compr} } jmpi (1) End_of_intra_Pred_Chroma // Mode 1 INTRA_CHROMA_HORIZONTAL: mov (1) PREF_LEFT_UD<1>:ud INTRA_REF_LEFT_ID*GRFWIB*0x00010001+0x00040000:ud // Set address registers for instruction compression $for(0,0; <8; 2,8) { mov (32) PRED_UVW(%1)<1> r[PREF_LEFT,%2+2]<0;2,1>:ub {Compr} // Actual left column reference data start at offset 2 } jmpi (1) End_of_intra_Pred_Chroma // Mode 2 INTRA_CHROMA_VERTICAL: $for(0; <8; 2) { mov (32) PRED_UVW(%1)<1> INTRA_REF_TOP(0) {Compr} } jmpi (1) End_of_intra_Pred_Chroma // Mode 3 INTRA_Chroma_PLANE: // Refer to H.264/AVC spec Section 8.3.4.4 #undef C #define A REG_INTRA_TEMP_2.0 // All are WORD type #define B REG_INTRA_TEMP_3.0 // B[U] & B[V] #define C REG_INTRA_TEMP_3.2 // C[U] & C[V] #define YP REG_INTRA_TEMP_0 // Store intermediate results of c*(y-3). Make sure it's an even GRF #define YP1 REG_INTRA_TEMP_1 // Store intermediate results of c*(y-3). Make sure it's an odd GRF #define XP REG_INTRA_TEMP_5 // Store intermediate results of a+b*(x-3)+16. Make sure it's an odd GRF // First Calculate constants H and V // H1 = sum((x'+1)*p[4+x',-1]), x'=0,1,2,3 // H2 = sum((-x'-1)*p[2-x',-1]), x'=3,2,1,0 // H = H1 + H2 // The same calculation holds for V // mul (8) H1(0)<1> INTRA_REF_TOP(0,8)REGION(8,1) 0x44332211:v mul (8) H2(0)<1> INTRA_REF_TOP(0,-2)REGION(8,1) 0xFFEEDDCC:v mul (8) V1(0)<1> INTRA_REF_LEFT_UV(0,4*4)<4;2,1> 0x44332211:v mul (8) V2(0)<1> INTRA_REF_LEFT_UV(0)<4;2,1> 0x00FFEEDD:v mul (2) V2(0,6)<1> INTRA_REF_TOP(0,-2)REGION(2,1) -4:w // Replace 0*p[-1,3] with -4*p[-1,-1] // Now, REG_INTRA_TEMP_0 holds [H2, H1] and REG_INTRA_TEMP_1 holds [V2, V1] // Sum up [H2, H1] and [V2, V1] using instruction compression // ExecSize = 16 is restricted by B-spec for instruction compression // Actual intermediate results are in lower sub-registers after each summing step add (16) H1(0)<1> H1(0) H2(0) {Compr} // Results in lower 8 WORDs add (16) H1(0)<1> H1(0) H1(0,4) {Compr} // Results in lower 4 WORDs add (16) H1(0)<1> H1(0) H1(0,2) {Compr} // Results in lower 2 WORDs // Calculate a, b, c and further derivations mov (16) acc0<1>:w 32:w mac (4) acc0<1>:w H1(0)<16;2,1> 34:w shr (4) B<1>:w acc0:w 6:w // Done b,c mov (16) acc0<1>:w 16:w mac (16) acc0<1>:w INTRA_REF_TOP(0,7*2)<0;2,1> 16:w mac (16) A<1>:w INTRA_REF_LEFT_UV(0,7*4)<0;2,1> 16:w // A = a+16 mac (16) XP<1>:w B<0;2,1>:w XY_3<1;2,0>:b // XP = A+b*(x-3) mul (8) YP<1>:w C<0;2,1>:w XY_3<2;2,0>:b // YP = c*(y-3), Even portion mul (8) YP1<1>:w C<0;2,1>:w XY_3_1<2;2,0>:b // YP = c*(y-3), Odd portion // Finally the intra_Chroma plane prediction $for(0; <8; 2) { add (32) acc0<1>:w XP<16;16,1>:w YP.%1<0;2,1>:w {Compr} shr.sat (32) PRED_UV(%1)<2> acc0<16;16,1>:w 5:w {Compr} } End_of_intra_Pred_Chroma: // End of intra_Pred_Chroma #endif // !defined(__INTRA_PRED_CHROMA__) intel-driver-1.3.0/src/shaders/h264/mc/intra_pred_16x16_Y.asm000066400000000000000000000117411231401140700234040ustar00rootroot00000000000000/* * Intra predict 16x16 luma block * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: intra_Pred_16x16_Y.asm // // Intra predict 16x16 luma block // and (1) PINTRAPRED_Y<1>:w INTRA_PRED_MODE(0)REGION(1,0) 0x0F:w // WA for "jmpi" restriction mov (1) REG_INTRA_TEMP_1<1>:ud r[PINTRAPRED_Y, INTRA_16X16_OFFSET]:ub jmpi (1) REG_INTRA_TEMP_1<0;1,0>:d // Mode 0 INTRA_16x16_VERTICAL: $for(0; <16; 2) { mov (32) PRED_YW(%1)<1> INTRA_REF_TOP(0) {Compr} } jmpi (1) End_intra_Pred_16x16_Y // Mode 1 INTRA_16x16_HORIZONTAL: mov (1) PREF_LEFT_UD<1>:ud INTRA_REF_LEFT_ID*GRFWIB*0x00010001+0x00040000:ud // Set address registers for instruction compression $for(0,0; <16; 2,8) { mov (32) PRED_YW(%1)<1> r[PREF_LEFT,%2+3]<0;1,0>:ub {Compr} // Actual left column reference data start at offset 3 } jmpi (1) End_intra_Pred_16x16_Y // Mode 2 INTRA_16x16_DC: and.nz.f0.0 (8) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_UP_AVAIL_FLAG:ud // Top macroblock available for intra prediction? and (8) acc0<1>:ud REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_LEFT_TH_AVAIL_FLAG+INTRA_PRED_LEFT_BH_AVAIL_FLAG:ud // Left macroblock available for intra prediction? xor.z.f0.1 (8) NULLREG acc0:ud INTRA_PRED_LEFT_TH_AVAIL_FLAG+INTRA_PRED_LEFT_BH_AVAIL_FLAG:ud // Left macroblock available for intra prediction? // Rearrange reference samples for unified DC prediction code // (-f0.0.any8h) mov (8) INTRA_REF_TOP_W(0)<1> 0x8080:uw (-f0.1.any8h) mov (8) INTRA_REF_LEFT(0)<4> INTRA_REF_TOP(0)REGION(8,1) (-f0.1.any8h) mov (8) INTRA_REF_LEFT(1)<4> INTRA_REF_TOP(0,8)REGION(8,1) (-f0.0.any8h) mov (8) INTRA_REF_TOP(0)<1> INTRA_REF_LEFT(0)REGION(8,4) (-f0.0.any8h) mov (8) INTRA_REF_TOP(0,8)<1> INTRA_REF_LEFT(1)REGION(8,4) // Split due to HW limitation // Perform DC prediction // add (16) PRED_YW(15)<1> INTRA_REF_LEFT(0)REGION(8,4) INTRA_REF_TOP(0)REGION(16,1) add (8) PRED_YW(15)<1> PRED_YW(15)REGION(8,1) PRED_YW(15,8)REGION(8,1) add (4) PRED_YW(15)<1> PRED_YW(15)REGION(4,1) PRED_YW(15,4)REGION(4,1) add (2) PRED_YW(15)<1> PRED_YW(15)REGION(2,1) PRED_YW(15,2)REGION(2,1) add (32) acc0<1>:w PRED_YW(15)REGION(1,0) PRED_YW(15,1)REGION(1,0) {Compr} // Set up both acc0 and acc1 add (32) acc0<1>:w acc0:w 16:w {Compr} $for(0; <16; 2) { shr (32) PRED_YW(%1)<1> acc0:w 5:w {Compr} } jmpi (1) End_intra_Pred_16x16_Y // Mode 3 INTRA_16x16_PLANE: // Refer to H.264/AVC spec Section 8.3.3.4 #define A REG_INTRA_TEMP_2.0 // All are WORD type #define B REG_INTRA_TEMP_3.0 #define C REG_INTRA_TEMP_3.1 #define YP REG_INTRA_TEMP_0 // Store intermediate results of c*(y-7). Make sure it's an even GRF #define YP1 REG_INTRA_TEMP_1 // Store intermediate results of c*(y-7). Make sure it's an odd GRF, used in {Comp} #define XP REG_INTRA_TEMP_5 // Store intermediate results of a+b*(x-7)+16. Make sure it's an odd GRF // First Calculate constants H and V // H1 = sum((-x'-1)*p[8+x',-1]), x'=0,1,...7 // H2 = sum((-x'-1)*p[6-x',-1]), x'=7,6,...0 // H = -H1 + H2 // The same calculation holds for V // mul (8) H1(0)<1> INTRA_REF_TOP(0,8)REGION(8,1) 0x89ABCDEF:v mul (8) H2(0)<1> INTRA_REF_TOP(0,-1)REGION(8,1) 0xFEDCBA98:v mul (8) V1(0)<1> INTRA_REF_LEFT(0,8*4)REGION(8,4) 0x89ABCDEF:v mul (8) V2(0)<1> INTRA_REF_LEFT(0)REGION(8,4) 0x0FEDCBA9:v mul (1) V2(0,7)<1> INTRA_REF_TOP(0,-1)<0;1,0> -8:w // Replace 0*p[-1,7] with -8*p[-1,-1] // Now, REG_INTRA_TEMP_0 holds [H2, -H1] and REG_INTRA_TEMP_1 holds [V2, -V1] // Sum up [H2, -H1] and [V2, -V1] using instruction compression // ExecSize = 16 is restricted by B-spec for instruction compression // Actual intermediate results are in lower sub-registers after each summing step add (16) H1(0)<1> -H1(0) H2(0) {Compr} // Results in lower 8 WORDs add (16) H1(0)<1> H1(0) H1(0,4) {Compr} // Results in lower 4 WORDs add (16) H1(0)<1> H1(0) H1(0,2) {Compr} // Results in lower 2 WORDs add (16) H1(0)<1> H1(0) H1(0,1) {Compr} // Results in lower 1 WORD // Calculate a, b, c and further derivations mov (16) acc0<1>:w 32:w mac (2) acc0<1>:w H1(0)<16;1,0> 5:w shr (2) B<1>:w acc0:w 6:w // Done b,c mov (16) acc0<1>:w 16:w mac (16) acc0<1>:w INTRA_REF_TOP(0,15)<0;1,0> 16:w mac (16) A<1>:w INTRA_REF_LEFT(0,15*4)<0;1,0> 16:w // A = a+16 mac (16) XP<1>:w B<0;1,0>:w XY_7<16;16,1>:b // XP = A+b*(x-7) mul (8) YP<1>:w C<0;1,0>:w XY_7<16;8,2>:b // YP = c*(y-7), even portion mul (8) YP1<1>:w C<0;1,0>:w XY_7_1<16;8,2>:b // YP = c*(y-7), odd portion // Finally the intra_16x16 plane prediction $for(0,0; <16; 2,1) { add (32) acc0<1>:w XP<16;16,1>:w YP.%2<16;16,0>:w {Compr} // Set Width!= 1 to trick EU to use YP_1.%2 for 2nd instruction shr.sat (32) PRED_Y(%1)<2> acc0<16;16,1>:w 5:w {Compr} } End_intra_Pred_16x16_Y: // End of intra_Pred_16x16_Y intel-driver-1.3.0/src/shaders/h264/mc/list000066400000000000000000000006731231401140700203160ustar00rootroot00000000000000INTRA_16x16 INTRA_8x8 INTRA_4x4 INTRA_PCM FRAME_MB FIELD_MB MBAFF_MB SETHWSCOREBOARD SETHWSCOREBOARD_MBAFF AVC_ILDB_ROOT_Y_ILDB_FRAME AVC_ILDB_CHILD_Y_ILDB_FRAME AVC_ILDB_ROOT_UV_ILDB_FRAME AVC_ILDB_CHILD_UV_ILDB_FRAME AVC_ILDB_ROOT_Y_ILDB_FIELD AVC_ILDB_CHILD_Y_ILDB_FIELD AVC_ILDB_ROOT_UV_ILDB_FIELD AVC_ILDB_CHILD_UV_ILDB_FIELD AVC_ILDB_ROOT_Y_ILDB_MBAFF AVC_ILDB_CHILD_Y_ILDB_MBAFF AVC_ILDB_ROOT_UV_ILDB_MBAFF AVC_ILDB_CHILD_UV_ILDB_MBAFF intel-driver-1.3.0/src/shaders/h264/mc/loadRef_C_10x5.asm000066400000000000000000000040121231401140700225040ustar00rootroot00000000000000/* * Load reference 10x5 area for chroma NV12 4x4 MC * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: LoadRef_C_10x5.asm // // Load reference 10x5 area for chroma NV12 4x4 MC //#if !defined(__LOADREF_C_10x5__) // Make sure this is only included once //#define __LOADREF_C_10x5__ #if 1 // Compute integer and fractional components of MV asr (2) gMVX_INT<1>:w r[pMV,0]<2;2,1>:w 0x03:w {NoDDClr} and (2) gMVX_FRACC<1>:w r[pMV,0]<2;2,1>:w 0x07:w {NoDDChk} // Check whether MVY is integer or.z.f0.0 (8) null:w gMVY_FRACC<0;1,0>:w 0:w // Compute top-left corner position to be loaded mov (2) gMSGSRC.0<1>:d gMVX_INT<2;2,1>:w shl (1) gMSGSRC.0:d gMSGSRC.0:d 1:w (f0.0) add (1) pMSGDSC:ud gMSGDSC_R:ud RESP_LEN(2)+nBI_LC_DIFF:ud (-f0.0) add (1) pMSGDSC:ud gMSGDSC_R:ud RESP_LEN(3)+nBI_LC_DIFF:ud // Read 16x5 pixels - TODO: Reading 12x5 instead of 16x5 took more time on CL. Why? (f0.0) mov (1) gMSGSRC.2:ud 0x00030009:ud //{NoDDChk} (-f0.0) mov (1) gMSGSRC.2:ud 0x00040009:ud //{NoDDChk} send (8) gudREFC(0)<1> mMSGHDRC gMSGSRC<8;8,1>:ud DAPREAD pMSGDSC:ud #else add (1) pMSGDSC:ud gMSGDSC_R:ud RESP_LEN(3)+nBI_LC_DIFF:ud // Compute integer and fractional components of MV asr (2) gMVX_INT<1>:w r[pMV,0]<2;2,1>:w 0x03:w {NoDDClr} and (2) gMVX_FRACC<1>:w r[pMV,0]<2;2,1>:w 0x07:w {NoDDChk} // Compute top-left corner position to be loaded mov (2) gMSGSRC.0<1>:d gMVX_INT<2;2,1>:w shl (1) gMSGSRC.0:d gMSGSRC.0:d 1:w // Read 16x5 pixels mov (1) gMSGSRC.2:ud 0x00040009:ud {NoDDChk} send (8) gudREFC(0)<1> mMSGHDRC gMSGSRC<8;8,1>:ud DAPREAD pMSGDSC:ud #endif //#endif // !defined(__LOADREF_C_10x5__) intel-driver-1.3.0/src/shaders/h264/mc/loadRef_C_6x3.asm000066400000000000000000000022741231401140700224370ustar00rootroot00000000000000/* * Load reference 6x3 area for chroma NV12 4x4 MC * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: LoadRef_C_6x3.asm // // Load reference 6x3 area for chroma NV12 4x4 MC //#if !defined(__LOADREF_C_6x3__) // Make sure this is only included once //#define __LOADREF_C_6x3__ #ifdef DEV_ILK add (1) pMSGDSC:ud gMSGDSC_R:ud 0x00100010:ud #else add (1) pMSGDSC:ud gMSGDSC_R:ud 0x00010010:ud #endif // DEV_ILK // Compute integer and fractional components of MV asr (2) gMVX_INT<1>:w r[pMV,0]<2;2,1>:w 0x03:w {NoDDClr} and (2) gMVX_FRACC<1>:w r[pMV,0]<2;2,1>:w 0x07:w {NoDDChk} // Compute top-left corner position to be loaded mov (2) gMSGSRC.0<1>:d gMVX_INT<2;2,1>:w shl (1) gMSGSRC.0:d gMSGSRC.0:d 1:w // Read 8x3 pixels mov (1) gMSGSRC.2:ud 0x00020005:ud send (8) gudREFC(0)<1> mMSGHDRC gMSGSRC<8;8,1>:ud DAPREAD pMSGDSC:ud //#endif // !defined(__LOADREF_C_6x3__) intel-driver-1.3.0/src/shaders/h264/mc/loadRef_Y_16x13.asm000066400000000000000000000106451231401140700226300ustar00rootroot00000000000000/* * Load reference 16x13 area for luma 8x8 MC * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: LoadRef_Y_16x13.asm // // Load reference 16x13 area for luma 8x8 MC //#if !defined(__LOADREF_Y_16x13__) // Make sure this is only included once //#define __LOADREF_Y_16x13__ #if 1 #if 1 // Check whether MVX is integer MV and.z.f0.0 (1) null:w r[pMV,0]<0;1,0>:w 0x3:w // Compute integer and fractional components of MV and (2) gMVX_FRAC<1>:w r[pMV,0]<2;2,1>:w 0x03:w //{NoDDClr} asr (2) gMVX_INT<1>:w r[pMV,0]<2;2,1>:w 0x02:w //{NoDDChk} // Check whether MVY is integer or.z.f0.1 (8) null:w gMVY_FRAC<0;1,0>:w 0:w // If MVX is a multiple of 4 (..., -4, 0, 4, ...) integer MV, do special handling (f0.0) jmpi (1) INTERLABEL(LOADREF_MVXZERO) // Set message descriptor (f0.1) add (1) pMSGDSC:ud gMSGDSC_R:ud RESP_LEN(4):ud (-f0.1) add (1) pMSGDSC:ud gMSGDSC_R:ud RESP_LEN(7):ud // Compute top-left corner position to be loaded // TODO: sel (-f0.1) add (2) gMSGSRC.0<1>:d gMVX_INT<2;2,1>:w -0x02:d //{NoDDClr} (-f0.1) mov (1) gMSGSRC.2:ud 0x000c000c:ud //{NoDDChk} (f0.1) add (1) gMSGSRC.0<1>:d gMVX_INT<0;1,0>:w -0x02:d //{NoDDClr} (f0.1) mov (1) gMSGSRC.1<1>:d gMVY_INT<0;1,0>:w //{NoDDChk,NoDDClr} (f0.1) mov (1) gMSGSRC.2:ud 0x0007000c:ud //{NoDDChk} // Read 16x13 pixels send (8) gudREF(0)<1> mMSGHDRY gMSGSRC<8;8,1>:ud DAPREAD pMSGDSC:ud jmpi INTERLABEL(EXIT_LOADREF_Y_16x13) INTERLABEL(LOADREF_MVXZERO): // Set message descriptor #ifdef DEV_ILK (f0.1) add (1) pMSGDSC:ud gMSGDSC_R:ud 0x00200000:ud (-f0.1) add (1) pMSGDSC:ud gMSGDSC_R:ud 0x00400000:ud #else (f0.1) add (1) pMSGDSC:ud gMSGDSC_R:ud 0x00020000:ud (-f0.1) add (1) pMSGDSC:ud gMSGDSC_R:ud 0x00040000:ud #endif // Compute top-left corner position to be loaded // TODO: sel mov (2) gMSGSRC.0<1>:d gMVX_INT<2;2,1>:w (-f0.1) add (1) gMSGSRC.1<1>:d gMVY_INT<0;1,0>:w -0x02:d (-f0.1) mov (1) gMSGSRC.2:ud 0x000c0007:ud //{NoDDChk} (f0.1) mov (1) gMSGSRC.2:ud 0x00070007:ud //{NoDDChk} // Read 16x13 pixels send (8) gudREF(0)<1> mMSGHDRY gMSGSRC<8;8,1>:ud DAPREAD pMSGDSC:ud #else // Compute integer and fractional components of MV and (2) gMVX_FRAC<1>:w r[pMV,0]<2;2,1>:w 0x03:w //{NoDDClr} asr (2) gMVX_INT<1>:w r[pMV,0]<2;2,1>:w 0x02:w //{NoDDChk} // Check whether MVY is integer or.z.f0.1 (8) null:w gMVY_FRAC<0;1,0>:w 0:w // Set message descriptor #ifdef DEV_ILK (f0.1) add (1) pMSGDSC:ud gMSGDSC_R:ud 0x00400000:ud (-f0.1) add (1) pMSGDSC:ud gMSGDSC_R:ud 0x00700000:ud #else (f0.1) add (1) pMSGDSC:ud gMSGDSC_R:ud 0x00040000:ud (-f0.1) add (1) pMSGDSC:ud gMSGDSC_R:ud 0x00070000:ud #endif // Compute top-left corner position to be loaded // TODO: sel (-f0.1) add (2) gMSGSRC.0<1>:d gMVX_INT<2;2,1>:w -0x02:d //{NoDDClr} (-f0.1) mov (1) gMSGSRC.2:ud 0x000c000c:ud //{NoDDChk} (f0.1) add (1) gMSGSRC.0<1>:d gMVX_INT<0;1,0>:w -0x02:d //{NoDDClr} (f0.1) mov (1) gMSGSRC.1<1>:d gMVY_INT<0;1,0>:w //{NoDDChk,NoDDClr} (f0.1) mov (1) gMSGSRC.2:ud 0x0007000c:ud //{NoDDChk} // Read 16x13 pixels send (8) gudREF(0)<1> mMSGHDRY gMSGSRC<8;8,1>:ud DAPREAD pMSGDSC:ud #endif #else // Compute integer and fractional components of MV and (2) gMVX_FRAC<1>:w r[pMV,0]<2;2,1>:w 0x03:w {NoDDClr} // asr (2) gMVX_INT<1>:w r[pMV,0]<2;2,1>:w 0x02:w {NoDDChk} // // Set message descriptor #ifdef DEV_ILK add (1) pMSGDSC:ud gMSGDSC_R:ud 0x00700000:ud #else add (1) pMSGDSC:ud gMSGDSC_R:ud 0x00070000:ud #endif // DEV_ILK // Compute top-left corner position to be loaded add (2) gMSGSRC.0<1>:d gMVX_INT<2;2,1>:w -0x02:d {NoDDClr} // mov (1) gMSGSRC.2:ud 0x000c000c:ud {NoDDChk} // // Read 16x13 pixels send (8) gudREF(0)<1> mMSGHDRY gMSGSRC<8;8,1>:ud DAPREAD pMSGDSC:ud #endif INTERLABEL(EXIT_LOADREF_Y_16x13): //#endif // !defined(__LOADREF_Y_16x13__) intel-driver-1.3.0/src/shaders/h264/mc/loadRef_Y_16x9.asm000066400000000000000000000041421231401140700225500ustar00rootroot00000000000000/* * Load reference 16x9 area for luma 4x4 MC * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: LoadRef_Y_16x9.asm // // Load reference 16x9 area for luma 4x4 MC //#if !defined(__LOADREF_Y_16x9__) // Make sure this is only included once //#define __LOADREF_Y_16x9__ #if 1 // Compute integer and fractional components of MV and (2) gMVX_FRAC<1>:w r[pMV,0]<2;2,1>:w 0x03:w //{NoDDClr} asr (2) gMVX_INT<1>:w r[pMV,0]<2;2,1>:w 0x02:w //{NoDDChk} // Check whether MVY is integer or.z.f0.1 (8) null:w gMVY_FRAC<0;1,0>:w 0:w // Set message descriptor (f0.1) add (1) pMSGDSC:ud gMSGDSC_R:ud RESP_LEN(2):ud (-f0.1) add (1) pMSGDSC:ud gMSGDSC_R:ud RESP_LEN(5):ud // Compute top-left corner position to be loaded // TODO: sel (-f0.1) add (2) gMSGSRC.0<1>:d gMVX_INT<2;2,1>:w -0x02:d //{NoDDClr} (-f0.1) mov (1) gMSGSRC.2:ud 0x00080008:ud //{NoDDChk} (f0.1) add (1) gMSGSRC.0<1>:d gMVX_INT<0;1,0>:w -0x02:d //{NoDDClr} (f0.1) mov (1) gMSGSRC.1<1>:d gMVY_INT<0;1,0>:w //{NoDDChk,NoDDClr} (f0.1) mov (1) gMSGSRC.2:ud 0x00030008:ud //{NoDDChk} // Read 16x9 pixels send (8) gudREF(0)<1> mMSGHDRY gMSGSRC<8;8,1>:ud DAPREAD pMSGDSC:ud #else // Compute integer and fractional components of MV and (2) gMVX_FRAC<1>:w r[pMV,0]<2;2,1>:w 0x03:w {NoDDClr} // asr (2) gMVX_INT<1>:w r[pMV,0]<2;2,1>:w 0x02:w {NoDDChk} // // Set message descriptor add (1) pMSGDSC:ud gMSGDSC_R:ud RESP_LEN(5):ud // Compute top-left corner position to be loaded add (2) gMSGSRC.0<1>:d gMVX_INT<2;2,1>:w -0x02:d {NoDDClr} // mov (1) gMSGSRC.2:ud 0x00080008:ud {NoDDChk} // // Read 16x9 pixels send (8) gudREF(0)<1> mMSGHDRY gMSGSRC<8;8,1>:ud DAPREAD pMSGDSC:ud #endif //#endif // !defined(__LOADREF_Y_16x9__) intel-driver-1.3.0/src/shaders/h264/mc/load_Intra_Ref_UV.asm000066400000000000000000000036341231401140700234040ustar00rootroot00000000000000/* * Load all reference U/V samples from neighboring macroblocks * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__LOAD_INTRA_REF_UV__) // Make sure this is only included once #define __LOAD_INTRA_REF_UV__ // Module name: load_Intra_Ref_UV.asm // // Load all reference U/V samples from neighboring macroblocks // // Note: Since loading of U/V data always follows writing of Y, the message descriptor is manipulated // to avoid recalculating due to frame/field variztions. // First load top 20x1 row U/V reference samples // 4 from macroblock D (actually use 2), 16 from macroblock B // shr (1) I_ORIY<1>:w I_ORIY<0;1,0>:w 1:w // Adjust I_ORIY for NV12 format add (2) MSGSRC.0<1>:d I_ORIX<2;2,1>:w TOP_REF_OFFSET<2;2,1>:b {NoDDClr} // Reference samples positioned at (-4, -1) mov (1) MSGSRC.2:ud 0x00000013:ud {NoDDChk} // Block width and height (20x1) // Update message descriptor based on previous Y block write // #ifdef DEV_ILK add (1) MSGDSC MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC+DESTUV-DWBWMSGDSC_WC-0x10000000-DESTY:ud // Set message descriptor #else add (1) MSGDSC MSGDSC RESP_LEN(1)+DWBRMSGDSC_RC+DESTUV-DWBWMSGDSC_WC-0x00800000-DESTY:ud // Set message descriptor #endif // DEV_ILK send (8) INTRA_REF_TOP_D(0) MSGHDR MSGSRC<8;8,1>:ud DAPREAD MSGDSC // Then load left 4x8 reference samples (actually use 1x8 column) // add (1) MSGSRC.1<1>:d MSGSRC.1<0;1,0>:d 1:w {NoDDClr} // Reference samples positioned next row mov (1) MSGSRC.2:ud 0x00070003:ud {NoDDChk} // Block width and height (4x8) send (8) INTRA_REF_LEFT_D(0) MSGHDRUV MSGSRC<8;8,1>:ud DAPREAD MSGDSC // End of load_Intra_Ref_UV #endif // !defined(__LOAD_INTRA_REF_UV__) intel-driver-1.3.0/src/shaders/h264/mc/load_Intra_Ref_Y.asm000066400000000000000000000032051231401140700232540ustar00rootroot00000000000000/* * Load all reference Y samples from neighboring macroblocks * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__LOAD_INTRA_REF_Y__) // Make sure this is only included once #define __LOAD_INTRA_REF_Y__ // Module name: load_Intra_Ref_Y.asm // // Load all reference Y samples from neighboring macroblocks // load_Intra_Ref_Y: // shl (2) I_ORIX<1>:uw ORIX<2;2,1>:ub 4:w // Convert MB origin to pixel unit // First load top 28x1 row reference samples // 4 from macroblock D (actually use 1), 16 from macroblock B, and 8 from macroblock C // add (2) MSGSRC.0<1>:d I_ORIX<2;2,1>:w TOP_REF_OFFSET<2;2,1>:b {NoDDClr} // Reference samples positioned at (-4, -1) mov (1) MSGSRC.2:ud 0x0000001B:ud {NoDDChk} // Block width and height (28x1) add (1) MSGDSC REG_MBAFF_FIELD<0;1,0>:uw RESP_LEN(1)+DWBRMSGDSC_RC+DESTY:ud // Set message descriptor send (8) INTRA_REF_TOP_D(0) MSGHDRY0 MSGSRC<8;8,1>:ud DAPREAD MSGDSC // Then load left 4x16 reference samples (actually use 1x16 column) // add (1) MSGSRC.1<1>:d MSGSRC.1<0;1,0>:d 1:w {NoDDClr} // Reference samples positioned next row mov (1) MSGSRC.2:ud 0x00F0003:ud {NoDDChk} // Block width and height (4x16) add (1) MSGDSC MSGDSC RESP_LEN(1):ud // Need to read 1 more GRF register send (8) INTRA_REF_LEFT_D(0) MSGHDRY1 MSGSRC<8;8,1>:ud DAPREAD MSGDSC RETURN // End of load_Intra_Ref_Y #endif // !defined(__LOAD_INTRA_REF_Y__) intel-driver-1.3.0/src/shaders/h264/mc/null.g4a000066400000000000000000000036471231401140700207730ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Xiang Haihao * */ define(`YUV_color',`0xFFFFFFFFUD') shl(2) g62.0<1>UD g3.4<2,2,1>UB 4UW {align1}; mov(1) g62.8<1>UD 0x000f000fUD {align1}; mov(16) m1<1>UD YUV_color {align1 compr}; mov(16) m3<1>UD YUV_color {align1 compr}; mov(16) m5<1>UD YUV_color {align1 compr}; mov(16) m7<1>UD YUV_color {align1 compr}; send(16) 0 acc0<1>UW g62<8,8,1>UW write(0, 0, 2, 0) mlen 9 rlen 0 {align1}; shr(1) g62.4<1>UD g62.4<1,1,1>UD 1UW {align1}; mov(1) g62.8<1>UD 0x0007000fUD {align1}; mov(16) m1<1>UD YUV_color {align1 compr}; mov(16) m3<1>UD YUV_color {align1 compr}; send(16) 0 acc0<1>UW g62<8,8,1>UW write(1, 0, 2, 0) mlen 5 rlen 0 {align1}; send(16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 {align1 EOT}; intel-driver-1.3.0/src/shaders/h264/mc/null.g4b000066400000000000000000000013131231401140700207600ustar00rootroot00000000000000 { 0x00200009, 0x27c02e21, 0x00450064, 0x00040004 }, { 0x00000001, 0x27c80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20200062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20600062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20a00062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20e00062, 0x00000000, 0xffffffff }, { 0x00800031, 0x24001d28, 0x008d07c0, 0x05902000 }, { 0x00000008, 0x27c42c21, 0x002107c4, 0x00010001 }, { 0x00000001, 0x27c80061, 0x00000000, 0x0007000f }, { 0x00802001, 0x20200062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20600062, 0x00000000, 0xffffffff }, { 0x00800031, 0x24001d28, 0x008d07c0, 0x05502001 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/h264/mc/null.g4b.gen5000066400000000000000000000013131231401140700216150ustar00rootroot00000000000000 { 0x00200009, 0x27c02e21, 0x00450064, 0x00040004 }, { 0x00000001, 0x27c80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20200062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20600062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20a00062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20e00062, 0x00000000, 0xffffffff }, { 0x00800031, 0x24001d28, 0x508d07c0, 0x12082000 }, { 0x00000008, 0x27c42c21, 0x002107c4, 0x00010001 }, { 0x00000001, 0x27c80061, 0x00000000, 0x0007000f }, { 0x00802001, 0x20200062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20600062, 0x00000000, 0xffffffff }, { 0x00800031, 0x24001d28, 0x508d07c0, 0x0a082001 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/h264/mc/recon_C_4x4.asm000066400000000000000000000025001231401140700221600ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: Recon_C_4x4.asm // // $Revision: 11 $ // $Date: 10/03/06 5:28p $ // //#if !defined(__RECON_C_4x4__) // Make sure this is only included once //#define __RECON_C_4x4__ // TODO: Use instruction compression add.sat (4) r[pERRORC,0]<2>:ub r[pERRORC,0]<4;4,1>:w gubCPRED(0)<16;4,4> add.sat (4) r[pERRORC,128]<2>:ub r[pERRORC,128]<4;4,1>:w gubCPRED(0,2)<16;4,4> add.sat (4) r[pERRORC,32]<2>:ub r[pERRORC,32]<4;4,1>:w gubCPRED(1)<16;4,4> add.sat (4) r[pERRORC,128+32]<2>:ub r[pERRORC,128+32]<4;4,1>:w gubCPRED(1,2)<16;4,4> add.sat (4) r[pERRORC,16]<2>:ub r[pERRORC,16]<4;4,1>:w gubCPRED(0,16)<16;4,4> add.sat (4) r[pERRORC,128+16]<2>:ub r[pERRORC,128+16]<4;4,1>:w gubCPRED(0,18)<16;4,4> add.sat (4) r[pERRORC,48]<2>:ub r[pERRORC,48]<4;4,1>:w gubCPRED(1,16)<16;4,4> add.sat (4) r[pERRORC,128+48]<2>:ub r[pERRORC,128+48]<4;4,1>:w gubCPRED(1,18)<16;4,4> // Increase chroma error block offset #ifndef MONO add (1) pERRORC:w pERRORC:w 8:w #endif //#endif // !defined(__RECON_C_4x4__) intel-driver-1.3.0/src/shaders/h264/mc/recon_Y_8x8.asm000066400000000000000000000015731231401140700222270ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: Recon_Y_8x8.asm // // $Revision: 10 $ // $Date: 9/22/06 2:50p $ // //#if !defined(__RECON_Y_8x8__) // Make sure this is only included once //#define __RECON_Y_8x8__ add.sat (16) r[pERRORY,0]<2>:ub r[pERRORY,0]<16;16,1>:w gubYPRED(0) add.sat (16) r[pERRORY,nGRFWIB]<2>:ub r[pERRORY,nGRFWIB]<16;16,1>:w gubYPRED(1) add.sat (16) r[pERRORY,nGRFWIB*2]<2>:ub r[pERRORY,nGRFWIB*2]<16;16,1>:w gubYPRED(2) add.sat (16) r[pERRORY,nGRFWIB*3]<2>:ub r[pERRORY,nGRFWIB*3]<16;16,1>:w gubYPRED(3) add (1) pERRORY:w pERRORY:w 128:w //#endif // !defined(__RECON_Y_8x8__) intel-driver-1.3.0/src/shaders/h264/mc/roundShift_C_4x4.asm000066400000000000000000000015021231401140700232000ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: RoundShift_C_4x4.asm // // Do (...+32)>>6 to 4x4 (NV12 8x4) interpolated chrominance data // //#if !defined(__RoundShift_C_4x4__) // Make sure this is only included once //#define __RoundShift_C_4x4__ // TODO: Optimize using instruction compression add (16) acc0<1>:w r[pRESULT,0]<16;16,1>:w 32:w add (16) acc1<1>:w r[pRESULT,nGRFWIB]<16;16,1>:w 32:w asr.sat (16) r[pRESULT,0]<2>:ub acc0<16;16,1>:w 6:w asr.sat (16) r[pRESULT,nGRFWIB]<2>:ub acc1<16;16,1>:w 6:w //#endif // !defined(__RoundShift_C_4x4__) intel-driver-1.3.0/src/shaders/h264/mc/save_16x16_Y.asm000066400000000000000000000027101231401140700222070ustar00rootroot00000000000000/* * Save decoded Y picture data to frame buffer * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__SAVE_16X16_Y__) // Make sure this is only included once #define __SAVE_16X16_Y__ // Module name: save_16x16_Y.asm // // Save decoded Y picture data to frame buffer // save_16x16_Y: mov (1) MSGSRC.2:ud 0x000F000F:ud {NoDDClr} // Block width and height (16x16) mov (2) MSGSRC.0:ud I_ORIX<2;2,1>:w {NoDDChk} // X, Y offset #ifdef DEV_ILK add (1) MSGDSC MSGDSC MSG_LEN(8)+DWBWMSGDSC_WC-DWBRMSGDSC_RC-0x00200000:ud // Set message descriptor #else add (1) MSGDSC MSGDSC MSG_LEN(8)+DWBWMSGDSC_WC-DWBRMSGDSC_RC-0x00020000:ud // Set message descriptor #endif // DEV_ILK mov (1) PDECBUF_UD<1>:ud 0x10001*DECBUF*GRFWIB+0x00400000:ud // Pointers to row 0 and 2 of decoded data $for(0,0; <8; 2,4) { mov (32) MSGPAYLOAD(%1)<1> r[PDECBUF, %2*GRFWIB]REGION(16,2) {Compr} // Block Y0/Y2 mov (32) MSGPAYLOAD(%1,16)<1> r[PDECBUF, (1+%2)*GRFWIB]REGION(16,2) {Compr} // Block Y1/Y3 } // Update message descriptor based on previous read setup // send (8) REG_WRITE_COMMIT_Y<1>:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC RETURN // End of save_16x16_Y #endif // !defined(__SAVE_16X16_Y__) intel-driver-1.3.0/src/shaders/h264/mc/save_4x4_Y.asm000066400000000000000000000030201231401140700220340ustar00rootroot00000000000000/* * Save Intra_4x4 decoded Y picture data to frame buffer * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__SAVE_4X4_Y__) // Make sure this is only included once #define __SAVE_4X4_Y__ // Module name: save_4x4_Y.asm // // Save Intra_4x4 decoded Y picture data to frame buffer // Note: Each 4x4 block is stored in 1 GRF register in the order of block raster scan order, // i.e. 0, 1, 4, 5, 2, 3, 6, 7, 8, 9, 12, 13, 10, 11, 14, 15 save_4x4_Y: mov (1) MSGSRC.2:ud 0x000F000F:ud {NoDDClr} // Block width and height (16x16) mov (2) MSGSRC.0:ud I_ORIX<2;2,1>:w {NoDDChk} // X, Y offset #ifdef DEV_ILK add (1) MSGDSC MSGDSC MSG_LEN(8)+DWBWMSGDSC_WC-DWBRMSGDSC_RC-0x00200000:ud // Set message descriptor #else add (1) MSGDSC MSGDSC MSG_LEN(8)+DWBWMSGDSC_WC-DWBRMSGDSC_RC-0x00020000:ud // Set message descriptor #endif // DEV_ILK $for(0; <8; 2) { mov (16) MSGPAYLOAD(%1)<1> DEC_Y(%1)<16;4,1> mov (16) MSGPAYLOAD(%1,16)<1> DEC_Y(%1,4)<16;4,1> mov (16) MSGPAYLOAD(%1+1)<1> DEC_Y(%1,8)<16;4,1> mov (16) MSGPAYLOAD(%1+1,16)<1> DEC_Y(%1,12)<16;4,1> } // Update message descriptor based on previous read setup // send (8) REG_WRITE_COMMIT_Y<1>:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC RETURN // End of save_4x4_Y #endif // !defined(__SAVE_4X4_Y__) intel-driver-1.3.0/src/shaders/h264/mc/save_8x8_UV.asm000066400000000000000000000035251231401140700222000ustar00rootroot00000000000000/* * Save decoded U/V picture data to frame buffer * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__SAVE_8x8_UV__) // Make sure this is only included once #define __SAVE_8x8_UV__ // Module name: save_8x8_UV.asm // // Save decoded U/V picture data to frame buffer // mov (1) MSGSRC.2:ud 0x0007000F:ud {NoDDClr} // Block width and height (16x8) mov (2) MSGSRC.0<1>:ud I_ORIX<2;2,1>:w {NoDDChk} // I_ORIX has already been adjusted for NV12 // Update message descriptor based on previous read setup // #ifdef DEV_ILK add (1) MSGDSC MSGDSC MSG_LEN(4)+DWBWMSGDSC_WC-DWBRMSGDSC_RC-0x00100000:ud // Set message descriptor #else add (1) MSGDSC MSGDSC MSG_LEN(4)+DWBWMSGDSC_WC-DWBRMSGDSC_RC-0x00010000:ud // Set message descriptor #endif // DEV_ILK // Write U/V picture data // #ifndef MONO mov MSGPAYLOAD(0,0)<1> DEC_UV(0)REGION(16,2) // U/V row 0 mov MSGPAYLOAD(0,16)<1> DEC_UV(1)REGION(16,2) // U/V row 1 mov MSGPAYLOAD(1,0)<1> DEC_UV(2)REGION(16,2) // U/V row 2 mov MSGPAYLOAD(1,16)<1> DEC_UV(3)REGION(16,2) // U/V row 3 mov MSGPAYLOAD(2,0)<1> DEC_UV(4)REGION(16,2) // U/V row 4 mov MSGPAYLOAD(2,16)<1> DEC_UV(5)REGION(16,2) // U/V row 5 mov MSGPAYLOAD(3,0)<1> DEC_UV(6)REGION(16,2) // U/V row 6 mov MSGPAYLOAD(3,16)<1> DEC_UV(7)REGION(16,2) // U/V row 7 #else // defined(MONO) $for(0; <4; 2) { mov (16) MSGPAYLOADD(%1)<1> 0x80808080:ud {Compr} } #endif // !defined(MONO) send (8) REG_WRITE_COMMIT_UV<1>:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC // End of save_8x8_UV #endif // !defined(__SAVE_8x8_UV__) intel-driver-1.3.0/src/shaders/h264/mc/save_8x8_Y.asm000066400000000000000000000037711231401140700220610ustar00rootroot00000000000000/* * Save Intra_8x8 decoded Y picture data to frame buffer * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__SAVE_8X8_Y__) // Make sure this is only included once #define __SAVE_8X8_Y__ // Module name: save_8x8_Y.asm // // Save Intra_8x8 decoded Y picture data to frame buffer // NotE: Every 4 rows of Y data are interleaved with the horizontal neighboring blcok // save_8x8_Y: mov (1) MSGSRC.2:ud 0x000F000F:ud {NoDDClr} // Block width and height (16x16) mov (2) MSGSRC.0:ud I_ORIX<2;2,1>:w {NoDDChk} // X, Y offset // Update message descriptor based on previous read setup // #ifdef DEV_ILK add (1) MSGDSC MSGDSC MSG_LEN(8)+DWBWMSGDSC_WC-DWBRMSGDSC_RC-0x00200000:ud // Set message descriptor #else add (1) MSGDSC MSGDSC MSG_LEN(8)+DWBWMSGDSC_WC-DWBRMSGDSC_RC-0x00020000:ud // Set message descriptor #endif // DEV_ILK mov (16) MSGPAYLOAD(0)<1> DEC_Y(0)<32;8,1> mov (16) MSGPAYLOAD(0,16)<1> DEC_Y(0,8)<32;8,1> mov (16) MSGPAYLOAD(1,0)<1> DEC_Y(0,16)<32;8,1> mov (16) MSGPAYLOAD(1,16)<1> DEC_Y(0,24)<32;8,1> mov (16) MSGPAYLOAD(2)<1> DEC_Y(2)<32;8,1> mov (16) MSGPAYLOAD(2,16)<1> DEC_Y(2,8)<32;8,1> mov (16) MSGPAYLOAD(3,0)<1> DEC_Y(2,16)<32;8,1> mov (16) MSGPAYLOAD(3,16)<1> DEC_Y(2,24)<32;8,1> mov (16) MSGPAYLOAD(4)<1> DEC_Y(4)<32;8,1> mov (16) MSGPAYLOAD(4,16)<1> DEC_Y(4,8)<32;8,1> mov (16) MSGPAYLOAD(5,0)<1> DEC_Y(4,16)<32;8,1> mov (16) MSGPAYLOAD(5,16)<1> DEC_Y(4,24)<32;8,1> mov (16) MSGPAYLOAD(6)<1> DEC_Y(6)<32;8,1> mov (16) MSGPAYLOAD(6,16)<1> DEC_Y(6,8)<32;8,1> mov (16) MSGPAYLOAD(7,0)<1> DEC_Y(6,16)<32;8,1> mov (16) MSGPAYLOAD(7,16)<1> DEC_Y(6,24)<32;8,1> send (8) REG_WRITE_COMMIT_Y<1>:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC RETURN // End of save_8x8_Y #endif // !defined(__SAVE_8X8_Y__) intel-driver-1.3.0/src/shaders/h264/mc/save_I_PCM.asm000066400000000000000000000037021231401140700220230ustar00rootroot00000000000000/* * Save I_PCM Y samples to Y picture buffer * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: save_I_PCM.asm // // First save I_PCM Y samples to Y picture buffer // mov (1) MSGSRC.2:ud 0x000F000F:ud {NoDDClr} // Block width and height (16x16) shl (2) MSGSRC.0:ud ORIX<2;2,1>:ub 4:w {NoDDChk} // Convert MB origin in pixel unit add (1) MSGDSC REG_MBAFF_FIELD<0;1,0>:uw MSG_LEN(8)+DWBWMSGDSC_WC+DESTY:ud // Set message descriptor $for(0; <8; 2) { mov (32) MSGPAYLOAD(%1)<1> I_PCM_Y(%1)REGION(16,1) {Compr,NoDDClr} mov (32) MSGPAYLOAD(%1,16)<1> I_PCM_Y(%1,16)REGION(16,1) {Compr,NoDDChk} } send (8) REG_WRITE_COMMIT_Y<1>:ud MSGHDR MSGSRC<8;8,1>:ud DAPWRITE MSGDSC // Then save I_PCM U/V samples to U/V picture buffer // mov (1) MSGHDR.2:ud 0x0007000F:ud {NoDDClr} // Block width and height (16x8) asr (1) MSGHDR.1:ud MSGSRC.1<0;1,0>:ud 1:w {NoDDChk} // Y offset should be halved add (1) MSGDSC MSGDSC 0x0-MSG_LEN(4)+0x1:d // Set message descriptor for U/V #if 0 and.z.f0.0 (1) NULLREG REG_CHROMA_FORMAT_IDC CHROMA_FORMAT_IDC:ud (f0.0) jmpi (1) MONOCHROME_I_PCM #endif #ifndef MONO // Non-monochrome picture // $for(0,0; <4; 2,1) { mov (16) MSGPAYLOAD(%1)<2> I_PCM_UV(%2)REGION(16,1) // U data mov (16) MSGPAYLOAD(%1,1)<2> I_PCM_UV(%2+2)REGION(16,1) // V data mov (16) MSGPAYLOAD(%1+1)<2> I_PCM_UV(%2,16)REGION(16,1) // U data mov (16) MSGPAYLOAD(%1+1,1)<2> I_PCM_UV(%2+2,16)REGION(16,1) // V data } #else // defined(MONO) MONOCHROME_I_PCM: $for(0; <4; 2) { mov (16) MSGPAYLOADD(%1)<1> 0x80808080:ud {Compr} } #endif // !defined(MONO) send (8) REG_WRITE_COMMIT_UV<1>:ud MSGHDR null:ud DAPWRITE MSGDSC // End of save_I_PCM intel-driver-1.3.0/src/shaders/h264/mc/scoreboard.asm000066400000000000000000000253761231401140700222540ustar00rootroot00000000000000/* * Dependency control scoreboard kernel * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: scoreboard.asm // // Dependency control scoreboard kernel // // $Revision: 16 $ // $Date: 10/18/06 4:10p $ // // ---------------------------------------------------- // Main: scoreboard // ---------------------------------------------------- // ---------------------------------------------------- // Scoreboard structure // ---------------------------------------------------- // // 1 DWORD per thread // // Bit 31: "Checking" thread, i.e. an intra MB that sends "check dependency" message // Bit 30: "Completed" thread. This bit set by an "update" message from intra/inter MB. // Bits 29:28: Must set to 0 // Bits 27:24: EUID // Bits 23:18: Reserved // Bits 17:16: TID // Bits 15:8: X offset of current MB // Bits 15:5: Reserved // Bits 4:0: 5 bits of available neighbor MB flags .kernel scoreboard SCOREBOARD: #ifdef _DEBUG // WA for FULSIM so we'll know which kernel is being debugged mov (1) acc0:ud 0xf0aa55a5:ud #endif #include "header.inc" #include "scoreboard_header.inc" // // Now, begin source code.... // .code #ifdef AS_ENABLED and.z.f0.1 (1) NULLREG r0.2<0;1,0>:ud TH_RES // Is this a restarted thread previously interrupted? (f0.1) jmpi (1) Scoreboard_Init #include "scoreboard_restore_AS.asm" jmpi (1) Scoreboard_OpenGW Scoreboard_Init: #endif // End AS_ENABLED // Scoreboard must be initialized to 0xc000ffff, meaning all "completed" // And it also avoids message mis-handling for the first MB $for(0; <32; 2) { mov (16) CMD_SB(%1)<1> 0xc000ffff:ud {Compr} } #ifdef DOUBLE_SB // Scoreboard size needs to be doubled $for(32; <64; 2) { mov (16) CMD_SB(%1)<1> 0xc000ffff:ud {Compr} } #endif // DOUBLE_SB //---------------------------------------------------------- // Open message gateway for the scoreboard thread // // RegBase = r4 (0x04) // Gateway Size = 64 GRF registers (0x6) // Dispatch ID = r0.20:ub // Scoreboard Thread Key = 0 //---------------------------------------------------------- Scoreboard_OpenGW: mov (8) MSGHDRY0<1>:ud 0x00000000:ud // Initialize message header payload with 0 // Send a message with register base RegBase=0x04(r4) and Gateway size = 0x6 = 64 GRF reg and Key = 0 // 000 00000100 00000 00000 110 00000000 ==> 0000 0000 1000 0000 0000 0110 0000 0000 #ifdef AS_ENABLED add (1) MSGHDRY0.5<1>:ud r0.20:ub 0x00800700:ud // Allocate 128 GRFs for message gateway - for SIP to send notification MSG #else #ifdef DOUBLE_SB add (1) MSGHDRY0.5<1>:ud r0.20:ub 0x00800600:ud // 64 GRF's for CTG-B #else add (1) MSGHDRY0.5<1>:ud r0.20:ub 0x00800500:ud // 32 GRF's for CTG-A #endif // DOUBLE_SB #endif send (8) NULLREG MSGHDRY0 null:ud MSG_GW OGWMSGDSC //------------------------------------------------------------------------ // Send Thread Spawning Message to start dispatching macroblock threads // //------------------------------------------------------------------------ #ifdef AS_ENABLED mov (8) acc0<1>:ud CMD_SB(31)<8;8,1> // Ensure scoreboard data have been completely restored #endif // End AS_ENABLED mov (8) MSGHDRY1<1>:ud r0<8;8,1>:ud // Initialize message header payload with R0 mov (1) MSGHDRY1.4<1>:ud 0x00000400:ud // Dispatch URB length = 1 send (8) NULLREG MSGHDRY1 null:ud TS TSMSGDSC mov (8) MSGHDRY0<1>:ud 0x00000000:ud // Initialize message header payload with 0 //------------------------------------------------------------------------ // Scoreboard control data initialization //------------------------------------------------------------------------ #ifdef AS_ENABLED or (1) cr0.1:ud cr0.1:ud AS_INT_EN // Enable interrupt (f0.1) jmpi (1) Scoreboard_State_Init // Jump if not restarted thread // Restore scoreboard kernel control data to r1 - r3 mov (1) m4.1:ud 64:ud // Starting r1 mov (1) m4.2:ud 0x0002001f:ud // for 3 registers send (8) r1.0<1>:ud m4 null:ud DWBRMSGDSC_SC+0x00030000+AS_SAVE // Restore r1 - r3 mov (8) a0.0<1>:uw AR_SAVE<8;8,1>:uw // Restore all address registers // Check whether all MBs have been decoded cmp.e.f0.0 (1) NULLREG TotalMB<0;1,0>:w 0:w // Set "Last MB" flag (-f0.0) jmpi (1) Before_First_MB END_THREAD // Check whether it is before the first MB Before_First_MB: cmp.e.f0.0 (1) NULLREG AVAILFLAGD<1>:ud 0x08020401:ud // in ACBD order (f0.0) jmpi (1) Wavefront_Walk Scoreboard_State_Init: #endif // End AS_ENABLED mov (2) WFLen_B<2>:w HEIGHTINMB_1<0;1,0>:w mov (1) AVAILFLAGD<1>:ud 0x08020401:ud // in ACBD order mov (1) CASE00PTR<1>:ud Notify_MSG_IP-No_Message_IP:ud // Inter kernel starts mov (1) CASE10PTR<1>:ud Dependency_Check_IP-No_Message_IP:ud // Intra kernel starts #ifdef AS_ENABLED mov (1) CASE11PTR<1>:ud 0:ud // No message #else mov (1) CASE11PTR<1>:ud MB_Loop_IP-No_Message_IP:ud // No message #endif // End AS_ENABLED mov (1) StartXD<1>:ud 0:ud mov (1) NewWFOffsetD<1>:ud 0x01ffff00:ud mov (4) WFStart(0)<1> 0xffff:w mov (1) WFStart(0)<1> 0:w mov (8) a0.0<1>:uw 0x0:uw // Initialize all pointers to 0 //------------------------------------------------------------------------ // Scoreboard message handling loop //------------------------------------------------------------------------ // Scoreboard_Loop: // Calculate current wavefront length add.ge.f0.1 (16) acc0<1>:w StartX<0;1,0>:w 0:w // Used for x>2*y check mac.g.f0.0 (16) NULLREGW WFLenY<0;1,0>:w -2:w // X - 2*Y > 0 ?? (f0.0) mov (1) WFLen<1>:w WFLenY<0;1,0>:w // Use smaller vertical wavefront length (-f0.0) asr.sat (1) WFLen<1>:uw StartX<0;1,0>:w 1:w // Horizontal wavefront length is smaller // Initialize 5-MB group #ifdef ONE_MB_WA mov (2) MBINDEX(0)<1> WFStart(0)<2;2,1> (f0.1) add (4) MBINDEX(0,2)<1> WFStart(0,1)<4;4,1> -1:w (-f0.1) add (4) MBINDEX(0,2)<1> WFStart(0,0)<4;4,1> -1:w (-f0.1) mov (1) StartX<1>:w 0:w // WA for 1-MB wide pictures #else mov (2) MBINDEX(0)<1> WFStart(0)<2;2,1> {NoDDClr} add (4) MBINDEX(0,2)<1> WFStart(0,1)<4;4,1> -1:w {NoDDChk} #endif // Update WFStart mov (8) acc0<1>:w WFStart(0)<0;1,0> // Move WFStart(0) to acc0 to remove dependency later mov (4) WFStart(0,1)<1> WFStart(0)<4;4,1> {NoDDClr} // Shift WFStart(0:2) to WFStart(1:3) add (1) WFStart(0)<1> acc0.0<0;1,0>:w WFLen<0;1,0>:w {NoDDChk} // WFStart(0) = WFStart(0) + WFLen mul (8) MBINDEX(0)<1> MBINDEX(0)<8;8,1> 4:w // Adjust MB order # to be DWORD aligned and (1) DEPPTR<1>:uw acc0<0;1,0>:w SB_MASK*4:uw {NoDDClr} // Wrap around scoreboard entries for current MB and (4) DEPPTRL<1>:uw acc0.1<4;4,1>:w SB_MASK*4:uw {NoDDChk} // Wrap around scoreboard entries for neighbor MBs Wavefront_Walk: wait n0:ud // Check for combined "checking" or "completed" threads in forwarded message // 2 MSB of scoreboard message indicate: // 0b00 = "inter start" message // 0b10 = "intra start" message // 0b11 = "No Message" or "inter complete" message // 0b01 = Reserved (should never occur) // MB_Loop: shr (1) PMSGSEL<1>:uw r[CMDPTR,CMD_SB_REG_OFF*GRFWIB+2]<0;1,0>:uw 12:w // DWORD aligned pointer to message handler and.nz.f0.1 (4) NULLREG r[CMDPTR,CMD_SB_REG_OFF*GRFWIB]<0;1,0>:ub AVAILFLAG<4;4,1>:ub // f0.1 4 LSB will have the available flags in ACBD order mov (1) MSGHDRY0.4<1>:ud r[CMDPTR,CMD_SB_REG_OFF*GRFWIB]<0;1,0>:ud // Copy MB thread info from scoreboard jmpi (1) r[PMSGSEL, INLINE_REG_OFF*GRFWIB+16]<0;1,0>:d // Now determine whether this is "inter done" or "no message" // through checking debug_counter // No_Message: #ifdef AS_ENABLED cmp.z.f0.1 (1) NULLREG n0:ud 0 // Are all messages handled? and.z.f0.0 (1) NULLREG cr0.1:ud AS_INT // Poll interrupt bit (-f0.1) jmpi (1) MB_Loop // Continue polling the remaining message from current thread // All messages have been handled (f0.0) jmpi (1) Wavefront_Walk // No interrupt occurs. Wait for next one // Interrupt has been detected // Save all contents and terminate the scoreboard // #include "scoreboard_save_AS.asm" // Save scoreboard control data as well // mov (8) AR_SAVE<1>:uw a0.0<8;8,1>:uw // All address registers needs to be saved mov (1) MSGHDR.1:ud 64:ud mov (1) MSGHDR.2:ud 0x0002001f:ud // for 3 registers $for(0; <3; 1) { mov (8) MSGPAYLOADD(%1)<1> CMD_SB(%1-3)REGION(8,1) } send (8) NULLREG MSGHDR null:ud DWBWMSGDSC+0x00300000+AS_SAVE // Save r1 - r3 send (8) NULLREG MSGHDR r0:ud EOTMSGDSC+TH_INT // Terminate with "Thread Interrupted" bit set #endif // End AS_ENABLED Dependency_Check: // Current thread is "checking" but not "completed" (0b10 case). // Check for dependency clear using all availability bits // (f0.1) and.z.f0.1 (4) NULLREG r[DEPPTRL,CMD_SB_REG_OFF*GRFWIB+3]<1,0>:ub DONEFLAG:uw // f0.1 4 LSB contains dependency clear (f0.1.any4h) jmpi (1) Dependency_Check // Dependency not clear, keep polling.. // "Checking" thread and dependency cleared, send a message to let the thread go // Notify_MSG: send (8) NULLREG MSGHDRY0 null:ud MSG_GW FWDMSGDSC+NOTIFYMSG // Current macroblock has been serviced. Update to next macroblock in special zig-zag order // Update_CurMB: #if 0 add.ge.f0.0 (1) WFLen<1>:w WFLen<0;1,0>:w -1:w // Set "End of wavefront" flag add (1) TotalMB<1>:w TotalMB<0;1,0>:w -1:w // Decrement "TotalMB" #else add.ge.f0.0 (2) TotalMB<2>:w TotalMB<4;2,2>:w -1:w // Set "End of wavefront" flag and decrement "TotalMB" #endif add (8) MBINDEX(0)<1> MBINDEX(0)<8;8,1> 4:w // Increment MB indices and (1) DEPPTR<1>:uw acc0<0;1,0>:w SB_MASK*4:uw {NoDDClr} // Wrap around 256 scoreboard entries for current MB and (4) DEPPTRL<1>:uw acc0.1<4;4,1>:w SB_MASK*4:uw {NoDDChk} // Wrap around 256 scoreboard entries for neighbor MBs cmp.e.f0.1 (16) NULLREGW StartX<0;1,0>:uw WIDTHINMB_1<0;1,0>:uw // Set "on picture right boundary" flag #if 0 (f0.0) jmpi (1) Wavefront_Walk // Continue wavefront walking #else (f0.0.all2h) jmpi (1) Wavefront_Walk // Continue wavefront walking #endif // Start new wavefront // cmp.e.f0.0 (1) NULLREG TotalMB<0;1,0>:w 0:w // Set "Last MB" flag (f0.1) add (4) WFLen<1>:w WFLen<4;4,1>:w NewWFOffset<4;4,1>:b (f0.1) add (4) WFStart(0)<1> WFStart(0)<4;4,1> 1:w (-f0.1) add (1) StartX<1>:w StartX<0;1,0>:w 1:w // Move to right MB (-f0.1) add (1) WFStart(0)<1> WFStart(0)<0;1,0> 1:w (-f0.0) jmpi (1) Scoreboard_Loop // Not last MB, start new wavefront walking // All MBs have decoded. Terminate the thread now // END_THREAD #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif // End of scoreboard intel-driver-1.3.0/src/shaders/h264/mc/scoreboard_MBAFF.asm000066400000000000000000000301661231401140700231400ustar00rootroot00000000000000/* * Dependency control scoreboard kernel for MBAFF frame * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: scoreboard_MBAFF.asm // // Dependency control scoreboard kernel for MBAFF frame // // $Revision: 16 $ // $Date: 10/18/06 4:10p $ // // ---------------------------------------------------- // Main: scoreboard_MBAFF // ---------------------------------------------------- // ---------------------------------------------------- // Scoreboard structure // ---------------------------------------------------- // // 1 DWORD per thread // // Bit 31: "Checking" thread, i.e. an intra MB that sends "check dependency" message // Bit 30: "Completed" thread. This bit set by an "update" message from intra/inter MB. // Bits 29:28: Must set to 0 // Bits 27:24: EUID // Bits 23:18: Reserved // Bits 17:16: TID // Bits 15:8: X offset of current MB // Bits 15:5: Reserved // Bits 4:0: 5 bits of available neighbor MB flags .kernel scoreboard_MBAFF SCOREBOARD_MBAFF: #ifdef _DEBUG // WA for FULSIM so we'll know which kernel is being debugged mov (1) acc0:ud 0xffaa55a5:ud #endif #include "header.inc" #include "scoreboard_header.inc" // // Now, begin source code.... // .code #ifdef AS_ENABLED and.z.f0.1 (1) NULLREG r0.2<0;1,0>:ud TH_RES // Is this a restarted thread previously interrupted? (f0.1) jmpi (1) MBAFF_Scoreboard_Init #include "scoreboard_restore_AS.asm" jmpi (1) MBAFF_Scoreboard_OpenGW MBAFF_Scoreboard_Init: #endif // End AS_ENABLED // Scoreboard must be initialized to 0xc000ffff, meaning all "completed" // And it also avoids message mis-handling for the first MB $for(0; <32; 2) { mov (16) CMD_SB(%1)<1> 0xc000ffff:ud {Compr} } #ifdef DOUBLE_SB // Scoreboard size needs to be doubled $for(32; <64; 2) { mov (16) CMD_SB(%1)<1> 0xc000ffff:ud {Compr} } #endif // DOUBLE_SB //---------------------------------------------------------- // Open message gateway for the scoreboard thread // // RegBase = r4 (0x04) // Gateway Size = 64 GRF registers (0x6) // Dispatch ID = r0.20:ub // Scoreboard Thread Key = 0 //---------------------------------------------------------- MBAFF_Scoreboard_OpenGW: mov (8) MSGHDRY0<1>:ud 0x00000000:ud // Initialize message header payload with 0 // Send a message with register base RegBase=0x04(r4) and Gateway size = 0x6 = 64 GRF reg and Key = 0 // 000 00000100 00000 00000 110 00000000 ==> 0000 0000 1000 0000 0000 0110 0000 0000 #ifdef AS_ENABLED add (1) MSGHDRY0.5<1>:ud r0.20:ub 0x00800700:ud // Allocate 128 GRFs for message gateway - for SIP to send notification MSG #else #ifdef DOUBLE_SB add (1) MSGHDRY0.5<1>:ud r0.20:ub 0x00800600:ud // 64 GRF's for CTG-B #else add (1) MSGHDRY0.5<1>:ud r0.20:ub 0x00800500:ud // 32 GRF's for CTG-A #endif // DOUBLE_SB #endif send (8) NULLREG MSGHDRY0 null:ud MSG_GW OGWMSGDSC //------------------------------------------------------------------------ // Send Thread Spawning Message to start dispatching macroblock threads // //------------------------------------------------------------------------ #ifdef AS_ENABLED mov (8) acc0<1>:ud CMD_SB(31)<8;8,1> // Ensure scoreboard data have been completely restored #endif // End AS_ENABLED mov (8) MSGHDRY1<1>:ud r0<8;8,1>:ud // Initialize message header payload with R0 mov (1) MSGHDRY1.4<1>:ud 0x00000400:ud // Dispatch URB length = 1 send (8) NULLREG MSGHDRY1 null:ud TS TSMSGDSC mov (8) MSGHDRY0<1>:ud 0x00000000:ud // Initialize message header payload with 0 //------------------------------------------------------------------------ // Scoreboard control data initialization //------------------------------------------------------------------------ #ifdef AS_ENABLED or (1) cr0.1:ud cr0.1:ud AS_INT_EN // Enable interrupt (f0.1) jmpi (1) MBAFF_Scoreboard_State_Init // Jump if not restarted thread // Restore scoreboard kernel control data to r1 - r3 mov (1) m4.1:ud 64:ud // Starting r1 mov (1) m4.2:ud 0x0002001f:ud // for 3 registers send (8) r1.0<1>:ud m4 null:ud DWBRMSGDSC_SC+0x00030000+AS_SAVE // Restore r1 - r3 and (1) CMDPTR<1>:uw MBINDEX(0)<0;1,0> SB_MASK*4:uw // Restore scoreboard entries for current MB // EOT if all MBs have been decoded cmp.e.f0.0 (1) NULLREG TotalMB<0;1,0>:w 0:w // Set "Last MB" flag (-f0.0) jmpi (1) MBAFF_Before_First_MB END_THREAD // Check whether it is before the first MB MBAFF_Before_First_MB: cmp.e.f0.0 (1) NULLREG AVAILFLAGD<1>:ud 0x08020401:ud // in ACBD order (f0.0) jmpi (1) MBAFF_Wavefront_Walk MBAFF_Scoreboard_State_Init: #endif // End AS_ENABLED mov (2) WFLen_B<2>:w HEIGHTINMB_1<0;1,0>:w mov (1) AVAILFLAGD<1>:ud 0x08020401:ud // in ACBD order mov (1) AVAILFLAG1D<1>:ud 0x08020410:ud // in A_C_B_D_ order mov (1) CASE00PTR<1>:ud MBAFF_Notify_MSG_IP-MBAFF_No_Message_IP:ud // Inter kernel starts mov (1) CASE10PTR<1>:ud MBAFF_Dependency_Check_IP-MBAFF_No_Message_IP:ud // Intra kernel starts #ifdef AS_ENABLED mov (1) CASE11PTR<1>:ud 0:ud // No message #else mov (1) CASE11PTR<1>:ud MBAFF_MB_Loop_IP-MBAFF_No_Message_IP:ud // No message #endif // End AS_ENABLED mov (1) StartXD<1>:ud 0:ud mov (1) NewWFOffsetD<1>:ud 0x01ffff00:ud mov (8) WFStart_T(0)<1> 0xffff:w mov (1) WFStart_T(0)<1> 0:w mov (8) a0.0<1>:uw 0x0:uw // Initialize all pointers to 0 //------------------------------------------------------------------------ // Scoreboard message handling loop //------------------------------------------------------------------------ // MBAFF_Scoreboard_Loop: // Calculate current wavefront length (same for top and bottom MB wavefronts) add.ge.f0.1 (16) acc0<1>:w StartX<0;1,0>:w 0:w // Used for x>2*y check mac.g.f0.0 (16) NULLREGW WFLenY<0;1,0>:w -2:w // X - 2*Y > 0 ?? (f0.0) mov (2) WFLen_B<1>:w WFLenY<0;1,0>:w // Use smaller vertical wavefront length (f0.0) mov (1) WFLen_Save<1>:w WFLenY<0;1,0>:w // Save current wave front length (-f0.0) asr.sat (2) WFLen_B<1>:uw StartX<0;1,0>:w 1:w // Horizontal wavefront length is smaller (-f0.0) asr.sat (1) WFLen_Save<1>:uw StartX<0;1,0>:w 1:w // Save current wave front length // Initialize 9-MB group for top macroblock wavefront #ifdef ONE_MB_WA_MBAFF mov (2) MBINDEX(0)<1> WFStart_T(0)<2;2,1> (f0.1) add (4) MBINDEX(0,2)<1> WFStart_B(0,1)<4;4,1> -1:w (-f0.1) add (4) MBINDEX(0,2)<1> WFStart_B(0,0)<4;4,1> -1:w mov (1) MBINDEX(0,5)<1> WFStart_B(0,1)<0;1,0> (-f0.1) mov (1) StartX<1>:w 0:w // WA for 1-MB wide pictures #else mov (2) MBINDEX(0)<1> WFStart_T(0)<2;2,1> {NoDDClr} add (4) MBINDEX(0,2)<1> WFStart_B(0,1)<4;4,1> -1:w {NoDDChk,NoDDClr} mov (1) MBINDEX(0,5)<1> WFStart_B(0,1)<0;1,0> {NoDDChk,NoDDClr} add (4) MBINDEX(0,6)<1> WFStart_T(0,1)<4;4,1> -1:w {NoDDChk} // Upper MB group (C_B_D_x) #endif // Update WFStart_B[0] add (8) acc0<1>:w WFLen<0;1,0>:w 1:w // WFLen + 1 add (1) WFStart_B(0,0)<1> acc0<0;1,0>:w WFStart_T(0,0)<0;1,0> // WFStart_T[0] + WFLen + 1 MBAFF_Start_Wavefront: mul (16) MBINDEX(0)<1> MBINDEX(0)REGION(16,1) 4:w // Adjust MB order # to be DWORD aligned and (1) CMDPTR<1>:uw acc0<0;1,0>:w SB_MASK*4:uw // Wrap around scoreboard entries for current MB MBAFF_Wavefront_Walk: wait n0:ud // Check for combined "checking" or "completed" threads in forwarded message // 2 MSB of scoreboard message indicate: // 0b00 = "inter start" message // 0b10 = "intra start" message // 0b11 = "No Message" or "inter complete" message // 0b01 = Reserved (should never occur) // MBAFF_MB_Loop: shr (1) PMSGSEL<1>:uw r[CMDPTR,CMD_SB_REG_OFF*GRFWIB+2]<0;1,0>:uw 12:w // DWORD aligned pointer to message handler and.nz.f0.1 (8) NULLREG r[CMDPTR,CMD_SB_REG_OFF*GRFWIB]<0;1,0>:ub AVAILFLAG<8;8,1>:ub // f0.1 8 LSB will have the available flags in ACBDA_C_B_D_ order mov (1) MSGHDRY0.4<1>:ud r[CMDPTR,CMD_SB_REG_OFF*GRFWIB]<0;1,0>:ud // Copy MB thread info from scoreboard jmpi (1) r[PMSGSEL, INLINE_REG_OFF*GRFWIB+16]<0;1,0>:d // Now determine whether this is "inter done" or "no message" // through checking debug_counter // MBAFF_No_Message: #ifdef AS_ENABLED cmp.z.f0.1 (1) NULLREG n0:ud 0 // Are all messages handled? and.z.f0.0 (1) NULLREG cr0.1:ud AS_INT // Poll interrupt bit (-f0.1) jmpi (1) MBAFF_MB_Loop // Continue polling the remaining message from current thread // All messages have been handled (f0.0) jmpi (1) MBAFF_Wavefront_Walk // No interrupt occurs. Wait for next one // Interrupt has been detected // Save all contents and terminate the scoreboard // #include "scoreboard_save_AS.asm" // Save scoreboard control data as well // mov (1) MSGHDR.1:ud 64:ud mov (1) MSGHDR.2:ud 0x0002001f:ud // for 3 registers $for(0; <3; 1) { mov (8) MSGPAYLOADD(%1)<1> CMD_SB(%1-3)REGION(8,1) } send (8) NULLREG MSGHDR null:ud DWBWMSGDSC+0x00300000+AS_SAVE // Save r1 - r3 send (8) NULLREG MSGHDR r0:ud EOTMSGDSC+TH_INT // Terminate with "Thread Interrupted" bit set #endif // End AS_ENABLED MBAFF_Dependency_Check: // Current thread is "checking" but not "completed" (0b10 case). // Check for dependency clear using all availability bits // and (8) DEPPTR<1>:uw MBINDEX(0,1)REGION(8,1) SB_MASK*4:uw // Wrap around scoreboard entries for current MB MBAFF_Dependency_Polling: (f0.1) and.z.f0.1 (8) NULLREG r[DEPPTR,CMD_SB_REG_OFF*GRFWIB+3]<1,0>:ub DONEFLAG:uw // f0.1 8 LSB contains dependency clear (f0.1.any8h) jmpi (1) MBAFF_Dependency_Polling // Dependency not clear, keep polling.. // "Checking" thread and dependency cleared, send a message to let the thread go // MBAFF_Notify_MSG: send (8) NULLREG MSGHDRY0 null:ud MSG_GW FWDMSGDSC+NOTIFYMSG // Current macroblock has been serviced. Update to next macroblock in special zig-zag order // MBAFF_Update_CurMB: add.ge.f0.0 (2) TotalMB<2>:w TotalMB<4;2,2>:w -1:w // Set "End of wavefront" flag and decrement "TotalMB" add (16) MBINDEX(0)<1> MBINDEX(0)REGION(16,1) 4:w // Increment MB indices and (1) CMDPTR<1>:uw acc0<0;1,0>:w SB_MASK*4:uw // Wrap around scoreboard entries for current MB (f0.0.all2h) jmpi (1) MBAFF_Wavefront_Walk // Continue wavefront walking // Top macroblock wavefront walk done, start bottom MB wavefront add.ge.f0.0 (1) WFLen<1>:w WFLen_B<0;1,0>:w 0:w {NoDDClr} // Set bottom MB wavefront length mov (1) WFLen_B<1>:w -1:w {NoDDChk} // Reset bottom MB wavefront length // Initialize 9-MB group for bottom macroblock wavefront mov (8) MBINDEX(0)<1> WFStart_B(0)<1;4,0> {NoDDClr} // Initialize with WFStart_B[0] and WFStart_B[1] mov (4) MBINDEX(0,1)<1> WFStart_T(0,1)<0;1,0> {NoDDChk,NoDDClr} // Initialize with WFStart_T[1] mov (2) MBINDEX(0,2)<1> WFStart_T(0)<0;1,0> {NoDDChk,NoDDClr} // Initialize with WFStart_T[0] add (4) MBINDEX(0,6)<1> WFStart_B(0,1)<4;4,1> -1:w {NoDDChk} // Upper MB group (C_B_D_x) (f0.0) jmpi (1) MBAFF_Start_Wavefront // Start bottom MB wavefront walk // Start new wavefront // cmp.e.f0.1 (16) NULLREGW StartX<0;1,0>:uw WIDTHINMB_1<0;1,0>:uw // Set "on picture right boundary" flag // Update WFStart_T and WFStart_B add (8) acc0<1>:w WFStart_T(0)REGION(1,0) 1:w // Move WFStart_T[0]+1 to acc0 to remove dependency later mov (8) WFStart_T(0,1)<1> WFStart_T(0)<8;8,1> {NoDDClr} // Shift WFStart_T(B)[0:2] to WFStart_T(B)[1:3] mac (1) WFStart_T(0,0)<1> WFLen_Save<0;1,0>:w 2:w {NoDDChk} // WFStart_T[0] = WFStart_T[0] + 2*WFLen cmp.e.f0.0 (1) NULLREG TotalMB<0;1,0>:w 0:w // Set "Last MB" flag (f0.1) add (4) WFLen<1>:w WFLen<4;4,1>:w NewWFOffset<4;4,1>:b // + (0, -1, -1, 1) (f0.1) add (8) WFStart_T(0)<1> WFStart_T(0)REGION(4,1) 1:w (-f0.1) add (1) StartX<1>:w StartX<0;1,0>:w 1:w // Move to right MB (-f0.1) add (1) WFStart_T(0)<1> WFStart_T(0)REGION(1,0) 1:w (-f0.0) jmpi (1) MBAFF_Scoreboard_Loop // Not last MB, start new wavefront walking // All MBs have decoded. Terminate the thread now // END_THREAD #if !defined(COMBINED_KERNEL) // For standalone kernel only .end_code .end_kernel #endif // End of scoreboard_MBAFF intel-driver-1.3.0/src/shaders/h264/mc/scoreboard_restore_AS.asm000066400000000000000000000042001231401140700243610ustar00rootroot00000000000000/* * Restore previously stored scoreboard data after content switching back * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: scoreboard_restore_AS.asm // // Restore previously stored scoreboard data after content switching back // // // Restore scoreboard data to r4 - r67 // They are saved in a 2D surface with width of 32 and height of 80. // Each row corresponds to one GRF register in the following order // r4 - r67 : Scoreboard message // mov (8) MSGSRC<1>:ud r0.0<8;8,1>:ud {NoDDClr} // Initialize message header payload with r0 mov (2) MSGSRC.0:ud 0:ud {NoDDClr, NoDDChk} // Starting r4 mov (1) MSGSRC.2:ud 0x0007001f:ud {NoDDChk} // for 8 registers send (8) CMD_SB(0)<1> m1 MSGSRC<8;8,1>:ud DWBRMSGDSC_SC+0x00080000+AS_SAVE // Restore r4 - r11 mov (8) m2:ud MSGSRC<8;8,1>:ud mov (1) m2.1:ud 8:ud send (8) CMD_SB(8)<1> m2 null:ud DWBRMSGDSC_SC+0x00080000+AS_SAVE // Restore r12 - r19 mov (8) m3:ud MSGSRC<8;8,1>:ud mov (1) m3.1:ud 16:ud send (8) CMD_SB(16)<1> m3 null:ud DWBRMSGDSC_SC+0x00080000+AS_SAVE // Restore r20 - r27 mov (8) m4:ud MSGSRC<8;8,1>:ud mov (1) m4.1:ud 24:ud send (8) CMD_SB(24)<1> m4 null:ud DWBRMSGDSC_SC+0x00080000+AS_SAVE // Restore r28 - r35 mov (8) m5:ud MSGSRC<8;8,1>:ud mov (1) m5.1:ud 32:ud send (8) CMD_SB(32)<1> m5 null:ud DWBRMSGDSC_SC+0x00080000+AS_SAVE // Restore r36 - r43 mov (8) m6:ud MSGSRC<8;8,1>:ud mov (1) m6.1:ud 40:ud send (8) CMD_SB(40)<1> m6 null:ud DWBRMSGDSC_SC+0x00080000+AS_SAVE // Restore r44 - r51 mov (8) m7:ud MSGSRC<8;8,1>:ud mov (1) m7.1:ud 48:ud send (8) CMD_SB(48)<1> m7 null:ud DWBRMSGDSC_SC+0x00080000+AS_SAVE // Restore r52 - r59 mov (8) m8:ud MSGSRC<8;8,1>:ud mov (1) m8.1:ud 56:ud send (8) CMD_SB(56)<1> m8 null:ud DWBRMSGDSC_SC+0x00080000+AS_SAVE // Restore r60 - r67 // End of scoreboard_restore_AS intel-driver-1.3.0/src/shaders/h264/mc/scoreboard_save_AS.asm000066400000000000000000000046601231401140700236460ustar00rootroot00000000000000/* * Save scoreboard data before content switching * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: scoreboard_save_AS.asm // // Save scoreboard data before content switching // // // r1 - r35 need to be saved // They are saved in a 2D surface with width of 32 and height of 64. // Each row corresponds to one GRF register in the following order // r4 - r35 : Scoreboard message // r1 - r3 : Scoreboard kernel control data mov (8) MSGHDR<1>:ud r0.0<8;8,1>:ud // Initialize message header payload with r0 mov (1) MSGHDR.2:ud 0x0007001f:ud // for 8 registers mov (2) MSGHDR.0:ud 0:ud $for(0; <8; 2) { mov (16) MSGPAYLOADD(%1)<1> CMD_SB(%1)REGION(8,1) {Compr} } send (8) NULLREG MSGHDR null:ud DWBWMSGDSC+0x00800000+AS_SAVE // Save r4 - r11 mov (1) MSGHDR.1:ud 8:ud $for(0; <8; 2) { mov (16) MSGPAYLOADD(%1)<1> CMD_SB(%1+8)REGION(8,1) {Compr} } send (8) NULLREG MSGHDR null:ud DWBWMSGDSC+0x00800000+AS_SAVE // Save r12 - r19 mov (1) MSGHDR.1:ud 16:ud $for(0; <8; 2) { mov (16) MSGPAYLOADD(%1)<1> CMD_SB(%1+16)REGION(8,1) {Compr} } send (8) NULLREG MSGHDR null:ud DWBWMSGDSC+0x00800000+AS_SAVE // Save r20 - r27 mov (1) MSGHDR.1:ud 24:ud $for(0; <8; 2) { mov (16) MSGPAYLOADD(%1)<1> CMD_SB(%1+24)REGION(8,1) {Compr} } send (8) NULLREG MSGHDR null:ud DWBWMSGDSC+0x00800000+AS_SAVE // Save r28 - r35 mov (1) MSGHDR.1:ud 32:ud $for(0; <8; 2) { mov (16) MSGPAYLOADD(%1)<1> CMD_SB(%1+32)REGION(8,1) {Compr} } send (8) NULLREG MSGHDR null:ud DWBWMSGDSC+0x00800000+AS_SAVE // Save r36 - r43 mov (1) MSGHDR.1:ud 40:ud $for(0; <8; 2) { mov (16) MSGPAYLOADD(%1)<1> CMD_SB(%1+40)REGION(8,1) {Compr} } send (8) NULLREG MSGHDR null:ud DWBWMSGDSC+0x00800000+AS_SAVE // Save r44 - r51 mov (1) MSGHDR.1:ud 48:ud $for(0; <8; 2) { mov (16) MSGPAYLOADD(%1)<1> CMD_SB(%1+48)REGION(8,1) {Compr} } send (8) NULLREG MSGHDR null:ud DWBWMSGDSC+0x00800000+AS_SAVE // Save r52 - r59 mov (1) MSGHDR.1:ud 56:ud $for(0; <8; 2) { mov (16) MSGPAYLOADD(%1)<1> CMD_SB(%1+56)REGION(8,1) {Compr} } send (8) NULLREG MSGHDR null:ud DWBWMSGDSC+0x00800000+AS_SAVE // Save r60 - r67 // End of scoreboard_save_AS intel-driver-1.3.0/src/shaders/h264/mc/scoreboard_sip.asm000066400000000000000000000020311231401140700231060ustar00rootroot00000000000000/* * Scoreboard interrupt handler * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: scoreboard_sip.asm // // scoreboard interrupt handler // // Simply send a notification message to scoreboard thread mov (8) m0<1>:ud 0x00000000:ud // Initialize message header payload with 0 #ifdef DOUBLE_SB mov (1) m0.5<1>:ud 0x08000200:ud // Message length = 1 DWORD, sent to GRF offset 64 registers #else mov (1) m0.5<1>:ud 0x04000200:ud // Message length = 1 DWORD, sent to GRF offset 32 registers #endif send (8) null<1>:ud m0 null:ud 0x03108002 // Send notification message to scoreboard kernel and (1) cr0.1:ud cr0.1:ud 0x00800000 // Clear preempt exception bit and (1) cr0.0:ud cr0.0:ud 0x7fffffff:ud // Exit SIP routine nop // Required by B-spec .end_code intel-driver-1.3.0/src/shaders/h264/mc/scoreboard_start_inter.asm000066400000000000000000000033551231401140700246630ustar00rootroot00000000000000/* * Scoreboard function for starting inter prediction kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__SCOREBOARD_START_INTER__) #define __SCOREBOARD_START_INTER__ // // Module name: scoreboard_start_inter.asm // // Scoreboard function for starting inter prediction kernels // This function is only used by inter prediction kernels to send message to // scoreboard in order to announce the inter kernel has started // // $Revision: 5 $ // $Date: 10/18/06 4:11p $ // scoreboard_start_inter: // First open message gateway since intra kernels need wake-up message to resume // mov (8) MSGHDRY0<1>:ud 0x00000000:ud // Initialize message header payload with 0 // Send a message with register base RegBase = r0 (0x0) and Size = 0x0 // 000 00000000 00000 00000 000 00000000 ==> 0000 0000 0000 0000 0000 0000 0000 0000 // --------------------------------------------------------------------------------- send (8) NULLREG MSGHDRY0 null:ud MSG_GW OGWMSGDSC // Derive the scoreboard location where the inter thread writes to // mov (8) MSGHDRY1<1>:ud 0x00000000:ud // Initialize message header payload with 0 // Compose M0.5:ud #include "set_SB_offset.asm" // Compose M0.0:ud, i.e. message payload or (1) MSGHDRY1.1<1>:uw sr0.0<0;1,0>:uw 0x0000:uw // Set EUID/TID bits + inter start bit send (8) NULLREG MSGHDRY1 null:ud MSG_GW FWDMSGDSC+NOTIFYMSG // Send "Inter start" message to scoreboard kernel RETURN #endif // !defined(__SCOREBOARD_START_INTER__) intel-driver-1.3.0/src/shaders/h264/mc/scoreboard_start_intra.asm000066400000000000000000000040161231401140700246520ustar00rootroot00000000000000/* * Scoreboard function for starting intra prediction kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #if !defined(__SCOREBOARD_START_INTRA__) #define __SCOREBOARD_START_INTRA__ // // Module name: scoreboard_start_intra.asm // // Scoreboard function for starting intra prediction kernels // This function is only used by intra prediction kernels to send message to // scoreboard in order to check dependency clearance // // $Revision: 5 $ // $Date: 10/18/06 4:11p $ // scoreboard_start_intra: // First open message gateway since intra kernels need wake-up message to resume // mov (8) MSGHDRY0<1>:ud 0x00000000:ud // Initialize message header payload with 0 // Send a message with register base RegBase = r0 (0x0) and Size = 0x0 // 000 00000000 00000 00000 000 00000000 ==> 0000 0000 0000 0000 0000 0000 0000 0000 // --------------------------------------------------------------------------------- and (1) MSGHDRY0.8<1>:uw REG_INTRA_PRED_AVAIL_FLAG_BYTE<0;1,0>:ub 0x1f:uw // Set lower word of key send (8) NULLREG MSGHDRY0 null:ud MSG_GW OGWMSGDSC // Send "check dependency" message to scoreboard thread // -------------------------- // Derive the scoreboard location where the intra thread writes to // mov (8) MSGHDRY1<1>:ud 0x00000000:ud // Initialize message header payload with 0 // Compose M0.5:ud #include "set_SB_offset.asm" // Compose M0.0:ud, i.e. message payload and (1) MSGHDRY1.0<1>:uw REG_INTRA_PRED_AVAIL_FLAG_BYTE<0;1,0>:ub 0x1f:uw // Set lower word of message or (1) MSGHDRY1.1<1>:uw sr0.0<0;1,0>:uw 0x8000:uw // Set EUID/TID bits + intra start bit send (8) NULLREG MSGHDRY1 null:ud MSG_GW FWDMSGDSC+NOTIFYMSG // Send "Intra start" message to scoreboard kernel RETURN #endif // !defined(__SCOREBOARD_START_INTRA__) intel-driver-1.3.0/src/shaders/h264/mc/scoreboard_update.asm000066400000000000000000000031461231401140700236050ustar00rootroot00000000000000/* * Scoreboard update function for decoding kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // // Module name: scoreboard_update.asm // // Scoreboard update function for decoding kernels // // This module is used by decoding kernels to send message to scoreboard to update the // "complete" status, thus the dependency of the MB can be cleared. // // $Revision: 6 $ // $Date: 10/16/06 5:19p $ // mov (8) MSGHDRY1<1>:ud 0x00000000:ud // Initialize message header payload with 0 // Compose M0.5:ud information add (1) MSGHDRY1.10<1>:uw r0.20:ub 0x0200:uw // Message length = 1 DWORD and (1) MSGHDRY1.11<1>:uw M05_STORE<0;1,0>:uw SB_MASK*4:uw // Retrieve stored value and wrap around scoreboard or (1) MSGHDRY1.0<1>:ud M05_STORE<0;1,0>:uw 0xc0000000:ud // Set "Completed" bits #ifndef BSDRESET_ENABLE #ifdef INTER_KERNEL mov (1) gREG_WRITE_COMMIT_Y<1>:ud gREG_WRITE_COMMIT_Y<0;1,0>:ud // Make sure Y write is committed mov (1) gREG_WRITE_COMMIT_UV<1>:ud gREG_WRITE_COMMIT_UV<0;1,0>:ud // Make sure U/V write is committed #else mov (1) REG_WRITE_COMMIT_Y<1>:ud REG_WRITE_COMMIT_Y<0;1,0>:ud // Make sure Y write is committed mov (1) REG_WRITE_COMMIT_UV<1>:ud REG_WRITE_COMMIT_UV<0;1,0>:ud // Make sure U/V write is committed #endif // INTER_KERNEL #endif // BSDRESET_ENABLE send (8) NULLREG MSGHDRY1 null:ud MSG_GW FWDMSGDSC // End of scoreboard_update intel-driver-1.3.0/src/shaders/h264/mc/set_SB_offset.asm000066400000000000000000000017501231401140700226440ustar00rootroot00000000000000/* * Common module to set offset into the scoreboard * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // // Module name: set_SB_offset.asm // // Common module to set offset into the scoreboard // Note: This is to encapsulate the way M0.5:ud in ForwardMsg is filled. // // $Revision: 2 $ // $Date: 10/16/06 5:19p $ // add (1) MSGHDRY1.10<1>:uw r0.20:ub 0x0200:uw // Message length = 1 DWORD add (16) acc0<1>:w r0.12<0;1,0>:uw -LEADING_THREAD:w // 0-based thread count derived from r0.6:ud shl (1) M05_STORE<1>:uw acc0<0;1,0>:uw 0x2:uw // Store for future "update" use, in DWORD unit and (16) acc0<1>:w acc0<16;16,1>:uw SB_MASK:uw // Wrap around scoreboard shl (1) MSGHDRY1.11<1>:uw acc0<0;1,0>:uw 0x2:uw // Convert to DWORD offset // End of set_SB_offsetintel-driver-1.3.0/src/shaders/h264/mc/weightedPred.asm000066400000000000000000000114201231401140700225250ustar00rootroot00000000000000/* * Weighted prediction of luminance and chrominance * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: WeightedPred.asm // // Weighted prediction of luminance and chrominance // //#if !defined(__WeightedPred__) // Make sure this is only included once //#define __WeightedPred__ and.z.f0.0 (1) gWEIGHTFLAG:w gWPREDFLAG:ub nWBIDIR_MASK:w cmp.e.f0.1 (1) null:w gPREDFLAG:w 2:w (-f0.0) jmpi INTERLABEL(WeightedPred) (f0.1) jmpi INTERLABEL(DefaultWeightedPred_BiPred) INTERLABEL(DefaultWeightedPred_UniPred): cmp.e.f0.0 (1) null:w gPREDFLAG:w 0:w (f0.0) jmpi INTERLABEL(Return_WeightedPred) // luma mov (32) gubYPRED(0)<2> gubINTPY1(0) {Compr} mov (32) gubYPRED(2)<2> gubINTPY1(2) {Compr} #ifndef MONO // chroma mov (32) gubCPRED(0)<2> gubINTPC1(0) {Compr} #endif jmpi INTERLABEL(Return_WeightedPred) INTERLABEL(DefaultWeightedPred_BiPred): // luma avg.sat (32) gubYPRED(0)<2> gubINTPY0(0) gubINTPY1(0) {Compr} avg.sat (32) gubYPRED(2)<2> gubINTPY0(2) gubINTPY1(2) {Compr} #ifndef MONO // chroma avg.sat (32) gubCPRED(0)<2> gubINTPC0(0) gubINTPC1(0) {Compr} #endif jmpi INTERLABEL(Return_WeightedPred) INTERLABEL(WeightedPred): cmp.e.f0.1 (1) null:w gWEIGHTFLAG:w 0x80:w (-f0.1) jmpi INTERLABEL(WeightedPred_Explicit) cmp.e.f0.0 (1) null:w gPREDFLAG:w 2:w (-f0.0) jmpi INTERLABEL(DefaultWeightedPred_UniPred) mov (2) gYADD<1>:w 32:w {NoDDClr} mov (2) gYSHIFT<1>:w 6:w {NoDDChk} mov (4) gOFFSET<1>:w 0:w mov (8) gWT0<2>:w r[pWGT,0]<0;2,1>:w jmpi INTERLABEL(WeightedPred_LOOP) // Explicit Prediction INTERLABEL(WeightedPred_Explicit): // WA for weighted prediction - 2007/09/06 #ifdef SW_W_128 // CTG SW WA cmp.e.f0.1 (8) null:ud r[pWGT,0]<8;8,1>:uw gudW128(0)<0;1,0> #else // ILK HW solution and.ne.f0.1 (8) null:uw r[pWGT,12]<0;1,0>:ub 0x88848421:v // Expand W=128 flag to all components. 2 MSB are don't care #endif asr.nz.f0.0 (2) gBIPRED<1>:w gPREDFLAG<0;1,0>:w 1:w asr (1) gWEIGHTFLAG:w gWEIGHTFLAG:w 6:w (-f0.0) mov (2) gPREDFLAG1<1>:w gPREDFLAG<0;1,0>:w (f0.0) mov (2) gPREDFLAG0<1>:ud 0x00010001:ud (-f0.0) add (2) gPREDFLAG0<1>:w -gPREDFLAG1<2;2,1>:w 1:w // WA for weighted prediction - 2007/09/06 (f0.1) mov (8) gWT0<1>:ud 0x00000080:ud (-f0.1) mov (8) gWT0<2>:w r[pWGT,0]<16;8,2>:b (-f0.1) mov (8) gO0<2>:w r[pWGT,1]<16;8,2>:b mul (16) gWT0<1>:w gWT0<16;16,1>:w gPREDFLAG0<0;4,1>:w // Compute addition cmp.e.f0.1 (2) null<1>:w gYWDENOM<2;2,1>:ub 0:w (-f0.1) shl (2) gW0<1>:w gWEIGHTFLAG<0;1,0>:w gYWDENOM<2;2,1>:ub (f0.1) mov (2) gW0<1>:w 0:w (-f0.1) asr (2) gW0<1>:w gW0<2;2,1>:w 1:w shl (2) gYADD<1>:w gW0<2;2,1>:w gBIPRED<0;1,0>:w (f0.1) add (2) gYADD<1>:w gYADD<2;2,1>:w gBIPRED<0;1,0>:w // Compute shift add (2) gYSHIFT<1>:w gYWDENOM<2;2,1>:ub gBIPRED<0;1,0>:w // Compute offset add (4) acc0<1>:w gO0<16;4,4>:w gO1<16;4,4>:w add (4) acc0<1>:w acc0<4;4,1>:w gBIPRED<0;1,0>:w asr (4) gOFFSET<1>:w acc0<4;4,1>:w gBIPRED<0;1,0>:w INTERLABEL(WeightedPred_LOOP): // luma $for(0;<4;2) { mul (16) acc0<1>:w gubINTPY0(%1) gWT0<0;1,0>:w mul (16) acc1<1>:w gubINTPY0(%1+1) gWT0<0;1,0>:w mac (16) acc0<1>:w gubINTPY1(%1) gWT1<0;1,0>:w mac (16) acc1<1>:w gubINTPY1(%1+1) gWT1<0;1,0>:w add (16) acc0<1>:w acc0<16;16,1>:w gYADD:w add (16) acc1<1>:w acc1<16;16,1>:w gYADD:w // Accumulator cannot be used as destination for ASR asr (16) gwINTERIM_BUF3(0)<1> acc0<16;16,1>:w gYSHIFT:w asr (16) gwINTERIM_BUF3(1)<1> acc1<16;16,1>:w gYSHIFT:w add.sat (16) gubYPRED(%1)<2> gwINTERIM_BUF3(0) gOFFSET:w add.sat (16) gubYPRED(%1+1)<2> gwINTERIM_BUF3(1) gOFFSET:w } #ifndef MONO // chroma mul (16) acc0<1>:w gubINTPC0(0) gUW0<0;2,4>:w mul (16) acc1<1>:w gubINTPC0(1) gUW0<0;2,4>:w mac (16) acc0<1>:w gubINTPC1(0) gUW1<0;2,4>:w mac (16) acc1<1>:w gubINTPC1(1) gUW1<0;2,4>:w add (16) acc0<1>:w acc0<16;16,1>:w gCADD:w add (16) acc1<1>:w acc1<16;16,1>:w gCADD:w // Accumulator cannot be used as destination for ASR asr (16) gwINTERIM_BUF3(0)<1> acc0<16;16,1>:w gCSHIFT:w asr (16) gwINTERIM_BUF3(1)<1> acc1<16;16,1>:w gCSHIFT:w add.sat (16) gubCPRED(0)<2> gwINTERIM_BUF3(0) gUOFFSET<0;2,1>:w add.sat (16) gubCPRED(1)<2> gwINTERIM_BUF3(1) gUOFFSET<0;2,1>:w #endif INTERLABEL(Return_WeightedPred): //#endif // !defined(__WeightedPred__) intel-driver-1.3.0/src/shaders/h264/mc/writeRecon_C_8x4.asm000066400000000000000000000031271231401140700232050ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: WriteRecon_C_8x4.asm // // $Revision: 10 $ // $Date: 10/03/06 5:28p $ // //#if !defined(__WRITERECON_C_8x4__) // Make sure this is only included once //#define __WRITERECON_C_8x4__ // TODO: Why did I use p0? #ifndef MONO add (1) p0:w pERRORC:w -16:w mov (16) mbMSGPAYLOADC(0,0)<2> r[p0,0]<32;16,2>:ub {NoDDClr} mov (16) mbMSGPAYLOADC(0,1)<2> r[p0,128]<32;16,2>:ub {NoDDChk} mov (16) mbMSGPAYLOADC(1,0)<2> r[p0,32]<32;16,2>:ub {NoDDClr} mov (16) mbMSGPAYLOADC(1,1)<2> r[p0,128+32]<32;16,2>:ub {NoDDChk} #else // defined(MONO) mov (16) mbMSGPAYLOADC(0)<1> 0x80808080:ud {Compr} #endif // !defined(MONO) #if defined(MBAFF) add (1) pMSGDSC:ud gFIELDFLAGS:uw MSG_LEN(2)+nDWBWMSGDSC+nBDIX_DESTC+ENWRCOM:ud #elif defined(FIELD) add (1) pMSGDSC:ud gFIELDFLAGS:uw MSG_LEN(2)+nDWBWMSGDSC_TF+nBDIX_DESTC+ENWRCOM:ud #endif asr (1) gMSGSRC.1:d gMSGSRC.1:d 1:w {NoDDClr} mov (1) gMSGSRC.2:ud 0x0003000f:ud {NoDDChk} // NV12 (16x4) #if defined(FRAME) send (8) gREG_WRITE_COMMIT_UV<1>:ud mMSGHDRCW gMSGSRC<8;8,1>:ud DAPWRITE MSG_LEN(2)+nDWBWMSGDSC+nBDIX_DESTC+ENWRCOM #else send (8) gREG_WRITE_COMMIT_UV<1>:ud mMSGHDRCW gMSGSRC<8;8,1>:ud DAPWRITE pMSGDSC:ud #endif // defined(FRAME) //#endif // !defined(__WRITERECON_C_8x4__) intel-driver-1.3.0/src/shaders/h264/mc/writeRecon_YC.asm000066400000000000000000000055221231401140700226340ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: WriteRecon_YC.asm // // $Revision: 10 $ // $Date: 10/03/06 5:28p $ // //#if !defined(__WRITERECON_YC__) // Make sure this is only included once //#define __WRITERECON_YC__ // TODO: Merge two inst to one. mov (1) p0:w nOFFSET_ERRORY:w mov (1) p1:w nOFFSET_ERRORY+128:w $for(0; <4; 1) { mov (16) mbMSGPAYLOADY(%1,0)<1> r[p0,%1*32+0]<8,2>:ub {NoDDClr} mov (16) mbMSGPAYLOADY(%1,16)<1> r[p0,%1*32+16]<8,2>:ub {NoDDChk} } $for(0; <4; 1) { mov (16) mbMSGPAYLOADY(%1+4,0)<1> r[p0,%1*32+256]<8,2>:ub {NoDDClr} mov (16) mbMSGPAYLOADY(%1+4,16)<1> r[p0,%1*32+16+256]<8,2>:ub {NoDDChk} } #if defined(MBAFF) add (1) pMSGDSC:ud gFIELDFLAGS:uw MSG_LEN(8)+nDWBWMSGDSC+nBDIX_DESTY+ENWRCOM:ud #elif defined(FIELD) add (1) pMSGDSC:ud gFIELDFLAGS:uw MSG_LEN(8)+nDWBWMSGDSC_TF+nBDIX_DESTY+ENWRCOM:ud #endif mov (2) gMSGSRC.0<1>:d gX<2;2,1>:w {NoDDClr} mov (1) gMSGSRC.2:ud 0x000f000f:ud {NoDDChk} #if defined(FRAME) send (8) gREG_WRITE_COMMIT_Y<1>:ud mMSGHDRYW gMSGSRC<8;8,1>:ud DAPWRITE MSG_LEN(8)+nDWBWMSGDSC+nBDIX_DESTY+ENWRCOM #else send (8) gREG_WRITE_COMMIT_Y<1>:ud mMSGHDRYW gMSGSRC<8;8,1>:ud DAPWRITE pMSGDSC:ud #endif #ifndef MONO // TODO: Why did I use p0? mov (1) p0:w nOFFSET_ERRORC:w mov (16) mbMSGPAYLOADC(0,0)<2> r[p0,0]<32;16,2>:ub {NoDDClr} mov (16) mbMSGPAYLOADC(0,1)<2> r[p0,128]<32;16,2>:ub {NoDDChk} mov (16) mbMSGPAYLOADC(1,0)<2> r[p0,32]<32;16,2>:ub {NoDDClr} mov (16) mbMSGPAYLOADC(1,1)<2> r[p0,128+32]<32;16,2>:ub {NoDDChk} mov (16) mbMSGPAYLOADC(2,0)<2> r[p0,64]<32;16,2>:ub {NoDDClr} mov (16) mbMSGPAYLOADC(2,1)<2> r[p0,128+64]<32;16,2>:ub {NoDDChk} mov (16) mbMSGPAYLOADC(3,0)<2> r[p0,96]<32;16,2>:ub {NoDDClr} mov (16) mbMSGPAYLOADC(3,1)<2> r[p0,128+96]<32;16,2>:ub {NoDDChk} #if defined(MBAFF) add (1) pMSGDSC:ud gFIELDFLAGS:uw MSG_LEN(4)+nDWBWMSGDSC+nBDIX_DESTC+ENWRCOM:ud #elif defined(FIELD) add (1) pMSGDSC:ud gFIELDFLAGS:uw MSG_LEN(4)+nDWBWMSGDSC_TF+nBDIX_DESTC+ENWRCOM:ud #endif asr (1) gMSGSRC.1:d gMSGSRC.1:d 1:w {NoDDClr} mov (1) gMSGSRC.2:ud 0x0007000f:ud {NoDDChk} // NV12 (16x4) #if defined(FRAME) send (8) gREG_WRITE_COMMIT_UV<1>:ud mMSGHDRCW gMSGSRC<8;8,1>:ud DAPWRITE MSG_LEN(4)+nDWBWMSGDSC+nBDIX_DESTC+ENWRCOM #else send (8) gREG_WRITE_COMMIT_UV<1>:ud mMSGHDRCW gMSGSRC<8;8,1>:ud DAPWRITE pMSGDSC:ud #endif // defined(FRAME) #endif // !defined(MONO) //#endif // !defined(__WRITERECON_YC__) intel-driver-1.3.0/src/shaders/h264/mc/writeRecon_Y_16x8.asm000066400000000000000000000025631231401140700233210ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Kernel name: WriteRecon_Y_16x8.asm // // $Revision: 10 $ // $Date: 10/03/06 5:28p $ // //#if !defined(__WRITERECON_Y_16x8__) // Make sure this is only included once //#define __WRITERECON_Y_16x8__ add (1) p0:w pERRORY:w -256:w add (1) p1:w pERRORY:w -128:w $for(0; <4; 1) { mov (16) mbMSGPAYLOADY(%1,0)<1> r[p0,%1*32+0]<8,2>:ub {NoDDClr} mov (16) mbMSGPAYLOADY(%1,16)<1> r[p0,%1*32+16]<8,2>:ub {NoDDChk} } #if defined(MBAFF) add (1) pMSGDSC:ud gFIELDFLAGS:uw MSG_LEN(4)+nDWBWMSGDSC+nBDIX_DESTY+ENWRCOM:ud #elif defined(FIELD) add (1) pMSGDSC:ud gFIELDFLAGS:uw MSG_LEN(4)+nDWBWMSGDSC_TF+nBDIX_DESTY+ENWRCOM:ud #endif mov (2) gMSGSRC.0<1>:d gX<2;2,1>:w {NoDDClr} mov (1) gMSGSRC.2:ud 0x0007000f:ud {NoDDChk} #if defined(FRAME) send (8) gREG_WRITE_COMMIT_Y<1>:ud mMSGHDRYW gMSGSRC<8;8,1>:ud DAPWRITE MSG_LEN(4)+nDWBWMSGDSC+nBDIX_DESTY+ENWRCOM #else send (8) gREG_WRITE_COMMIT_Y<1>:ud mMSGHDRYW gMSGSRC<8;8,1>:ud DAPWRITE pMSGDSC:ud #endif //#endif // !defined(__WRITERECON_Y_16x8__) intel-driver-1.3.0/src/shaders/mpeg2/000077500000000000000000000000001231401140700173425ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/mpeg2/Makefile.am000066400000000000000000000001641231401140700213770ustar00rootroot00000000000000SUBDIRS = vld # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/mpeg2/vld/000077500000000000000000000000001231401140700201275ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/mpeg2/vld/Makefile.am000066400000000000000000000060151231401140700221650ustar00rootroot00000000000000INTEL_G4I = \ addidct.g4i \ do_iq_intra.g4i \ do_iq_non_intra.g4i \ field_addidct.g4i \ field_motion_uv.g4i \ field_motion_y.g4i \ field_read_x0y0_uv.g4i \ field_read_x0y0_y.g4i \ field_read_x0y1_uv.g4i \ field_read_x0y1_y.g4i \ field_read_x1y0_uv.g4i \ field_read_x1y0_y.g4i \ field_read_x1y1_uv.g4i \ field_read_x1y1_y.g4i \ idct.g4i \ iq_intra.g4i \ iq_non_intra.g4i \ motion_field_uv.g4i \ motion_field_y.g4i \ motion_frame_uv.g4i \ motion_frame_y.g4i \ read_field_x0y0_uv.g4i \ read_field_x0y0_y.g4i \ read_field_x0y1_uv.g4i \ read_field_x0y1_y.g4i \ read_field_x1y0_uv.g4i \ read_field_x1y0_y.g4i \ read_field_x1y1_uv.g4i \ read_field_x1y1_y.g4i \ read_frame_x0y0_uv.g4i \ read_frame_x0y0_y.g4i \ read_frame_x0y1_uv.g4i \ read_frame_x0y1_y.g4i \ read_frame_x1y0_uv.g4i \ read_frame_x1y0_y.g4i \ read_frame_x1y1_uv.g4i \ read_frame_x1y1_y.g4i \ $(NULL) INTEL_G4A = frame_intra.g4a \ frame_frame_pred_forward.g4a \ frame_frame_pred_backward.g4a \ frame_frame_pred_bidirect.g4a \ frame_field_pred_forward.g4a \ frame_field_pred_backward.g4a \ frame_field_pred_bidirect.g4a \ lib.g4a \ field_intra.g4a \ field_forward.g4a \ field_forward_16x8.g4a \ field_backward.g4a \ field_backward_16x8.g4a \ field_bidirect.g4a \ field_bidirect_16x8.g4a \ null.g4a INTEL_G4S = $(INTEL_G4A:%.g4a=%.g4s) INTEL_G4B = frame_intra.g4b \ frame_frame_pred_forward.g4b \ frame_frame_pred_backward.g4b \ frame_frame_pred_bidirect.g4b \ frame_field_pred_forward.g4b \ frame_field_pred_backward.g4b \ frame_field_pred_bidirect.g4b \ lib.g4b \ field_intra.g4b \ field_forward.g4b \ field_forward_16x8.g4b \ field_backward.g4b \ field_backward_16x8.g4b \ field_bidirect.g4b \ field_bidirect_16x8.g4b INTEL_G4B_GEN5 = frame_intra.g4b.gen5 \ frame_frame_pred_forward.g4b.gen5 \ frame_frame_pred_backward.g4b.gen5 \ frame_frame_pred_bidirect.g4b.gen5 \ frame_field_pred_forward.g4b.gen5 \ frame_field_pred_backward.g4b.gen5 \ frame_field_pred_bidirect.g4b.gen5 \ lib.g4b.gen5 \ field_intra.g4b.gen5 \ field_forward.g4b.gen5 \ field_forward_16x8.g4b.gen5 \ field_backward.g4b.gen5 \ field_backward_16x8.g4b.gen5 \ field_bidirect.g4b.gen5 \ field_bidirect_16x8.g4b.gen5 TARGETS = if HAVE_GEN4ASM TARGETS += $(INTEL_G4B) TARGETS += $(INTEL_G4B_GEN5) endif all-local: $(TARGETS) SUFFIXES = .g4a .g4s .g4b .g4b.gen5 if HAVE_GEN4ASM $(INTEL_G4S): $(INTEL_G4A) $(INTEL_G4I) .g4a.g4s: $(AM_V_GEN)m4 $< > $@ .g4s.g4b: $(AM_V_GEN)$(GEN4ASM) -o $@ $< .g4s.g4b.gen5: $(AM_V_GEN)$(GEN4ASM) -g 5 -o $@ $< endif CLEANFILES = $(INTEL_G4S) EXTRA_DIST = \ $(INTEL_G4A) \ $(INTEL_G4B) \ $(INTEL_G4B_GEN5) \ $(INTEL_G4I) \ $(NULL) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/mpeg2/vld/addidct.g4i000066400000000000000000000157111231401140700221350ustar00rootroot00000000000000/* * Copyright © 2008 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g32: message descriptor for reading reference data g58~g81:reference data g82: thread payload backup g83~g106:IDCT data */ mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; //restore x and y and.nz (1) null g82.2<1,1,1>UW 0x20UW {align1}; //dct_type (f0) jmpi field_dct; add (16) g58.0<1>W g83.0<16,16,1>W g58.0<16,16,2>UB {align1}; add (16) g59.0<1>W g84.0<16,16,1>W g59.0<16,16,2>UB {align1}; add (16) g60.0<1>W g85.0<16,16,1>W g60.0<16,16,2>UB {align1}; add (16) g61.0<1>W g86.0<16,16,1>W g61.0<16,16,2>UB {align1}; add (16) g62.0<1>W g87.0<16,16,1>W g62.0<16,16,2>UB {align1}; add (16) g63.0<1>W g88.0<16,16,1>W g63.0<16,16,2>UB {align1}; add (16) g64.0<1>W g89.0<16,16,1>W g64.0<16,16,2>UB {align1}; add (16) g65.0<1>W g90.0<16,16,1>W g65.0<16,16,2>UB {align1}; add (16) g66.0<1>W g91.0<16,16,1>W g66.0<16,16,2>UB {align1}; add (16) g67.0<1>W g92.0<16,16,1>W g67.0<16,16,2>UB {align1}; add (16) g68.0<1>W g93.0<16,16,1>W g68.0<16,16,2>UB {align1}; add (16) g69.0<1>W g94.0<16,16,1>W g69.0<16,16,2>UB {align1}; add (16) g70.0<1>W g95.0<16,16,1>W g70.0<16,16,2>UB {align1}; add (16) g71.0<1>W g96.0<16,16,1>W g71.0<16,16,2>UB {align1}; add (16) g72.0<1>W g97.0<16,16,1>W g72.0<16,16,2>UB {align1}; add (16) g73.0<1>W g98.0<16,16,1>W g73.0<16,16,2>UB {align1}; jmpi write_back; field_dct: add (16) g58.0<1>W g83.0<16,16,1>W g58.0<16,16,2>UB {align1}; add (16) g59.0<1>W g91.0<16,16,1>W g59.0<16,16,2>UB {align1}; add (16) g60.0<1>W g84.0<16,16,1>W g60.0<16,16,2>UB {align1}; add (16) g61.0<1>W g92.0<16,16,1>W g61.0<16,16,2>UB {align1}; add (16) g62.0<1>W g85.0<16,16,1>W g62.0<16,16,2>UB {align1}; add (16) g63.0<1>W g93.0<16,16,1>W g63.0<16,16,2>UB {align1}; add (16) g64.0<1>W g86.0<16,16,1>W g64.0<16,16,2>UB {align1}; add (16) g65.0<1>W g94.0<16,16,1>W g65.0<16,16,2>UB {align1}; add (16) g66.0<1>W g87.0<16,16,1>W g66.0<16,16,2>UB {align1}; add (16) g67.0<1>W g95.0<16,16,1>W g67.0<16,16,2>UB {align1}; add (16) g68.0<1>W g88.0<16,16,1>W g68.0<16,16,2>UB {align1}; add (16) g69.0<1>W g96.0<16,16,1>W g69.0<16,16,2>UB {align1}; add (16) g70.0<1>W g89.0<16,16,1>W g70.0<16,16,2>UB {align1}; add (16) g71.0<1>W g97.0<16,16,1>W g71.0<16,16,2>UB {align1}; add (16) g72.0<1>W g90.0<16,16,1>W g72.0<16,16,2>UB {align1}; add (16) g73.0<1>W g98.0<16,16,1>W g73.0<16,16,2>UB {align1}; write_back: mov (1) g31.8<1>UD 0x00F000FUD {align1}; mov.sat (16) g58.0<2>UB g58.0<16,16,1>W {align1}; mov.sat (16) g59.0<2>UB g59.0<16,16,1>W {align1}; mov.sat (16) g60.0<2>UB g60.0<16,16,1>W {align1}; mov.sat (16) g61.0<2>UB g61.0<16,16,1>W {align1}; mov.sat (16) g62.0<2>UB g62.0<16,16,1>W {align1}; mov.sat (16) g63.0<2>UB g63.0<16,16,1>W {align1}; mov.sat (16) g64.0<2>UB g64.0<16,16,1>W {align1}; mov.sat (16) g65.0<2>UB g65.0<16,16,1>W {align1}; mov.sat (16) g66.0<2>UB g66.0<16,16,1>W {align1}; mov.sat (16) g67.0<2>UB g67.0<16,16,1>W {align1}; mov.sat (16) g68.0<2>UB g68.0<16,16,1>W {align1}; mov.sat (16) g69.0<2>UB g69.0<16,16,1>W {align1}; mov.sat (16) g70.0<2>UB g70.0<16,16,1>W {align1}; mov.sat (16) g71.0<2>UB g71.0<16,16,1>W {align1}; mov.sat (16) g72.0<2>UB g72.0<16,16,1>W {align1}; mov.sat (16) g73.0<2>UB g73.0<16,16,1>W {align1}; mov (16) m1.0<1>UB g58.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g59.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g60.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g61.0<16,16,2>UB {align1}; mov (16) m3.0<1>UB g62.0<16,16,2>UB {align1}; mov (16) m3.16<1>UB g63.0<16,16,2>UB {align1}; mov (16) m4.0<1>UB g64.0<16,16,2>UB {align1}; mov (16) m4.16<1>UB g65.0<16,16,2>UB {align1}; mov (16) m5.0<1>UB g66.0<16,16,2>UB {align1}; mov (16) m5.16<1>UB g67.0<16,16,2>UB {align1}; mov (16) m6.0<1>UB g68.0<16,16,2>UB {align1}; mov (16) m6.16<1>UB g69.0<16,16,2>UB {align1}; mov (16) m7.0<1>UB g70.0<16,16,2>UB {align1}; mov (16) m7.16<1>UB g71.0<16,16,2>UB {align1}; mov (16) m8.0<1>UB g72.0<16,16,2>UB {align1}; mov (16) m8.16<1>UB g73.0<16,16,2>UB {align1}; send (16) 0 acc0<1>UW g31<8,8,1>UW write(0,0,2,0) mlen 9 rlen 0 {align1}; //U mov (1) g31.8<1>UD 0x0070007UD { align1 }; shr (2) g31.0<1>UD g31.0<2,2,1>UD 1D {align1}; add (16) g74.0<1>W g99.0<16,16,1>W g74.0<16,16,1>UW {align1}; add (16) g75.0<1>W g100.0<16,16,1>W g75.0<16,16,1>UW {align1}; add (16) g76.0<1>W g101.0<16,16,1>W g76.0<16,16,1>UW {align1}; add (16) g77.0<1>W g102.0<16,16,1>W g77.0<16,16,1>UW {align1}; mov.sat (16) g74.0<2>UB g74.0<16,16,1>W {align1}; mov.sat (16) g75.0<2>UB g75.0<16,16,1>W {align1}; mov.sat (16) g76.0<2>UB g76.0<16,16,1>W {align1}; mov.sat (16) g77.0<2>UB g77.0<16,16,1>W {align1}; mov (16) m1.0<1>UB g74.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g75.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g76.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g77.0<16,16,2>UB {align1}; send (16) 0 acc0<1>UW g31<8,8,1>UW write(1, 0, 2, 0) mlen 3 rlen 0 { align1 }; //V add (16) g78.0<1>UW g103.0<16,16,1>W g78.0<16,16,1>UW {align1}; add (16) g79.0<1>UW g104.0<16,16,1>W g79.0<16,16,1>UW {align1}; add (16) g80.0<1>UW g105.0<16,16,1>W g80.0<16,16,1>UW {align1}; add (16) g81.0<1>UW g106.0<16,16,1>W g81.0<16,16,1>UW {align1}; mov.sat (16) g78.0<2>UB g78.0<16,16,1>W {align1}; mov.sat (16) g79.0<2>UB g79.0<16,16,1>W {align1}; mov.sat (16) g80.0<2>UB g80.0<16,16,1>W {align1}; mov.sat (16) g81.0<2>UB g81.0<16,16,1>W {align1}; mov (16) m1.0<1>UB g78.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g79.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g80.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g81.0<16,16,2>UB {align1}; send (16) 0 acc0<1>UW g31<8,8,1>UW write(2, 0, 2, 0) mlen 3 rlen 0 { align1 }; send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/do_iq_intra.g4i000066400000000000000000000055631231401140700230350ustar00rootroot00000000000000/* * Copyright © 2008 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g112~g115: intra IQ matrix in UW format (in order to use instruction compress), copys from g1~g2 g[a0.0]:DCT data of a block g125: ip before jump if(v==0 && u==0 && intra_mb) F''[v][u] = QF[v][u] * intra_dc_mult else F''[v][u] = (QF[v][u]*W[w][v][u]*quantiser_scale*2)/32 */ DO_IQ_INTRA: add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1}; mov (1) g111.0<1>W g[a0.0]<1,1,1>W {align1}; mul (16) g116.0<1>D g[a0.0]<8,8,1>W g112.0<8,8,1>UW {align1 compr}; mul (16) g116.0<1>D g116.0<8,8,1>D g109.0<8,8,0>UW {align1 compr}; asr (16) g116.0<1>D g116.0<8,8,1>D 4UW {align1 compr}; mul (1) g116.0<1>D g111<1,1,1>W g109.4<1,1,1>UW {align1}; //intra_dc_mult add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1}; mul (16) g118.0<1>D g[a0.0]<8,8,1>W g113.0<8,8,1>UW {align1 compr}; mul (16) g118.0<1>D g118.0<8,8,1>D g109.0<8,8,0>UW {align1 compr}; asr (16) g118.0<1>D g118.0<8,8,1>D 4UW {align1 compr}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1}; mul (16) g120.0<1>D g[a0.0]<8,8,1>W g114.0<8,8,1>UW {align1 compr}; mul (16) g120.0<1>D g120.0<8,8,1>D g109.0<8,8,0>UW {align1 compr}; asr (16) g120.0<1>D g120.0<8,8,1>D 4UW {align1 compr}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1}; mul (16) g122.0<1>D g[a0.0]<8,8,1>W g115.0<8,8,1>UW {align1 compr}; mul (16) g122.0<1>D g122.0<8,8,1>D g109.0<8,8,0>UW {align1 compr}; asr (16) g122.0<1>D g122.0<8,8,1>D 4UW {align1 compr}; add (1) ip g125.0<1,1,1>UD 0x20UD {align1}; //jump back intel-driver-1.3.0/src/shaders/mpeg2/vld/do_iq_non_intra.g4i000066400000000000000000000052771231401140700237110ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g112~g115: intra IQ matrix in UW format (in order to use instruction compress), copys from g1~g2 g[a0.0]:DCT data of a block g125: ip before jump F''[v][u]=(((QF[v][u]*2)+Sign(QF[v][u])) * W[w][v][u] * quantiser_scale)/32; */ DO_IQ_NON_INTRA: add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1}; mul (16) g116.0<1>D g[a0.0]<8,8,1>W g112.0<8,8,1>UW {align1 compr}; mul (16) g116.0<1>D g116.0<8,8,1>D g109.0<8,8,0>UW {align1 compr}; asr (16) g116.0<1>D g116.0<8,8,1>D 4UW {align1 compr}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1}; mul (16) g118.0<1>D g[a0.0]<8,8,1>W g113.0<8,8,1>UW {align1 compr}; mul (16) g118.0<1>D g118.0<8,8,1>D g109.0<8,8,0>UW {align1 compr}; asr (16) g118.0<1>D g118.0<8,8,1>D 4UW {align1 compr}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1}; mul (16) g120.0<1>D g[a0.0]<8,8,1>W g114.0<8,8,1>UW {align1 compr}; mul (16) g120.0<1>D g120.0<8,8,1>D g109.0<8,8,0>UW {align1 compr}; asr (16) g120.0<1>D g120.0<8,8,1>D 4UW {align1 compr}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1}; mul (16) g122.0<1>D g[a0.0]<8,8,1>W g115.0<8,8,1>UW {align1 compr}; mul (16) g122.0<1>D g122.0<8,8,1>D g109.0<8,8,0>UW {align1 compr}; asr (16) g122.0<1>D g122.0<8,8,1>D 4UW {align1 compr}; add (1) ip g125.0<1,1,1>UD 0x20UD {align1}; //jump back intel-driver-1.3.0/src/shaders/mpeg2/vld/field_addidct.g4i000066400000000000000000000157121231401140700233010ustar00rootroot00000000000000/* * Copyright © 2008 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g32: message descriptor for reading reference data g58~g81:reference data g82: thread payload backup g83~g106:IDCT data */ mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; //restore x and y and.nz (1) null g82.2<1,1,1>UW 0x20UW {align1}; //dct_type (f0) jmpi field_dct; add (16) g58.0<1>W g83.0<16,16,1>W g58.0<16,16,2>UB {align1}; add (16) g59.0<1>W g84.0<16,16,1>W g59.0<16,16,2>UB {align1}; add (16) g60.0<1>W g85.0<16,16,1>W g60.0<16,16,2>UB {align1}; add (16) g61.0<1>W g86.0<16,16,1>W g61.0<16,16,2>UB {align1}; add (16) g62.0<1>W g87.0<16,16,1>W g62.0<16,16,2>UB {align1}; add (16) g63.0<1>W g88.0<16,16,1>W g63.0<16,16,2>UB {align1}; add (16) g64.0<1>W g89.0<16,16,1>W g64.0<16,16,2>UB {align1}; add (16) g65.0<1>W g90.0<16,16,1>W g65.0<16,16,2>UB {align1}; add (16) g66.0<1>W g91.0<16,16,1>W g66.0<16,16,2>UB {align1}; add (16) g67.0<1>W g92.0<16,16,1>W g67.0<16,16,2>UB {align1}; add (16) g68.0<1>W g93.0<16,16,1>W g68.0<16,16,2>UB {align1}; add (16) g69.0<1>W g94.0<16,16,1>W g69.0<16,16,2>UB {align1}; add (16) g70.0<1>W g95.0<16,16,1>W g70.0<16,16,2>UB {align1}; add (16) g71.0<1>W g96.0<16,16,1>W g71.0<16,16,2>UB {align1}; add (16) g72.0<1>W g97.0<16,16,1>W g72.0<16,16,2>UB {align1}; add (16) g73.0<1>W g98.0<16,16,1>W g73.0<16,16,2>UB {align1}; jmpi write_back; field_dct: add (16) g58.0<1>W g83.0<16,16,1>W g58.0<16,16,2>UB {align1}; add (16) g59.0<1>W g91.0<16,16,1>W g59.0<16,16,2>UB {align1}; add (16) g60.0<1>W g84.0<16,16,1>W g60.0<16,16,2>UB {align1}; add (16) g61.0<1>W g92.0<16,16,1>W g61.0<16,16,2>UB {align1}; add (16) g62.0<1>W g85.0<16,16,1>W g62.0<16,16,2>UB {align1}; add (16) g63.0<1>W g93.0<16,16,1>W g63.0<16,16,2>UB {align1}; add (16) g64.0<1>W g86.0<16,16,1>W g64.0<16,16,2>UB {align1}; add (16) g65.0<1>W g94.0<16,16,1>W g65.0<16,16,2>UB {align1}; add (16) g66.0<1>W g87.0<16,16,1>W g66.0<16,16,2>UB {align1}; add (16) g67.0<1>W g95.0<16,16,1>W g67.0<16,16,2>UB {align1}; add (16) g68.0<1>W g88.0<16,16,1>W g68.0<16,16,2>UB {align1}; add (16) g69.0<1>W g96.0<16,16,1>W g69.0<16,16,2>UB {align1}; add (16) g70.0<1>W g89.0<16,16,1>W g70.0<16,16,2>UB {align1}; add (16) g71.0<1>W g97.0<16,16,1>W g71.0<16,16,2>UB {align1}; add (16) g72.0<1>W g90.0<16,16,1>W g72.0<16,16,2>UB {align1}; add (16) g73.0<1>W g98.0<16,16,1>W g73.0<16,16,2>UB {align1}; write_back: mov (1) g31.8<1>UD 0x00F000FUD {align1}; mov.sat (16) g58.0<2>UB g58.0<16,16,1>W {align1}; mov.sat (16) g59.0<2>UB g59.0<16,16,1>W {align1}; mov.sat (16) g60.0<2>UB g60.0<16,16,1>W {align1}; mov.sat (16) g61.0<2>UB g61.0<16,16,1>W {align1}; mov.sat (16) g62.0<2>UB g62.0<16,16,1>W {align1}; mov.sat (16) g63.0<2>UB g63.0<16,16,1>W {align1}; mov.sat (16) g64.0<2>UB g64.0<16,16,1>W {align1}; mov.sat (16) g65.0<2>UB g65.0<16,16,1>W {align1}; mov.sat (16) g66.0<2>UB g66.0<16,16,1>W {align1}; mov.sat (16) g67.0<2>UB g67.0<16,16,1>W {align1}; mov.sat (16) g68.0<2>UB g68.0<16,16,1>W {align1}; mov.sat (16) g69.0<2>UB g69.0<16,16,1>W {align1}; mov.sat (16) g70.0<2>UB g70.0<16,16,1>W {align1}; mov.sat (16) g71.0<2>UB g71.0<16,16,1>W {align1}; mov.sat (16) g72.0<2>UB g72.0<16,16,1>W {align1}; mov.sat (16) g73.0<2>UB g73.0<16,16,1>W {align1}; mov (16) m1.0<1>UB g58.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g59.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g60.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g61.0<16,16,2>UB {align1}; mov (16) m3.0<1>UB g62.0<16,16,2>UB {align1}; mov (16) m3.16<1>UB g63.0<16,16,2>UB {align1}; mov (16) m4.0<1>UB g64.0<16,16,2>UB {align1}; mov (16) m4.16<1>UB g65.0<16,16,2>UB {align1}; mov (16) m5.0<1>UB g66.0<16,16,2>UB {align1}; mov (16) m5.16<1>UB g67.0<16,16,2>UB {align1}; mov (16) m6.0<1>UB g68.0<16,16,2>UB {align1}; mov (16) m6.16<1>UB g69.0<16,16,2>UB {align1}; mov (16) m7.0<1>UB g70.0<16,16,2>UB {align1}; mov (16) m7.16<1>UB g71.0<16,16,2>UB {align1}; mov (16) m8.0<1>UB g72.0<16,16,2>UB {align1}; mov (16) m8.16<1>UB g73.0<16,16,2>UB {align1}; send (16) 0 acc0<1>UW g31<8,8,1>UW write(0,0,2,0) mlen 9 rlen 0 {align1}; //U mov (1) g31.8<1>UD 0x0070007UD { align1 }; shr (2) g31.0<1>UD g31.0<2,2,1>UD 1D {align1}; add (16) g74.0<1>W g99.0<16,16,1>W g74.0<16,16,1>UW {align1}; add (16) g75.0<1>W g100.0<16,16,1>W g75.0<16,16,1>UW {align1}; add (16) g76.0<1>W g101.0<16,16,1>W g76.0<16,16,1>UW {align1}; add (16) g77.0<1>W g102.0<16,16,1>W g77.0<16,16,1>UW {align1}; mov.sat (16) g74.0<2>UB g74.0<16,16,1>W {align1}; mov.sat (16) g75.0<2>UB g75.0<16,16,1>W {align1}; mov.sat (16) g76.0<2>UB g76.0<16,16,1>W {align1}; mov.sat (16) g77.0<2>UB g77.0<16,16,1>W {align1}; mov (16) m1.0<1>UB g74.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g75.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g76.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g77.0<16,16,2>UB {align1}; send (16) 0 acc0<1>UW g31<8,8,1>UW write(1, 0, 2, 0) mlen 3 rlen 0 { align1 }; //V add (16) g78.0<1>UW g103.0<16,16,1>W g78.0<16,16,1>UW {align1}; add (16) g79.0<1>UW g104.0<16,16,1>W g79.0<16,16,1>UW {align1}; add (16) g80.0<1>UW g105.0<16,16,1>W g80.0<16,16,1>UW {align1}; add (16) g81.0<1>UW g106.0<16,16,1>W g81.0<16,16,1>UW {align1}; mov.sat (16) g78.0<2>UB g78.0<16,16,1>W {align1}; mov.sat (16) g79.0<2>UB g79.0<16,16,1>W {align1}; mov.sat (16) g80.0<2>UB g80.0<16,16,1>W {align1}; mov.sat (16) g81.0<2>UB g81.0<16,16,1>W {align1}; mov (16) m1.0<1>UB g78.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g79.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g80.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g81.0<16,16,2>UB {align1}; send (16) 0 acc0<1>UW g31<8,8,1>UW write(2, 0, 2, 0) mlen 3 rlen 0 { align1 }; send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_backward.g4a000066400000000000000000000073151231401140700234530ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g32: message descriptor for reading reference data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; mov (1) g126.8<1>UD ip {align1}; mov (1) ip g21.0<1,1,1>UD {align1}; //Y of top field first_field_picture: asr (2) g31.14<1>W g82.20<2,2,1>W 1W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; mov (1) g32.28<1>UD 0UD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x2000UW {align1}; //motion vertical field select forward (f0) mov (1) g32.28<1>UD 1UD {align1}; shl (1) g32.4<1>UD g32.4<1,1,1>UD 1UD {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD g32.28<1,1,1>UD {align1}; define(`surface',`7') define(`mv1',`g82.20') define(`mv2',`g82.22') include(`field_motion_y.g4i') //UV of top field shr (2) g31.0<1>UD g31.0<2,2,1>UD 1UD {align1}; asr (2) g31.14<1>W g82.20<2,2,1>W 2W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; mov (1) g32.28<1>UD 0UD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x2000UW {align1}; //motion vertical field select forward (f0) mov (1) g32.28<1>UD 1UD {align1}; shl (1) g32.4<1>UD g32.4<1,1,1>UD 1UD {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD g32.28<1,1,1>UD {align1}; define(`surface_u', `8') define(`surface_v', `9') define(`mv1',`g82.20') define(`mv2',`g82.22') include(`field_motion_uv.g4i') jmpi field_addidct; second_field_picture: //Y of bottom field asr (2) g31.14<1>W g82.20<2,2,1>W 1W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; shl (1) g32.4<1>UD g32.4<1,1,1>UD 1UD {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD g32.28<1,1,1>UD {align1}; define(`surface',`3') define(`mv1',`g82.20') define(`mv2',`g82.22') include(`field_motion_y.g4i') //UV of bottom field shr (2) g31.0<1>UD g31.0<2,2,1>UD 1UD {align1}; asr (2) g31.14<1>W g82.20<2,2,1>W 2W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; shl (1) g32.4<1>UD g32.4<1,1,1>UD 1UD {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD g32.28<1,1,1>UD {align1}; define(`surface_u', `10') define(`surface_v', `11') define(`mv1',`g82.20') define(`mv2',`g82.22') include(`field_motion_uv.g4i') field_addidct: include(`field_addidct.g4i') out: send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_backward.g4b000066400000000000000000001212431231401140700234510ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20002dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000006a }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000004f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a007 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10500 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10540 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10580 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c0 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10600 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10640 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10680 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10501 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10541 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10581 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c1 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10601 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10641 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10681 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c1 }, { 0x00800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x00800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x00800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x00800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x00800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x00800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x00800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x00800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a007 }, { 0x00800040, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10500 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10540 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10580 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c0 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10600 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10640 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10680 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10501 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10541 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10581 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c1 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10601 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10641 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10681 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x00800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x00800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x00800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x00800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x00800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x00800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x00800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x00800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000039 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a007 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b106c0 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a007 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b10680, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00800001, 0x28400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b10680, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20003dbc, 0x00210a54, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005c }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000043 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a008 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a009 }, { 0x00600040, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0520 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0540 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0560 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0580 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0521 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0541 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0561 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0581 }, { 0x00600040, 0x29c04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29d04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x29e04629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x29f04629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0600 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0620 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0640 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0601 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0621 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0641 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a008 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a009 }, { 0x00600040, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0520 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0540 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0560 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0580 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0521 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0541 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0561 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0581 }, { 0x00600040, 0x2a004629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x2a104629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a204629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a304629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e0 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0600 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0620 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0640 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e1 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0601 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0621 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0641 }, { 0x00a02008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00a02008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00a02008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00a02008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a009 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a009 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x2a004629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x2a104629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x2a204629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x2a304629, 0x008d05e0, 0x008d05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000037 }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a008 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a009 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x29c04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29d04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x29e04629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x29f04629, 0x008d0620, 0x008d0640 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a008 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a009 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x2a004629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x2a104629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a204629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a304629, 0x008d0620, 0x008d0640 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a009 }, { 0x00600001, 0x29400229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29500229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29600229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29700229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x29c00229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x29d00229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x29e00229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x29f00229, 0x008d05e0, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a009 }, { 0x00600001, 0x29800229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29900229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29a00229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29b00229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x2a000229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x2a100229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x2a200229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x2a300229, 0x008d05e0, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000143 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20002dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000006a }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000004f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a003 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10500 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10540 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10580 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c0 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10600 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10640 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10680 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10501 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10541 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10581 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c1 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10601 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10641 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10681 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c1 }, { 0x00800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x00800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x00800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x00800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x00800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x00800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x00800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x00800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a003 }, { 0x00800040, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10500 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10540 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10580 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c0 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10600 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10640 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10680 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10501 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10541 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10581 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c1 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10601 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10641 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10681 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x00800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x00800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x00800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x00800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x00800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x00800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x00800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x00800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000039 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a003 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b106c0 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a003 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b10680, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00800001, 0x28400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b10680, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20003dbc, 0x00210a54, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005c }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000043 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a00a }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a00b }, { 0x00600040, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0520 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0540 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0560 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0580 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0521 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0541 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0561 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0581 }, { 0x00600040, 0x29c04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29d04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x29e04629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x29f04629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0600 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0620 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0640 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0601 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0621 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0641 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a00a }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a00b }, { 0x00600040, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0520 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0540 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0560 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0580 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0521 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0541 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0561 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0581 }, { 0x00600040, 0x2a004629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x2a104629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a204629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a304629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e0 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0600 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0620 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0640 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e1 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0601 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0621 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0641 }, { 0x00a02008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00a02008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00a02008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00a02008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a00b }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a00b }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x2a004629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x2a104629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x2a204629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x2a304629, 0x008d05e0, 0x008d05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000037 }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a00a }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a00b }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x29c04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29d04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x29e04629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x29f04629, 0x008d0620, 0x008d0640 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a00a }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a00b }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x2a004629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x2a104629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a204629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a304629, 0x008d0620, 0x008d0640 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a00b }, { 0x00600001, 0x29400229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29500229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29600229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29700229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x29c00229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x29d00229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x29e00229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x29f00229, 0x008d05e0, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a00b }, { 0x00600001, 0x29800229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29900229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29a00229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29b00229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x2a000229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x2a100229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x2a200229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x2a300229, 0x008d05e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05902000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_backward.g4b.gen5000066400000000000000000001212431231401140700243060ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20002dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000d4 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000009e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a007 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10500 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10540 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10580 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c0 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10600 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10640 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10680 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10501 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10541 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10581 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c1 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10601 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10641 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10681 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c1 }, { 0x00800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x00800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x00800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x00800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x00800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x00800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x00800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x00800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a007 }, { 0x00800040, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10500 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10540 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10580 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c0 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10600 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10640 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10680 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10501 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10541 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10581 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c1 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10601 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10641 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10681 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x00800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x00800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x00800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x00800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x00800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x00800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x00800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x00800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000a4 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000072 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000003e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a007 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b106c0 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a007 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b10680, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00800001, 0x28400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b10680, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20003dbc, 0x00210a54, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000b8 }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a008 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a009 }, { 0x00600040, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0520 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0540 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0560 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0580 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0521 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0541 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0561 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0581 }, { 0x00600040, 0x29c04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29d04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x29e04629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x29f04629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0600 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0620 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0640 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0601 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0621 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0641 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a008 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a009 }, { 0x00600040, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0520 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0540 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0560 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0580 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0521 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0541 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0561 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0581 }, { 0x00600040, 0x2a004629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x2a104629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a204629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a304629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e0 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0600 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0620 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0640 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e1 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0601 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0621 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0641 }, { 0x00a02008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00a02008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00a02008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00a02008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000009c }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a009 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a009 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x2a004629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x2a104629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x2a204629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x2a304629, 0x008d05e0, 0x008d05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000006e }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000003e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a008 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a009 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x29c04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29d04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x29e04629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x29f04629, 0x008d0620, 0x008d0640 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a008 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a009 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x2a004629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x2a104629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a204629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a304629, 0x008d0620, 0x008d0640 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a009 }, { 0x00600001, 0x29400229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29500229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29600229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29700229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x29c00229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x29d00229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x29e00229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x29f00229, 0x008d05e0, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a009 }, { 0x00600001, 0x29800229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29900229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29a00229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29b00229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x2a000229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x2a100229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x2a200229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x2a300229, 0x008d05e0, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000286 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20002dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000d4 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000009e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a003 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10500 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10540 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10580 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c0 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10600 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10640 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10680 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10501 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10541 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10581 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c1 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10601 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10641 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10681 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c1 }, { 0x00800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x00800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x00800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x00800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x00800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x00800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x00800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x00800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a003 }, { 0x00800040, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10500 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10540 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10580 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c0 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10600 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10640 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10680 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10501 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10541 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10581 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c1 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10601 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10641 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10681 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x00800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x00800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x00800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x00800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x00800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x00800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x00800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x00800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000a4 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000072 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000003e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a003 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b106c0 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a003 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b10680, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00800001, 0x28400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b10680, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20003dbc, 0x00210a54, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000b8 }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a00a }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a00b }, { 0x00600040, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0520 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0540 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0560 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0580 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0521 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0541 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0561 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0581 }, { 0x00600040, 0x29c04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29d04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x29e04629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x29f04629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0600 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0620 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0640 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0601 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0621 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0641 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a00a }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a00b }, { 0x00600040, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0520 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0540 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0560 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0580 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0521 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0541 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0561 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0581 }, { 0x00600040, 0x2a004629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x2a104629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a204629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a304629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e0 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0600 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0620 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0640 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e1 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0601 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0621 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0641 }, { 0x00a02008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00a02008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00a02008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00a02008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000009c }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a00b }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a00b }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x2a004629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x2a104629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x2a204629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x2a304629, 0x008d05e0, 0x008d05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000006e }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000003e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a00a }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a00b }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x29c04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29d04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x29e04629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x29f04629, 0x008d0620, 0x008d0640 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a00a }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a00b }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x2a004629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x2a104629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a204629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a304629, 0x008d0620, 0x008d0640 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a00b }, { 0x00600001, 0x29400229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29500229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29600229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29700229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x29c00229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x29d00229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x29e00229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x29f00229, 0x008d05e0, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a00b }, { 0x00600001, 0x29800229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29900229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29a00229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29b00229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x2a000229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x2a100229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x2a200229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x2a300229, 0x008d05e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x12082000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_backward_16x8.g4a000066400000000000000000000023611231401140700242350ustar00rootroot00000000000000/* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g32: message descriptor for reading reference data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; define(`UV_red',`0xffffffffUD') define(`UV_white',`0x7f7f7f7fUD') define(`UV_green',`0x00000000UD') mov(2) g6.0<1>UD g82.12<2,2,1>UW {align1}; mov(1) g6.8<1>UD 0x000f000fUD { align1 }; mov(16) m1<1>UD 0xFFFFFFFFUD {align1 compr}; mov(16) m3<1>UD 0xFFFFFFFFUD {align1 compr}; mov(16) m5<1>UD 0xFFFFFFFFUD {align1 compr}; mov(16) m7<1>UD 0xFFFFFFFFUD {align1 compr}; send (16) 0 acc0<1>UW g6<8,8,1>UW write(0, 0, 2, 0) mlen 9 rlen 0 { align1 }; /*Fill U buffer & V buffer with 0x7F*/ shr (2) g6.0<1>UD g82.12<2,2,1>UW 1UW {align1}; mov(1) g6.8<1>UD 0x00070007UD { align1 }; mov (16) m1<1>UD UV_white {align1 compr}; send (16) 0 acc0<1>UW g6<8,8,1>UW write(2, 0, 2, 0) mlen 3 rlen 0 { align1 }; send (16) 0 acc0<1>UW g6<8,8,1>UW write(1, 0, 2, 0) mlen 3 rlen 0 { align1 }; send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_backward_16x8.g4b000066400000000000000000000014711231401140700242370ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00200001, 0x20c00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x20c80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20200062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20600062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20a00062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20e00062, 0x00000000, 0xffffffff }, { 0x00800031, 0x24001d28, 0x008d00c0, 0x05902000 }, { 0x00200008, 0x20c02d21, 0x00450a4c, 0x00010001 }, { 0x00000001, 0x20c80061, 0x00000000, 0x00070007 }, { 0x00802001, 0x20200062, 0x00000000, 0x7f7f7f7f }, { 0x00800031, 0x24001d28, 0x008d00c0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d00c0, 0x05302001 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_backward_16x8.g4b.gen5000066400000000000000000000014711231401140700250740ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00200001, 0x20c00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x20c80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20200062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20600062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20a00062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20e00062, 0x00000000, 0xffffffff }, { 0x00800031, 0x24001d28, 0x508d00c0, 0x12082000 }, { 0x00200008, 0x20c02d21, 0x00450a4c, 0x00010001 }, { 0x00000001, 0x20c80061, 0x00000000, 0x00070007 }, { 0x00802001, 0x20200062, 0x00000000, 0x7f7f7f7f }, { 0x00800031, 0x24001d28, 0x508d00c0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x508d00c0, 0x06082001 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_bidirect.g4a000066400000000000000000000141341231401140700234570ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g32: message descriptor for reading reference data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; mov (1) g126.8<1>UD ip {align1}; mov (1) ip g21.0<1,1,1>UD {align1}; //Y of forward asr (2) g31.14<1>W g82.16<2,2,1>W 1W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; mov (1) g32.28<1>UD 0UD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x1000UW {align1}; //motion vertical field select (f0) mov (1) g32.28<1>UD 1UD {align1}; shl (1) g32.4<1>UD g32.4<1,1,1>UD 1UD {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD g32.28<1,1,1>UD {align1}; define(`surface',`4') define(`mv1',`g82.16') define(`mv2',`g82.18') include(`field_motion_y.g4i') mov (16) g108.0<1>UD g58.0<16,16,1>UD {align1 compr}; mov (16) g110.0<1>UD g60.0<16,16,1>UD {align1 compr}; mov (16) g112.0<1>UD g62.0<16,16,1>UD {align1 compr}; mov (16) g114.0<1>UD g64.0<16,16,1>UD {align1 compr}; mov (16) g116.0<1>UD g66.0<16,16,1>UD {align1 compr}; mov (16) g118.0<1>UD g68.0<16,16,1>UD {align1 compr}; mov (16) g120.0<1>UD g70.0<16,16,1>UD {align1 compr}; mov (16) g122.0<1>UD g72.0<16,16,1>UD {align1 compr}; //Y of backward asr (2) g31.14<1>W g82.20<2,2,1>W 1W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; mov (1) g32.28<1>UD 0UD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x2000UW {align1}; //motion vertical field select (f0) mov (1) g32.28<1>UD 1UD {align1}; shl (1) g32.4<1>UD g32.4<1,1,1>UD 1UD {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD g32.28<1,1,1>UD {align1}; define(`surface',`7') define(`mv1',`g82.20') define(`mv2',`g82.22') include(`field_motion_y.g4i') avg (16) g58.0<1>UW g58.0<16,16,1>UW g108.0<16,16,1>UW {align1}; avg (16) g59.0<1>UW g59.0<16,16,1>UW g109.0<16,16,1>UW {align1}; avg (16) g60.0<1>UW g60.0<16,16,1>UW g110.0<16,16,1>UW {align1}; avg (16) g61.0<1>UW g61.0<16,16,1>UW g111.0<16,16,1>UW {align1}; avg (16) g62.0<1>UW g62.0<16,16,1>UW g112.0<16,16,1>UW {align1}; avg (16) g63.0<1>UW g63.0<16,16,1>UW g113.0<16,16,1>UW {align1}; avg (16) g64.0<1>UW g64.0<16,16,1>UW g114.0<16,16,1>UW {align1}; avg (16) g65.0<1>UW g65.0<16,16,1>UW g115.0<16,16,1>UW {align1}; avg (16) g66.0<1>UW g66.0<16,16,1>UW g116.0<16,16,1>UW {align1}; avg (16) g67.0<1>UW g67.0<16,16,1>UW g117.0<16,16,1>UW {align1}; avg (16) g68.0<1>UW g68.0<16,16,1>UW g118.0<16,16,1>UW {align1}; avg (16) g69.0<1>UW g69.0<16,16,1>UW g119.0<16,16,1>UW {align1}; avg (16) g70.0<1>UW g70.0<16,16,1>UW g120.0<16,16,1>UW {align1}; avg (16) g71.0<1>UW g71.0<16,16,1>UW g121.0<16,16,1>UW {align1}; avg (16) g72.0<1>UW g72.0<16,16,1>UW g122.0<16,16,1>UW {align1}; avg (16) g73.0<1>UW g73.0<16,16,1>UW g123.0<16,16,1>UW {align1}; //UV, Forward shr (2) g31.0<1>UD g31.0<2,2,1>UD 1UD {align1}; asr (2) g31.14<1>W g82.16<2,2,1>W 2W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; mov (1) g32.28<1>UD 0UD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x1000UW {align1}; //motion vertical field select (f0) mov (1) g32.28<1>UD 1UD {align1}; shl (1) g32.4<1>UD g32.4<1,1,1>UD 1UD {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD g32.28<1,1,1>UD {align1}; define(`surface_u', `5') define(`surface_v', `6') define(`mv1',`g82.16') define(`mv2',`g82.18') include(`field_motion_uv.g4i') //Save UV Forward mov (16) g108.0<1>UD g74.0<16,16,1>UD {align1 compr}; mov (16) g110.0<1>UD g76.0<16,16,1>UD {align1 compr}; mov (16) g112.0<1>UD g78.0<16,16,1>UD {align1 compr}; mov (16) g114.0<1>UD g80.0<16,16,1>UD {align1 compr}; //UV, Backward asr (2) g31.14<1>W g82.20<2,2,1>W 2W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; mov (1) g32.28<1>UD 0UD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x2000UW {align1}; //motion vertical field select (f0) mov (1) g32.28<1>UD 1UD {align1}; shl (1) g32.4<1>UD g32.4<1,1,1>UD 1UD {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD g32.28<1,1,1>UD {align1}; define(`surface_u', `8') define(`surface_v', `9') define(`mv1',`g82.20') define(`mv2',`g82.22') include(`field_motion_uv.g4i') //Average Forward and Backward avg (16) g74.0<1>UW g74.0<16,16,1>UW g108.0<16,16,1>UW {align1}; avg (16) g75.0<1>UW g75.0<16,16,1>UW g109.0<16,16,1>UW {align1}; avg (16) g76.0<1>UW g76.0<16,16,1>UW g110.0<16,16,1>UW {align1}; avg (16) g77.0<1>UW g77.0<16,16,1>UW g111.0<16,16,1>UW {align1}; avg (16) g78.0<1>UW g78.0<16,16,1>UW g112.0<16,16,1>UW {align1}; avg (16) g79.0<1>UW g79.0<16,16,1>UW g113.0<16,16,1>UW {align1}; avg (16) g80.0<1>UW g80.0<16,16,1>UW g114.0<16,16,1>UW {align1}; avg (16) g81.0<1>UW g81.0<16,16,1>UW g115.0<16,16,1>UW {align1}; field_addidct: include(`field_addidct.g4i') out: send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_bidirect.g4b000066400000000000000000001254731231401140700234710ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20002dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000006a }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000004f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a004 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10500 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10540 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10580 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c0 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10600 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10640 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10680 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10501 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10541 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10581 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c1 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10601 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10641 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10681 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c1 }, { 0x00800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x00800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x00800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x00800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x00800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x00800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x00800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x00800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a004 }, { 0x00800040, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10500 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10540 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10580 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c0 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10600 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10640 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10680 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10501 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10541 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10581 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c1 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10601 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10641 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10681 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x00800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x00800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x00800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x00800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x00800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x00800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x00800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x00800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000039 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a004 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b106c0 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a004 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b10680, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00800001, 0x28400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b10680, 0x00000000 }, { 0x00802001, 0x2d800021, 0x00b10740, 0x00000000 }, { 0x00802001, 0x2dc00021, 0x00b10780, 0x00000000 }, { 0x00802001, 0x2e000021, 0x00b107c0, 0x00000000 }, { 0x00802001, 0x2e400021, 0x00b10800, 0x00000000 }, { 0x00802001, 0x2e800021, 0x00b10840, 0x00000000 }, { 0x00802001, 0x2ec00021, 0x00b10880, 0x00000000 }, { 0x00802001, 0x2f000021, 0x00b108c0, 0x00000000 }, { 0x00802001, 0x2f400021, 0x00b10900, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20002dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000006a }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000004f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a007 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10500 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10540 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10580 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c0 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10600 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10640 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10680 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10501 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10541 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10581 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c1 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10601 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10641 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10681 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c1 }, { 0x00800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x00800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x00800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x00800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x00800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x00800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x00800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x00800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a007 }, { 0x00800040, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10500 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10540 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10580 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c0 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10600 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10640 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10680 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10501 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10541 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10581 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c1 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10601 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10641 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10681 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x00800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x00800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x00800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x00800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x00800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x00800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x00800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x00800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000039 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a007 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b106c0 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a007 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b10680, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00800001, 0x28400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b10680, 0x00000000 }, { 0x00800042, 0x27402529, 0x00b10740, 0x00b10d80 }, { 0x00800042, 0x27602529, 0x00b10760, 0x00b10da0 }, { 0x00800042, 0x27802529, 0x00b10780, 0x00b10dc0 }, { 0x00800042, 0x27a02529, 0x00b107a0, 0x00b10de0 }, { 0x00800042, 0x27c02529, 0x00b107c0, 0x00b10e00 }, { 0x00800042, 0x27e02529, 0x00b107e0, 0x00b10e20 }, { 0x00800042, 0x28002529, 0x00b10800, 0x00b10e40 }, { 0x00800042, 0x28202529, 0x00b10820, 0x00b10e60 }, { 0x00800042, 0x28402529, 0x00b10840, 0x00b10e80 }, { 0x00800042, 0x28602529, 0x00b10860, 0x00b10ea0 }, { 0x00800042, 0x28802529, 0x00b10880, 0x00b10ec0 }, { 0x00800042, 0x28a02529, 0x00b108a0, 0x00b10ee0 }, { 0x00800042, 0x28c02529, 0x00b108c0, 0x00b10f00 }, { 0x00800042, 0x28e02529, 0x00b108e0, 0x00b10f20 }, { 0x00800042, 0x29002529, 0x00b10900, 0x00b10f40 }, { 0x00800042, 0x29202529, 0x00b10920, 0x00b10f60 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20003dbc, 0x00210a50, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005c }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000043 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a005 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a006 }, { 0x00600040, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0520 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0540 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0560 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0580 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0521 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0541 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0561 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0581 }, { 0x00600040, 0x29c04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29d04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x29e04629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x29f04629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0600 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0620 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0640 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0601 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0621 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0641 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a005 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a006 }, { 0x00600040, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0520 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0540 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0560 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0580 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0521 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0541 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0561 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0581 }, { 0x00600040, 0x2a004629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x2a104629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a204629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a304629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e0 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0600 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0620 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0640 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e1 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0601 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0621 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0641 }, { 0x00a02008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00a02008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00a02008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00a02008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a006 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a006 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x2a004629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x2a104629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x2a204629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x2a304629, 0x008d05e0, 0x008d05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000037 }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a005 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a006 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x29c04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29d04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x29e04629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x29f04629, 0x008d0620, 0x008d0640 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a005 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a006 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x2a004629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x2a104629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a204629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a304629, 0x008d0620, 0x008d0640 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a006 }, { 0x00600001, 0x29400229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29500229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29600229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29700229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x29c00229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x29d00229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x29e00229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x29f00229, 0x008d05e0, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a006 }, { 0x00600001, 0x29800229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29900229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29a00229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29b00229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x2a000229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x2a100229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x2a200229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x2a300229, 0x008d05e0, 0x00000000 }, { 0x00802001, 0x2d800021, 0x00b10940, 0x00000000 }, { 0x00802001, 0x2dc00021, 0x00b10980, 0x00000000 }, { 0x00802001, 0x2e000021, 0x00b109c0, 0x00000000 }, { 0x00802001, 0x2e400021, 0x00b10a00, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20003dbc, 0x00210a54, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005c }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000043 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a008 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a009 }, { 0x00600040, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0520 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0540 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0560 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0580 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0521 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0541 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0561 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0581 }, { 0x00600040, 0x29c04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29d04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x29e04629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x29f04629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0600 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0620 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0640 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0601 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0621 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0641 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a008 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a009 }, { 0x00600040, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0520 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0540 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0560 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0580 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0521 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0541 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0561 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0581 }, { 0x00600040, 0x2a004629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x2a104629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a204629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a304629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e0 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0600 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0620 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0640 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e1 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0601 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0621 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0641 }, { 0x00a02008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00a02008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00a02008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00a02008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a009 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a009 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x2a004629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x2a104629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x2a204629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x2a304629, 0x008d05e0, 0x008d05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000037 }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a008 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a009 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x29c04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29d04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x29e04629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x29f04629, 0x008d0620, 0x008d0640 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a008 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a009 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x2a004629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x2a104629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a204629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a304629, 0x008d0620, 0x008d0640 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a009 }, { 0x00600001, 0x29400229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29500229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29600229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29700229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x29c00229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x29d00229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x29e00229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x29f00229, 0x008d05e0, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a009 }, { 0x00600001, 0x29800229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29900229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29a00229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29b00229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x2a000229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x2a100229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x2a200229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x2a300229, 0x008d05e0, 0x00000000 }, { 0x00800042, 0x29402529, 0x00b10940, 0x00b10d80 }, { 0x00800042, 0x29602529, 0x00b10960, 0x00b10da0 }, { 0x00800042, 0x29802529, 0x00b10980, 0x00b10dc0 }, { 0x00800042, 0x29a02529, 0x00b109a0, 0x00b10de0 }, { 0x00800042, 0x29c02529, 0x00b109c0, 0x00b10e00 }, { 0x00800042, 0x29e02529, 0x00b109e0, 0x00b10e20 }, { 0x00800042, 0x2a002529, 0x00b10a00, 0x00b10e40 }, { 0x00800042, 0x2a202529, 0x00b10a20, 0x00b10e60 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05902000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_bidirect.g4b.gen5000066400000000000000000001254731231401140700243260ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20002dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000d4 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000009e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a004 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10500 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10540 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10580 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c0 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10600 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10640 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10680 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10501 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10541 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10581 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c1 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10601 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10641 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10681 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c1 }, { 0x00800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x00800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x00800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x00800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x00800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x00800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x00800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x00800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a004 }, { 0x00800040, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10500 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10540 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10580 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c0 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10600 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10640 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10680 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10501 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10541 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10581 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c1 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10601 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10641 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10681 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x00800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x00800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x00800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x00800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x00800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x00800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x00800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x00800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000a4 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000072 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000003e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a004 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b106c0 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a004 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b10680, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00800001, 0x28400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b10680, 0x00000000 }, { 0x00802001, 0x2d800021, 0x00b10740, 0x00000000 }, { 0x00802001, 0x2dc00021, 0x00b10780, 0x00000000 }, { 0x00802001, 0x2e000021, 0x00b107c0, 0x00000000 }, { 0x00802001, 0x2e400021, 0x00b10800, 0x00000000 }, { 0x00802001, 0x2e800021, 0x00b10840, 0x00000000 }, { 0x00802001, 0x2ec00021, 0x00b10880, 0x00000000 }, { 0x00802001, 0x2f000021, 0x00b108c0, 0x00000000 }, { 0x00802001, 0x2f400021, 0x00b10900, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20002dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000d4 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000009e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a007 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10500 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10540 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10580 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c0 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10600 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10640 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10680 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10501 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10541 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10581 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c1 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10601 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10641 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10681 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c1 }, { 0x00800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x00800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x00800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x00800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x00800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x00800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x00800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x00800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a007 }, { 0x00800040, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10500 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10540 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10580 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c0 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10600 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10640 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10680 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10501 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10541 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10581 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c1 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10601 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10641 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10681 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x00800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x00800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x00800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x00800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x00800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x00800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x00800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x00800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000a4 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000072 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000003e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a007 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b106c0 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a007 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b10680, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00800001, 0x28400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b10680, 0x00000000 }, { 0x00800042, 0x27402529, 0x00b10740, 0x00b10d80 }, { 0x00800042, 0x27602529, 0x00b10760, 0x00b10da0 }, { 0x00800042, 0x27802529, 0x00b10780, 0x00b10dc0 }, { 0x00800042, 0x27a02529, 0x00b107a0, 0x00b10de0 }, { 0x00800042, 0x27c02529, 0x00b107c0, 0x00b10e00 }, { 0x00800042, 0x27e02529, 0x00b107e0, 0x00b10e20 }, { 0x00800042, 0x28002529, 0x00b10800, 0x00b10e40 }, { 0x00800042, 0x28202529, 0x00b10820, 0x00b10e60 }, { 0x00800042, 0x28402529, 0x00b10840, 0x00b10e80 }, { 0x00800042, 0x28602529, 0x00b10860, 0x00b10ea0 }, { 0x00800042, 0x28802529, 0x00b10880, 0x00b10ec0 }, { 0x00800042, 0x28a02529, 0x00b108a0, 0x00b10ee0 }, { 0x00800042, 0x28c02529, 0x00b108c0, 0x00b10f00 }, { 0x00800042, 0x28e02529, 0x00b108e0, 0x00b10f20 }, { 0x00800042, 0x29002529, 0x00b10900, 0x00b10f40 }, { 0x00800042, 0x29202529, 0x00b10920, 0x00b10f60 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20003dbc, 0x00210a50, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000b8 }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a005 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a006 }, { 0x00600040, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0520 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0540 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0560 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0580 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0521 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0541 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0561 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0581 }, { 0x00600040, 0x29c04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29d04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x29e04629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x29f04629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0600 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0620 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0640 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0601 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0621 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0641 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a005 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a006 }, { 0x00600040, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0520 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0540 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0560 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0580 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0521 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0541 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0561 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0581 }, { 0x00600040, 0x2a004629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x2a104629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a204629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a304629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e0 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0600 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0620 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0640 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e1 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0601 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0621 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0641 }, { 0x00a02008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00a02008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00a02008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00a02008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000009c }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a006 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a006 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x2a004629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x2a104629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x2a204629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x2a304629, 0x008d05e0, 0x008d05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000006e }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000003e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a005 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a006 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x29c04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29d04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x29e04629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x29f04629, 0x008d0620, 0x008d0640 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a005 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a006 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x2a004629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x2a104629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a204629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a304629, 0x008d0620, 0x008d0640 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a006 }, { 0x00600001, 0x29400229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29500229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29600229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29700229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x29c00229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x29d00229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x29e00229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x29f00229, 0x008d05e0, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a006 }, { 0x00600001, 0x29800229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29900229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29a00229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29b00229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x2a000229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x2a100229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x2a200229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x2a300229, 0x008d05e0, 0x00000000 }, { 0x00802001, 0x2d800021, 0x00b10940, 0x00000000 }, { 0x00802001, 0x2dc00021, 0x00b10980, 0x00000000 }, { 0x00802001, 0x2e000021, 0x00b109c0, 0x00000000 }, { 0x00802001, 0x2e400021, 0x00b10a00, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20003dbc, 0x00210a54, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000b8 }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a008 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a009 }, { 0x00600040, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0520 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0540 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0560 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0580 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0521 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0541 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0561 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0581 }, { 0x00600040, 0x29c04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29d04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x29e04629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x29f04629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0600 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0620 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0640 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0601 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0621 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0641 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a008 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a009 }, { 0x00600040, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0520 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0540 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0560 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0580 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0521 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0541 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0561 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0581 }, { 0x00600040, 0x2a004629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x2a104629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a204629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a304629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e0 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0600 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0620 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0640 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e1 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0601 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0621 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0641 }, { 0x00a02008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00a02008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00a02008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00a02008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000009c }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a009 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a009 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x2a004629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x2a104629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x2a204629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x2a304629, 0x008d05e0, 0x008d05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000006e }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000003e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a008 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a009 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x29c04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29d04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x29e04629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x29f04629, 0x008d0620, 0x008d0640 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a008 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a009 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x2a004629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x2a104629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a204629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a304629, 0x008d0620, 0x008d0640 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a009 }, { 0x00600001, 0x29400229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29500229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29600229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29700229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x29c00229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x29d00229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x29e00229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x29f00229, 0x008d05e0, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a009 }, { 0x00600001, 0x29800229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29900229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29a00229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29b00229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x2a000229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x2a100229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x2a200229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x2a300229, 0x008d05e0, 0x00000000 }, { 0x00800042, 0x29402529, 0x00b10940, 0x00b10d80 }, { 0x00800042, 0x29602529, 0x00b10960, 0x00b10da0 }, { 0x00800042, 0x29802529, 0x00b10980, 0x00b10dc0 }, { 0x00800042, 0x29a02529, 0x00b109a0, 0x00b10de0 }, { 0x00800042, 0x29c02529, 0x00b109c0, 0x00b10e00 }, { 0x00800042, 0x29e02529, 0x00b109e0, 0x00b10e20 }, { 0x00800042, 0x2a002529, 0x00b10a00, 0x00b10e40 }, { 0x00800042, 0x2a202529, 0x00b10a20, 0x00b10e60 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x12082000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_bidirect_16x8.g4a000066400000000000000000000023621231401140700242450ustar00rootroot00000000000000/* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g32: message descriptor for reading reference data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; define(`UV_red',`0xffffffffUD') define(`UV_white',`0x7f7f7f7fUD') define(`UV_green',`0x00000000UD') mov(2) g6.0<1>UD g82.12<2,2,1>UW {align1}; mov(1) g6.8<1>UD 0x000f000fUD { align1 }; mov(16) m1<1>UD 0xFFFFFFFFUD {align1 compr}; mov(16) m3<1>UD 0xFFFFFFFFUD {align1 compr}; mov(16) m5<1>UD 0xFFFFFFFFUD {align1 compr}; mov(16) m7<1>UD 0xFFFFFFFFUD {align1 compr}; send (16) 0 acc0<1>UW g6<8,8,1>UW write(0, 0, 2, 0) mlen 9 rlen 0 { align1 }; /*Fill U buffer & V buffer with 0x7F*/ shr (2) g6.0<1>UD g82.12<2,2,1>UW 1UW {align1}; mov(1) g6.8<1>UD 0x00070007UD { align1 }; mov (16) m1<1>UD UV_white {align1 compr}; send (16) 0 acc0<1>UW g6<8,8,1>UW write(2, 0, 2, 0) mlen 3 rlen 0 { align1 }; send (16) 0 acc0<1>UW g6<8,8,1>UW write(1, 0, 2, 0) mlen 3 rlen 0 { align1 }; send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_bidirect_16x8.g4b000066400000000000000000000014711231401140700242460ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00200001, 0x20c00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x20c80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20200062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20600062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20a00062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20e00062, 0x00000000, 0xffffffff }, { 0x00800031, 0x24001d28, 0x008d00c0, 0x05902000 }, { 0x00200008, 0x20c02d21, 0x00450a4c, 0x00010001 }, { 0x00000001, 0x20c80061, 0x00000000, 0x00070007 }, { 0x00802001, 0x20200062, 0x00000000, 0x7f7f7f7f }, { 0x00800031, 0x24001d28, 0x008d00c0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d00c0, 0x05302001 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_bidirect_16x8.g4b.gen5000066400000000000000000000014711231401140700251030ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00200001, 0x20c00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x20c80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20200062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20600062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20a00062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20e00062, 0x00000000, 0xffffffff }, { 0x00800031, 0x24001d28, 0x508d00c0, 0x12082000 }, { 0x00200008, 0x20c02d21, 0x00450a4c, 0x00010001 }, { 0x00000001, 0x20c80061, 0x00000000, 0x00070007 }, { 0x00802001, 0x20200062, 0x00000000, 0x7f7f7f7f }, { 0x00800031, 0x24001d28, 0x508d00c0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x508d00c0, 0x06082001 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_forward.g4a000066400000000000000000000110621231401140700233330ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g32: message descriptor for reading reference data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; mov (1) g126.8<1>UD ip {align1}; mov (1) ip g21.0<1,1,1>UD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x0800UW {align1}; //second field-picture? (f0) jmpi first_field_picture; and (1) g32.0<1>UW g82.10<1,1,1>UW 0x0003UW {align1}; cmp.e (1) null g32.0<1,1,1>UW 0x0002UW {align1}; //bottom field? (f0) jmpi bottom_field; top_field: and.z (1) null g82.2<1,1,1>UW 0x1000UW {align1}; //motion vertical field select forward (f0) jmpi first_field_picture; //second field-picture top field from top mov (1) g32.28<1>UD 1UD {align1}; jmpi first_field_picture; //second field-picture top field from bottom bottom_field: and.nz (1) null g82.2<1,1,1>UW 0x1000UW {align1}; //motion vertical field select forward (f0) jmpi first_field_picture; //second field-picture bottom field from bottom mov (1) g32.28<1>UD 0UD {align1}; jmpi second_field_picture; //second field-picture bottom field from top //Y of top field first_field_picture: asr (2) g31.14<1>W g82.16<2,2,1>W 1W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; mov (1) g32.28<1>UD 0UD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x1000UW {align1}; //motion vertical field select forward (f0) mov (1) g32.28<1>UD 1UD {align1}; shl (1) g32.4<1>UD g32.4<1,1,1>UD 1UD {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD g32.28<1,1,1>UD {align1}; define(`surface',`4') define(`mv1',`g82.16') define(`mv2',`g82.18') include(`field_motion_y.g4i') //UV of top field shr (2) g31.0<1>UD g31.0<2,2,1>UD 1UD {align1}; asr (2) g31.14<1>W g82.16<2,2,1>W 2W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; mov (1) g32.28<1>UD 0UD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x1000UW {align1}; //motion vertical field select forward (f0) mov (1) g32.28<1>UD 1UD {align1}; shl (1) g32.4<1>UD g32.4<1,1,1>UD 1UD {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD g32.28<1,1,1>UD {align1}; define(`surface_u', `5') define(`surface_v', `6') define(`mv1',`g82.16') define(`mv2',`g82.18') include(`field_motion_uv.g4i') jmpi field_addidct; second_field_picture: //Y of bottom field asr (2) g31.14<1>W g82.16<2,2,1>W 1W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; shl (1) g32.4<1>UD g32.4<1,1,1>UD 1UD {align1}; define(`surface',`3') define(`mv1',`g82.16') define(`mv2',`g82.18') include(`field_motion_y.g4i') //UV of bottom field shr (2) g31.0<1>UD g31.0<2,2,1>UD 1UD {align1}; asr (2) g31.14<1>W g82.16<2,2,1>W 2W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; shl (1) g32.4<1>UD g32.4<1,1,1>UD 1UD {align1}; define(`surface_u', `10') define(`surface_v', `11') define(`mv1',`g82.16') define(`mv2',`g82.18') include(`field_motion_uv.g4i') field_addidct: include(`field_addidct.g4i') out: send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_forward.g4b000066400000000000000000001224001231401140700233330ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x08000800 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000005, 0x24002d29, 0x00210a4a, 0x00030003 }, { 0x01000010, 0x20002d3c, 0x00210400, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000004 }, { 0x01000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000004 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000014a }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20002dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000006a }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000004f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a004 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10500 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10540 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10580 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c0 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10600 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10640 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10680 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10501 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10541 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10581 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c1 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10601 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10641 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10681 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c1 }, { 0x00800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x00800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x00800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x00800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x00800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x00800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x00800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x00800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a004 }, { 0x00800040, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10500 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10540 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10580 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c0 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10600 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10640 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10680 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10501 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10541 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10581 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c1 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10601 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10641 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10681 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x00800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x00800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x00800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x00800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x00800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x00800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x00800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x00800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000039 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a004 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b106c0 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a004 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b10680, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00800001, 0x28400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b10680, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20003dbc, 0x00210a50, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005c }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000043 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a005 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a006 }, { 0x00600040, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0520 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0540 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0560 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0580 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0521 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0541 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0561 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0581 }, { 0x00600040, 0x29c04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29d04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x29e04629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x29f04629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0600 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0620 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0640 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0601 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0621 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0641 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a005 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a006 }, { 0x00600040, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0520 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0540 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0560 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0580 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0521 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0541 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0561 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0581 }, { 0x00600040, 0x2a004629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x2a104629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a204629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a304629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e0 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0600 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0620 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0640 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e1 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0601 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0621 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0641 }, { 0x00a02008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00a02008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00a02008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00a02008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a006 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a006 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x2a004629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x2a104629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x2a204629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x2a304629, 0x008d05e0, 0x008d05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000037 }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a005 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a006 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x29c04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29d04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x29e04629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x29f04629, 0x008d0620, 0x008d0640 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a005 }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a006 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x2a004629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x2a104629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a204629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a304629, 0x008d0620, 0x008d0640 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a006 }, { 0x00600001, 0x29400229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29500229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29600229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29700229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x29c00229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x29d00229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x29e00229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x29f00229, 0x008d05e0, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a006 }, { 0x00600001, 0x29800229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29900229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29a00229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29b00229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x2a000229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x2a100229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x2a200229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x2a300229, 0x008d05e0, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000141 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000006a }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000004f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a003 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10500 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10540 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10580 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c0 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10600 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10640 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10680 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10501 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10541 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10581 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c1 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10601 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10641 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10681 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c1 }, { 0x00800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x00800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x00800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x00800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x00800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x00800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x00800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x00800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a003 }, { 0x00800040, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10500 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10540 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10580 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c0 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10600 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10640 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10680 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10501 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10541 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10581 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c1 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10601 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10641 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10681 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x00800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x00800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x00800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x00800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x00800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x00800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x00800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x00800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000039 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a003 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b106c0 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a003 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b10680, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a003 }, { 0x00800001, 0x28400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b10680, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a50, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005c }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000043 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a00a }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a00b }, { 0x00600040, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0520 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0540 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0560 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0580 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0521 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0541 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0561 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0581 }, { 0x00600040, 0x29c04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29d04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x29e04629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x29f04629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0600 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0620 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0640 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0601 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0621 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0641 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a00a }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a00b }, { 0x00600040, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0520 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0540 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0560 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0580 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0521 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0541 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0561 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0581 }, { 0x00600040, 0x2a004629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x2a104629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a204629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a304629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e0 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0600 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0620 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0640 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e1 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0601 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0621 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0641 }, { 0x00a02008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00a02008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00a02008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00a02008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a00b }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a00b }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x2a004629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x2a104629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x2a204629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x2a304629, 0x008d05e0, 0x008d05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000037 }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001f }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a00a }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a00b }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x29c04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29d04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x29e04629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x29f04629, 0x008d0620, 0x008d0640 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0414a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0411a00a }, { 0x00800031, 0x26401d29, 0x008d0400, 0x0411a00b }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x2a004629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x2a104629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a204629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a304629, 0x008d0620, 0x008d0640 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a00b }, { 0x00600001, 0x29400229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29500229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29600229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29700229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x29c00229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x29d00229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x29e00229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x29f00229, 0x008d05e0, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a00a }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a00b }, { 0x00600001, 0x29800229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29900229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29a00229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29b00229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x2a000229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x2a100229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x2a200229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x2a300229, 0x008d05e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05902000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_forward.g4b.gen5000066400000000000000000001224001231401140700241700ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x08000800 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000005, 0x24002d29, 0x00210a4a, 0x00030003 }, { 0x01000010, 0x20002d3c, 0x00210400, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x01000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000004 }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000294 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20002dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000d4 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000009e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a004 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10500 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10540 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10580 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c0 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10600 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10640 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10680 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10501 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10541 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10581 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c1 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10601 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10641 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10681 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c1 }, { 0x00800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x00800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x00800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x00800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x00800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x00800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x00800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x00800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a004 }, { 0x00800040, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10500 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10540 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10580 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c0 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10600 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10640 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10680 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10501 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10541 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10581 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c1 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10601 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10641 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10681 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x00800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x00800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x00800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x00800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x00800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x00800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x00800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x00800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000a4 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000072 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000003e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a004 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b106c0 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a004 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b10680, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00800001, 0x28400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b10680, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x241c0061, 0x00000000, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010001, 0x241c0061, 0x00000000, 0x00000001 }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x00000040, 0x24040421, 0x00210404, 0x0021041c }, { 0x01000005, 0x20003dbc, 0x00210a50, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000b8 }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a005 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a006 }, { 0x00600040, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0520 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0540 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0560 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0580 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0521 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0541 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0561 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0581 }, { 0x00600040, 0x29c04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29d04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x29e04629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x29f04629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0600 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0620 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0640 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0601 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0621 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0641 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a005 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a006 }, { 0x00600040, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0520 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0540 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0560 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0580 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0521 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0541 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0561 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0581 }, { 0x00600040, 0x2a004629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x2a104629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a204629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a304629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e0 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0600 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0620 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0640 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e1 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0601 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0621 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0641 }, { 0x00a02008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00a02008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00a02008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00a02008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000009c }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a006 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a006 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x2a004629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x2a104629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x2a204629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x2a304629, 0x008d05e0, 0x008d05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000006e }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000003e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a005 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a006 }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x29c04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29d04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x29e04629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x29f04629, 0x008d0620, 0x008d0640 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a005 }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a006 }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x2a004629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x2a104629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a204629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a304629, 0x008d0620, 0x008d0640 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a006 }, { 0x00600001, 0x29400229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29500229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29600229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29700229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x29c00229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x29d00229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x29e00229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x29f00229, 0x008d05e0, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a006 }, { 0x00600001, 0x29800229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29900229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29a00229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29b00229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x2a000229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x2a100229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x2a200229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x2a300229, 0x008d05e0, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000282 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000d4 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000009e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a003 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10500 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10540 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10580 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c0 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10600 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10640 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10680 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b10501 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10541 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10581 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b105c1 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10601 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10641 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b10681 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b106c1 }, { 0x00800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x00800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x00800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x00800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x00800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x00800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x00800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x00800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a003 }, { 0x00800040, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10500 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10540 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10580 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c0 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10600 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10640 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10680 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b10501 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10541 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10581 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b105c1 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10601 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10641 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b10681 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x00800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x00800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x00800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x00800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x00800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x00800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x00800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x00800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000a4 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b10681 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b104c1 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10501 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10541 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b10581 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b105c1 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10601 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10641 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b10681 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000072 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000003e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a003 }, { 0x00800042, 0x27404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x27604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x27804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x27a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x27c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x27e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x28004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x28204629, 0x00b10680, 0x00b106c0 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a003 }, { 0x00800042, 0x28404629, 0x00b104c0, 0x00b10500 }, { 0x00800042, 0x28604629, 0x00b10500, 0x00b10540 }, { 0x00800042, 0x28804629, 0x00b10540, 0x00b10580 }, { 0x00800042, 0x28a04629, 0x00b10580, 0x00b105c0 }, { 0x00800042, 0x28c04629, 0x00b105c0, 0x00b10600 }, { 0x00800042, 0x28e04629, 0x00b10600, 0x00b10640 }, { 0x00800042, 0x29004629, 0x00b10640, 0x00b10680 }, { 0x00800042, 0x29204629, 0x00b10680, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b10680, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a003 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a003 }, { 0x00800001, 0x28400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b10680, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000009, 0x24040c21, 0x00210404, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a50, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000b8 }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a00a }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a00b }, { 0x00600040, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0520 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0540 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0560 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0580 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0521 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0541 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d0561 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d0581 }, { 0x00600040, 0x29c04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29d04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x29e04629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x29f04629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0600 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0620 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0640 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05e1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d0601 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d0621 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0641 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a00a }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a00b }, { 0x00600040, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600040, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0520 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0540 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0560 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0580 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d0521 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0541 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0561 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0581 }, { 0x00600040, 0x2a004629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x2a104629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a204629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a304629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e0 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0600 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0620 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0640 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d05e1 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0601 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0621 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0641 }, { 0x00a02008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00a02008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00a02008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00a02008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000009c }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a00b }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a00b }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0501 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0521 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0541 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0561 }, { 0x00600042, 0x2a004629, 0x008d0580, 0x008d0581 }, { 0x00600042, 0x2a104629, 0x008d05a0, 0x008d05a1 }, { 0x00600042, 0x2a204629, 0x008d05c0, 0x008d05c1 }, { 0x00600042, 0x2a304629, 0x008d05e0, 0x008d05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000006e }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000003e }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a00a }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a00b }, { 0x00600042, 0x29404629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29504629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29604629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29704629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x29c04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29d04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x29e04629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x29f04629, 0x008d0620, 0x008d0640 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0248a00b }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000000f }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0218a00a }, { 0x00800031, 0x26401d29, 0x408d0400, 0x0218a00b }, { 0x00600042, 0x29804629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29904629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29a04629, 0x008d0540, 0x008d0560 }, { 0x00600042, 0x29b04629, 0x008d0560, 0x008d0580 }, { 0x00600042, 0x2a004629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x2a104629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a204629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a304629, 0x008d0620, 0x008d0640 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a00b }, { 0x00600001, 0x29400229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29500229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29600229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29700229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x29c00229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x29d00229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x29e00229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x29f00229, 0x008d05e0, 0x00000000 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a00a }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a00b }, { 0x00600001, 0x29800229, 0x008d0500, 0x00000000 }, { 0x00600001, 0x29900229, 0x008d0520, 0x00000000 }, { 0x00600001, 0x29a00229, 0x008d0540, 0x00000000 }, { 0x00600001, 0x29b00229, 0x008d0560, 0x00000000 }, { 0x00600001, 0x2a000229, 0x008d0580, 0x00000000 }, { 0x00600001, 0x2a100229, 0x008d05a0, 0x00000000 }, { 0x00600001, 0x2a200229, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x2a300229, 0x008d05e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x12082000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_forward_16x8.g4a000066400000000000000000000023621231401140700241240ustar00rootroot00000000000000/* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g32: message descriptor for reading reference data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; define(`UV_red',`0xffffffffUD') define(`UV_white',`0x7f7f7f7fUD') define(`UV_green',`0x00000000UD') mov(2) g6.0<1>UD g82.12<2,2,1>UW {align1}; mov(1) g6.8<1>UD 0x000f000fUD { align1 }; mov(16) m1<1>UD 0xFFFFFFFFUD {align1 compr}; mov(16) m3<1>UD 0xFFFFFFFFUD {align1 compr}; mov(16) m5<1>UD 0xFFFFFFFFUD {align1 compr}; mov(16) m7<1>UD 0xFFFFFFFFUD {align1 compr}; send (16) 0 acc0<1>UW g6<8,8,1>UW write(0, 0, 2, 0) mlen 9 rlen 0 { align1 }; /*Fill U buffer & V buffer with 0x7F*/ shr (2) g6.0<1>UD g82.12<2,2,1>UW 1UW {align1}; mov(1) g6.8<1>UD 0x00070007UD { align1 }; mov (16) m1<1>UD UV_white {align1 compr}; send (16) 0 acc0<1>UW g6<8,8,1>UW write(2, 0, 2, 0) mlen 3 rlen 0 { align1 }; send (16) 0 acc0<1>UW g6<8,8,1>UW write(1, 0, 2, 0) mlen 3 rlen 0 { align1 }; send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_forward_16x8.g4b000066400000000000000000000014711231401140700241250ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00200001, 0x20c00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x20c80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20200062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20600062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20a00062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20e00062, 0x00000000, 0xffffffff }, { 0x00800031, 0x24001d28, 0x008d00c0, 0x05902000 }, { 0x00200008, 0x20c02d21, 0x00450a4c, 0x00010001 }, { 0x00000001, 0x20c80061, 0x00000000, 0x00070007 }, { 0x00802001, 0x20200062, 0x00000000, 0x7f7f7f7f }, { 0x00800031, 0x24001d28, 0x008d00c0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d00c0, 0x05302001 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_forward_16x8.g4b.gen5000066400000000000000000000014711231401140700247620ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00200001, 0x20c00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x20c80061, 0x00000000, 0x000f000f }, { 0x00802001, 0x20200062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20600062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20a00062, 0x00000000, 0xffffffff }, { 0x00802001, 0x20e00062, 0x00000000, 0xffffffff }, { 0x00800031, 0x24001d28, 0x508d00c0, 0x12082000 }, { 0x00200008, 0x20c02d21, 0x00450a4c, 0x00010001 }, { 0x00000001, 0x20c80061, 0x00000000, 0x00070007 }, { 0x00802001, 0x20200062, 0x00000000, 0x7f7f7f7f }, { 0x00800031, 0x24001d28, 0x508d00c0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x508d00c0, 0x06082001 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_intra.g4a000066400000000000000000000175341231401140700230160ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT tab g31: read and write message descriptor g32~g55:DCT data g58~g81:reference data g82: thread payload g83~g106:IDCT data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; include(`iq_intra.g4i') //defined for idct define(`ROW_SHIFT', `11UD') define(`ROW_ADD', `0x400UD') define(`COL_SHIFT', `20UD') define(`COL_ADD', `0x80000UD') mov (1) a0.0<1>UD 0x06F006E0UD {align1}; //0x06F006E0UD+0x00200020UD=0x07100700UD (g56.0 and g56.16) //Y0 mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; add (8) g83.0<1>W g32.0<16,8,2>W 128UW {align1}; add (8) g84.0<1>W g33.0<16,8,2>W 128UW {align1}; add (8) g85.0<1>W g34.0<16,8,2>W 128UW {align1}; add (8) g86.0<1>W g35.0<16,8,2>W 128UW {align1}; add (8) g87.0<1>W g36.0<16,8,2>W 128UW {align1}; add (8) g88.0<1>W g37.0<16,8,2>W 128UW {align1}; add (8) g89.0<1>W g38.0<16,8,2>W 128UW {align1}; add (8) g90.0<1>W g39.0<16,8,2>W 128UW {align1}; //Y1 mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; add (8) g83.16<1>W g32.0<16,8,2>W 128UW {align1}; add (8) g84.16<1>W g33.0<16,8,2>W 128UW {align1}; add (8) g85.16<1>W g34.0<16,8,2>W 128UW {align1}; add (8) g86.16<1>W g35.0<16,8,2>W 128UW {align1}; add (8) g87.16<1>W g36.0<16,8,2>W 128UW {align1}; add (8) g88.16<1>W g37.0<16,8,2>W 128UW {align1}; add (8) g89.16<1>W g38.0<16,8,2>W 128UW {align1}; add (8) g90.16<1>W g39.0<16,8,2>W 128UW {align1}; //Y2 mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; add (8) g91.0<1>W g32.0<16,8,2>W 128UW {align1}; add (8) g92.0<1>W g33.0<16,8,2>W 128UW {align1}; add (8) g93.0<1>W g34.0<16,8,2>W 128UW {align1}; add (8) g94.0<1>W g35.0<16,8,2>W 128UW {align1}; add (8) g95.0<1>W g36.0<16,8,2>W 128UW {align1}; add (8) g96.0<1>W g37.0<16,8,2>W 128UW {align1}; add (8) g97.0<1>W g38.0<16,8,2>W 128UW {align1}; add (8) g98.0<1>W g39.0<16,8,2>W 128UW {align1}; //Y3 mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; add (8) g91.16<1>W g32.0<16,8,2>W 128UW {align1}; add (8) g92.16<1>W g33.0<16,8,2>W 128UW {align1}; add (8) g93.16<1>W g34.0<16,8,2>W 128UW {align1}; add (8) g94.16<1>W g35.0<16,8,2>W 128UW {align1}; add (8) g95.16<1>W g36.0<16,8,2>W 128UW {align1}; add (8) g96.16<1>W g37.0<16,8,2>W 128UW {align1}; add (8) g97.16<1>W g38.0<16,8,2>W 128UW {align1}; add (8) g98.16<1>W g39.0<16,8,2>W 128UW {align1}; //U mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; add (16) g99.0<1>W g32.0<16,8,2>W 128UW {align1}; add (16) g100.0<1>W g34.0<16,8,2>W 128UW {align1}; add (16) g101.0<1>W g36.0<16,8,2>W 128UW {align1}; add (16) g102.0<1>W g38.0<16,8,2>W 128UW {align1}; //V mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; add (16) g103.0<1>W g32.0<16,8,2>W 128UW {align1}; add (16) g104.0<1>W g34.0<16,8,2>W 128UW {align1}; add (16) g105.0<1>W g36.0<16,8,2>W 128UW {align1}; add (16) g106.0<1>W g38.0<16,8,2>W 128UW {align1}; //send msg mov (1) g31.8<1>UD 0x00F000FUD {align1}; mov.sat (16) g83.0<2>UB g83.0<16,16,1>W {align1}; mov.sat (16) g84.0<2>UB g84.0<16,16,1>W {align1}; mov.sat (16) g85.0<2>UB g85.0<16,16,1>W {align1}; mov.sat (16) g86.0<2>UB g86.0<16,16,1>W {align1}; mov.sat (16) g87.0<2>UB g87.0<16,16,1>W {align1}; mov.sat (16) g88.0<2>UB g88.0<16,16,1>W {align1}; mov.sat (16) g89.0<2>UB g89.0<16,16,1>W {align1}; mov.sat (16) g90.0<2>UB g90.0<16,16,1>W {align1}; mov.sat (16) g91.0<2>UB g91.0<16,16,1>W {align1}; mov.sat (16) g92.0<2>UB g92.0<16,16,1>W {align1}; mov.sat (16) g93.0<2>UB g93.0<16,16,1>W {align1}; mov.sat (16) g94.0<2>UB g94.0<16,16,1>W {align1}; mov.sat (16) g95.0<2>UB g95.0<16,16,1>W {align1}; mov.sat (16) g96.0<2>UB g96.0<16,16,1>W {align1}; mov.sat (16) g97.0<2>UB g97.0<16,16,1>W {align1}; mov.sat (16) g98.0<2>UB g98.0<16,16,1>W {align1}; and.nz (1) null g82.2<1,1,1>UW 0x20UW{align1}; (f0) jmpi field_dct; mov (16) m1.0<1>UB g83.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g84.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g85.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g86.0<16,16,2>UB {align1}; mov (16) m3.0<1>UB g87.0<16,16,2>UB {align1}; mov (16) m3.16<1>UB g88.0<16,16,2>UB {align1}; mov (16) m4.0<1>UB g89.0<16,16,2>UB {align1}; mov (16) m4.16<1>UB g90.0<16,16,2>UB {align1}; mov (16) m5.0<1>UB g91.0<16,16,2>UB {align1}; mov (16) m5.16<1>UB g92.0<16,16,2>UB {align1}; mov (16) m6.0<1>UB g93.0<16,16,2>UB {align1}; mov (16) m6.16<1>UB g94.0<16,16,2>UB {align1}; mov (16) m7.0<1>UB g95.0<16,16,2>UB {align1}; mov (16) m7.16<1>UB g96.0<16,16,2>UB {align1}; mov (16) m8.0<1>UB g97.0<16,16,2>UB {align1}; mov (16) m8.16<1>UB g98.0<16,16,2>UB {align1}; jmpi write_back; field_dct: mov (16) m1.0<1>UB g83.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g91.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g84.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g92.0<16,16,2>UB {align1}; mov (16) m3.0<1>UB g85.0<16,16,2>UB {align1}; mov (16) m3.16<1>UB g93.0<16,16,2>UB {align1}; mov (16) m4.0<1>UB g86.0<16,16,2>UB {align1}; mov (16) m4.16<1>UB g94.0<16,16,2>UB {align1}; mov (16) m5.0<1>UB g87.0<16,16,2>UB {align1}; mov (16) m5.16<1>UB g95.0<16,16,2>UB {align1}; mov (16) m6.0<1>UB g88.0<16,16,2>UB {align1}; mov (16) m6.16<1>UB g96.0<16,16,2>UB {align1}; mov (16) m7.0<1>UB g89.0<16,16,2>UB {align1}; mov (16) m7.16<1>UB g97.0<16,16,2>UB {align1}; mov (16) m8.0<1>UB g90.0<16,16,2>UB {align1}; mov (16) m8.16<1>UB g98.0<16,16,2>UB {align1}; write_back: send (16) 0 acc0<1>UW g31<8,8,1>UW write(0,0,2,0) mlen 9 rlen 0 {align1}; //U mov (1) g31.8<1>UD 0x0070007UD { align1 }; shr (2) g31.0<1>UD g82.12<2,2,1>UW 1D {align1}; mov.sat (16) g99.0<2>UB g99.0<16,16,1>W {align1}; mov.sat (16) g100.0<2>UB g100.0<16,16,1>W {align1}; mov.sat (16) g101.0<2>UB g101.0<16,16,1>W {align1}; mov.sat (16) g102.0<2>UB g102.0<16,16,1>W {align1}; mov (16) m1.0<1>UB g99.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g100.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g101.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g102.0<16,16,2>UB {align1}; send (16) 0 acc0<1>UW g31<8,8,1>UW write(1, 0, 2, 0) mlen 3 rlen 0 { align1 }; //V mov.sat (16) g103.0<2>UB g103.0<16,16,1>W {align1}; mov.sat (16) g104.0<2>UB g104.0<16,16,1>W {align1}; mov.sat (16) g105.0<2>UB g105.0<16,16,1>W {align1}; mov.sat (16) g106.0<2>UB g106.0<16,16,1>W {align1}; mov (16) m1.0<1>UB g103.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g104.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g105.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g106.0<16,16,2>UB {align1}; send (16) 0 acc0<1>UW g31<8,8,1>UW write(2, 0, 2, 0) mlen 3 rlen 0 { align1 }; OUT: send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; include(`do_iq_intra.g4i') include(`idct.g4i') intel-driver-1.3.0/src/shaders/mpeg2/vld/field_intra.g4b000066400000000000000000000414771231401140700230220ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000005, 0x2da02d29, 0x00210a48, 0x001f001f }, { 0x00000005, 0x2da42d29, 0x00210a48, 0x60006000 }, { 0x00000008, 0x2da42d29, 0x00210da4, 0x000d000d }, { 0x00000001, 0x2da60169, 0x00000000, 0x00080008 }, { 0x00000008, 0x2da42529, 0x00210da6, 0x00210da4 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00090009 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00110011 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00190019 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xffe7ffe7 }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00030003 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x00400040 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000009 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xfff7fff7 }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00010001 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x000a000a }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000005 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xffefffef }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00020002 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x001c001c }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000001 }, { 0x00000009, 0x2da00d29, 0x00210da0, 0x00000001 }, { 0x00000001, 0x2dc00129, 0x00210da0, 0x00000000 }, { 0x00800001, 0x2e000229, 0x00b10020, 0x00000000 }, { 0x00800001, 0x2e200229, 0x00b10030, 0x00000000 }, { 0x00800001, 0x2e400229, 0x00b10040, 0x00000000 }, { 0x00800001, 0x2e600229, 0x00b10050, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x03f003e0 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000a1 }, { 0x00800001, 0x270001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x272001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x274001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x276001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000009b }, { 0x00800001, 0x278001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x27a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x27c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x27e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000095 }, { 0x00800001, 0x280001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x282001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x284001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x286001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000008f }, { 0x00800001, 0x288001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x28a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x28c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x28e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000089 }, { 0x00800001, 0x290001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x292001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x294001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x296001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000083 }, { 0x00800001, 0x298001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x29a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x29c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x29e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x06f006e0 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000008f }, { 0x00600040, 0x2a602dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2a802dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2aa02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2ac02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2ae02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2b002dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2b202dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2b402dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000085 }, { 0x00600040, 0x2a702dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2a902dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2ab02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2ad02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2af02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2b102dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2b302dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2b502dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000007b }, { 0x00600040, 0x2b602dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2b802dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2ba02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2bc02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2be02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2c002dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2c202dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2c402dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000071 }, { 0x00600040, 0x2b702dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2b902dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2bb02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2bd02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2bf02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2c102dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2c302dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2c502dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000067 }, { 0x00800040, 0x2c602dad, 0x00ae0400, 0x00800080 }, { 0x00800040, 0x2c802dad, 0x00ae0440, 0x00800080 }, { 0x00800040, 0x2ca02dad, 0x00ae0480, 0x00800080 }, { 0x00800040, 0x2cc02dad, 0x00ae04c0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000061 }, { 0x00800040, 0x2ce02dad, 0x00ae0400, 0x00800080 }, { 0x00800040, 0x2d002dad, 0x00ae0440, 0x00800080 }, { 0x00800040, 0x2d202dad, 0x00ae0480, 0x00800080 }, { 0x00800040, 0x2d402dad, 0x00ae04c0, 0x00800080 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x4a6001b1, 0x00b10a60, 0x00000000 }, { 0x80800001, 0x4a8001b1, 0x00b10a80, 0x00000000 }, { 0x80800001, 0x4aa001b1, 0x00b10aa0, 0x00000000 }, { 0x80800001, 0x4ac001b1, 0x00b10ac0, 0x00000000 }, { 0x80800001, 0x4ae001b1, 0x00b10ae0, 0x00000000 }, { 0x80800001, 0x4b0001b1, 0x00b10b00, 0x00000000 }, { 0x80800001, 0x4b2001b1, 0x00b10b20, 0x00000000 }, { 0x80800001, 0x4b4001b1, 0x00b10b40, 0x00000000 }, { 0x80800001, 0x4b6001b1, 0x00b10b60, 0x00000000 }, { 0x80800001, 0x4b8001b1, 0x00b10b80, 0x00000000 }, { 0x80800001, 0x4ba001b1, 0x00b10ba0, 0x00000000 }, { 0x80800001, 0x4bc001b1, 0x00b10bc0, 0x00000000 }, { 0x80800001, 0x4be001b1, 0x00b10be0, 0x00000000 }, { 0x80800001, 0x4c0001b1, 0x00b10c00, 0x00000000 }, { 0x80800001, 0x4c2001b1, 0x00b10c20, 0x00000000 }, { 0x80800001, 0x4c4001b1, 0x00b10c40, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x00800001, 0x20200232, 0x00b20a60, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20a80, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20aa0, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20ac0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b20ae0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b20b00, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20b20, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20b40, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20b60, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20b80, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20ba0, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b20bc0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b20be0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b20c00, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20c20, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20c40, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00800001, 0x20200232, 0x00b20a60, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20b60, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a80, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20b80, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b20aa0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b20ba0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20ac0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20bc0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20ae0, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20be0, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20b00, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b20c00, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b20b20, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b20c20, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20b40, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20c40, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05902000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01d21, 0x00450a4c, 0x00000001 }, { 0x80800001, 0x4c6001b1, 0x00b10c60, 0x00000000 }, { 0x80800001, 0x4c8001b1, 0x00b10c80, 0x00000000 }, { 0x80800001, 0x4ca001b1, 0x00b10ca0, 0x00000000 }, { 0x80800001, 0x4cc001b1, 0x00b10cc0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20c60, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20c80, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20ca0, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20cc0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302001 }, { 0x80800001, 0x4ce001b1, 0x00b10ce0, 0x00000000 }, { 0x80800001, 0x4d0001b1, 0x00b10d00, 0x00000000 }, { 0x80800001, 0x4d2001b1, 0x00b10d20, 0x00000000 }, { 0x80800001, 0x4d4001b1, 0x00b10d40, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20ce0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20d00, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20d20, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20d40, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00000001, 0x2de001ad, 0x00218000, 0x00000000 }, { 0x00802041, 0x2e8025a5, 0x008d8000, 0x008d0e00 }, { 0x00802041, 0x2e8024a5, 0x008d0e80, 0x008c0da0 }, { 0x0080200c, 0x2e802ca5, 0x008d0e80, 0x00040004 }, { 0x00000041, 0x2e8025a5, 0x00210de0, 0x00210da4 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2ec025a5, 0x008d8000, 0x008d0e20 }, { 0x00802041, 0x2ec024a5, 0x008d0ec0, 0x008c0da0 }, { 0x0080200c, 0x2ec02ca5, 0x008d0ec0, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2f0025a5, 0x008d8000, 0x008d0e40 }, { 0x00802041, 0x2f0024a5, 0x008d0f00, 0x008c0da0 }, { 0x0080200c, 0x2f002ca5, 0x008d0f00, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2f4025a5, 0x008d8000, 0x008d0e60 }, { 0x00802041, 0x2f4024a5, 0x008d0f40, 0x008c0da0 }, { 0x0080200c, 0x2f402ca5, 0x008d0f40, 0x00040004 }, { 0x00000040, 0x34000c20, 0x00210fa0, 0x00000020 }, { 0x00000001, 0x2fc00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00802040, 0x24000ca5, 0x008d0400, 0x00000400 }, { 0x00802040, 0x24400ca5, 0x008d0440, 0x00000400 }, { 0x00802040, 0x24800ca5, 0x008d0480, 0x00000400 }, { 0x00802040, 0x24c00ca5, 0x008d04c0, 0x00000400 }, { 0x00802008, 0x24000ca5, 0x008d0400, 0x0000000b }, { 0x00802008, 0x24400ca5, 0x008d0440, 0x0000000b }, { 0x00802008, 0x24800ca5, 0x008d0480, 0x0000000b }, { 0x00802008, 0x24c00ca5, 0x008d04c0, 0x0000000b }, { 0x00800001, 0x2dc001ad, 0x00ae0400, 0x00000000 }, { 0x00800001, 0x2de001ad, 0x00ae0440, 0x00000000 }, { 0x00800001, 0x2e0001ad, 0x00ae0480, 0x00000000 }, { 0x00800001, 0x2e2001ad, 0x00ae04c0, 0x00000000 }, { 0x00000001, 0x2a000001, 0x00210200, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x0db00da0 }, { 0x00000001, 0x2fc00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00802040, 0x24000ca5, 0x008d0400, 0x00080000 }, { 0x00802040, 0x24400ca5, 0x008d0440, 0x00080000 }, { 0x00802040, 0x24800ca5, 0x008d0480, 0x00080000 }, { 0x00802040, 0x24c00ca5, 0x008d04c0, 0x00080000 }, { 0x00802008, 0x24000ca5, 0x008d0400, 0x00000014 }, { 0x00802008, 0x24400ca5, 0x008d0440, 0x00000014 }, { 0x00802008, 0x24800ca5, 0x008d0480, 0x00000014 }, { 0x00802008, 0x24c00ca5, 0x008d04c0, 0x00000014 }, { 0x00000001, 0x22000020, 0x00210a00, 0x00000000 }, { 0x00000040, 0x34000c20, 0x00210fa0, 0x00000020 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x240014a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x242014a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x244014a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x246014a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x248014a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24a014a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24c014a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24e014a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x240814a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x242814a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x244814a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x246814a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x248814a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24a814a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24c814a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24e814a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x241014a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x243014a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x245014a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x247014a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x249014a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24b014a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24d014a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24f014a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x241814a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x243814a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x245814a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x247814a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x249814a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24b814a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24d814a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24f814a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x34000c20, 0x00210fc0, 0x00000020 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_intra.g4b.gen5000066400000000000000000000414771231401140700236570ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000005, 0x2da02d29, 0x00210a48, 0x001f001f }, { 0x00000005, 0x2da42d29, 0x00210a48, 0x60006000 }, { 0x00000008, 0x2da42d29, 0x00210da4, 0x000d000d }, { 0x00000001, 0x2da60169, 0x00000000, 0x00080008 }, { 0x00000008, 0x2da42529, 0x00210da6, 0x00210da4 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000024 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00090009 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00110011 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00190019 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xffe7ffe7 }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00030003 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x00400040 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xfff7fff7 }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00010001 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x000a000a }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xffefffef }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00020002 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x001c001c }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00000009, 0x2da00d29, 0x00210da0, 0x00000001 }, { 0x00000001, 0x2dc00129, 0x00210da0, 0x00000000 }, { 0x00800001, 0x2e000229, 0x00b10020, 0x00000000 }, { 0x00800001, 0x2e200229, 0x00b10030, 0x00000000 }, { 0x00800001, 0x2e400229, 0x00b10040, 0x00000000 }, { 0x00800001, 0x2e600229, 0x00b10050, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x03f003e0 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000142 }, { 0x00800001, 0x270001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x272001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x274001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x276001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000136 }, { 0x00800001, 0x278001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x27a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x27c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x27e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000012a }, { 0x00800001, 0x280001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x282001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x284001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x286001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000011e }, { 0x00800001, 0x288001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x28a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x28c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x28e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000112 }, { 0x00800001, 0x290001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x292001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x294001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x296001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000106 }, { 0x00800001, 0x298001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x29a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x29c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x29e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x06f006e0 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000011e }, { 0x00600040, 0x2a602dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2a802dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2aa02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2ac02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2ae02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2b002dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2b202dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2b402dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000010a }, { 0x00600040, 0x2a702dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2a902dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2ab02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2ad02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2af02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2b102dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2b302dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2b502dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000f6 }, { 0x00600040, 0x2b602dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2b802dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2ba02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2bc02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2be02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2c002dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2c202dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2c402dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000e2 }, { 0x00600040, 0x2b702dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2b902dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2bb02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2bd02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2bf02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2c102dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2c302dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2c502dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000ce }, { 0x00800040, 0x2c602dad, 0x00ae0400, 0x00800080 }, { 0x00800040, 0x2c802dad, 0x00ae0440, 0x00800080 }, { 0x00800040, 0x2ca02dad, 0x00ae0480, 0x00800080 }, { 0x00800040, 0x2cc02dad, 0x00ae04c0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000c2 }, { 0x00800040, 0x2ce02dad, 0x00ae0400, 0x00800080 }, { 0x00800040, 0x2d002dad, 0x00ae0440, 0x00800080 }, { 0x00800040, 0x2d202dad, 0x00ae0480, 0x00800080 }, { 0x00800040, 0x2d402dad, 0x00ae04c0, 0x00800080 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x4a6001b1, 0x00b10a60, 0x00000000 }, { 0x80800001, 0x4a8001b1, 0x00b10a80, 0x00000000 }, { 0x80800001, 0x4aa001b1, 0x00b10aa0, 0x00000000 }, { 0x80800001, 0x4ac001b1, 0x00b10ac0, 0x00000000 }, { 0x80800001, 0x4ae001b1, 0x00b10ae0, 0x00000000 }, { 0x80800001, 0x4b0001b1, 0x00b10b00, 0x00000000 }, { 0x80800001, 0x4b2001b1, 0x00b10b20, 0x00000000 }, { 0x80800001, 0x4b4001b1, 0x00b10b40, 0x00000000 }, { 0x80800001, 0x4b6001b1, 0x00b10b60, 0x00000000 }, { 0x80800001, 0x4b8001b1, 0x00b10b80, 0x00000000 }, { 0x80800001, 0x4ba001b1, 0x00b10ba0, 0x00000000 }, { 0x80800001, 0x4bc001b1, 0x00b10bc0, 0x00000000 }, { 0x80800001, 0x4be001b1, 0x00b10be0, 0x00000000 }, { 0x80800001, 0x4c0001b1, 0x00b10c00, 0x00000000 }, { 0x80800001, 0x4c2001b1, 0x00b10c20, 0x00000000 }, { 0x80800001, 0x4c4001b1, 0x00b10c40, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00800001, 0x20200232, 0x00b20a60, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20a80, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20aa0, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20ac0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b20ae0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b20b00, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20b20, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20b40, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20b60, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20b80, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20ba0, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b20bc0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b20be0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b20c00, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20c20, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20c40, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00800001, 0x20200232, 0x00b20a60, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20b60, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a80, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20b80, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b20aa0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b20ba0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20ac0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20bc0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20ae0, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20be0, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20b00, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b20c00, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b20b20, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b20c20, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20b40, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20c40, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x12082000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01d21, 0x00450a4c, 0x00000001 }, { 0x80800001, 0x4c6001b1, 0x00b10c60, 0x00000000 }, { 0x80800001, 0x4c8001b1, 0x00b10c80, 0x00000000 }, { 0x80800001, 0x4ca001b1, 0x00b10ca0, 0x00000000 }, { 0x80800001, 0x4cc001b1, 0x00b10cc0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20c60, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20c80, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20ca0, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20cc0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082001 }, { 0x80800001, 0x4ce001b1, 0x00b10ce0, 0x00000000 }, { 0x80800001, 0x4d0001b1, 0x00b10d00, 0x00000000 }, { 0x80800001, 0x4d2001b1, 0x00b10d20, 0x00000000 }, { 0x80800001, 0x4d4001b1, 0x00b10d40, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20ce0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20d00, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20d20, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20d40, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00000001, 0x2de001ad, 0x00218000, 0x00000000 }, { 0x00802041, 0x2e8025a5, 0x008d8000, 0x008d0e00 }, { 0x00802041, 0x2e8024a5, 0x008d0e80, 0x008c0da0 }, { 0x0080200c, 0x2e802ca5, 0x008d0e80, 0x00040004 }, { 0x00000041, 0x2e8025a5, 0x00210de0, 0x00210da4 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2ec025a5, 0x008d8000, 0x008d0e20 }, { 0x00802041, 0x2ec024a5, 0x008d0ec0, 0x008c0da0 }, { 0x0080200c, 0x2ec02ca5, 0x008d0ec0, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2f0025a5, 0x008d8000, 0x008d0e40 }, { 0x00802041, 0x2f0024a5, 0x008d0f00, 0x008c0da0 }, { 0x0080200c, 0x2f002ca5, 0x008d0f00, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2f4025a5, 0x008d8000, 0x008d0e60 }, { 0x00802041, 0x2f4024a5, 0x008d0f40, 0x008c0da0 }, { 0x0080200c, 0x2f402ca5, 0x008d0f40, 0x00040004 }, { 0x00000040, 0x34000c20, 0x00210fa0, 0x00000020 }, { 0x00000001, 0x2fc00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00802040, 0x24000ca5, 0x008d0400, 0x00000400 }, { 0x00802040, 0x24400ca5, 0x008d0440, 0x00000400 }, { 0x00802040, 0x24800ca5, 0x008d0480, 0x00000400 }, { 0x00802040, 0x24c00ca5, 0x008d04c0, 0x00000400 }, { 0x00802008, 0x24000ca5, 0x008d0400, 0x0000000b }, { 0x00802008, 0x24400ca5, 0x008d0440, 0x0000000b }, { 0x00802008, 0x24800ca5, 0x008d0480, 0x0000000b }, { 0x00802008, 0x24c00ca5, 0x008d04c0, 0x0000000b }, { 0x00800001, 0x2dc001ad, 0x00ae0400, 0x00000000 }, { 0x00800001, 0x2de001ad, 0x00ae0440, 0x00000000 }, { 0x00800001, 0x2e0001ad, 0x00ae0480, 0x00000000 }, { 0x00800001, 0x2e2001ad, 0x00ae04c0, 0x00000000 }, { 0x00000001, 0x2a000001, 0x00210200, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x0db00da0 }, { 0x00000001, 0x2fc00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00802040, 0x24000ca5, 0x008d0400, 0x00080000 }, { 0x00802040, 0x24400ca5, 0x008d0440, 0x00080000 }, { 0x00802040, 0x24800ca5, 0x008d0480, 0x00080000 }, { 0x00802040, 0x24c00ca5, 0x008d04c0, 0x00080000 }, { 0x00802008, 0x24000ca5, 0x008d0400, 0x00000014 }, { 0x00802008, 0x24400ca5, 0x008d0440, 0x00000014 }, { 0x00802008, 0x24800ca5, 0x008d0480, 0x00000014 }, { 0x00802008, 0x24c00ca5, 0x008d04c0, 0x00000014 }, { 0x00000001, 0x22000020, 0x00210a00, 0x00000000 }, { 0x00000040, 0x34000c20, 0x00210fa0, 0x00000020 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x240014a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x242014a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x244014a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x246014a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x248014a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24a014a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24c014a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24e014a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x240814a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x242814a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x244814a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x246814a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x248814a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24a814a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24c814a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24e814a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x241014a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x243014a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x245014a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x247014a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x249014a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24b014a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24d014a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24f014a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x241814a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x243814a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x245814a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x247814a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x249814a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24b814a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24d814a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24f814a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x34000c20, 0x00210fc0, 0x00000020 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/field_motion_uv.g4i000066400000000000000000000033431231401140700237210ustar00rootroot00000000000000/* * Copyright © 2008 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Zhang Hua jun * Xing Dong sheng * */ and.z (1) null mv1<1,1,1>W 2W {align1}; (f0) jmpi L1; and.z (1) null mv2<1,1,1>W 2W {align1}; (f0) jmpi L2; include(`field_read_x1y1_uv.g4i') jmpi L5; L2: include(`field_read_x1y0_uv.g4i') jmpi L5; L1: and.z (1) null mv2<1,1,1>W 2W {align1}; (f0) jmpi L4; include(`field_read_x0y1_uv.g4i') jmpi L5; L4: include(`field_read_x0y0_uv.g4i') L5: intel-driver-1.3.0/src/shaders/mpeg2/vld/field_motion_y.g4i000066400000000000000000000032001231401140700235270ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Zhang Hua jun * Xing Dong sheng * */ and.z (1) null mv1<1,1,1>W 1UW {align1}; (f0) jmpi L1; and.z (1) null mv2<1,1,1>W 1UW {align1}; (f0) jmpi L2; include(`field_read_x1y1_y.g4i') jmpi L5; L2: include(`field_read_x1y0_y.g4i') jmpi L5; L1: and.z (1) null mv2<1,1,1>W 1UW {align1}; (f0) jmpi L4; include(`field_read_x0y1_y.g4i') jmpi L5; L4: include(`field_read_x0y0_y.g4i') L5: intel-driver-1.3.0/src/shaders/mpeg2/vld/field_read_x0y0_uv.g4i000066400000000000000000000053351231401140700242120ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g32: message descriptor for reading reference data */ mov (1) g32.8<1>UD 0x7000FUD {align1}; //8*16 send (16) 0 g40.0<1>UW g32<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U send (16) 0 g44.0<1>UW g32<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V //U mov (8) g74.0<1>UW g40.0<8,8,1>UB {align1}; mov (8) g74.16<1>UW g41.0<8,8,1>UB {align1}; mov (8) g75.0<1>UW g42.0<8,8,1>UB {align1}; mov (8) g75.16<1>UW g43.0<8,8,1>UB {align1}; //V mov (8) g78.0<1>UW g44.0<8,8,1>UB {align1}; mov (8) g78.16<1>UW g45.0<8,8,1>UB {align1}; mov (8) g79.0<1>UW g46.0<8,8,1>UB {align1}; mov (8) g79.16<1>UW g47.0<8,8,1>UB {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g40.0<1>UW g32<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U send (16) 0 g44.0<1>UW g32<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V //U mov (8) g76.0<1>UW g40.0<8,8,1>UB {align1}; mov (8) g76.16<1>UW g41.0<8,8,1>UB {align1}; mov (8) g77.0<1>UW g42.0<8,8,1>UB {align1}; mov (8) g77.16<1>UW g43.0<8,8,1>UB {align1}; //V mov (8) g80.0<1>UW g44.0<8,8,1>UB {align1}; mov (8) g80.16<1>UW g45.0<8,8,1>UB {align1}; mov (8) g81.0<1>UW g46.0<8,8,1>UB {align1}; mov (8) g81.16<1>UW g47.0<8,8,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_read_x0y0_y.g4i000066400000000000000000000054461231401140700240330ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g32: message descriptor for reading reference data */ mov (1) g32.8<1>UD 0x07001FUD {align1}; send (16) 0 g38.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g46.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; mov (16) g58.0<1>UW g38.0<16,16,1>UB {align1}; mov (16) g59.0<1>UW g40.0<16,16,1>UB {align1}; mov (16) g60.0<1>UW g42.0<16,16,1>UB {align1}; mov (16) g61.0<1>UW g44.0<16,16,1>UB {align1}; mov (16) g62.0<1>UW g46.0<16,16,1>UB {align1}; mov (16) g63.0<1>UW g48.0<16,16,1>UB {align1}; mov (16) g64.0<1>UW g50.0<16,16,1>UB {align1}; mov (16) g65.0<1>UW g52.0<16,16,1>UB {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g38.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g46.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; mov (16) g66.0<1>UW g38.0<16,16,1>UB {align1}; mov (16) g67.0<1>UW g40.0<16,16,1>UB {align1}; mov (16) g68.0<1>UW g42.0<16,16,1>UB {align1}; mov (16) g69.0<1>UW g44.0<16,16,1>UB {align1}; mov (16) g70.0<1>UW g46.0<16,16,1>UB {align1}; mov (16) g71.0<1>UW g48.0<16,16,1>UB {align1}; mov (16) g72.0<1>UW g50.0<16,16,1>UB {align1}; mov (16) g73.0<1>UW g52.0<16,16,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_read_x0y1_uv.g4i000066400000000000000000000043221231401140700242060ustar00rootroot00000000000000/* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g32.8<1>UD 0x7000FUD {align1}; //8*16 send (16) 0 g40.0<1>UW g32<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U send (16) 0 g46.0<1>UW g32<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; mov (1) g32.8<1>UD 0x0FUD {align1}; send (16) 0 g44.0<1>UW g32<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 1 {align1};//U send (16) 0 g50.0<1>UW g32<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 1 {align1};//V //U avg (8) g74.0<1>UW g40.0<8,8,1>UB g41.0<8,8,1>UB {align1}; avg (8) g74.16<1>UW g41.0<8,8,1>UB g42.0<8,8,1>UB {align1}; avg (8) g75.0<1>UW g42.0<8,8,1>UB g43.0<8,8,1>UB {align1}; avg (8) g75.16<1>UW g43.0<8,8,1>UB g44.0<8,8,1>UB {align1}; //V avg (8) g78.0<1>UW g46.0<8,8,1>UB g47.0<8,8,1>UB {align1}; avg (8) g78.16<1>UW g47.0<8,8,1>UB g48.0<8,8,1>UB {align1}; avg (8) g79.0<1>UW g48.0<8,8,1>UB g49.0<8,8,1>UB {align1}; avg (8) g79.16<1>UW g49.0<8,8,1>UB g50.0<8,8,1>UB {align1}; mov (1) g32.8<1>UD 0x7000FUD {align1}; //8*16 send (16) 0 g40.0<1>UW g32<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U send (16) 0 g46.0<1>UW g32<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; mov (1) g32.8<1>UD 0x0FUD {align1}; send (16) 0 g44.0<1>UW g32<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 1 {align1};//U send (16) 0 g50.0<1>UW g32<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 1 {align1};//V //U avg (8) g76.0<1>UW g40.0<8,8,1>UB g41.0<8,8,1>UB {align1}; avg (8) g76.16<1>UW g41.0<8,8,1>UB g42.0<8,8,1>UB {align1}; avg (8) g77.0<1>UW g42.0<8,8,1>UB g43.0<8,8,1>UB {align1}; avg (8) g77.16<1>UW g43.0<8,8,1>UB g44.0<8,8,1>UB {align1}; //V avg (8) g80.0<1>UW g46.0<8,8,1>UB g47.0<8,8,1>UB {align1}; avg (8) g80.16<1>UW g47.0<8,8,1>UB g48.0<8,8,1>UB {align1}; avg (8) g81.0<1>UW g48.0<8,8,1>UB g49.0<8,8,1>UB {align1}; avg (8) g81.16<1>UW g49.0<8,8,1>UB g50.0<8,8,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_read_x0y1_y.g4i000066400000000000000000000065671231401140700240410ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g32.8<1>UD 0x07001FUD {align1}; send (16) 0 g38.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g46.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; mov (1) g32.8<1>UD 0x1FUD {align1}; send (16) 0 g54.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; avg (16) g58.0<1>UW g38.0<16,16,1>UB g40.0<16,16,1>UB {align1}; avg (16) g59.0<1>UW g40.0<16,16,1>UB g42.0<16,16,1>UB {align1}; avg (16) g60.0<1>UW g42.0<16,16,1>UB g44.0<16,16,1>UB {align1}; avg (16) g61.0<1>UW g44.0<16,16,1>UB g46.0<16,16,1>UB {align1}; avg (16) g62.0<1>UW g46.0<16,16,1>UB g48.0<16,16,1>UB {align1}; avg (16) g63.0<1>UW g48.0<16,16,1>UB g50.0<16,16,1>UB {align1}; avg (16) g64.0<1>UW g50.0<16,16,1>UB g52.0<16,16,1>UB {align1}; avg (16) g65.0<1>UW g52.0<16,16,1>UB g54.0<16,16,1>UB {align1}; mov (1) g32.8<1>UD 0x07001FUD {align1}; send (16) 0 g38.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g46.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; mov (1) g32.8<1>UD 0x1FUD {align1}; send (16) 0 g54.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; avg (16) g66.0<1>UW g38.0<16,16,1>UB g40.0<16,16,1>UB {align1}; avg (16) g67.0<1>UW g40.0<16,16,1>UB g42.0<16,16,1>UB {align1}; avg (16) g68.0<1>UW g42.0<16,16,1>UB g44.0<16,16,1>UB {align1}; avg (16) g69.0<1>UW g44.0<16,16,1>UB g46.0<16,16,1>UB {align1}; avg (16) g70.0<1>UW g46.0<16,16,1>UB g48.0<16,16,1>UB {align1}; avg (16) g71.0<1>UW g48.0<16,16,1>UB g50.0<16,16,1>UB {align1}; avg (16) g72.0<1>UW g50.0<16,16,1>UB g52.0<16,16,1>UB {align1}; avg (16) g73.0<1>UW g52.0<16,16,1>UB g54.0<16,16,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_read_x1y0_uv.g4i000066400000000000000000000033711231401140700242110ustar00rootroot00000000000000/* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g32.8<1>UD 0x7000FUD {align1}; //8*16 send (16) 0 g40.0<1>UW g32<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U send (16) 0 g44.0<1>UW g32<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V //U avg (8) g74.0<1>UW g40.0<8,8,1>UB g40.1<8,8,1>UB {align1}; avg (8) g74.16<1>UW g41.0<8,8,1>UB g41.1<8,8,1>UB {align1}; avg (8) g75.0<1>UW g42.0<8,8,1>UB g42.1<8,8,1>UB {align1}; avg (8) g75.16<1>UW g43.0<8,8,1>UB g43.1<8,8,1>UB {align1}; //V avg (8) g78.0<1>UW g44.0<8,8,1>UB g44.1<8,8,1>UB {align1}; avg (8) g78.16<1>UW g45.0<8,8,1>UB g45.1<8,8,1>UB {align1}; avg (8) g79.0<1>UW g46.0<8,8,1>UB g46.1<8,8,1>UB {align1}; avg (8) g79.16<1>UW g47.0<8,8,1>UB g47.1<8,8,1>UB {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g40.0<1>UW g32<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U send (16) 0 g44.0<1>UW g32<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V //U avg (8) g76.0<1>UW g40.0<8,8,1>UB g40.1<8,8,1>UB {align1}; avg (8) g76.16<1>UW g41.0<8,8,1>UB g41.1<8,8,1>UB {align1}; avg (8) g77.0<1>UW g42.0<8,8,1>UB g42.1<8,8,1>UB {align1}; avg (8) g77.16<1>UW g43.0<8,8,1>UB g43.1<8,8,1>UB {align1}; //V avg (8) g80.0<1>UW g44.0<8,8,1>UB g44.1<8,8,1>UB {align1}; avg (8) g80.16<1>UW g45.0<8,8,1>UB g45.1<8,8,1>UB {align1}; avg (8) g81.0<1>UW g46.0<8,8,1>UB g46.1<8,8,1>UB {align1}; avg (8) g81.16<1>UW g47.0<8,8,1>UB g47.1<8,8,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_read_x1y0_y.g4i000066400000000000000000000060671231401140700240340ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g32.8<1>UD 0x07001FUD {align1}; send (16) 0 g38.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g46.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; avg (16) g58.0<1>UW g38.0<16,16,1>UB g38.1<16,16,1>UB {align1}; avg (16) g59.0<1>UW g40.0<16,16,1>UB g40.1<16,16,1>UB {align1}; avg (16) g60.0<1>UW g42.0<16,16,1>UB g42.1<16,16,1>UB {align1}; avg (16) g61.0<1>UW g44.0<16,16,1>UB g44.1<16,16,1>UB {align1}; avg (16) g62.0<1>UW g46.0<16,16,1>UB g46.1<16,16,1>UB {align1}; avg (16) g63.0<1>UW g48.0<16,16,1>UB g48.1<16,16,1>UB {align1}; avg (16) g64.0<1>UW g50.0<16,16,1>UB g50.1<16,16,1>UB {align1}; avg (16) g65.0<1>UW g52.0<16,16,1>UB g52.1<16,16,1>UB {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g38.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g46.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; avg (16) g66.0<1>UW g38.0<16,16,1>UB g38.1<16,16,1>UB {align1}; avg (16) g67.0<1>UW g40.0<16,16,1>UB g40.1<16,16,1>UB {align1}; avg (16) g68.0<1>UW g42.0<16,16,1>UB g42.1<16,16,1>UB {align1}; avg (16) g69.0<1>UW g44.0<16,16,1>UB g44.1<16,16,1>UB {align1}; avg (16) g70.0<1>UW g46.0<16,16,1>UB g46.1<16,16,1>UB {align1}; avg (16) g71.0<1>UW g48.0<16,16,1>UB g48.1<16,16,1>UB {align1}; avg (16) g72.0<1>UW g50.0<16,16,1>UB g50.1<16,16,1>UB {align1}; avg (16) g73.0<1>UW g52.0<16,16,1>UB g52.1<16,16,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_read_x1y1_uv.g4i000066400000000000000000000105401231401140700242060ustar00rootroot00000000000000/* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g32.8<1>UD 0x7000FUD {align1}; //8*16 send (16) 0 g40.0<1>UW g32<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U send (16) 0 g46.0<1>UW g32<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; mov (1) g32.8<1>UD 0x0FUD {align1}; send (16) 0 g44.0<1>UW g32<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 1 {align1};//U send (16) 0 g50.0<1>UW g32<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 1 {align1};//V //U add (8) g74.0<1>UW g40.0<8,8,1>UB g40.1<8,8,1>UB {align1}; add (8) g74.16<1>UW g41.0<8,8,1>UB g41.1<8,8,1>UB {align1}; add (8) g75.0<1>UW g42.0<8,8,1>UB g42.1<8,8,1>UB {align1}; add (8) g75.16<1>UW g43.0<8,8,1>UB g43.1<8,8,1>UB {align1}; add (8) g74.0<1>UW g74.0<8,8,1>UW g41.0<8,8,1>UB {align1}; add (8) g74.16<1>UW g74.16<8,8,1>UW g42.0<8,8,1>UB {align1}; add (8) g75.0<1>UW g75.0<8,8,1>UW g43.0<8,8,1>UB {align1}; add (8) g75.16<1>UW g75.16<8,8,1>UW g44.0<8,8,1>UB {align1}; add (8) g74.0<1>UW g74.0<8,8,1>UW g41.1<8,8,1>UB {align1}; add (8) g74.16<1>UW g74.16<8,8,1>UW g42.1<8,8,1>UB {align1}; add (8) g75.0<1>UW g75.0<8,8,1>UW g43.1<8,8,1>UB {align1}; add (8) g75.16<1>UW g75.16<8,8,1>UW g44.1<8,8,1>UB {align1}; //V add (8) g78.0<1>UW g46.0<8,8,1>UB g46.1<8,8,1>UB {align1}; add (8) g78.16<1>UW g47.0<8,8,1>UB g47.1<8,8,1>UB {align1}; add (8) g79.0<1>UW g48.0<8,8,1>UB g48.1<8,8,1>UB {align1}; add (8) g79.16<1>UW g49.0<8,8,1>UB g49.1<8,8,1>UB {align1}; add (8) g78.0<1>UW g78.0<8,8,1>UW g47.0<8,8,1>UB {align1}; add (8) g78.16<1>UW g78.16<8,8,1>UW g48.0<8,8,1>UB {align1}; add (8) g79.0<1>UW g79.0<8,8,1>UW g49.0<8,8,1>UB {align1}; add (8) g79.16<1>UW g79.16<8,8,1>UW g50.0<8,8,1>UB {align1}; add (8) g78.0<1>UW g78.0<8,8,1>UW g47.1<8,8,1>UB {align1}; add (8) g78.16<1>UW g78.16<8,8,1>UW g48.1<8,8,1>UB {align1}; add (8) g79.0<1>UW g79.0<8,8,1>UW g49.1<8,8,1>UB {align1}; add (8) g79.16<1>UW g79.16<8,8,1>UW g50.1<8,8,1>UB {align1}; mov (1) g32.8<1>UD 0x7000FUD {align1}; //8*16 send (16) 0 g40.0<1>UW g32<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U send (16) 0 g46.0<1>UW g32<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; mov (1) g32.8<1>UD 0x0FUD {align1}; send (16) 0 g44.0<1>UW g32<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 1 {align1};//U send (16) 0 g50.0<1>UW g32<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 1 {align1};//V //U add (8) g76.0<1>UW g40.0<8,8,1>UB g40.1<8,8,1>UB {align1}; add (8) g76.16<1>UW g41.0<8,8,1>UB g41.1<8,8,1>UB {align1}; add (8) g77.0<1>UW g42.0<8,8,1>UB g42.1<8,8,1>UB {align1}; add (8) g77.16<1>UW g43.0<8,8,1>UB g43.1<8,8,1>UB {align1}; add (8) g76.0<1>UW g76.0<8,8,1>UW g41.0<8,8,1>UB {align1}; add (8) g76.16<1>UW g76.16<8,8,1>UW g42.0<8,8,1>UB {align1}; add (8) g77.0<1>UW g77.0<8,8,1>UW g43.0<8,8,1>UB {align1}; add (8) g77.16<1>UW g77.16<8,8,1>UW g44.0<8,8,1>UB {align1}; add (8) g76.0<1>UW g76.0<8,8,1>UW g41.1<8,8,1>UB {align1}; add (8) g76.16<1>UW g76.16<8,8,1>UW g42.1<8,8,1>UB {align1}; add (8) g77.0<1>UW g77.0<8,8,1>UW g43.1<8,8,1>UB {align1}; add (8) g77.16<1>UW g77.16<8,8,1>UW g44.1<8,8,1>UB {align1}; //V add (8) g80.0<1>UW g46.0<8,8,1>UB g46.1<8,8,1>UB {align1}; add (8) g80.16<1>UW g47.0<8,8,1>UB g47.1<8,8,1>UB {align1}; add (8) g81.0<1>UW g48.0<8,8,1>UB g48.1<8,8,1>UB {align1}; add (8) g81.16<1>UW g49.0<8,8,1>UB g49.1<8,8,1>UB {align1}; add (8) g80.0<1>UW g80.0<8,8,1>UW g47.0<8,8,1>UB {align1}; add (8) g80.16<1>UW g80.16<8,8,1>UW g48.0<8,8,1>UB {align1}; add (8) g81.0<1>UW g81.0<8,8,1>UW g49.0<8,8,1>UB {align1}; add (8) g81.16<1>UW g81.16<8,8,1>UW g50.0<8,8,1>UB {align1}; add (8) g80.0<1>UW g80.0<8,8,1>UW g47.1<8,8,1>UB {align1}; add (8) g80.16<1>UW g80.16<8,8,1>UW g48.1<8,8,1>UB {align1}; add (8) g81.0<1>UW g81.0<8,8,1>UW g49.1<8,8,1>UB {align1}; add (8) g81.16<1>UW g81.16<8,8,1>UW g50.1<8,8,1>UB {align1}; shr (32) g74.0<1>UW g74.0<16,16,1>UW 2UW {align1 compr}; shr (32) g76.0<1>UW g76.0<16,16,1>UW 2UW {align1 compr}; shr (32) g78.0<1>UW g78.0<16,16,1>UW 2UW {align1 compr}; shr (32) g80.0<1>UW g80.0<16,16,1>UW 2UW {align1 compr}; intel-driver-1.3.0/src/shaders/mpeg2/vld/field_read_x1y1_y.g4i000066400000000000000000000142561231401140700240340ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g32.8<1>UD 0x07001FUD {align1}; send (16) 0 g38.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g46.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; mov (1) g32.8<1>UD 0x1FUD {align1}; send (16) 0 g54.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (16) g58.0<1>UW g38.0<16,16,1>UB g38.1<16,16,1>UB {align1}; add (16) g59.0<1>UW g40.0<16,16,1>UB g40.1<16,16,1>UB {align1}; add (16) g60.0<1>UW g42.0<16,16,1>UB g42.1<16,16,1>UB {align1}; add (16) g61.0<1>UW g44.0<16,16,1>UB g44.1<16,16,1>UB {align1}; add (16) g62.0<1>UW g46.0<16,16,1>UB g46.1<16,16,1>UB {align1}; add (16) g63.0<1>UW g48.0<16,16,1>UB g48.1<16,16,1>UB {align1}; add (16) g64.0<1>UW g50.0<16,16,1>UB g50.1<16,16,1>UB {align1}; add (16) g65.0<1>UW g52.0<16,16,1>UB g52.1<16,16,1>UB {align1}; add (16) g58.0<1>UW g58.0<16,16,1>UW g40.0<16,16,1>UB {align1}; add (16) g59.0<1>UW g59.0<16,16,1>UW g42.0<16,16,1>UB {align1}; add (16) g60.0<1>UW g60.0<16,16,1>UW g44.0<16,16,1>UB {align1}; add (16) g61.0<1>UW g61.0<16,16,1>UW g46.0<16,16,1>UB {align1}; add (16) g62.0<1>UW g62.0<16,16,1>UW g48.0<16,16,1>UB {align1}; add (16) g63.0<1>UW g63.0<16,16,1>UW g50.0<16,16,1>UB {align1}; add (16) g64.0<1>UW g64.0<16,16,1>UW g52.0<16,16,1>UB {align1}; add (16) g65.0<1>UW g65.0<16,16,1>UW g54.0<16,16,1>UB {align1}; add (16) g58.0<1>UW g58.0<16,16,1>UW g40.1<16,16,1>UB {align1}; add (16) g59.0<1>UW g59.0<16,16,1>UW g42.1<16,16,1>UB {align1}; add (16) g60.0<1>UW g60.0<16,16,1>UW g44.1<16,16,1>UB {align1}; add (16) g61.0<1>UW g61.0<16,16,1>UW g46.1<16,16,1>UB {align1}; add (16) g62.0<1>UW g62.0<16,16,1>UW g48.1<16,16,1>UB {align1}; add (16) g63.0<1>UW g63.0<16,16,1>UW g50.1<16,16,1>UB {align1}; add (16) g64.0<1>UW g64.0<16,16,1>UW g52.1<16,16,1>UB {align1}; add (16) g65.0<1>UW g65.0<16,16,1>UW g54.1<16,16,1>UB {align1}; shr (16) g58.0<1>UW g58.0<16,16,1>UW 2UW {align1}; shr (16) g59.0<1>UW g59.0<16,16,1>UW 2UW {align1}; shr (16) g60.0<1>UW g60.0<16,16,1>UW 2UW {align1}; shr (16) g61.0<1>UW g61.0<16,16,1>UW 2UW {align1}; shr (16) g62.0<1>UW g62.0<16,16,1>UW 2UW {align1}; shr (16) g63.0<1>UW g63.0<16,16,1>UW 2UW {align1}; shr (16) g64.0<1>UW g64.0<16,16,1>UW 2UW {align1}; shr (16) g65.0<1>UW g65.0<16,16,1>UW 2UW {align1}; mov (1) g32.8<1>UD 0x07001FUD {align1}; send (16) 0 g38.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g46.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; mov (1) g32.8<1>UD 0x1FUD {align1}; send (16) 0 g54.0<1>UW g32<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (16) g66.0<1>UW g38.0<16,16,1>UB g38.1<16,16,1>UB {align1}; add (16) g67.0<1>UW g40.0<16,16,1>UB g40.1<16,16,1>UB {align1}; add (16) g68.0<1>UW g42.0<16,16,1>UB g42.1<16,16,1>UB {align1}; add (16) g69.0<1>UW g44.0<16,16,1>UB g44.1<16,16,1>UB {align1}; add (16) g70.0<1>UW g46.0<16,16,1>UB g46.1<16,16,1>UB {align1}; add (16) g71.0<1>UW g48.0<16,16,1>UB g48.1<16,16,1>UB {align1}; add (16) g72.0<1>UW g50.0<16,16,1>UB g50.1<16,16,1>UB {align1}; add (16) g73.0<1>UW g52.0<16,16,1>UB g52.1<16,16,1>UB {align1}; add (16) g66.0<1>UW g66.0<16,16,1>UW g40.0<16,16,1>UB {align1}; add (16) g67.0<1>UW g67.0<16,16,1>UW g42.0<16,16,1>UB {align1}; add (16) g68.0<1>UW g68.0<16,16,1>UW g44.0<16,16,1>UB {align1}; add (16) g69.0<1>UW g69.0<16,16,1>UW g46.0<16,16,1>UB {align1}; add (16) g70.0<1>UW g70.0<16,16,1>UW g48.0<16,16,1>UB {align1}; add (16) g71.0<1>UW g71.0<16,16,1>UW g50.0<16,16,1>UB {align1}; add (16) g72.0<1>UW g72.0<16,16,1>UW g52.0<16,16,1>UB {align1}; add (16) g73.0<1>UW g73.0<16,16,1>UW g54.0<16,16,1>UB {align1}; add (16) g66.0<1>UW g66.0<16,16,1>UW g40.1<16,16,1>UB {align1}; add (16) g67.0<1>UW g67.0<16,16,1>UW g42.1<16,16,1>UB {align1}; add (16) g68.0<1>UW g68.0<16,16,1>UW g44.1<16,16,1>UB {align1}; add (16) g69.0<1>UW g69.0<16,16,1>UW g46.1<16,16,1>UB {align1}; add (16) g70.0<1>UW g70.0<16,16,1>UW g48.1<16,16,1>UB {align1}; add (16) g71.0<1>UW g71.0<16,16,1>UW g50.1<16,16,1>UB {align1}; add (16) g72.0<1>UW g72.0<16,16,1>UW g52.1<16,16,1>UB {align1}; add (16) g73.0<1>UW g73.0<16,16,1>UW g54.1<16,16,1>UB {align1}; shr (16) g66.0<1>UW g66.0<16,16,1>UW 2UW {align1}; shr (16) g67.0<1>UW g67.0<16,16,1>UW 2UW {align1}; shr (16) g68.0<1>UW g68.0<16,16,1>UW 2UW {align1}; shr (16) g69.0<1>UW g69.0<16,16,1>UW 2UW {align1}; shr (16) g70.0<1>UW g70.0<16,16,1>UW 2UW {align1}; shr (16) g71.0<1>UW g71.0<16,16,1>UW 2UW {align1}; shr (16) g72.0<1>UW g72.0<16,16,1>UW 2UW {align1}; shr (16) g73.0<1>UW g73.0<16,16,1>UW 2UW {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_field_pred_backward.g4a000066400000000000000000000116761231401140700256440ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov(2) g31.0<1>UD g82.12<2,2,1>UW {align1}; mov (1) g126.8<1>UD ip {align1}; mov (1) ip g21.0<1,1,1>UD {align1}; /*field 0 of Y*/ asr (2) g31.14<1>W g82.20<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x2000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface',`7') define(`mv1',`g82.20') define(`mv2',`g82.22') include(`motion_field_y.g4i') mov (8) g58.0<1>UD g32.0<8,8,1>UD {align1}; mov (8) g60.0<1>UD g33.0<8,8,1>UD {align1}; mov (8) g62.0<1>UD g34.0<8,8,1>UD {align1}; mov (8) g64.0<1>UD g35.0<8,8,1>UD {align1}; mov (8) g66.0<1>UD g36.0<8,8,1>UD {align1}; mov (8) g68.0<1>UD g37.0<8,8,1>UD {align1}; mov (8) g70.0<1>UD g38.0<8,8,1>UD {align1}; mov (8) g72.0<1>UD g39.0<8,8,1>UD {align1}; /*field 1 of Y*/ asr (2) g31.14<1>W g82.28<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x8000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface',`7') define(`mv1',`g82.28') define(`mv2',`g82.30') include(`motion_field_y.g4i') mov (8) g59.0<1>UD g32.0<8,8,1>UD {align1}; mov (8) g61.0<1>UD g33.0<8,8,1>UD {align1}; mov (8) g63.0<1>UD g34.0<8,8,1>UD {align1}; mov (8) g65.0<1>UD g35.0<8,8,1>UD {align1}; mov (8) g67.0<1>UD g36.0<8,8,1>UD {align1}; mov (8) g69.0<1>UD g37.0<8,8,1>UD {align1}; mov (8) g71.0<1>UD g38.0<8,8,1>UD {align1}; mov (8) g73.0<1>UD g39.0<8,8,1>UD {align1}; /*field 0 of UV*/ shr (2) g31.0<1>UD g31.0<2,2,1>UD 1UD {align1}; asr (2) g82.20<1>W g82.20<2,2,1>W 1W {align1}; asr (2) g31.14<1>W g82.20<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and.nz (1) null g82.2<1,1,1>UW 0x2000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface_u', `8') define(`surface_v', `9') define(`mv1',`g82.20') define(`mv2',`g82.22') include(`motion_field_uv.g4i') mov (8) g74.0<1>UW g32.0<8,8,1>UW {align1}; mov (8) g75.0<1>UW g33.0<8,8,1>UW {align1}; mov (8) g76.0<1>UW g34.0<8,8,1>UW {align1}; mov (8) g77.0<1>UW g35.0<8,8,1>UW {align1}; mov (8) g78.0<1>UW g36.0<8,8,1>UW {align1}; mov (8) g79.0<1>UW g37.0<8,8,1>UW {align1}; mov (8) g80.0<1>UW g38.0<8,8,1>UW {align1}; mov (8) g81.0<1>UW g39.0<8,8,1>UW {align1}; /*field 1 of UV*/ asr (2) g82.28<1>W g82.28<2,2,1>W 1W {align1}; asr (2) g31.14<1>W g82.28<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and.nz (1) null g82.2<1,1,1>UW 0x8000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`mv1',`g82.28') define(`mv2',`g82.30') include(`motion_field_uv.g4i') mov (8) g74.16<1>UW g32.0<8,8,1>UW {align1}; mov (8) g75.16<1>UW g33.0<8,8,1>UW {align1}; mov (8) g76.16<1>UW g34.0<8,8,1>UW {align1}; mov (8) g77.16<1>UW g35.0<8,8,1>UW {align1}; mov (8) g78.16<1>UW g36.0<8,8,1>UW {align1}; mov (8) g79.16<1>UW g37.0<8,8,1>UW {align1}; mov (8) g80.16<1>UW g38.0<8,8,1>UW {align1}; mov (8) g81.16<1>UW g39.0<8,8,1>UW {align1}; include(`addidct.g4i') send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_field_pred_backward.g4b000066400000000000000000000733171231401140700256450ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000045 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002f }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a007 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000017 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000013 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x00600001, 0x27400021, 0x008d0400, 0x00000000 }, { 0x00600001, 0x27800021, 0x008d0420, 0x00000000 }, { 0x00600001, 0x27c00021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28c00021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x29000021, 0x008d04e0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a5c, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x80008000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a5c, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000045 }, { 0x01000005, 0x20002dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002f }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a007 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x01000005, 0x20002dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000017 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000013 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x00600001, 0x27600021, 0x008d0400, 0x00000000 }, { 0x00600001, 0x27a00021, 0x008d0420, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28a00021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28e00021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x29200021, 0x008d04e0, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x2a543dad, 0x00450a54, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000032 }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a008 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a008 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a009 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000029 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0414a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000001d }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a008 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a008 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x00ad0e60, 0x0414a008 }, { 0x00800031, 0x25a01d29, 0x00ad0e60, 0x0414a009 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x00600001, 0x29400129, 0x008d0400, 0x00000000 }, { 0x00600001, 0x29600129, 0x008d0420, 0x00000000 }, { 0x00600001, 0x29800129, 0x008d0440, 0x00000000 }, { 0x00600001, 0x29a00129, 0x008d0460, 0x00000000 }, { 0x00600001, 0x29c00129, 0x008d0480, 0x00000000 }, { 0x00600001, 0x29e00129, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x2a000129, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x2a200129, 0x008d04e0, 0x00000000 }, { 0x0020000c, 0x2a5c3dad, 0x00450a5c, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a5c, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x80008000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a5c, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000032 }, { 0x01000005, 0x20003dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a008 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a008 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a009 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000029 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0414a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000001d }, { 0x01000005, 0x20003dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a008 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a008 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x00ad0e60, 0x0414a008 }, { 0x00800031, 0x25a01d29, 0x00ad0e60, 0x0414a009 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x00600001, 0x29500129, 0x008d0400, 0x00000000 }, { 0x00600001, 0x29700129, 0x008d0420, 0x00000000 }, { 0x00600001, 0x29900129, 0x008d0440, 0x00000000 }, { 0x00600001, 0x29b00129, 0x008d0460, 0x00000000 }, { 0x00600001, 0x29d00129, 0x008d0480, 0x00000000 }, { 0x00600001, 0x29f00129, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x2a100129, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x2a300129, 0x008d04e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05902000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_field_pred_backward.g4b.gen5000066400000000000000000000733171231401140700265020ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000008a }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a007 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000058 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x00600001, 0x27400021, 0x008d0400, 0x00000000 }, { 0x00600001, 0x27800021, 0x008d0420, 0x00000000 }, { 0x00600001, 0x27c00021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28c00021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x29000021, 0x008d04e0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a5c, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x80008000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a5c, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000008a }, { 0x01000005, 0x20002dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a007 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000058 }, { 0x01000005, 0x20002dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x00600001, 0x27600021, 0x008d0400, 0x00000000 }, { 0x00600001, 0x27a00021, 0x008d0420, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28a00021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28e00021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x29200021, 0x008d04e0, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x2a543dad, 0x00450a54, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000064 }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a008 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a008 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a009 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0248a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000003a }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a008 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a008 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x40ad0e60, 0x0248a008 }, { 0x00800031, 0x25a01d29, 0x40ad0e60, 0x0248a009 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x00600001, 0x29400129, 0x008d0400, 0x00000000 }, { 0x00600001, 0x29600129, 0x008d0420, 0x00000000 }, { 0x00600001, 0x29800129, 0x008d0440, 0x00000000 }, { 0x00600001, 0x29a00129, 0x008d0460, 0x00000000 }, { 0x00600001, 0x29c00129, 0x008d0480, 0x00000000 }, { 0x00600001, 0x29e00129, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x2a000129, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x2a200129, 0x008d04e0, 0x00000000 }, { 0x0020000c, 0x2a5c3dad, 0x00450a5c, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a5c, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x80008000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a5c, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000064 }, { 0x01000005, 0x20003dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a008 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a008 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a009 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0248a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000003a }, { 0x01000005, 0x20003dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a008 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a008 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x40ad0e60, 0x0248a008 }, { 0x00800031, 0x25a01d29, 0x40ad0e60, 0x0248a009 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x00600001, 0x29500129, 0x008d0400, 0x00000000 }, { 0x00600001, 0x29700129, 0x008d0420, 0x00000000 }, { 0x00600001, 0x29900129, 0x008d0440, 0x00000000 }, { 0x00600001, 0x29b00129, 0x008d0460, 0x00000000 }, { 0x00600001, 0x29d00129, 0x008d0480, 0x00000000 }, { 0x00600001, 0x29f00129, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x2a100129, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x2a300129, 0x008d04e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x12082000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_field_pred_bidirect.g4a000066400000000000000000000222351231401140700256440ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov(2) g31.0<1>UD g82.12<2,2,1>UW {align1}; mov (1) g126.8<1>UD ip {align1}; mov (1) ip g21.0<1,1,1>UD {align1}; /*field 0 forward prediction of Y*/ asr (2) g31.14<1>W g82.16<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x1000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface',`4') define(`mv1',`g82.16') define(`mv2',`g82.18') include(`motion_field_y.g4i') mov (8) g58.0<1>UD g32.0<8,8,1>UD {align1}; mov (8) g60.0<1>UD g33.0<8,8,1>UD {align1}; mov (8) g62.0<1>UD g34.0<8,8,1>UD {align1}; mov (8) g64.0<1>UD g35.0<8,8,1>UD {align1}; mov (8) g66.0<1>UD g36.0<8,8,1>UD {align1}; mov (8) g68.0<1>UD g37.0<8,8,1>UD {align1}; mov (8) g70.0<1>UD g38.0<8,8,1>UD {align1}; mov (8) g72.0<1>UD g39.0<8,8,1>UD {align1}; /*field 1 forward prediction of Y*/ asr (2) g31.14<1>W g82.24<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x4000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface',`4') define(`mv1',`g82.24') define(`mv2',`g82.26') include(`motion_field_y.g4i') mov (8) g59.0<1>UD g32.0<8,8,1>UD {align1}; mov (8) g61.0<1>UD g33.0<8,8,1>UD {align1}; mov (8) g63.0<1>UD g34.0<8,8,1>UD {align1}; mov (8) g65.0<1>UD g35.0<8,8,1>UD {align1}; mov (8) g67.0<1>UD g36.0<8,8,1>UD {align1}; mov (8) g69.0<1>UD g37.0<8,8,1>UD {align1}; mov (8) g71.0<1>UD g38.0<8,8,1>UD {align1}; mov (8) g73.0<1>UD g39.0<8,8,1>UD {align1}; /*field 0 forward prediction of UV*/ shr (2) g31.0<1>UD g31.0<2,2,1>UD 1UD {align1}; asr (2) g82.16<1>W g82.16<2,2,1>W 1W {align1}; asr (2) g31.14<1>W g82.16<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x1000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface_u', `5') define(`surface_v', `6') define(`mv1',`g82.16') define(`mv2',`g82.18') include(`motion_field_uv.g4i') mov (8) g74.0<1>UW g32.0<8,8,1>UW {align1}; mov (8) g75.0<1>UW g33.0<8,8,1>UW {align1}; mov (8) g76.0<1>UW g34.0<8,8,1>UW {align1}; mov (8) g77.0<1>UW g35.0<8,8,1>UW {align1}; mov (8) g78.0<1>UW g36.0<8,8,1>UW {align1}; mov (8) g79.0<1>UW g37.0<8,8,1>UW {align1}; mov (8) g80.0<1>UW g38.0<8,8,1>UW {align1}; mov (8) g81.0<1>UW g39.0<8,8,1>UW {align1}; /*field 1 forward prediction of UV*/ asr (2) g82.24<1>W g82.24<2,2,1>W 1W {align1}; asr (2) g31.14<1>W g82.24<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x4000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`mv1',`g82.24') define(`mv2',`g82.26') include(`motion_field_uv.g4i') mov (8) g74.16<1>UW g32.0<8,8,1>UW {align1}; mov (8) g75.16<1>UW g33.0<8,8,1>UW {align1}; mov (8) g76.16<1>UW g34.0<8,8,1>UW {align1}; mov (8) g77.16<1>UW g35.0<8,8,1>UW {align1}; mov (8) g78.16<1>UW g36.0<8,8,1>UW {align1}; mov (8) g79.16<1>UW g37.0<8,8,1>UW {align1}; mov (8) g80.16<1>UW g38.0<8,8,1>UW {align1}; mov (8) g81.16<1>UW g39.0<8,8,1>UW {align1}; /*field 0 backward prediction of Y*/ mov(2) g31.0<1>UD g82.12<2,2,1>UW {align1}; asr (2) g31.14<1>W g82.20<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x2000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface',`7') define(`mv1',`g82.20') define(`mv2',`g82.22') include(`motion_field_y.g4i') avg.sat (16) g58.0<1>UW g58.0<16,16,1>UW g32.0<16,16,1>UW {align1}; avg.sat (16) g60.0<1>UW g60.0<16,16,1>UW g33.0<16,16,1>UW {align1}; avg.sat (16) g62.0<1>UW g62.0<16,16,1>UW g34.0<16,16,1>UW {align1}; avg.sat (16) g64.0<1>UW g64.0<16,16,1>UW g35.0<16,16,1>UW {align1}; avg.sat (16) g66.0<1>UW g66.0<16,16,1>UW g36.0<16,16,1>UW {align1}; avg.sat (16) g68.0<1>UW g68.0<16,16,1>UW g37.0<16,16,1>UW {align1}; avg.sat (16) g70.0<1>UW g70.0<16,16,1>UW g38.0<16,16,1>UW {align1}; avg.sat (16) g72.0<1>UW g72.0<16,16,1>UW g39.0<16,16,1>UW {align1}; /*field 1 backward prediction of Y*/ asr (2) g31.14<1>W g82.28<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x8000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface',`7') define(`mv1',`g82.28') define(`mv2',`g82.30') include(`motion_field_y.g4i') avg.sat (16) g59.0<1>UW g59.0<16,16,1>UW g32.0<16,16,1>UW {align1}; avg.sat (16) g61.0<1>UW g61.0<16,16,1>UW g33.0<16,16,1>UW {align1}; avg.sat (16) g63.0<1>UW g63.0<16,16,1>UW g34.0<16,16,1>UW {align1}; avg.sat (16) g65.0<1>UW g65.0<16,16,1>UW g35.0<16,16,1>UW {align1}; avg.sat (16) g67.0<1>UW g67.0<16,16,1>UW g36.0<16,16,1>UW {align1}; avg.sat (16) g69.0<1>UW g69.0<16,16,1>UW g37.0<16,16,1>UW {align1}; avg.sat (16) g71.0<1>UW g71.0<16,16,1>UW g38.0<16,16,1>UW {align1}; avg.sat (16) g73.0<1>UW g73.0<16,16,1>UW g39.0<16,16,1>UW {align1}; /*field 0 backward prediction of UV*/ shr (2) g31.0<1>UD g31.0<2,2,1>UD 1UD {align1}; asr (2) g82.20<1>W g82.20<2,2,1>W 1W {align1}; asr (2) g31.14<1>W g82.20<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x2000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface_u', `8') define(`surface_v', `9') define(`mv1',`g82.20') define(`mv2',`g82.22') include(`motion_field_uv.g4i') avg.sat (8) g74.0<1>UW g74.0<8,8,1>UW g32.0<8,8,1>UW {align1}; avg.sat (8) g75.0<1>UW g75.0<8,8,1>UW g33.0<8,8,1>UW {align1}; avg.sat (8) g76.0<1>UW g76.0<8,8,1>UW g34.0<8,8,1>UW {align1}; avg.sat (8) g77.0<1>UW g77.0<8,8,1>UW g35.0<8,8,1>UW {align1}; avg.sat (8) g78.0<1>UW g78.0<8,8,1>UW g36.0<8,8,1>UW {align1}; avg.sat (8) g79.0<1>UW g79.0<8,8,1>UW g37.0<8,8,1>UW {align1}; avg.sat (8) g80.0<1>UW g80.0<8,8,1>UW g38.0<8,8,1>UW {align1}; avg.sat (8) g81.0<1>UW g81.0<8,8,1>UW g39.0<8,8,1>UW {align1}; /*field 1 backward prediction of UV*/ asr (2) g82.28<1>W g82.28<2,2,1>W 1W {align1}; asr (2) g31.14<1>W g82.28<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x8000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`mv1',`g82.28') define(`mv2',`g82.30') include(`motion_field_uv.g4i') avg.sat (8) g74.16<1>UW g74.16<8,8,1>UW g32.0<8,8,1>UW {align1}; avg.sat (8) g75.16<1>UW g75.16<8,8,1>UW g33.0<8,8,1>UW {align1}; avg.sat (8) g76.16<1>UW g76.16<8,8,1>UW g34.0<8,8,1>UW {align1}; avg.sat (8) g77.16<1>UW g77.16<8,8,1>UW g35.0<8,8,1>UW {align1}; avg.sat (8) g78.16<1>UW g78.16<8,8,1>UW g36.0<8,8,1>UW {align1}; avg.sat (8) g79.16<1>UW g79.16<8,8,1>UW g37.0<8,8,1>UW {align1}; avg.sat (8) g80.16<1>UW g80.16<8,8,1>UW g38.0<8,8,1>UW {align1}; avg.sat (8) g81.16<1>UW g81.16<8,8,1>UW g39.0<8,8,1>UW {align1}; include(`addidct.g4i') send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_field_pred_bidirect.g4b000066400000000000000000001541311231401140700256460ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000045 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002f }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a004 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000017 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000013 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x00600001, 0x27400021, 0x008d0400, 0x00000000 }, { 0x00600001, 0x27800021, 0x008d0420, 0x00000000 }, { 0x00600001, 0x27c00021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28c00021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x29000021, 0x008d04e0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a58, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x40004000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a58, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000045 }, { 0x01000005, 0x20002dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002f }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a004 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x01000005, 0x20002dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000017 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000013 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x00600001, 0x27600021, 0x008d0400, 0x00000000 }, { 0x00600001, 0x27a00021, 0x008d0420, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28a00021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28e00021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x29200021, 0x008d04e0, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x2a503dad, 0x00450a50, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000032 }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a005 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a005 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a006 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000029 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0414a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000001d }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a005 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a005 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x00ad0e60, 0x0414a005 }, { 0x00800031, 0x25a01d29, 0x00ad0e60, 0x0414a006 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x00600001, 0x29400129, 0x008d0400, 0x00000000 }, { 0x00600001, 0x29600129, 0x008d0420, 0x00000000 }, { 0x00600001, 0x29800129, 0x008d0440, 0x00000000 }, { 0x00600001, 0x29a00129, 0x008d0460, 0x00000000 }, { 0x00600001, 0x29c00129, 0x008d0480, 0x00000000 }, { 0x00600001, 0x29e00129, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x2a000129, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x2a200129, 0x008d04e0, 0x00000000 }, { 0x0020000c, 0x2a583dad, 0x00450a58, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a58, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x40004000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a58, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000032 }, { 0x01000005, 0x20003dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a005 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a005 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a006 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000029 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0414a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000001d }, { 0x01000005, 0x20003dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a005 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a005 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x00ad0e60, 0x0414a005 }, { 0x00800031, 0x25a01d29, 0x00ad0e60, 0x0414a006 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x00600001, 0x29500129, 0x008d0400, 0x00000000 }, { 0x00600001, 0x29700129, 0x008d0420, 0x00000000 }, { 0x00600001, 0x29900129, 0x008d0440, 0x00000000 }, { 0x00600001, 0x29b00129, 0x008d0460, 0x00000000 }, { 0x00600001, 0x29d00129, 0x008d0480, 0x00000000 }, { 0x00600001, 0x29f00129, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x2a100129, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x2a300129, 0x008d04e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000045 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002f }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a007 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000017 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000013 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x80800042, 0x27402529, 0x00b10740, 0x00b10400 }, { 0x80800042, 0x27802529, 0x00b10780, 0x00b10420 }, { 0x80800042, 0x27c02529, 0x00b107c0, 0x00b10440 }, { 0x80800042, 0x28002529, 0x00b10800, 0x00b10460 }, { 0x80800042, 0x28402529, 0x00b10840, 0x00b10480 }, { 0x80800042, 0x28802529, 0x00b10880, 0x00b104a0 }, { 0x80800042, 0x28c02529, 0x00b108c0, 0x00b104c0 }, { 0x80800042, 0x29002529, 0x00b10900, 0x00b104e0 }, { 0x0020000c, 0x23ee3dad, 0x00450a5c, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x80008000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a5c, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000045 }, { 0x01000005, 0x20002dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002f }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a007 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x01000005, 0x20002dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000017 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000013 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a007 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x80800042, 0x27602529, 0x00b10760, 0x00b10400 }, { 0x80800042, 0x27a02529, 0x00b107a0, 0x00b10420 }, { 0x80800042, 0x27e02529, 0x00b107e0, 0x00b10440 }, { 0x80800042, 0x28202529, 0x00b10820, 0x00b10460 }, { 0x80800042, 0x28602529, 0x00b10860, 0x00b10480 }, { 0x80800042, 0x28a02529, 0x00b108a0, 0x00b104a0 }, { 0x80800042, 0x28e02529, 0x00b108e0, 0x00b104c0 }, { 0x80800042, 0x29202529, 0x00b10920, 0x00b104e0 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x2a543dad, 0x00450a54, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000032 }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a008 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a008 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a009 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000029 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0414a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000001d }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a008 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a008 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x00ad0e60, 0x0414a008 }, { 0x00800031, 0x25a01d29, 0x00ad0e60, 0x0414a009 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x80600042, 0x29402529, 0x008d0940, 0x008d0400 }, { 0x80600042, 0x29602529, 0x008d0960, 0x008d0420 }, { 0x80600042, 0x29802529, 0x008d0980, 0x008d0440 }, { 0x80600042, 0x29a02529, 0x008d09a0, 0x008d0460 }, { 0x80600042, 0x29c02529, 0x008d09c0, 0x008d0480 }, { 0x80600042, 0x29e02529, 0x008d09e0, 0x008d04a0 }, { 0x80600042, 0x2a002529, 0x008d0a00, 0x008d04c0 }, { 0x80600042, 0x2a202529, 0x008d0a20, 0x008d04e0 }, { 0x0020000c, 0x2a5c3dad, 0x00450a5c, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a5c, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x80008000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a5c, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000032 }, { 0x01000005, 0x20003dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a008 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a008 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a009 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000029 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0414a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000001d }, { 0x01000005, 0x20003dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a008 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a008 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x00ad0e60, 0x0414a008 }, { 0x00800031, 0x25a01d29, 0x00ad0e60, 0x0414a009 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x80600042, 0x29502529, 0x008d0950, 0x008d0400 }, { 0x80600042, 0x29702529, 0x008d0970, 0x008d0420 }, { 0x80600042, 0x29902529, 0x008d0990, 0x008d0440 }, { 0x80600042, 0x29b02529, 0x008d09b0, 0x008d0460 }, { 0x80600042, 0x29d02529, 0x008d09d0, 0x008d0480 }, { 0x80600042, 0x29f02529, 0x008d09f0, 0x008d04a0 }, { 0x80600042, 0x2a102529, 0x008d0a10, 0x008d04c0 }, { 0x80600042, 0x2a302529, 0x008d0a30, 0x008d04e0 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05902000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_field_pred_bidirect.g4b.gen5000066400000000000000000001541311231401140700265030ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000008a }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a004 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000058 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x00600001, 0x27400021, 0x008d0400, 0x00000000 }, { 0x00600001, 0x27800021, 0x008d0420, 0x00000000 }, { 0x00600001, 0x27c00021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28c00021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x29000021, 0x008d04e0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a58, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x40004000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a58, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000008a }, { 0x01000005, 0x20002dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a004 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000058 }, { 0x01000005, 0x20002dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x00600001, 0x27600021, 0x008d0400, 0x00000000 }, { 0x00600001, 0x27a00021, 0x008d0420, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28a00021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28e00021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x29200021, 0x008d04e0, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x2a503dad, 0x00450a50, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000064 }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a005 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a005 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a006 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0248a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000003a }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a005 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a005 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x40ad0e60, 0x0248a005 }, { 0x00800031, 0x25a01d29, 0x40ad0e60, 0x0248a006 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x00600001, 0x29400129, 0x008d0400, 0x00000000 }, { 0x00600001, 0x29600129, 0x008d0420, 0x00000000 }, { 0x00600001, 0x29800129, 0x008d0440, 0x00000000 }, { 0x00600001, 0x29a00129, 0x008d0460, 0x00000000 }, { 0x00600001, 0x29c00129, 0x008d0480, 0x00000000 }, { 0x00600001, 0x29e00129, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x2a000129, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x2a200129, 0x008d04e0, 0x00000000 }, { 0x0020000c, 0x2a583dad, 0x00450a58, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a58, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x40004000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a58, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000064 }, { 0x01000005, 0x20003dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a005 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a005 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a006 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0248a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000003a }, { 0x01000005, 0x20003dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a005 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a005 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x40ad0e60, 0x0248a005 }, { 0x00800031, 0x25a01d29, 0x40ad0e60, 0x0248a006 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x00600001, 0x29500129, 0x008d0400, 0x00000000 }, { 0x00600001, 0x29700129, 0x008d0420, 0x00000000 }, { 0x00600001, 0x29900129, 0x008d0440, 0x00000000 }, { 0x00600001, 0x29b00129, 0x008d0460, 0x00000000 }, { 0x00600001, 0x29d00129, 0x008d0480, 0x00000000 }, { 0x00600001, 0x29f00129, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x2a100129, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x2a300129, 0x008d04e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000008a }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a007 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000058 }, { 0x01000005, 0x20002dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x80800042, 0x27402529, 0x00b10740, 0x00b10400 }, { 0x80800042, 0x27802529, 0x00b10780, 0x00b10420 }, { 0x80800042, 0x27c02529, 0x00b107c0, 0x00b10440 }, { 0x80800042, 0x28002529, 0x00b10800, 0x00b10460 }, { 0x80800042, 0x28402529, 0x00b10840, 0x00b10480 }, { 0x80800042, 0x28802529, 0x00b10880, 0x00b104a0 }, { 0x80800042, 0x28c02529, 0x00b108c0, 0x00b104c0 }, { 0x80800042, 0x29002529, 0x00b10900, 0x00b104e0 }, { 0x0020000c, 0x23ee3dad, 0x00450a5c, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x80008000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a5c, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000008a }, { 0x01000005, 0x20002dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a007 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000058 }, { 0x01000005, 0x20002dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a007 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a007 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a007 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x80800042, 0x27602529, 0x00b10760, 0x00b10400 }, { 0x80800042, 0x27a02529, 0x00b107a0, 0x00b10420 }, { 0x80800042, 0x27e02529, 0x00b107e0, 0x00b10440 }, { 0x80800042, 0x28202529, 0x00b10820, 0x00b10460 }, { 0x80800042, 0x28602529, 0x00b10860, 0x00b10480 }, { 0x80800042, 0x28a02529, 0x00b108a0, 0x00b104a0 }, { 0x80800042, 0x28e02529, 0x00b108e0, 0x00b104c0 }, { 0x80800042, 0x29202529, 0x00b10920, 0x00b104e0 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x2a543dad, 0x00450a54, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x20002000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a54, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000064 }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a008 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a008 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a009 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0248a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000003a }, { 0x01000005, 0x20003dbc, 0x00210a56, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a008 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a008 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x40ad0e60, 0x0248a008 }, { 0x00800031, 0x25a01d29, 0x40ad0e60, 0x0248a009 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x80600042, 0x29402529, 0x008d0940, 0x008d0400 }, { 0x80600042, 0x29602529, 0x008d0960, 0x008d0420 }, { 0x80600042, 0x29802529, 0x008d0980, 0x008d0440 }, { 0x80600042, 0x29a02529, 0x008d09a0, 0x008d0460 }, { 0x80600042, 0x29c02529, 0x008d09c0, 0x008d0480 }, { 0x80600042, 0x29e02529, 0x008d09e0, 0x008d04a0 }, { 0x80600042, 0x2a002529, 0x008d0a00, 0x008d04c0 }, { 0x80600042, 0x2a202529, 0x008d0a20, 0x008d04e0 }, { 0x0020000c, 0x2a5c3dad, 0x00450a5c, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a5c, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x80008000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a5c, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000064 }, { 0x01000005, 0x20003dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a008 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a008 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a009 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0248a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000003a }, { 0x01000005, 0x20003dbc, 0x00210a5e, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a008 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a009 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a008 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a009 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x40ad0e60, 0x0248a008 }, { 0x00800031, 0x25a01d29, 0x40ad0e60, 0x0248a009 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x80600042, 0x29502529, 0x008d0950, 0x008d0400 }, { 0x80600042, 0x29702529, 0x008d0970, 0x008d0420 }, { 0x80600042, 0x29902529, 0x008d0990, 0x008d0440 }, { 0x80600042, 0x29b02529, 0x008d09b0, 0x008d0460 }, { 0x80600042, 0x29d02529, 0x008d09d0, 0x008d0480 }, { 0x80600042, 0x29f02529, 0x008d09f0, 0x008d04a0 }, { 0x80600042, 0x2a102529, 0x008d0a10, 0x008d04c0 }, { 0x80600042, 0x2a302529, 0x008d0a30, 0x008d04e0 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x12082000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_field_pred_forward.g4a000066400000000000000000000122221231401140700255160ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; mov (1) g126.8<1>UD ip {align1}; mov (1) ip g21.0<1,1,1>UD {align1}; /*field 0 of Y*/ asr (2) g31.14<1>W g82.16<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x1000UW {align1}; //motion vertical field select (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface',`4') define(`mv1',`g82.16') define(`mv2',`g82.18') include(`motion_field_y.g4i') mov (8) g58.0<1>UD g32.0<8,8,1>UD {align1}; mov (8) g60.0<1>UD g33.0<8,8,1>UD {align1}; mov (8) g62.0<1>UD g34.0<8,8,1>UD {align1}; mov (8) g64.0<1>UD g35.0<8,8,1>UD {align1}; mov (8) g66.0<1>UD g36.0<8,8,1>UD {align1}; mov (8) g68.0<1>UD g37.0<8,8,1>UD {align1}; mov (8) g70.0<1>UD g38.0<8,8,1>UD {align1}; mov (8) g72.0<1>UD g39.0<8,8,1>UD {align1}; /*field 1 of Y*/ asr (2) g31.14<1>W g82.24<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x4000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface',`4') define(`mv1',`g82.24') define(`mv2',`g82.26') include(`motion_field_y.g4i') mov (8) g59.0<1>UD g32.0<8,8,1>UD {align1}; mov (8) g61.0<1>UD g33.0<8,8,1>UD {align1}; mov (8) g63.0<1>UD g34.0<8,8,1>UD {align1}; mov (8) g65.0<1>UD g35.0<8,8,1>UD {align1}; mov (8) g67.0<1>UD g36.0<8,8,1>UD {align1}; mov (8) g69.0<1>UD g37.0<8,8,1>UD {align1}; mov (8) g71.0<1>UD g38.0<8,8,1>UD {align1}; mov (8) g73.0<1>UD g39.0<8,8,1>UD {align1}; /*field 0 of UV*/ shr (2) g31.0<1>UD g31.0<2,2,1>UD 1UD {align1}; asr (2) g82.16<1>W g82.16<2,2,1>W 1W {align1}; asr (2) g31.14<1>W g82.16<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x1000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface_u', `5') define(`surface_v', `6') define(`mv1',`g82.16') define(`mv2',`g82.18') include(`motion_field_uv.g4i') mov (8) g74.0<1>UW g32.0<8,8,1>UW {align1}; mov (8) g75.0<1>UW g33.0<8,8,1>UW {align1}; mov (8) g76.0<1>UW g34.0<8,8,1>UW {align1}; mov (8) g77.0<1>UW g35.0<8,8,1>UW {align1}; mov (8) g78.0<1>UW g36.0<8,8,1>UW {align1}; mov (8) g79.0<1>UW g37.0<8,8,1>UW {align1}; mov (8) g80.0<1>UW g38.0<8,8,1>UW {align1}; mov (8) g81.0<1>UW g39.0<8,8,1>UW {align1}; /*field 1 of UV*/ asr (2) g82.24<1>W g82.24<2,2,1>W 1W {align1}; asr (2) g31.14<1>W g82.24<2,2,1>W 1W {align1}; shl (1) g31.16<1>W g31.16<1,1,1>W 1W {align1}; add (2) g115.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; and (1) g115.4<1>UD g115.4<1,1,1>UD 0xFFFFFFFEUD {align1}; and.nz (1) null g82.2<1,1,1>UW 0x4000UW {align1}; (f0) add (1) g115.4<1>UD g115.4<1,1,1>UD 1UD {align1}; define(`surface_u', `5') define(`surface_v', `6') define(`mv1',`g82.24') define(`mv2',`g82.26') include(`motion_field_uv.g4i') mov (8) g74.16<1>UW g32.0<8,8,1>UW {align1}; mov (8) g75.16<1>UW g33.0<8,8,1>UW {align1}; mov (8) g76.16<1>UW g34.0<8,8,1>UW {align1}; mov (8) g77.16<1>UW g35.0<8,8,1>UW {align1}; mov (8) g78.16<1>UW g36.0<8,8,1>UW {align1}; mov (8) g79.16<1>UW g37.0<8,8,1>UW {align1}; mov (8) g80.16<1>UW g38.0<8,8,1>UW {align1}; mov (8) g81.16<1>UW g39.0<8,8,1>UW {align1}; include(`addidct.g4i') send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_field_pred_forward.g4b000066400000000000000000000734751231401140700255400ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000045 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002f }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a004 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000017 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000013 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x00600001, 0x27400021, 0x008d0400, 0x00000000 }, { 0x00600001, 0x27800021, 0x008d0420, 0x00000000 }, { 0x00600001, 0x27c00021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28c00021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x29000021, 0x008d04e0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a58, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x40004000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a58, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000045 }, { 0x01000005, 0x20002dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002f }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a004 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x01000005, 0x20002dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000017 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x008d0e60, 0x0411a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000013 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x008d0e60, 0x0411a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x008d0e60, 0x0418a004 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x00600001, 0x27600021, 0x008d0400, 0x00000000 }, { 0x00600001, 0x27a00021, 0x008d0420, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28a00021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28e00021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x29200021, 0x008d04e0, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x2a503dad, 0x00450a50, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000032 }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a005 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a005 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a006 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000029 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0414a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000001d }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a005 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a005 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x00ad0e60, 0x0414a005 }, { 0x00800031, 0x25a01d29, 0x00ad0e60, 0x0414a006 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x00600001, 0x29400129, 0x008d0400, 0x00000000 }, { 0x00600001, 0x29600129, 0x008d0420, 0x00000000 }, { 0x00600001, 0x29800129, 0x008d0440, 0x00000000 }, { 0x00600001, 0x29a00129, 0x008d0460, 0x00000000 }, { 0x00600001, 0x29c00129, 0x008d0480, 0x00000000 }, { 0x00600001, 0x29e00129, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x2a000129, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x2a200129, 0x008d04e0, 0x00000000 }, { 0x0020000c, 0x2a583dad, 0x00450a58, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a58, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x40004000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a58, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000032 }, { 0x01000005, 0x20003dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a005 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a005 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a006 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000029 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0414a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000001d }, { 0x01000005, 0x20003dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x008d0e60, 0x0414a005 }, { 0x00800031, 0x25a01d29, 0x008d0e60, 0x0414a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x008d0e60, 0x0411a005 }, { 0x00800031, 0x26201d29, 0x008d0e60, 0x0411a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x00ad0e60, 0x0414a005 }, { 0x00800031, 0x25a01d29, 0x00ad0e60, 0x0414a006 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x00600001, 0x29500129, 0x008d0400, 0x00000000 }, { 0x00600001, 0x29700129, 0x008d0420, 0x00000000 }, { 0x00600001, 0x29900129, 0x008d0440, 0x00000000 }, { 0x00600001, 0x29b00129, 0x008d0460, 0x00000000 }, { 0x00600001, 0x29d00129, 0x008d0480, 0x00000000 }, { 0x00600001, 0x29f00129, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x2a100129, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x2a300129, 0x008d04e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05902000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_field_pred_forward.g4b.gen5000066400000000000000000000734751231401140700263750ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000008a }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a004 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000058 }, { 0x01000005, 0x20002dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x00600001, 0x27400021, 0x008d0400, 0x00000000 }, { 0x00600001, 0x27800021, 0x008d0420, 0x00000000 }, { 0x00600001, 0x27c00021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28c00021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x29000021, 0x008d04e0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a58, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x40004000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20002dbc, 0x00210a58, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000008a }, { 0x01000005, 0x20002dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a004 }, { 0x00800040, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x00800040, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x00800040, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x00800040, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x00800040, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x00800040, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x00800040, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x00800040, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10501 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10541 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b10581 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b105c1 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10601 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10641 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b10681 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b106c1 }, { 0x00800040, 0x24004529, 0x00b10400, 0x00b10541 }, { 0x00800040, 0x24204529, 0x00b10420, 0x00b10581 }, { 0x00800040, 0x24404529, 0x00b10440, 0x00b105c1 }, { 0x00800040, 0x24604529, 0x00b10460, 0x00b10601 }, { 0x00800040, 0x24804529, 0x00b10480, 0x00b10641 }, { 0x00800040, 0x24a04529, 0x00b104a0, 0x00b10681 }, { 0x00800040, 0x24c04529, 0x00b104c0, 0x00b106c1 }, { 0x00800040, 0x24e04529, 0x00b104e0, 0x00b10701 }, { 0x00800008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00800008, 0x24202d29, 0x00b10420, 0x00020002 }, { 0x00800008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00800008, 0x24602d29, 0x00b10460, 0x00020002 }, { 0x00800008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00800008, 0x24a02d29, 0x00b104a0, 0x00020002 }, { 0x00800008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00800008, 0x24e02d29, 0x00b104e0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b106c1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000058 }, { 0x01000005, 0x20002dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002e }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x27001d29, 0x408d0e60, 0x0218a004 }, { 0x80800042, 0x24004629, 0x00b10500, 0x00b10540 }, { 0x80800042, 0x24204629, 0x00b10540, 0x00b10580 }, { 0x80800042, 0x24404629, 0x00b10580, 0x00b105c0 }, { 0x80800042, 0x24604629, 0x00b105c0, 0x00b10600 }, { 0x80800042, 0x24804629, 0x00b10600, 0x00b10640 }, { 0x80800042, 0x24a04629, 0x00b10640, 0x00b10680 }, { 0x80800042, 0x24c04629, 0x00b10680, 0x00b106c0 }, { 0x80800042, 0x24e04629, 0x00b106c0, 0x00b10700 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25401d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00800031, 0x25c01d29, 0x408d0e60, 0x0218a004 }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000002 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007001f }, { 0x00800031, 0x26001d29, 0x408d0e60, 0x0288a004 }, { 0x00800001, 0x24000229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x24400229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x24600229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x24800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00b106c0, 0x00000000 }, { 0x00600001, 0x27600021, 0x008d0400, 0x00000000 }, { 0x00600001, 0x27a00021, 0x008d0420, 0x00000000 }, { 0x00600001, 0x27e00021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28a00021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28e00021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x29200021, 0x008d04e0, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x2a503dad, 0x00450a50, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x10001000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a50, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000064 }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a005 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a005 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a006 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0248a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000003a }, { 0x01000005, 0x20003dbc, 0x00210a52, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a005 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a005 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x40ad0e60, 0x0248a005 }, { 0x00800031, 0x25a01d29, 0x40ad0e60, 0x0248a006 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x00600001, 0x29400129, 0x008d0400, 0x00000000 }, { 0x00600001, 0x29600129, 0x008d0420, 0x00000000 }, { 0x00600001, 0x29800129, 0x008d0440, 0x00000000 }, { 0x00600001, 0x29a00129, 0x008d0460, 0x00000000 }, { 0x00600001, 0x29c00129, 0x008d0480, 0x00000000 }, { 0x00600001, 0x29e00129, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x2a000129, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x2a200129, 0x008d04e0, 0x00000000 }, { 0x0020000c, 0x2a583dad, 0x00450a58, 0x00010001 }, { 0x0020000c, 0x23ee3dad, 0x00450a58, 0x00010001 }, { 0x00000009, 0x23f03dad, 0x002103f0, 0x00010001 }, { 0x00200040, 0x2e603421, 0x004503e0, 0x004503ee }, { 0x00000005, 0x2e640c21, 0x00210e64, 0xfffffffe }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x40004000 }, { 0x00010040, 0x2e640c21, 0x00210e64, 0x00000001 }, { 0x01000005, 0x20003dbc, 0x00210a58, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000064 }, { 0x01000005, 0x20003dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a005 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0001000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a005 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a006 }, { 0x00800040, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800040, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800040, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800040, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0501 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0521 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0541 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0561 }, { 0x00800040, 0x24004529, 0x00ad0400, 0x00ad0521 }, { 0x00800040, 0x24204529, 0x00ad0420, 0x00ad0541 }, { 0x00800040, 0x24404529, 0x00ad0440, 0x00ad0561 }, { 0x00800040, 0x24604529, 0x00ad0460, 0x00ad0581 }, { 0x00800040, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800040, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800040, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800040, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05a1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05c1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad05e1 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0601 }, { 0x00800040, 0x24804529, 0x00ad0480, 0x00ad05c1 }, { 0x00800040, 0x24a04529, 0x00ad04a0, 0x00ad05e1 }, { 0x00800040, 0x24c04529, 0x00ad04c0, 0x00ad0601 }, { 0x00800040, 0x24e04529, 0x00ad04e0, 0x00ad0621 }, { 0x00a02008, 0x24002d29, 0x00b10400, 0x00020002 }, { 0x00a02008, 0x24402d29, 0x00b10440, 0x00020002 }, { 0x00a02008, 0x24802d29, 0x00b10480, 0x00020002 }, { 0x00a02008, 0x24c02d29, 0x00b104c0, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0248a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0501 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0521 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0541 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0561 }, { 0x00800042, 0x24804629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x24a04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x24c04629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x24e04629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000003a }, { 0x01000005, 0x20003dbc, 0x00210a5a, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x408d0e60, 0x0248a005 }, { 0x00800031, 0x25a01d29, 0x408d0e60, 0x0248a006 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0000000f }, { 0x00000040, 0x2e640c21, 0x00210e64, 0x00000008 }, { 0x00800031, 0x25801d29, 0x408d0e60, 0x0218a005 }, { 0x00800031, 0x26201d29, 0x408d0e60, 0x0218a006 }, { 0x00800042, 0x24004629, 0x00ad0500, 0x00ad0520 }, { 0x00800042, 0x24204629, 0x00ad0520, 0x00ad0540 }, { 0x00800042, 0x24404629, 0x00ad0540, 0x00ad0560 }, { 0x00800042, 0x24604629, 0x00ad0560, 0x00ad0580 }, { 0x00800042, 0x24804629, 0x00ad05a0, 0x00ad05c0 }, { 0x00800042, 0x24a04629, 0x00ad05c0, 0x00ad05e0 }, { 0x00800042, 0x24c04629, 0x00ad05e0, 0x00ad0600 }, { 0x00800042, 0x24e04629, 0x00ad0600, 0x00ad0620 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x2e680061, 0x00000000, 0x0007000f }, { 0x00800031, 0x25001d29, 0x40ad0e60, 0x0248a005 }, { 0x00800031, 0x25a01d29, 0x40ad0e60, 0x0248a006 }, { 0x00800001, 0x24000229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x24200229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x24400229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x24600229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x24800229, 0x00ad05a0, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00ad05c0, 0x00000000 }, { 0x00800001, 0x24c00229, 0x00ad05e0, 0x00000000 }, { 0x00800001, 0x24e00229, 0x00ad0600, 0x00000000 }, { 0x00600001, 0x29500129, 0x008d0400, 0x00000000 }, { 0x00600001, 0x29700129, 0x008d0420, 0x00000000 }, { 0x00600001, 0x29900129, 0x008d0440, 0x00000000 }, { 0x00600001, 0x29b00129, 0x008d0460, 0x00000000 }, { 0x00600001, 0x29d00129, 0x008d0480, 0x00000000 }, { 0x00600001, 0x29f00129, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x2a100129, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x2a300129, 0x008d04e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x12082000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_frame_pred_backward.g4a000066400000000000000000000047121231401140700256440ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g32: message descriptor for reading reference data g58~g81:reference data g82: thread payload backup g83~g106:IDCT data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov(2) g31.0<1>UD g82.12<2,2,1>UW {align1}; mov (1) g126.8<1>UD ip {align1}; mov (1) ip g21.0<1,1,1>UD {align1}; //Y, (x', y') = (x, y) + (motion_vector.x >> 1, motion_vector.y >> 1) asr (2) g31.14<1>W g82.20<2,2,1>W 1W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; define(`input_surface', `7') define(`mv1', `g82.20') define(`mv2', `g82.22') include(`motion_frame_y.g4i') //UV, (x', y') = (x >> 1, y >> 1) + (motion_vector.x >> 2, motion_vector.y >> 2) shr (2) g31.0<1>UD g31.0<2,2,1>UD 1UD {align1}; asr (2) g31.14<1>W g82.20<2,2,1>W 2W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; define(`input_surface1', `8') define(`input_surface2', `9') include(`motion_frame_uv.g4i') include(`addidct.g4i') send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_frame_pred_backward.g4b000066400000000000000000000475071231401140700256560ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a54, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005f }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a007 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x00800040, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x00800040, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x00800040, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x00800040, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x00800040, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x00800040, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x00800040, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e0 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10500 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10520 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10540 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10560 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10580 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a0 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e0 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10600 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10620 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10640 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10660 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10680 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a0 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e1 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10501 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10521 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10541 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10561 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10581 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a1 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c1 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e1 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10601 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10621 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10641 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10661 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10681 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a1 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x80800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x80800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x80800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x80800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x80800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x80800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x80800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x80800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x80800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x80800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x80800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x80800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x80800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x80800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x80800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x80800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000043 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002e }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a007 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104e0 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b10500 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10520 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10540 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10560 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10580 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b105a0 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105c0 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105e0 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b10600 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10620 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10640 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10660 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10680 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b106a0 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b104e0, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10520, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10560, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b105a0, 0x00000000 }, { 0x00800001, 0x28400229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b105e0, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10620, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10660, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b106a0, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a54, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000004e }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x008d0400, 0x0418a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0418a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x008d0400, 0x0411a008 }, { 0x00800031, 0x26801d29, 0x008d0400, 0x0411a009 }, { 0x00600040, 0x29404629, 0x008d0440, 0x008d0441 }, { 0x00600040, 0x29504629, 0x008d0460, 0x008d0461 }, { 0x00600040, 0x29604629, 0x008d0480, 0x008d0481 }, { 0x00600040, 0x29704629, 0x008d04a0, 0x008d04a1 }, { 0x00600040, 0x29804629, 0x008d04c0, 0x008d04c1 }, { 0x00600040, 0x29904629, 0x008d04e0, 0x008d04e1 }, { 0x00600040, 0x29a04629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29b04629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0460 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0480 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a0 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c0 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e0 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0500 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0520 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0540 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0461 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0481 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a1 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c1 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e1 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0501 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0521 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0541 }, { 0x00600040, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600040, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600040, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a004629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a104629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a204629, 0x008d0640, 0x008d0641 }, { 0x00600040, 0x2a304629, 0x008d0660, 0x008d0661 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c0 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e0 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0600 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0620 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0640 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0660 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0680 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c1 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e1 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0601 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0621 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0641 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0661 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0681 }, { 0x00800008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00800008, 0x29602d29, 0x00b10960, 0x00020002 }, { 0x00800008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00800008, 0x29a02d29, 0x00b109a0, 0x00020002 }, { 0x00800008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00800008, 0x29e02d29, 0x00b109e0, 0x00020002 }, { 0x00800008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00800008, 0x2a202d29, 0x00b10a20, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000031 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24401d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a009 }, { 0x00800042, 0x29404629, 0x00ad0440, 0x00ad0441 }, { 0x00800042, 0x29604629, 0x00ad0460, 0x00ad0461 }, { 0x00800042, 0x29804629, 0x00ad0480, 0x00ad0481 }, { 0x00800042, 0x29a04629, 0x00ad04a0, 0x00ad04a1 }, { 0x00800042, 0x29c04629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x29e04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x2a004629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x2a204629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000025 }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x008d0400, 0x0418a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0418a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x008d0400, 0x0411a008 }, { 0x00800031, 0x26801d29, 0x008d0400, 0x0411a009 }, { 0x00600042, 0x29404629, 0x008d0440, 0x008d0460 }, { 0x00600042, 0x29504629, 0x008d0460, 0x008d0480 }, { 0x00600042, 0x29604629, 0x008d0480, 0x008d04a0 }, { 0x00600042, 0x29704629, 0x008d04a0, 0x008d04c0 }, { 0x00600042, 0x29804629, 0x008d04c0, 0x008d04e0 }, { 0x00600042, 0x29904629, 0x008d04e0, 0x008d0500 }, { 0x00600042, 0x29a04629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29b04629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d05a0 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05c0 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a004629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a104629, 0x008d0620, 0x008d0640 }, { 0x00600042, 0x2a204629, 0x008d0640, 0x008d0660 }, { 0x00600042, 0x2a304629, 0x008d0660, 0x008d0680 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24801d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a009 }, { 0x00800001, 0x29400229, 0x00ad0480, 0x00000000 }, { 0x00800001, 0x29600229, 0x00ad04a0, 0x00000000 }, { 0x00800001, 0x29800229, 0x00ad04c0, 0x00000000 }, { 0x00800001, 0x29a00229, 0x00ad04e0, 0x00000000 }, { 0x00800001, 0x29c00229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x29e00229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x2a000229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x2a200229, 0x00ad0560, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05902000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_frame_pred_backward.g4b.gen5000066400000000000000000000475071231401140700265130ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a54, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000be }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000090 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a007 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x00800040, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x00800040, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x00800040, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x00800040, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x00800040, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x00800040, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x00800040, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e0 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10500 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10520 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10540 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10560 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10580 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a0 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e0 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10600 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10620 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10640 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10660 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10680 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a0 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e1 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10501 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10521 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10541 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10561 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10581 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a1 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c1 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e1 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10601 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10621 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10641 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10661 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10681 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a1 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x80800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x80800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x80800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x80800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x80800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x80800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x80800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x80800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x80800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x80800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x80800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x80800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x80800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x80800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x80800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x80800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000005c }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a007 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104e0 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b10500 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10520 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10540 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10560 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10580 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b105a0 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105c0 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105e0 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b10600 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10620 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10640 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10660 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10680 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b106a0 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000028 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b104e0, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10520, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10560, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b105a0, 0x00000000 }, { 0x00800001, 0x28400229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b105e0, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10620, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10660, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b106a0, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a54, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000009c }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x408d0400, 0x0288a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0288a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x408d0400, 0x0218a008 }, { 0x00800031, 0x26801d29, 0x408d0400, 0x0218a009 }, { 0x00600040, 0x29404629, 0x008d0440, 0x008d0441 }, { 0x00600040, 0x29504629, 0x008d0460, 0x008d0461 }, { 0x00600040, 0x29604629, 0x008d0480, 0x008d0481 }, { 0x00600040, 0x29704629, 0x008d04a0, 0x008d04a1 }, { 0x00600040, 0x29804629, 0x008d04c0, 0x008d04c1 }, { 0x00600040, 0x29904629, 0x008d04e0, 0x008d04e1 }, { 0x00600040, 0x29a04629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29b04629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0460 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0480 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a0 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c0 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e0 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0500 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0520 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0540 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0461 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0481 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a1 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c1 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e1 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0501 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0521 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0541 }, { 0x00600040, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600040, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600040, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a004629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a104629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a204629, 0x008d0640, 0x008d0641 }, { 0x00600040, 0x2a304629, 0x008d0660, 0x008d0661 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c0 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e0 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0600 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0620 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0640 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0660 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0680 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c1 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e1 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0601 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0621 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0641 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0661 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0681 }, { 0x00800008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00800008, 0x29602d29, 0x00b10960, 0x00020002 }, { 0x00800008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00800008, 0x29a02d29, 0x00b109a0, 0x00020002 }, { 0x00800008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00800008, 0x29e02d29, 0x00b109e0, 0x00020002 }, { 0x00800008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00800008, 0x2a202d29, 0x00b10a20, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000062 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24401d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a009 }, { 0x00800042, 0x29404629, 0x00ad0440, 0x00ad0441 }, { 0x00800042, 0x29604629, 0x00ad0460, 0x00ad0461 }, { 0x00800042, 0x29804629, 0x00ad0480, 0x00ad0481 }, { 0x00800042, 0x29a04629, 0x00ad04a0, 0x00ad04a1 }, { 0x00800042, 0x29c04629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x29e04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x2a004629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x2a204629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004a }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x408d0400, 0x0288a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0288a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x408d0400, 0x0218a008 }, { 0x00800031, 0x26801d29, 0x408d0400, 0x0218a009 }, { 0x00600042, 0x29404629, 0x008d0440, 0x008d0460 }, { 0x00600042, 0x29504629, 0x008d0460, 0x008d0480 }, { 0x00600042, 0x29604629, 0x008d0480, 0x008d04a0 }, { 0x00600042, 0x29704629, 0x008d04a0, 0x008d04c0 }, { 0x00600042, 0x29804629, 0x008d04c0, 0x008d04e0 }, { 0x00600042, 0x29904629, 0x008d04e0, 0x008d0500 }, { 0x00600042, 0x29a04629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29b04629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d05a0 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05c0 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a004629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a104629, 0x008d0620, 0x008d0640 }, { 0x00600042, 0x2a204629, 0x008d0640, 0x008d0660 }, { 0x00600042, 0x2a304629, 0x008d0660, 0x008d0680 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24801d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a009 }, { 0x00800001, 0x29400229, 0x00ad0480, 0x00000000 }, { 0x00800001, 0x29600229, 0x00ad04a0, 0x00000000 }, { 0x00800001, 0x29800229, 0x00ad04c0, 0x00000000 }, { 0x00800001, 0x29a00229, 0x00ad04e0, 0x00000000 }, { 0x00800001, 0x29c00229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x29e00229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x2a000229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x2a200229, 0x00ad0560, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x12082000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_frame_pred_bidirect.g4a000066400000000000000000000125551231401140700256570ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g32: message descriptor for reading reference data g58~g81:reference data g82: thread payload backup g83~g106:IDCT data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; mov (1) g126.8<1>UD ip {align1}; mov (1) ip g21.0<1,1,1>UD {align1}; //Y, Forward mov (1) g31.8<1>UD 0x0070007UD {align1}; define(`input_surface', `4') define(`mv1', `g82.16') define(`mv2', `g82.18') asr (2) g31.14<1>W g82.16<2,2,1>W 1W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; include(`motion_frame_y.g4i') //Save Forward mov (16) g108.0<1>UD g58.0<16,16,1>UD {align1 compr}; mov (16) g110.0<1>UD g60.0<16,16,1>UD {align1 compr}; mov (16) g112.0<1>UD g62.0<16,16,1>UD {align1 compr}; mov (16) g114.0<1>UD g64.0<16,16,1>UD {align1 compr}; mov (16) g116.0<1>UD g66.0<16,16,1>UD {align1 compr}; mov (16) g118.0<1>UD g68.0<16,16,1>UD {align1 compr}; mov (16) g120.0<1>UD g70.0<16,16,1>UD {align1 compr}; mov (16) g122.0<1>UD g72.0<16,16,1>UD {align1 compr}; //Y, Backward define(`input_surface', `7') define(`mv1', `g82.20') define(`mv2', `g82.22') asr (2) g31.14<1>W g82.20<2,2,1>W 1W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; include(`motion_frame_y.g4i') //Average Forward and Backward avg.sat (16) g58.0<1>UW g58.0<16,16,1>UW g108.0<16,16,1>UW {align1}; avg.sat (16) g59.0<1>UW g59.0<16,16,1>UW g109.0<16,16,1>UW {align1}; avg.sat (16) g60.0<1>UW g60.0<16,16,1>UW g110.0<16,16,1>UW {align1}; avg.sat (16) g61.0<1>UW g61.0<16,16,1>UW g111.0<16,16,1>UW {align1}; avg.sat (16) g62.0<1>UW g62.0<16,16,1>UW g112.0<16,16,1>UW {align1}; avg.sat (16) g63.0<1>UW g63.0<16,16,1>UW g113.0<16,16,1>UW {align1}; avg.sat (16) g64.0<1>UW g64.0<16,16,1>UW g114.0<16,16,1>UW {align1}; avg.sat (16) g65.0<1>UW g65.0<16,16,1>UW g115.0<16,16,1>UW {align1}; avg.sat (16) g66.0<1>UW g66.0<16,16,1>UW g116.0<16,16,1>UW {align1}; avg.sat (16) g67.0<1>UW g67.0<16,16,1>UW g117.0<16,16,1>UW {align1}; avg.sat (16) g68.0<1>UW g68.0<16,16,1>UW g118.0<16,16,1>UW {align1}; avg.sat (16) g69.0<1>UW g69.0<16,16,1>UW g119.0<16,16,1>UW {align1}; avg.sat (16) g70.0<1>UW g70.0<16,16,1>UW g120.0<16,16,1>UW {align1}; avg.sat (16) g71.0<1>UW g71.0<16,16,1>UW g121.0<16,16,1>UW {align1}; avg.sat (16) g72.0<1>UW g72.0<16,16,1>UW g122.0<16,16,1>UW {align1}; avg.sat (16) g73.0<1>UW g73.0<16,16,1>UW g123.0<16,16,1>UW {align1}; //UV, Forward shr (2) g31.0<1>UD g31.0<2,2,1>UD 1UD {align1}; asr (2) g31.14<1>W g82.16<2,2,1>W 2W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; define(`input_surface1', `5') define(`input_surface2', `6') mov (1) g32.8<1>UD 0x007000fUD {align1}; include(`motion_frame_uv.g4i') //Save UV Forward mov (16) g108.0<1>UB g74.0<16,16,2>UB {align1}; mov (16) g108.16<1>UB g75.0<16,16,2>UB {align1}; mov (16) g109.0<1>UB g76.0<16,16,2>UB {align1}; mov (16) g109.16<1>UB g77.0<16,16,2>UB {align1}; mov (16) g110.0<1>UB g78.0<16,16,2>UB {align1}; mov (16) g110.16<1>UB g79.0<16,16,2>UB {align1}; mov (16) g111.0<1>UB g80.0<16,16,2>UB {align1}; mov (16) g111.16<1>UB g81.0<16,16,2>UB {align1}; //UV, Backward asr (2) g31.14<1>W g82.20<2,2,1>W 2W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; define(`input_surface1', `8') define(`input_surface2', `9') include(`motion_frame_uv.g4i') //Average Forward and Backward avg.sat (16) g74.0<1>UW g74.0<16,16,1>UW g108.0<16,16,1>UB {align1}; avg.sat (16) g75.0<1>UW g75.0<16,16,1>UW g108.16<16,16,1>UB {align1}; avg.sat (16) g76.0<1>UW g76.0<16,16,1>UW g109.0<16,16,1>UB {align1}; avg.sat (16) g77.0<1>UW g77.0<16,16,1>UW g109.16<16,16,1>UB {align1}; avg.sat (16) g78.0<1>UW g78.0<16,16,1>UW g110.0<16,16,1>UB {align1}; avg.sat (16) g79.0<1>UW g79.0<16,16,1>UW g110.16<16,16,1>UB {align1}; avg.sat (16) g80.0<1>UW g80.0<16,16,1>UW g111.0<16,16,1>UB {align1}; avg.sat (16) g81.0<1>UW g81.0<16,16,1>UW g111.16<16,16,1>UB {align1}; include(`addidct.g4i') send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_frame_pred_bidirect.g4b000066400000000000000000001104051231401140700256510ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a50, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005f }, { 0x01000005, 0x20000d3c, 0x00210a52, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a004 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x00800040, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x00800040, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x00800040, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x00800040, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x00800040, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x00800040, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x00800040, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e0 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10500 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10520 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10540 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10560 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10580 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a0 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e0 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10600 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10620 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10640 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10660 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10680 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a0 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e1 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10501 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10521 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10541 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10561 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10581 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a1 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c1 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e1 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10601 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10621 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10641 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10661 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10681 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a1 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x80800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x80800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x80800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x80800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x80800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x80800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x80800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x80800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x80800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x80800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x80800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x80800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x80800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x80800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x80800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x80800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000043 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002e }, { 0x01000005, 0x20000d3c, 0x00210a52, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a004 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104e0 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b10500 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10520 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10540 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10560 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10580 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b105a0 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105c0 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105e0 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b10600 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10620 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10640 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10660 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10680 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b106a0 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b104e0, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10520, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10560, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b105a0, 0x00000000 }, { 0x00800001, 0x28400229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b105e0, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10620, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10660, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b106a0, 0x00000000 }, { 0x00802001, 0x2d800021, 0x00b10740, 0x00000000 }, { 0x00802001, 0x2dc00021, 0x00b10780, 0x00000000 }, { 0x00802001, 0x2e000021, 0x00b107c0, 0x00000000 }, { 0x00802001, 0x2e400021, 0x00b10800, 0x00000000 }, { 0x00802001, 0x2e800021, 0x00b10840, 0x00000000 }, { 0x00802001, 0x2ec00021, 0x00b10880, 0x00000000 }, { 0x00802001, 0x2f000021, 0x00b108c0, 0x00000000 }, { 0x00802001, 0x2f400021, 0x00b10900, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a54, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005f }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a007 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x00800040, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x00800040, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x00800040, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x00800040, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x00800040, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x00800040, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x00800040, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e0 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10500 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10520 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10540 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10560 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10580 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a0 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e0 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10600 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10620 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10640 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10660 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10680 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a0 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e1 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10501 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10521 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10541 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10561 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10581 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a1 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c1 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e1 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10601 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10621 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10641 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10661 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10681 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a1 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x80800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x80800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x80800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x80800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x80800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x80800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x80800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x80800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x80800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x80800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x80800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x80800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x80800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x80800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x80800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x80800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000043 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002e }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a007 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104e0 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b10500 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10520 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10540 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10560 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10580 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b105a0 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105c0 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105e0 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b10600 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10620 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10640 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10660 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10680 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b106a0 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a007 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b104e0, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10520, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10560, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b105a0, 0x00000000 }, { 0x00800001, 0x28400229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b105e0, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10620, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10660, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b106a0, 0x00000000 }, { 0x80800042, 0x27402529, 0x00b10740, 0x00b10d80 }, { 0x80800042, 0x27602529, 0x00b10760, 0x00b10da0 }, { 0x80800042, 0x27802529, 0x00b10780, 0x00b10dc0 }, { 0x80800042, 0x27a02529, 0x00b107a0, 0x00b10de0 }, { 0x80800042, 0x27c02529, 0x00b107c0, 0x00b10e00 }, { 0x80800042, 0x27e02529, 0x00b107e0, 0x00b10e20 }, { 0x80800042, 0x28002529, 0x00b10800, 0x00b10e40 }, { 0x80800042, 0x28202529, 0x00b10820, 0x00b10e60 }, { 0x80800042, 0x28402529, 0x00b10840, 0x00b10e80 }, { 0x80800042, 0x28602529, 0x00b10860, 0x00b10ea0 }, { 0x80800042, 0x28802529, 0x00b10880, 0x00b10ec0 }, { 0x80800042, 0x28a02529, 0x00b108a0, 0x00b10ee0 }, { 0x80800042, 0x28c02529, 0x00b108c0, 0x00b10f00 }, { 0x80800042, 0x28e02529, 0x00b108e0, 0x00b10f20 }, { 0x80800042, 0x29002529, 0x00b10900, 0x00b10f40 }, { 0x80800042, 0x29202529, 0x00b10920, 0x00b10f60 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x01000005, 0x20000d3c, 0x00210a54, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000004e }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x008d0400, 0x0418a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0418a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x008d0400, 0x0411a005 }, { 0x00800031, 0x26801d29, 0x008d0400, 0x0411a006 }, { 0x00600040, 0x29404629, 0x008d0440, 0x008d0441 }, { 0x00600040, 0x29504629, 0x008d0460, 0x008d0461 }, { 0x00600040, 0x29604629, 0x008d0480, 0x008d0481 }, { 0x00600040, 0x29704629, 0x008d04a0, 0x008d04a1 }, { 0x00600040, 0x29804629, 0x008d04c0, 0x008d04c1 }, { 0x00600040, 0x29904629, 0x008d04e0, 0x008d04e1 }, { 0x00600040, 0x29a04629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29b04629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0460 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0480 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a0 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c0 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e0 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0500 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0520 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0540 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0461 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0481 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a1 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c1 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e1 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0501 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0521 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0541 }, { 0x00600040, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600040, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600040, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a004629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a104629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a204629, 0x008d0640, 0x008d0641 }, { 0x00600040, 0x2a304629, 0x008d0660, 0x008d0661 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c0 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e0 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0600 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0620 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0640 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0660 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0680 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c1 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e1 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0601 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0621 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0641 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0661 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0681 }, { 0x00800008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00800008, 0x29602d29, 0x00b10960, 0x00020002 }, { 0x00800008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00800008, 0x29a02d29, 0x00b109a0, 0x00020002 }, { 0x00800008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00800008, 0x29e02d29, 0x00b109e0, 0x00020002 }, { 0x00800008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00800008, 0x2a202d29, 0x00b10a20, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000031 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24401d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a006 }, { 0x00800042, 0x29404629, 0x00ad0440, 0x00ad0441 }, { 0x00800042, 0x29604629, 0x00ad0460, 0x00ad0461 }, { 0x00800042, 0x29804629, 0x00ad0480, 0x00ad0481 }, { 0x00800042, 0x29a04629, 0x00ad04a0, 0x00ad04a1 }, { 0x00800042, 0x29c04629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x29e04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x2a004629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x2a204629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000025 }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x008d0400, 0x0418a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0418a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x008d0400, 0x0411a005 }, { 0x00800031, 0x26801d29, 0x008d0400, 0x0411a006 }, { 0x00600042, 0x29404629, 0x008d0440, 0x008d0460 }, { 0x00600042, 0x29504629, 0x008d0460, 0x008d0480 }, { 0x00600042, 0x29604629, 0x008d0480, 0x008d04a0 }, { 0x00600042, 0x29704629, 0x008d04a0, 0x008d04c0 }, { 0x00600042, 0x29804629, 0x008d04c0, 0x008d04e0 }, { 0x00600042, 0x29904629, 0x008d04e0, 0x008d0500 }, { 0x00600042, 0x29a04629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29b04629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d05a0 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05c0 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a004629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a104629, 0x008d0620, 0x008d0640 }, { 0x00600042, 0x2a204629, 0x008d0640, 0x008d0660 }, { 0x00600042, 0x2a304629, 0x008d0660, 0x008d0680 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24801d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a006 }, { 0x00800001, 0x29400229, 0x00ad0480, 0x00000000 }, { 0x00800001, 0x29600229, 0x00ad04a0, 0x00000000 }, { 0x00800001, 0x29800229, 0x00ad04c0, 0x00000000 }, { 0x00800001, 0x29a00229, 0x00ad04e0, 0x00000000 }, { 0x00800001, 0x29c00229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x29e00229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x2a000229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x2a200229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x2d800231, 0x00b20940, 0x00000000 }, { 0x00800001, 0x2d900231, 0x00b20960, 0x00000000 }, { 0x00800001, 0x2da00231, 0x00b20980, 0x00000000 }, { 0x00800001, 0x2db00231, 0x00b209a0, 0x00000000 }, { 0x00800001, 0x2dc00231, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x2dd00231, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x2de00231, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x2df00231, 0x00b20a20, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a54, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000004e }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x008d0400, 0x0418a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0418a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x008d0400, 0x0411a008 }, { 0x00800031, 0x26801d29, 0x008d0400, 0x0411a009 }, { 0x00600040, 0x29404629, 0x008d0440, 0x008d0441 }, { 0x00600040, 0x29504629, 0x008d0460, 0x008d0461 }, { 0x00600040, 0x29604629, 0x008d0480, 0x008d0481 }, { 0x00600040, 0x29704629, 0x008d04a0, 0x008d04a1 }, { 0x00600040, 0x29804629, 0x008d04c0, 0x008d04c1 }, { 0x00600040, 0x29904629, 0x008d04e0, 0x008d04e1 }, { 0x00600040, 0x29a04629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29b04629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0460 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0480 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a0 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c0 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e0 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0500 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0520 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0540 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0461 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0481 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a1 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c1 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e1 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0501 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0521 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0541 }, { 0x00600040, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600040, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600040, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a004629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a104629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a204629, 0x008d0640, 0x008d0641 }, { 0x00600040, 0x2a304629, 0x008d0660, 0x008d0661 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c0 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e0 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0600 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0620 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0640 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0660 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0680 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c1 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e1 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0601 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0621 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0641 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0661 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0681 }, { 0x00800008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00800008, 0x29602d29, 0x00b10960, 0x00020002 }, { 0x00800008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00800008, 0x29a02d29, 0x00b109a0, 0x00020002 }, { 0x00800008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00800008, 0x29e02d29, 0x00b109e0, 0x00020002 }, { 0x00800008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00800008, 0x2a202d29, 0x00b10a20, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000031 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24401d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a009 }, { 0x00800042, 0x29404629, 0x00ad0440, 0x00ad0441 }, { 0x00800042, 0x29604629, 0x00ad0460, 0x00ad0461 }, { 0x00800042, 0x29804629, 0x00ad0480, 0x00ad0481 }, { 0x00800042, 0x29a04629, 0x00ad04a0, 0x00ad04a1 }, { 0x00800042, 0x29c04629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x29e04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x2a004629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x2a204629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000025 }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x008d0400, 0x0418a008 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0418a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x008d0400, 0x0411a008 }, { 0x00800031, 0x26801d29, 0x008d0400, 0x0411a009 }, { 0x00600042, 0x29404629, 0x008d0440, 0x008d0460 }, { 0x00600042, 0x29504629, 0x008d0460, 0x008d0480 }, { 0x00600042, 0x29604629, 0x008d0480, 0x008d04a0 }, { 0x00600042, 0x29704629, 0x008d04a0, 0x008d04c0 }, { 0x00600042, 0x29804629, 0x008d04c0, 0x008d04e0 }, { 0x00600042, 0x29904629, 0x008d04e0, 0x008d0500 }, { 0x00600042, 0x29a04629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29b04629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d05a0 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05c0 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a004629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a104629, 0x008d0620, 0x008d0640 }, { 0x00600042, 0x2a204629, 0x008d0640, 0x008d0660 }, { 0x00600042, 0x2a304629, 0x008d0660, 0x008d0680 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24801d29, 0x008d0400, 0x0414a008 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a009 }, { 0x00800001, 0x29400229, 0x00ad0480, 0x00000000 }, { 0x00800001, 0x29600229, 0x00ad04a0, 0x00000000 }, { 0x00800001, 0x29800229, 0x00ad04c0, 0x00000000 }, { 0x00800001, 0x29a00229, 0x00ad04e0, 0x00000000 }, { 0x00800001, 0x29c00229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x29e00229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x2a000229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x2a200229, 0x00ad0560, 0x00000000 }, { 0x80800042, 0x29404529, 0x00b10940, 0x00b10d80 }, { 0x80800042, 0x29604529, 0x00b10960, 0x00b10d90 }, { 0x80800042, 0x29804529, 0x00b10980, 0x00b10da0 }, { 0x80800042, 0x29a04529, 0x00b109a0, 0x00b10db0 }, { 0x80800042, 0x29c04529, 0x00b109c0, 0x00b10dc0 }, { 0x80800042, 0x29e04529, 0x00b109e0, 0x00b10dd0 }, { 0x80800042, 0x2a004529, 0x00b10a00, 0x00b10de0 }, { 0x80800042, 0x2a204529, 0x00b10a20, 0x00b10df0 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05902000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_frame_pred_bidirect.g4b.gen5000066400000000000000000001104051231401140700265060ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a50, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000be }, { 0x01000005, 0x20000d3c, 0x00210a52, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000090 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a004 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x00800040, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x00800040, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x00800040, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x00800040, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x00800040, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x00800040, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x00800040, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e0 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10500 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10520 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10540 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10560 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10580 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a0 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e0 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10600 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10620 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10640 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10660 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10680 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a0 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e1 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10501 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10521 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10541 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10561 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10581 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a1 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c1 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e1 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10601 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10621 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10641 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10661 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10681 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a1 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x80800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x80800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x80800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x80800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x80800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x80800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x80800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x80800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x80800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x80800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x80800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x80800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x80800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x80800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x80800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x80800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000005c }, { 0x01000005, 0x20000d3c, 0x00210a52, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a004 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104e0 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b10500 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10520 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10540 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10560 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10580 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b105a0 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105c0 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105e0 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b10600 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10620 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10640 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10660 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10680 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b106a0 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000028 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b104e0, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10520, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10560, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b105a0, 0x00000000 }, { 0x00800001, 0x28400229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b105e0, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10620, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10660, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b106a0, 0x00000000 }, { 0x00802001, 0x2d800021, 0x00b10740, 0x00000000 }, { 0x00802001, 0x2dc00021, 0x00b10780, 0x00000000 }, { 0x00802001, 0x2e000021, 0x00b107c0, 0x00000000 }, { 0x00802001, 0x2e400021, 0x00b10800, 0x00000000 }, { 0x00802001, 0x2e800021, 0x00b10840, 0x00000000 }, { 0x00802001, 0x2ec00021, 0x00b10880, 0x00000000 }, { 0x00802001, 0x2f000021, 0x00b108c0, 0x00000000 }, { 0x00802001, 0x2f400021, 0x00b10900, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a54, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000be }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000090 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a007 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x00800040, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x00800040, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x00800040, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x00800040, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x00800040, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x00800040, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x00800040, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e0 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10500 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10520 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10540 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10560 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10580 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a0 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e0 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10600 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10620 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10640 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10660 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10680 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a0 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e1 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10501 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10521 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10541 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10561 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10581 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a1 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c1 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e1 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10601 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10621 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10641 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10661 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10681 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a1 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x80800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x80800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x80800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x80800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x80800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x80800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x80800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x80800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x80800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x80800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x80800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x80800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x80800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x80800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x80800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x80800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000005c }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a007 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104e0 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b10500 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10520 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10540 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10560 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10580 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b105a0 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105c0 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105e0 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b10600 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10620 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10640 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10660 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10680 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b106a0 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000028 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a007 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a007 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b104e0, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10520, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10560, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b105a0, 0x00000000 }, { 0x00800001, 0x28400229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b105e0, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10620, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10660, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b106a0, 0x00000000 }, { 0x80800042, 0x27402529, 0x00b10740, 0x00b10d80 }, { 0x80800042, 0x27602529, 0x00b10760, 0x00b10da0 }, { 0x80800042, 0x27802529, 0x00b10780, 0x00b10dc0 }, { 0x80800042, 0x27a02529, 0x00b107a0, 0x00b10de0 }, { 0x80800042, 0x27c02529, 0x00b107c0, 0x00b10e00 }, { 0x80800042, 0x27e02529, 0x00b107e0, 0x00b10e20 }, { 0x80800042, 0x28002529, 0x00b10800, 0x00b10e40 }, { 0x80800042, 0x28202529, 0x00b10820, 0x00b10e60 }, { 0x80800042, 0x28402529, 0x00b10840, 0x00b10e80 }, { 0x80800042, 0x28602529, 0x00b10860, 0x00b10ea0 }, { 0x80800042, 0x28802529, 0x00b10880, 0x00b10ec0 }, { 0x80800042, 0x28a02529, 0x00b108a0, 0x00b10ee0 }, { 0x80800042, 0x28c02529, 0x00b108c0, 0x00b10f00 }, { 0x80800042, 0x28e02529, 0x00b108e0, 0x00b10f20 }, { 0x80800042, 0x29002529, 0x00b10900, 0x00b10f40 }, { 0x80800042, 0x29202529, 0x00b10920, 0x00b10f60 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x01000005, 0x20000d3c, 0x00210a54, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000009c }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x408d0400, 0x0288a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0288a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x408d0400, 0x0218a005 }, { 0x00800031, 0x26801d29, 0x408d0400, 0x0218a006 }, { 0x00600040, 0x29404629, 0x008d0440, 0x008d0441 }, { 0x00600040, 0x29504629, 0x008d0460, 0x008d0461 }, { 0x00600040, 0x29604629, 0x008d0480, 0x008d0481 }, { 0x00600040, 0x29704629, 0x008d04a0, 0x008d04a1 }, { 0x00600040, 0x29804629, 0x008d04c0, 0x008d04c1 }, { 0x00600040, 0x29904629, 0x008d04e0, 0x008d04e1 }, { 0x00600040, 0x29a04629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29b04629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0460 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0480 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a0 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c0 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e0 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0500 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0520 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0540 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0461 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0481 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a1 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c1 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e1 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0501 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0521 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0541 }, { 0x00600040, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600040, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600040, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a004629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a104629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a204629, 0x008d0640, 0x008d0641 }, { 0x00600040, 0x2a304629, 0x008d0660, 0x008d0661 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c0 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e0 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0600 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0620 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0640 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0660 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0680 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c1 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e1 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0601 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0621 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0641 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0661 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0681 }, { 0x00800008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00800008, 0x29602d29, 0x00b10960, 0x00020002 }, { 0x00800008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00800008, 0x29a02d29, 0x00b109a0, 0x00020002 }, { 0x00800008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00800008, 0x29e02d29, 0x00b109e0, 0x00020002 }, { 0x00800008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00800008, 0x2a202d29, 0x00b10a20, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000062 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24401d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a006 }, { 0x00800042, 0x29404629, 0x00ad0440, 0x00ad0441 }, { 0x00800042, 0x29604629, 0x00ad0460, 0x00ad0461 }, { 0x00800042, 0x29804629, 0x00ad0480, 0x00ad0481 }, { 0x00800042, 0x29a04629, 0x00ad04a0, 0x00ad04a1 }, { 0x00800042, 0x29c04629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x29e04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x2a004629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x2a204629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004a }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x408d0400, 0x0288a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0288a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x408d0400, 0x0218a005 }, { 0x00800031, 0x26801d29, 0x408d0400, 0x0218a006 }, { 0x00600042, 0x29404629, 0x008d0440, 0x008d0460 }, { 0x00600042, 0x29504629, 0x008d0460, 0x008d0480 }, { 0x00600042, 0x29604629, 0x008d0480, 0x008d04a0 }, { 0x00600042, 0x29704629, 0x008d04a0, 0x008d04c0 }, { 0x00600042, 0x29804629, 0x008d04c0, 0x008d04e0 }, { 0x00600042, 0x29904629, 0x008d04e0, 0x008d0500 }, { 0x00600042, 0x29a04629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29b04629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d05a0 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05c0 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a004629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a104629, 0x008d0620, 0x008d0640 }, { 0x00600042, 0x2a204629, 0x008d0640, 0x008d0660 }, { 0x00600042, 0x2a304629, 0x008d0660, 0x008d0680 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24801d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a006 }, { 0x00800001, 0x29400229, 0x00ad0480, 0x00000000 }, { 0x00800001, 0x29600229, 0x00ad04a0, 0x00000000 }, { 0x00800001, 0x29800229, 0x00ad04c0, 0x00000000 }, { 0x00800001, 0x29a00229, 0x00ad04e0, 0x00000000 }, { 0x00800001, 0x29c00229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x29e00229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x2a000229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x2a200229, 0x00ad0560, 0x00000000 }, { 0x00800001, 0x2d800231, 0x00b20940, 0x00000000 }, { 0x00800001, 0x2d900231, 0x00b20960, 0x00000000 }, { 0x00800001, 0x2da00231, 0x00b20980, 0x00000000 }, { 0x00800001, 0x2db00231, 0x00b209a0, 0x00000000 }, { 0x00800001, 0x2dc00231, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x2dd00231, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x2de00231, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x2df00231, 0x00b20a20, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a54, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a54, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000009c }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x408d0400, 0x0288a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0288a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x408d0400, 0x0218a008 }, { 0x00800031, 0x26801d29, 0x408d0400, 0x0218a009 }, { 0x00600040, 0x29404629, 0x008d0440, 0x008d0441 }, { 0x00600040, 0x29504629, 0x008d0460, 0x008d0461 }, { 0x00600040, 0x29604629, 0x008d0480, 0x008d0481 }, { 0x00600040, 0x29704629, 0x008d04a0, 0x008d04a1 }, { 0x00600040, 0x29804629, 0x008d04c0, 0x008d04c1 }, { 0x00600040, 0x29904629, 0x008d04e0, 0x008d04e1 }, { 0x00600040, 0x29a04629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29b04629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0460 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0480 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a0 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c0 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e0 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0500 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0520 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0540 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0461 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0481 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a1 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c1 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e1 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0501 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0521 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0541 }, { 0x00600040, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600040, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600040, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a004629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a104629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a204629, 0x008d0640, 0x008d0641 }, { 0x00600040, 0x2a304629, 0x008d0660, 0x008d0661 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c0 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e0 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0600 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0620 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0640 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0660 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0680 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c1 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e1 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0601 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0621 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0641 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0661 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0681 }, { 0x00800008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00800008, 0x29602d29, 0x00b10960, 0x00020002 }, { 0x00800008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00800008, 0x29a02d29, 0x00b109a0, 0x00020002 }, { 0x00800008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00800008, 0x29e02d29, 0x00b109e0, 0x00020002 }, { 0x00800008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00800008, 0x2a202d29, 0x00b10a20, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000062 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24401d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a009 }, { 0x00800042, 0x29404629, 0x00ad0440, 0x00ad0441 }, { 0x00800042, 0x29604629, 0x00ad0460, 0x00ad0461 }, { 0x00800042, 0x29804629, 0x00ad0480, 0x00ad0481 }, { 0x00800042, 0x29a04629, 0x00ad04a0, 0x00ad04a1 }, { 0x00800042, 0x29c04629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x29e04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x2a004629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x2a204629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004a }, { 0x01000005, 0x20000d3c, 0x00210a56, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x408d0400, 0x0288a008 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0288a009 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x408d0400, 0x0218a008 }, { 0x00800031, 0x26801d29, 0x408d0400, 0x0218a009 }, { 0x00600042, 0x29404629, 0x008d0440, 0x008d0460 }, { 0x00600042, 0x29504629, 0x008d0460, 0x008d0480 }, { 0x00600042, 0x29604629, 0x008d0480, 0x008d04a0 }, { 0x00600042, 0x29704629, 0x008d04a0, 0x008d04c0 }, { 0x00600042, 0x29804629, 0x008d04c0, 0x008d04e0 }, { 0x00600042, 0x29904629, 0x008d04e0, 0x008d0500 }, { 0x00600042, 0x29a04629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29b04629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d05a0 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05c0 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a004629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a104629, 0x008d0620, 0x008d0640 }, { 0x00600042, 0x2a204629, 0x008d0640, 0x008d0660 }, { 0x00600042, 0x2a304629, 0x008d0660, 0x008d0680 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24801d29, 0x408d0400, 0x0248a008 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a009 }, { 0x00800001, 0x29400229, 0x00ad0480, 0x00000000 }, { 0x00800001, 0x29600229, 0x00ad04a0, 0x00000000 }, { 0x00800001, 0x29800229, 0x00ad04c0, 0x00000000 }, { 0x00800001, 0x29a00229, 0x00ad04e0, 0x00000000 }, { 0x00800001, 0x29c00229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x29e00229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x2a000229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x2a200229, 0x00ad0560, 0x00000000 }, { 0x80800042, 0x29404529, 0x00b10940, 0x00b10d80 }, { 0x80800042, 0x29604529, 0x00b10960, 0x00b10d90 }, { 0x80800042, 0x29804529, 0x00b10980, 0x00b10da0 }, { 0x80800042, 0x29a04529, 0x00b109a0, 0x00b10db0 }, { 0x80800042, 0x29c04529, 0x00b109c0, 0x00b10dc0 }, { 0x80800042, 0x29e04529, 0x00b109e0, 0x00b10dd0 }, { 0x80800042, 0x2a004529, 0x00b10a00, 0x00b10de0 }, { 0x80800042, 0x2a204529, 0x00b10a20, 0x00b10df0 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x12082000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_frame_pred_forward.g4a000066400000000000000000000047131231401140700255330ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g32: message descriptor for reading reference data g58~g81:reference data g82: thread payload backup g83~g106:IDCT data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; mov (1) g126.8<1>UD ip {align1}; mov (1) ip g21.0<1,1,1>UD {align1}; //Y, (x', y') = (x, y) + (motion_vector.x >> 1, motion_vector.y >> 1) asr (2) g31.14<1>W g82.16<2,2,1>W 1W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; define(`input_surface', `4') define(`mv1', `g82.16') define(`mv2', `g82.18') include(`motion_frame_y.g4i') //UV, (x', y') = (x >> 1, y >> 1) + (motion_vector.x >> 2, motion_vector.y >> 2) shr (2) g31.0<1>UD g31.0<2,2,1>UD 1UD {align1}; asr (2) g31.14<1>W g82.16<2,2,1>W 2W {align1}; add (2) g32.0<1>UD g31.0<2,2,1>UD g31.14<2,2,1>W {align1}; define(`input_surface1', `5') define(`input_surface2', `6') include(`motion_frame_uv.g4i') include(`addidct.g4i') send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_frame_pred_forward.g4b000066400000000000000000000475071231401140700255440ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a50, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000005f }, { 0x01000005, 0x20000d3c, 0x00210a52, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000048 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a004 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x00800040, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x00800040, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x00800040, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x00800040, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x00800040, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x00800040, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x00800040, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e0 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10500 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10520 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10540 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10560 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10580 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a0 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e0 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10600 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10620 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10640 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10660 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10680 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a0 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e1 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10501 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10521 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10541 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10561 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10581 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a1 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c1 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e1 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10601 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10621 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10641 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10661 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10681 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a1 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x80800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x80800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x80800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x80800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x80800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x80800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x80800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x80800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x80800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x80800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x80800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x80800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x80800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x80800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x80800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x80800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000043 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002e }, { 0x01000005, 0x20000d3c, 0x00210a52, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x008d0400, 0x0411a004 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104e0 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b10500 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10520 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10540 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10560 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10580 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b105a0 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105c0 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105e0 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b10600 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10620 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10640 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10660 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10680 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b106a0 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x008d0400, 0x0418a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x008d0400, 0x0418a004 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b104e0, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10520, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10560, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b105a0, 0x00000000 }, { 0x00800001, 0x28400229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b105e0, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10620, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10660, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b106a0, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a50, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000004e }, { 0x01000005, 0x20000d3c, 0x00210a52, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x008d0400, 0x0418a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0418a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x008d0400, 0x0411a005 }, { 0x00800031, 0x26801d29, 0x008d0400, 0x0411a006 }, { 0x00600040, 0x29404629, 0x008d0440, 0x008d0441 }, { 0x00600040, 0x29504629, 0x008d0460, 0x008d0461 }, { 0x00600040, 0x29604629, 0x008d0480, 0x008d0481 }, { 0x00600040, 0x29704629, 0x008d04a0, 0x008d04a1 }, { 0x00600040, 0x29804629, 0x008d04c0, 0x008d04c1 }, { 0x00600040, 0x29904629, 0x008d04e0, 0x008d04e1 }, { 0x00600040, 0x29a04629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29b04629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0460 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0480 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a0 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c0 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e0 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0500 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0520 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0540 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0461 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0481 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a1 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c1 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e1 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0501 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0521 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0541 }, { 0x00600040, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600040, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600040, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a004629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a104629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a204629, 0x008d0640, 0x008d0641 }, { 0x00600040, 0x2a304629, 0x008d0660, 0x008d0661 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c0 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e0 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0600 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0620 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0640 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0660 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0680 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c1 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e1 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0601 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0621 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0641 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0661 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0681 }, { 0x00800008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00800008, 0x29602d29, 0x00b10960, 0x00020002 }, { 0x00800008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00800008, 0x29a02d29, 0x00b109a0, 0x00020002 }, { 0x00800008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00800008, 0x29e02d29, 0x00b109e0, 0x00020002 }, { 0x00800008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00800008, 0x2a202d29, 0x00b10a20, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000031 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24401d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0414a006 }, { 0x00800042, 0x29404629, 0x00ad0440, 0x00ad0441 }, { 0x00800042, 0x29604629, 0x00ad0460, 0x00ad0461 }, { 0x00800042, 0x29804629, 0x00ad0480, 0x00ad0481 }, { 0x00800042, 0x29a04629, 0x00ad04a0, 0x00ad04a1 }, { 0x00800042, 0x29c04629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x29e04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x2a004629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x2a204629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000025 }, { 0x01000005, 0x20000d3c, 0x00210a52, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x008d0400, 0x0418a005 }, { 0x00800031, 0x25801d29, 0x008d0400, 0x0418a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x008d0400, 0x0411a005 }, { 0x00800031, 0x26801d29, 0x008d0400, 0x0411a006 }, { 0x00600042, 0x29404629, 0x008d0440, 0x008d0460 }, { 0x00600042, 0x29504629, 0x008d0460, 0x008d0480 }, { 0x00600042, 0x29604629, 0x008d0480, 0x008d04a0 }, { 0x00600042, 0x29704629, 0x008d04a0, 0x008d04c0 }, { 0x00600042, 0x29804629, 0x008d04c0, 0x008d04e0 }, { 0x00600042, 0x29904629, 0x008d04e0, 0x008d0500 }, { 0x00600042, 0x29a04629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29b04629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d05a0 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05c0 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a004629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a104629, 0x008d0620, 0x008d0640 }, { 0x00600042, 0x2a204629, 0x008d0640, 0x008d0660 }, { 0x00600042, 0x2a304629, 0x008d0660, 0x008d0680 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000b }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24801d29, 0x008d0400, 0x0414a005 }, { 0x00800031, 0x25001d29, 0x008d0400, 0x0414a006 }, { 0x00800001, 0x29400229, 0x00ad0480, 0x00000000 }, { 0x00800001, 0x29600229, 0x00ad04a0, 0x00000000 }, { 0x00800001, 0x29800229, 0x00ad04c0, 0x00000000 }, { 0x00800001, 0x29a00229, 0x00ad04e0, 0x00000000 }, { 0x00800001, 0x29c00229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x29e00229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x2a000229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x2a200229, 0x00ad0560, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05902000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_frame_pred_forward.g4b.gen5000066400000000000000000000475071231401140700264010ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000001, 0x2fc80001, 0x00001400, 0x00000000 }, { 0x00000001, 0x34000020, 0x002102a0, 0x00000000 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00010001 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a50, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000be }, { 0x01000005, 0x20000d3c, 0x00210a52, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000090 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a004 }, { 0x00800040, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x00800040, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x00800040, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x00800040, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x00800040, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x00800040, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x00800040, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x00800040, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x00800040, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x00800040, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x00800040, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x00800040, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x00800040, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x00800040, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x00800040, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x00800040, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e0 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10500 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10520 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10540 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10560 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10580 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a0 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c0 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e0 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10600 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10620 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10640 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10660 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10680 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a0 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c0 }, { 0x00800040, 0x27404529, 0x00b10740, 0x00b104e1 }, { 0x00800040, 0x27604529, 0x00b10760, 0x00b10501 }, { 0x00800040, 0x27804529, 0x00b10780, 0x00b10521 }, { 0x00800040, 0x27a04529, 0x00b107a0, 0x00b10541 }, { 0x00800040, 0x27c04529, 0x00b107c0, 0x00b10561 }, { 0x00800040, 0x27e04529, 0x00b107e0, 0x00b10581 }, { 0x00800040, 0x28004529, 0x00b10800, 0x00b105a1 }, { 0x00800040, 0x28204529, 0x00b10820, 0x00b105c1 }, { 0x00800040, 0x28404529, 0x00b10840, 0x00b105e1 }, { 0x00800040, 0x28604529, 0x00b10860, 0x00b10601 }, { 0x00800040, 0x28804529, 0x00b10880, 0x00b10621 }, { 0x00800040, 0x28a04529, 0x00b108a0, 0x00b10641 }, { 0x00800040, 0x28c04529, 0x00b108c0, 0x00b10661 }, { 0x00800040, 0x28e04529, 0x00b108e0, 0x00b10681 }, { 0x00800040, 0x29004529, 0x00b10900, 0x00b106a1 }, { 0x00800040, 0x29204529, 0x00b10920, 0x00b106c1 }, { 0x80800008, 0x27402d29, 0x00b10740, 0x00020002 }, { 0x80800008, 0x27602d29, 0x00b10760, 0x00020002 }, { 0x80800008, 0x27802d29, 0x00b10780, 0x00020002 }, { 0x80800008, 0x27a02d29, 0x00b107a0, 0x00020002 }, { 0x80800008, 0x27c02d29, 0x00b107c0, 0x00020002 }, { 0x80800008, 0x27e02d29, 0x00b107e0, 0x00020002 }, { 0x80800008, 0x28002d29, 0x00b10800, 0x00020002 }, { 0x80800008, 0x28202d29, 0x00b10820, 0x00020002 }, { 0x80800008, 0x28402d29, 0x00b10840, 0x00020002 }, { 0x80800008, 0x28602d29, 0x00b10860, 0x00020002 }, { 0x80800008, 0x28802d29, 0x00b10880, 0x00020002 }, { 0x80800008, 0x28a02d29, 0x00b108a0, 0x00020002 }, { 0x80800008, 0x28c02d29, 0x00b108c0, 0x00020002 }, { 0x80800008, 0x28e02d29, 0x00b108e0, 0x00020002 }, { 0x80800008, 0x29002d29, 0x00b10900, 0x00020002 }, { 0x80800008, 0x29202d29, 0x00b10920, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000086 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104c1 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b104e1 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10501 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10521 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10541 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10561 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b10581 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105a1 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105c1 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b105e1 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10601 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10621 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10641 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10661 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b10681 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106a1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000005c }, { 0x01000005, 0x20000d3c, 0x00210a52, 0x00000001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x26c01d29, 0x408d0400, 0x0218a004 }, { 0x80800042, 0x27404629, 0x00b104c0, 0x00b104e0 }, { 0x80800042, 0x27604629, 0x00b104e0, 0x00b10500 }, { 0x80800042, 0x27804629, 0x00b10500, 0x00b10520 }, { 0x80800042, 0x27a04629, 0x00b10520, 0x00b10540 }, { 0x80800042, 0x27c04629, 0x00b10540, 0x00b10560 }, { 0x80800042, 0x27e04629, 0x00b10560, 0x00b10580 }, { 0x80800042, 0x28004629, 0x00b10580, 0x00b105a0 }, { 0x80800042, 0x28204629, 0x00b105a0, 0x00b105c0 }, { 0x80800042, 0x28404629, 0x00b105c0, 0x00b105e0 }, { 0x80800042, 0x28604629, 0x00b105e0, 0x00b10600 }, { 0x80800042, 0x28804629, 0x00b10600, 0x00b10620 }, { 0x80800042, 0x28a04629, 0x00b10620, 0x00b10640 }, { 0x80800042, 0x28c04629, 0x00b10640, 0x00b10660 }, { 0x80800042, 0x28e04629, 0x00b10660, 0x00b10680 }, { 0x80800042, 0x29004629, 0x00b10680, 0x00b106a0 }, { 0x80800042, 0x29204629, 0x00b106a0, 0x00b106c0 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000028 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24c01d29, 0x408d0400, 0x0288a004 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00800031, 0x25c01d29, 0x408d0400, 0x0288a004 }, { 0x00800001, 0x27400229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x27600229, 0x00b104e0, 0x00000000 }, { 0x00800001, 0x27800229, 0x00b10500, 0x00000000 }, { 0x00800001, 0x27a00229, 0x00b10520, 0x00000000 }, { 0x00800001, 0x27c00229, 0x00b10540, 0x00000000 }, { 0x00800001, 0x27e00229, 0x00b10560, 0x00000000 }, { 0x00800001, 0x28000229, 0x00b10580, 0x00000000 }, { 0x00800001, 0x28200229, 0x00b105a0, 0x00000000 }, { 0x00800001, 0x28400229, 0x00b105c0, 0x00000000 }, { 0x00800001, 0x28600229, 0x00b105e0, 0x00000000 }, { 0x00800001, 0x28800229, 0x00b10600, 0x00000000 }, { 0x00800001, 0x28a00229, 0x00b10620, 0x00000000 }, { 0x00800001, 0x28c00229, 0x00b10640, 0x00000000 }, { 0x00800001, 0x28e00229, 0x00b10660, 0x00000000 }, { 0x00800001, 0x29000229, 0x00b10680, 0x00000000 }, { 0x00800001, 0x29200229, 0x00b106a0, 0x00000000 }, { 0x00200008, 0x23e00c21, 0x004503e0, 0x00000001 }, { 0x0020000c, 0x23ee3dad, 0x00450a50, 0x00020002 }, { 0x00200040, 0x24003421, 0x004503e0, 0x004503ee }, { 0x01000005, 0x20000d3c, 0x00210a50, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000009c }, { 0x01000005, 0x20000d3c, 0x00210a52, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x408d0400, 0x0288a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0288a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x408d0400, 0x0218a005 }, { 0x00800031, 0x26801d29, 0x408d0400, 0x0218a006 }, { 0x00600040, 0x29404629, 0x008d0440, 0x008d0441 }, { 0x00600040, 0x29504629, 0x008d0460, 0x008d0461 }, { 0x00600040, 0x29604629, 0x008d0480, 0x008d0481 }, { 0x00600040, 0x29704629, 0x008d04a0, 0x008d04a1 }, { 0x00600040, 0x29804629, 0x008d04c0, 0x008d04c1 }, { 0x00600040, 0x29904629, 0x008d04e0, 0x008d04e1 }, { 0x00600040, 0x29a04629, 0x008d0500, 0x008d0501 }, { 0x00600040, 0x29b04629, 0x008d0520, 0x008d0521 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0460 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0480 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a0 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c0 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e0 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0500 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0520 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0540 }, { 0x00600040, 0x29404529, 0x008d0940, 0x008d0461 }, { 0x00600040, 0x29504529, 0x008d0950, 0x008d0481 }, { 0x00600040, 0x29604529, 0x008d0960, 0x008d04a1 }, { 0x00600040, 0x29704529, 0x008d0970, 0x008d04c1 }, { 0x00600040, 0x29804529, 0x008d0980, 0x008d04e1 }, { 0x00600040, 0x29904529, 0x008d0990, 0x008d0501 }, { 0x00600040, 0x29a04529, 0x008d09a0, 0x008d0521 }, { 0x00600040, 0x29b04529, 0x008d09b0, 0x008d0541 }, { 0x00600040, 0x29c04629, 0x008d0580, 0x008d0581 }, { 0x00600040, 0x29d04629, 0x008d05a0, 0x008d05a1 }, { 0x00600040, 0x29e04629, 0x008d05c0, 0x008d05c1 }, { 0x00600040, 0x29f04629, 0x008d05e0, 0x008d05e1 }, { 0x00600040, 0x2a004629, 0x008d0600, 0x008d0601 }, { 0x00600040, 0x2a104629, 0x008d0620, 0x008d0621 }, { 0x00600040, 0x2a204629, 0x008d0640, 0x008d0641 }, { 0x00600040, 0x2a304629, 0x008d0660, 0x008d0661 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a0 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c0 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e0 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0600 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0620 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0640 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0660 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0680 }, { 0x00600040, 0x29c04529, 0x008d09c0, 0x008d05a1 }, { 0x00600040, 0x29d04529, 0x008d09d0, 0x008d05c1 }, { 0x00600040, 0x29e04529, 0x008d09e0, 0x008d05e1 }, { 0x00600040, 0x29f04529, 0x008d09f0, 0x008d0601 }, { 0x00600040, 0x2a004529, 0x008d0a00, 0x008d0621 }, { 0x00600040, 0x2a104529, 0x008d0a10, 0x008d0641 }, { 0x00600040, 0x2a204529, 0x008d0a20, 0x008d0661 }, { 0x00600040, 0x2a304529, 0x008d0a30, 0x008d0681 }, { 0x00800008, 0x29402d29, 0x00b10940, 0x00020002 }, { 0x00800008, 0x29602d29, 0x00b10960, 0x00020002 }, { 0x00800008, 0x29802d29, 0x00b10980, 0x00020002 }, { 0x00800008, 0x29a02d29, 0x00b109a0, 0x00020002 }, { 0x00800008, 0x29c02d29, 0x00b109c0, 0x00020002 }, { 0x00800008, 0x29e02d29, 0x00b109e0, 0x00020002 }, { 0x00800008, 0x2a002d29, 0x00b10a00, 0x00020002 }, { 0x00800008, 0x2a202d29, 0x00b10a20, 0x00020002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000062 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24401d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0248a006 }, { 0x00800042, 0x29404629, 0x00ad0440, 0x00ad0441 }, { 0x00800042, 0x29604629, 0x00ad0460, 0x00ad0461 }, { 0x00800042, 0x29804629, 0x00ad0480, 0x00ad0481 }, { 0x00800042, 0x29a04629, 0x00ad04a0, 0x00ad04a1 }, { 0x00800042, 0x29c04629, 0x00ad0580, 0x00ad0581 }, { 0x00800042, 0x29e04629, 0x00ad05a0, 0x00ad05a1 }, { 0x00800042, 0x2a004629, 0x00ad05c0, 0x00ad05c1 }, { 0x00800042, 0x2a204629, 0x00ad05e0, 0x00ad05e1 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004a }, { 0x01000005, 0x20000d3c, 0x00210a52, 0x00000002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007001f }, { 0x00800031, 0x24401d29, 0x408d0400, 0x0288a005 }, { 0x00800031, 0x25801d29, 0x408d0400, 0x0288a006 }, { 0x00000040, 0x24040c21, 0x00210404, 0x00000008 }, { 0x00000001, 0x24080061, 0x00000000, 0x0000001f }, { 0x00800031, 0x25401d29, 0x408d0400, 0x0218a005 }, { 0x00800031, 0x26801d29, 0x408d0400, 0x0218a006 }, { 0x00600042, 0x29404629, 0x008d0440, 0x008d0460 }, { 0x00600042, 0x29504629, 0x008d0460, 0x008d0480 }, { 0x00600042, 0x29604629, 0x008d0480, 0x008d04a0 }, { 0x00600042, 0x29704629, 0x008d04a0, 0x008d04c0 }, { 0x00600042, 0x29804629, 0x008d04c0, 0x008d04e0 }, { 0x00600042, 0x29904629, 0x008d04e0, 0x008d0500 }, { 0x00600042, 0x29a04629, 0x008d0500, 0x008d0520 }, { 0x00600042, 0x29b04629, 0x008d0520, 0x008d0540 }, { 0x00600042, 0x29c04629, 0x008d0580, 0x008d05a0 }, { 0x00600042, 0x29d04629, 0x008d05a0, 0x008d05c0 }, { 0x00600042, 0x29e04629, 0x008d05c0, 0x008d05e0 }, { 0x00600042, 0x29f04629, 0x008d05e0, 0x008d0600 }, { 0x00600042, 0x2a004629, 0x008d0600, 0x008d0620 }, { 0x00600042, 0x2a104629, 0x008d0620, 0x008d0640 }, { 0x00600042, 0x2a204629, 0x008d0640, 0x008d0660 }, { 0x00600042, 0x2a304629, 0x008d0660, 0x008d0680 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x24080061, 0x00000000, 0x0007000f }, { 0x00800031, 0x24801d29, 0x408d0400, 0x0248a005 }, { 0x00800031, 0x25001d29, 0x408d0400, 0x0248a006 }, { 0x00800001, 0x29400229, 0x00ad0480, 0x00000000 }, { 0x00800001, 0x29600229, 0x00ad04a0, 0x00000000 }, { 0x00800001, 0x29800229, 0x00ad04c0, 0x00000000 }, { 0x00800001, 0x29a00229, 0x00ad04e0, 0x00000000 }, { 0x00800001, 0x29c00229, 0x00ad0500, 0x00000000 }, { 0x00800001, 0x29e00229, 0x00ad0520, 0x00000000 }, { 0x00800001, 0x2a000229, 0x00ad0540, 0x00000000 }, { 0x00800001, 0x2a200229, 0x00ad0560, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10a80, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10aa0, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10ac0, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10ae0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10b00, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10b20, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10b40, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10b60, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10b80, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10ba0, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10bc0, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10be0, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c00, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10c20, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00800040, 0x274045ad, 0x00b10a60, 0x00b20740 }, { 0x00800040, 0x276045ad, 0x00b10b60, 0x00b20760 }, { 0x00800040, 0x278045ad, 0x00b10a80, 0x00b20780 }, { 0x00800040, 0x27a045ad, 0x00b10b80, 0x00b207a0 }, { 0x00800040, 0x27c045ad, 0x00b10aa0, 0x00b207c0 }, { 0x00800040, 0x27e045ad, 0x00b10ba0, 0x00b207e0 }, { 0x00800040, 0x280045ad, 0x00b10ac0, 0x00b20800 }, { 0x00800040, 0x282045ad, 0x00b10bc0, 0x00b20820 }, { 0x00800040, 0x284045ad, 0x00b10ae0, 0x00b20840 }, { 0x00800040, 0x286045ad, 0x00b10be0, 0x00b20860 }, { 0x00800040, 0x288045ad, 0x00b10b00, 0x00b20880 }, { 0x00800040, 0x28a045ad, 0x00b10c00, 0x00b208a0 }, { 0x00800040, 0x28c045ad, 0x00b10b20, 0x00b208c0 }, { 0x00800040, 0x28e045ad, 0x00b10c20, 0x00b208e0 }, { 0x00800040, 0x290045ad, 0x00b10b40, 0x00b20900 }, { 0x00800040, 0x292045ad, 0x00b10c40, 0x00b20920 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x474001b1, 0x00b10740, 0x00000000 }, { 0x80800001, 0x476001b1, 0x00b10760, 0x00000000 }, { 0x80800001, 0x478001b1, 0x00b10780, 0x00000000 }, { 0x80800001, 0x47a001b1, 0x00b107a0, 0x00000000 }, { 0x80800001, 0x47c001b1, 0x00b107c0, 0x00000000 }, { 0x80800001, 0x47e001b1, 0x00b107e0, 0x00000000 }, { 0x80800001, 0x480001b1, 0x00b10800, 0x00000000 }, { 0x80800001, 0x482001b1, 0x00b10820, 0x00000000 }, { 0x80800001, 0x484001b1, 0x00b10840, 0x00000000 }, { 0x80800001, 0x486001b1, 0x00b10860, 0x00000000 }, { 0x80800001, 0x488001b1, 0x00b10880, 0x00000000 }, { 0x80800001, 0x48a001b1, 0x00b108a0, 0x00000000 }, { 0x80800001, 0x48c001b1, 0x00b108c0, 0x00000000 }, { 0x80800001, 0x48e001b1, 0x00b108e0, 0x00000000 }, { 0x80800001, 0x490001b1, 0x00b10900, 0x00000000 }, { 0x80800001, 0x492001b1, 0x00b10920, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20740, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20760, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20780, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b207a0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b207c0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b207e0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20800, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20820, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20840, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20860, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20880, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b208a0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b208c0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b208e0, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20900, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20920, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x12082000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01c21, 0x004503e0, 0x00000001 }, { 0x00800040, 0x294025ad, 0x00b10c60, 0x00b10940 }, { 0x00800040, 0x296025ad, 0x00b10c80, 0x00b10960 }, { 0x00800040, 0x298025ad, 0x00b10ca0, 0x00b10980 }, { 0x00800040, 0x29a025ad, 0x00b10cc0, 0x00b109a0 }, { 0x80800001, 0x494001b1, 0x00b10940, 0x00000000 }, { 0x80800001, 0x496001b1, 0x00b10960, 0x00000000 }, { 0x80800001, 0x498001b1, 0x00b10980, 0x00000000 }, { 0x80800001, 0x49a001b1, 0x00b109a0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20940, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20960, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20980, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b209a0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082001 }, { 0x00800040, 0x29c025a9, 0x00b10ce0, 0x00b109c0 }, { 0x00800040, 0x29e025a9, 0x00b10d00, 0x00b109e0 }, { 0x00800040, 0x2a0025a9, 0x00b10d20, 0x00b10a00 }, { 0x00800040, 0x2a2025a9, 0x00b10d40, 0x00b10a20 }, { 0x80800001, 0x49c001b1, 0x00b109c0, 0x00000000 }, { 0x80800001, 0x49e001b1, 0x00b109e0, 0x00000000 }, { 0x80800001, 0x4a0001b1, 0x00b10a00, 0x00000000 }, { 0x80800001, 0x4a2001b1, 0x00b10a20, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b209c0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b209e0, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a00, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20a20, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_intra.g4a000066400000000000000000000176171231401140700230270ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT tab g31: read and write message descriptor g32~g55:DCT data g58~g81:reference data g82: thread payload g83~g106:IDCT data */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; //shl (1) g31.4<1>UD g31.4<1,1,1>UD 1UD {align1}; include(`iq_intra.g4i') //defined for idct define(`ROW_SHIFT', `11UD') define(`ROW_ADD', `0x400UD') define(`COL_SHIFT', `20UD') define(`COL_ADD', `0x80000UD') mov (1) a0.0<1>UD 0x06F006E0UD {align1}; //0x06F006E0UD+0x00200020UD=0x07100700UD (g56.0 and g56.16) //Y0 mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; add (8) g83.0<1>W g32.0<16,8,2>W 128UW {align1}; add (8) g84.0<1>W g33.0<16,8,2>W 128UW {align1}; add (8) g85.0<1>W g34.0<16,8,2>W 128UW {align1}; add (8) g86.0<1>W g35.0<16,8,2>W 128UW {align1}; add (8) g87.0<1>W g36.0<16,8,2>W 128UW {align1}; add (8) g88.0<1>W g37.0<16,8,2>W 128UW {align1}; add (8) g89.0<1>W g38.0<16,8,2>W 128UW {align1}; add (8) g90.0<1>W g39.0<16,8,2>W 128UW {align1}; //Y1 mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; add (8) g83.16<1>W g32.0<16,8,2>W 128UW {align1}; add (8) g84.16<1>W g33.0<16,8,2>W 128UW {align1}; add (8) g85.16<1>W g34.0<16,8,2>W 128UW {align1}; add (8) g86.16<1>W g35.0<16,8,2>W 128UW {align1}; add (8) g87.16<1>W g36.0<16,8,2>W 128UW {align1}; add (8) g88.16<1>W g37.0<16,8,2>W 128UW {align1}; add (8) g89.16<1>W g38.0<16,8,2>W 128UW {align1}; add (8) g90.16<1>W g39.0<16,8,2>W 128UW {align1}; //Y2 mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; add (8) g91.0<1>W g32.0<16,8,2>W 128UW {align1}; add (8) g92.0<1>W g33.0<16,8,2>W 128UW {align1}; add (8) g93.0<1>W g34.0<16,8,2>W 128UW {align1}; add (8) g94.0<1>W g35.0<16,8,2>W 128UW {align1}; add (8) g95.0<1>W g36.0<16,8,2>W 128UW {align1}; add (8) g96.0<1>W g37.0<16,8,2>W 128UW {align1}; add (8) g97.0<1>W g38.0<16,8,2>W 128UW {align1}; add (8) g98.0<1>W g39.0<16,8,2>W 128UW {align1}; //Y3 mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; add (8) g91.16<1>W g32.0<16,8,2>W 128UW {align1}; add (8) g92.16<1>W g33.0<16,8,2>W 128UW {align1}; add (8) g93.16<1>W g34.0<16,8,2>W 128UW {align1}; add (8) g94.16<1>W g35.0<16,8,2>W 128UW {align1}; add (8) g95.16<1>W g36.0<16,8,2>W 128UW {align1}; add (8) g96.16<1>W g37.0<16,8,2>W 128UW {align1}; add (8) g97.16<1>W g38.0<16,8,2>W 128UW {align1}; add (8) g98.16<1>W g39.0<16,8,2>W 128UW {align1}; //U mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; add (16) g99.0<1>W g32.0<16,8,2>W 128UW {align1}; add (16) g100.0<1>W g34.0<16,8,2>W 128UW {align1}; add (16) g101.0<1>W g36.0<16,8,2>W 128UW {align1}; add (16) g102.0<1>W g38.0<16,8,2>W 128UW {align1}; //V mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; add (16) g103.0<1>W g32.0<16,8,2>W 128UW {align1}; add (16) g104.0<1>W g34.0<16,8,2>W 128UW {align1}; add (16) g105.0<1>W g36.0<16,8,2>W 128UW {align1}; add (16) g106.0<1>W g38.0<16,8,2>W 128UW {align1}; //send msg mov (1) g31.8<1>UD 0x00F000FUD {align1}; mov.sat (16) g83.0<2>UB g83.0<16,16,1>W {align1}; mov.sat (16) g84.0<2>UB g84.0<16,16,1>W {align1}; mov.sat (16) g85.0<2>UB g85.0<16,16,1>W {align1}; mov.sat (16) g86.0<2>UB g86.0<16,16,1>W {align1}; mov.sat (16) g87.0<2>UB g87.0<16,16,1>W {align1}; mov.sat (16) g88.0<2>UB g88.0<16,16,1>W {align1}; mov.sat (16) g89.0<2>UB g89.0<16,16,1>W {align1}; mov.sat (16) g90.0<2>UB g90.0<16,16,1>W {align1}; mov.sat (16) g91.0<2>UB g91.0<16,16,1>W {align1}; mov.sat (16) g92.0<2>UB g92.0<16,16,1>W {align1}; mov.sat (16) g93.0<2>UB g93.0<16,16,1>W {align1}; mov.sat (16) g94.0<2>UB g94.0<16,16,1>W {align1}; mov.sat (16) g95.0<2>UB g95.0<16,16,1>W {align1}; mov.sat (16) g96.0<2>UB g96.0<16,16,1>W {align1}; mov.sat (16) g97.0<2>UB g97.0<16,16,1>W {align1}; mov.sat (16) g98.0<2>UB g98.0<16,16,1>W {align1}; and.nz (1) null g82.2<1,1,1>UW 0x20UW{align1}; (f0) jmpi field_dct; mov (16) m1.0<1>UB g83.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g84.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g85.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g86.0<16,16,2>UB {align1}; mov (16) m3.0<1>UB g87.0<16,16,2>UB {align1}; mov (16) m3.16<1>UB g88.0<16,16,2>UB {align1}; mov (16) m4.0<1>UB g89.0<16,16,2>UB {align1}; mov (16) m4.16<1>UB g90.0<16,16,2>UB {align1}; mov (16) m5.0<1>UB g91.0<16,16,2>UB {align1}; mov (16) m5.16<1>UB g92.0<16,16,2>UB {align1}; mov (16) m6.0<1>UB g93.0<16,16,2>UB {align1}; mov (16) m6.16<1>UB g94.0<16,16,2>UB {align1}; mov (16) m7.0<1>UB g95.0<16,16,2>UB {align1}; mov (16) m7.16<1>UB g96.0<16,16,2>UB {align1}; mov (16) m8.0<1>UB g97.0<16,16,2>UB {align1}; mov (16) m8.16<1>UB g98.0<16,16,2>UB {align1}; jmpi write_back; field_dct: mov (16) m1.0<1>UB g83.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g91.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g84.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g92.0<16,16,2>UB {align1}; mov (16) m3.0<1>UB g85.0<16,16,2>UB {align1}; mov (16) m3.16<1>UB g93.0<16,16,2>UB {align1}; mov (16) m4.0<1>UB g86.0<16,16,2>UB {align1}; mov (16) m4.16<1>UB g94.0<16,16,2>UB {align1}; mov (16) m5.0<1>UB g87.0<16,16,2>UB {align1}; mov (16) m5.16<1>UB g95.0<16,16,2>UB {align1}; mov (16) m6.0<1>UB g88.0<16,16,2>UB {align1}; mov (16) m6.16<1>UB g96.0<16,16,2>UB {align1}; mov (16) m7.0<1>UB g89.0<16,16,2>UB {align1}; mov (16) m7.16<1>UB g97.0<16,16,2>UB {align1}; mov (16) m8.0<1>UB g90.0<16,16,2>UB {align1}; mov (16) m8.16<1>UB g98.0<16,16,2>UB {align1}; write_back: send (16) 0 acc0<1>UW g31<8,8,1>UW write(0,0,2,0) mlen 9 rlen 0 {align1}; //U mov (1) g31.8<1>UD 0x0070007UD { align1 }; shr (2) g31.0<1>UD g82.12<2,2,1>UW 1D {align1}; mov.sat (16) g99.0<2>UB g99.0<16,16,1>W {align1}; mov.sat (16) g100.0<2>UB g100.0<16,16,1>W {align1}; mov.sat (16) g101.0<2>UB g101.0<16,16,1>W {align1}; mov.sat (16) g102.0<2>UB g102.0<16,16,1>W {align1}; mov (16) m1.0<1>UB g99.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g100.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g101.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g102.0<16,16,2>UB {align1}; send (16) 0 acc0<1>UW g31<8,8,1>UW write(1, 0, 2, 0) mlen 3 rlen 0 { align1 }; //V mov.sat (16) g103.0<2>UB g103.0<16,16,1>W {align1}; mov.sat (16) g104.0<2>UB g104.0<16,16,1>W {align1}; mov.sat (16) g105.0<2>UB g105.0<16,16,1>W {align1}; mov.sat (16) g106.0<2>UB g106.0<16,16,1>W {align1}; mov (16) m1.0<1>UB g103.0<16,16,2>UB {align1}; mov (16) m1.16<1>UB g104.0<16,16,2>UB {align1}; mov (16) m2.0<1>UB g105.0<16,16,2>UB {align1}; mov (16) m2.16<1>UB g106.0<16,16,2>UB {align1}; send (16) 0 acc0<1>UW g31<8,8,1>UW write(2, 0, 2, 0) mlen 3 rlen 0 { align1 }; OUT: send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; include(`do_iq_intra.g4i') include(`idct.g4i') intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_intra.g4b000066400000000000000000000414771231401140700230310ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000005, 0x2da02d29, 0x00210a48, 0x001f001f }, { 0x00000005, 0x2da42d29, 0x00210a48, 0x60006000 }, { 0x00000008, 0x2da42d29, 0x00210da4, 0x000d000d }, { 0x00000001, 0x2da60169, 0x00000000, 0x00080008 }, { 0x00000008, 0x2da42529, 0x00210da6, 0x00210da4 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00090009 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00110011 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00190019 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xffe7ffe7 }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00030003 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x00400040 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000009 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xfff7fff7 }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00010001 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x000a000a }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000005 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xffefffef }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00020002 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x001c001c }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000001 }, { 0x00000009, 0x2da00d29, 0x00210da0, 0x00000001 }, { 0x00000001, 0x2dc00129, 0x00210da0, 0x00000000 }, { 0x00800001, 0x2e000229, 0x00b10020, 0x00000000 }, { 0x00800001, 0x2e200229, 0x00b10030, 0x00000000 }, { 0x00800001, 0x2e400229, 0x00b10040, 0x00000000 }, { 0x00800001, 0x2e600229, 0x00b10050, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x03f003e0 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000a1 }, { 0x00800001, 0x270001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x272001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x274001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x276001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000009b }, { 0x00800001, 0x278001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x27a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x27c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x27e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000095 }, { 0x00800001, 0x280001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x282001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x284001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x286001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000008f }, { 0x00800001, 0x288001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x28a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x28c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x28e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000089 }, { 0x00800001, 0x290001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x292001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x294001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x296001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000083 }, { 0x00800001, 0x298001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x29a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x29c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x29e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x06f006e0 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000008f }, { 0x00600040, 0x2a602dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2a802dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2aa02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2ac02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2ae02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2b002dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2b202dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2b402dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000085 }, { 0x00600040, 0x2a702dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2a902dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2ab02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2ad02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2af02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2b102dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2b302dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2b502dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000007b }, { 0x00600040, 0x2b602dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2b802dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2ba02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2bc02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2be02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2c002dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2c202dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2c402dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000071 }, { 0x00600040, 0x2b702dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2b902dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2bb02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2bd02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2bf02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2c102dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2c302dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2c502dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000067 }, { 0x00800040, 0x2c602dad, 0x00ae0400, 0x00800080 }, { 0x00800040, 0x2c802dad, 0x00ae0440, 0x00800080 }, { 0x00800040, 0x2ca02dad, 0x00ae0480, 0x00800080 }, { 0x00800040, 0x2cc02dad, 0x00ae04c0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000061 }, { 0x00800040, 0x2ce02dad, 0x00ae0400, 0x00800080 }, { 0x00800040, 0x2d002dad, 0x00ae0440, 0x00800080 }, { 0x00800040, 0x2d202dad, 0x00ae0480, 0x00800080 }, { 0x00800040, 0x2d402dad, 0x00ae04c0, 0x00800080 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x4a6001b1, 0x00b10a60, 0x00000000 }, { 0x80800001, 0x4a8001b1, 0x00b10a80, 0x00000000 }, { 0x80800001, 0x4aa001b1, 0x00b10aa0, 0x00000000 }, { 0x80800001, 0x4ac001b1, 0x00b10ac0, 0x00000000 }, { 0x80800001, 0x4ae001b1, 0x00b10ae0, 0x00000000 }, { 0x80800001, 0x4b0001b1, 0x00b10b00, 0x00000000 }, { 0x80800001, 0x4b2001b1, 0x00b10b20, 0x00000000 }, { 0x80800001, 0x4b4001b1, 0x00b10b40, 0x00000000 }, { 0x80800001, 0x4b6001b1, 0x00b10b60, 0x00000000 }, { 0x80800001, 0x4b8001b1, 0x00b10b80, 0x00000000 }, { 0x80800001, 0x4ba001b1, 0x00b10ba0, 0x00000000 }, { 0x80800001, 0x4bc001b1, 0x00b10bc0, 0x00000000 }, { 0x80800001, 0x4be001b1, 0x00b10be0, 0x00000000 }, { 0x80800001, 0x4c0001b1, 0x00b10c00, 0x00000000 }, { 0x80800001, 0x4c2001b1, 0x00b10c20, 0x00000000 }, { 0x80800001, 0x4c4001b1, 0x00b10c40, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x00800001, 0x20200232, 0x00b20a60, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20a80, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20aa0, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20ac0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b20ae0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b20b00, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20b20, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20b40, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20b60, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20b80, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20ba0, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b20bc0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b20be0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b20c00, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20c20, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20c40, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00800001, 0x20200232, 0x00b20a60, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20b60, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a80, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20b80, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b20aa0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b20ba0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20ac0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20bc0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20ae0, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20be0, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20b00, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b20c00, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b20b20, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b20c20, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20b40, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20c40, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05902000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01d21, 0x00450a4c, 0x00000001 }, { 0x80800001, 0x4c6001b1, 0x00b10c60, 0x00000000 }, { 0x80800001, 0x4c8001b1, 0x00b10c80, 0x00000000 }, { 0x80800001, 0x4ca001b1, 0x00b10ca0, 0x00000000 }, { 0x80800001, 0x4cc001b1, 0x00b10cc0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20c60, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20c80, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20ca0, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20cc0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302001 }, { 0x80800001, 0x4ce001b1, 0x00b10ce0, 0x00000000 }, { 0x80800001, 0x4d0001b1, 0x00b10d00, 0x00000000 }, { 0x80800001, 0x4d2001b1, 0x00b10d20, 0x00000000 }, { 0x80800001, 0x4d4001b1, 0x00b10d40, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20ce0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20d00, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20d20, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20d40, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d03e0, 0x05302002 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00000001, 0x2de001ad, 0x00218000, 0x00000000 }, { 0x00802041, 0x2e8025a5, 0x008d8000, 0x008d0e00 }, { 0x00802041, 0x2e8024a5, 0x008d0e80, 0x008c0da0 }, { 0x0080200c, 0x2e802ca5, 0x008d0e80, 0x00040004 }, { 0x00000041, 0x2e8025a5, 0x00210de0, 0x00210da4 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2ec025a5, 0x008d8000, 0x008d0e20 }, { 0x00802041, 0x2ec024a5, 0x008d0ec0, 0x008c0da0 }, { 0x0080200c, 0x2ec02ca5, 0x008d0ec0, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2f0025a5, 0x008d8000, 0x008d0e40 }, { 0x00802041, 0x2f0024a5, 0x008d0f00, 0x008c0da0 }, { 0x0080200c, 0x2f002ca5, 0x008d0f00, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2f4025a5, 0x008d8000, 0x008d0e60 }, { 0x00802041, 0x2f4024a5, 0x008d0f40, 0x008c0da0 }, { 0x0080200c, 0x2f402ca5, 0x008d0f40, 0x00040004 }, { 0x00000040, 0x34000c20, 0x00210fa0, 0x00000020 }, { 0x00000001, 0x2fc00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00802040, 0x24000ca5, 0x008d0400, 0x00000400 }, { 0x00802040, 0x24400ca5, 0x008d0440, 0x00000400 }, { 0x00802040, 0x24800ca5, 0x008d0480, 0x00000400 }, { 0x00802040, 0x24c00ca5, 0x008d04c0, 0x00000400 }, { 0x00802008, 0x24000ca5, 0x008d0400, 0x0000000b }, { 0x00802008, 0x24400ca5, 0x008d0440, 0x0000000b }, { 0x00802008, 0x24800ca5, 0x008d0480, 0x0000000b }, { 0x00802008, 0x24c00ca5, 0x008d04c0, 0x0000000b }, { 0x00800001, 0x2dc001ad, 0x00ae0400, 0x00000000 }, { 0x00800001, 0x2de001ad, 0x00ae0440, 0x00000000 }, { 0x00800001, 0x2e0001ad, 0x00ae0480, 0x00000000 }, { 0x00800001, 0x2e2001ad, 0x00ae04c0, 0x00000000 }, { 0x00000001, 0x2a000001, 0x00210200, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x0db00da0 }, { 0x00000001, 0x2fc00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00802040, 0x24000ca5, 0x008d0400, 0x00080000 }, { 0x00802040, 0x24400ca5, 0x008d0440, 0x00080000 }, { 0x00802040, 0x24800ca5, 0x008d0480, 0x00080000 }, { 0x00802040, 0x24c00ca5, 0x008d04c0, 0x00080000 }, { 0x00802008, 0x24000ca5, 0x008d0400, 0x00000014 }, { 0x00802008, 0x24400ca5, 0x008d0440, 0x00000014 }, { 0x00802008, 0x24800ca5, 0x008d0480, 0x00000014 }, { 0x00802008, 0x24c00ca5, 0x008d04c0, 0x00000014 }, { 0x00000001, 0x22000020, 0x00210a00, 0x00000000 }, { 0x00000040, 0x34000c20, 0x00210fa0, 0x00000020 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x240014a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x242014a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x244014a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x246014a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x248014a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24a014a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24c014a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24e014a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x240814a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x242814a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x244814a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x246814a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x248814a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24a814a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24c814a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24e814a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x241014a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x243014a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x245014a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x247014a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x249014a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24b014a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24d014a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24f014a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x241814a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x243814a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x245814a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x247814a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x249814a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24b814a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24d814a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24f814a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x34000c20, 0x00210fc0, 0x00000020 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/frame_intra.g4b.gen5000066400000000000000000000414771231401140700236660ustar00rootroot00000000000000 { 0x00600001, 0x2a400021, 0x008d03e0, 0x00000000 }, { 0x00200001, 0x23e00121, 0x00450a4c, 0x00000000 }, { 0x00000005, 0x2da02d29, 0x00210a48, 0x001f001f }, { 0x00000005, 0x2da42d29, 0x00210a48, 0x60006000 }, { 0x00000008, 0x2da42d29, 0x00210da4, 0x000d000d }, { 0x00000001, 0x2da60169, 0x00000000, 0x00080008 }, { 0x00000008, 0x2da42529, 0x00210da6, 0x00210da4 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000024 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00090009 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00110011 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00190019 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xffe7ffe7 }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00030003 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x00400040 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xfff7fff7 }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00010001 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x000a000a }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xffefffef }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00020002 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x001c001c }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00000009, 0x2da00d29, 0x00210da0, 0x00000001 }, { 0x00000001, 0x2dc00129, 0x00210da0, 0x00000000 }, { 0x00800001, 0x2e000229, 0x00b10020, 0x00000000 }, { 0x00800001, 0x2e200229, 0x00b10030, 0x00000000 }, { 0x00800001, 0x2e400229, 0x00b10040, 0x00000000 }, { 0x00800001, 0x2e600229, 0x00b10050, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x03f003e0 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000142 }, { 0x00800001, 0x270001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x272001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x274001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x276001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000136 }, { 0x00800001, 0x278001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x27a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x27c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x27e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000012a }, { 0x00800001, 0x280001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x282001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x284001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x286001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000011e }, { 0x00800001, 0x288001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x28a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x28c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x28e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000112 }, { 0x00800001, 0x290001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x292001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x294001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x296001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000106 }, { 0x00800001, 0x298001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x29a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x29c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x29e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x06f006e0 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000011e }, { 0x00600040, 0x2a602dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2a802dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2aa02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2ac02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2ae02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2b002dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2b202dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2b402dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000010a }, { 0x00600040, 0x2a702dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2a902dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2ab02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2ad02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2af02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2b102dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2b302dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2b502dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000f6 }, { 0x00600040, 0x2b602dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2b802dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2ba02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2bc02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2be02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2c002dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2c202dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2c402dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000e2 }, { 0x00600040, 0x2b702dad, 0x00ae0400, 0x00800080 }, { 0x00600040, 0x2b902dad, 0x00ae0420, 0x00800080 }, { 0x00600040, 0x2bb02dad, 0x00ae0440, 0x00800080 }, { 0x00600040, 0x2bd02dad, 0x00ae0460, 0x00800080 }, { 0x00600040, 0x2bf02dad, 0x00ae0480, 0x00800080 }, { 0x00600040, 0x2c102dad, 0x00ae04a0, 0x00800080 }, { 0x00600040, 0x2c302dad, 0x00ae04c0, 0x00800080 }, { 0x00600040, 0x2c502dad, 0x00ae04e0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000ce }, { 0x00800040, 0x2c602dad, 0x00ae0400, 0x00800080 }, { 0x00800040, 0x2c802dad, 0x00ae0440, 0x00800080 }, { 0x00800040, 0x2ca02dad, 0x00ae0480, 0x00800080 }, { 0x00800040, 0x2cc02dad, 0x00ae04c0, 0x00800080 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000c2 }, { 0x00800040, 0x2ce02dad, 0x00ae0400, 0x00800080 }, { 0x00800040, 0x2d002dad, 0x00ae0440, 0x00800080 }, { 0x00800040, 0x2d202dad, 0x00ae0480, 0x00800080 }, { 0x00800040, 0x2d402dad, 0x00ae04c0, 0x00800080 }, { 0x00000001, 0x23e80061, 0x00000000, 0x000f000f }, { 0x80800001, 0x4a6001b1, 0x00b10a60, 0x00000000 }, { 0x80800001, 0x4a8001b1, 0x00b10a80, 0x00000000 }, { 0x80800001, 0x4aa001b1, 0x00b10aa0, 0x00000000 }, { 0x80800001, 0x4ac001b1, 0x00b10ac0, 0x00000000 }, { 0x80800001, 0x4ae001b1, 0x00b10ae0, 0x00000000 }, { 0x80800001, 0x4b0001b1, 0x00b10b00, 0x00000000 }, { 0x80800001, 0x4b2001b1, 0x00b10b20, 0x00000000 }, { 0x80800001, 0x4b4001b1, 0x00b10b40, 0x00000000 }, { 0x80800001, 0x4b6001b1, 0x00b10b60, 0x00000000 }, { 0x80800001, 0x4b8001b1, 0x00b10b80, 0x00000000 }, { 0x80800001, 0x4ba001b1, 0x00b10ba0, 0x00000000 }, { 0x80800001, 0x4bc001b1, 0x00b10bc0, 0x00000000 }, { 0x80800001, 0x4be001b1, 0x00b10be0, 0x00000000 }, { 0x80800001, 0x4c0001b1, 0x00b10c00, 0x00000000 }, { 0x80800001, 0x4c2001b1, 0x00b10c20, 0x00000000 }, { 0x80800001, 0x4c4001b1, 0x00b10c40, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a42, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00800001, 0x20200232, 0x00b20a60, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20a80, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20aa0, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20ac0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b20ae0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b20b00, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20b20, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20b40, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20b60, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20b80, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20ba0, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b20bc0, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b20be0, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b20c00, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20c20, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20c40, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00800001, 0x20200232, 0x00b20a60, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20b60, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20a80, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20b80, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b20aa0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b20ba0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00b20ac0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00b20bc0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00b20ae0, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00b20be0, 0x00000000 }, { 0x00800001, 0x20c00232, 0x00b20b00, 0x00000000 }, { 0x00800001, 0x20d00232, 0x00b20c00, 0x00000000 }, { 0x00800001, 0x20e00232, 0x00b20b20, 0x00000000 }, { 0x00800001, 0x20f00232, 0x00b20c20, 0x00000000 }, { 0x00800001, 0x21000232, 0x00b20b40, 0x00000000 }, { 0x00800001, 0x21100232, 0x00b20c40, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x12082000 }, { 0x00000001, 0x23e80061, 0x00000000, 0x00070007 }, { 0x00200008, 0x23e01d21, 0x00450a4c, 0x00000001 }, { 0x80800001, 0x4c6001b1, 0x00b10c60, 0x00000000 }, { 0x80800001, 0x4c8001b1, 0x00b10c80, 0x00000000 }, { 0x80800001, 0x4ca001b1, 0x00b10ca0, 0x00000000 }, { 0x80800001, 0x4cc001b1, 0x00b10cc0, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20c60, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20c80, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20ca0, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20cc0, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082001 }, { 0x80800001, 0x4ce001b1, 0x00b10ce0, 0x00000000 }, { 0x80800001, 0x4d0001b1, 0x00b10d00, 0x00000000 }, { 0x80800001, 0x4d2001b1, 0x00b10d20, 0x00000000 }, { 0x80800001, 0x4d4001b1, 0x00b10d40, 0x00000000 }, { 0x00800001, 0x20200232, 0x00b20ce0, 0x00000000 }, { 0x00800001, 0x20300232, 0x00b20d00, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b20d20, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b20d40, 0x00000000 }, { 0x00800031, 0x24001d28, 0x508d03e0, 0x06082002 }, { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00000001, 0x2de001ad, 0x00218000, 0x00000000 }, { 0x00802041, 0x2e8025a5, 0x008d8000, 0x008d0e00 }, { 0x00802041, 0x2e8024a5, 0x008d0e80, 0x008c0da0 }, { 0x0080200c, 0x2e802ca5, 0x008d0e80, 0x00040004 }, { 0x00000041, 0x2e8025a5, 0x00210de0, 0x00210da4 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2ec025a5, 0x008d8000, 0x008d0e20 }, { 0x00802041, 0x2ec024a5, 0x008d0ec0, 0x008c0da0 }, { 0x0080200c, 0x2ec02ca5, 0x008d0ec0, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2f0025a5, 0x008d8000, 0x008d0e40 }, { 0x00802041, 0x2f0024a5, 0x008d0f00, 0x008c0da0 }, { 0x0080200c, 0x2f002ca5, 0x008d0f00, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2f4025a5, 0x008d8000, 0x008d0e60 }, { 0x00802041, 0x2f4024a5, 0x008d0f40, 0x008c0da0 }, { 0x0080200c, 0x2f402ca5, 0x008d0f40, 0x00040004 }, { 0x00000040, 0x34000c20, 0x00210fa0, 0x00000020 }, { 0x00000001, 0x2fc00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00802040, 0x24000ca5, 0x008d0400, 0x00000400 }, { 0x00802040, 0x24400ca5, 0x008d0440, 0x00000400 }, { 0x00802040, 0x24800ca5, 0x008d0480, 0x00000400 }, { 0x00802040, 0x24c00ca5, 0x008d04c0, 0x00000400 }, { 0x00802008, 0x24000ca5, 0x008d0400, 0x0000000b }, { 0x00802008, 0x24400ca5, 0x008d0440, 0x0000000b }, { 0x00802008, 0x24800ca5, 0x008d0480, 0x0000000b }, { 0x00802008, 0x24c00ca5, 0x008d04c0, 0x0000000b }, { 0x00800001, 0x2dc001ad, 0x00ae0400, 0x00000000 }, { 0x00800001, 0x2de001ad, 0x00ae0440, 0x00000000 }, { 0x00800001, 0x2e0001ad, 0x00ae0480, 0x00000000 }, { 0x00800001, 0x2e2001ad, 0x00ae04c0, 0x00000000 }, { 0x00000001, 0x2a000001, 0x00210200, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x0db00da0 }, { 0x00000001, 0x2fc00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00802040, 0x24000ca5, 0x008d0400, 0x00080000 }, { 0x00802040, 0x24400ca5, 0x008d0440, 0x00080000 }, { 0x00802040, 0x24800ca5, 0x008d0480, 0x00080000 }, { 0x00802040, 0x24c00ca5, 0x008d04c0, 0x00080000 }, { 0x00802008, 0x24000ca5, 0x008d0400, 0x00000014 }, { 0x00802008, 0x24400ca5, 0x008d0440, 0x00000014 }, { 0x00802008, 0x24800ca5, 0x008d0480, 0x00000014 }, { 0x00802008, 0x24c00ca5, 0x008d04c0, 0x00000014 }, { 0x00000001, 0x22000020, 0x00210a00, 0x00000000 }, { 0x00000040, 0x34000c20, 0x00210fa0, 0x00000020 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x240014a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x242014a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x244014a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x246014a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x248014a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24a014a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24c014a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24e014a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x240814a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x242814a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x244814a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x246814a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x248814a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24a814a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24c814a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24e814a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x241014a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x243014a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x245014a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x247014a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x249014a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24b014a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24d014a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24f014a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x241814a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x243814a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x245814a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x247814a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x249814a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24b814a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24d814a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24f814a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x34000c20, 0x00210fc0, 0x00000020 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/idct.g4i000066400000000000000000000155541231401140700214710ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix in UB format g3~g4:non intra IQ matrix in UB format g5~g20:IDCT table g56~g79:DCT data after IQ before idct g83~g106: IDCT data after idct g82: thread payload backup g125: ip before idct */ IDCT_START: mov (1) g126.0<1>UD ip {align1}; jmpi DO_IDCT; add (16) g32<1>D g32<8,8,1>D ROW_ADD {compr}; add (16) g34<1>D g34<8,8,1>D ROW_ADD {compr}; add (16) g36<1>D g36<8,8,1>D ROW_ADD {compr}; add (16) g38<1>D g38<8,8,1>D ROW_ADD {compr}; shr (16) g32<1>D g32<8,8,1>D ROW_SHIFT {compr}; shr (16) g34<1>D g34<8,8,1>D ROW_SHIFT {compr}; shr (16) g36<1>D g36<8,8,1>D ROW_SHIFT {compr}; shr (16) g38<1>D g38<8,8,1>D ROW_SHIFT {compr}; mov (16) g110.0<1>W g32<16,8,2>W {align1}; mov (16) g111.0<1>W g34<16,8,2>W {align1}; mov (16) g112.0<1>W g36<16,8,2>W {align1}; mov (16) g113.0<1>W g38<16,8,2>W {align1}; mov (1) g80.0<1>UD a0.0<1,1,1>UD {align1}; //save a0 mov (1) a0.0<1>UD 0x0DB00DA0UD {align1}; //begin at g110.0, the output of idct_row.g4i mov (1) g126.0<1>UD ip {align1}; jmpi DO_IDCT; add (16) g32<1>D g32<8,8,1>D COL_ADD {compr}; add (16) g34<1>D g34<8,8,1>D COL_ADD {compr}; add (16) g36<1>D g36<8,8,1>D COL_ADD {compr}; add (16) g38<1>D g38<8,8,1>D COL_ADD {compr}; shr (16) g32<1>D g32<8,8,1>D COL_SHIFT {compr}; shr (16) g34<1>D g34<8,8,1>D COL_SHIFT {compr}; shr (16) g36<1>D g36<8,8,1>D COL_SHIFT {compr}; shr (16) g38<1>D g38<8,8,1>D COL_SHIFT {compr}; mov (1) a0.0<1>UD g80.0<1,1,1>UD {align1}; //restore a0 add (1) ip g125.0<1,1,1>UD 0x20UD {align1}; //jump back DO_IDCT: add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1}; //increase the address dp4 (16) g40<1>D g[a0.0]<8,8,1>W g5<8,8,1>D {align1 compr}; dp4 (16) g42<1>D g[a0.0]<8,8,1>W g7<8,8,1>D {align1 compr}; dp4 (16) g44<1>D g[a0.0]<8,8,1>W g9<8,8,1>D {align1 compr}; dp4 (16) g46<1>D g[a0.0]<8,8,1>W g11<8,8,1>D {align1 compr}; dp4 (16) g48<1>D g[a0.0]<8,8,1>W g13<8,8,1>D {align1 compr}; dp4 (16) g50<1>D g[a0.0]<8,8,1>W g15<8,8,1>D {align1 compr}; dp4 (16) g52<1>D g[a0.0]<8,8,1>W g17<8,8,1>D {align1 compr}; dp4 (16) g54<1>D g[a0.0]<8,8,1>W g19<8,8,1>D {align1 compr}; add (2) g32.0<1>D g40.0<8,1,8>D g40.16<8,1,8>D {align1}; add (2) g33.0<1>D g42.0<8,1,8>D g42.16<8,1,8>D {align1}; add (2) g34.0<1>D g44.0<8,1,8>D g44.16<8,1,8>D {align1}; add (2) g35.0<1>D g46.0<8,1,8>D g46.16<8,1,8>D {align1}; add (2) g36.0<1>D g48.0<8,1,8>D g48.16<8,1,8>D {align1}; add (2) g37.0<1>D g50.0<8,1,8>D g50.16<8,1,8>D {align1}; add (2) g38.0<1>D g52.0<8,1,8>D g52.16<8,1,8>D {align1}; add (2) g39.0<1>D g54.0<8,1,8>D g54.16<8,1,8>D {align1}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1}; dp4 (16) g40<1>D g[a0.0]<8,8,1>W g5<8,8,1>D {align1 compr}; dp4 (16) g42<1>D g[a0.0]<8,8,1>W g7<8,8,1>D {align1 compr}; dp4 (16) g44<1>D g[a0.0]<8,8,1>W g9<8,8,1>D {align1 compr}; dp4 (16) g46<1>D g[a0.0]<8,8,1>W g11<8,8,1>D {align1 compr}; dp4 (16) g48<1>D g[a0.0]<8,8,1>W g13<8,8,1>D {align1 compr}; dp4 (16) g50<1>D g[a0.0]<8,8,1>W g15<8,8,1>D {align1 compr}; dp4 (16) g52<1>D g[a0.0]<8,8,1>W g17<8,8,1>D {align1 compr}; dp4 (16) g54<1>D g[a0.0]<8,8,1>W g19<8,8,1>D {align1 compr}; add (2) g32.8<1>D g40.0<8,1,8>D g40.16<8,1,8>D {align1}; add (2) g33.8<1>D g42.0<8,1,8>D g42.16<8,1,8>D {align1}; add (2) g34.8<1>D g44.0<8,1,8>D g44.16<8,1,8>D {align1}; add (2) g35.8<1>D g46.0<8,1,8>D g46.16<8,1,8>D {align1}; add (2) g36.8<1>D g48.0<8,1,8>D g48.16<8,1,8>D {align1}; add (2) g37.8<1>D g50.0<8,1,8>D g50.16<8,1,8>D {align1}; add (2) g38.8<1>D g52.0<8,1,8>D g52.16<8,1,8>D {align1}; add (2) g39.8<1>D g54.0<8,1,8>D g54.16<8,1,8>D {align1}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1}; dp4 (16) g40<1>D g[a0.0]<8,8,1>W g5<8,8,1>D {align1 compr}; dp4 (16) g42<1>D g[a0.0]<8,8,1>W g7<8,8,1>D {align1 compr}; dp4 (16) g44<1>D g[a0.0]<8,8,1>W g9<8,8,1>D {align1 compr}; dp4 (16) g46<1>D g[a0.0]<8,8,1>W g11<8,8,1>D {align1 compr}; dp4 (16) g48<1>D g[a0.0]<8,8,1>W g13<8,8,1>D {align1 compr}; dp4 (16) g50<1>D g[a0.0]<8,8,1>W g15<8,8,1>D {align1 compr}; dp4 (16) g52<1>D g[a0.0]<8,8,1>W g17<8,8,1>D {align1 compr}; dp4 (16) g54<1>D g[a0.0]<8,8,1>W g19<8,8,1>D {align1 compr}; add (2) g32.16<1>D g40.0<8,1,8>D g40.16<8,1,8>D {align1}; add (2) g33.16<1>D g42.0<8,1,8>D g42.16<8,1,8>D {align1}; add (2) g34.16<1>D g44.0<8,1,8>D g44.16<8,1,8>D {align1}; add (2) g35.16<1>D g46.0<8,1,8>D g46.16<8,1,8>D {align1}; add (2) g36.16<1>D g48.0<8,1,8>D g48.16<8,1,8>D {align1}; add (2) g37.16<1>D g50.0<8,1,8>D g50.16<8,1,8>D {align1}; add (2) g38.16<1>D g52.0<8,1,8>D g52.16<8,1,8>D {align1}; add (2) g39.16<1>D g54.0<8,1,8>D g54.16<8,1,8>D {align1}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00200020UD {align1}; dp4 (16) g40<1>D g[a0.0]<8,8,1>W g5<8,8,1>D {align1 compr}; dp4 (16) g42<1>D g[a0.0]<8,8,1>W g7<8,8,1>D {align1 compr}; dp4 (16) g44<1>D g[a0.0]<8,8,1>W g9<8,8,1>D {align1 compr}; dp4 (16) g46<1>D g[a0.0]<8,8,1>W g11<8,8,1>D {align1 compr}; dp4 (16) g48<1>D g[a0.0]<8,8,1>W g13<8,8,1>D {align1 compr}; dp4 (16) g50<1>D g[a0.0]<8,8,1>W g15<8,8,1>D {align1 compr}; dp4 (16) g52<1>D g[a0.0]<8,8,1>W g17<8,8,1>D {align1 compr}; dp4 (16) g54<1>D g[a0.0]<8,8,1>W g19<8,8,1>D {align1 compr}; add (2) g32.24<1>D g40.0<8,1,8>D g40.16<8,1,8>D {align1}; add (2) g33.24<1>D g42.0<8,1,8>D g42.16<8,1,8>D {align1}; add (2) g34.24<1>D g44.0<8,1,8>D g44.16<8,1,8>D {align1}; add (2) g35.24<1>D g46.0<8,1,8>D g46.16<8,1,8>D {align1}; add (2) g36.24<1>D g48.0<8,1,8>D g48.16<8,1,8>D {align1}; add (2) g37.24<1>D g50.0<8,1,8>D g50.16<8,1,8>D {align1}; add (2) g38.24<1>D g52.0<8,1,8>D g52.16<8,1,8>D {align1}; add (2) g39.24<1>D g54.0<8,1,8>D g54.16<8,1,8>D {align1}; add (1) ip g126.0<1,1,1>UD 0x20UD {align1}; //jump back intel-driver-1.3.0/src/shaders/mpeg2/vld/iq_intra.g4i000066400000000000000000000112051231401140700223410ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix in UB format g3~g4:non intra IQ matrix in UB format g5~g20:IDCT table g32~g55:DCT data before IQ g56~g79:DCT data after IQ g82: thread payload backup g109: g109.0:q_scale_code, g109.4:intra_dc_mult, g110: q_scale_code g111: intra DC coefficient g112~g115: intra IQ matrix in UW format (in order to use instruction compress), copys from g1~g2 g125: ip before jump */ and (1) g109.0<1>UW g82.8<1,1,1>UW 0x1fUW {align1}; //q_scale_code and (1) g109.4<1>UW g82.8<1,1,1>UW 0x6000UW {align1}; //intra_dc_presion shr (1) g109.4<1>UW g109.4<1,1,1>UW 13UW {align1}; mov (1) g109.6<1>UW 0x8UW {align1}; shr (1) g109.4<1>UW g109.6<1,1,1>UW g109.4<1,1,1>UW {align1}; //intra_dc_mult and.z (1) null g82.8<1,1,1>UW 0x20UW {align1}; //if(q_scale_type==0) q_scale=q_scale_code*2; (f0) jmpi Q_SCALE_TYPE_0; cmp.l (1) null g109.0<1,1,1>UW 9UW {align1}; //if(q_scale_type!=0) calculate q_scale (f0) jmpi DO_IQ; cmp.l (1) null g109.0<1,1,1>UW 17UW {align1}; (f0) jmpi RANG_9_16; cmp.l (1) null g109.0<1,1,1>UW 25UW {align1}; (f0) jmpi RANG_17_24; RANG_25_31: add (1) g109.0<1>UW g109.0<1,1,1>UW -25W {align1}; shl (1) g109.0<1>UW g109.0<1,1,1>UW 3UW {align1}; add (1) g109.0<1>UW g109.0<1,1,1>UW 64UW {align1}; jmpi DO_IQ; RANG_9_16: add (1) g109.0<1>UW g109.0<1,1,1>UW -9W {align1}; shl (1) g109.0<1>UW g109.0<1,1,1>UW 1UW {align1}; add (1) g109.0<1>UW g109.0<1,1,1>UW 10UW {align1}; jmpi DO_IQ; RANG_17_24: add (1) g109.0<1>UW g109.0<1,1,1>UW -17W {align1}; shl (1) g109.0<1>UW g109.0<1,1,1>UW 2UW {align1}; add (1) g109.0<1>UW g109.0<1,1,1>UW 28UW {align1}; jmpi DO_IQ; Q_SCALE_TYPE_0: shl (1) g109.0<1>UW g109.0<1,1,1>UW 1UD {align1}; DO_IQ: mov (1) g110.0<1>UW g109.0<1,1,1>UW {align1}; mov (16) g112.0<1>UW g1.0<16,16,1>UB {align1}; mov (16) g113.0<1>UW g1.16<16,16,1>UB {align1}; mov (16) g114.0<1>UW g2.0<16,16,1>UB {align1}; mov (16) g115.0<1>UW g2.16<16,16,1>UB {align1}; mov (1) a0.0<1>UD 0x03F003E0UD {align1}; mov (1) g125.0<1>UD ip {align1}; jmpi DO_IQ_INTRA; mov (16) g56.0<1>W g116.0<16,8,2>W {align1}; mov (16) g57.0<1>W g118.0<16,8,2>W {align1}; mov (16) g58.0<1>W g120.0<16,8,2>W {align1}; mov (16) g59.0<1>W g122.0<16,8,2>W {align1}; mov (1) g125.0<1>UD ip {align1}; jmpi DO_IQ_INTRA; mov (16) g60.0<1>W g116.0<16,8,2>W {align1}; mov (16) g61.0<1>W g118.0<16,8,2>W {align1}; mov (16) g62.0<1>W g120.0<16,8,2>W {align1}; mov (16) g63.0<1>W g122.0<16,8,2>W {align1}; mov (1) g125.0<1>UD ip {align1}; jmpi DO_IQ_INTRA; mov (16) g64.0<1>W g116.0<16,8,2>W {align1}; mov (16) g65.0<1>W g118.0<16,8,2>W {align1}; mov (16) g66.0<1>W g120.0<16,8,2>W {align1}; mov (16) g67.0<1>W g122.0<16,8,2>W {align1}; mov (1) g125.0<1>UD ip {align1}; jmpi DO_IQ_INTRA; mov (16) g68.0<1>W g116.0<16,8,2>W {align1}; mov (16) g69.0<1>W g118.0<16,8,2>W {align1}; mov (16) g70.0<1>W g120.0<16,8,2>W {align1}; mov (16) g71.0<1>W g122.0<16,8,2>W {align1}; mov (1) g125.0<1>UD ip {align1}; jmpi DO_IQ_INTRA; mov (16) g72.0<1>W g116.0<16,8,2>W {align1}; mov (16) g73.0<1>W g118.0<16,8,2>W {align1}; mov (16) g74.0<1>W g120.0<16,8,2>W {align1}; mov (16) g75.0<1>W g122.0<16,8,2>W {align1}; mov (1) g125.0<1>UD ip {align1}; jmpi DO_IQ_INTRA; mov (16) g76.0<1>W g116.0<16,8,2>W {align1}; mov (16) g77.0<1>W g118.0<16,8,2>W {align1}; mov (16) g78.0<1>W g120.0<16,8,2>W {align1}; mov (16) g79.0<1>W g122.0<16,8,2>W {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/iq_non_intra.g4i000066400000000000000000000116741231401140700232250ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix in UB format g3~g4:non intra IQ matrix in UB format g5~g20:IDCT table g32~g55:DCT data before IQ g56~g79:DCT data after IQ g82: thread payload backup g109: q_scale_code g110: q_scale_code g112~g115: non intra IQ matrix in UW format (in order to use instruction compress), copys from g3~g4 g125: ip before jump */ and (1) g109.0<1>UW g82.8<1,1,1>UW 0x1fUW {align1}; //q_scale_code and.z (1) null g82.8<1,1,1>UW 0x20UW {align1}; //if(q_scale_type==0) q_scale=q_scale_code*2; (f0) jmpi Q_SCALE_TYPE_0; cmp.l (1) null g109.0<1,1,1>UW 9UW {align1}; //if(q_scale_type!=0) calculate q_scale (f0) jmpi DO_IQ; cmp.l (1) null g109.0<1,1,1>UW 17UW {align1}; (f0) jmpi RANG_9_16; cmp.l (1) null g109.0<1,1,1>UW 25UW {align1}; (f0) jmpi RANG_17_24; RANG_25_31: add (1) g109.0<1>UW g109.0<1,1,1>UW -25W {align1}; shl (1) g109.0<1>UW g109.0<1,1,1>UW 3UW {align1}; add (1) g109.0<1>UW g109.0<1,1,1>UW 64UW {align1}; jmpi DO_IQ; RANG_9_16: add (1) g109.0<1>UW g109.0<1,1,1>UW -9W {align1}; shl (1) g109.0<1>UW g109.0<1,1,1>UW 1UW {align1}; add (1) g109.0<1>UW g109.0<1,1,1>UW 10UW {align1}; jmpi DO_IQ; RANG_17_24: add (1) g109.0<1>UW g109.0<1,1,1>UW -17W {align1}; shl (1) g109.0<1>UW g109.0<1,1,1>UW 2UW {align1}; add (1) g109.0<1>UW g109.0<1,1,1>UW 28UW {align1}; jmpi DO_IQ; Q_SCALE_TYPE_0: shl (1) g109.0<1>UW g109.0<1,1,1>UW 1UD {align1}; DO_IQ: mov (1) g110.0<1>UW g109.0<1,1,1>UW {align1}; mov (16) g112.0<1>UW g3.0<16,16,1>UB {align1}; mov (16) g113.0<1>UW g3.16<16,16,1>UB {align1}; mov (16) g114.0<1>UW g4.0<16,16,1>UB {align1}; mov (16) g115.0<1>UW g4.16<16,16,1>UB {align1}; mov (1) a0.0<1>UD 0x03F003E0UD {align1}; //Y0 iq_non_intra_y0: and.z (1) null g82.8<1,1,1>UW 0x800UW {align1}; (f0) jmpi iq_non_intra_y1; mov (1) g125.0<1>UD ip {align1}; jmpi DO_IQ_NON_INTRA; mov (16) g56.0<1>W g116.0<16,8,2>W {align1}; mov (16) g57.0<1>W g118.0<16,8,2>W {align1}; mov (16) g58.0<1>W g120.0<16,8,2>W {align1}; mov (16) g59.0<1>W g122.0<16,8,2>W {align1}; //Y1 iq_non_intra_y1: and.z (1) null g82.8<1,1,1>UW 0x400UW {align1}; (f0) jmpi iq_non_intra_y2; mov (1) g125.0<1>UD ip {align1}; jmpi DO_IQ_NON_INTRA; mov (16) g60.0<1>W g116.0<16,8,2>W {align1}; mov (16) g61.0<1>W g118.0<16,8,2>W {align1}; mov (16) g62.0<1>W g120.0<16,8,2>W {align1}; mov (16) g63.0<1>W g122.0<16,8,2>W {align1}; //Y2 iq_non_intra_y2: and.z (1) null g82.8<1,1,1>UW 0x200UW {align1}; (f0) jmpi iq_non_intra_y3; mov (1) g125.0<1>UD ip {align1}; jmpi DO_IQ_NON_INTRA; mov (16) g64.0<1>W g116.0<16,8,2>W {align1}; mov (16) g65.0<1>W g118.0<16,8,2>W {align1}; mov (16) g66.0<1>W g120.0<16,8,2>W {align1}; mov (16) g67.0<1>W g122.0<16,8,2>W {align1}; //Y3 iq_non_intra_y3: and.z (1) null g82.8<1,1,1>UW 0x100UW {align1}; (f0) jmpi iq_non_intra_u; mov (1) g125.0<1>UD ip {align1}; jmpi DO_IQ_NON_INTRA; mov (16) g68.0<1>W g116.0<16,8,2>W {align1}; mov (16) g69.0<1>W g118.0<16,8,2>W {align1}; mov (16) g70.0<1>W g120.0<16,8,2>W {align1}; mov (16) g71.0<1>W g122.0<16,8,2>W {align1}; //U iq_non_intra_u: and.z (1) null g82.8<1,1,1>UW 0x80UW {align1}; (f0) jmpi iq_non_intra_v; mov (1) g125.0<1>UD ip {align1}; jmpi DO_IQ_NON_INTRA; mov (16) g72.0<1>W g116.0<16,8,2>W {align1}; mov (16) g73.0<1>W g118.0<16,8,2>W {align1}; mov (16) g74.0<1>W g120.0<16,8,2>W {align1}; mov (16) g75.0<1>W g122.0<16,8,2>W {align1}; //V iq_non_intra_v: and.z (1) null g82.8<1,1,1>UW 0x40UW {align1}; (f0) jmpi iq_non_intra_end; mov (1) g125.0<1>UD ip {align1}; jmpi DO_IQ_NON_INTRA; mov (16) g76.0<1>W g116.0<16,8,2>W {align1}; mov (16) g77.0<1>W g118.0<16,8,2>W {align1}; mov (16) g78.0<1>W g120.0<16,8,2>W {align1}; mov (16) g79.0<1>W g122.0<16,8,2>W {align1}; iq_non_intra_end: intel-driver-1.3.0/src/shaders/mpeg2/vld/lib.g4a000066400000000000000000000144371231401140700213030ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix in UB format g3~g4:non intra IQ matrix in UB format g5~g20:IDCT table g32~g55:DCT data before IQ g56~g79:DCT data after IQ g83~g106: IDCT data after idct g82: thread payload backup g125: ip before jump */ include(`iq_non_intra.g4i') define(`ROW_SHIFT', `11UD') //define for idct define(`ROW_ADD', `0x400UD') define(`COL_SHIFT', `20UD') define(`COL_ADD', `0x80000UD') mov (1) a0.0<1>UD 0x06F006E0UD {align1};//0x06F006E0UD+0x00200020UD=0x07100700UD (g56.0 and g56.16,the start of DCT data) //Y0 and.nz (1) null g82.8<1,1,1>UW 0x800UW {align1}; (f0) jmpi do_idct_y0; mov (8) g83.0<1>UW 0UW {align1}; mov (8) g84.0<1>UW 0UW {align1}; mov (8) g85.0<1>UW 0UW {align1}; mov (8) g86.0<1>UW 0UW {align1}; mov (8) g87.0<1>UW 0UW {align1}; mov (8) g88.0<1>UW 0UW {align1}; mov (8) g89.0<1>UW 0UW {align1}; mov (8) g90.0<1>UW 0UW {align1}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00800080UD {align1}; jmpi block_y1; do_idct_y0: mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; mov (8) g83.0<1>W g32.0<16,8,2>W {align1}; mov (8) g84.0<1>W g33.0<16,8,2>W {align1}; mov (8) g85.0<1>W g34.0<16,8,2>W {align1}; mov (8) g86.0<1>W g35.0<16,8,2>W {align1}; mov (8) g87.0<1>W g36.0<16,8,2>W {align1}; mov (8) g88.0<1>W g37.0<16,8,2>W {align1}; mov (8) g89.0<1>W g38.0<16,8,2>W {align1}; mov (8) g90.0<1>W g39.0<16,8,2>W {align1}; //Y1 block_y1: and.nz (1) null g82.8<1,1,1>UW 0x400UW {align1}; (f0) jmpi do_idct_y1; mov (8) g83.16<1>UW 0UW {align1}; mov (8) g84.16<1>UW 0UW {align1}; mov (8) g85.16<1>UW 0UW {align1}; mov (8) g86.16<1>UW 0UW {align1}; mov (8) g87.16<1>UW 0UW {align1}; mov (8) g88.16<1>UW 0UW {align1}; mov (8) g89.16<1>UW 0UW {align1}; mov (8) g90.16<1>UW 0UW {align1}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00800080UD {align1}; jmpi block_y2; do_idct_y1: mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; mov (8) g83.16<1>W g32.0<16,8,2>W {align1}; mov (8) g84.16<1>W g33.0<16,8,2>W {align1}; mov (8) g85.16<1>W g34.0<16,8,2>W {align1}; mov (8) g86.16<1>W g35.0<16,8,2>W {align1}; mov (8) g87.16<1>W g36.0<16,8,2>W {align1}; mov (8) g88.16<1>W g37.0<16,8,2>W {align1}; mov (8) g89.16<1>W g38.0<16,8,2>W {align1}; mov (8) g90.16<1>W g39.0<16,8,2>W {align1}; //Y2 block_y2: and.nz (1) null g82.8<1,1,1>UW 0x200UW {align1}; (f0) jmpi do_idct_y2; mov (8) g91.0<1>UW 0UW {align1}; mov (8) g92.0<1>UW 0UW {align1}; mov (8) g93.0<1>UW 0UW {align1}; mov (8) g94.0<1>UW 0UW {align1}; mov (8) g95.0<1>UW 0UW {align1}; mov (8) g96.0<1>UW 0UW {align1}; mov (8) g97.0<1>UW 0UW {align1}; mov (8) g98.0<1>UW 0UW {align1}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00800080UD {align1}; jmpi block_y3; do_idct_y2: mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; mov (8) g91.0<1>W g32.0<16,8,2>W {align1}; mov (8) g92.0<1>W g33.0<16,8,2>W {align1}; mov (8) g93.0<1>W g34.0<16,8,2>W {align1}; mov (8) g94.0<1>W g35.0<16,8,2>W {align1}; mov (8) g95.0<1>W g36.0<16,8,2>W {align1}; mov (8) g96.0<1>W g37.0<16,8,2>W {align1}; mov (8) g97.0<1>W g38.0<16,8,2>W {align1}; mov (8) g98.0<1>W g39.0<16,8,2>W {align1}; //Y3 block_y3: and.nz (1) null g82.8<1,1,1>UW 0x100UW {align1}; (f0) jmpi do_idct_y3; mov (8) g91.16<1>UW 0UW {align1}; mov (8) g92.16<1>UW 0UW {align1}; mov (8) g93.16<1>UW 0UW {align1}; mov (8) g94.16<1>UW 0UW {align1}; mov (8) g95.16<1>UW 0UW {align1}; mov (8) g96.16<1>UW 0UW {align1}; mov (8) g97.16<1>UW 0UW {align1}; mov (8) g98.16<1>UW 0UW {align1}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00800080UD {align1}; jmpi block_u; do_idct_y3: mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; mov (8) g91.16<1>W g32.0<16,8,2>W {align1}; mov (8) g92.16<1>W g33.0<16,8,2>W {align1}; mov (8) g93.16<1>W g34.0<16,8,2>W {align1}; mov (8) g94.16<1>W g35.0<16,8,2>W {align1}; mov (8) g95.16<1>W g36.0<16,8,2>W {align1}; mov (8) g96.16<1>W g37.0<16,8,2>W {align1}; mov (8) g97.16<1>W g38.0<16,8,2>W {align1}; mov (8) g98.16<1>W g39.0<16,8,2>W {align1}; //U block_u: and.nz (1) null g82.8<1,1,1>UW 0x80UW {align1}; (f0) jmpi do_idct_u; mov (16) g99.0<1>UW 0UW {align1}; mov (16) g100.0<1>UW 0UW {align1}; mov (16) g101.0<1>UW 0UW {align1}; mov (16) g102.0<1>UW 0UW {align1}; add (1) a0.0<1>UD a0.0<1,1,1>UD 0x00800080UD {align1}; jmpi block_v; do_idct_u: mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; mov (16) g99.0<1>W g32.0<16,8,2>W {align1}; mov (16) g100.0<1>W g34.0<16,8,2>W {align1}; mov (16) g101.0<1>W g36.0<16,8,2>W {align1}; mov (16) g102.0<1>W g38.0<16,8,2>W {align1}; //V block_v: and.nz (1) null g82.8<1,1,1>UW 0x40UW {align1}; (f0) jmpi do_idct_v; mov (16) g103.0<1>UW 0UW {align1}; mov (16) g104.0<1>UW 0UW {align1}; mov (16) g105.0<1>UW 0UW {align1}; mov (16) g106.0<1>UW 0UW {align1}; jmpi block_end; do_idct_v: mov (1) g125.0<1>UD ip {align1}; jmpi IDCT_START; mov (16) g103.0<1>W g32.0<16,8,2>W {align1}; mov (16) g104.0<1>W g34.0<16,8,2>W {align1}; mov (16) g105.0<1>W g36.0<16,8,2>W {align1}; mov (16) g106.0<1>W g38.0<16,8,2>W {align1}; block_end: add (1) ip g126.8<1,1,1>UD 0x20UD {align1}; //jump back include(`do_iq_non_intra.g4i') include(`idct.g4i') intel-driver-1.3.0/src/shaders/mpeg2/vld/lib.g4b000066400000000000000000000407651231401140700213070ustar00rootroot00000000000000 { 0x00000005, 0x2da02d29, 0x00210a48, 0x001f001f }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00090009 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000011 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00110011 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00190019 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xffe7ffe7 }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00030003 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x00400040 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000009 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xfff7fff7 }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00010001 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x000a000a }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000005 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xffefffef }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00020002 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x001c001c }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000001 }, { 0x00000009, 0x2da00d29, 0x00210da0, 0x00000001 }, { 0x00000001, 0x2dc00129, 0x00210da0, 0x00000000 }, { 0x00800001, 0x2e000229, 0x00b10060, 0x00000000 }, { 0x00800001, 0x2e200229, 0x00b10070, 0x00000000 }, { 0x00800001, 0x2e400229, 0x00b10080, 0x00000000 }, { 0x00800001, 0x2e600229, 0x00b10090, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x03f003e0 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x08000800 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000a1 }, { 0x00800001, 0x270001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x272001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x274001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x276001ad, 0x00ae0f40, 0x00000000 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x04000400 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000099 }, { 0x00800001, 0x278001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x27a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x27c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x27e001ad, 0x00ae0f40, 0x00000000 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x02000200 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000091 }, { 0x00800001, 0x280001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x282001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x284001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x286001ad, 0x00ae0f40, 0x00000000 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x01000100 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000089 }, { 0x00800001, 0x288001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x28a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x28c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x28e001ad, 0x00ae0f40, 0x00000000 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x00800080 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000081 }, { 0x00800001, 0x290001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x292001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x294001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x296001ad, 0x00ae0f40, 0x00000000 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x00400040 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000079 }, { 0x00800001, 0x298001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x29a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x29c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x29e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x06f006e0 }, { 0x02000005, 0x20002d3c, 0x00210a48, 0x08000800 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00600001, 0x2a600169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a800169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2aa00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ac00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ae00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b000169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b200169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b400169, 0x00000000, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00800080 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000077 }, { 0x00600001, 0x2a6001ad, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x2a8001ad, 0x00ae0420, 0x00000000 }, { 0x00600001, 0x2aa001ad, 0x00ae0440, 0x00000000 }, { 0x00600001, 0x2ac001ad, 0x00ae0460, 0x00000000 }, { 0x00600001, 0x2ae001ad, 0x00ae0480, 0x00000000 }, { 0x00600001, 0x2b0001ad, 0x00ae04a0, 0x00000000 }, { 0x00600001, 0x2b2001ad, 0x00ae04c0, 0x00000000 }, { 0x00600001, 0x2b4001ad, 0x00ae04e0, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a48, 0x04000400 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00600001, 0x2a700169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a900169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ab00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ad00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2af00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b100169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b300169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b500169, 0x00000000, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00800080 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000061 }, { 0x00600001, 0x2a7001ad, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x2a9001ad, 0x00ae0420, 0x00000000 }, { 0x00600001, 0x2ab001ad, 0x00ae0440, 0x00000000 }, { 0x00600001, 0x2ad001ad, 0x00ae0460, 0x00000000 }, { 0x00600001, 0x2af001ad, 0x00ae0480, 0x00000000 }, { 0x00600001, 0x2b1001ad, 0x00ae04a0, 0x00000000 }, { 0x00600001, 0x2b3001ad, 0x00ae04c0, 0x00000000 }, { 0x00600001, 0x2b5001ad, 0x00ae04e0, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a48, 0x02000200 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00600001, 0x2b600169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b800169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ba00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2bc00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2be00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2c000169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2c200169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2c400169, 0x00000000, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00800080 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004b }, { 0x00600001, 0x2b6001ad, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x2b8001ad, 0x00ae0420, 0x00000000 }, { 0x00600001, 0x2ba001ad, 0x00ae0440, 0x00000000 }, { 0x00600001, 0x2bc001ad, 0x00ae0460, 0x00000000 }, { 0x00600001, 0x2be001ad, 0x00ae0480, 0x00000000 }, { 0x00600001, 0x2c0001ad, 0x00ae04a0, 0x00000000 }, { 0x00600001, 0x2c2001ad, 0x00ae04c0, 0x00000000 }, { 0x00600001, 0x2c4001ad, 0x00ae04e0, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a48, 0x01000100 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00600001, 0x2b700169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b900169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2bb00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2bd00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2bf00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2c100169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2c300169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2c500169, 0x00000000, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00800080 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000035 }, { 0x00600001, 0x2b7001ad, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x2b9001ad, 0x00ae0420, 0x00000000 }, { 0x00600001, 0x2bb001ad, 0x00ae0440, 0x00000000 }, { 0x00600001, 0x2bd001ad, 0x00ae0460, 0x00000000 }, { 0x00600001, 0x2bf001ad, 0x00ae0480, 0x00000000 }, { 0x00600001, 0x2c1001ad, 0x00ae04a0, 0x00000000 }, { 0x00600001, 0x2c3001ad, 0x00ae04c0, 0x00000000 }, { 0x00600001, 0x2c5001ad, 0x00ae04e0, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a48, 0x00800080 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00800001, 0x2c600169, 0x00000000, 0x00000000 }, { 0x00800001, 0x2c800169, 0x00000000, 0x00000000 }, { 0x00800001, 0x2ca00169, 0x00000000, 0x00000000 }, { 0x00800001, 0x2cc00169, 0x00000000, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00800080 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000023 }, { 0x00800001, 0x2c6001ad, 0x00ae0400, 0x00000000 }, { 0x00800001, 0x2c8001ad, 0x00ae0440, 0x00000000 }, { 0x00800001, 0x2ca001ad, 0x00ae0480, 0x00000000 }, { 0x00800001, 0x2cc001ad, 0x00ae04c0, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a48, 0x00400040 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000005 }, { 0x00800001, 0x2ce00169, 0x00000000, 0x00000000 }, { 0x00800001, 0x2d000169, 0x00000000, 0x00000000 }, { 0x00800001, 0x2d200169, 0x00000000, 0x00000000 }, { 0x00800001, 0x2d400169, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00800001, 0x2ce001ad, 0x00ae0400, 0x00000000 }, { 0x00800001, 0x2d0001ad, 0x00ae0440, 0x00000000 }, { 0x00800001, 0x2d2001ad, 0x00ae0480, 0x00000000 }, { 0x00800001, 0x2d4001ad, 0x00ae04c0, 0x00000000 }, { 0x00000040, 0x34000c20, 0x00210fc8, 0x00000020 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2e8025a5, 0x008d8000, 0x008d0e00 }, { 0x00802041, 0x2e8024a5, 0x008d0e80, 0x008c0da0 }, { 0x0080200c, 0x2e802ca5, 0x008d0e80, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2ec025a5, 0x008d8000, 0x008d0e20 }, { 0x00802041, 0x2ec024a5, 0x008d0ec0, 0x008c0da0 }, { 0x0080200c, 0x2ec02ca5, 0x008d0ec0, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2f0025a5, 0x008d8000, 0x008d0e40 }, { 0x00802041, 0x2f0024a5, 0x008d0f00, 0x008c0da0 }, { 0x0080200c, 0x2f002ca5, 0x008d0f00, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2f4025a5, 0x008d8000, 0x008d0e60 }, { 0x00802041, 0x2f4024a5, 0x008d0f40, 0x008c0da0 }, { 0x0080200c, 0x2f402ca5, 0x008d0f40, 0x00040004 }, { 0x00000040, 0x34000c20, 0x00210fa0, 0x00000020 }, { 0x00000001, 0x2fc00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00802040, 0x24000ca5, 0x008d0400, 0x00000400 }, { 0x00802040, 0x24400ca5, 0x008d0440, 0x00000400 }, { 0x00802040, 0x24800ca5, 0x008d0480, 0x00000400 }, { 0x00802040, 0x24c00ca5, 0x008d04c0, 0x00000400 }, { 0x00802008, 0x24000ca5, 0x008d0400, 0x0000000b }, { 0x00802008, 0x24400ca5, 0x008d0440, 0x0000000b }, { 0x00802008, 0x24800ca5, 0x008d0480, 0x0000000b }, { 0x00802008, 0x24c00ca5, 0x008d04c0, 0x0000000b }, { 0x00800001, 0x2dc001ad, 0x00ae0400, 0x00000000 }, { 0x00800001, 0x2de001ad, 0x00ae0440, 0x00000000 }, { 0x00800001, 0x2e0001ad, 0x00ae0480, 0x00000000 }, { 0x00800001, 0x2e2001ad, 0x00ae04c0, 0x00000000 }, { 0x00000001, 0x2a000001, 0x00210200, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x0db00da0 }, { 0x00000001, 0x2fc00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00802040, 0x24000ca5, 0x008d0400, 0x00080000 }, { 0x00802040, 0x24400ca5, 0x008d0440, 0x00080000 }, { 0x00802040, 0x24800ca5, 0x008d0480, 0x00080000 }, { 0x00802040, 0x24c00ca5, 0x008d04c0, 0x00080000 }, { 0x00802008, 0x24000ca5, 0x008d0400, 0x00000014 }, { 0x00802008, 0x24400ca5, 0x008d0440, 0x00000014 }, { 0x00802008, 0x24800ca5, 0x008d0480, 0x00000014 }, { 0x00802008, 0x24c00ca5, 0x008d04c0, 0x00000014 }, { 0x00000001, 0x22000020, 0x00210a00, 0x00000000 }, { 0x00000040, 0x34000c20, 0x00210fa0, 0x00000020 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x240014a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x242014a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x244014a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x246014a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x248014a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24a014a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24c014a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24e014a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x240814a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x242814a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x244814a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x246814a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x248814a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24a814a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24c814a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24e814a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x241014a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x243014a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x245014a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x247014a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x249014a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24b014a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24d014a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24f014a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x241814a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x243814a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x245814a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x247814a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x249814a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24b814a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24d814a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24f814a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x34000c20, 0x00210fc0, 0x00000020 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/lib.g4b.gen5000066400000000000000000000407651231401140700221440ustar00rootroot00000000000000 { 0x00000005, 0x2da02d29, 0x00210a48, 0x001f001f }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x00200020 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000024 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00090009 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00110011 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x05000010, 0x20002d3c, 0x00210da0, 0x00190019 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xffe7ffe7 }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00030003 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x00400040 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xfff7fff7 }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00010001 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x000a000a }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00000040, 0x2da03d29, 0x00210da0, 0xffefffef }, { 0x00000009, 0x2da02d29, 0x00210da0, 0x00020002 }, { 0x00000040, 0x2da02d29, 0x00210da0, 0x001c001c }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00000009, 0x2da00d29, 0x00210da0, 0x00000001 }, { 0x00000001, 0x2dc00129, 0x00210da0, 0x00000000 }, { 0x00800001, 0x2e000229, 0x00b10060, 0x00000000 }, { 0x00800001, 0x2e200229, 0x00b10070, 0x00000000 }, { 0x00800001, 0x2e400229, 0x00b10080, 0x00000000 }, { 0x00800001, 0x2e600229, 0x00b10090, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x03f003e0 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x08000800 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000142 }, { 0x00800001, 0x270001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x272001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x274001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x276001ad, 0x00ae0f40, 0x00000000 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x04000400 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000132 }, { 0x00800001, 0x278001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x27a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x27c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x27e001ad, 0x00ae0f40, 0x00000000 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x02000200 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000122 }, { 0x00800001, 0x280001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x282001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x284001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x286001ad, 0x00ae0f40, 0x00000000 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x01000100 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000112 }, { 0x00800001, 0x288001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x28a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x28c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x28e001ad, 0x00ae0f40, 0x00000000 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x00800080 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000102 }, { 0x00800001, 0x290001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x292001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x294001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x296001ad, 0x00ae0f40, 0x00000000 }, { 0x01000005, 0x20002d3c, 0x00210a48, 0x00400040 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000f2 }, { 0x00800001, 0x298001ad, 0x00ae0e80, 0x00000000 }, { 0x00800001, 0x29a001ad, 0x00ae0ec0, 0x00000000 }, { 0x00800001, 0x29c001ad, 0x00ae0f00, 0x00000000 }, { 0x00800001, 0x29e001ad, 0x00ae0f40, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x06f006e0 }, { 0x02000005, 0x20002d3c, 0x00210a48, 0x08000800 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00600001, 0x2a600169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a800169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2aa00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ac00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ae00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b000169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b200169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b400169, 0x00000000, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00800080 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000ee }, { 0x00600001, 0x2a6001ad, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x2a8001ad, 0x00ae0420, 0x00000000 }, { 0x00600001, 0x2aa001ad, 0x00ae0440, 0x00000000 }, { 0x00600001, 0x2ac001ad, 0x00ae0460, 0x00000000 }, { 0x00600001, 0x2ae001ad, 0x00ae0480, 0x00000000 }, { 0x00600001, 0x2b0001ad, 0x00ae04a0, 0x00000000 }, { 0x00600001, 0x2b2001ad, 0x00ae04c0, 0x00000000 }, { 0x00600001, 0x2b4001ad, 0x00ae04e0, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a48, 0x04000400 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00600001, 0x2a700169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a900169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ab00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ad00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2af00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b100169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b300169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b500169, 0x00000000, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00800080 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000c2 }, { 0x00600001, 0x2a7001ad, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x2a9001ad, 0x00ae0420, 0x00000000 }, { 0x00600001, 0x2ab001ad, 0x00ae0440, 0x00000000 }, { 0x00600001, 0x2ad001ad, 0x00ae0460, 0x00000000 }, { 0x00600001, 0x2af001ad, 0x00ae0480, 0x00000000 }, { 0x00600001, 0x2b1001ad, 0x00ae04a0, 0x00000000 }, { 0x00600001, 0x2b3001ad, 0x00ae04c0, 0x00000000 }, { 0x00600001, 0x2b5001ad, 0x00ae04e0, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a48, 0x02000200 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00600001, 0x2b600169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b800169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ba00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2bc00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2be00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2c000169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2c200169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2c400169, 0x00000000, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00800080 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000096 }, { 0x00600001, 0x2b6001ad, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x2b8001ad, 0x00ae0420, 0x00000000 }, { 0x00600001, 0x2ba001ad, 0x00ae0440, 0x00000000 }, { 0x00600001, 0x2bc001ad, 0x00ae0460, 0x00000000 }, { 0x00600001, 0x2be001ad, 0x00ae0480, 0x00000000 }, { 0x00600001, 0x2c0001ad, 0x00ae04a0, 0x00000000 }, { 0x00600001, 0x2c2001ad, 0x00ae04c0, 0x00000000 }, { 0x00600001, 0x2c4001ad, 0x00ae04e0, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a48, 0x01000100 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00600001, 0x2b700169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b900169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2bb00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2bd00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2bf00169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2c100169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2c300169, 0x00000000, 0x00000000 }, { 0x00600001, 0x2c500169, 0x00000000, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00800080 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000006a }, { 0x00600001, 0x2b7001ad, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x2b9001ad, 0x00ae0420, 0x00000000 }, { 0x00600001, 0x2bb001ad, 0x00ae0440, 0x00000000 }, { 0x00600001, 0x2bd001ad, 0x00ae0460, 0x00000000 }, { 0x00600001, 0x2bf001ad, 0x00ae0480, 0x00000000 }, { 0x00600001, 0x2c1001ad, 0x00ae04a0, 0x00000000 }, { 0x00600001, 0x2c3001ad, 0x00ae04c0, 0x00000000 }, { 0x00600001, 0x2c5001ad, 0x00ae04e0, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a48, 0x00800080 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x00800001, 0x2c600169, 0x00000000, 0x00000000 }, { 0x00800001, 0x2c800169, 0x00000000, 0x00000000 }, { 0x00800001, 0x2ca00169, 0x00000000, 0x00000000 }, { 0x00800001, 0x2cc00169, 0x00000000, 0x00000000 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00800080 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000046 }, { 0x00800001, 0x2c6001ad, 0x00ae0400, 0x00000000 }, { 0x00800001, 0x2c8001ad, 0x00ae0440, 0x00000000 }, { 0x00800001, 0x2ca001ad, 0x00ae0480, 0x00000000 }, { 0x00800001, 0x2cc001ad, 0x00ae04c0, 0x00000000 }, { 0x02000005, 0x20002d3c, 0x00210a48, 0x00400040 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00800001, 0x2ce00169, 0x00000000, 0x00000000 }, { 0x00800001, 0x2d000169, 0x00000000, 0x00000000 }, { 0x00800001, 0x2d200169, 0x00000000, 0x00000000 }, { 0x00800001, 0x2d400169, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x00000001, 0x2fa00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x00800001, 0x2ce001ad, 0x00ae0400, 0x00000000 }, { 0x00800001, 0x2d0001ad, 0x00ae0440, 0x00000000 }, { 0x00800001, 0x2d2001ad, 0x00ae0480, 0x00000000 }, { 0x00800001, 0x2d4001ad, 0x00ae04c0, 0x00000000 }, { 0x00000040, 0x34000c20, 0x00210fc8, 0x00000020 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2e8025a5, 0x008d8000, 0x008d0e00 }, { 0x00802041, 0x2e8024a5, 0x008d0e80, 0x008c0da0 }, { 0x0080200c, 0x2e802ca5, 0x008d0e80, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2ec025a5, 0x008d8000, 0x008d0e20 }, { 0x00802041, 0x2ec024a5, 0x008d0ec0, 0x008c0da0 }, { 0x0080200c, 0x2ec02ca5, 0x008d0ec0, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2f0025a5, 0x008d8000, 0x008d0e40 }, { 0x00802041, 0x2f0024a5, 0x008d0f00, 0x008c0da0 }, { 0x0080200c, 0x2f002ca5, 0x008d0f00, 0x00040004 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802041, 0x2f4025a5, 0x008d8000, 0x008d0e60 }, { 0x00802041, 0x2f4024a5, 0x008d0f40, 0x008c0da0 }, { 0x0080200c, 0x2f402ca5, 0x008d0f40, 0x00040004 }, { 0x00000040, 0x34000c20, 0x00210fa0, 0x00000020 }, { 0x00000001, 0x2fc00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00802040, 0x24000ca5, 0x008d0400, 0x00000400 }, { 0x00802040, 0x24400ca5, 0x008d0440, 0x00000400 }, { 0x00802040, 0x24800ca5, 0x008d0480, 0x00000400 }, { 0x00802040, 0x24c00ca5, 0x008d04c0, 0x00000400 }, { 0x00802008, 0x24000ca5, 0x008d0400, 0x0000000b }, { 0x00802008, 0x24400ca5, 0x008d0440, 0x0000000b }, { 0x00802008, 0x24800ca5, 0x008d0480, 0x0000000b }, { 0x00802008, 0x24c00ca5, 0x008d04c0, 0x0000000b }, { 0x00800001, 0x2dc001ad, 0x00ae0400, 0x00000000 }, { 0x00800001, 0x2de001ad, 0x00ae0440, 0x00000000 }, { 0x00800001, 0x2e0001ad, 0x00ae0480, 0x00000000 }, { 0x00800001, 0x2e2001ad, 0x00ae04c0, 0x00000000 }, { 0x00000001, 0x2a000001, 0x00210200, 0x00000000 }, { 0x00000001, 0x22000060, 0x00000000, 0x0db00da0 }, { 0x00000001, 0x2fc00001, 0x00001400, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00802040, 0x24000ca5, 0x008d0400, 0x00080000 }, { 0x00802040, 0x24400ca5, 0x008d0440, 0x00080000 }, { 0x00802040, 0x24800ca5, 0x008d0480, 0x00080000 }, { 0x00802040, 0x24c00ca5, 0x008d04c0, 0x00080000 }, { 0x00802008, 0x24000ca5, 0x008d0400, 0x00000014 }, { 0x00802008, 0x24400ca5, 0x008d0440, 0x00000014 }, { 0x00802008, 0x24800ca5, 0x008d0480, 0x00000014 }, { 0x00802008, 0x24c00ca5, 0x008d04c0, 0x00000014 }, { 0x00000001, 0x22000020, 0x00210a00, 0x00000000 }, { 0x00000040, 0x34000c20, 0x00210fa0, 0x00000020 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x240014a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x242014a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x244014a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x246014a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x248014a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24a014a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24c014a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24e014a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x240814a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x242814a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x244814a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x246814a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x248814a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24a814a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24c814a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24e814a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x241014a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x243014a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x245014a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x247014a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x249014a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24b014a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24d014a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24f014a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x22000c00, 0x00210200, 0x00200020 }, { 0x00802054, 0x250015a5, 0x008d8000, 0x008d00a0 }, { 0x00802054, 0x254015a5, 0x008d8000, 0x008d00e0 }, { 0x00802054, 0x258015a5, 0x008d8000, 0x008d0120 }, { 0x00802054, 0x25c015a5, 0x008d8000, 0x008d0160 }, { 0x00802054, 0x260015a5, 0x008d8000, 0x008d01a0 }, { 0x00802054, 0x264015a5, 0x008d8000, 0x008d01e0 }, { 0x00802054, 0x268015a5, 0x008d8000, 0x008d0220 }, { 0x00802054, 0x26c015a5, 0x008d8000, 0x008d0260 }, { 0x00200040, 0x241814a5, 0x00800500, 0x00800510 }, { 0x00200040, 0x243814a5, 0x00800540, 0x00800550 }, { 0x00200040, 0x245814a5, 0x00800580, 0x00800590 }, { 0x00200040, 0x247814a5, 0x008005c0, 0x008005d0 }, { 0x00200040, 0x249814a5, 0x00800600, 0x00800610 }, { 0x00200040, 0x24b814a5, 0x00800640, 0x00800650 }, { 0x00200040, 0x24d814a5, 0x00800680, 0x00800690 }, { 0x00200040, 0x24f814a5, 0x008006c0, 0x008006d0 }, { 0x00000040, 0x34000c20, 0x00210fc0, 0x00000020 }, intel-driver-1.3.0/src/shaders/mpeg2/vld/motion_field_uv.g4i000066400000000000000000000033421231401140700237200ustar00rootroot00000000000000/* * Copyright © 2008 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Zhang Hua jun * Xing Dong sheng * */ and.z (1) null mv1<1,1,1>W 1W {align1}; (f0) jmpi L1; and.z (1) null mv2<1,1,1>W 1W {align1}; (f0) jmpi L2; include(`read_field_x1y1_uv.g4i') jmpi L5; L2: include(`read_field_x1y0_uv.g4i') jmpi L5; L1: and.z (1) null mv2<1,1,1>W 1W {align1}; (f0) jmpi L4; include(`read_field_x0y1_uv.g4i') jmpi L5; L4: include(`read_field_x0y0_uv.g4i') L5: intel-driver-1.3.0/src/shaders/mpeg2/vld/motion_field_y.g4i000066400000000000000000000032001231401140700235270ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Zhang Hua jun * Xing Dong sheng * */ and.z (1) null mv1<1,1,1>W 1UW {align1}; (f0) jmpi L1; and.z (1) null mv2<1,1,1>W 1UW {align1}; (f0) jmpi L2; include(`read_field_x1y1_y.g4i') jmpi L5; L2: include(`read_field_x1y0_y.g4i') jmpi L5; L1: and.z (1) null mv2<1,1,1>W 1UW {align1}; (f0) jmpi L4; include(`read_field_x0y1_y.g4i') jmpi L5; L4: include(`read_field_x0y0_y.g4i') L5: intel-driver-1.3.0/src/shaders/mpeg2/vld/motion_frame_uv.g4i000066400000000000000000000032211231401140700237230ustar00rootroot00000000000000/* * Copyright © 2008 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Zhang Hua jun * Xing Dong sheng */ and.z (1) null mv1<1,1,1>UW 2UD {align1}; (f0) jmpi LL1; and.z (1) null mv2<1,1,1>UW 2UD {align1}; (f0) jmpi LL2; include(`read_frame_x1y1_uv.g4i') jmpi LL5; LL2: include(`read_frame_x1y0_uv.g4i') jmpi LL5; LL1: and.z (1) null mv2<1,1,1>UW 2UD {align1}; (f0) jmpi LL4; include(`read_frame_x0y1_uv.g4i') jmpi LL5; LL4: include(`read_frame_x0y0_uv.g4i') LL5: intel-driver-1.3.0/src/shaders/mpeg2/vld/motion_frame_y.g4i000066400000000000000000000034141231401140700235450ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai */ /* if (motion_vect.x & 1) { * if (motion_vect.y & 1) * half_pixel in x and y; * else * half_pixel in x; * } else { * if (motion_vect.y & 1) * half_pixel y; * else * full_pixel_read; * } */ and.z (1) null mv1<1,1,1>UW 1UD {align1}; (f0) jmpi LL1; and.z (1) null mv2<1,1,1>UW 1UD {align1}; (f0) jmpi LL2; include(`read_frame_x1y1_y.g4i') jmpi LL5; LL2: include(`read_frame_x1y0_y.g4i') jmpi LL5; LL1: and.z (1) null mv2<1,1,1>UW 1UD {align1}; (f0) jmpi LL4; include(`read_frame_x0y1_y.g4i') jmpi LL5; LL4: include(`read_frame_x0y0_y.g4i') LL5: intel-driver-1.3.0/src/shaders/mpeg2/vld/null.g4a000066400000000000000000000042531231401140700215020ustar00rootroot00000000000000/* * Copyright © 2008 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * */ mov (8) g82.0<1>UD g31.0<8,8,1>UD {align1}; mov (2) g31.0<1>UD g82.12<2,2,1>UW {align1}; define(`UV_red',`0xffffffffUD') define(`UV_white',`0x7f7f7f7fUD') define(`UV_green',`0x00000000UD') mov(2) g6.0<1>UD g82.12<2,2,1>UW {align1}; mov(1) g6.8<1>UD 0x000f000fUD { align1 }; mov(16) m1<1>UD 0xFFFFFFFFUD {align1 compr}; mov(16) m3<1>UD 0xFFFFFFFFUD {align1 compr}; mov(16) m5<1>UD 0xFFFFFFFFUD {align1 compr}; mov(16) m7<1>UD 0xFFFFFFFFUD {align1 compr}; send (16) 0 acc0<1>UW g6<8,8,1>UW write(0, 0, 2, 0) mlen 9 rlen 0 { align1 }; /*Fill U buffer & V buffer with 0x7F*/ shr (2) g6.0<1>UD g82.12<2,2,1>UW 1UW {align1}; mov(1) g6.8<1>UD 0x00070007UD { align1 }; mov (16) m1<1>UD UV_white {align1 compr}; //mov (16) m1<1>UD g1.0<16,8,1>UD {align1 compr}; send (16) 0 acc0<1>UW g6<8,8,1>UW write(2, 0, 2, 0) mlen 3 rlen 0 { align1 }; send (16) 0 acc0<1>UW g6<8,8,1>UW write(1, 0, 2, 0) mlen 3 rlen 0 { align1 }; send (16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_field_x0y0_uv.g4i000066400000000000000000000042311231401140700242040ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g115.8<1>UD 0x7000FUD {align1}; // 8*16/32=4 send (16) 0 g40.0<1>UW g115<16,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U send (16) 0 g45.0<1>UW g115<16,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V mov (16) g32.0<1>UW g40.0<16,8,1>UB {align1}; mov (16) g33.0<1>UW g41.0<16,8,1>UB {align1}; mov (16) g34.0<1>UW g42.0<16,8,1>UB {align1}; mov (16) g35.0<1>UW g43.0<16,8,1>UB {align1}; mov (16) g36.0<1>UW g45.0<16,8,1>UB {align1}; mov (16) g37.0<1>UW g46.0<16,8,1>UB {align1}; mov (16) g38.0<1>UW g47.0<16,8,1>UB {align1}; mov (16) g39.0<1>UW g48.0<16,8,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_field_x0y0_y.g4i000066400000000000000000000051431231401140700240250ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g115.8<1>UD 0x01FUD {align1}; send (16) 0 g40.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; send (16) 0 g42.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; send (16) 0 g44.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; send (16) 0 g46.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; mov (1) g115.8<1>UD 0x07001FUD {align1}; send (16) 0 g48.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; mov (16) g32.0<1>UW g40.0<16,16,1>UB {align1}; mov (16) g33.0<1>UW g42.0<16,16,1>UB {align1}; mov (16) g34.0<1>UW g44.0<16,16,1>UB {align1}; mov (16) g35.0<1>UW g46.0<16,16,1>UB {align1}; mov (16) g36.0<1>UW g48.0<16,16,1>UB {align1}; mov (16) g37.0<1>UW g50.0<16,16,1>UB {align1}; mov (16) g38.0<1>UW g52.0<16,16,1>UB {align1}; mov (16) g39.0<1>UW g54.0<16,16,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_field_x0y1_uv.g4i000066400000000000000000000024361231401140700242120ustar00rootroot00000000000000/* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g115.8<1>UD 0x07000FUD {align1}; // 8*16/32=4 send (16) 0 g40.0<1>UW g115<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U send (16) 0 g45.0<1>UW g115<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V mov (1) g115.8<1>UD 0xFUD {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 8UD {align1}; send (16) 0 g44.0<1>UW g115<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 1 {align1};//U send (16) 0 g49.0<1>UW g115<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 1 {align1};//V avg (16) g32.0<1>UW g40.0<16,8,1>UB g41.0<16,8,1>UB {align1}; avg (16) g33.0<1>UW g41.0<16,8,1>UB g42.0<16,8,1>UB {align1}; avg (16) g34.0<1>UW g42.0<16,8,1>UB g43.0<16,8,1>UB {align1}; avg (16) g35.0<1>UW g43.0<16,8,1>UB g44.0<16,8,1>UB {align1}; avg (16) g36.0<1>UW g45.0<16,8,1>UB g46.0<16,8,1>UB {align1}; avg (16) g37.0<1>UW g46.0<16,8,1>UB g47.0<16,8,1>UB {align1}; avg (16) g38.0<1>UW g47.0<16,8,1>UB g48.0<16,8,1>UB {align1}; avg (16) g39.0<1>UW g48.0<16,8,1>UB g49.0<16,8,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_field_x0y1_y.g4i000066400000000000000000000056631231401140700240350ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g115.8<1>UD 0x01FUD {align1}; send (16) 0 g40.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; send (16) 0 g42.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; send (16) 0 g44.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; send (16) 0 g46.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; mov (1) g115.8<1>UD 0x07001FUD {align1}; send (16) 0 g48.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 8UD {align1}; mov (1) g115.8<1>UD 0x1FUD {align1}; send (16) 0 g56.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; avg.sat (16) g32.0<1>UW g40.0<16,16,1>UB g42.0<16,16,1>UB {align1}; avg.sat (16) g33.0<1>UW g42.0<16,16,1>UB g44.0<16,16,1>UB {align1}; avg.sat (16) g34.0<1>UW g44.0<16,16,1>UB g46.0<16,16,1>UB {align1}; avg.sat (16) g35.0<1>UW g46.0<16,16,1>UB g48.0<16,16,1>UB {align1}; avg.sat (16) g36.0<1>UW g48.0<16,16,1>UB g50.0<16,16,1>UB {align1}; avg.sat (16) g37.0<1>UW g50.0<16,16,1>UB g52.0<16,16,1>UB {align1}; avg.sat (16) g38.0<1>UW g52.0<16,16,1>UB g54.0<16,16,1>UB {align1}; avg.sat (16) g39.0<1>UW g54.0<16,16,1>UB g56.0<16,16,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_field_x1y0_uv.g4i000066400000000000000000000020261231401140700242050ustar00rootroot00000000000000/* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g115.8<1>UD 0x07000FUD {align1}; // 8*16/32=4 send (16) 0 g40.0<1>UW g115<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U send (16) 0 g44.0<1>UW g115<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V avg (16) g32.0<1>UW g40.0<16,8,1>UB g40.1<16,8,1>UB {align1}; avg (16) g33.0<1>UW g41.0<16,8,1>UB g41.1<16,8,1>UB {align1}; avg (16) g34.0<1>UW g42.0<16,8,1>UB g42.1<16,8,1>UB {align1}; avg (16) g35.0<1>UW g43.0<16,8,1>UB g43.1<16,8,1>UB {align1}; avg (16) g36.0<1>UW g44.0<16,8,1>UB g44.1<16,8,1>UB {align1}; avg (16) g37.0<1>UW g45.0<16,8,1>UB g45.1<16,8,1>UB {align1}; avg (16) g38.0<1>UW g46.0<16,8,1>UB g46.1<16,8,1>UB {align1}; avg (16) g39.0<1>UW g47.0<16,8,1>UB g47.1<16,8,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_field_x1y0_y.g4i000066400000000000000000000054131231401140700240260ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g115.8<1>UD 0x01FUD {align1}; send (16) 0 g40.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; send (16) 0 g42.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; send (16) 0 g44.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; send (16) 0 g46.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; mov (1) g115.8<1>UD 0x07001FUD {align1}; send (16) 0 g48.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; avg.sat (16) g32.0<1>UW g40.0<16,16,1>UB g40.1<16,16,1>UB {align1}; avg.sat (16) g33.0<1>UW g42.0<16,16,1>UB g42.1<16,16,1>UB {align1}; avg.sat (16) g34.0<1>UW g44.0<16,16,1>UB g44.1<16,16,1>UB {align1}; avg.sat (16) g35.0<1>UW g46.0<16,16,1>UB g46.1<16,16,1>UB {align1}; avg.sat (16) g36.0<1>UW g48.0<16,16,1>UB g48.1<16,16,1>UB {align1}; avg.sat (16) g37.0<1>UW g50.0<16,16,1>UB g50.1<16,16,1>UB {align1}; avg.sat (16) g38.0<1>UW g52.0<16,16,1>UB g52.1<16,16,1>UB {align1}; avg.sat (16) g39.0<1>UW g54.0<16,16,1>UB g54.1<16,16,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_field_x1y1_uv.g4i000066400000000000000000000047451231401140700242200ustar00rootroot00000000000000/* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g115.8<1>UD 0x07000FUD {align1}; send (16) 0 g40.0<1>UW g115<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U send (16) 0 g45.0<1>UW g115<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V mov (1) g115.8<1>UD 0x01000FUD {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 8UD {align1}; send (16) 0 g44.0<1>UW g115<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 1 {align1};//U send (16) 0 g49.0<1>UW g115<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 1 {align1};//V //U add (16) g32.0<1>UW g40.0<16,8,1>UB g41.0<16,8,1>UB {align1}; add (16) g33.0<1>UW g41.0<16,8,1>UB g42.0<16,8,1>UB {align1}; add (16) g34.0<1>UW g42.0<16,8,1>UB g43.0<16,8,1>UB {align1}; add (16) g35.0<1>UW g43.0<16,8,1>UB g44.0<16,8,1>UB {align1}; add (16) g32.0<1>UW g32.0<16,8,1>UW g40.1<16,8,1>UB {align1}; add (16) g33.0<1>UW g33.0<16,8,1>UW g41.1<16,8,1>UB {align1}; add (16) g34.0<1>UW g34.0<16,8,1>UW g42.1<16,8,1>UB {align1}; add (16) g35.0<1>UW g35.0<16,8,1>UW g43.1<16,8,1>UB {align1}; add (16) g32.0<1>UW g32.0<16,8,1>UW g41.1<16,8,1>UB {align1}; add (16) g33.0<1>UW g33.0<16,8,1>UW g42.1<16,8,1>UB {align1}; add (16) g34.0<1>UW g34.0<16,8,1>UW g43.1<16,8,1>UB {align1}; add (16) g35.0<1>UW g35.0<16,8,1>UW g44.1<16,8,1>UB {align1}; //V add (16) g36.0<1>UW g45.0<16,8,1>UB g46.0<16,8,1>UB {align1}; add (16) g37.0<1>UW g46.0<16,8,1>UB g47.0<16,8,1>UB {align1}; add (16) g38.0<1>UW g47.0<16,8,1>UB g48.0<16,8,1>UB {align1}; add (16) g39.0<1>UW g48.0<16,8,1>UB g49.0<16,8,1>UB {align1}; add (16) g36.0<1>UW g36.0<16,8,1>UW g45.1<16,8,1>UB {align1}; add (16) g37.0<1>UW g37.0<16,8,1>UW g46.1<16,8,1>UB {align1}; add (16) g38.0<1>UW g38.0<16,8,1>UW g47.1<16,8,1>UB {align1}; add (16) g39.0<1>UW g39.0<16,8,1>UW g48.1<16,8,1>UB {align1}; add (16) g36.0<1>UW g36.0<16,8,1>UW g46.1<16,8,1>UB {align1}; add (16) g37.0<1>UW g37.0<16,8,1>UW g47.1<16,8,1>UB {align1}; add (16) g38.0<1>UW g38.0<16,8,1>UW g48.1<16,8,1>UB {align1}; add (16) g39.0<1>UW g39.0<16,8,1>UW g49.1<16,8,1>UB {align1}; shr (32) g32.0<1>UW g32.0<16,16,1>UW 2UW {align1 compr}; shr (32) g34.0<1>UW g34.0<16,16,1>UW 2UW {align1 compr}; shr (32) g36.0<1>UW g36.0<16,16,1>UW 2UW {align1 compr}; shr (32) g38.0<1>UW g38.0<16,16,1>UW 2UW {align1 compr}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_field_x1y1_y.g4i000066400000000000000000000104561231401140700240320ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g58~g81:reference data g82: thread payload backup g83~g106:IDCT data g115: message descriptor for reading reference data */ mov (1) g115.8<1>UD 0x01FUD {align1}; send (16) 0 g40.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; send (16) 0 g42.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; send (16) 0 g44.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; send (16) 0 g46.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 2UD {align1}; mov (1) g115.8<1>UD 0x07001FUD {align1}; send (16) 0 g48.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 8 {align1}; add (1) g115.4<1>UD g115.4<1,1,1>UD 8UD {align1}; mov (1) g115.8<1>UD 0x1FUD {align1}; send (16) 0 g56.0<1>UW g115<8,8,1>UW read(surface,2,0,2) mlen 1 rlen 1 {align1}; add (16) g32.0<1>UW g40.0<16,16,1>UB g42.0<16,16,1>UB {align1}; add (16) g33.0<1>UW g42.0<16,16,1>UB g44.0<16,16,1>UB {align1}; add (16) g34.0<1>UW g44.0<16,16,1>UB g46.0<16,16,1>UB {align1}; add (16) g35.0<1>UW g46.0<16,16,1>UB g48.0<16,16,1>UB {align1}; add (16) g36.0<1>UW g48.0<16,16,1>UB g50.0<16,16,1>UB {align1}; add (16) g37.0<1>UW g50.0<16,16,1>UB g52.0<16,16,1>UB {align1}; add (16) g38.0<1>UW g52.0<16,16,1>UB g54.0<16,16,1>UB {align1}; add (16) g39.0<1>UW g54.0<16,16,1>UB g56.0<16,16,1>UB {align1}; add (16) g32.0<1>UW g32.0<16,16,1>UW g40.1<16,16,1>UB {align1}; add (16) g33.0<1>UW g33.0<16,16,1>UW g42.1<16,16,1>UB {align1}; add (16) g34.0<1>UW g34.0<16,16,1>UW g44.1<16,16,1>UB {align1}; add (16) g35.0<1>UW g35.0<16,16,1>UW g46.1<16,16,1>UB {align1}; add (16) g36.0<1>UW g36.0<16,16,1>UW g48.1<16,16,1>UB {align1}; add (16) g37.0<1>UW g37.0<16,16,1>UW g50.1<16,16,1>UB {align1}; add (16) g38.0<1>UW g38.0<16,16,1>UW g52.1<16,16,1>UB {align1}; add (16) g39.0<1>UW g39.0<16,16,1>UW g54.1<16,16,1>UB {align1}; add (16) g32.0<1>UW g32.0<16,16,1>UW g42.1<16,16,1>UB {align1}; add (16) g33.0<1>UW g33.0<16,16,1>UW g44.1<16,16,1>UB {align1}; add (16) g34.0<1>UW g34.0<16,16,1>UW g46.1<16,16,1>UB {align1}; add (16) g35.0<1>UW g35.0<16,16,1>UW g48.1<16,16,1>UB {align1}; add (16) g36.0<1>UW g36.0<16,16,1>UW g50.1<16,16,1>UB {align1}; add (16) g37.0<1>UW g37.0<16,16,1>UW g52.1<16,16,1>UB {align1}; add (16) g38.0<1>UW g38.0<16,16,1>UW g54.1<16,16,1>UB {align1}; add (16) g39.0<1>UW g39.0<16,16,1>UW g56.1<16,16,1>UB {align1}; shr (16) g32.0<1>UW g32.0<16,16,1>UW 2UW {align1}; shr (16) g33.0<1>UW g33.0<16,16,1>UW 2UW {align1}; shr (16) g34.0<1>UW g34.0<16,16,1>UW 2UW {align1}; shr (16) g35.0<1>UW g35.0<16,16,1>UW 2UW {align1}; shr (16) g36.0<1>UW g36.0<16,16,1>UW 2UW {align1}; shr (16) g37.0<1>UW g37.0<16,16,1>UW 2UW {align1}; shr (16) g38.0<1>UW g38.0<16,16,1>UW 2UW {align1}; shr (16) g39.0<1>UW g39.0<16,16,1>UW 2UW {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_frame_x0y0_uv.g4i000066400000000000000000000042451231401140700242200ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g32: message descriptor for reading reference data g58~g81:reference data g82: thread payload backup g83~g106:IDCT data */ mov (1) g32.8<1>UD 0x007000fUD {align1}; send (16) 0 g36.0<1>UW g32<8,8,1>UW read(input_surface1, 2, 0, 2) mlen 1 rlen 4 {align1}; send (16) 0 g40.0<1>UW g32<8,8,1>UW read(input_surface2, 2, 0, 2) mlen 1 rlen 4 {align1}; mov (16) g74.0<1>UW g36.0<16,8,1>UB {align1}; mov (16) g75.0<1>UW g37.0<16,8,1>UB {align1}; mov (16) g76.0<1>UW g38.0<16,8,1>UB {align1}; mov (16) g77.0<1>UW g39.0<16,8,1>UB {align1}; mov (16) g78.0<1>UW g40.0<16,8,1>UB {align1}; mov (16) g79.0<1>UW g41.0<16,8,1>UB {align1}; mov (16) g80.0<1>UW g42.0<16,8,1>UB {align1}; mov (16) g81.0<1>UW g43.0<16,8,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_frame_x0y0_y.g4i000066400000000000000000000051221231401140700240310ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g32: message descriptor for reading reference data g58~g81:reference data g82: thread payload backup g83~g106:IDCT data */ mov (1) g32.8<1>UD 0x007001FUD {align1}; send (16) 0 g38.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g46.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 8 {align1}; mov (16) g58.0<1>UW g38.0<16,16,1>UB {align1}; mov (16) g59.0<1>UW g39.0<16,16,1>UB {align1}; mov (16) g60.0<1>UW g40.0<16,16,1>UB {align1}; mov (16) g61.0<1>UW g41.0<16,16,1>UB {align1}; mov (16) g62.0<1>UW g42.0<16,16,1>UB {align1}; mov (16) g63.0<1>UW g43.0<16,16,1>UB {align1}; mov (16) g64.0<1>UW g44.0<16,16,1>UB {align1}; mov (16) g65.0<1>UW g45.0<16,16,1>UB {align1}; mov (16) g66.0<1>UW g46.0<16,16,1>UB {align1}; mov (16) g67.0<1>UW g47.0<16,16,1>UB {align1}; mov (16) g68.0<1>UW g48.0<16,16,1>UB {align1}; mov (16) g69.0<1>UW g49.0<16,16,1>UB {align1}; mov (16) g70.0<1>UW g50.0<16,16,1>UB {align1}; mov (16) g71.0<1>UW g51.0<16,16,1>UB {align1}; mov (16) g72.0<1>UW g52.0<16,16,1>UB {align1}; mov (16) g73.0<1>UW g53.0<16,16,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_frame_x0y1_uv.g4i000066400000000000000000000053341231401140700242210ustar00rootroot00000000000000/* * Copyright © 2008 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDINg BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINgEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIgHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAgES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISINg FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINgS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Zhang Hua jun * Xing Dong sheng * */ mov (1) g32.8<1>UD 0x007001FUD {align1}; send (16) 0 g34.0<1>UW g32<8,8,1>UW read(input_surface1, 2, 0, 2) mlen 1 rlen 8 {align1}; //U send (16) 0 g44.0<1>UW g32<8,8,1>UW read(input_surface2, 2, 0, 2) mlen 1 rlen 8 {align1}; //V add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; mov (1) g32.8<1>UD 0x1FUD {align1}; send (16) 0 g42.0<1>UW g32<8,8,1>UW read(input_surface1, 2, 0, 2) mlen 1 rlen 1 {align1}; //U send (16) 0 g52.0<1>UW g32<8,8,1>UW read(input_surface2, 2, 0, 2) mlen 1 rlen 1 {align1}; //V //U avg (8) g74.0<1>UW g34.0<8,8,1>UB g35.0<8,8,1>UB {align1}; avg (8) g74.16<1>UW g35.0<8,8,1>UB g36.0<8,8,1>UB {align1}; avg (8) g75.0<1>UW g36.0<8,8,1>UB g37.0<8,8,1>UB {align1}; avg (8) g75.16<1>UW g37.0<8,8,1>UB g38.0<8,8,1>UB {align1}; avg (8) g76.0<1>UW g38.0<8,8,1>UB g39.0<8,8,1>UB {align1}; avg (8) g76.16<1>UW g39.0<8,8,1>UB g40.0<8,8,1>UB {align1}; avg (8) g77.0<1>UW g40.0<8,8,1>UB g41.0<8,8,1>UB {align1}; avg (8) g77.16<1>UW g41.0<8,8,1>UB g42.0<8,8,1>UB {align1}; //V avg (8) g78.0<1>UW g44.0<8,8,1>UB g45.0<8,8,1>UB {align1}; avg (8) g78.16<1>UW g45.0<8,8,1>UB g46.0<8,8,1>UB {align1}; avg (8) g79.0<1>UW g46.0<8,8,1>UB g47.0<8,8,1>UB {align1}; avg (8) g79.16<1>UW g47.0<8,8,1>UB g48.0<8,8,1>UB {align1}; avg (8) g80.0<1>UW g48.0<8,8,1>UB g49.0<8,8,1>UB {align1}; avg (8) g80.16<1>UW g49.0<8,8,1>UB g50.0<8,8,1>UB {align1}; avg (8) g81.0<1>UW g50.0<8,8,1>UB g51.0<8,8,1>UB {align1}; avg (8) g81.16<1>UW g51.0<8,8,1>UB g52.0<8,8,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_frame_x0y1_y.g4i000066400000000000000000000061171231401140700240370ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g32: message descriptor for reading reference data g58~g81:reference data g82: thread payload backup g83~g106:IDCT data */ mov (1) g32.8<1>UD 0x007001FUD {align1}; send (16) 0 g38.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g46.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; mov (1) g32.8<1>UD 0x1FUD {align1}; send (16) 0 g54.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 1 {align1}; avg.sat (16) g58.0<1>UW g38.0<16,16,1>UB g39.0<16,16,1>UB {align1}; avg.sat (16) g59.0<1>UW g39.0<16,16,1>UB g40.0<16,16,1>UB {align1}; avg.sat (16) g60.0<1>UW g40.0<16,16,1>UB g41.0<16,16,1>UB {align1}; avg.sat (16) g61.0<1>UW g41.0<16,16,1>UB g42.0<16,16,1>UB {align1}; avg.sat (16) g62.0<1>UW g42.0<16,16,1>UB g43.0<16,16,1>UB {align1}; avg.sat (16) g63.0<1>UW g43.0<16,16,1>UB g44.0<16,16,1>UB {align1}; avg.sat (16) g64.0<1>UW g44.0<16,16,1>UB g45.0<16,16,1>UB {align1}; avg.sat (16) g65.0<1>UW g45.0<16,16,1>UB g46.0<16,16,1>UB {align1}; avg.sat (16) g66.0<1>UW g46.0<16,16,1>UB g47.0<16,16,1>UB {align1}; avg.sat (16) g67.0<1>UW g47.0<16,16,1>UB g48.0<16,16,1>UB {align1}; avg.sat (16) g68.0<1>UW g48.0<16,16,1>UB g49.0<16,16,1>UB {align1}; avg.sat (16) g69.0<1>UW g49.0<16,16,1>UB g50.0<16,16,1>UB {align1}; avg.sat (16) g70.0<1>UW g50.0<16,16,1>UB g51.0<16,16,1>UB {align1}; avg.sat (16) g71.0<1>UW g51.0<16,16,1>UB g52.0<16,16,1>UB {align1}; avg.sat (16) g72.0<1>UW g52.0<16,16,1>UB g53.0<16,16,1>UB {align1}; avg.sat (16) g73.0<1>UW g53.0<16,16,1>UB g54.0<16,16,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_frame_x1y0_uv.g4i000066400000000000000000000037451231401140700242250ustar00rootroot00000000000000/* * Copyright © 2008 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Zhang Hua jun * Xing Dong sheng * */ mov (1) g32.8<1>UD 0x007000fUD {align1}; send (16) 0 g34.0<1>UW g32<8,8,1>UW read(input_surface1, 2, 0, 2) mlen 1 rlen 4 {align1}; send (16) 0 g44.0<1>UW g32<8,8,1>UW read(input_surface2, 2, 0, 2) mlen 1 rlen 4 {align1}; avg (16) g74.0<1>UW g34.0<16,8,1>UB g34.1<16,8,1>UB{align1}; avg (16) g75.0<1>UW g35.0<16,8,1>UB g35.1<16,8,1>UB{align1}; avg (16) g76.0<1>UW g36.0<16,8,1>UB g36.1<16,8,1>UB{align1}; avg (16) g77.0<1>UW g37.0<16,8,1>UB g37.1<16,8,1>UB{align1}; avg (16) g78.0<1>UW g44.0<16,8,1>UB g44.1<16,8,1>UB{align1}; avg (16) g79.0<1>UW g45.0<16,8,1>UB g45.1<16,8,1>UB{align1}; avg (16) g80.0<1>UW g46.0<16,8,1>UB g46.1<16,8,1>UB{align1}; avg (16) g81.0<1>UW g47.0<16,8,1>UB g47.1<16,8,1>UB{align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_frame_x1y0_y.g4i000066400000000000000000000056421231401140700240410ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g32: message descriptor for reading reference data g58~g81:reference data g82: thread payload backup g83~g106:IDCT data */ mov (1) g32.8<1>UD 0x007001FUD {align1}; send (16) 0 g38.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g46.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 8 {align1}; avg.sat (16) g58.0<1>UW g38.0<16,16,1>UB g38.1<16,16,1>UB {align1}; avg.sat (16) g59.0<1>UW g39.0<16,16,1>UB g39.1<16,16,1>UB {align1}; avg.sat (16) g60.0<1>UW g40.0<16,16,1>UB g40.1<16,16,1>UB {align1}; avg.sat (16) g61.0<1>UW g41.0<16,16,1>UB g41.1<16,16,1>UB {align1}; avg.sat (16) g62.0<1>UW g42.0<16,16,1>UB g42.1<16,16,1>UB {align1}; avg.sat (16) g63.0<1>UW g43.0<16,16,1>UB g43.1<16,16,1>UB {align1}; avg.sat (16) g64.0<1>UW g44.0<16,16,1>UB g44.1<16,16,1>UB {align1}; avg.sat (16) g65.0<1>UW g45.0<16,16,1>UB g45.1<16,16,1>UB {align1}; avg.sat (16) g66.0<1>UW g46.0<16,16,1>UB g46.1<16,16,1>UB {align1}; avg.sat (16) g67.0<1>UW g47.0<16,16,1>UB g47.1<16,16,1>UB {align1}; avg.sat (16) g68.0<1>UW g48.0<16,16,1>UB g48.1<16,16,1>UB {align1}; avg.sat (16) g69.0<1>UW g49.0<16,16,1>UB g49.1<16,16,1>UB {align1}; avg.sat (16) g70.0<1>UW g50.0<16,16,1>UB g50.1<16,16,1>UB {align1}; avg.sat (16) g71.0<1>UW g51.0<16,16,1>UB g51.1<16,16,1>UB {align1}; avg.sat (16) g72.0<1>UW g52.0<16,16,1>UB g52.1<16,16,1>UB {align1}; avg.sat (16) g73.0<1>UW g53.0<16,16,1>UB g53.1<16,16,1>UB {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_frame_x1y1_uv.g4i000066400000000000000000000074031231401140700242210ustar00rootroot00000000000000/* */ mov (1) g32.8<1>UD 0x007001FUD {align1}; send (16) 0 g34.0<1>UW g32<8,8,1>UW read(input_surface1, 2, 0, 2) mlen 1 rlen 8 {align1}; //U send (16) 0 g44.0<1>UW g32<8,8,1>UW read(input_surface2, 2, 0, 2) mlen 1 rlen 8 {align1}; //V add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; mov (1) g32.8<1>UD 0x1FUD {align1}; send (16) 0 g42.0<1>UW g32<8,8,1>UW read(input_surface1, 2, 0, 2) mlen 1 rlen 1 {align1}; //U send (16) 0 g52.0<1>UW g32<8,8,1>UW read(input_surface2, 2, 0, 2) mlen 1 rlen 1 {align1}; //V //U add (8) g74.0<1>UW g34.0<8,8,1>UB g34.1<8,8,1>UB {align1}; add (8) g74.16<1>UW g35.0<8,8,1>UB g35.1<8,8,1>UB {align1}; add (8) g75.0<1>UW g36.0<8,8,1>UB g36.1<8,8,1>UB {align1}; add (8) g75.16<1>UW g37.0<8,8,1>UB g37.1<8,8,1>UB {align1}; add (8) g76.0<1>UW g38.0<8,8,1>UB g38.1<8,8,1>UB {align1}; add (8) g76.16<1>UW g39.0<8,8,1>UB g39.1<8,8,1>UB {align1}; add (8) g77.0<1>UW g40.0<8,8,1>UB g40.1<8,8,1>UB {align1}; add (8) g77.16<1>UW g41.0<8,8,1>UB g41.1<8,8,1>UB {align1}; add (8) g74.0<1>UW g74.0<8,8,1>UW g35.0<8,8,1>UB {align1}; add (8) g74.16<1>UW g74.16<8,8,1>UW g36.0<8,8,1>UB {align1}; add (8) g75.0<1>UW g75.0<8,8,1>UW g37.0<8,8,1>UB {align1}; add (8) g75.16<1>UW g75.16<8,8,1>UW g38.0<8,8,1>UB {align1}; add (8) g76.0<1>UW g76.0<8,8,1>UW g39.0<8,8,1>UB {align1}; add (8) g76.16<1>UW g76.16<8,8,1>UW g40.0<8,8,1>UB {align1}; add (8) g77.0<1>UW g77.0<8,8,1>UW g41.0<8,8,1>UB {align1}; add (8) g77.16<1>UW g77.16<8,8,1>UW g42.0<8,8,1>UB {align1}; add (8) g74.0<1>UW g74.0<8,8,1>UW g35.1<8,8,1>UB {align1}; add (8) g74.16<1>UW g74.16<8,8,1>UW g36.1<8,8,1>UB {align1}; add (8) g75.0<1>UW g75.0<8,8,1>UW g37.1<8,8,1>UB {align1}; add (8) g75.16<1>UW g75.16<8,8,1>UW g38.1<8,8,1>UB {align1}; add (8) g76.0<1>UW g76.0<8,8,1>UW g39.1<8,8,1>UB {align1}; add (8) g76.16<1>UW g76.16<8,8,1>UW g40.1<8,8,1>UB {align1}; add (8) g77.0<1>UW g77.0<8,8,1>UW g41.1<8,8,1>UB {align1}; add (8) g77.16<1>UW g77.16<8,8,1>UW g42.1<8,8,1>UB {align1}; //V add (8) g78.0<1>UW g44.0<8,8,1>UB g44.1<8,8,1>UB {align1}; add (8) g78.16<1>UW g45.0<8,8,1>UB g45.1<8,8,1>UB {align1}; add (8) g79.0<1>UW g46.0<8,8,1>UB g46.1<8,8,1>UB {align1}; add (8) g79.16<1>UW g47.0<8,8,1>UB g47.1<8,8,1>UB {align1}; add (8) g80.0<1>UW g48.0<8,8,1>UB g48.1<8,8,1>UB {align1}; add (8) g80.16<1>UW g49.0<8,8,1>UB g49.1<8,8,1>UB {align1}; add (8) g81.0<1>UW g50.0<8,8,1>UB g50.1<8,8,1>UB {align1}; add (8) g81.16<1>UW g51.0<8,8,1>UB g51.1<8,8,1>UB {align1}; add (8) g78.0<1>UW g78.0<8,8,1>UW g45.0<8,8,1>UB {align1}; add (8) g78.16<1>UW g78.16<8,8,1>UW g46.0<8,8,1>UB {align1}; add (8) g79.0<1>UW g79.0<8,8,1>UW g47.0<8,8,1>UB {align1}; add (8) g79.16<1>UW g79.16<8,8,1>UW g48.0<8,8,1>UB {align1}; add (8) g80.0<1>UW g80.0<8,8,1>UW g49.0<8,8,1>UB {align1}; add (8) g80.16<1>UW g80.16<8,8,1>UW g50.0<8,8,1>UB {align1}; add (8) g81.0<1>UW g81.0<8,8,1>UW g51.0<8,8,1>UB {align1}; add (8) g81.16<1>UW g81.16<8,8,1>UW g52.0<8,8,1>UB {align1}; add (8) g78.0<1>UW g78.0<8,8,1>UW g45.1<8,8,1>UB {align1}; add (8) g78.16<1>UW g78.16<8,8,1>UW g46.1<8,8,1>UB {align1}; add (8) g79.0<1>UW g79.0<8,8,1>UW g47.1<8,8,1>UB {align1}; add (8) g79.16<1>UW g79.16<8,8,1>UW g48.1<8,8,1>UB {align1}; add (8) g80.0<1>UW g80.0<8,8,1>UW g49.1<8,8,1>UB {align1}; add (8) g80.16<1>UW g80.16<8,8,1>UW g50.1<8,8,1>UB {align1}; add (8) g81.0<1>UW g81.0<8,8,1>UW g51.1<8,8,1>UB {align1}; add (8) g81.16<1>UW g81.16<8,8,1>UW g52.1<8,8,1>UB {align1}; shr (16) g74.0<1>UW g74.0<16,16,1>UW 2UW {align1}; shr (16) g75.0<1>UW g75.0<16,16,1>UW 2UW {align1}; shr (16) g76.0<1>UW g76.0<16,16,1>UW 2UW {align1}; shr (16) g77.0<1>UW g77.0<16,16,1>UW 2UW {align1}; shr (16) g78.0<1>UW g78.0<16,16,1>UW 2UW {align1}; shr (16) g79.0<1>UW g79.0<16,16,1>UW 2UW {align1}; shr (16) g80.0<1>UW g80.0<16,16,1>UW 2UW {align1}; shr (16) g81.0<1>UW g81.0<16,16,1>UW 2UW {align1}; intel-driver-1.3.0/src/shaders/mpeg2/vld/read_frame_x1y1_y.g4i000066400000000000000000000136021231401140700240350ustar00rootroot00000000000000/* * Copyright © 2009 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Author: * Zou Nan hai * Yan Li * Liu Xi bin */ /* GRF allocation: g1~g30: constant buffer g1~g2:intra IQ matrix g3~g4:non intra IQ matrix g5~g20:IDCT table g31: thread payload g32: message descriptor for reading reference data g58~g81:reference data g82: thread payload backup g83~g106:IDCT data */ mov (1) g32.8<1>UD 0x007001FUD {align1}; send (16) 0 g38.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; send (16) 0 g46.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 8 {align1}; add (1) g32.4<1>UD g32.4<1,1,1>UD 8UD {align1}; mov (1) g32.8<1>UD 0x1FUD {align1}; send (16) 0 g54.0<1>UW g32<8,8,1>UW read(input_surface, 2, 0, 2) mlen 1 rlen 1 {align1}; add (16) g58.0<1>UW g38.0<16,16,1>UB g38.1<16,16,1>UB {align1}; add (16) g59.0<1>UW g39.0<16,16,1>UB g39.1<16,16,1>UB {align1}; add (16) g60.0<1>UW g40.0<16,16,1>UB g40.1<16,16,1>UB {align1}; add (16) g61.0<1>UW g41.0<16,16,1>UB g41.1<16,16,1>UB {align1}; add (16) g62.0<1>UW g42.0<16,16,1>UB g42.1<16,16,1>UB {align1}; add (16) g63.0<1>UW g43.0<16,16,1>UB g43.1<16,16,1>UB {align1}; add (16) g64.0<1>UW g44.0<16,16,1>UB g44.1<16,16,1>UB {align1}; add (16) g65.0<1>UW g45.0<16,16,1>UB g45.1<16,16,1>UB {align1}; add (16) g66.0<1>UW g46.0<16,16,1>UB g46.1<16,16,1>UB {align1}; add (16) g67.0<1>UW g47.0<16,16,1>UB g47.1<16,16,1>UB {align1}; add (16) g68.0<1>UW g48.0<16,16,1>UB g48.1<16,16,1>UB {align1}; add (16) g69.0<1>UW g49.0<16,16,1>UB g49.1<16,16,1>UB {align1}; add (16) g70.0<1>UW g50.0<16,16,1>UB g50.1<16,16,1>UB {align1}; add (16) g71.0<1>UW g51.0<16,16,1>UB g51.1<16,16,1>UB {align1}; add (16) g72.0<1>UW g52.0<16,16,1>UB g52.1<16,16,1>UB {align1}; add (16) g73.0<1>UW g53.0<16,16,1>UB g53.1<16,16,1>UB {align1}; add (16) g58.0<1>UW g58.0<16,16,1>UW g39.0<16,16,1>UB {align1}; add (16) g59.0<1>UW g59.0<16,16,1>UW g40.0<16,16,1>UB {align1}; add (16) g60.0<1>UW g60.0<16,16,1>UW g41.0<16,16,1>UB {align1}; add (16) g61.0<1>UW g61.0<16,16,1>UW g42.0<16,16,1>UB {align1}; add (16) g62.0<1>UW g62.0<16,16,1>UW g43.0<16,16,1>UB {align1}; add (16) g63.0<1>UW g63.0<16,16,1>UW g44.0<16,16,1>UB {align1}; add (16) g64.0<1>UW g64.0<16,16,1>UW g45.0<16,16,1>UB {align1}; add (16) g65.0<1>UW g65.0<16,16,1>UW g46.0<16,16,1>UB {align1}; add (16) g66.0<1>UW g66.0<16,16,1>UW g47.0<16,16,1>UB {align1}; add (16) g67.0<1>UW g67.0<16,16,1>UW g48.0<16,16,1>UB {align1}; add (16) g68.0<1>UW g68.0<16,16,1>UW g49.0<16,16,1>UB {align1}; add (16) g69.0<1>UW g69.0<16,16,1>UW g50.0<16,16,1>UB {align1}; add (16) g70.0<1>UW g70.0<16,16,1>UW g51.0<16,16,1>UB {align1}; add (16) g71.0<1>UW g71.0<16,16,1>UW g52.0<16,16,1>UB {align1}; add (16) g72.0<1>UW g72.0<16,16,1>UW g53.0<16,16,1>UB {align1}; add (16) g73.0<1>UW g73.0<16,16,1>UW g54.0<16,16,1>UB {align1}; add (16) g58.0<1>UW g58.0<16,16,1>UW g39.1<16,16,1>UB {align1}; add (16) g59.0<1>UW g59.0<16,16,1>UW g40.1<16,16,1>UB {align1}; add (16) g60.0<1>UW g60.0<16,16,1>UW g41.1<16,16,1>UB {align1}; add (16) g61.0<1>UW g61.0<16,16,1>UW g42.1<16,16,1>UB {align1}; add (16) g62.0<1>UW g62.0<16,16,1>UW g43.1<16,16,1>UB {align1}; add (16) g63.0<1>UW g63.0<16,16,1>UW g44.1<16,16,1>UB {align1}; add (16) g64.0<1>UW g64.0<16,16,1>UW g45.1<16,16,1>UB {align1}; add (16) g65.0<1>UW g65.0<16,16,1>UW g46.1<16,16,1>UB {align1}; add (16) g66.0<1>UW g66.0<16,16,1>UW g47.1<16,16,1>UB {align1}; add (16) g67.0<1>UW g67.0<16,16,1>UW g48.1<16,16,1>UB {align1}; add (16) g68.0<1>UW g68.0<16,16,1>UW g49.1<16,16,1>UB {align1}; add (16) g69.0<1>UW g69.0<16,16,1>UW g50.1<16,16,1>UB {align1}; add (16) g70.0<1>UW g70.0<16,16,1>UW g51.1<16,16,1>UB {align1}; add (16) g71.0<1>UW g71.0<16,16,1>UW g52.1<16,16,1>UB {align1}; add (16) g72.0<1>UW g72.0<16,16,1>UW g53.1<16,16,1>UB {align1}; add (16) g73.0<1>UW g73.0<16,16,1>UW g54.1<16,16,1>UB {align1}; shr.sat (16) g58.0<1>UW g58.0<16,16,1>UW 2UW {align1}; shr.sat (16) g59.0<1>UW g59.0<16,16,1>UW 2UW {align1}; shr.sat (16) g60.0<1>UW g60.0<16,16,1>UW 2UW {align1}; shr.sat (16) g61.0<1>UW g61.0<16,16,1>UW 2UW {align1}; shr.sat (16) g62.0<1>UW g62.0<16,16,1>UW 2UW {align1}; shr.sat (16) g63.0<1>UW g63.0<16,16,1>UW 2UW {align1}; shr.sat (16) g64.0<1>UW g64.0<16,16,1>UW 2UW {align1}; shr.sat (16) g65.0<1>UW g65.0<16,16,1>UW 2UW {align1}; shr.sat (16) g66.0<1>UW g66.0<16,16,1>UW 2UW {align1}; shr.sat (16) g67.0<1>UW g67.0<16,16,1>UW 2UW {align1}; shr.sat (16) g68.0<1>UW g68.0<16,16,1>UW 2UW {align1}; shr.sat (16) g69.0<1>UW g69.0<16,16,1>UW 2UW {align1}; shr.sat (16) g70.0<1>UW g70.0<16,16,1>UW 2UW {align1}; shr.sat (16) g71.0<1>UW g71.0<16,16,1>UW 2UW {align1}; shr.sat (16) g72.0<1>UW g72.0<16,16,1>UW 2UW {align1}; shr.sat (16) g73.0<1>UW g73.0<16,16,1>UW 2UW {align1}; intel-driver-1.3.0/src/shaders/post_processing/000077500000000000000000000000001231401140700215515ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/post_processing/Makefile.am000066400000000000000000000002071231401140700236040ustar00rootroot00000000000000SUBDIRS = gen5_6 gen7 gen75 gen8 # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/post_processing/gen5_6/000077500000000000000000000000001231401140700226345ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/000077500000000000000000000000001231401140700240645ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm000066400000000000000000000045541231401140700271070ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: AYUV_Load_16x8.asm //---------------------------------------------------------------- #include "AYUV_Load_16x8.inc" // In order to load 64x8 AYUV data (16x8 pixels), we need to divide the data // into two regions and load them separately. // // 32 byte 32 byte //|----------------|----------------| //| | | //| A | B |8 //| | | //| | | //|----------------|----------------| // Load the first 32x8 data block // Packed data block should be loaded as 32x8 pixel block add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Block origin shl (1) rMSGSRC.0<1>:d acc0:w 2:w { NoDDClr } // H. block origin need to be four times larger mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_YUV:ud { NoDDChk } // Block width and height (32x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_YUV(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_YUV+nBI_CURRENT_SRC_YUV:ud //Load the second 32x8 data block // Offset the origin X - move to next 32 colomns add (1) rMSGSRC.0<1>:d rMSGSRC.0<0;1,0>:d 32:w // Increase X origin by 8 // Size stays the same - 32x8 mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud // Copy message description to message header send (8) udSRC_YUV(8)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_YUV+nBI_CURRENT_SRC_YUV:ud // Give AYUV region addresses to address register mov (1) SRC_YUV_OFFSET<1>:ud 0x00400038*32:ud //Address registers contain starting addresses of two halves //Directly move the data to destination $for(0; r[SRC_YUV_OFFSET,%1*32+2]<8,4>:ub mov (16) uwDEST_U(%1)<1> r[SRC_YUV_OFFSET,%1*32+1]<8,4>:ub mov (16) uwDEST_V(%1)<1> r[SRC_YUV_OFFSET,%1*32+0]<8,4>:ub } intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc000066400000000000000000000030001231401140700270610ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: AYUV_Load_16x8.inc // // AYUV data are first loaded to bottom I/O REGION_2, then unpacked to planar data // and stored in top I/O REGION_1 #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 // Number of Y rows per block #define nDPR_BLOCK_SIZE_YUV nBLOCK_WIDTH_32+nBLOCK_HEIGHT_8 // Y block size 32x8 #define nDPR_MSG_SIZE_YUV nRESLEN_8 // # of MRF's to hold Y block data (8) //Temporary storage for unpacked AYUV data #define rUNPACK_TEMP REG(r,nTEMP0) .declare udUNPACK_TEMP Base=rUNPACK_TEMP ElementSize=4 SrcRegion=<8;8,1> Type=ud //1 GRF .declare ubUNPACK_TEMP Base=rUNPACK_TEMP ElementSize=1 SrcRegion=<32;32,1> Type=ub //1 GRF .declare ubBOT_Y_IO Base=REG(r,nBOT_Y) ElementSize=1 SrcRegion=REGION(32,1) Type=ub #define udSRC_YUV udBOT_Y_IO #define ubSRC_YUV ubBOT_Y_IO #define nSRC_YUV_REG nBOT_Y #define uwDEST_Y uwTOP_Y #define uwDEST_U uwTOP_U #define uwDEST_V uwTOP_V #define SRC_YUV_OFFSET a0.0 #define nSRC_REGION nREGION_1 // REGION_1 will be the source region for first kernel // End of AYUV_Load_16x8.inc intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/Expansion.inc000066400000000000000000000014211231401140700265210ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: Expansion.inc // Number of U/V rows per block definition #undef nUV_NUM_OF_ROWS #ifdef EXPAND_9x5 #define nUV_NUM_OF_ROWS 6 #else #define nUV_NUM_OF_ROWS 8 #endif // Source/destination region definitions #undef uwDEST_U #undef uwDEST_V #if (nSRC_REGION==nREGION_1) #define uwDEST_U uwTOP_U #define uwDEST_V uwTOP_V #elif (nSRC_REGION==nREGION_2) #define uwDEST_U uwBOT_U #define uwDEST_V uwBOT_V #endif // End of Expansion.inc intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/IMC3_Load_8x4.asm000066400000000000000000000037611231401140700267320ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: IMC3_Load_8x4.asm // //---------------------------------------------------------------- #define IMC3_LOAD_8x4 #include "PL3_Load.inc" // Load 16x8 planar Y ---------------------------------------------------------- add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin #if !defined(LOAD_UV_ONLY) mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_Y:ud // Block width and height (16x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_Y(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_CURRENT_SRC_Y:ud #endif // Load 8x4 planar U and V ----------------------------------------------------- asr (2) rMSGSRC.0<1>:d rMSGSRC.0<2;2,1>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // U/V block width and height (8x4) mov (8) mMSGHDRU<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_U(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_U:ud mov (8) mMSGHDRV<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_V(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_V:ud // Convert to word-aligned format ---------------------------------------------- #if !defined(LOAD_UV_ONLY) $for (nY_NUM_OF_ROWS-1; >-1; -1) { mov (16) uwDEST_Y(0,%1*16)<1> ubSRC_Y(0,%1*16) } #endif $for (nUV_NUM_OF_ROWS/2-1; >-1; -1) { mov (16) uwDEST_U(0, %1*16)<1> ubSRC_U(0, %1*16) mov (16) uwDEST_V(0, %1*16)<1> ubSRC_V(0, %1*16) } // End of IMC3_Load_8x4 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/IMC3_Load_8x5.asm000066400000000000000000000037611231401140700267330ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: IMC3_Load_8x5.asm // //---------------------------------------------------------------- #define IMC3_LOAD_8x5 #include "PL3_Load.inc" // Load 16x8 planar Y ---------------------------------------------------------- add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin #if !defined(LOAD_UV_ONLY) mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_Y:ud // Block width and height (16x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_Y(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_CURRENT_SRC_Y:ud #endif // Load 8x5 planar U and V ----------------------------------------------------- asr (2) rMSGSRC.0<1>:d rMSGSRC.0<2;2,1>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // U/V block width and height (8x5) mov (8) mMSGHDRU<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_U(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_U:ud mov (8) mMSGHDRV<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_V(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_V:ud // Convert to word-aligned format ---------------------------------------------- #if !defined(LOAD_UV_ONLY) $for (nY_NUM_OF_ROWS-1; >-1; -1) { mov (16) uwDEST_Y(0,%1*16)<1> ubSRC_Y(0,%1*16) } #endif $for (nUV_NUM_OF_ROWS/2-1; >-1; -1) { mov (16) uwDEST_U(0, %1*16)<1> ubSRC_U(0, %1*16) mov (16) uwDEST_V(0, %1*16)<1> ubSRC_V(0, %1*16) } // End of IMC3_Load_8x5 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/IMC3_Load_9x5.asm000066400000000000000000000042531231401140700267310ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: IMC3_Load_9x5.asm // //---------------------------------------------------------------- // This module loads 16x8 Y, 9x5 U and 9x5 V planar data blocks for CSC module // and stores it in byte-aligned format. //---------------------------------------------------------------- #define IMC3_LOAD_9x5 #include "PL3_Load.inc" // Load 16x8 planar Y ---------------------------------------------------------- add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin #if !defined(LOAD_UV_ONLY) mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_Y:ud // Block width and height (16x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_Y(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_CURRENT_SRC_Y:ud #endif // Load 9x5 planar U and V ----------------------------------------------------- asr (2) rMSGSRC.0<1>:d rMSGSRC.0<2;2,1>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // U/V block width and height (12x5) mov (8) mMSGHDRU<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_U(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_U:ud mov (8) mMSGHDRV<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_V(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_V:ud // Convert to word-aligned format ---------------------------------------------- #if !defined(LOAD_UV_ONLY) $for (nY_NUM_OF_ROWS-1; >-1; -1) { mov (16) uwDEST_Y(0,%1*16)<1> ubSRC_Y(0,%1*16) } #endif $for(nUV_NUM_OF_ROWS-2; >-1; -1) { mov (16) uwDEST_U(0, %1*16)<1> ubSRC_U(0, %1*16) mov (16) uwDEST_V(0, %1*16)<1> ubSRC_V(0, %1*16) } // End of IMC3_Load_9x5 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm000066400000000000000000000007641231401140700272500ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #ifdef GT // to remove error messages of un-initialized GRF .declare udGRF_space Base=r0.0 ElementSize=4 SrcRegion=REGION(8,1) Type=ud $for (7; <80; 1) { mov (8) udGRF_space(%1)<1> 0:ud } #else #endifintel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/Multiple_Loop.asm000077500000000000000000000057711231401140700273670ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ///////////////////////////////////////////////////////////////////////////////// // Multiple_Loop.asm // This lable is for satisfying component kernel build. // DL will remove this label and reference the real one in Multiple_Loop_Head.asm. #if defined(COMPONENT) VIDEO_PROCESSING_LOOP: #endif //===== Possible build flags for component kernels // 1) INC_SCALING // 2) INC_BLENDING // 3) INC_BLENDING and INC_SCALING // 4) (no flags) #define MxN_MULTIPLE_BLOCKS //------------------------------------------------------------------------------ #if defined(MxN_MULTIPLE_BLOCKS) // Do Multiple Block Processing ------------------------------------------------ // The 1st block has been processed before entering the loop // Processed all blocks? add.z.f0.0 (1) wNUM_BLKS:w wNUM_BLKS:w -1:w // Reached multi-block width? add (1) wORIX:w wORIX:w 16:w cmp.l.f0.1 (1) null:w wORIX:w wFRAME_ENDX:w // acc0.0 has wORIX #if defined(INC_SCALING) // Update SRC_VID_H_ORI for scaling mul (1) REG(r,nTEMP0):f fVIDEO_STEP_X:f 16.0:f add (1) fSRC_VID_H_ORI:f REG(r,nTEMP0):f fSRC_VID_H_ORI:f #endif #if defined(INC_BLENDING) // Update SRC_ALPHA_H_ORI for blending mul (1) REG(r,nTEMP0):f fALPHA_STEP_X:f 16.0:f add (1) fSRC_ALPHA_H_ORI:f REG(r,nTEMP0):f fSRC_ALPHA_H_ORI:f #endif (f0.0)jmpi (1) END_VIDEO_PROCESSING // All blocks are done - Exit loop // blocks in the middle of the loop (neither the first nor the last one)? // it may be on the left edge (Mx1) or not (1xN) mov (1) uwBLOCK_MASK_H<1>:uw uwBLOCK_MASK_H_MIDDLE:uw // the last block? cmp.e.f0.0 (1) null:w wNUM_BLKS:w 1:w (f0.0) mov (1) uwBLOCK_MASK_H<1>:uw uwBLOCK_MASK_H_RIGHT:uw (f0.0) mov (1) ubBLOCK_MASK_V<1>:ub ubBLOCK_MASK_V_BOTTOM:ub (f0.1)jmpi (1) VIDEO_PROCESSING_LOOP // If not the end of row, goto the beginning of the loop //If end of row, restart Horizontal offset and calculate Vertical offsets next row. mov (1) wORIX:w wCOPY_ORIX:w add (1) wORIY:w wORIY:w 8:w #if defined(INC_SCALING) // Update SRC_VID_H_ORI and SRC_VID_V_ORI for scaling mov (1) fSRC_VID_H_ORI:f fFRAME_VID_ORIX:f // Reset normalised X origin to 0 for video and alpha mul (1) REG(r,nTEMP0):f fVIDEO_STEP_Y:f 8.0:f add (1) fSRC_VID_V_ORI:f REG(r,nTEMP0):f fSRC_VID_V_ORI:f #endif #if defined(INC_BLENDING) // Update SRC_ALPHA_H_ORI and SRC_ALPHA_V_ORI for blending mov (1) fSRC_ALPHA_H_ORI:f fFRAME_ALPHA_ORIX:f // Reset normalised X origin to 0 for video and alpha mul (1) REG(r,nTEMP0):f fALPHA_STEP_Y:f 8.0:f add (1) fSRC_ALPHA_V_ORI:f REG(r,nTEMP0):f fSRC_ALPHA_V_ORI:f #endif jmpi (1) VIDEO_PROCESSING_LOOP // Continue Loop END_VIDEO_PROCESSING: nop #endif END_THREAD // End of Thread intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/Multiple_Loop_Head.asm000066400000000000000000000021051231401140700302710ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ ////////////////////////////////////////////////////////////////////////////////// // Multiple_Loop_Head.asm // This code sets up the loop control for multiple blocks per thread mul (1) wFRAME_ENDX:w ubBLK_CNT_X:ub 16:uw { NoDDClr } // Build multi-block loop counters mov (1) wNUM_BLKS:w ubNUM_BLKS:ub { NoDDClr, NoDDChk } // Copy num blocks to word variable mov (1) wCOPY_ORIX:w wORIX:w { NoDDChk } // Copy multi-block origin in pixel mov (2) fFRAME_VID_ORIX<1>:f fSRC_VID_H_ORI<4;2,2>:f // Copy src video origin for scaling, and alpha origin for blending add (1) wFRAME_ENDX:w wFRAME_ENDX:w wORIX:w // Continue building multi-block loop counters VIDEO_PROCESSING_LOOP: // Loop back entry point as the biginning of the loop for multiple blocks // Beginning of the loop intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/NV11_Load_4x8.asm000066400000000000000000000035031231401140700267160ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: NV11_Load_4x8.asm //---------------------------------------------------------------- #define NV11_LOAD_4x8 #include "PL2_Load.inc" // Load 16x8 NV11 Y ------------------------------------------------------------ add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin #if !defined(LOAD_UV_ONLY) mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_Y:ud // Y block width and height (16x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_Y(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_CURRENT_SRC_Y:ud #endif // Load 8x8 NV11 UV ---------------------------------------------------------- asr (1) rMSGSRC.0<1>:d rMSGSRC.0<0;1,0>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // U/V block width and height (8x8) mov (8) mMSGHDRU<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_U(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_UV:ud // Convert to word-aligned format ---------------------------------------------- #if !defined(LOAD_UV_ONLY) $for (nY_NUM_OF_ROWS-1; >-1; -1) { mov (16) uwDEST_Y(0,%1*16)<1> ubSRC_Y(0,%1*16) } #endif $for (nUV_NUM_OF_ROWS/4-1; >-1; -1) { mov (16) uwDEST_U(0,%1*16)<1> ubSRC_U(0,%1*32)<32;16,2> mov (16) uwDEST_V(0,%1*16)<1> ubSRC_U(0,%1*32+1)<32;16,2> } // End of NV11_Load_4x8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/NV11_Load_5x8.asm000066400000000000000000000035021231401140700267160ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: NV11_Load_5x8.asm //---------------------------------------------------------------- #define NV11_LOAD_5x8 #include "PL2_Load.inc" // Load 16x8 NV11 Y ------------------------------------------------------------ add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin #if !defined(LOAD_UV_ONLY) mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_Y:ud // Y block width and height (16x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_Y(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_CURRENT_SRC_Y:ud #endif // Load 12x8 NV11 UV --------------------------------------------------------- asr (1) rMSGSRC.0<1>:d rMSGSRC.0<0;1,0>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // U/V block width and height (12x8) mov (8) mMSGHDRU<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_U(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_UV:ud // Convert to word-aligned format ---------------------------------------------- #if !defined(LOAD_UV_ONLY) $for (nY_NUM_OF_ROWS-1; >-1; -1) { mov (16) uwDEST_Y(0,%1*16)<1> ubSRC_Y(0,%1*16) } #endif $for (nUV_NUM_OF_ROWS/2-1; >-1; -1) { mov (16) uwDEST_U(0,%1*16)<1> ubSRC_U(0,%1*32)<16;8,2> mov (16) uwDEST_V(0,%1*16)<1> ubSRC_U(0,%1*32+1)<16;8,2> } // End of NV11_Load_5x8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm000077500000000000000000000060761231401140700267320ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: NV12_Load_8x4.asm //---------------------------------------------------------------- #define NV12_LOAD_8x4 #include "PL2_Load.inc" // Load 16x8 planar Y ---------------------------------------------------------- add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin #if !defined(LOAD_UV_ONLY) mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_Y:ud // Y block width and height (16x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_Y(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_CURRENT_SRC_Y:ud #endif // Load 8x4 planar U and V ----------------------------------------------------- asr (1) rMSGSRC.1<1>:d rMSGSRC.1<0;1,0>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // U/V block width and height (16x4) mov (8) mMSGHDRU<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_U(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_UV:ud // Convert to word-aligned format ---------------------------------------------- #if defined(FIX_POINT_CONVERSION) || defined(FLOAT_POINT_CONVERSION) // load NV12 and save it as packed AYUV to dst (64x8) $for (nY_NUM_OF_ROWS-1; >-1; -1) { // #### Y mov (8) ubDEST_Y(0,%1*16*4)<4> ubSRC_Y(0,%1*16)<0;8,1> mov (8) ubDEST_Y(0,(%1*16+8)*4)<4> ubSRC_Y(0,%1*16+8)<0;8,1> // #### U/V // error from compile: "Invalid horiz size 8", so I have to repeat UV first // mov (4) ubDEST_Y(0,%1*16*4+1)<8> ubSRC_U(0,%1/2*16)<0;4,2> // mov (4) ubDEST_Y(0,%1*16*4+1+32)<8> ubSRC_U(0,%1/2*16+8)<0;4,2> // repeate U/V for each one mov (8) REG2(r,nTEMP18,0)<2>:uw uwSRC_U(0,%1/2*8)<0;8,1> mov (8) REG2(r,nTEMP18,1)<2>:uw uwSRC_U(0,%1/2*8)<0;8,1> // mov U/V to ubDEST mov (8) ubDEST_Y(0,%1*16*4+1)<4> REG2(r,nTEMP18,0)<0;8,2>:ub mov (8) ubDEST_Y(0,%1*16*4+1+32)<4> REG2(r,nTEMP18,16)<0;8,2>:ub mov (8) ubDEST_Y(0,%1*16*4+2)<4> REG2(r,nTEMP18,1)<0;8,2>:ub mov (8) ubDEST_Y(0,%1*16*4+2+32)<4> REG2(r,nTEMP18,17)<0;8,2>:ub } #else #if !defined(LOAD_UV_ONLY) $for (nY_NUM_OF_ROWS-1; >-1; -1) { mov (16) uwDEST_Y(0,%1*16)<1> ubSRC_Y(0,%1*16) } #endif $for (nUV_NUM_OF_ROWS/2-1; >-1; -1) { // why "mov (16)"? should it be 8? mov (16) uwDEST_U(0,%1*16)<1> ubSRC_U(0,%1*32)<32;16,2> mov (16) uwDEST_V(0,%1*16)<1> ubSRC_U(0,%1*32+1)<32;16,2> } #endif // End of NV12_Load_8x4 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/NV12_Load_8x5.asm000066400000000000000000000035041231401140700267210ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: NV12_Load_8x5.asm //---------------------------------------------------------------- #define NV12_LOAD_8x5 #include "PL2_Load.inc" // Load 16x8 planar Y ---------------------------------------------------------- add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin #if !defined(LOAD_UV_ONLY) mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_Y:ud // Y block width and height (16x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_Y(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_CURRENT_SRC_Y:ud #endif // Load 8x5 planar U and V ----------------------------------------------------- asr (1) rMSGSRC.1<1>:d rMSGSRC.1<0;1,0>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // U/V block width and height (16x5) mov (8) mMSGHDRU<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_U(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_UV:ud // Convert to word-aligned format ---------------------------------------------- #if !defined(LOAD_UV_ONLY) $for (nY_NUM_OF_ROWS-1; >-1; -1) { mov (16) uwDEST_Y(0,%1*16)<1> ubSRC_Y(0,%1*16) } #endif $for (nUV_NUM_OF_ROWS/2-1; >-1; -1) { mov (16) uwDEST_U(0,%1*16)<1> ubSRC_U(0,%1*32)<16;8,2> mov (16) uwDEST_V(0,%1*16)<1> ubSRC_U(0,%1*32+1)<16;8,2> } // End of NV12_Load_8x5 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/NV12_Load_9x5.asm000066400000000000000000000034761231401140700267320ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: NV12_Load_9x5.asm //---------------------------------------------------------------- #define NV12_LOAD_9x5 #include "PL2_Load.inc" // Load 16x8 planar Y ---------------------------------------------------------- add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin #if !defined(LOAD_UV_ONLY) mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_Y:ud // Y block width and height (16x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_Y(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_CURRENT_SRC_Y:ud #endif // Load 9x5 planar U and V ----------------------------------------------------- asr (1) rMSGSRC.1<1>:d rMSGSRC.1<0;1,0>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // U/V block width and height (20x5) mov (8) mMSGHDRU<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_U(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_UV:ud // Convert to word-aligned format ---------------------------------------------- #if !defined(LOAD_UV_ONLY) $for (nY_NUM_OF_ROWS-1; >-1; -1) { mov (16) uwDEST_Y(0,%1*16)<1> ubSRC_Y(0,%1*16) } #endif $for(nUV_NUM_OF_ROWS-2; >-1; -1) { mov (16) uwDEST_U(0,%1*16)<1> ubSRC_U(0,%1*32)<16;8,2> mov (16) uwDEST_V(0,%1*16)<1> ubSRC_U(0,%1*32+1)<16;8,2> } // End of NV12_Load_9x5 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/P208_Load_8x8.asm000066400000000000000000000031321231401140700266640ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: P208_Load_8x8.asm //---------------------------------------------------------------- #define P208_LOAD_8x8 #include "PL2_Load.inc" add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_Y:ud // Y Block width and height (16x8) (U/V block size is the same) // Load 16x8 P208 Y ------------------------------------------------------------ #if !defined(LOAD_UV_ONLY) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_Y(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_CURRENT_SRC_Y:ud #endif // Load 16x8 planar UV ----------------------------------------------------- mov (8) mMSGHDRU<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_U(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_UV:ud // Convert to word-aligned format ---------------------------------------------- #if !defined(LOAD_UV_ONLY) $for (0; mov (16) uwDEST_V(0,%1*16) ubSRC_U(0,%1*32+1)<32;16,2> } // End of P208_Load_8x8.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/P208_Load_9x8.asm000066400000000000000000000032671231401140700266760ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: P208_Load_9x8.asm //---------------------------------------------------------------- #define P208_LOAD_9x8 #include "PL2_Load.inc" add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin // Load 16x8 P208 Y ------------------------------------------------------------ #if !defined(LOAD_UV_ONLY) mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_Y:ud // Y block width and height (16x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_Y(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_CURRENT_SRC_Y:ud #endif // Load 16x8 planar UV ----------------------------------------------------- mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // U/V block width and height (20x8) mov (8) mMSGHDRU<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_U(0)<1> mMSGHDRU udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_UV:ud // Convert to word-aligned format ---------------------------------------------- #if !defined(LOAD_UV_ONLY) $for (0; mov (16) uwDEST_V(0,%1*16) ubSRC_U(0,%1*32+1)<32;16,2> } // End of P208_Load_9x8.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PA_Load.inc000066400000000000000000000032221231401140700260150ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PA_Load.inc // // YUV422 data are first loaded to bottom I/O REGION_2, then unpacked to planar data // and stored in top I/O REGION_1 #undef nY_NUM_OF_ROWS #undef nUV_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 // Number of Y rows per block #define nUV_NUM_OF_ROWS 8 // Number of U/V rows per block #if defined(PA_LOAD_8x8) #define nDPR_BLOCK_SIZE_YUV nBLOCK_WIDTH_32+nBLOCK_HEIGHT_8 // Y block size 32x8 #define nDPR_MSG_SIZE_YUV nRESLEN_8 // # of MRF's to hold Y block data (8) #endif #if defined(PA_LOAD_9x8) #define nDPR_BLOCK_SIZE_YUV_MAIN nBLOCK_WIDTH_32+nBLOCK_HEIGHT_8 // Main YUV block size 32x8 #define nDPR_MSG_SIZE_YUV_MAIN nRESLEN_8 // # of MRF's to hold Y block data (8) #define nDPR_BLOCK_SIZE_YUV_ADDITION nBLOCK_WIDTH_4+nBLOCK_HEIGHT_8 // Additional YUV block size 4x8 #define nDPR_MSG_SIZE_YUV_ADDITION nRESLEN_1 // # of MRF's to hold Y block data (8) #endif #define udSRC_YUV udBOT_Y_IO #define nSRC_YUV_REG nBOT_Y #define uwDEST_Y uwTOP_Y #define uwDEST_U uwTOP_U #define uwDEST_V uwTOP_V #define nSRC_REGION nREGION_1 // REGION_1 will be the source region for first kernel // End of PA_Load.inc intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PA_Load_8x8.asm000077500000000000000000000030211231401140700265330ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PA_Load_8x8.asm //---------------------------------------------------------------- #define PA_LOAD_8x8 #include "PA_Load.inc" // Load 16x8 packed data block // Packed data block should be loaded as 32x8 pixel block add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Block origin shl (1) rMSGSRC.0<1>:d rMSGSRC.0<0;1,0>:w 1:w // H. block origin need to be doubled mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_YUV:ud // Block width and height (32x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_YUV(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_YUV+nBI_CURRENT_SRC_YUV:ud // Unpack to "planar" YUV422 format in word-aligned bytes add (4) pCF_Y_OFFSET<1>:uw ubSRC_CF_OFFSET<4;4,1>:ub nSRC_YUV_REG*nGRFWIB:w // Initial Y,U,V offset in YUV422 block $for(0; r[pCF_Y_OFFSET, %1*nGRFWIB]REGION(16,2) mov (8) uwDEST_U(0, %1*8)<1> r[pCF_U_OFFSET, %1*nGRFWIB]REGION(8,4) mov (8) uwDEST_V(0, %1*8)<1> r[pCF_V_OFFSET, %1*nGRFWIB]REGION(8,4) } // End of PA_Load_8x8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PA_Load_9x8.asm000066400000000000000000000046111231401140700265370ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PA_Load_9x8.asm //---------------------------------------------------------------- // This module loads 16x8 Y, 9x8 U and 9x8 V planar data blocks for CSC module // and stores it in word-aligned format. //---------------------------------------------------------------- #define PA_LOAD_9x8 #include "PA_Load.inc" // Load 18x8 packed data block // Packed data block should be loaded as 36x8 pixel block add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Block origin shl (1) rMSGSRC.0<1>:d acc0:w 1:w // H. block origin need to be doubled mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_YUV_MAIN:ud // Block width and height (32x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_YUV(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_YUV_MAIN+nBI_CURRENT_SRC_YUV:ud add (1) rMSGSRC.0<1>:d rMSGSRC.0:d 32:w //the last 4 pixels are read again for optimization mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_YUV_ADDITION:ud // Block width and height (4x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_YUV(8)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_YUV_ADDITION+nBI_CURRENT_SRC_YUV:ud // Unpack to "planar" YUV422 format in word-aligned bytes add (4) pCF_Y_OFFSET<1>:uw ubSRC_CF_OFFSET<4;4,1>:ub nSRC_YUV_REG*nGRFWIB:w // Initial Y,U,V offset in YUV422 block $for(0; r[pCF_Y_OFFSET, %1*nGRFWIB]REGION(16,2) mov (8) uwDEST_U(0, %1*16)<1> r[pCF_U_OFFSET, %1*nGRFWIB]REGION(8,4) mov (8) uwDEST_V(0, %1*16)<1> r[pCF_V_OFFSET, %1*nGRFWIB]REGION(8,4) } $for(0; r[pCF_U_OFFSET, %1*4+256]REGION(1,0) mov (1) uwDEST_V(0, %1*16+8)<1> r[pCF_V_OFFSET, %1*4+256]REGION(1,0) } //UV expansion done in PL9x8_PL16x8.asm module // End of PA_Load_9x8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL16x8_PL8x4.asm000066400000000000000000000016471231401140700264770ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL16x8_PL8x4.asm //---------------------------------------------------------------- #include "common.inc" #ifndef DEST_U //DEST_U, DEST_V not defined #if (nSRC_REGION==nREGION_1) #define DEST_Y uwTOP_Y #define DEST_U uwTOP_U #define DEST_V uwTOP_V #elif (nSRC_REGION==nREGION_2) #define DEST_Y uwBOT_Y #define DEST_U uwBOT_U #define DEST_V uwBOT_V #endif #endif //Convert 444 from sampler to 422 $for (0, 0; <8; 2, 1) { mov (8) DEST_U(0,%2*8)<1> DEST_U(%1)<16;8,2> mov (8) DEST_V(0,%2*8)<1> DEST_V(%1)<16;8,2> } // Re-define new number of lines #undef nUV_NUM_OF_ROWS #define nUV_NUM_OF_ROWS 4 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL16x8_PL8x8.asm000066400000000000000000000015031231401140700264720ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL16x8_PL8x8.asm //---------------------------------------------------------------- #include "common.inc" #ifndef DEST_U //DEST_U, DEST_V not defined #if (nSRC_REGION==nREGION_1) #define DEST_Y uwTOP_Y #define DEST_U uwTOP_U #define DEST_V uwTOP_V #elif (nSRC_REGION==nREGION_2) #define DEST_Y uwBOT_Y #define DEST_U uwBOT_U #define DEST_V uwBOT_V #endif #endif //Convert 444 from sampler to 422 $for (0, 0; <8; 2, 1) { mov DEST_U(%2)<1> DEST_U(%1)<16;8,2> mov DEST_V(%2)<1> DEST_V(%1)<16;8,2> } intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL2_Load.inc000077500000000000000000000075401231401140700261240ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL2_Load.inc #undef nY_NUM_OF_ROWS #undef nUV_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 // Number of Y rows per block #define nDPR_BLOCK_SIZE_Y nBLOCK_WIDTH_16+nBLOCK_HEIGHT_8 // Y block size 16x8 #define nDPR_MSG_SIZE_Y nRESLEN_4 // # of MRF's to hold Y block data (4) #if defined(NV11_LOAD_4x8) #define nUV_NUM_OF_ROWS 8 // Number of U/V rows per block #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_8+nBLOCK_HEIGHT_8 // U/V block size 8x8 #define nDPR_MSG_SIZE_UV nRESLEN_2 // # of MRF's to hold U/V block data (2) #endif #if defined(NV11_LOAD_5x8) #define nUV_NUM_OF_ROWS 8 // Number of U/V rows per block #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_12+nBLOCK_HEIGHT_8 // U/V block size 12x8 #define nDPR_MSG_SIZE_UV nRESLEN_4 // # of MRF's to hold U/V block data (4) #endif #if defined(NV12_LOAD_8x4) #define nUV_NUM_OF_ROWS 4 // Number of U/V rows per block #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_16+nBLOCK_HEIGHT_4 // U/V block size 16x4 #define nDPR_MSG_SIZE_UV nRESLEN_2 // # of MRF's to hold U/V block data (2) #endif #if defined(NV12_LOAD_8x5) #define nUV_NUM_OF_ROWS 6 // Number of U/V rows per block (Rounded Up to Nearest Even Number) #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_16+nBLOCK_HEIGHT_5 // U/V block size 16x5 #define nDPR_MSG_SIZE_UV nRESLEN_3 // # of MRF's to hold U/V block data (3) #endif #if defined(NV12_LOAD_9x5) #define nUV_NUM_OF_ROWS 6 // Number of U/V rows per block (Rounded Up to Nearest Even Number) #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_20+nBLOCK_HEIGHT_5 // U/V block size 20x5 #define nDPR_MSG_SIZE_UV nRESLEN_5 // # of MRF's to hold U/V block data (5) #endif #if defined(P208_LOAD_8x8) #define nUV_NUM_OF_ROWS 8 // Number of U/V rows per block #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_16+nBLOCK_HEIGHT_8 // U/V block size 16x8 #define nDPR_MSG_SIZE_UV nRESLEN_4 // # of MRF's to hold U/V block data (4) #endif #if defined(P208_LOAD_9x8) #define nUV_NUM_OF_ROWS 8 // Number of U/V rows per block #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_20+nBLOCK_HEIGHT_8 // U/V block size 20x8 #define nDPR_MSG_SIZE_UV nRESLEN_8 // # of MRF's to hold U/V block data (8) #endif // Source/destination region definitions #if !defined(udSRC_Y) #define udSRC_Y udBOT_Y_IO // Default Y source region is top Y region #endif #if !defined(udSRC_U) #define udSRC_U udBOT_U_IO // Default U source region is top U region #endif #define ubSRC_Y ubBOT_Y #define nSRC_Y_REG nBOT_Y #define ubSRC_U ubBOT_U #define nSRC_U_REG nBOT_U #define uwDEST_Y uwTOP_Y // However they can be transferred to word-aligned byte if desired #define uwDEST_U uwTOP_U #define uwDEST_V uwTOP_V #define ubDEST_Y ubTOP_Y // I'd like use them for color conversion #define uwSRC_U uwBOT_U #define nSRC_REGION nREGION_1 // REGION_1 will be the source region for first kernel // End of PL2_Load.inc intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL3_Load.inc000066400000000000000000000046731231401140700261260ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL3_Load.inc #undef nY_NUM_OF_ROWS #undef nUV_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 // Number of Y rows per block #define nDPR_BLOCK_SIZE_Y nBLOCK_WIDTH_16+nBLOCK_HEIGHT_8 // Y block size 16x8 #define nDPR_MSG_SIZE_Y nRESLEN_4 // # of MRF's to hold Y block data (4) #if defined(IMC3_LOAD_8x4) #define nUV_NUM_OF_ROWS 4 // Number of U/V rows per block #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_8+nBLOCK_HEIGHT_4 // U/V block size 8x4 #define nDPR_MSG_SIZE_UV nRESLEN_1 // # of MRF's to hold U/V block data (1) #endif #if defined(IMC3_LOAD_8x5) #define nUV_NUM_OF_ROWS 6 // Number of U/V rows per block (Rounded Up to Nearest Even Number) #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_8+nBLOCK_HEIGHT_5 // U/V block size 8x5 #define nDPR_MSG_SIZE_UV nRESLEN_2 // # of MRF's to hold U/V block data (2) #endif #if defined(IMC3_LOAD_9x5) #define nUV_NUM_OF_ROWS 6 // Number of U/V rows per block (Rounded Up to Nearest Even Number) #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_12+nBLOCK_HEIGHT_5 // U/V block size 12x5 #define nDPR_MSG_SIZE_UV nRESLEN_3 // # of MRF's to hold U/V block data (3) #endif // Source/destination region definitions #if !defined(udSRC_Y) #define udSRC_Y udBOT_Y_IO // Default Y source region is top Y region #endif #if !defined(udSRC_U) #define udSRC_U udBOT_U_IO // Default U source region is top U region #endif #if !defined(udSRC_V) #define udSRC_V udBOT_V_IO // Default V source region is top V region #endif #define ubSRC_Y ubBOT_Y // Loading data are always in byte type #define ubSRC_U ubBOT_U #define ubSRC_V ubBOT_V #define uwDEST_Y uwTOP_Y // However they can be transferred to word-aligned byte if desired #define uwDEST_U uwTOP_U #define uwDEST_V uwTOP_V #define nSRC_REGION nREGION_1 // REGION_1 will be the source region for first kernel // End of PL3_Load.inc intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL4x8_Save_NV11.asm000066400000000000000000000102221231401140700271650ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #include "PL4x8_Save_NV11.inc" mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud #if !defined(SAVE_UV_ONLY) // Save current planar frame Y block data (16x8) ------------------------------- mov (2) mMSGHDR.0<1>:d wORIX<2;2,1>:w // Block origin mov (1) mMSGHDR.2<1>:ud nDPW_BLOCK_SIZE_Y:ud // Block width and height (16x8) ///* Yoni - masking is not relevant for ILK?!? // // //Use the mask to determine which pixels shouldn't be over-written // cmp.ge.f0.0 (1) NULLREG BLOCK_MASK_D:ud 0x00FFFFFF:ud //Check if all pixels in the block need to be modified // (f0.0) jmpi WritePlanarToDataPort // // //If mask is not all 1's, then load the entire 16x8 block // //so that only those bytes may be modified that need to be (using the mask) // send (8) SRC_YD(0)<1> MSGHDR MSGSRC<8;8,1>:ud DWBRMSGDSC+0x00040000+BI_DEST_Y:ud //16x8 // // asr (2) MSGSRC.0<1>:ud ORIX<2;2,1>:w 1:w // U/V block origin should be half of Y's // mov (1) MSGSRC.2<1>:ud 0x00030007:ud // Block width and height (8x4) // send (8) SRC_UD(0)<1> MSGHDR MSGSRC<8;8,1>:ud DWBRMSGDSC+0x00010000+BI_DEST_U:ud // send (8) SRC_VD(0)<1> MSGHDR MSGSRC<8;8,1>:ud DWBRMSGDSC+0x00010000+BI_DEST_V:ud // // //Restore the origin information // mov (2) MSGSRC.0<1>:ud ORIX<2;2,1>:w // Block origin // mov (1) MSGSRC.2<1>:ud 0x0007000F:ud // Block width and height (16x8) // // //expand U and V to be aligned on word boundary // mov (16) SRC_UW(1)<1> SRC_U(0,16) // mov (16) SRC_UW(0)<1> SRC_U(0, 0) // mov (16) SRC_VW(1)<1> SRC_V(0,16) // mov (16) SRC_VW(0)<1> SRC_V(0, 0) // // //Merge the data // mov (1) f0.1:uw BLOCK_MASK_V:uw //Load the mask on flag reg // (f0.1) mov (8) TEMP0<1>:uw BLOCK_MASK_H:uw // (-f0.1) mov (8) TEMP0<1>:uw 0:uw // // // Destination is Word aligned // $for(0; // (-f0.1) mov (16) DEST_Y(0, %1*32)<2> SRC_Y(0, %1*16) // (-f0.1) mov (16) DEST_U(0, %1*8)<1> SRC_U(0, %1*8) //only works for Word aligned Byte data // (-f0.1) mov (16) DEST_V(0, %1*8)<1> SRC_V(0, %1*8) //only works for Word aligned Byte data // // mov (1) f0.1:uw TEMP(0,1+%1)<0;1,0> // (-f0.1) mov (16) DEST_Y(0, 1+%1*32)<2> SRC_Y(0, 1+%1*16) // // } // //*/ Yoni - masking is not relevant for ILK?!? WritePlanarToDataPort: $for(0,0; ub2DEST_Y(%1)REGION(16,2) mov (16) mubMSGPAYLOAD(%2,16)<1> ub2DEST_Y(%1+1)REGION(16,2) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_Y+nBI_DESTINATION_Y:ud #endif // Save U/V data block in planar format (4x8) ---------------------------------- mov (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w // Block origin asr (1) rMSGSRC.0<1>:d rMSGSRC.0<0;1,0>:d 1:w // U/V block origin should be half of Y's mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud $for(0,0; ub2DEST_U(%2)REGION(16,2) mov (16) mubMSGPAYLOAD(%2,1)<2> ub2DEST_V(%2)REGION(16,2) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_UV+nBI_DESTINATION_UV:ud // End of PL4x8_Save_NV11 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL4x8_Save_NV11.inc000066400000000000000000000043541231401140700271670ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //Module name: PL8x4_Save_NV11.inc // // Setup for storing planar data // #include "undefall.inc" //Undefine the SRC and DEST sysmbols #define nDPW_BLOCK_SIZE_Y nBLOCK_WIDTH_16+nBLOCK_HEIGHT_8 // Y block size 16x8 #define nDPW_MSG_SIZE_Y nMSGLEN_4 // # of MRF's to hold Y block data (4) #define nDPW_BLOCK_SIZE_UV nBLOCK_WIDTH_8+nBLOCK_HEIGHT_8 // U/V interleaved block width and height (8x8) #define nDPW_MSG_SIZE_UV nMSGLEN_2 // # of MRF's to hold U/V block data (2) #if (nSRC_REGION==nREGION_1) #define udSRC_Y udBOT_Y_IO #define udSRC_U udBOT_U_IO #define udSRC_V udBOT_V_IO #define ubSRC_Y ubBOT_Y #define ubSRC_U ubBOT_U #define ubSRC_V ubBOT_V #define uwSRC_U uwBOT_U //For masking operation #define uwSRC_V uwBOT_V #define ub2DEST_Y ub2TOP_Y #define ub2DEST_U ub2TOP_U #define ub2DEST_V ub2TOP_V #elif (nSRC_REGION==nREGION_2) #define udSRC_Y udTOP_Y_IO #define udSRC_U udTOP_U_IO #define udSRC_V udTOP_V_IO #define ubSRC_Y ubTOP_Y #define ubSRC_U ubTOP_U #define ubSRC_V ubTOP_V #define uwSRC_U uwTOP_U //For masking operation #define uwSRC_V uwTOP_V #define ub2DEST_Y ub2BOT_Y #define ub2DEST_U ub2BOT_U #define ub2DEST_V ub2BOT_V #endif ///* Yoni - masking is not relevant for ILK?!? //#define TEMP0 REG(r,54) //.declare TEMP Base=TEMP0 ElementSize=2 SrcRegion=<8;8,1> Type=uw ///* Yoni - masking is not relevant for ILK?!? intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL5x8_PL16x8.asm000066400000000000000000000025041231401140700264710ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL5x8_PL16x8.asm #include "Expansion.inc" //------------------------------ Horizontal Upconversion ----------------------------- $for (nUV_NUM_OF_ROWS/2-1; >-1; -1) { avg.sat (16) uwDEST_U(0, %1*32+16) uwDEST_U(0, %1*16+7)<1;2,0> uwDEST_U(0, %1*16+7)<1;2,1> avg.sat (16) uwDEST_V(0, %1*32+16) uwDEST_V(0, %1*16+7)<1;2,0> uwDEST_V(0, %1*16+7)<1;2,1> avg.sat (16) uwDEST_U(0, %1*32) uwDEST_U(0, %1*16)<1;2,0> uwDEST_U(0, %1*16)<1;2,1> avg.sat (16) uwDEST_V(0, %1*32) uwDEST_V(0, %1*16)<1;2,0> uwDEST_V(0, %1*16)<1;2,1> } $for (nUV_NUM_OF_ROWS/2-1; >-1; -1) { avg.sat (16) uwDEST_U(0, %1*32+16) uwDEST_U(0, %1*32+18)<1;2,0> uwDEST_U(0, %1*32+18)<1;2,1> avg.sat (16) uwDEST_V(0, %1*32+16) uwDEST_V(0, %1*32+18)<1;2,0> uwDEST_V(0, %1*32+18)<1;2,1> avg.sat (16) uwDEST_U(0, %1*32) uwDEST_U(0, %1*32)<1;2,0> uwDEST_U(0, %1*32)<1;2,1> avg.sat (16) uwDEST_V(0, %1*32) uwDEST_V(0, %1*32)<1;2,0> uwDEST_V(0, %1*32)<1;2,1> } // End of PL5x8_PL16x8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL5x8_PL8x8.asm000066400000000000000000000012601231401140700264100ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL5x8_PL8x8.asm #include "Expansion.inc" //------------------------------ Horizontal Upconversion ----------------------------- $for (0; uwDEST_U(0, %1*8)<1;2,1> avg.sat (8) uwDEST_V(0, %1*8) uwDEST_V(0, %1*8)<1;2,0> uwDEST_V(0, %1*8)<1;2,1> } // End of PL5x8_PL8x8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL8x4_Save_IMC3.asm000077500000000000000000000113141231401140700272010ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL8x4_Save_IMC3.asm // // Save planar YUV420 frame data block of size 16x8 #include "PL8x4_Save_IMC3.inc" //Use the mask to determine which pixels shouldn't be over-written and (1) acc0.0<1>:ud udBLOCK_MASK<0;1,0>:ud 0x00FFFFFF:ud cmp.ge.f0.0(1) dNULLREG acc0.0<0;1,0>:ud 0x00FFFFFF:ud //Check if all pixels in the block need to be modified (f0.0) jmpi WritePlanarToDataPort //If mask is not all 1's, then load the entire 16x8 block //so that only those bytes may be modified that need to be (using the mask) // Load 16x8 planar Y ---------------------------------------------------------- mov (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w // Block origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_Y:ud // Block width and height (16x8) mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_Y(0)<1> mMSGHDR udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_DESTINATION_Y:ud // Load 8x4 planar U and V ----------------------------------------------------- asr (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_UV:ud // Block width and height (8x4) mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_U(0)<1> mMSGHDR udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_DESTINATION_U:ud mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_V(0)<1> mMSGHDR udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_DESTINATION_V:ud //expand U and V to be aligned on word boundary - Y remains in bytes $for (nUV_NUM_OF_ROWS/2-1; >-1; -1) { mov (16) uwSRC_U(0, %1*16)<1> ubSRC_U(0, %1*16) mov (16) uwSRC_V(0, %1*16)<1> ubSRC_V(0, %1*16) } //Merge the data mov (1) f0.0:uw ubBLOCK_MASK_V:ub //Load the mask on flag reg (f0.0) mov (8) rMASK_TEMP<1>:uw uwBLOCK_MASK_H:uw (-f0.0) mov (8) rMASK_TEMP<1>:uw 0:uw // Destination is Word aligned $for(0; (-f0.1) mov (16) ub2DEST_Y(0, %1*32)<2> ubSRC_Y(0, %1*16) (-f0.1) mov (16) ub2DEST_U(0, %1*8)<1> ubSRC_U(0, %1*8) //only works for Word aligned Byte data (-f0.1) mov (16) ub2DEST_V(0, %1*8)<1> ubSRC_V(0, %1*8) //only works for Word aligned Byte data mov (1) f0.1:uw uwMASK_TEMP(0,1+%1)<0;1,0> (-f0.1) mov (16) ub2DEST_Y(0, (1+%1)*32)<2> ubSRC_Y(0, (1+%1)*16) } WritePlanarToDataPort: #if !defined(SAVE_UV_ONLY) // Save current planar frame Y block data (16x8) ------------------------------- mov (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w // Block origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_Y:ud // Block width and height (16x8) mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud $for(0,0; ub2DEST_Y(%1)REGION(16,2) mov(16) mubMSGPAYLOAD(%2,16)<1> ub2DEST_Y(%1+1)REGION(16,2) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_Y+nBI_DESTINATION_Y:ud #endif // Save U/V data block in planar format (8x4) ---------------------------------- asr (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_UV:ud // Block width and height (8x4) mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud // Save U picture data --------------------------------------------------------- mov (16) mubMSGPAYLOAD(0,0)<1> ub2DEST_U(0)REGION(16,2) // U rows 0,1 mov (16) mubMSGPAYLOAD(0,16)<1> ub2DEST_U(1)REGION(16,2) // U rows 2,3 send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_UV+nBI_DESTINATION_U:ud mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud // Save V picture data --------------------------------------------------------- mov (16) mubMSGPAYLOAD(0,0)<1> ub2DEST_V(0)REGION(16,2) // V rows 0,1 mov (16) mubMSGPAYLOAD(0,16)<1> ub2DEST_V(1)REGION(16,2) // V rows 2,3 send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_UV+nBI_DESTINATION_V:ud // End of PL8x4_Save_IMC3 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL8x4_Save_IMC3.inc000066400000000000000000000042751231401140700271770ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL8x4_Save_IMC3.inc // // Setup for storing planar data // #include "undefall.inc" //Undefine the SRC and DEST sysmbols // For saving #define nDPW_BLOCK_SIZE_Y nBLOCK_WIDTH_16+nBLOCK_HEIGHT_8 // Y block size 16x8 #define nDPW_MSG_SIZE_Y nMSGLEN_4 // # of MRF's to hold Y block data (4) #define nDPW_BLOCK_SIZE_UV nBLOCK_WIDTH_8+nBLOCK_HEIGHT_4 // U/V block size 8x4 #define nDPW_MSG_SIZE_UV nMSGLEN_1 // # of MRF's to hold U/V block data (1) // For masking #undef nDPR_MSG_SIZE_Y #define nDPR_MSG_SIZE_Y nRESLEN_4 // # of MRF's to hold Y block data (4) #undef nDPR_MSG_SIZE_UV #define nDPR_MSG_SIZE_UV nRESLEN_1 // # of MRF's to hold U/V block data (1) #define rMASK_TEMP REG(r,nTEMP0) .declare uwMASK_TEMP Base=rMASK_TEMP ElementSize=2 SrcRegion=<8;8,1> Type=uw //1 GRF #if (nSRC_REGION==nREGION_1) // For saving #define ub2DEST_Y ub2TOP_Y #define ub2DEST_U ub2TOP_U #define ub2DEST_V ub2TOP_V //For masking operation #define udSRC_Y udBOT_Y_IO #define udSRC_U udBOT_U_IO #define udSRC_V udBOT_V_IO #define ubSRC_Y ubBOT_Y #define ubSRC_U ubBOT_U #define ubSRC_V ubBOT_V #define uwSRC_U uwBOT_U #define uwSRC_V uwBOT_V #elif (nSRC_REGION==nREGION_2) // For saving #define ub2DEST_Y ub2BOT_Y #define ub2DEST_U ub2BOT_U #define ub2DEST_V ub2BOT_V //For masking operation #define udSRC_Y udTOP_Y_IO #define udSRC_U udTOP_U_IO #define udSRC_V udTOP_V_IO #define ubSRC_Y ubTOP_Y #define ubSRC_U ubTOP_U #define ubSRC_V ubTOP_V #define uwSRC_U uwTOP_U #define uwSRC_V uwTOP_V #endif intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL8x4_Save_NV12.asm000066400000000000000000000111271231401140700271730ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL8x4_Save_NV12.asm // // Save entire current planar frame data block of size 16x8 //--------------------------------------------------------------- // Symbols needed to be defined before including this module // // DWORD_ALIGNED_DEST: only if DEST_Y, DEST_U, DEST_V data are DWord aligned // ORIX: //--------------------------------------------------------------- #include "PL8x4_Save_NV12.inc" mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud #if !defined(SAVE_UV_ONLY) // Save current planar frame Y block data (16x8) ------------------------------- mov (2) mMSGHDR.0<1>:d wORIX<2;2,1>:w // Block origin mov (1) mMSGHDR.2<1>:ud nDPW_BLOCK_SIZE_Y:ud // Block width and height (16x8) #endif //Use the mask to determine which pixels shouldn't be over-written and (1) acc0<1>:ud udBLOCK_MASK<0;1,0>:ud 0x00FFFFFF:ud cmp.ge.f0.0 (1) dNULLREG acc0<0;1,0>:ud 0x00FFFFFF:ud //Check if all pixels in the block need to be modified (f0.0) jmpi WritePlanarToDataPort //If mask is not all 1's, then load the entire 16x8 block //so that only those bytes may be modified that need to be (using the mask) send (8) udSRC_Y(0)<1> mMSGHDR udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_DESTINATION_Y:ud //16x8 asr (1) rMSGSRC.1<1>:ud wORIY<0;1,0>:w 1:w { NoDDClr } // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_UV:ud { NoDDChk } // Block width and height (16x4) mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud //move message desrcptor to the message header send (8) udSRC_U(0)<1> mMSGHDR udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_DESTINATION_UV:ud //Restore the origin information mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // Block origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_Y:ud // Block width and height (16x8) mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud //move message desrcptor to the message header //Merge the data mov (1) f0.1:uw ubBLOCK_MASK_V:ub //Load the mask on flag reg (f0.1) mov (8) rMASK_TEMP<1>:uw uwBLOCK_MASK_H:uw (-f0.1) mov (8) rMASK_TEMP<1>:uw 0:uw //convert the mask from 16bits to 8bits by selecting every other bit mov (1) udMASK_TEMP1(0,0)<1> 0x00040001:ud mov (1) udMASK_TEMP1(0,1)<1> 0x00400010:ud mov (1) udMASK_TEMP1(0,2)<1> 0x04000100:ud mov (1) udMASK_TEMP1(0,3)<1> 0x40001000:ud //merge the loaded block with the current block $for(0,0; (-f0.1) mov (16) ubDEST_Y(0,%1*32)<2> ubSRC_Y(0,%1*16) and.nz.f0.1 (8) wNULLREG uwMASK_TEMP(0,%1)<0;1,0> uwMASK_TEMP1(0,0) //change the mask by selecting every other bit (-f0.1) mov (8) ubDEST_U(0, %2*16)<2> ub2SRC_U(0, %1*8)<16;8,2> (-f0.1) mov (8) ubDEST_V(0, %2*16)<2> ub2SRC_U(0, %1*8+1)<16;8,2> mov (1) f0.1:uw uwMASK_TEMP(0,1+%1)<0;1,0> (-f0.1) mov (16) ubDEST_Y(0, (1+%1)*32)<2> ubSRC_Y(0, (1+%1)*16) } WritePlanarToDataPort: #if !defined(SAVE_UV_ONLY) $for(0,0; ub2DEST_Y(%1)REGION(16,2) mov (16) mubMSGPAYLOAD(%2,16)<1> ub2DEST_Y(%1+1)REGION(16,2) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_Y+nBI_DESTINATION_Y:ud #endif //** Save 8x4 packed U and V ----------------------------------------------------- // we could write directly wORIX to mMSGHDR and then execute asr on it, that way we could // avoid using rMSGSRC as a buffer and have one command less in code, but it is unknown whether //it is possible to do asr on mMSGHDR so we use rMSGSRC. mov (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w // Block origin asr (1) rMSGSRC.1<1>:d rMSGSRC.1<0;1,0>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_UV:ud // U/V block width and height (16x4) mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud $for(0,0; ub2DEST_U(%2)REGION(16,2) mov (16) mubMSGPAYLOAD(%2,1)<2> ub2DEST_V(%2)REGION(16,2) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_UV+nBI_DESTINATION_UV:ud // End of PL8x4_Save_NV12 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL8x4_Save_NV12.inc000066400000000000000000000064701231401140700271710ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //Module name: PL8x4_Save_NV12.inc // // Setup for storing planar data // #include "undefall.inc" //Undefine the SRC and DEST sysmbols #undef nDPW_BLOCK_SIZE_Y #undef nDPW_MSG_SIZE_Y #undef nDPW_BLOCK_SIZE_UV #undef nDPW_MSG_SIZE_UV #define nDPW_BLOCK_SIZE_Y nBLOCK_WIDTH_16+nBLOCK_HEIGHT_8 // Y block size 16x8 #define nDPW_MSG_SIZE_Y nMSGLEN_4 // # of MRF's to hold Y block data (4) #define nDPW_BLOCK_SIZE_UV nBLOCK_WIDTH_16+nBLOCK_HEIGHT_4 // U/V interleaved block width and height (16x4) #define nDPW_MSG_SIZE_UV nMSGLEN_2 // # of MRF's to hold U/V block data (2) // For masking #undef nDPR_MSG_SIZE_Y #define nDPR_MSG_SIZE_Y nRESLEN_4 // # of MRF's to hold Y block data (4) #undef nDPR_MSG_SIZE_UV #define nDPR_MSG_SIZE_UV nRESLEN_2 #define rMASK_TEMP REG(r,nTEMP0) .declare uwMASK_TEMP Base=rMASK_TEMP ElementSize=2 SrcRegion=<8;8,1> Type=uw //1 GRF #define rMASK_TEMP1 REG(r,nTEMP1) .declare udMASK_TEMP1 Base=rMASK_TEMP1 ElementSize=4 SrcRegion=<4;4,1> Type=ud //1 GRF .declare uwMASK_TEMP1 Base=rMASK_TEMP1 ElementSize=2 SrcRegion=<8;8,1> Type=uw //1 GRF #if (nSRC_REGION==nREGION_1) #define udSRC_Y udBOT_Y_IO #define udSRC_U udBOT_U_IO #define udSRC_V udBOT_V_IO #define ubSRC_Y ubBOT_Y #define ubSRC_U ubBOT_U #define ubSRC_V ubBOT_V #define uwSRC_U uwBOT_U //For masking operation #define uwSRC_V uwBOT_V #define ub2DEST_Y ub2TOP_Y #define ub2DEST_U ub2TOP_U #define ub2DEST_V ub2TOP_V #define ubDEST_Y ubTOP_Y #define ubDEST_U ubTOP_U #define ubDEST_V ubTOP_V #define ub2SRC_U ub2BOT_U #elif (nSRC_REGION==nREGION_2) #define udSRC_Y udTOP_Y_IO #define udSRC_U udTOP_U_IO #define udSRC_V udTOP_V_IO #define ubSRC_Y ubTOP_Y #define ubSRC_U ubTOP_U #define ubSRC_V ubTOP_V #define uwSRC_U uwTOP_U //For masking operation #define uwSRC_V uwTOP_V #define ub2DEST_Y ub2BOT_Y #define ub2DEST_U ub2BOT_U #define ub2DEST_V ub2BOT_V #define ubDEST_Y ubBOT_Y #define ubDEST_U ubBOT_U #define ubDEST_V ubBOT_V #define ub2SRC_U ub2TOP_U #endif ///* Yoni - masking is not relevant for ILK?!? //#define TEMP0 REG(r,54) //.declare TEMP Base=TEMP0 ElementSize=2 SrcRegion=<8;8,1> Type=uw ///* Yoni - masking is not relevant for ILK?!? intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL8x5_PL8x8.asm000066400000000000000000000020051231401140700264060ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL8x5_PL8x8.asm #include "Expansion.inc" //------------------------------- Vertical Upconversion ------------------------------ avg.sat (8) uwDEST_U(0, 3*16+8)<1> uwDEST_U(0, 3*8) uwDEST_U(0, (1+3)*8) // Optimization avg.sat (8) uwDEST_V(0, 3*16+8)<1> uwDEST_V(0, 3*8) uwDEST_V(0, (1+3)*8) // Optimization $for(nUV_NUM_OF_ROWS/2-2; >-1; -1) { mov (8) uwDEST_U(0, (1+%1)*16)<1> uwDEST_U(0, (1+%1)*8) avg.sat (8) uwDEST_U(0, %1*16+8)<1> uwDEST_U(0, %1*8) uwDEST_U(0, (1+%1)*8) mov (8) uwDEST_V(0, (1+%1)*16)<1> uwDEST_V(0, (1+%1)*8) avg.sat (8) uwDEST_V(0, %1*16+8)<1> uwDEST_V(0, %1*8) uwDEST_V(0, (1+%1)*8) } // End of PL8x5_PL8x8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL8x8_PL8x4.asm000066400000000000000000000022031231401140700264050ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL8x8_PL8x4.asm // // Convert PL 8x8 to PL8x4 in GRF //--------------------------------------------------------------- // Symbols needed to be defined before including this module // // DWORD_ALIGNED_DEST: only if DEST_Y, DEST_U, DEST_V data are DWord aligned // ORIX: //--------------------------------------------------------------- #include "PL8x8_PL8x4.inc" // Convert PL8x8 to PL8x4 --------------------------------------------------------- mov (8) ubDEST_U(0,16)<2> ubDEST_U(1)<16;8,2> //selecting U every other row mov (16) ubDEST_U(0,32)<2> ubDEST_U(2)<32;8,2> //selecting U every other row mov (8) ubDEST_V(0,16)<2> ubDEST_V(1)<16;8,2> //selecting V every other row mov (16) ubDEST_V(0,32)<2> ubDEST_V(2)<32;8,2> //selecting V every other row // End of PL8x8_PL8x4.asm -------------------------------------------------------intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL8x8_PL8x4.inc000066400000000000000000000014041231401140700264000ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL8x8_PL8x4.inc // // Setup module for convert PL8x8 to PL8x4 // // // Source/destination region definitions // #include "undefall.inc" //Undefine the SRC and DEST sysmbols #if (nSRC_REGION==nREGION_1) //REGION_1 selected #define ubDEST_Y ubTOP_Y #define ubDEST_U ubTOP_U #define ubDEST_V ubTOP_V #elif (nSRC_REGION==nREGION_2) //REGION_2 selected #define ubDEST_Y ubBOT_Y #define ubDEST_U ubBOT_U #define ubDEST_V ubBOT_V #endif intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL8x8_Save_P208.asm000066400000000000000000000045251231401140700271460ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL8x8_Save_P208.asm // // Save entire current planar frame data block of size 16x8 //--------------------------------------------------------------- // Symbols needed to be defined before including this module // // DWORD_ALIGNED_DEST: only if DEST_Y, DEST_U, DEST_V data are DWord aligned // ORIX: //--------------------------------------------------------------- #include "PL8x8_Save_P208.inc" mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud #if !defined(SAVE_UV_ONLY) // Save current planar frame Y block data (16x8) ------------------------------- mov (2) mMSGHDR.0<1>:d wORIX<2;2,1>:w // Block origin mov (1) mMSGHDR.2<1>:ud nDPW_BLOCK_SIZE_Y:ud // Block width and height (16x8) WritePlanarToDataPort: $for(0,0; ub2DEST_Y(%1)REGION(16,2) mov (16) mubMSGPAYLOAD(%2,16)<1> ub2DEST_Y(%1+1)REGION(16,2) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_Y+nBI_DESTINATION_Y:ud #endif //** Save 8x8 packed U and V ----------------------------------------------------- // we could write directly wORIX to mMSGHDR and then execute asr on it, that way we could // avoid using rMSGSRC as a buffer and have one command less in code, but it is unknown whether //it is possible to do asr on mMSGHDR so we use rMSGSRC. mov (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w // Block origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_UV:ud // U/V block width and height (16x4) mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud $for(0,0; ub2DEST_U(%2)REGION(16,2) mov (16) mubMSGPAYLOAD(%2,1)<2> ub2DEST_V(%2)REGION(16,2) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_UV+nBI_DESTINATION_UV:ud //End of PL8x8_Save_P208.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL8x8_Save_P208.inc000066400000000000000000000043571231401140700271420ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //Module name: PL8x8_Save_P208.inc // // Setup for storing planar data // #include "undefall.inc" //Undefine the SRC and DEST sysmbols #define nDPW_BLOCK_SIZE_Y nBLOCK_WIDTH_16+nBLOCK_HEIGHT_8 // Y block size 16x8 #define nDPW_MSG_SIZE_Y nMSGLEN_4 // # of MRF's to hold Y block data (4) #define nDPW_BLOCK_SIZE_UV nBLOCK_WIDTH_16+nBLOCK_HEIGHT_8 // U/V interleaved block width and height (16x8) #define nDPW_MSG_SIZE_UV nMSGLEN_4 // # of MRF's to hold U/V block data (4) #if (nSRC_REGION==nREGION_1) #define udSRC_Y udBOT_Y_IO #define udSRC_U udBOT_U_IO #define udSRC_V udBOT_V_IO #define ubSRC_Y ubBOT_Y #define ubSRC_U ubBOT_U #define ubSRC_V ubBOT_V #define uwSRC_U uwBOT_U //For masking operation #define uwSRC_V uwBOT_V #define ub2DEST_Y ub2TOP_Y #define ub2DEST_U ub2TOP_U #define ub2DEST_V ub2TOP_V #elif (nSRC_REGION==nREGION_2) #define udSRC_Y udTOP_Y_IO #define udSRC_U udTOP_U_IO #define udSRC_V udTOP_V_IO #define ubSRC_Y ubTOP_Y #define ubSRC_U ubTOP_U #define ubSRC_V ubTOP_V #define uwSRC_U uwTOP_U //For masking operation #define uwSRC_V uwTOP_V #define ub2DEST_Y ub2BOT_Y #define ub2DEST_U ub2BOT_U #define ub2DEST_V ub2BOT_V #endif ///* Yoni - masking is not relevant for ILK?!? //#define TEMP0 REG(r,54) //.declare TEMP Base=TEMP0 ElementSize=2 SrcRegion=<8;8,1> Type=uw ///* Yoni - masking is not relevant for ILK?!? intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL8x8_Save_PA.asm000066400000000000000000000060251231401140700270120ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL8x8_Save_PA.asm // // Save planar YUV422 to packed YUV422 format data // // Note: SRC_* must reference to regions with data type "BYTE" // in order to save to byte-aligned byte location #include "PL8x8_Save_PA.inc" add (4) pCF_Y_OFFSET<1>:uw ubDEST_CF_OFFSET<4;4,1>:ub nDEST_YUV_REG*nGRFWIB:w // Initial Y,U,V offset in YUV422 block // Pack Y $for(0; ubSRC_Y(0,%1*32) } // Pack U/V $for(0; ubSRC_U(0, %1*16) mov (8) r[pCF_V_OFFSET, %1*nGRFWIB]<4> ubSRC_V(0, %1*16) } shl (1) rMSGSRC.0<1>:d wORIX<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be doubled mov (1) rMSGSRC.1<1>:d wORIY<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_YUV:ud { NoDDChk } // Block width and height (32x8) mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud //Use the mask to determine which pixels shouldn't be over-written and (1) acc0.0<1>:ud udBLOCK_MASK<0;1,0>:ud 0x00FFFFFF:ud cmp.ge.f0.0(1) dNULLREG acc0.0<0;1,0>:ud 0x00FFFFFF:ud //Check if all pixels in the block need to be modified (f0.0) jmpi WritePackedToDataPort //If mask is not all 1's, then load the entire 32x8 block //so that only those bytes may be modified that need to be (using the mask) // Load 32x8 packed YUV 422 ---------------------------------------------------- send (8) udSRC_YUV(0)<1> mMSGHDR udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_YUV+nBI_DESTINATION_YUV:ud mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud //Merge the data mov (1) f0.0:uw ubBLOCK_MASK_V:ub //Load the mask on flag reg (f0.0) mov (8) rMASK_TEMP<1>:uw uwBLOCK_MASK_H:uw (-f0.0) mov (8) rMASK_TEMP<1>:uw 0:uw // Destination is Byte aligned $for(0; (-f0.1) mov (16) uwDEST_YUV(%1)<1> uwSRC_YUV(%1) //check the UV merge - vK } WritePackedToDataPort: // Packed YUV data are stored in one of the I/O regions before moving to MRF // Note: This is necessary since indirect addressing is not supported for MRF. // Packed data block should be saved as 32x8 pixel block $for(0; udDEST_YUV(%1)REGION(8,1) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_YUV+nBI_DESTINATION_YUV:ud // End of PL8x8_Save_PA intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL8x8_Save_PA.inc000066400000000000000000000032741231401140700270060ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL8x8_Save_PA.inc // // Setup for storing packed data // #include "undefall.inc" //Undefine the SRC and DEST sysmbols // For saving #define nDPW_BLOCK_SIZE_YUV nBLOCK_WIDTH_32+nBLOCK_HEIGHT_8 // YUV block size 32x8 #define nDPW_MSG_SIZE_YUV nMSGLEN_8 // # of MRF's to hold YUV block data (8) // For masking #undef nDPR_MSG_SIZE_YUV #define nDPR_MSG_SIZE_YUV nRESLEN_8 // # of MRF's to hold YUV block data (8) #define rMASK_TEMP REG(r,nTEMP0) .declare uwMASK_TEMP Base=rMASK_TEMP ElementSize=2 SrcRegion=<8;8,1> Type=uw //1 GRF #if (nSRC_REGION==nREGION_1) // For saving #define udSRC_YUV udTOP_Y_IO #define udDEST_YUV udBOT_Y_IO #define nDEST_YUV_REG nBOT_Y //For masking operation #define ubSRC_Y ub2TOP_Y #define ubSRC_U ub2TOP_U #define ubSRC_V ub2TOP_V #define uwSRC_YUV uwTOP_Y #define uwDEST_YUV uwBOT_Y #elif (nSRC_REGION==nREGION_2) // For saving #define udSRC_YUV udBOT_Y_IO #define udDEST_YUV udTOP_Y_IO #define nDEST_YUV_REG nTOP_Y //For masking operation #define ubSRC_Y ub2BOT_Y #define ubSRC_U ub2BOT_U #define ubSRC_V ub2BOT_V #define uwSRC_YUV uwBOT_Y #define uwDEST_YUV uwTOP_Y #endif intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL9x5_PL16x8.asm000066400000000000000000000027001231401140700264700ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL9x5_PL16x8.asm #define EXPAND_9x5 #include "Expansion.inc" //------------------------------ Horizontal Upconversion ----------------------------- $for (nUV_NUM_OF_ROWS-2; >-1; -1) { avg.sat (16) uwDEST_U(0, %1*16)<1> uwDEST_U(0, %1*16)<1;2,0> uwDEST_U(0, %1*16)<1;2,1> avg.sat (16) uwDEST_V(0, %1*16)<1> uwDEST_V(0, %1*16)<1;2,0> uwDEST_V(0, %1*16)<1;2,1> } #undef nUV_NUM_OF_ROWS #define nUV_NUM_OF_ROWS 8 //use packed version of all post-processing kernels //------------------------------- Vertical Upconversion ------------------------------ avg.sat (16) uwDEST_U(0, 3*32+16)<1> uwDEST_U(0, 3*16) uwDEST_U(0, (1+3)*16) avg.sat (16) uwDEST_V(0, 3*32+16)<1> uwDEST_V(0, 3*16) uwDEST_V(0, (1+3)*16) $for(nUV_NUM_OF_ROWS/2-2; >-1; -1) { mov (16) uwDEST_U(0, (1+%1)*32)<1> uwDEST_U(0, (1+%1)*16) avg.sat (16) uwDEST_U(0, %1*32+16)<1> uwDEST_U(0, %1*16) uwDEST_U(0, (1+%1)*16) mov (16) uwDEST_V(0, (1+%1)*32)<1> uwDEST_V(0, (1+%1)*16) avg.sat (16) uwDEST_V(0, %1*32+16)<1> uwDEST_V(0, %1*16) uwDEST_V(0, (1+%1)*16) } // End of PL9x5_PL16x8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/PL9x8_PL16x8.asm000066400000000000000000000012771231401140700265030ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: PL9x5_PL16x8.asm #include "Expansion.inc" //------------------------------ Horizontal Upconversion ----------------------------- $for (0; uwDEST_U(0, %1*16)<1;2,0> uwDEST_U(0, %1*16)<1;2,1> avg.sat (16) uwDEST_V(0, %1*16)<1> uwDEST_V(0, %1*16)<1;2,0> uwDEST_V(0, %1*16)<1;2,1> } // End of PL9x5_PL16x8intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/RGB16x8_Save_RGB.asm000066400000000000000000000105311231401140700272770ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: RGB16x8_Save_RGB.asm // // Save packed ARGB 444 frame data block of size 16x8 // // To save 16x8 block (64x8 byte layout for ARGB8888) we need 2 send instructions // --------- // | 1 | 2 | // --------- #include "RGB16x8_Save_RGB.inc" shl (1) rMSGSRC.0<1>:d wORIX<0;1,0>:w 2:w { NoDDClr } // H. block origin need to be quadrupled mov (1) rMSGSRC.1<1>:d wORIY<0;1,0>:w { NoDDClr, NoDDChk } // Block origin (1st quadrant) mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_ARGB:ud { NoDDChk } // Block width and height (32x8) mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud //Use the mask to determine which pixels shouldn't be over-written and (1) acc0.0<1>:ud udBLOCK_MASK<0;1,0>:ud 0x00FFFFFF:ud cmp.ge.f0.0(1) dNULLREG acc0.0<0;1,0>:ud 0x00FFFFFF:ud //Check if all pixels in the block need to be modified (f0.0) jmpi WriteARGBToDataPort //If mask is not all 1's, then load the entire 64x8 block //so that only those bytes may be modified that need to be (using the mask) // Load first block 16x8 packed ARGB 444 --------------------------------------- or (1) acc0.0<1>:ud udBLOCK_MASK<0;1,0>:ud 0xFF00FF00:ud //Check first block cmp.e.f0.0 (1) dNULLREG acc0.0<0;1,0>:ud 0xFFFFFFFF:ud (f0.0) jmpi SkipFirstBlockMerge //If full mask then skip this block send (8) udSRC_ARGB(0)<1> mMSGHDR udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_ARGB+nBI_DESTINATION_RGB:ud mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud //Merge the data mov (1) f0.0:uw ubBLOCK_MASK_V:ub //Load the mask on flag reg (f0.0) mov (8) rMASK_TEMP<1>:uw uwBLOCK_MASK_H:uw //use sel instruction - vK (-f0.0) mov (8) rMASK_TEMP<1>:uw 0:uw $for(0, 0; (-f0.1) mov (8) udDEST_ARGB(%2)<1> udSRC_ARGB(%1) } SkipFirstBlockMerge: // Load second block 16x8 packed ARGB 444 --------------------------------------- or (1) acc0.0<1>:ud udBLOCK_MASK<0;1,0>:ud 0xFF0000FF:ud //Check second block cmp.e.f0.0 (1) dNULLREG acc0.0<0;1,0>:ud 0xFFFFFFFF:ud (f0.0) jmpi WriteARGBToDataPort //If full mask then skip this block add (1) mMSGHDR.0<1>:d rMSGSRC.0<0;1,0>:d 32:d // Point to 2nd part send (8) udSRC_ARGB(0)<1> mMSGHDR udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_ARGB+nBI_DESTINATION_RGB:ud mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud // Point to 1st part again //Merge the data mov (1) f0.0:uw ubBLOCK_MASK_V:ub //Load the mask on flag reg (f0.0) shr (8) rMASK_TEMP<1>:uw uwBLOCK_MASK_H:uw 8:uw //load the mask for second block (-f0.0) mov (8) rMASK_TEMP<1>:uw 0:uw $for(0, 1; (-f0.1) mov (8) udDEST_ARGB(%2)<1> udSRC_ARGB(%1) } WriteARGBToDataPort: // Move packed data to MRF and output $for(0; udDEST_ARGB(%1*2) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_ARGB+nBI_DESTINATION_RGB:ud mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud add (1) mMSGHDR.0<1>:d rMSGSRC.0<0;1,0>:d 32:d // Point to 2nd part $for(0; udDEST_ARGB(%1*2+1) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_ARGB+nBI_DESTINATION_RGB:ud // End of RGB16x8_Save_RGB intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/RGB16x8_Save_RGB.inc000066400000000000000000000030351231401140700272710ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: RGB16x8_Save_RGB.inc // #include "undefall.inc" //Undefine the SRC and DEST sysmbols // For saving #define nDPW_BLOCK_SIZE_ARGB nBLOCK_WIDTH_32+nBLOCK_HEIGHT_8 // ARGB block size 32x8 #define nDPW_MSG_SIZE_ARGB nMSGLEN_8 // # of MRF's to hold ARGB block data (8) // For masking #undef nDPR_MSG_SIZE_ARGB #define nDPR_MSG_SIZE_ARGB nRESLEN_8 // # of MRF's to hold ARGB block data (8) #define rMASK_TEMP REG(r,nTEMP0) .declare uwMASK_TEMP Base=rMASK_TEMP ElementSize=2 SrcRegion=<8;8,1> Type=uw //1 GRF #if (nSRC_REGION==nREGION_1) // For saving #define udDEST_ARGB udTOP_Y_IO //The output of previous stage is stored here; This is modified and is written to render cache //For masking operation #define udSRC_ARGB udBOT_Y_IO //To hold the destination data that shouldn't be modified #elif (nSRC_REGION==nREGION_2) // For saving #define udDEST_ARGB udBOT_Y_IO //The output of previous stage is stored here; This is modified and is written to render cache //For masking operation #define udSRC_ARGB udTOP_Y_IO //To hold the destination data that shouldn't be modified #endif intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/RGB16x8_Save_RGB16.asm000066400000000000000000000061611231401140700274520ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: RGB16x8_Save_RGB16.asm // // Save packed RGB565 frame data block of size 16x8 // // To save 16x8 block (32x8 byte layout for RGB565) we need 1 send instruction // ----- // | 1 | // ----- #include "RGB16x8_Save_RGB16.inc" //convert 32 bit RGB to 16 bit RGB // Truncate A8R8G8B8 to A6R5G6B5 within byte. // That is keeping 5 MSB of R and B, and 6 MSB of G. $for (0, 0; ubDEST_ARGB(%2,0)<32;8,4> 3:w // B >> 3 shl (16) uwTEMP_RGB16(0)<1> uwDEST_ARGB(%2,1)<16;8,2> 8:w // R << 8 and (16) uwTEMP_RGB16(0)<1> uwTEMP_RGB16(0) 0xF800:uw or (16) uwCSC_TEMP(%1,0)<1> uwCSC_TEMP(%1,0)<16;16,1> uwTEMP_RGB16(0) shr (16) uwTEMP_RGB16(0)<1> uwDEST_ARGB(%2,0)<16;8,2> 5:w // G >> 5 and (16) uwTEMP_RGB16(0)<1> uwTEMP_RGB16(0) 0x07E0:uw or (16) uwCSC_TEMP(%1,0)<1> uwCSC_TEMP(%1,0)<16;16,1> uwTEMP_RGB16(0) } mov (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w // Block origin (1st quadrant) shl (1) rMSGSRC.0<1>:d wORIX<0;1,0>:w 1:w // H. block origin need to be doubled for byte offset mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_RGB16:ud // Block width and height (32x8) mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud //Use the mask to determine which pixels shouldn't be over-written and (1) acc0.0<1>:ud udBLOCK_MASK<0;1,0>:ud 0x00FFFFFF:ud cmp.ge.f0.0(1) dNULLREG acc0.0<0;1,0>:ud 0x00FFFFFF:ud //Check if all pixels in the block need to be modified (f0.0) jmpi WriteRGB16ToDataPort //If mask is not all 1's, then load the entire 32x8 block //so that only those bytes may be modified that need to be (using the mask) // Load 32x8 packed RGB565 ----------------------------------------------------- send (8) udSRC_RGB16(0)<1> mMSGHDR udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_RGB16+nBI_DESTINATION_RGB:ud mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud //Merge the data mov (1) f0.0:uw ubBLOCK_MASK_V:ub //Load the mask on flag reg (f0.0) mov (8) rMASK_TEMP<1>:uw uwBLOCK_MASK_H:uw //use sel instruction - vK (-f0.0) mov (8) rMASK_TEMP<1>:uw 0:uw $for(0; (-f0.1) mov (16) uwCSC_TEMP(%1)<1> uwSRC_RGB16(%1) } WriteRGB16ToDataPort: // Move packed data to MRF and output $for(0; udCSC_TEMP(%1) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_RGB16+nBI_DESTINATION_RGB:ud // End of RGB16x8_Save_RGB16 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/RGB16x8_Save_RGB16.inc000066400000000000000000000037071231401140700274460ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: RGB16x8_Save_RGB16.inc // #include "undefall.inc" //Undefine the SRC and DEST sysmbols // For saving #define nDPW_BLOCK_SIZE_RGB16 nBLOCK_WIDTH_32+nBLOCK_HEIGHT_8 // RGB16 block size 32x8 #define nDPW_MSG_SIZE_RGB16 nMSGLEN_8 // # of MRF's to hold RGB16 block data (8) // For conversion to 16bit .declare uwTEMP_RGB16 Base=REG(r,nTEMP1) ElementSize=2 SrcRegion=<16;16,1> Type=uw //1 GRF // For masking #undef nDPR_MSG_SIZE_RGB16 #define nDPR_MSG_SIZE_RGB16 nRESLEN_8 // # of MRF's to hold ARGB block data (8) #define rMASK_TEMP REG(r,nTEMP0) .declare uwMASK_TEMP Base=rMASK_TEMP ElementSize=2 SrcRegion=<8;8,1> Type=uw //1 GRF #if (nSRC_REGION==nREGION_1) // For saving #define ubDEST_ARGB ubTOP_Y //Data from previous module #define uwDEST_ARGB uwTOP_Y //Data from previous module #define udCSC_TEMP udBOT_Y_IO //Data Converted to 16 bits #define uwCSC_TEMP uwBOT_Y //For masking operation #define udSRC_RGB16 udTOP_Y_IO //To hold the destination data that shouldn't be modified #define uwSRC_RGB16 uwTOP_Y #elif (nSRC_REGION==nREGION_2) // For saving #define ubDEST_ARGB ubBOT_Y //Data from previous module #define uwDEST_ARGB uwBOT_Y //Data from previous module #define udCSC_TEMP udTOP_Y_IO //Data Converted to 16 bits #define uwCSC_TEMP uwTOP_Y //For masking operation #define udSRC_RGB16 udBOT_Y_IO //To hold the destination data that shouldn't be modified #define uwSRC_RGB16 uwBOT_Y #endif intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/RGB16x8_Save_Y416.asm000066400000000000000000000124351231401140700273350ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: RGB16x8_Save_Y416.asm // // Save packed ARGB 444 frame data block of size 16x8 // // To save 16x8 block (128x8 byte layout for ARGB 16bit per component) we need 4 send instructions // ----------------- // | 1 | 2 | 3 | 4 | // ----------------- #include "RGB16x8_Save_RGB.inc" shl (1) rMSGSRC.0<1>:d wORIX<0;1,0>:w 3:w { NoDDClr } // H. block origin need to become 8 times mov (1) rMSGSRC.1<1>:d wORIY<0;1,0>:w { NoDDClr, NoDDChk } // Block origin (1st quadrant) mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_ARGB:ud { NoDDChk } // Block width and height (32x8) mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud /* Not needed for validation kernels for now -vK //Use the mask to determine which pixels shouldn't be over-written and (1) acc0.0<1>:ud udBLOCK_MASK<0;1,0>:ud 0x00FFFFFF:ud cmp.ge.f0.0(1) dNULLREG acc0.0<0;1,0>:ud 0x00FFFFFF:ud //Check if all pixels in the block need to be modified (f0.0) jmpi WriteARGBToDataPort //If mask is not all 1's, then load the entire 64x8 block //so that only those bytes may be modified that need to be (using the mask) // Load first block 16x8 packed ARGB 444 --------------------------------------- or (1) acc0.0<1>:ud udBLOCK_MASK<0;1,0>:ud 0xFF00FF00:ud //Check first block cmp.e.f0.0 (1) dNULLREG acc0.0<0;1,0>:ud 0xFFFFFFFF:ud (f0.0) jmpi SkipFirstBlockMerge //If full mask then skip this block send (8) udSRC_ARGB(0)<1> mMSGHDR udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_ARGB+nBI_DESTINATION_RGB:ud mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud //Merge the data mov (1) f0.0:uw ubBLOCK_MASK_V:ub //Load the mask on flag reg (f0.0) mov (8) rMASK_TEMP<1>:uw uwBLOCK_MASK_H:uw //use sel instruction - vK (-f0.0) mov (8) rMASK_TEMP<1>:uw 0:uw $for(0, 0; (-f0.1) mov (8) udDEST_ARGB(%2)<1> udSRC_ARGB(%1) } SkipFirstBlockMerge: // Load second block 16x8 packed ARGB 444 --------------------------------------- or (1) acc0.0<1>:ud udBLOCK_MASK<0;1,0>:ud 0xFF0000FF:ud //Check second block cmp.e.f0.0 (1) dNULLREG acc0.0<0;1,0>:ud 0xFFFFFFFF:ud (f0.0) jmpi WriteARGBToDataPort //If full mask then skip this block add (1) mMSGHDR.0<1>:d rMSGSRC.0<0;1,0>:d 32:d // Point to 2nd part send (8) udSRC_ARGB(0)<1> mMSGHDR udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_ARGB+nBI_DESTINATION_RGB:ud mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud // Point to 1st part again //Merge the data mov (1) f0.0:uw ubBLOCK_MASK_V:ub //Load the mask on flag reg (f0.0) shr (8) rMASK_TEMP<1>:uw uwBLOCK_MASK_H:uw 8:uw //load the mask for second block (-f0.0) mov (8) rMASK_TEMP<1>:uw 0:uw $for(0, 1; (-f0.1) mov (8) udDEST_ARGB(%2)<1> udSRC_ARGB(%1) } */ WriteARGBToDataPort: // Move packed data to MRF and output //Write 1st 4X8 pixels $for(0; udDEST_ARGB(%1*4) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_ARGB+nBI_DESTINATION_RGB:ud //Write 2nd 4X8 pixels mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud add (1) mMSGHDR.0<1>:d rMSGSRC.0<0;1,0>:d 32:d // Point to 2nd part $for(0; udDEST_ARGB(%1*4+1) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_ARGB+nBI_DESTINATION_RGB:ud //Write 3rd 4X8 pixels mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud add (1) mMSGHDR.0<1>:d rMSGSRC.0<0;1,0>:d 64:d // Point to 2nd part $for(0; udDEST_ARGB(%1*4+2) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_ARGB+nBI_DESTINATION_RGB:ud //Write 4th 4X8 pixels mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud add (1) mMSGHDR.0<1>:d rMSGSRC.0<0;1,0>:d 96:d // Point to 2nd part $for(0; udDEST_ARGB(%1*4+3) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_ARGB+nBI_DESTINATION_RGB:ud // End of RGB16x8_Save_Y416 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/RGB16x8_Save_Y416.inc000066400000000000000000000030361231401140700273230ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: RGB16x8_Save_Y416.inc // #include "undefall.inc" //Undefine the SRC and DEST sysmbols // For saving #define nDPW_BLOCK_SIZE_ARGB nBLOCK_WIDTH_32+nBLOCK_HEIGHT_8 // ARGB block size 32x8 #define nDPW_MSG_SIZE_ARGB nMSGLEN_8 // # of MRF's to hold ARGB block data (8) // For masking #undef nDPR_MSG_SIZE_ARGB #define nDPR_MSG_SIZE_ARGB nRESLEN_8 // # of MRF's to hold ARGB block data (8) #define rMASK_TEMP REG(r,nTEMP0) .declare uwMASK_TEMP Base=rMASK_TEMP ElementSize=2 SrcRegion=<8;8,1> Type=uw //1 GRF #if (nSRC_REGION==nREGION_1) // For saving #define udDEST_ARGB udTOP_Y_IO //The output of previous stage is stored here; This is modified and is written to render cache //For masking operation #define udSRC_ARGB udBOT_Y_IO //To hold the destination data that shouldn't be modified #elif (nSRC_REGION==nREGION_2) // For saving #define udDEST_ARGB udBOT_Y_IO //The output of previous stage is stored here; This is modified and is written to render cache //For masking operation #define udSRC_ARGB udTOP_Y_IO //To hold the destination data that shouldn't be modified #endif intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm000077500000000000000000000051761231401140700270710ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: RGBA_Load_16x8.asm (copied from AYUV_Load_16x8.asm) //---------------------------------------------------------------- #include "RGBX_Load_16x8.inc" // In order to load 64x8 RGBA data (16x8 pixels), we need to divide the data // into two regions and load them separately. // // 32 byte 32 byte //|----------------|----------------| //| | | //| A | B |8 //| | | //| | | //|----------------|----------------| // Load the first 32x8 data block // Packed data block should be loaded as 32x8 pixel block add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Block origin shl (1) rMSGSRC.0<1>:d rMSGSRC.0<0;1,0>:w 2:w { NoDDClr } // H. block origin need to be four times larger mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_RGBA:ud { NoDDChk } // Block width and height (32x8) mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud send (8) udSRC_RGBA(0)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_RGBA+nBI_CURRENT_SRC_YUV:ud //Load the second 32x8 data block // Offset the origin X - move to next 32 colomns add (1) rMSGSRC.0<1>:d rMSGSRC.0<0;1,0>:d 32:w // Increase X origin by 8 // Size stays the same - 32x8 mov (8) mMSGHDRY<1>:ud rMSGSRC<8;8,1>:ud // Copy message description to message header send (8) udSRC_RGBA(8)<1> mMSGHDRY udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nDPR_MSG_SIZE_RGBA+nBI_CURRENT_SRC_YUV:ud // Give AYUV region addresses to address register // a0.0 is 0x38*32, a0.1 is 0x40*32. 0x40-0x38=8 (pixel) mov (1) SRC_RGBA_OFFSET<1>:ud 0x00400038*32:ud //Address registers contain starting addresses of two halves #if !defined(FIX_POINT_CONVERSION) && !defined(FLOAT_POINT_CONVERSION) //Directly move the data to destination $for(0; r[SRC_RGBA_OFFSET,%1*32+3]<8,4>:ub // A/R mov (16) uwDEST_U(%1)<1> r[SRC_RGBA_OFFSET,%1*32+2]<8,4>:ub // Y/G mov (16) uwDEST_V(%1)<1> r[SRC_RGBA_OFFSET,%1*32+1]<8,4>:ub // U/B } #endif intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc000077500000000000000000000033341231401140700270540ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #ifndef RGBA_LOAD_16X8_INC #define RGBA_LOAD_16X8_INC // Module name: RGBA_Load_16x8.inc // // RGBA data are first loaded to bottom I/O REGION_2, then does color conversion from RGB to YUV // finally, YUV data are stored in top I/O REGION_1 with planar format #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 // Number of Y rows per block #define nDPR_BLOCK_SIZE_RGBA nBLOCK_WIDTH_32+nBLOCK_HEIGHT_8 // RGBA block size 32x8 (it is half size) #define nDPR_MSG_SIZE_RGBA nRESLEN_8 // # of MRF's to hold RGBA block data (8) //Temporary storage for unpacked AYUV data #define rUNPACK_TEMP REG(r,nTEMP0) .declare udUNPACK_TEMP Base=rUNPACK_TEMP ElementSize=4 SrcRegion=<8;8,1> Type=ud //1 GRF .declare ubUNPACK_TEMP Base=rUNPACK_TEMP ElementSize=1 SrcRegion=<32;32,1> Type=ub //1 GRF .declare ubBOT_Y_IO Base=REG(r,nBOT_Y) ElementSize=1 SrcRegion=REGION(32,1) Type=ub #define udSRC_RGBA udBOT_Y_IO #define ubSRC_RGBA ubBOT_Y_IO #define nSRC_RGBA_REG nBOT_Y #define uwDEST_Y uwTOP_Y #define uwDEST_U uwTOP_U #define uwDEST_V uwTOP_V #define SRC_RGBA_OFFSET a0.0 #define SRC_RGBA_OFFSET_1 a0.0 #define SRC_RGBA_OFFSET_2 a0.1 #define nSRC_REGION nREGION_1 // REGION_1 will be the source region for first kernel // End of RGBA_Load_16x8.inc #endifintel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/RGBX_Save_YUV_Fix.asm000077500000000000000000000161471231401140700276730ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * * Authors: * Halley Zhao */ // Module name: PL16x8_PL8x4.asm //---------------------------------------------------------------- #include "RGBX_Load_16x8.inc" #if (0) #define nTEMP0 34 // transformation coefficient #define nTEMP1 35 // one row of Y (first half register is used) #define nTEMP2 36 // first half of one row #define nTEMP3 37 // second half of one row #define nTEMP4 38 // mul and add #define nTEMP5 39 // mul and add #define nTEMP6 40 // mul and add #define nTEMP7 41 // mul and add #define nTEMP8 42 // sum of mul #define nTEMP10 44 #define nTEMP12 46 #define nTEMP14 48 #define nTEMP16 50 #define nTEMP17 51 #define nTEMP18 52 #define nTEMP24 58 #endif $for(0; :uw r[SRC_RGBA_OFFSET_1, %1*32 + 0]<0; 16,1>:ub ubRGB_to_Y_Coef_Fix<0;4,1>:ub mul (16) REG2(r, nTEMP5, 0)<1>:uw r[SRC_RGBA_OFFSET_1, %1*32 + 16]<0; 16,1>:ub ubRGB_to_Y_Coef_Fix<0;4,1>:ub mul (16) REG2(r, nTEMP6, 0)<1>:uw r[SRC_RGBA_OFFSET_2, %1*32 + 0]<0; 16,1>:ub ubRGB_to_Y_Coef_Fix<0;4,1>:ub mul (16) REG2(r, nTEMP7, 0)<1>:uw r[SRC_RGBA_OFFSET_2, %1*32 + 16]<0; 16,1>:ub ubRGB_to_Y_Coef_Fix<0;4,1>:ub add (4) REG2(r, nTEMP4, 0)<4>:uw REG2(r, nTEMP4, 0)<0;4,4>:uw REG2(r, nTEMP4, 1)<0;4,4>:uw add (4) REG2(r, nTEMP5, 0)<4>:uw REG2(r, nTEMP5, 0)<0;4,4>:uw REG2(r, nTEMP5, 1)<0;4,4>:uw add (4) REG2(r, nTEMP6, 0)<4>:uw REG2(r, nTEMP6, 0)<0;4,4>:uw REG2(r, nTEMP6, 1)<0;4,4>:uw add (4) REG2(r, nTEMP7, 0)<4>:uw REG2(r, nTEMP7, 0)<0;4,4>:uw REG2(r, nTEMP7, 1)<0;4,4>:uw add (4) REG2(r, nTEMP4, 0)<4>:uw REG2(r, nTEMP4, 0)<0;4,4>:uw REG2(r, nTEMP4, 2)<0;4,4>:uw add (4) REG2(r, nTEMP5, 0)<4>:uw REG2(r, nTEMP5, 0)<0;4,4>:uw REG2(r, nTEMP5, 2)<0;4,4>:uw add (4) REG2(r, nTEMP6, 0)<4>:uw REG2(r, nTEMP6, 0)<0;4,4>:uw REG2(r, nTEMP6, 2)<0;4,4>:uw add (4) REG2(r, nTEMP7, 0)<4>:uw REG2(r, nTEMP7, 0)<0;4,4>:uw REG2(r, nTEMP7, 2)<0;4,4>:uw // #### write Y to the 1 row mov (4) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP4, 0)<0; 4, 4>:uw mov (4) REG2(r, nTEMP8, 4)<1>:uw REG2(r, nTEMP5, 0)<0; 4, 4>:uw mov (4) REG2(r, nTEMP8, 8)<1>:uw REG2(r, nTEMP6, 0)<0; 4, 4>:uw mov (4) REG2(r, nTEMP8, 12)<1>:uw REG2(r, nTEMP7, 0)<0; 4, 4>:uw add (16) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP8, 0)<0; 16, 1>:uw 0x1080:uw mov (16) REG2(r, nTEMP8, 0)<1>:ub REG2(r, nTEMP8, 1)<0; 16, 2>:ub mov (16) uwDEST_Y(%1)<1> REG2(r,nTEMP8, 0)<0;16,1>:ub // ###### do one row for U // #### mul and add mul (16) REG2(r, nTEMP4, 0)<1>:w r[SRC_RGBA_OFFSET_1, %1*32 + 0]<0; 16,1>:ub bRGB_to_U_Coef_Fix<0;4,1>:b mul (16) REG2(r, nTEMP5, 0)<1>:w r[SRC_RGBA_OFFSET_1, %1*32 + 16]<0; 16,1>:ub bRGB_to_U_Coef_Fix<0;4,1>:b mul (16) REG2(r, nTEMP6, 0)<1>:w r[SRC_RGBA_OFFSET_2, %1*32 + 0]<0; 16,1>:ub bRGB_to_U_Coef_Fix<0;4,1>:b mul (16) REG2(r, nTEMP7, 0)<1>:w r[SRC_RGBA_OFFSET_2, %1*32 + 16]<0; 16,1>:ub bRGB_to_U_Coef_Fix<0;4,1>:b add (4) REG2(r, nTEMP4, 0)<4>:w REG2(r, nTEMP4, 0)<0;4,4>:w REG2(r, nTEMP4, 1)<0;4,4>:w add (4) REG2(r, nTEMP5, 0)<4>:w REG2(r, nTEMP5, 0)<0;4,4>:w REG2(r, nTEMP5, 1)<0;4,4>:w add (4) REG2(r, nTEMP6, 0)<4>:w REG2(r, nTEMP6, 0)<0;4,4>:w REG2(r, nTEMP6, 1)<0;4,4>:w add (4) REG2(r, nTEMP7, 0)<4>:w REG2(r, nTEMP7, 0)<0;4,4>:w REG2(r, nTEMP7, 1)<0;4,4>:w add (4) REG2(r, nTEMP4, 0)<4>:w REG2(r, nTEMP4, 0)<0;4,4>:w REG2(r, nTEMP4, 2)<0;4,4>:w add (4) REG2(r, nTEMP5, 0)<4>:w REG2(r, nTEMP5, 0)<0;4,4>:w REG2(r, nTEMP5, 2)<0;4,4>:w add (4) REG2(r, nTEMP6, 0)<4>:w REG2(r, nTEMP6, 0)<0;4,4>:w REG2(r, nTEMP6, 2)<0;4,4>:w add (4) REG2(r, nTEMP7, 0)<4>:w REG2(r, nTEMP7, 0)<0;4,4>:w REG2(r, nTEMP7, 2)<0;4,4>:w // #### write U to the 1 row mov (4) REG2(r, nTEMP8, 0)<1>:w REG2(r, nTEMP4, 0)<0; 4, 4>:w mov (4) REG2(r, nTEMP8, 4)<1>:w REG2(r, nTEMP5, 0)<0; 4, 4>:w mov (4) REG2(r, nTEMP8, 8)<1>:w REG2(r, nTEMP6, 0)<0; 4, 4>:w mov (4) REG2(r, nTEMP8, 12)<1>:w REG2(r, nTEMP7, 0)<0; 4, 4>:w add (16) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP8, 0)<0; 16, 1>:w 0x8080:uw mov (16) REG2(r, nTEMP8, 0)<1>:ub REG2(r, nTEMP8, 1)<0; 16, 2>:ub mov (16) uwDEST_U(%1)<1> REG2(r,nTEMP8, 0)<0;16,1>:ub // ###### do one row for V // #### mul and add mul (16) REG2(r, nTEMP4, 0)<1>:w r[SRC_RGBA_OFFSET_1, %1*32 + 0]<0; 16,1>:ub bRGB_to_V_Coef_Fix<0;4,1>:b mul (16) REG2(r, nTEMP5, 0)<1>:w r[SRC_RGBA_OFFSET_1, %1*32 + 16]<0; 16,1>:ub bRGB_to_V_Coef_Fix<0;4,1>:b mul (16) REG2(r, nTEMP6, 0)<1>:w r[SRC_RGBA_OFFSET_2, %1*32 + 0]<0; 16,1>:ub bRGB_to_V_Coef_Fix<0;4,1>:b mul (16) REG2(r, nTEMP7, 0)<1>:w r[SRC_RGBA_OFFSET_2, %1*32 + 16]<0; 16,1>:ub bRGB_to_V_Coef_Fix<0;4,1>:b add (4) REG2(r, nTEMP4, 0)<4>:w REG2(r, nTEMP4, 0)<0;4,4>:w REG2(r, nTEMP4, 1)<0;4,4>:w add (4) REG2(r, nTEMP5, 0)<4>:w REG2(r, nTEMP5, 0)<0;4,4>:w REG2(r, nTEMP5, 1)<0;4,4>:w add (4) REG2(r, nTEMP6, 0)<4>:w REG2(r, nTEMP6, 0)<0;4,4>:w REG2(r, nTEMP6, 1)<0;4,4>:w add (4) REG2(r, nTEMP7, 0)<4>:w REG2(r, nTEMP7, 0)<0;4,4>:w REG2(r, nTEMP7, 1)<0;4,4>:w add (4) REG2(r, nTEMP4, 0)<4>:w REG2(r, nTEMP4, 0)<0;4,4>:w REG2(r, nTEMP4, 2)<0;4,4>:w add (4) REG2(r, nTEMP5, 0)<4>:w REG2(r, nTEMP5, 0)<0;4,4>:w REG2(r, nTEMP5, 2)<0;4,4>:w add (4) REG2(r, nTEMP6, 0)<4>:w REG2(r, nTEMP6, 0)<0;4,4>:w REG2(r, nTEMP6, 2)<0;4,4>:w add (4) REG2(r, nTEMP7, 0)<4>:w REG2(r, nTEMP7, 0)<0;4,4>:w REG2(r, nTEMP7, 2)<0;4,4>:w // #### write V to the 1 row mov (4) REG2(r, nTEMP8, 0)<1>:w REG2(r, nTEMP4, 0)<0; 4, 4>:w mov (4) REG2(r, nTEMP8, 4)<1>:w REG2(r, nTEMP5, 0)<0; 4, 4>:w mov (4) REG2(r, nTEMP8, 8)<1>:w REG2(r, nTEMP6, 0)<0; 4, 4>:w mov (4) REG2(r, nTEMP8, 12)<1>:w REG2(r, nTEMP7, 0)<0; 4, 4>:w add (16) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP8, 0)<0; 16, 1>:w 0x8080:uw mov (16) REG2(r, nTEMP8, 0)<1>:ub REG2(r, nTEMP8, 1)<0; 16, 2>:ub mov (16) uwDEST_V(%1)<1> REG2(r,nTEMP8, 0)<0;16,1>:ub } intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/RGBX_Save_YUV_Float.asm000077500000000000000000000222511231401140700302030ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * * Authors: * Halley Zhao */ // Module name: RGBX_Save_YUV_Float.asm //---------------------------------------------------------------- #include "RGBX_Load_16x8.inc" #if (0) // 8 grf reg for one row of pixel (2 pixel per grf) #define nTEMP0 34 #define nTEMP1 35 #define nTEMP2 36 #define nTEMP3 37 #define nTEMP4 38 #define nTEMP5 39 #define nTEMP6 40 #define nTEMP7 41 #define nTEMP8 42 // transformation coefficient #define nTEMP10 44 // transformation coefficient #define nTEMP12 46 // save Y/U/V in ub format #define nTEMP14 48 // save YUV in ud format #define nTEMP16 50 // dp4 result #define nTEMP17 51 #define nTEMP18 52 #define nTEMP24 58 #endif $for(0; :f r[SRC_RGBA_OFFSET_1,%1*32 + 0]<4,1>:ub mov (4) REG(r, nTEMP1)<1>:f r[SRC_RGBA_OFFSET_1,%1*32 + 8]<4,1>:ub mov (4) REG(r, nTEMP2)<1>:f r[SRC_RGBA_OFFSET_1,%1*32 + 16]<4,1>:ub mov (4) REG(r, nTEMP3)<1>:f r[SRC_RGBA_OFFSET_1,%1*32 + 24]<4,1>:ub mov (4) REG(r, nTEMP4)<1>:f r[SRC_RGBA_OFFSET_2,%1*32 + 0]<4,1>:ub mov (4) REG(r, nTEMP5)<1>:f r[SRC_RGBA_OFFSET_2,%1*32 + 8]<4,1>:ub mov (4) REG(r, nTEMP6)<1>:f r[SRC_RGBA_OFFSET_2,%1*32 + 16]<4,1>:ub mov (4) REG(r, nTEMP7)<1>:f r[SRC_RGBA_OFFSET_2,%1*32 + 24]<4,1>:ub mov (4) REG2(r, nTEMP0, 4)<1>:f r[SRC_RGBA_OFFSET_1,%1*32 + 4]<4,1>:ub mov (4) REG2(r, nTEMP1, 4)<1>:f r[SRC_RGBA_OFFSET_1,%1*32 + 12]<4,1>:ub mov (4) REG2(r, nTEMP2, 4)<1>:f r[SRC_RGBA_OFFSET_1,%1*32 + 20]<4,1>:ub mov (4) REG2(r, nTEMP3, 4)<1>:f r[SRC_RGBA_OFFSET_1,%1*32 + 28]<4,1>:ub mov (4) REG2(r, nTEMP4, 4)<1>:f r[SRC_RGBA_OFFSET_2,%1*32 + 4]<4,1>:ub mov (4) REG2(r, nTEMP5, 4)<1>:f r[SRC_RGBA_OFFSET_2,%1*32 + 12]<4,1>:ub mov (4) REG2(r, nTEMP6, 4)<1>:f r[SRC_RGBA_OFFSET_2,%1*32 + 20]<4,1>:ub mov (4) REG2(r, nTEMP7, 4)<1>:f r[SRC_RGBA_OFFSET_2,%1*32 + 24]<4,1>:ub // ###### do one row for Y // ##### dp4(nTEMP16) and save result to uw format(nTEMP12) dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(0, 0)<0;8,1> fRGB_to_Y_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 0)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(1, 0)<0;8,1> fRGB_to_Y_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 2)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(2, 0)<0;8,1> fRGB_to_Y_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 4)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(3, 0)<0;8,1> fRGB_to_Y_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 6)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(4, 0)<0;8,1> fRGB_to_Y_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 8)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(5, 0)<0;8,1> fRGB_to_Y_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 10)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(6, 0)<0;8,1> fRGB_to_Y_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 12)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(7, 0)<0;8,1> fRGB_to_Y_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 14)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub // #### write Y to the 1 row mov (16) uwDEST_Y(%1)<1> REG2(r,nTEMP12, 0)<0;16,1>:ub // ###### do one row for U // ##### dp4(nTEMP16) and save result to uw format(nTEMP12) dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(0, 0)<0;8,1> fRGB_to_U_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 0)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(1, 0)<0;8,1> fRGB_to_U_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 2)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(2, 0)<0;8,1> fRGB_to_U_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 4)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(3, 0)<0;8,1> fRGB_to_U_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 6)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(4, 0)<0;8,1> fRGB_to_U_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 8)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(5, 0)<0;8,1> fRGB_to_U_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 10)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(6, 0)<0;8,1> fRGB_to_U_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 12)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(7, 0)<0;8,1> fRGB_to_U_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 14)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w add (16) REG2(r, nTEMP12, 0)<1>:w REG2(r, nTEMP12, 0)<0;16,1>:w 128:w // #### write U to the 1 row mov (16) uwDEST_U(%1)<1> REG2(r,nTEMP12, 0)<0;16,2>:ub // ###### do one row for V // ##### dp4(nTEMP16) and save result to uw format(nTEMP12) dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(0, 0)<0;8,1> fRGB_to_V_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 0)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(1, 0)<0;8,1> fRGB_to_V_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 2)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(2, 0)<0;8,1> fRGB_to_V_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 4)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(3, 0)<0;8,1> fRGB_to_V_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 6)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(4, 0)<0;8,1> fRGB_to_V_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 8)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(5, 0)<0;8,1> fRGB_to_V_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 10)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(6, 0)<0;8,1> fRGB_to_V_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 12)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_BGRX(7, 0)<0;8,1> fRGB_to_V_Coef_Float<0;4,1>:f mov (2) REG2(r, nTEMP14, 0)<1>:d REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 14)<1>:w REG2(r, nTEMP14, 0)<0;2,2>:w add (16) REG2(r, nTEMP12, 0)<1>:w REG2(r, nTEMP12, 0)<0;16,1>:w 128:w // #### write V to the 1 row mov (16) uwDEST_V(%1)<1> REG2(r,nTEMP12, 0)<0;16,2>:ub } intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/RGBX_to_YUV_Coef.asm000077500000000000000000000063751231401140700275470ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * * Authors: * Halley Zhao */ // Module name: RGB_to_YUV_Coef.asm //---------------------------------------------------------------- // is src surface |R|G|B|X| layout? otherwise it is |B|G|R|X| and.nz.f0.1 (1) dNULLREG r1.1:ud 0xFF000000:ud #ifdef FIX_POINT_CONVERSION // Y = ( ( 66 * R + 129 * G + 25 * B + 128 ) >> 8) + 16 (-f0.1) mov (1) REG2(r, nTEMP0, 0):ud 0x00428119:ud // used as unsigned byte ( f0.1) mov (1) REG2(r, nTEMP0, 0):ud 0x00198142:ud // used as unsigned byte // U = ( ( -38 * R - 74 * G + 112 * B + 128 ) >> 8) + 128 (-f0.1) mov (1) REG2(r, nTEMP0, 1):ud 0x00DAB670:ud // used as signed byte ( f0.1) mov (1) REG2(r, nTEMP0, 1):ud 0x0070B6DA:ud // used as signed byte // V = ( ( 112 * R - 94 * G - 18 * B + 128 ) >> 8) + 128 (-f0.1) mov (1) REG2(r, nTEMP0, 2):ud 0x0070A2EEud // used as signed byte ( f0.1) mov (1) REG2(r, nTEMP0, 2):ud 0x00EEA270ud // used as signed byte #define ubRGB_to_Y_Coef_Fix REG2(r, nTEMP0, 0) #define bRGB_to_U_Coef_Fix REG2(r, nTEMP0, 4) #define bRGB_to_V_Coef_Fix REG2(r, nTEMP0, 8) #else // Y = 0.299R + 0.587G + 0.114B (-f0.1) mov (1) REG2(r, nTEMP8, 0):f 0.114f // B coef ( f0.1) mov (1) REG2(r, nTEMP8, 2):f 0.114f // R coef mov (1) REG2(r, nTEMP8, 1):f 0.587f // G coef (-f0.1) mov (1) REG2(r, nTEMP8, 2):f 0.299f // R coef ( f0.1) mov (1) REG2(r, nTEMP8, 0):f 0.299f // B coef mov (1) REG2(r, nTEMP8, 3):f 0.000f // A coef // Cb= -0.169R - 0.331G + 0.499B + 128 // U = -0.147R - 0.289G + 0.436B + 128 (-f0.1) mov (1) REG2(r, nTEMP8, 4):f 0.436f // B coef ( f0.1) mov (1) REG2(r, nTEMP8, 6):f 0.436f // R coef mov (1) REG2(r, nTEMP8, 5):f -0.289f // G coef (-f0.1) mov (1) REG2(r, nTEMP8, 6):f -0.147f // R coef ( f0.1) mov (1) REG2(r, nTEMP8, 4):f -0.147f // B coef mov (1) REG2(r, nTEMP8, 7):f 0.000f // A coef // Cr= 0.499R - 0.418G - 0.0813B+ 128 // V = 0.615R - 0.515G - 0.100B + 128 (-f0.1) mov (1) REG2(r, nTEMP10, 0):f -0.100f // B coef ( f0.1) mov (1) REG2(r, nTEMP10, 2):f -0.100f // R coef mov (1) REG2(r, nTEMP10, 1):f -0.515f // G coef (-f0.1) mov (1) REG2(r, nTEMP10, 2):f 0.615f // R coef ( f0.1) mov (1) REG2(r, nTEMP10, 0):f 0.615f // B coef mov (1) REG2(r, nTEMP10, 3):f 0.000f // A coef #define fRGB_to_Y_Coef_Float REG2(r, nTEMP8, 0) #define fRGB_to_U_Coef_Float REG2(r, nTEMP8, 4) #define fRGB_to_V_Coef_Float REG2(r, nTEMP10, 0) .declare fROW_BGRX Base=REG(r,nTEMP0) ElementSize=4 SrcRegion=REGION(8,8) Type=f // r nTEMP0 - r nTEMP7 #endif intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/RGB_Pack.asm000066400000000000000000000033661231401140700261460ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ .declare SRC_B Base=REG(r,10) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare SRC_G Base=REG(r,18) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare SRC_R Base=REG(r,26) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare SRC_A Base=REG(r,34) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw #define DEST_ARGB ubBOT_ARGB #undef nSRC_REGION #define nSRC_REGION nREGION_2 //Pack directly to mrf as optimization - vK $for(0, 0; <8; 1, 2) { // mov (16) DEST_ARGB(%2,0)<4> SRC_B(%1) { Compr, NoDDClr } // 16 B // mov (16) DEST_ARGB(%2,1)<4> SRC_G(%1) { Compr, NoDDClr, NoDDChk } // 16 G // mov (16) DEST_ARGB(%2,2)<4> SRC_R(%1) { Compr, NoDDClr, NoDDChk } // 16 R //these 2 inst can be merged - vK // mov (16) DEST_ARGB(%2,3)<4> SRC_A(%1) { Compr, NoDDChk } //DEST_RGB_FORMAT<0;1,0>:ub { Compr, NoDDChk } // 16 A mov (8) DEST_ARGB(%2, 0)<4> SRC_B(%1) { NoDDClr } // 8 B mov (8) DEST_ARGB(%2, 1)<4> SRC_G(%1) { NoDDClr, NoDDChk } // 8 G mov (8) DEST_ARGB(%2, 2)<4> SRC_R(%1) { NoDDClr, NoDDChk } // 8 R mov (8) DEST_ARGB(%2, 3)<4> SRC_A(%1) { NoDDChk } // 8 A mov (8) DEST_ARGB(%2+1,0)<4> SRC_B(%1,8) { NoDDClr } // 8 B mov (8) DEST_ARGB(%2+1,1)<4> SRC_G(%1,8) { NoDDClr, NoDDChk } // 8 G mov (8) DEST_ARGB(%2+1,2)<4> SRC_R(%1,8) { NoDDClr, NoDDChk } // 8 R mov (8) DEST_ARGB(%2+1,3)<4> SRC_A(%1,8) { NoDDChk } // 8 A } intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/SetupVPKernel.asm000066400000000000000000000013571231401140700273030ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: SetupVPKernel.asm // // Initial setup for running video-processing kernels // #include "common.inc" // // Now, begin source code.... // .code #include "Init_All_Regs.asm" mov (8) rMSGSRC.0<1>:ud r0.0<8;8,1>:ud // Initialize message payload header with R0 #if defined (INC_BLENDING) mul (1) fALPHA_STEP_X:f fSCALING_STEP_RATIO:f fVIDEO_STEP_X:f //StepX_ratio = AlphaStepX / VideoStepX #endif // End of SetupVPKernel intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/YUVX_Save_RGBX_Fix.asm000077500000000000000000000243601231401140700300170ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * * Authors: * Halley Zhao */ // Module name: YUVX_Save_RGBX_Fix.asm //---------------------------------------------------------------- #include "RGBX_Load_16x8.inc" #if (0) #define nTEMP0 34 // transformation coefficient #define nTEMP1 35 // one row of R (first half register is used) #define nTEMP2 36 // one row of G (first half register is used) #define nTEMP3 37 // one row of B (first half register is used) #define nTEMP4 38 // mul and add #define nTEMP5 39 // mul and add #define nTEMP6 40 // mul and add #define nTEMP7 41 // mul and add #define nTEMP8 42 // sum of mul #define nTEMP10 44 #define nTEMP10 44 // split ub pixel to word width 1st quarter #define nTEMP12 46 // split ub pixel to word width 2nd quarter #define nTEMP14 48 // split ub pixel to word width 3rd quarter #define nTEMP16 50 // split ub pixel to word width 4th quarter #define nTEMP17 51 #define nTEMP18 52 #define nTEMP24 58 // temp using for repeat U/V in NV12_Load_8x4.asm #endif #define ONE_ROW_DEBUG 0 #if (ONE_ROW_DEBUG) #define ROW_NUM 0 #define DBG_ROWNUM_BASE 1 CHANNEL_2 2 #else #define ROW_NUM %1 $for(0; :w ubDEST_RGBX(0,ROW_NUM*64 )<0;16,1> bYUV_OFF<0;4,1>:b add (16) REG2(r,nTEMP12,0)<1>:w ubDEST_RGBX(0,ROW_NUM*64+16)<0;16,1> bYUV_OFF<0;4,1>:b add (16) REG2(r,nTEMP14,0)<1>:w ubDEST_RGBX(0,ROW_NUM*64+32)<0;16,1> bYUV_OFF<0;4,1>:b add (16) REG2(r,nTEMP16,0)<1>:w ubDEST_RGBX(0,ROW_NUM*64+48)<0;16,1> bYUV_OFF<0;4,1>:b #if (ONE_ROW_DEBUG) mov (16) ubDEST_RGBX(0,(DBG_ROWNUM_BASE)*64 )<1> REG2(r,nTEMP10, 0)<0;16,2>:ub mov (16) ubDEST_RGBX(0,(DBG_ROWNUM_BASE)*64+16)<1> REG2(r,nTEMP12, 0)<0;16,2>:ub mov (16) ubDEST_RGBX(0,(DBG_ROWNUM_BASE)*64+32)<1> REG2(r,nTEMP14, 0)<0;16,2>:ub mov (16) ubDEST_RGBX(0,(DBG_ROWNUM_BASE)*64+48)<1> REG2(r,nTEMP16, 0)<0;16,2>:ub #endif // |Y|U|V|X|==>|R|G|B|X| // ###### do one row for R // #### mul and add mul.sat (16) REG2(r, nTEMP4, 0)<1>:w REG2(r,nTEMP10,0)<0;16,1>:w wYUV_to_RGB_CH2_Coef_Fix<0;4,1>:w mul.sat (16) REG2(r, nTEMP5, 0)<1>:w REG2(r,nTEMP12,0)<0;16,1>:w wYUV_to_RGB_CH2_Coef_Fix<0;4,1>:w mul.sat (16) REG2(r, nTEMP6, 0)<1>:w REG2(r,nTEMP14,0)<0;16,1>:w wYUV_to_RGB_CH2_Coef_Fix<0;4,1>:w mul.sat (16) REG2(r, nTEMP7, 0)<1>:w REG2(r,nTEMP16,0)<0;16,1>:w wYUV_to_RGB_CH2_Coef_Fix<0;4,1>:w #if (ONE_ROW_DEBUG) mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+1)*64+CHANNEL_2 )<4> bYUV_to_RGB_CH2_Coef_Fix<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+1)*64+CHANNEL_2+32)<4> bYUV_to_RGB_CH2_Coef_Fix<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+2)*64+CHANNEL_2 )<4> REG2(r,nTEMP4, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+2)*64+CHANNEL_2+32)<4> REG2(r,nTEMP4, 8)<0;8,1>:ub #endif add.sat (4) REG2(r, nTEMP4, 0)<4>:uw REG2(r, nTEMP4, 0)<0;4,4>:w REG2(r, nTEMP4, 1)<0;4,4>:w add.sat (4) REG2(r, nTEMP5, 0)<4>:uw REG2(r, nTEMP5, 0)<0;4,4>:w REG2(r, nTEMP5, 1)<0;4,4>:w add.sat (4) REG2(r, nTEMP6, 0)<4>:uw REG2(r, nTEMP6, 0)<0;4,4>:w REG2(r, nTEMP6, 1)<0;4,4>:w add.sat (4) REG2(r, nTEMP7, 0)<4>:uw REG2(r, nTEMP7, 0)<0;4,4>:w REG2(r, nTEMP7, 1)<0;4,4>:w add.sat (4) REG2(r, nTEMP4, 0)<4>:uw REG2(r, nTEMP4, 0)<0;4,4>:uw REG2(r, nTEMP4, 2)<0;4,4>:w add.sat (4) REG2(r, nTEMP5, 0)<4>:uw REG2(r, nTEMP5, 0)<0;4,4>:uw REG2(r, nTEMP5, 2)<0;4,4>:w add.sat (4) REG2(r, nTEMP6, 0)<4>:uw REG2(r, nTEMP6, 0)<0;4,4>:uw REG2(r, nTEMP6, 2)<0;4,4>:w add.sat (4) REG2(r, nTEMP7, 0)<4>:uw REG2(r, nTEMP7, 0)<0;4,4>:uw REG2(r, nTEMP7, 2)<0;4,4>:w // #### write one row of R to rnTEMP1 mov (4) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP4, 0)<0; 4, 4>:uw mov (4) REG2(r, nTEMP8, 4)<1>:uw REG2(r, nTEMP5, 0)<0; 4, 4>:uw mov (4) REG2(r, nTEMP8, 8)<1>:uw REG2(r, nTEMP6, 0)<0; 4, 4>:uw mov (4) REG2(r, nTEMP8, 12)<1>:uw REG2(r, nTEMP7, 0)<0; 4, 4>:uw #if (ONE_ROW_DEBUG) mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+3)*64+CHANNEL_2 )<4> REG2(r,nTEMP8, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+3)*64+CHANNEL_2+32)<4> REG2(r,nTEMP8, 8)<0;8,1>:ub #endif add.sat (16) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP8, 0)<0; 16, 1>:uw 0x80:uw shl.sat (16) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP8, 0)<0; 16, 1>:uw 1:w mov (16) REG2(r, nTEMP1, 0)<1>:ub REG2(r, nTEMP8, 1)<0; 16, 2>:ub #if (ONE_ROW_DEBUG) mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+4)*64+CHANNEL_2 )<4> REG2(r,nTEMP8, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+4)*64+CHANNEL_2+32)<4> REG2(r,nTEMP8, 8)<0;8,1>:ub #endif // ###### do one row for G // #### mul and add mul.sat (16) REG2(r, nTEMP4, 0)<1>:w REG2(r,nTEMP10,0)<0;16,1>:w wYUV_to_RGB_CH1_Coef_Fix<0;4,1>:w mul.sat (16) REG2(r, nTEMP5, 0)<1>:w REG2(r,nTEMP12,0)<0;16,1>:w wYUV_to_RGB_CH1_Coef_Fix<0;4,1>:w mul.sat (16) REG2(r, nTEMP6, 0)<1>:w REG2(r,nTEMP14,0)<0;16,1>:w wYUV_to_RGB_CH1_Coef_Fix<0;4,1>:w mul.sat (16) REG2(r, nTEMP7, 0)<1>:w REG2(r,nTEMP16,0)<0;16,1>:w wYUV_to_RGB_CH1_Coef_Fix<0;4,1>:w add.sat (4) REG2(r, nTEMP4, 0)<4>:uw REG2(r, nTEMP4, 0)<0;4,4>:w REG2(r, nTEMP4, 1)<0;4,4>:w add.sat (4) REG2(r, nTEMP5, 0)<4>:uw REG2(r, nTEMP5, 0)<0;4,4>:w REG2(r, nTEMP5, 1)<0;4,4>:w add.sat (4) REG2(r, nTEMP6, 0)<4>:uw REG2(r, nTEMP6, 0)<0;4,4>:w REG2(r, nTEMP6, 1)<0;4,4>:w add.sat (4) REG2(r, nTEMP7, 0)<4>:uw REG2(r, nTEMP7, 0)<0;4,4>:w REG2(r, nTEMP7, 1)<0;4,4>:w add.sat (4) REG2(r, nTEMP4, 0)<4>:uw REG2(r, nTEMP4, 0)<0;4,4>:uw REG2(r, nTEMP4, 2)<0;4,4>:w add.sat (4) REG2(r, nTEMP5, 0)<4>:uw REG2(r, nTEMP5, 0)<0;4,4>:uw REG2(r, nTEMP5, 2)<0;4,4>:w add.sat (4) REG2(r, nTEMP6, 0)<4>:uw REG2(r, nTEMP6, 0)<0;4,4>:uw REG2(r, nTEMP6, 2)<0;4,4>:w add.sat (4) REG2(r, nTEMP7, 0)<4>:uw REG2(r, nTEMP7, 0)<0;4,4>:uw REG2(r, nTEMP7, 2)<0;4,4>:w // #### write one row of G to rnTEMP2 mov (4) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP4, 0)<0; 4, 4>:uw mov (4) REG2(r, nTEMP8, 4)<1>:uw REG2(r, nTEMP5, 0)<0; 4, 4>:uw mov (4) REG2(r, nTEMP8, 8)<1>:uw REG2(r, nTEMP6, 0)<0; 4, 4>:uw mov (4) REG2(r, nTEMP8, 12)<1>:uw REG2(r, nTEMP7, 0)<0; 4, 4>:uw add (16) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP8, 0)<0; 16, 1>:uw 0x80:uw // saturation shl.sat (16) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP8, 0)<0; 16, 1>:uw 1:w mov (16) REG2(r, nTEMP2, 0)<1>:ub REG2(r, nTEMP8, 1)<0; 16, 2>:ub // ###### do one row for B // #### mul and add mul.sat (16) REG2(r, nTEMP4, 0)<1>:w REG2(r,nTEMP10,0)<0;16,1>:w wYUV_to_RGB_CH0_Coef_Fix<0;4,1>:w mul.sat (16) REG2(r, nTEMP5, 0)<1>:w REG2(r,nTEMP12,0)<0;16,1>:w wYUV_to_RGB_CH0_Coef_Fix<0;4,1>:w mul.sat (16) REG2(r, nTEMP6, 0)<1>:w REG2(r,nTEMP14,0)<0;16,1>:w wYUV_to_RGB_CH0_Coef_Fix<0;4,1>:w mul.sat (16) REG2(r, nTEMP7, 0)<1>:w REG2(r,nTEMP16,0)<0;16,1>:w wYUV_to_RGB_CH0_Coef_Fix<0;4,1>:w // I had reduced the following add because U coef is zero for B; but in order to support BGR/RGB at the same time, I have to add it back. add.sat (4) REG2(r, nTEMP4, 0)<4>:uw REG2(r, nTEMP4, 0)<0;4,4>:w REG2(r, nTEMP4, 1)<0;4,4>:w add.sat (4) REG2(r, nTEMP5, 0)<4>:uw REG2(r, nTEMP5, 0)<0;4,4>:w REG2(r, nTEMP5, 1)<0;4,4>:w add.sat (4) REG2(r, nTEMP6, 0)<4>:uw REG2(r, nTEMP6, 0)<0;4,4>:w REG2(r, nTEMP6, 1)<0;4,4>:w add.sat (4) REG2(r, nTEMP7, 0)<4>:uw REG2(r, nTEMP7, 0)<0;4,4>:w REG2(r, nTEMP7, 1)<0;4,4>:w add.sat (4) REG2(r, nTEMP4, 0)<4>:uw REG2(r, nTEMP4, 0)<0;4,4>:uw REG2(r, nTEMP4, 2)<0;4,4>:w add.sat (4) REG2(r, nTEMP5, 0)<4>:uw REG2(r, nTEMP5, 0)<0;4,4>:uw REG2(r, nTEMP5, 2)<0;4,4>:w add.sat (4) REG2(r, nTEMP6, 0)<4>:uw REG2(r, nTEMP6, 0)<0;4,4>:uw REG2(r, nTEMP6, 2)<0;4,4>:w add.sat (4) REG2(r, nTEMP7, 0)<4>:uw REG2(r, nTEMP7, 0)<0;4,4>:uw REG2(r, nTEMP7, 2)<0;4,4>:w // #### write one row of B to rnTEMP3 mov (4) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP4, 0)<0; 4, 4>:uw mov (4) REG2(r, nTEMP8, 4)<1>:uw REG2(r, nTEMP5, 0)<0; 4, 4>:uw mov (4) REG2(r, nTEMP8, 8)<1>:uw REG2(r, nTEMP6, 0)<0; 4, 4>:uw mov (4) REG2(r, nTEMP8, 12)<1>:uw REG2(r, nTEMP7, 0)<0; 4, 4>:uw add.sat (16) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP8, 0)<0; 16, 1>:uw 0x80:uw // saturation shl.sat (16) REG2(r, nTEMP8, 0)<1>:uw REG2(r, nTEMP8, 0)<0; 16, 1>:uw 1:w mov (16) REG2(r, nTEMP3, 0)<1>:ub REG2(r, nTEMP8, 1)<0; 16, 2>:ub // B mov (8) ubDEST_RGBX(0,ROW_NUM*64 )<4> REG2(r,nTEMP3, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,ROW_NUM*64+32)<4> REG2(r,nTEMP3, 8)<0;8,1>:ub // G mov (8) ubDEST_RGBX(0,ROW_NUM*64+1 )<4> REG2(r,nTEMP2, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,ROW_NUM*64+1+32)<4> REG2(r,nTEMP2, 8)<0;8,1>:ub // R mov (8) ubDEST_RGBX(0,ROW_NUM*64+2 )<4> REG2(r,nTEMP1, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,ROW_NUM*64+2+32)<4> REG2(r,nTEMP1, 8)<0;8,1>:ub #if (!ONE_ROW_DEBUG) } #endif intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/YUVX_Save_RGBX_Float.asm000077500000000000000000000404341231401140700303360ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * * Authors: * Halley Zhao */ // Module name: YUVX_Save_RGBX_Float.asm //---------------------------------------------------------------- #include "RGBX_Load_16x8.inc" #if (0) // 8 grf reg for one row of pixel (2 pixel per grf) #define nTEMP0 34 #define nTEMP1 35 #define nTEMP2 36 #define nTEMP3 37 #define nTEMP4 38 #define nTEMP5 39 #define nTEMP6 40 #define nTEMP7 41 #define nTEMP8 42 // transformation coefficient #define nTEMP10 44 // transformation coefficient #define nTEMP12 46 // save Y/U/V in ub format #define nTEMP14 48 // save YUV in ud format #define nTEMP16 50 // dp4 result #define nTEMP17 51 #define nTEMP18 52 // temp used for repeat U/V in NV12_Load_8x4.asm #define nTEMP24 58 // it is not safe to use in my case. I try to use it for repeat U/V in NV12_Load_8x4.asm, Y data is taint in row 4/5 #endif #define ONE_ROW_DEBUG 0 #if (ONE_ROW_DEBUG) // if you want to debug a row which is not the first one, try the following: // 1. define ROW_NUM_READ to the row you want to debug // 2. ROW_NUM_WRITE can be same to DBG_ROWNUM_READ to overwrite original YUV data, or define it to a new row // 3. change (DBG_ROWNUM_BASE+?)=ROW_NUM_READ or ROW_NUM_WRITE to DBG_ROWNUM_0, to not conflict with others #define ROW_NUM_READ 0 #define ROW_NUM_WRITE 0 #define DBG_ROWNUM_BASE 1 #define DBG_ROWNUM_0 0 #else #define ROW_NUM_READ %1 #define ROW_NUM_WRITE %1 $for(0; :f r[SRC_RGBA_OFFSET_1,ROW_NUM_READ*32 + 0]<4,1>:ub REG2(r, nTEMP10, 16)<0;4,1>:b add (16) REG2(r,nTEMP12,0)<1>:w ubDEST_RGBX(0,ROW_NUM_READ*64 )<0;16,1> bYUV_OFF<0;4,1>:b add (16) REG2(r,nTEMP14,0)<1>:w ubDEST_RGBX(0,ROW_NUM_READ*64+16)<0;16,1> bYUV_OFF<0;4,1>:b add (16) REG2(r,nTEMP16,0)<1>:w ubDEST_RGBX(0,ROW_NUM_READ*64+32)<0;16,1> bYUV_OFF<0;4,1>:b add (16) REG2(r,nTEMP17,0)<1>:w ubDEST_RGBX(0,ROW_NUM_READ*64+48)<0;16,1> bYUV_OFF<0;4,1>:b mov (8) fROW_YUVA(0,0)<1> REG2(r, nTEMP12, 0)<0;8,1>:w mov (8) fROW_YUVA(1,0)<1> REG2(r, nTEMP12, 8)<0;8,1>:w mov (8) fROW_YUVA(2,0)<1> REG2(r, nTEMP14, 0)<0;8,1>:w mov (8) fROW_YUVA(3,0)<1> REG2(r, nTEMP14, 8)<0;8,1>:w mov (8) fROW_YUVA(4,0)<1> REG2(r, nTEMP16, 0)<0;8,1>:w mov (8) fROW_YUVA(5,0)<1> REG2(r, nTEMP16, 8)<0;8,1>:w mov (8) fROW_YUVA(6,0)<1> REG2(r, nTEMP17, 0)<0;8,1>:w mov (8) fROW_YUVA(7,0)<1> REG2(r, nTEMP17, 8)<0;8,1>:w #if (ONE_ROW_DEBUG) mov.sat (8) REG2(r, nTEMP14, 0)<1>:ud fROW_YUVA(0,0)<0;8,1>:f mov (8) REG2(r, nTEMP12, 0)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub // write Y-16, U-128, V-128 to the 2nd row of RGB (convert float to int first, write whole ud): 1st half, 2 pixels mov (16) ubDEST_RGBX(0,(DBG_ROWNUM_BASE)*64 )<1> REG2(r,nTEMP14, 0)<0;16,1>:ub mov (16) ubDEST_RGBX(0,(DBG_ROWNUM_BASE)*64+16)<1> REG2(r,nTEMP14, 16)<0;16,1>:ub mov.sat (8) REG2(r, nTEMP14, 0)<1>:ud fROW_YUVA(1,0)<0;8,1>:f mov (8) REG2(r, nTEMP12, 8)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub // write Y-16, U-128, V-128 to the 2nd row of RGB (convert float to int first, write whole ud): 2nd half, 2 pixels mov (16) ubDEST_RGBX(0,(DBG_ROWNUM_BASE)*64+32)<1> REG2(r,nTEMP14, 0)<0;16,1>:ub mov (16) ubDEST_RGBX(0,(DBG_ROWNUM_BASE)*64+48)<1> REG2(r,nTEMP14, 16)<0;16,1>:ub mov.sat (8) REG2(r, nTEMP14, 0)<1>:ud fROW_YUVA(2,0)<0;8,1>:f mov (8) REG2(r, nTEMP12, 16)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub mov.sat (8) REG2(r, nTEMP14, 0)<1>:ud fROW_YUVA(3,0)<0;8,1>:f mov (8) REG2(r, nTEMP12, 24)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub // write Y-16, U-128, V-128 to the 3rd row of RGB (convert float to int first, only LSB is used): 1st half, 8 pixels mov (16) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+1)*64 )<1> REG2(r,nTEMP12, 0)<0;16,1>:ub mov (16) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+1)*64+16)<1> REG2(r,nTEMP12, 16)<0;16,1>:ub mov.sat (8) REG2(r, nTEMP14, 0)<1>:ud fROW_YUVA(4,0)<0;8,1>:f mov (8) REG2(r, nTEMP12, 0)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub mov.sat (8) REG2(r, nTEMP14, 0)<1>:ud fROW_YUVA(5,0)<0;8,1>:f mov (8) REG2(r, nTEMP12, 8)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub mov.sat (8) REG2(r, nTEMP14, 0)<1>:ud fROW_YUVA(6,0)<0;8,1>:f mov (8) REG2(r, nTEMP12, 16)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub mov.sat (8) REG2(r, nTEMP14, 0)<1>:ud fROW_YUVA(7,0)<0;8,1>:f mov (8) REG2(r, nTEMP12, 24)<1>:ub REG2(r, nTEMP14, 0)<0;8,4>:ub // write Y-16, U-128, V-128 to the 3rd row of RGB (convert float to int first, only LSB is used): 2nd half, 8 pixels mov (16) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+1)*64+32)<1> REG2(r,nTEMP12, 0)<0;16,1>:ub mov (16) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+1)*64+48)<1> REG2(r,nTEMP12, 16)<0;16,1>:ub #endif // ######## do one row for Red ######## #define fCOEF_REG fYUV_to_RGB_CH2_Coef_Float #define CHANNEL 2 // ##### dp4(nTEMP16) and save result to uw format(nTEMP12) dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(0, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 0)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub #if (ONE_ROW_DEBUG) // write dp4 (raw float) of 2 pixel to the 4/5th row mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+2)*64+CHANNEL )<4> REG2(r,nTEMP16, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+2)*64+CHANNEL+32)<4> REG2(r,nTEMP16, 8)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+3)*64+CHANNEL )<4> REG2(r,nTEMP16, 16)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+3)*64+CHANNEL+32)<4> REG2(r,nTEMP16, 24)<0;8,1>:ub // write dp4 (convert float to ud first, write whole ud) of 2 pixel to the 6/7th row mov (8) REG2(r, nTEMP17, 0)<1>:d REG2(r, nTEMP16, 0)<0;8,1>:f mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+4)*64+CHANNEL )<4> REG2(r,nTEMP17, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+4)*64+CHANNEL+32)<4> REG2(r,nTEMP17, 8)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+5)*64+CHANNEL )<4> REG2(r,nTEMP17, 16)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+5)*64+CHANNEL+32)<4> REG2(r,nTEMP17, 24)<0;8,1>:ub #endif dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(1, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 2)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(2, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 4)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(3, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 6)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(4, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 8)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(5, 0)<5;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 10)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(6, 0)<6;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 12)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(7, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 14)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub // #### write this channel mov (8) ubDEST_RGBX(0,ROW_NUM_WRITE*64+CHANNEL )<4> REG2(r,nTEMP12, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,ROW_NUM_WRITE*64+CHANNEL+32)<4> REG2(r,nTEMP12, 8)<0;8,1>:ub // ######## do one row for Green ######## #define fCOEF_REG fYUV_to_RGB_CH1_Coef_Float // reg for green coefficient #define CHANNEL 1 // ##### dp4(nTEMP16) and save result to uw format(nTEMP12) dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(0, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 0)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub #if (ONE_ROW_DEBUG) // write dp4 (raw float) of 2 pixel to the 4/5th row mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+2)*64+CHANNEL )<4> REG2(r,nTEMP16, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+2)*64+CHANNEL+32)<4> REG2(r,nTEMP16, 8)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+3)*64+CHANNEL )<4> REG2(r,nTEMP16, 16)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+3)*64+CHANNEL+32)<4> REG2(r,nTEMP16, 24)<0;8,1>:ub // write dp4 (convert float to ud first, write whole ud) of 2 pixel to the 6/7th row mov (8) REG2(r, nTEMP17, 0)<1>:d REG2(r, nTEMP16, 0)<0;8,1>:f mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+4)*64+CHANNEL )<4> REG2(r,nTEMP17, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+4)*64+CHANNEL+32)<4> REG2(r,nTEMP17, 8)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+5)*64+CHANNEL )<4> REG2(r,nTEMP17, 16)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+5)*64+CHANNEL+32)<4> REG2(r,nTEMP17, 24)<0;8,1>:ub #endif dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(1, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 2)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(2, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 4)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(3, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 6)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(4, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 8)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(5, 0)<5;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 10)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(6, 0)<6;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 12)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(7, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 14)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub // #### write this channel mov (8) ubDEST_RGBX(0,ROW_NUM_WRITE*64+CHANNEL )<4> REG2(r,nTEMP12, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,ROW_NUM_WRITE*64+CHANNEL+32)<4> REG2(r,nTEMP12, 8)<0;8,1>:ub // ###### do one row for Blue channel #define fCOEF_REG fYUV_to_RGB_CH0_Coef_Float // reg for Blue coefficient #define CHANNEL 0 // ##### dp4(nTEMP16) and save result to uw format(nTEMP12) dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(0, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 0)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub #if (ONE_ROW_DEBUG) // write dp4 (raw float) of 2 pixel to the 4/5th row mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+2)*64+CHANNEL )<4> REG2(r,nTEMP16, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+2)*64+CHANNEL+32)<4> REG2(r,nTEMP16, 8)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+3)*64+CHANNEL )<4> REG2(r,nTEMP16, 16)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+3)*64+CHANNEL+32)<4> REG2(r,nTEMP16, 24)<0;8,1>:ub // write dp4 (convert float to ud first, write whole ud) of 2 pixel to the 6/7th row mov (8) REG2(r, nTEMP17, 0)<1>:d REG2(r, nTEMP16, 0)<0;8,1>:f mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+4)*64+CHANNEL )<4> REG2(r,nTEMP17, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+4)*64+CHANNEL+32)<4> REG2(r,nTEMP17, 8)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+5)*64+CHANNEL )<4> REG2(r,nTEMP17, 16)<0;8,1>:ub mov (8) ubDEST_RGBX(0,(DBG_ROWNUM_BASE+5)*64+CHANNEL+32)<4> REG2(r,nTEMP17, 24)<0;8,1>:ub #endif dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(1, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 2)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(2, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 4)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(3, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 6)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(4, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 8)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(5, 0)<5;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 10)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(6, 0)<6;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 12)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub dp4 (8) REG2(r, nTEMP16, 0)<1>:f fROW_YUVA(7, 0)<0;8,1> fCOEF_REG<0;4,1>:f mov.sat (2) REG2(r, nTEMP14, 0)<1>:ud REG2(r, nTEMP16, 0)<0;2,4>:f mov (2) REG2(r, nTEMP12, 14)<1>:ub REG2(r, nTEMP14, 0)<0;2,4>:ub // #### write this channel mov (8) ubDEST_RGBX(0,ROW_NUM_WRITE*64+CHANNEL )<4> REG2(r,nTEMP12, 0)<0;8,1>:ub mov (8) ubDEST_RGBX(0,ROW_NUM_WRITE*64+CHANNEL+32)<4> REG2(r,nTEMP12, 8)<0;8,1>:ub #if (!ONE_ROW_DEBUG) } #endif intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/YUV_to_RGBX_Coef.asm000077500000000000000000000113001231401140700275270ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * * Authors: * Halley Zhao */ // Module name: YUV_to_RGBX_Coef.asm //---------------------------------------------------------------- #define ubDEST_RGBX ubTOP_Y // I'd like use them for color conversion // is dst surface |R|G|B|X| layout? otherwise, it is |B|G|R|X| layout and.nz.f0.1 (1) dNULLREG r1.2:ud 0xFF000000:ud #ifdef FIX_POINT_CONVERSION // ###### set up transformation coefficient // R = clip(( 298 * C + 0 * D + 409 * E + 128) >> 8) // R = clip((0x012A * C + 0 * D + 0x0199 * E + 128) >> 8) (-f0.1) mov (1) REG2(r, nTEMP0, 0):ud 0x0000012A:ud (-f0.1) mov (1) REG2(r, nTEMP0, 1):ud 0x00000199:ud ( f0.1) mov (1) REG2(r, nTEMP0, 4):ud 0x0000012A:ud ( f0.1) mov (1) REG2(r, nTEMP0, 5):ud 0x00000199:ud // G = clip(( 298 * C - 100 * D - 208 * E + 128) >> 8) // G = clip(( 0x012A * C - 0x64 * D - 0xD0 * E + 128) >> 8) // G = clip(( 0x012A * C + 0xFF9C * D + 0xFF30 * E + 128) >> 8) mov (1) REG2(r, nTEMP0, 2):ud 0xFF9C012A:ud mov (1) REG2(r, nTEMP0, 3):ud 0x0000FF30:ud // B = clip(( 298 * C + 516 * D + 0 * E + 128) >> 8) // B = clip((0x012A* C + 0x0204 * D + 0 * E + 128) >> 8) (-f0.1) mov (1) REG2(r, nTEMP0, 4):ud 0x0204012A:ud (-f0.1) mov (1) REG2(r, nTEMP0, 5):ud 0x00000000:ud ( f0.1) mov (1) REG2(r, nTEMP0, 0):ud 0x0204012A:ud ( f0.1) mov (1) REG2(r, nTEMP0, 1):ud 0x00000000:ud // asr.sat (24) REG2(r,nTEMP0,0)<1> REG2(r,nTEMP0,0)<0;24,1> 1:w asr.sat (8) REG2(r,nTEMP0, 0)<1>:w REG2(r,nTEMP0, 0)<0;8,1>:w 1:w asr.sat (4) REG2(r,nTEMP0,8)<1>:w REG2(r,nTEMP0,8)<0;4,1>:w 1:w // C = Y' - 16 D = U - 128 E = V - 128 mov (1) REG2(r, nTEMP0, 6):ud 0x008080F0:ud #define wYUV_to_RGB_CH2_Coef_Fix REG2(r, nTEMP0, 0) #define wYUV_to_RGB_CH1_Coef_Fix REG2(r, nTEMP0, 4) #define wYUV_to_RGB_CH0_Coef_Fix REG2(r, nTEMP0, 8) #define bYUV_OFF REG2(r,nTEMP0,24) // debug use #define bYUV_to_RGB_CH2_Coef_Fix REG2(r, nTEMP0, 0) #define bYUV_to_RGB_CH1_Coef_Fix REG2(r, nTEMP0, 8) #define bYUV_to_RGB_CH0_Coef_Fix REG2(r, nTEMP0, 16) #else // R = Y + 1.13983*V // R = clip( Y + 1.402*(Cr-128)) // ITU-R (-f0.1) mov (1) REG2(r, nTEMP8, 3):f 0.000f // A coef (-f0.1) mov (1) REG2(r, nTEMP8, 2):f 1.402f // V coef (-f0.1) mov (1) REG2(r, nTEMP8, 1):f 0.0f // U coef (-f0.1) mov (1) REG2(r, nTEMP8, 0):f 1.0f // Y coef ( f0.1) mov (1) REG2(r, nTEMP10, 3):f 0.000f // A coef ( f0.1) mov (1) REG2(r, nTEMP10, 2):f 1.402f // V coef ( f0.1) mov (1) REG2(r, nTEMP10, 1):f 0.0f // U coef ( f0.1) mov (1) REG2(r, nTEMP10, 0):f 1.0f // Y coef // G = Y - 0.39465*U - 0.58060*V // G = clip( Y - 0.344*(Cb-128) - 0.714*(Cr-128)) mov (1) REG2(r, nTEMP8, 7):f 0.000f // A coef mov (1) REG2(r, nTEMP8, 6):f -0.714f // V coef mov (1) REG2(r, nTEMP8, 5):f -0.344f // U coef mov (1) REG2(r, nTEMP8, 4):f 1.0f // Y coef // B = Y + 2.03211*U // B = clip( Y + 1.772*(Cb-128)) (-f0.1) mov (1) REG2(r, nTEMP10, 3):f 0.000f // A coef (-f0.1) mov (1) REG2(r, nTEMP10, 2):f 0.0f // V coef (-f0.1) mov (1) REG2(r, nTEMP10, 1):f 1.772f // U coef (-f0.1) mov (1) REG2(r, nTEMP10, 0):f 1.0f // Y coef ( f0.1) mov (1) REG2(r, nTEMP8, 3):f 0.000f // A coef ( f0.1) mov (1) REG2(r, nTEMP8, 2):f 0.0f // V coef ( f0.1) mov (1) REG2(r, nTEMP8, 1):f 1.772f // U coef ( f0.1) mov (1) REG2(r, nTEMP8, 0):f 1.0f // Y coef mov (1) REG2(r, nTEMP10, 4):ud 0x008080F0:ud #define fYUV_to_RGB_CH2_Coef_Float REG2(r, nTEMP8, 0) #define fYUV_to_RGB_CH1_Coef_Float REG2(r, nTEMP8, 4) #define fYUV_to_RGB_CH0_Coef_Float REG2(r, nTEMP10, 0) #define bYUV_OFF REG2(r,nTEMP10,16) .declare fROW_YUVA Base=REG(r,nTEMP0) ElementSize=4 SrcRegion=REGION(8,8) Type=f // r nTEMP0 - r nTEMP7 #endif intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/common.inc000077500000000000000000000673541231401140700260710ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #ifndef COMMON_INC #define COMMON_INC // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 80 .reg_count_payload 4 //========== Common constants ========== // Bit position constants #define BIT0 0x01 #define BIT1 0x02 #define BIT2 0x04 #define BIT3 0x08 #define BIT4 0x10 #define BIT5 0x20 #define BIT6 0x40 #define BIT7 0x80 #define BIT8 0x0100 #define BIT9 0x0200 #define BIT10 0x0400 #define BIT11 0x0800 #define BIT12 0x1000 #define BIT13 0x2000 #define BIT14 0x4000 #define BIT15 0x8000 #define BIT16 0x00010000 #define BIT17 0x00020000 #define BIT18 0x00040000 #define BIT19 0x00080000 #define BIT20 0x00100000 #define BIT21 0x00200000 #define BIT22 0x00400000 #define BIT23 0x00800000 #define BIT24 0x01000000 #define BIT25 0x02000000 #define BIT26 0x04000000 #define BIT27 0x08000000 #define BIT28 0x10000000 #define BIT29 0x20000000 #define BIT30 0x40000000 #define BIT31 0x80000000 #define nGRFWIB 32 // GRF register width in byte #define nGRFWIW 16 // GRF register width in word #define nGRFWID 8 // GRF register width in dword #define nTOP_FIELD 0 #define nBOTTOM_FIELD 1 #define nPREVIOUS_FRAME 0 // Previous frame #define nCURRENT_FRAME 1 // Current frame #define nNEXT_FRAME 2 // Next frame #ifdef GT // GT DI Kernel #else // ILK // ILK DI Kernel #endif //=================================== //========== Macros ========== #define REGION(Width,HStride) // Region definition when ExecSize = Width #define RegFile(a) a #define REG(r,n) _REG(RegFile(r),n) #define _REG(r,n) __REG(r,n) #define __REG(r,n) r##n.0 #define REG2(r,n,s) _REG2(RegFile(r),n,s) #define _REG2(r,n,s) __REG2(r,n,s) #define __REG2(r,n,s) r##n.##s #define dNULLREG null<1>:d #define wNULLREG null<1>:w #define KERNEL_ID(kernel_ID) mov NULLREG kernel_ID:ud #define NODDCLR #define NODDCLR_NODDCHK #define NODDCHK //#define NODDCLR { NoDDClr } //#define NODDCLR_NODDCHK { NoDDClr, NoDDChk } //#define NODDCHK { NoDDChk } //========== Defines ==================== //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r5 (5 GRFS) // Inline parameters : r6 - r7 (2 GRFs) // MSGSRC : r9 (1 GRF) // Top IO region : r10 - r33 (24 GRFS 8 for each component Y,U,V 16X8:w) // Free space : r34 - r55 (22 GRFS) // Bottom IO region : r56 - r79 (24 GRFS 8 for each component Y,U,V 16X8:w) //=================================== //========== Static Parameters ========== // r1 #define fPROCAMP_C0 r1.0 // DWORD 0, Procamp constant C0 in :f #define wPROCAMP_C0 r1.0 // DWORD 0, Procamp constant C0 in :w #define NUMBER_0002 r1.1 // DWORD 0, 0x0002 used in procamp for GT #define udCP_MessageFormat r1.0 // DWORD 0, bits 2:3 of DWORD. (CE) #define udCP_StatePointer r1.0 // DWORD 0, bits 31:5 of DWORD.(CE) #define ubSRC_CF_OFFSET r1.4 // DWORD 1, byte 0-2. SRC packed color format YUV offset in :ub #define ubDEST_RGB_FORMAT r1.8 // DWORD 2, byte 0. Dest RGB color format (0:ARGB FF:XRGB) #define ubDEST_CF_OFFSET r1.8 // DWORD 2, byte 0-2. Dest packed color format YUV offset in :ub #define fPROCAMP_C1 r1.3 // DWORD 3, Procamp constant C1 in :f #define wPROCAMP_C1 r1.6 // DWORD 3, Procamp constant C1 in :w #define NUMBER_0100 r1.7 // DWORD 3, 0x0100 used in procamp for GT #define fPROCAMP_C2 r1.4 // DWORD 4, Procamp constant C2 in :f #define wPROCAMP_C2 r1.8 // DWORD 4, Procamp constant C2 in :w #define uwSPITCH_DIV2 r1.10 // DWORD 5, byte 0-1. statistics surface pitch divided by 2 #define fVIDEO_STEP_Y r1.6 // DWORD 6, :f, AVS normalized reciprocal of Y Scaling factor #define ubSTMM_SHIFT r1.24 // DWORD 6, byte 0. Amount of right shift for the DI blending equation #define ubSTMM_MIN r1.25 // DWORD 6, byte 1. Min STMM for DI blending equation #define ubSTMM_MAX r1.26 // DWORD 6, byte 2. Max STMM for DI blending equation #define ubTFLD_FIRST r1.27 // DWORD 6, byte 3. Field parity order #define fPROCAMP_C5 r1.7 // DWORD 7, Procamp constant C3 in :f #define wPROCAMP_C5 r1.14 // DWORD 7, Procamp constant C3 in :w // r2 #define fPROCAMP_C3 r2.0 // DWORD 0, Procamp constant C4 in :f #define wPROCAMP_C3 r2.0 // DWORD 0, Procamp constant C4 in :w #define fCSC_C5 r2.2 // DWORD 2. WG+CSC constant C5 #define wCSC_C5 r2.4 // DWORD 2. WG+CSC constant C5 #define fPROCAMP_C4 r2.3 // DWORD 3, Procamp constant C5 in :f #define wPROCAMP_C4 r2.6 // DWORD 3, Procamp constant C5 in :w #define fCSC_C8 r2.4 // DWORD 4. WG+CSC constant C8 #define wCSC_C8 r2.8 // DWORD 4. WG+CSC constant C8 #define fCSC_C9 r2.7 // DWORD 7. WG+CSC constant C9 #define wCSC_C9 r2.14 // DWORD 7. WG+CSC constant C9 // r3 #define fCSC_C0 r3.0 // DWORD 0. WG+CSC constant C0 #define wCSC_C0 r3.0 // DWORD 0. WG+CSC constant C0 #define fSCALING_STEP_RATIO r3.1 // DWORD 1, = Alpha_X_Scaling_Step / Video_X_scaling_Step :f (blending) #define fALPHA_STEP_X r3.1 // DWORD 1, = 1/Scale X, 0.5 = 2x, in :f (blending) #define fALPHA_STEP_Y r3.2 // DWORD 2, = 1/Scale Y, in :f #define fCSC_C4 r3.3 // DWORD 3. WG+CSC constant C4 #define wCSC_C4 r3.6 // DWORD 3. WG+CSC constant C4 #define fCSC_C1 r3.4 // DWORD 4. WG+CSC constant C1 #define wCSC_C1 r3.8 // DWORD 4. WG+CSC constant C1 #define wSRC_H_ORI_OFFSET r3.10 // DWORD 5, bytes 0,1 :w #define wSRC_V_ORI_OFFSET r3.11 // DWORD 5, bytes 2,3 :w #define dCOLOR_PIXEL r3.6 // DWORD 6. Color pixel for Colorfill #define fCSC_C2 r3.6 // DWORD 6. WG+CSC constant C2 #define wCSC_C2 r3.12 // DWORD 6. WG+CSC constant C2 #define fCSC_C3 r3.7 // DWORD 7. WG+CSC constant C3 #define wCSC_C3 r3.14 // DWORD 7. WG+CSC constant C3 // r4 #define fCSC_C6 r4.0 // DWORD 0. WG+CSC constant C6 #define wCSC_C6 r4.0 // DWORD 0. WG+CSC constant C6 #define wFRAME_ENDX r4.2 // DWORD 1, word 0. Horizontal end = Origin+Width (in pixels)(for multiple blocks) #define wNUM_BLKS r4.3 // DWORD 1, word 1. Number of blocks to process (for multiple blocks) #define wCOPY_ORIX r4.5 // DWORD 2, word 1. A copy of X origin (for multiple blocks) #define uwNLAS_ENABLE r4.4 // DWORD 2, bit 15, NLAS enble bit #define fCSC_C7 r4.3 // DWORD 3. WG+CSC constant C7 #define wCSC_C7 r4.6 // DWORD 3. WG+CSC constant C7 #define fCSC_C10 r4.4 // DWORD 4. WG+CSC constant C10 #define wCSC_C10 r4.8 // DWORD 4. WG+CSC constant C10 #define fFRAME_VID_ORIX r4.5 // DWORD 5, Frame horizontal origin normalized for scale kernel #define fFRAME_ALPHA_ORIX r4.6 // DWORD 6. Normalized alpha horiz origin for the frame #define fCSC_C11 r4.7 // DWORD 7. WG+CSC constant C11 #define wCSC_C11 r4.14 // DWORD 7. WG+CSC constant C11 //======================================== //========== Inline parameters =========== // r5 #define wORIX r5.0 // DWORD 0, byte 0-1. :w, Destination Block Horizontal Origin in pel #define wORIY r5.1 // DWORD 0, byte 2-3. :w, Destination Block Vertical Origin in pel #define fSRC_VID_H_ORI r5.1 // DWORD 1, :f, SRC Y horizontal origin normalized for scale kernel #define fSRC_VID_V_ORI r5.2 // DWORD 2, :f, SRC Y vertical origin normalized for scale kernel #define fSRC_ALPHA_H_ORI r5.3 // DWORD 3, :f, Normalized alpha horizontal origin #define fSRC_ALPHA_V_ORI r5.4 // DWORD 4, :f, Normalized alpha vertical origin #define uwALPHA_MASK_X r5.10 // DWORD 5, byte 0-1 :w, H. alpha mask #define ubALPHA_MASK_Y r5.22 // DWORD 5, byte 2. :ub,V. alpha mask #define ubBLK_CNT_X r5.23 // DWORD 5, byte 3, :ub, Horizontal Block Count per thread // mask is used for each block. it will be reloaded from r6 below for the last block. #define udBLOCK_MASK r5.6 // DWORD 6 #define uwBLOCK_MASK_H r5.12 // DWORD 6, byte 0-1 :uw, Block horizontal mask used in non-DWord aligned kernels #define ubBLOCK_MASK_V r5.26 // DWORD 6, byte 2 :ub, Block vertical mask used in non-DWord aligned kernels #define ubNUM_BLKS r5.27 // DWORD 6, byte 3, :ub, Total Block Count per thread #define fVIDEO_STEP_X r5.7 // DWORD 7. :f, AVS normalized reciprocal of X Scaling factor // r6 #define fVIDEO_STEP_DELTA r6.0 // DWORD 0. :f, AVS normalized delta between 2 adjacent scaling steps (used for non-linear scaling) // mask is used for the last block (assume only M*1 and 1*N block partation aer supported) #define udBLOCK_MASK_2 r6.1 // DWORD 1 #define uwBLOCK_MASK_H_RIGHT r6.2 // DWORD 1, byte 0-1 :uw, Block horizontal mask used in non-DWord aligned kernels (right) #define ubBLOCK_MASK_V_BOTTOM r6.6 // DWORD 1, byte 2 :ub, Block vertical mask used in non-DWord aligned kernels #define uwBLOCK_MASK_H_MIDDLE r6.4 // DWORD 2, byte 0-1 :uw, Block horizontal mask used in non-DWord aligned kernels (left) //====================== Binding table ========================================= #if defined(DNDI) // DNDI Surface Binding Table //#define nBI_SRC_CURR 0 // Current input frame surface //#define nBI_SRC_PRIV 1 // Denoised previous input frame surface //#define nBI_SRC_STAT 2 // Statistics input surface (STMM / Noise motion history) //#define nBI_DEST_1ST 3 // 1st deinterlaced output frame surface // #define nBI_DEST_YUV 3 // Dest frame YUV (for DN only) //#define nBI_DEST_Y 3 // Dest frame Y (for DN only) //#define nBI_DEST_2ND 4 // 2nd deinterlaced output frame surface //#define nBI_DEST_DN_CURR 6 // Denoised current output frame surface //#define nBI_DEST_STAT 7 // Statistics output surface (STMM / Noise motion history) // #define nBI_DEST_U 8 // Dest frame U (for DN only) // #define nBI_DEST_V 9 // Dest frame V (for DN only) // #define nBI_SRC_U 10 // Src frame U (for DN only) // #define nBI_SRC_V 11 // Src frame V (for DN only) // #define nBI_SRC_UV 10 // Current src frame for UV #endif #if defined(INPUT_PL3) // PL3 Surface Binding Table // #define nBI_SRC_ALPHA 0 // Alpha // #define nBI_SRC_Y 1 // Current src frame // #define nBI_SRC_U 2 // Current src frame // #define nBI_SRC_V 3 // Current src frame // #define nBI_DEST_Y 10 // Dest frame // #define nBI_DEST_U 11 // Dest frame // #define nBI_DEST_V 12 // Dest frame // #define nBI_DEST_YUV 7 // Dest frame // #define nBI_DEST_RGB 7 // same num as BI_DEST_YUV, never used at the same time #endif #if defined(INPUT_PL2) // PL2 Surface Binding Table // #define nBI_SRC_ALPHA 0 // Alpha // #define nBI_SRC_Y 1 // Current src frame for Y + offseted UV // #define nBI_SRC_YUV 1 // Current src frame for YUV in case of NV12_AVS // #define nBI_SRC_UV 2 // Current src frame for UV // #define nBI_DEST_YUV 7 // Current dest frame for Y + offseted UV // #define nBI_DEST_RGB 7 // same num as BI_DEST_YUV, never used at the same time // #define nBI_DEST_Y 10 // Dest frame // #define nBI_DEST_U 11 // Dest frame // #define nBI_DEST_V 12 // Dest frame #endif #if defined(INPUT_PA) || defined(COLORFILL) // Packed Surface Binding Table // #define nBI_SRC_ALPHA 0 // Alpha // #define nBI_SRC_YUV 1 // Current src frame // #define nBI_DEST_YUV 3 // Dest frame // #define nBI_DEST_RGB 3 // same num as BI_DEST_YUV, never used at the same time #endif //supper binding table #define nBI_ALPHA_SRC 0 #define nBI_CURRENT_SRC_YUV 1 #define nBI_FIELD_COPY_SRC_1_YUV 1 #define nBI_CURRENT_SRC_Y 1 #define nBI_FIELD_COPY_SRC_1_Y 1 #define nBI_CURRENT_SRC_RGB 1 #define nBI_CURRENT_SRC_UV 2 #define nBI_FIELD_COPY_SRC_1_UV 2 #define nBI_CURRENT_SRC_U 2 #define nBI_FIELD_COPY_SRC_1_U 2 #define nBI_CURRENT_SRC_V 3 #define nBI_FIELD_COPY_SRC_1_V 3 #define nBI_TEMPORAL_REFERENCE_YUV 4 #define nBI_FIELD_COPY_SRC_2_YUV 4 #define nBI_TEMPORAL_REFERENCE_Y 4 #define nBI_FIELD_COPY_SRC_2_Y 4 #define nBI_CURRENT_SRC_YUV_HW_DI 4 #define nBI_TEMPORAL_REFERENCE_UV 5 #define nBI_FIELD_COPY_SRC_2_UV 5 #define nBI_TEMPORAL_REFERENCE_U 5 #define nBI_FIELD_COPY_SRC_2_U 5 #define nBI_DENOISED_PREV_HW_DI 5 #define nBI_TEMPORAL_REFERENCE_V 6 #define nBI_FIELD_COPY_SRC_2_V 6 #define nBI_STMM_HISTORY 6 #define nBI_DESTINATION_YUV 7 #define nBI_DESTINATION_RGB 7 #define nBI_DESTINATION_Y 7 #define nBI_DESTINATION_UV 8 #define nBI_DESTINATION_U 8 #define nBI_DESTINATION_V 9 #define nBI_DESTINATION_1_YUV 10 #define nBI_DESTINATION_1_Y 10 #define nBI_DESTINATION_1_UV 11 #define nBI_DESTINATION_1_U 11 #define nBI_DESTINATION_1_V 12 #define nBI_DESTINATION_2_YUV 13 #define nBI_DESTINATION_2_Y 13 #define nBI_DESTINATION_2_UV 14 #define nBI_DESTINATION_2_U 14 #define nBI_DESTINATION_2_V 15 #define nBI_STMM_HISTORY_OUTPUT 20 #define nBI_TEMPORAL_REFERENCE_YUV_PDI 21 #define nBI_TEMPORAL_REFERENCE_Y_PDI 21 #define nBI_TEMPORAL_REFERENCE_UV_PDI 22 #define nBI_TEMPORAL_REFERENCE_U_PDI 22 #define nBI_TEMPORAL_REFERENCE_V_PDI 23 #define nBI_SUBVIDEO_YUV 26 #define nBI_SUBVIDEO_Y 26 #define nBI_SUBVIDEO_UV 27 #define nBI_SUBVIDEO_U 27 #define nBI_SUBVIDEO_V 28 #define nBI_SUBPICTURE_YUV 29 #define nBI_SUBPICTURE_P8 29 #define nBI_SUBPICTURE_A8 30 #define nBI_GRAPHIC_YUV 31 #define nBI_GRAPHIC_P8 31 #define nBI_GRAPHIC_A8 32 //========== Planar Sampler State Table Index ========== #define nSI_SRC_ALPHA 0x000 // Sampler State for Alpha //Sampler Index for AVS/IEF messages #define nSI_SRC_Y 0x400 // Sampler State for Y #define nSI_SRC_U 0x800 // Sampler State for U #define nSI_SRC_V 0xC00 // Sampler State for V #define nSI_SRC_UV 0x800 // For NV12 surfaces #define nSI_SRC_YUV 0x400 // For Packed surfaces #define nSI_SRC_RGB 0x400 // For ARGB surfaces //Sampler Index for SIMD16 sampler messages #define nSI_SRC_SIMD16_Y 0x100 // Sampler State for Y #define nSI_SRC_SIMD16_U 0x200 // Sampler State for U #define nSI_SRC_SIMD16_V 0x300 // Sampler State for V #define nSI_SRC_SIMD16_UV 0x200 // For NV12 surfaces #define nSI_SRC_SIMD16_YUV 0x100 // For Packed surfaces #define nSI_SRC_SIMD16_RGB 0x100 // For ARGB surfaces // Common Registers #define pCF_Y_OFFSET a0.4 // Address register holding Y offset #define pCF_U_OFFSET a0.5 // Address register holding U offset #define pCF_V_OFFSET a0.6 // Address register holding V offset // #define YUV_ORI ORIX // Used by writing packed data to dport //================= Message Payload Header fields ============================== #define IDP r0.2:ud // Interface Descriptor Pointer //================= Common Message Descriptor TBD add common load and save ===== // Message descriptor for dataport media write #ifdef GT // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 0 1010 (media block write) 00000 // 00000000 (binding table index - set later) // = 0x02094000 #define nDPMW_MSGDSC 0x02094000 #define nDPMR_MSGDSC 0x02098000 // Data Port Media Block Read Message Descriptor // TBD #else // ILK // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 000 0 010 (media block write) 0000 // 00000000 (binding table index - set later) // = 0x02082000 #define nDPMW_MSGDSC 0x02082000 // Data Port Media Block Write Message Descriptor #define nDPMR_MSGDSC 0x0208A000 // Data Port Media Block Read Message Descriptor #endif // Message Length defines #define nMSGLEN_1 0x02000000 // Message Length of 1 GRF for Send #define nMSGLEN_2 0x04000000 // Message Length of 2 GRF for Send #define nMSGLEN_4 0x08000000 // Message Length of 4 GRF for Send #define nMSGLEN_8 0x10000000 // Message Length of 8 GRF for Send // Response Length defines #define nRESLEN_1 0x00100000 // Message Response Length of 1 GRF from Send #define nRESLEN_2 0x00200000 // Message Response Length of 2 GRF from Send #define nRESLEN_3 0x00300000 // Message Response Length of 3 GRF from Send #define nRESLEN_4 0x00400000 // Message Response Length of 4 GRF from Send #define nRESLEN_5 0x00500000 // Message Response Length of 5 GRF from Send #define nRESLEN_8 0x00800000 // Message Response Length of 8 GRF from Send #define nRESLEN_9 0x00900000 // Message Response Length of 9 GRF from Send #define nRESLEN_11 0x00B00000 // Message Response Length of 11 GRF from Send #define nRESLEN_12 0x00C00000 // Message Response Length of 12 GRF from Send #define nRESLEN_16 0x01000000 // Message Response Length of 16 GRF from Send // Block Width and Height Size defines #define nBLOCK_WIDTH_4 0x00000003 // Block Width 4 #define nBLOCK_WIDTH_5 0x00000004 // Block Width 5 #define nBLOCK_WIDTH_8 0x00000007 // Block Width 8 #define nBLOCK_WIDTH_9 0x00000008 // Block Width 9 #define nBLOCK_WIDTH_12 0x0000000B // Block Width 12 #define nBLOCK_WIDTH_16 0x0000000F // Block Width 16 #define nBLOCK_WIDTH_20 0x00000013 // Block Width 20 #define nBLOCK_WIDTH_32 0x0000001F // Block Width 32 #define nBLOCK_HEIGHT_1 0x00000000 // Block Height 1 #define nBLOCK_HEIGHT_2 0x00010000 // Block Height 2 #define nBLOCK_HEIGHT_4 0x00030000 // Block Height 4 #define nBLOCK_HEIGHT_5 0x00040000 // Block Height 5 #define nBLOCK_HEIGHT_8 0x00070000 // Block Height 8 // Extended Message Descriptors #define nEXTENDED_MATH 0x1 #define nSMPL_ENGINE 0x2 #define nMESSAGE_GATEWAY 0x3 #define nDATAPORT_READ 0x4 #define nDATAPORT_WRITE 0x5 #define nURB 0x6 #define nTS_EOT 0x27 // with End-Of-Thread bit ON // Common message descriptors: #ifdef GT #define nEOT_MSGDSC 0x02000010 // End of Thread Message Descriptor #define IF_NULL null:uw null:uw null:uw //for different if instructions on ILK and Gen6 #else //ILK #define nEOT_MSGDSC 0x02000000 // End of Thread Message Descriptor #define IF_NULL #endif //===================== Math Function Control =================================== #define mfcINV 0x1 // reciprocal #define mfcLOG 0x2 // log #define mfcEXP 0x3 // exponent #define mfcSQRT 0x4 // square root #define mfcRSQ 0x5 // reciprocal square root #define mfcSIN 0x6 // sine (in radians) #define mfcCOS 0x7 // cosine (in radians) #define mfcSINCOS 0x8 // dst0 = sin of src0, dst1 = cosine of src0 (in radians) - GT+ ONLY #define mfcPOW 0xA // abs(src0) raised to the src1 power #define mfcINT_DIV_QR 0xB // return quotient and remainder #define mfcINT_DIV_Q 0xC // return quotient #define mfcINT_DIV_R 0xD // return remainder //=================== Message related registers ================================= #ifdef GT #define udDUMMY_NULL #else // _ILK #define udDUMMY_NULL null:ud // Used in send inst as src0 #endif //----------- Message Registers ------------ #define mMSGHDR m1 // Message Payload Header #define mMSGHDRY m1 // Message Payload Header register for Y data #define mMSGHDRU m2 // Message Payload Header register for U data #define mMSGHDRV m3 // Message Payload Header register for V data #define mMSGHDRYA m4 // Second Message Payload Header register for Y data #define mMSGHDRH m5 // Message Payload Header register for motion history #define mMSGHDRY1 m1 // Message Payload Header register for first Y data #define mMSGHDRY2 m2 // Message Payload Header register for second Y data #define mMSGHDRY3 m3 // Message Payload Header register for third Y data #define mMSGHDRY4 m4 // Message Payload Header register for fourth Y data #define mMSGHDRY5 m5 // Message Payload Header register for fifth Y data #define mMSGHDRY6 m6 // Message Payload Header register for sixth Y data #define mMSGHDR_EOT m15 // Dummy Message Register for EOT #define rMSGSRC r8 // Message source register #define pMSGDSC a0.0:ud // Message Descriptor register (type DWORD) #define udMH_ORI rMSGSRC.0 // Data Port Media Block R/W message header block offset #define udMH_ORIX rMSGSRC.0 // Data Port Media Block R/W message header X offset #define udMH_ORIY rMSGSRC.1 // Data Port Media Block R/W message header Y offset #define udMH_SIZE rMSGSRC.2 // Data Port Media Block R/W message header block width & height // M2 - M9 for message data payload .declare mubMSGPAYLOAD Base=m2 ElementSize=1 SrcRegion=REGION(16,1) Type=ub .declare muwMSGPAYLOAD Base=m2 ElementSize=2 SrcRegion=REGION(16,1) Type=uw .declare mudMSGPAYLOAD Base=m2 ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare mfMSGPAYLOAD Base=m2 ElementSize=4 SrcRegion=REGION(8,1) Type=f //=================== End of thread instruction =========================== #ifdef GT #define END_THREAD mov (8) mMSGHDR_EOT<1>:ud r0.0<8;8,1>:ud \n\ send (1) null<1>:d mMSGHDR_EOT nTS_EOT nEOT_MSGDSC #else // ILK This should be changed to 1 instruction; I have tested it and it works - vK #define END_THREAD mov (8) mMSGHDR_EOT<1>:ud r0.0<8;8,1>:ud \n\ send (1) dNULLREG mMSGHDR_EOT udDUMMY_NULL nTS_EOT nEOT_MSGDSC:ud #endif //======================================================================= // Region declarations for SRC and DEST as TOP and BOT // Common I/O regions #define nREGION_1 1 #define nREGION_2 2 //*** These region base GRFs are fixed regardless planar/packed, and data alignment. //*** Each kernel is responsible to select the correct region declaration below. //*** YUV regions are not necessarily next to each other. #define nTOP_Y 10 // r10 - r17 (8 GRFs) #define nTOP_U 18 // r18 - r25 (8 GRFs) #define nTOP_V 26 // r26 - r33 (8 GRFs) #define nBOT_Y 56 // r56 - r63 (8 GRFs) #define nBOT_U 64 // r64 - r71 (8 GRFs) #define nBOT_V 72 // r72 - r79 (8 GRFs) // Define temp space for any usages #define nTEMP0 34 #define nTEMP1 35 #define nTEMP2 36 #define nTEMP3 37 #define nTEMP4 38 #define nTEMP5 39 #define nTEMP6 40 #define nTEMP7 41 #define nTEMP8 42 #define nTEMP10 44 #define nTEMP12 46 #define nTEMP14 48 #define nTEMP16 50 #define nTEMP17 51 #define nTEMP18 52 #define nTEMP24 58 // Common region 1 .declare ubTOP_Y Base=REG(r,nTOP_Y) ElementSize=1 SrcRegion=REGION(16,1) DstRegion=<1> Type=ub .declare ubTOP_U Base=REG(r,nTOP_U) ElementSize=1 SrcRegion=REGION(8,1) DstRegion=<1> Type=ub .declare ubTOP_V Base=REG(r,nTOP_V) ElementSize=1 SrcRegion=REGION(8,1) DstRegion=<1> Type=ub .declare uwTOP_Y Base=REG(r,nTOP_Y) ElementSize=2 SrcRegion=REGION(16,1) DstRegion=<1> Type=uw .declare uwTOP_U Base=REG(r,nTOP_U) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare uwTOP_V Base=REG(r,nTOP_V) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare ub2TOP_Y Base=REG(r,nTOP_Y) ElementSize=1 SrcRegion=REGION(16,2) DstRegion=<1> Type=ub .declare ub2TOP_U Base=REG(r,nTOP_U) ElementSize=1 SrcRegion=REGION(8,2) DstRegion=<1> Type=ub .declare ub2TOP_V Base=REG(r,nTOP_V) ElementSize=1 SrcRegion=REGION(8,2) DstRegion=<1> Type=ub .declare ub4TOP_Y Base=REG(r,nTOP_Y) ElementSize=1 SrcRegion=REGION(8,4) Type=ub .declare ub4TOP_U Base=REG(r,nTOP_U) ElementSize=1 SrcRegion=REGION(8,4) Type=ub .declare ub4TOP_V Base=REG(r,nTOP_V) ElementSize=1 SrcRegion=REGION(8,4) Type=ub .declare ubTOP_ARGB Base=REG(r,nTOP_Y) ElementSize=1 SrcRegion=REGION(8,4) Type=ub // Used by "send" instruction .declare udTOP_Y_IO Base=REG(r,nTOP_Y) ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare udTOP_U_IO Base=REG(r,nTOP_U) ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare udTOP_V_IO Base=REG(r,nTOP_V) ElementSize=4 SrcRegion=REGION(8,1) Type=ud // Common region 2 .declare ubBOT_Y Base=REG(r,nBOT_Y) ElementSize=1 SrcRegion=REGION(16,1) DstRegion=<1> Type=ub .declare ubBOT_U Base=REG(r,nBOT_U) ElementSize=1 SrcRegion=REGION(8,1) DstRegion=<1> Type=ub .declare ubBOT_V Base=REG(r,nBOT_V) ElementSize=1 SrcRegion=REGION(8,1) DstRegion=<1> Type=ub .declare uwBOT_Y Base=REG(r,nBOT_Y) ElementSize=2 SrcRegion=REGION(16,1) DstRegion=<1> Type=uw .declare uwBOT_U Base=REG(r,nBOT_U) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare uwBOT_V Base=REG(r,nBOT_V) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare ub2BOT_Y Base=REG(r,nBOT_Y) ElementSize=1 SrcRegion=REGION(16,2) DstRegion=<1> Type=ub .declare ub2BOT_U Base=REG(r,nBOT_U) ElementSize=1 SrcRegion=REGION(8,2) DstRegion=<1> Type=ub .declare ub2BOT_V Base=REG(r,nBOT_V) ElementSize=1 SrcRegion=REGION(8,2) DstRegion=<1> Type=ub .declare ubBOT_ARGB Base=REG(r,nBOT_Y) ElementSize=1 SrcRegion=REGION(8,4) Type=ub // Used by "send" instruction .declare udBOT_Y_IO Base=REG(r,nBOT_Y) ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare udBOT_U_IO Base=REG(r,nBOT_U) ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare udBOT_V_IO Base=REG(r,nBOT_V) ElementSize=4 SrcRegion=REGION(8,1) Type=ud // End of common.inc #endif // COMMON_INC intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/readSampler16x1.asm000066400000000000000000000031301231401140700274420ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: readSampler16x1.asm // // Read one row of pix through sampler // //#define SAMPLER_MSG_DSC 0x166A0000 // ILK Sampler Message Descriptor // Send Message [DevILK] Message Descriptor // MBZ MsgL=5 MsgR=8 H MBZ SIMD MsgType SmplrIndx BindTab // 000 0 101 0 1000 1 0 10 0000 0000 00000000 // 0 A 8 A 0 0 0 0 // MsgL=1+2*2(u,v)=5 MsgR=8 #define SAMPLER_MSG_DSC 0x0A8A0000 // ILK Sampler Message Descriptor // Assume MSGSRC is set already in the caller //mov (8) rMSGSRC.0<1>:ud 0:ud // Unused fileds // Read 16 sampled pixels and stored them in float32 in 8 GRFs // 422 data is expanded to 444, return 8 GRF in the order of RGB- (UYV-). // 420 data has three surfaces, return 8 GRF. Valid is always in the 1st GRF when in R8. Make sure no overwrite the following 3 GRFs. // alpha data is expanded to 4444, return 8 GRF in the order of RGBA (UYVA). mov(16) mMSGHDR<1>:uw rMSGSRC<16;16,1>:uw send (16) DATABUF(0)<1> mMSGHDR udDUMMY_NULL 0x2 SAMPLER_MSG_DSC+SAMPLER_IDX+BINDING_IDX:ud intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Common/undefall.inc000066400000000000000000000021421231401140700263500ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: undefall.inc // // undefine all global symbol for new process // //Source definitions #undef ubSRC_Y #undef ubSRC_U #undef ubSRC_V #undef ub2SRC_Y #undef ub2SRC_U #undef ub2SRC_V #undef ub4SRC_Y #undef ub4SRC_U #undef ub4SRC_V #undef uwSRC_Y #undef uwSRC_U #undef uwSRC_V #undef udSRC_Y #undef udSRC_U #undef udSRC_V #undef udSRC_YUV #undef nSRC_YUV_REG //Destination definitions #undef ubDEST_Y #undef ubDEST_U #undef ubDEST_V #undef ub2DEST_Y #undef ub2DEST_U #undef ub2DEST_V #undef ub4DEST_Y #undef ub4DEST_U #undef ub4DEST_V #undef uwDEST_Y #undef uwDEST_U #undef uwDEST_V #undef udDEST_Y #undef udDEST_U #undef udDEST_V #undef udDEST_YUV #undef nDEST_YUV_REG #undef ubDEST_ARGB // End of undefall.inc intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/000077500000000000000000000000001231401140700252075ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/AVS_IEF.inc000066400000000000000000000102501231401140700270140ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: AVS_IEF.inc #ifndef _AVS_INF_INC_ #define _AVS_INF_INC_ #include "undefall.inc" //Undefine the SRC and DEST sysmbols // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (V) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (U) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored #define mAVS_8x8_HDR m0 // Message Header #define mAVS_PAYLOAD m1 // Message Payload Header #define mAVS_8x8_HDR_2 m2 // Message Header #define mAVS_PAYLOAD_2 m3 // Message Payload Header #define mAVS_8x8_HDR_UV m2 // Message Header #define mAVS_PAYLOAD_UV m3 // Message Payload Header #define rAVS_8x8_HDR rMSGSRC // Mirror of Message Header #define rAVS_PAYLOAD r9 // Mirror of Message Payload Header // AVS payload // m1.7 Ignored // m1.6 Pixel 0 V Address ---> ORIY (Y0) // m1.5 Delta V ---> Step Y // m1.4 Ignored // m1.3 Ignored // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 U 2nd Derivative ---> NLAS dx // m1.0 Delta U ---> Step X // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel // 19 Header Present 1 // 18 MBZ 0 // 17:16 SIMD Mode 11 ---> SIMD64 // 15:12 Message Type 0011 ---> sample_8x8 // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx #define nAVS_MSG_DSC_1CH 0x044BB000 #define nAVS_MSG_DSC_2CH 0x048BB000 #define nAVS_MSG_DSC_3CH 0x04CBB000 #define nAVS_MSG_DSC_4CH 0x050BB000 #define nAVS_RED_CHANNEL_ONLY 0x0000E000 // Enable Red channel only #define nAVS_GREEN_CHANNEL_ONLY 0x0000D000 // Enable Green channel only #define nAVS_RED_BLUE_CHANNELS 0x0000A000 // Enable Red and Blue channels #define nAVS_RGB_CHANNELS 0x00008000 // Enable RGB(YUV) channels #define nAVS_ALL_CHANNELS 0x00000000 // Enable all channels (ARGB\AYUV) .declare ubAVS_RESPONSE Base=REG(r,nTEMP8) ElementSize=1 SrcRegion=REGION(16,1) Type=ub .declare uwAVS_RESPONSE Base=REG(r,nTEMP8) ElementSize=2 SrcRegion=REGION(16,1) Type=uw .declare ubAVS_RESPONSE_2 Base=REG(r,nTEMP24) ElementSize=1 SrcRegion=REGION(16,1) Type=ub .declare uwAVS_RESPONSE_2 Base=REG(r,nTEMP24) ElementSize=2 SrcRegion=REGION(16,1) Type=uw #if (nSRC_REGION==nREGION_2) #define uwDEST_Y uwBOT_Y #define uwDEST_U uwBOT_U #define uwDEST_V uwBOT_V #define ubDEST_Y ubBOT_Y #undef nSRC_REGION #define nSRC_REGION nREGION_2 #else //(nSRC_REGION==nREGION_1) #define uwDEST_Y uwTOP_Y #define uwDEST_U uwTOP_U #define uwDEST_V uwTOP_V #define ubDEST_Y ubTOP_Y #undef nSRC_REGION #define nSRC_REGION nREGION_1 #endif #endif //_AVS_INF_INC_ intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/AVS_SetupFirstBlock.asm000066400000000000000000000022031231401140700315020ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //------------------------------------------------------------------------------ // AVS_SetupFirstBlock.asm //------------------------------------------------------------------------------ // Setup Message Header // mov (8) mAVS_8x8_HDR<1>:ud rMSGSRC<8;8,1>:ud // Check NLAS Enable bit and.z.f0.0 (1) wNULLREG uwNLAS_ENABLE:uw BIT15:uw (f0.0)mov (1) fVIDEO_STEP_DELTA:f 0.0:f // Setup Message Payload Header for 1st block of Media Sampler 8x8 mov (1) rAVS_PAYLOAD.0:f fVIDEO_STEP_DELTA:f //NLAS dx mov (1) rAVS_PAYLOAD.1:f fVIDEO_STEP_X:f //Step X mov (1) rAVS_PAYLOAD.5:f fVIDEO_STEP_Y:f //Step Y mov (2) rAVS_PAYLOAD.2<4>:f fSRC_VID_H_ORI<2;2,1>:f //Orig X and Y intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/AVS_SetupSecondBlock.asm000066400000000000000000000021541231401140700316330ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //------------------------------------------------------------------------------ // AVS_SetupSecondBlock.asm //------------------------------------------------------------------------------ //NLAS calculations for 2nd block of Media Sampler 8x8: // X(i) = X0 + dx*i + ddx*i*(i-1)/2 ==> X(8) = X0 + dx*8 +ddx*28 // dx(i)= dx(0) + ddx*i ==> dx(8)= dx + ddx*8 // Calculating X(8) mov (1) acc0.2<1>:f fSRC_VID_H_ORI:f mac (1) acc0.2<1>:f fVIDEO_STEP_X:f 8.0:f mac (1) rAVS_PAYLOAD.2:f fVIDEO_STEP_DELTA:f 28.0:f // Calculating dx(8) mov (1) acc0.1<1>:f fVIDEO_STEP_X:f mac (1) rAVS_PAYLOAD.1:f fVIDEO_STEP_DELTA:f 8.0:f intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/DI.inc000066400000000000000000000175231231401140700262060ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: DI.inc #ifdef GT // GT DI Kernel #else // ILK // ILK DI Kernel #endif //--------------------------------------------------------------------------- // Binding table indices //--------------------------------------------------------------------------- #define nBIDX_DI_PRV 10 // Previous DI-ed frame #define nBIDX_DI_CUR 13 // Current DI-ed frame #define nBIDX_DN 7 // Denoised frame #define nBIDX_STAT 20 // Statistics #define nBIDX_DI_Source 4 // Source Surface //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor #define nSMPL_ENGINE 0x2 #define nDATAPORT_WRITE 0x5 #define nTS_EOT 0x27 // with End-Of-Thread bit ON // Message descriptor for end-of-thread // = 000 0001 (message len) 00000 (resp len) // 0 (header present 0) 00000000000000 0 (URB dereferenced) 0000 #define nEOT_MSGDSC 0x02000000 // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // comment begin // The following is commented out because of walker feature // It corresponds to the #ifdef GT #else and #endif //#define nSMPL_MSGDSC 0x040b8000 //#define nSMPL_RESP_LEN_DI 0x00c00000 // 12 //#define nSMPL_RESP_LEN_NODI_PL 0x00500000 // 5 //#define nSMPL_RESP_LEN_NODI_PA 0x00900000 // 9 //#define nSMPL_RESP_LEN_NODN 0x00900000 // 9 //#define nSMPL_RESP_LEN_PDI 0x00b00000 // 11 // comment end #ifdef GT #define nSMPL_MSGDSC 0x040b8000 #define nSMPL_RESP_LEN_DI 0x00c00000 // 12 #define nSMPL_RESP_LEN_NODI_PL 0x00500000 // 5 //DI disable, the XY stored in 5th GRF, no impact to return length #define nSMPL_RESP_LEN_NODI_PA 0x00900000 // 9 //DI disable, the XY stored in 5th GRF, no impact to return length #define nSMPL_RESP_LEN_NODN 0x00a00000 // 10 //NO DN, originally use 9, now we need use 10 to store the XY with walker #define nSMPL_RESP_LEN_PDI 0x00b00000 // 11 #else #define nSMPL_MSGDSC 0x040b8000 #define nSMPL_RESP_LEN_DI 0x00c00000 // 12 #define nSMPL_RESP_LEN_NODI_PL 0x00500000 // 5 #define nSMPL_RESP_LEN_NODI_PA 0x00900000 // 9 #define nSMPL_RESP_LEN_NODN 0x00900000 // 9 #define nSMPL_RESP_LEN_PDI 0x00b00000 // 11 #endif // Message descriptor for dataport media write #ifdef GT // = 000 0000 (message len - set later) 00000 (resp len 0) // 1 (header present 1) 0 0 1010 (media block write) 00000 // 00000000 (binding table index - set later) // = 0x00094000 #define nDPMW_MSGDSC 0x00094000 #else // ILK // = 000 0000 (message len - set later) 00000 (resp len 0) // 1 (header present 1) 000 0 010 (media block write) 0000 // 00000000 (binding table index - set later) // = 0x00082000 #define nDPMW_MSGDSC 0x00082000 #endif #define nDPMW_MSG_LEN_STMM 0x04000000 // 2 - STMM #define nDPMW_MSG_LEN_DH 0x04000000 // 2 - Denoise history #define nDPMW_MSG_LEN_PA_DN 0x0a000000 // 5 - Denoised output #define nDPMW_MSG_LEN_PA_NODI 0x12000000 // 9 - Denoised output - denoise only - DI disabled #define nDPMW_MSG_LEN_PL_DN 0x06000000 // 3 - Denoised output #define nDPMW_MSG_LEN_PL_NODI 0x0a000000 // 5 - Denoised output - denoise only - DI disabled #define nDPMW_MSG_LEN_DI 0x0a000000 // 5 - DI output //--------------------------------------------------------------------------- // Static and inline parameters //--------------------------------------------------------------------------- // Static parameters .declare ubTFLD_FIRST Base=r1.27 ElementSize=1 Type=ub // top field first .declare ubSRCYUVOFFSET Base=r1.4 ElementSize=1 Type=ub // source packed format .declare ubDSTYUVOFFSET Base=r1.8 ElementSize=1 Type=ub // destination packed format .declare uwSPITCH_DIV2 Base=r1.10 ElementSize=2 Type=uw // statistics surface pitch divided by 2 // Inline parameters .declare uwXORIGIN Base=r5.0 ElementSize=2 Type=uw // X and Y origin .declare uwYORIGIN Base=r5.1 ElementSize=2 Type=uw //--------------------------------------------------------------------------- // Kernel GRF variables //--------------------------------------------------------------------------- // Message response (Denoised & DI-ed pixels & statistics) .declare dRESP Base=r8 ElementSize=4 Type=d // Response message (12 or 5 or 11) .declare ubRESP Base=r8 ElementSize=1 Type=ub .declare dSTMM Base=r16 ElementSize=4 Type=d // STMM .declare ubDN_HIST_NODI Base=r12 ElementSize=1 Type=ub // Denoise history data (DI disabled) .declare ubDN_HIST_DI Base=r17 ElementSize=1 Type=ub // Denoise history data (DI enabled) .declare uwRETURNED_POSITION_DI Base=r17 ElementSize=2 Type=uw // XY_Return_Data (DI enabled) .declare uwRETURNED_POSITION_DN Base=r12 ElementSize=2 Type=uw // XY_Return_Data (DI disabled) .declare ub1ST_FLD_DN Base=r12 ElementSize=1 Type=ub // 1st field Denoised data (DI enabled) .declare d1ST_FLD_DN Base=r12 ElementSize=4 Type=d .declare ub2ND_FLD_DN Base=r18 ElementSize=1 Type=ub // 2nd field Denoised data (DI enabled) .declare d2ND_FLD_DN Base=r18 ElementSize=4 Type=d .declare ubPRV_DI Base=r8 ElementSize=1 Type=ub // Previous frame DI (DI enabled) .declare ubCUR_DI Base=r12 ElementSize=1 Type=ub // Previous frame DI (DI enabled) // Packed denoised output .declare ubDN_YUV Base=r22 ElementSize=1 Type=ub // Denoised YUV422 .declare dDN_YUV Base=r22 ElementSize=4 Type=d #define npDN_YUV 704 // = 22*32 = 0x280 // Packed DI output .declare dDI_YUV_PRV Base=r32 ElementSize=4 Type=d // Previous frame DI output .declare dDI_YUV_CUR Base=r36 ElementSize=4 Type=d // Current frame DI output #define npDI_YUV 1024 // = 32*32 = 0x // For packed output #define p422_YOFFSET a0.2 #define p422_UOFFSET a0.3 #define p422_VOFFSET a0.4 #define pDN_TFLDSRC a0.6 #define pDN_BFLDSRC a0.7 #define npRESP 192 // = 6*32 // Message source .declare udMSGSRC Base=r70 ElementSize=4 Type=ud .declare uwMSGSRC Base=r70 ElementSize=2 Type=uw .declare dMSGSRC Base=r70 ElementSize=4 Type=d //--------------------------------------------------------------------------- // Kernel MRF variables //--------------------------------------------------------------------------- #define mMSGHDR_SMPL m1 // Sampler response: m1~m2 .declare mudMSGHDR_SMPL Base=m1 ElementSize=4 Type=ud .declare muwMSGHDR_SMPL Base=m1 ElementSize=2 Type=uw #define mMSGHDR_DN m3 // Denoise output: m3~m7 for PA, m3~m5 for PL .declare mdMSGHDR_DN Base=m3 ElementSize=4 Type=d #define mMSGHDR_STAT m8 // Statistics output: m8~m9 .declare mdMSGHDR_STAT Base=m8 ElementSize=4 Type=d .declare mubMSGHDR_STAT Base=m8 ElementSize=1 Type=ub #define mMSGHDR_DI m10 // DI output: m10~m14 .declare mdMSGHDR_DI Base=m10 ElementSize=4 Type=d #define mMSGHDR_EOT m15 // EOT #ifdef GT #define MSGSRC #else #define MSGSRC null:ud #endif //--------------------------------------------------------------------------- // End of thread instruction //--------------------------------------------------------------------------- #ifdef GT #define END_THREAD send (8) null<1>:d mMSGHDR_EOT nTS_EOT nEOT_MSGDSC #else // ILK #define END_THREAD send (8) null<1>:d mMSGHDR_EOT null:ud nTS_EOT nEOT_MSGDSC #endif // end of DI.inc intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/DI_Hist_Save.asm000066400000000000000000000020071231401140700301510ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Write denoise history to memory shr (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w 2:w NODDCLR // X,Y origin / 4 add (1) rMSGSRC.0<1>:ud rMSGSRC.0<0;1,0>:ud uwSPITCH_DIV2<0;1,0>:uw NODDCLR_NODDCHK // Add pitch to X origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_HIST:ud NODDCHK // block width and height (4x2) mov (8) mMSGHDR_HIST<1>:ud rMSGSRC.0<8;8,1>:ud // message header mov (1) mudMSGHDR_HIST(1)<1> udRESP(nDI_HIST_OFFSET,0)<0;1,0> // Move denoise history to MRF send (8) dNULLREG mMSGHDR_HIST udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_HIST+nBI_STMM_HISTORY_OUTPUT:ud intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/DI_SAVE_PA.asm000066400000000000000000000045221231401140700274060ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ shl (1) rMSGSRC.0<1>:ud wORIX<0;1,0>:w 1:w NODDCLR // H. block origin need to be doubled mov (1) rMSGSRC.1<1>:ud wORIY<0;1,0>:w NODDCLR_NODDCHK // Block origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DI:ud NODDCHK // Block width and height (32x8) add (4) pCF_Y_OFFSET<1>:uw ubDEST_CF_OFFSET<4;4,1>:ub nDEST_YUV_REG*nGRFWIB:w // Initial Y,U,V offset in YUV422 block // Pack 2nd field Y $for(0; ubRESP(nDI_PREV_FRAME_LUMA_OFFSET,%1*16) } // Pack 1st field Y $for(0; ubRESP(nDI_CURR_FRAME_LUMA_OFFSET,%1*16) } // Pack 2nd field U $for(0; ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels } // Pack 1st field U $for(0; ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels } // Pack 2nd field V $for(0; ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //Vpixels } // Packs1st field V $for(0; ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //Vpixels } //save the previous frame mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud $for(0; <4; 1) { mov (8) mudMSGPAYLOAD(%1)<1> udDEST_YUV(%1)REGION(8,1) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_DI+nBI_DESTINATION_1_YUV:ud //save the current frame mov (8) mMSGHDR<1>:ud rMSGSRC<8;8,1>:ud $for(0; <4; 1) { mov (8) mudMSGPAYLOAD(%1)<1> udDEST_YUV(%1+4)REGION(8,1) } send (8) dNULLREG mMSGHDR udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPW_MSG_SIZE_DI+nBI_DESTINATION_2_YUV:ud intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/DNDI.inc000066400000000000000000000153011231401140700264200ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Module name: DI.inc #ifdef GT // GT DI Kernel #else // ILK // ILK DI Kernel #endif #include "undefall.inc" //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // // 1 (header present 1) 0 11 (SIMD32/64 mode) // // 1000 (message type) 0000 (DI state index) // // 00000000 (binding table index - set later) // // = 0x040b8000 #define nSMPL_DI_MSGDSC 0x040b8000 #define nSMPL_RESP_LEN_DNDI nRESLEN_12 // 12 - for DN + DI Alg #define nSMPL_RESP_LEN_DN_PL nRESLEN_5 // 5 - for DN Planar Alg #define nSMPL_RESP_LEN_DN_PA nRESLEN_9 // 9 - for DN Packed Alg #define nSMPL_RESP_LEN_DI nRESLEN_9 // 9 - for DI Only Alg #define nSMPL_RESP_LEN_PDI nRESLEN_11 // 11 - for Partial DI Alg // Attention: The Message Length is The Number of GRFs with Data Only, without the Header #define nDPMW_MSG_LEN_STMM nMSGLEN_1 // 1 - For STMM Save #define nDPMW_MSG_LEN_HIST nMSGLEN_1 // 1 - For Denoise History Save #define nDPMW_MSG_LEN_PA_DN_DI nMSGLEN_4 // 4 - For DN Curr Save #define nDPMW_MSG_LEN_PA_DN_NODI nMSGLEN_8 // 8 - For DN Curr Save (denoise only - DI disabled) #define nDPMW_MSG_LEN_PL_DN_DI nMSGLEN_2 // 2 - For DN Curr Save #define nDPMW_MSG_LEN_PL_DN_NODI nMSGLEN_4 // 4 - For DN Curr Save (denoise only - DI disabled) #define nDPW_BLOCK_SIZE_STMM nBLOCK_WIDTH_8+nBLOCK_HEIGHT_4 // Y block size 8x4 #undef nDPW_BLOCK_SIZE_DI #undef nDPW_MSG_SIZE_DI #define nDPW_BLOCK_SIZE_DI nBLOCK_WIDTH_32+nBLOCK_HEIGHT_4 #define nDPW_MSG_SIZE_DI nMSGLEN_4 //--------------------------------------------------------------------------- // Kernel GRF variables //--------------------------------------------------------------------------- // Defines for DI enabled #define nDI_PREV_FRAME_LUMA_OFFSET 0 #define nDI_PREV_FRAME_CHROMA_OFFSET 2 #define nDI_CURR_FRAME_LUMA_OFFSET 4 #define nDI_CURR_FRAME_CHROMA_OFFSET 6 #define nDI_STMM_OFFSET 8 #define nDI_HIST_OFFSET 9 #define nDI_CURR_2ND_FIELD_LUMA_OFFSET 10 #define nDI_CURR_2ND_FIELD_CHROMA_OFFSET 11 // Defines for DI disabled #define nNODI_LUMA_OFFSET 0 #define nNODI_HIST_OFFSET 4 #define nNODI_CHROMA_OFFSET 5 #ifdef DI_ENABLE #define nHIST_OFFSET nDI_HIST_OFFSET #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 // Number of Y rows per block (4 rows for each frame) #undef nUV_NUM_OF_ROWS #define nUV_NUM_OF_ROWS 8 // Number of U/V rows per block #endif #ifdef DI_DISABLE #define nHIST_OFFSET nNODI_HIST_OFFSET #endif #if (nSRC_REGION==nREGION_2) #define ub2SRC_Y ub2BOT_Y #define ub2SRC_U ub2BOT_U #define ub2SRC_V ub2BOT_V #define uwDEST_Y uwBOT_Y #define uwDEST_U uwBOT_U #define uwDEST_V uwBOT_V #define nDEST_YUV_REG nTOP_Y #define udDEST_YUV udTOP_Y_IO #define nRESP nTEMP0 // DI return message requires 12 GRFs #define nDN_YUV nTOP_Y // Space for Packing DN for next run requires 8 GRFs #undef nSRC_REGION #define nSRC_REGION nREGION_2 #else #define ub2SRC_Y ub2TOP_Y #define ub2SRC_U ub2TOP_U #define ub2SRC_V ub2TOP_V #define uwDEST_Y uwTOP_Y #define uwDEST_U uwTOP_U #define uwDEST_V uwTOP_V #define nDEST_YUV_REG nBOT_Y #define udDEST_YUV udBOT_Y_IO #define nRESP nTEMP0 // DI return message requires 12 GRFs #define nDN_YUV nBOT_Y // Space for Packing DN for next run requires 8 GRFs #undef nSRC_REGION #define nSRC_REGION nREGION_1 // REGION_1 will be the source region for first kernel #endif // Message response (Denoised & DI-ed pixels & statistics) .declare udRESP Base=REG(r,nRESP) ElementSize=4 SrcRegion=REGION(8,1) DstRegion=<1> Type=ud .declare ubRESP Base=REG(r,nRESP) ElementSize=1 SrcRegion=REGION(16,1) DstRegion=<1> Type=ub // For Denoised Curr Output (Used as Priv in Next Run) .declare ubDN_YUV Base=REG(r,nDN_YUV) ElementSize=1 Type=ub .declare udDN_YUV Base=REG(r,nDN_YUV) ElementSize=4 Type=ud #define npDN_YUV nDN_YUV*nGRFWIB // For DI Process Output (1st and 2nd Frames Output) //.declare udDI_YUV_PRIV Base=REG(r,nTEMP0) ElementSize=4 Type=ud // Previous frame DI output //.declare udDI_YUV_CURR Base=REG(r,nTEMP0) ElementSize=4 Type=ud // Current frame DI output //#define npDI_YUV nTEMP0*nGRFWIB //--------------------------------------------------------------------------- // Kernel MRF variables //--------------------------------------------------------------------------- #define mMSG_SMPL m1 // Sampler Command is in: m1~m2 .declare mudMSG_SMPL Base=mMSG_SMPL ElementSize=4 Type=ud .declare muwMSG_SMPL Base=mMSG_SMPL ElementSize=2 Type=uw #define mMSGHDR_DN m1 // Denoise Output: m1~m9 for PA, m3~m5 for PL .declare mudMSGHDR_DN Base=mMSGHDR_DN ElementSize=4 Type=ud .declare mubMSGHDR_DN Base=mMSGHDR_DN ElementSize=1 Type=ub #define mMSGHDR_STMM m11 // STMM Output: m11~m12 .declare mudMSGHDR_STMM Base=mMSGHDR_STMM ElementSize=4 Type=ud #define mMSGHDR_HIST m13 // HIST Output: m13~m14 .declare mudMSGHDR_HIST Base=mMSGHDR_HIST ElementSize=1 Type=ud #define mMSGHDR_DI_1ST m1 // DI output: m1~m5 .declare mudMSGHDR_DI_1ST Base=mMSGHDR_DI_1ST ElementSize=4 Type=ud #define mMSGHDR_DI_2ND m6 // DI output: m6~m10 .declare mudMSGHDR_DI_2ND Base=mMSGHDR_DI_2ND ElementSize=4 Type=ud // end of DNDI.inc intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/DNDI_COMMAND.asm000066400000000000000000000015401231401140700275650ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Activate the DNDI send command mov (8) mudMSG_SMPL(0)<1> rMSGSRC.0<8;8,1>:ud NODDCLR // message header mov (1) muwMSG_SMPL(1,4)<1> wORIX<0;1,0>:w NODDCLR_NODDCHK// horizontal origin mov (1) muwMSG_SMPL(1,12)<1> wORIY<0;1,0>:w NODDCLR_NODDCHK // vertical origin //mov (2) muwMSG_SMPL(1,4)<2> wORIX<2;2,1>:w NODDCHK// problem during compile !! when using this line send (8) udRESP(0)<1> mMSG_SMPL udDUMMY_NULL nSMPL_ENGINE nSMPL_DI_MSGDSC+nSMPL_RESP_LEN+nBI_CURRENT_SRC_YUV_HW_DI:ud intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/DNDI_Hist_Save.asm000066400000000000000000000020021231401140700303660ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Write denoise history to memory shr (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w 2:w NODDCLR // X,Y origin / 4 add (1) rMSGSRC.0<1>:ud rMSGSRC.0<0;1,0>:ud uwSPITCH_DIV2<0;1,0>:uw NODDCLR_NODDCHK// Add pitch to X origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_HIST:ud NODDCHK // block width and height (4x2) mov (8) mMSGHDR_HIST<1>:ud rMSGSRC.0<8;8,1>:ud // message header mov (2) mudMSGHDR_HIST(1)<1> udRESP(nNODI_HIST_OFFSET,0)<2;2,1> // Move denoise history to MRF send (8) dNULLREG mMSGHDR_HIST udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_HIST+nBI_STMM_HISTORY_OUTPUT:ud intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PA_AVS_IEF_16x8.asm000066400000000000000000000016401231401140700301740ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PA_AVS_IEF_16x8.asm ---------- #include "AVS_IEF.inc" //------------------------------------------------------------------------------ // 2 sampler reads for 8x8 YUV packed //------------------------------------------------------------------------------ #include "PA_AVS_IEF_Sample.asm" //------------------------------------------------------------------------------ // Unpacking sampler reads to 4:4:4 internal planar //------------------------------------------------------------------------------ #include "PA_AVS_IEF_Unpack_16x8.asm" //------------------------------------------------------------------------------ intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PA_AVS_IEF_8x4.asm000066400000000000000000000016341231401140700301140ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PA_AVS_IEF_8x4.asm ---------- #include "AVS_IEF.inc" //------------------------------------------------------------------------------ // 2 sampler reads for 8x8 YUV packed //------------------------------------------------------------------------------ #include "PA_AVS_IEF_Sample.asm" //------------------------------------------------------------------------------ // Unpacking sampler data to 4:2:0 internal planar //------------------------------------------------------------------------------ #include "PA_AVS_IEF_Unpack_8x4.asm" //------------------------------------------------------------------------------ intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PA_AVS_IEF_8x8.asm000066400000000000000000000016341231401140700301200ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PA_AVS_IEF_8x8.asm ---------- #include "AVS_IEF.inc" //------------------------------------------------------------------------------ // 2 sampler reads for 8x8 YUV packed //------------------------------------------------------------------------------ #include "PA_AVS_IEF_Sample.asm" //------------------------------------------------------------------------------ // Unpacking sampler data to 4:2:2 internal planar //------------------------------------------------------------------------------ #include "PA_AVS_IEF_Unpack_8x8.asm" //------------------------------------------------------------------------------ intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PA_AVS_IEF_Sample.asm000066400000000000000000000024521231401140700307110ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PA_AVS_IEF_Sample.asm ---------- //------------------------------------------------------------------------------ // 2 sampler reads for 8x8 YUV packed //------------------------------------------------------------------------------ // 1st 8x8 setup #include "AVS_SetupFirstBlock.asm" // Enable RGB(YUV) channels mov (1) rAVS_8x8_HDR.2:ud nAVS_RGB_CHANNELS:ud mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(0)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_3CH+nSI_SRC_YUV+nBI_CURRENT_SRC_YUV // Return YUV in 12 GRFs // 2nd 8x8 setup #include "AVS_SetupSecondBlock.asm" mov (16) mAVS_8x8_HDR_2.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE_2(0)<1> mAVS_8x8_HDR_2 udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_3CH+nSI_SRC_YUV+nBI_CURRENT_SRC_YUV // Return YUV in 12 GRFs intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PA_AVS_IEF_Unpack_16x8.asm000066400000000000000000000512141231401140700314770ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PA_AVS_IEF_Unpack_16x8.asm ---------- #ifdef AVS_OUTPUT_16_BIT //Output is packed in AVYU format // Move first 8x8 words of Y to dest GRF (as packed) mov (4) uwDEST_Y(0,1)<4> uwAVS_RESPONSE(2,0)<4;4,1> mov (4) uwDEST_Y(1,1)<4> uwAVS_RESPONSE(2,8)<4;4,1> mov (4) uwDEST_Y(4,1)<4> uwAVS_RESPONSE(2,4)<4;4,1> mov (4) uwDEST_Y(5,1)<4> uwAVS_RESPONSE(2,12)<4;4,1> mov (4) uwDEST_Y(8,1)<4> uwAVS_RESPONSE(3,0)<4;4,1> mov (4) uwDEST_Y(9,1)<4> uwAVS_RESPONSE(3,8)<4;4,1> mov (4) uwDEST_Y(12,1)<4> uwAVS_RESPONSE(3,4)<4;4,1> mov (4) uwDEST_Y(13,1)<4> uwAVS_RESPONSE(3,12)<4;4,1> mov (4) uwDEST_Y(16,1)<4> uwAVS_RESPONSE(8,0)<4;4,1> mov (4) uwDEST_Y(17,1)<4> uwAVS_RESPONSE(8,8)<4;4,1> mov (4) uwDEST_Y(20,1)<4> uwAVS_RESPONSE(8,4)<4;4,1> mov (4) uwDEST_Y(21,1)<4> uwAVS_RESPONSE(8,12)<4;4,1> mov (4) uwDEST_Y(24,1)<4> uwAVS_RESPONSE(9,0)<4;4,1> mov (4) uwDEST_Y(25,1)<4> uwAVS_RESPONSE(9,8)<4;4,1> mov (4) uwDEST_Y(28,1)<4> uwAVS_RESPONSE(9,4)<4;4,1> mov (4) uwDEST_Y(29,1)<4> uwAVS_RESPONSE(9,12)<4;4,1> // Move first 8x8 words of U to dest GRF (as packed) mov (4) uwDEST_Y(0,0)<4> uwAVS_RESPONSE(4,0)<4;4,1> mov (4) uwDEST_Y(1,0)<4> uwAVS_RESPONSE(4,8)<4;4,1> mov (4) uwDEST_Y(4,0)<4> uwAVS_RESPONSE(4,4)<4;4,1> mov (4) uwDEST_Y(5,0)<4> uwAVS_RESPONSE(4,12)<4;4,1> mov (4) uwDEST_Y(8,0)<4> uwAVS_RESPONSE(5,0)<4;4,1> mov (4) uwDEST_Y(9,0)<4> uwAVS_RESPONSE(5,8)<4;4,1> mov (4) uwDEST_Y(12,0)<4> uwAVS_RESPONSE(5,4)<4;4,1> mov (4) uwDEST_Y(13,0)<4> uwAVS_RESPONSE(5,12)<4;4,1> mov (4) uwDEST_Y(16,0)<4> uwAVS_RESPONSE(10,0)<4;4,1> mov (4) uwDEST_Y(17,0)<4> uwAVS_RESPONSE(10,8)<4;4,1> mov (4) uwDEST_Y(20,0)<4> uwAVS_RESPONSE(10,4)<4;4,1> mov (4) uwDEST_Y(21,0)<4> uwAVS_RESPONSE(10,12)<4;4,1> mov (4) uwDEST_Y(24,0)<4> uwAVS_RESPONSE(11,0)<4;4,1> mov (4) uwDEST_Y(25,0)<4> uwAVS_RESPONSE(11,8)<4;4,1> mov (4) uwDEST_Y(28,0)<4> uwAVS_RESPONSE(11,4)<4;4,1> mov (4) uwDEST_Y(29,0)<4> uwAVS_RESPONSE(11,12)<4;4,1> // Move first 8x8 words of V to dest GRF (as packed) mov (4) uwDEST_Y(0,2)<4> uwAVS_RESPONSE(0,0)<4;4,1> mov (4) uwDEST_Y(1,2)<4> uwAVS_RESPONSE(0,8)<4;4,1> mov (4) uwDEST_Y(4,2)<4> uwAVS_RESPONSE(0,4)<4;4,1> mov (4) uwDEST_Y(5,2)<4> uwAVS_RESPONSE(0,12)<4;4,1> mov (4) uwDEST_Y(8,2)<4> uwAVS_RESPONSE(1,0)<4;4,1> mov (4) uwDEST_Y(9,2)<4> uwAVS_RESPONSE(1,8)<4;4,1> mov (4) uwDEST_Y(12,2)<4> uwAVS_RESPONSE(1,4)<4;4,1> mov (4) uwDEST_Y(13,2)<4> uwAVS_RESPONSE(1,12)<4;4,1> mov (4) uwDEST_Y(16,2)<4> uwAVS_RESPONSE(6,0)<4;4,1> mov (4) uwDEST_Y(17,2)<4> uwAVS_RESPONSE(6,8)<4;4,1> mov (4) uwDEST_Y(20,2)<4> uwAVS_RESPONSE(6,4)<4;4,1> mov (4) uwDEST_Y(21,2)<4> uwAVS_RESPONSE(6,12)<4;4,1> mov (4) uwDEST_Y(24,2)<4> uwAVS_RESPONSE(7,0)<4;4,1> mov (4) uwDEST_Y(25,2)<4> uwAVS_RESPONSE(7,8)<4;4,1> mov (4) uwDEST_Y(28,2)<4> uwAVS_RESPONSE(7,4)<4;4,1> mov (4) uwDEST_Y(29,2)<4> uwAVS_RESPONSE(7,12)<4;4,1> // Move first 8x8 words of A to dest GRF (as packed) mov (4) uwDEST_Y(0,3)<4> 0:uw mov (4) uwDEST_Y(1,3)<4> 0:uw mov (4) uwDEST_Y(4,3)<4> 0:uw mov (4) uwDEST_Y(5,3)<4> 0:uw mov (4) uwDEST_Y(8,3)<4> 0:uw mov (4) uwDEST_Y(9,3)<4> 0:uw mov (4) uwDEST_Y(12,3)<4> 0:uw mov (4) uwDEST_Y(13,3)<4> 0:uw mov (4) uwDEST_Y(16,3)<4> 0:uw mov (4) uwDEST_Y(17,3)<4> 0:uw mov (4) uwDEST_Y(20,3)<4> 0:uw mov (4) uwDEST_Y(21,3)<4> 0:uw mov (4) uwDEST_Y(24,3)<4> 0:uw mov (4) uwDEST_Y(25,3)<4> 0:uw mov (4) uwDEST_Y(28,3)<4> 0:uw mov (4) uwDEST_Y(29,3)<4> 0:uw // Move second 8x8 words of Y to dest GRF mov (4) uwDEST_Y(2,1)<4> uwAVS_RESPONSE_2(2,0)<4;4,1> mov (4) uwDEST_Y(3,1)<4> uwAVS_RESPONSE_2(2,8)<4;4,1> mov (4) uwDEST_Y(6,1)<4> uwAVS_RESPONSE_2(2,4)<4;4,1> mov (4) uwDEST_Y(7,1)<4> uwAVS_RESPONSE_2(2,12)<4;4,1> mov (4) uwDEST_Y(10,1)<4> uwAVS_RESPONSE_2(3,0)<4;4,1> mov (4) uwDEST_Y(11,1)<4> uwAVS_RESPONSE_2(3,8)<4;4,1> mov (4) uwDEST_Y(14,1)<4> uwAVS_RESPONSE_2(3,4)<4;4,1> mov (4) uwDEST_Y(15,1)<4> uwAVS_RESPONSE_2(3,12)<4;4,1> mov (4) uwDEST_Y(18,1)<4> uwAVS_RESPONSE_2(8,0)<4;4,1> mov (4) uwDEST_Y(19,1)<4> uwAVS_RESPONSE_2(8,8)<4;4,1> mov (4) uwDEST_Y(22,1)<4> uwAVS_RESPONSE_2(8,4)<4;4,1> mov (4) uwDEST_Y(23,1)<4> uwAVS_RESPONSE_2(8,12)<4;4,1> mov (4) uwDEST_Y(26,1)<4> uwAVS_RESPONSE_2(9,0)<4;4,1> mov (4) uwDEST_Y(27,1)<4> uwAVS_RESPONSE_2(9,8)<4;4,1> mov (4) uwDEST_Y(30,1)<4> uwAVS_RESPONSE_2(9,4)<4;4,1> mov (4) uwDEST_Y(31,1)<4> uwAVS_RESPONSE_2(9,12)<4;4,1> // Move second 8x8 words of U to dest GRF mov (4) uwDEST_Y(2,0)<4> uwAVS_RESPONSE_2(4,0)<4;4,1> mov (4) uwDEST_Y(3,0)<4> uwAVS_RESPONSE_2(4,8)<4;4,1> mov (4) uwDEST_Y(6,0)<4> uwAVS_RESPONSE_2(4,4)<4;4,1> mov (4) uwDEST_Y(7,0)<4> uwAVS_RESPONSE_2(4,12)<4;4,1> mov (4) uwDEST_Y(10,0)<4> uwAVS_RESPONSE_2(5,0)<4;4,1> mov (4) uwDEST_Y(11,0)<4> uwAVS_RESPONSE_2(5,8)<4;4,1> mov (4) uwDEST_Y(14,0)<4> uwAVS_RESPONSE_2(5,4)<4;4,1> mov (4) uwDEST_Y(15,0)<4> uwAVS_RESPONSE_2(5,12)<4;4,1> mov (4) uwDEST_Y(18,0)<4> uwAVS_RESPONSE_2(10,0)<4;4,1> mov (4) uwDEST_Y(19,0)<4> uwAVS_RESPONSE_2(10,8)<4;4,1> mov (4) uwDEST_Y(22,0)<4> uwAVS_RESPONSE_2(10,4)<4;4,1> mov (4) uwDEST_Y(23,0)<4> uwAVS_RESPONSE_2(10,12)<4;4,1> mov (4) uwDEST_Y(26,0)<4> uwAVS_RESPONSE_2(11,0)<4;4,1> mov (4) uwDEST_Y(27,0)<4> uwAVS_RESPONSE_2(11,8)<4;4,1> mov (4) uwDEST_Y(30,0)<4> uwAVS_RESPONSE_2(11,4)<4;4,1> mov (4) uwDEST_Y(31,0)<4> uwAVS_RESPONSE_2(11,12)<4;4,1> // Move second 8x8 words of V to dest GRF mov (4) uwDEST_Y(2,2)<4> uwAVS_RESPONSE_2(0,0)<4;4,1> mov (4) uwDEST_Y(3,2)<4> uwAVS_RESPONSE_2(0,8)<4;4,1> mov (4) uwDEST_Y(6,2)<4> uwAVS_RESPONSE_2(0,4)<4;4,1> mov (4) uwDEST_Y(7,2)<4> uwAVS_RESPONSE_2(0,12)<4;4,1> mov (4) uwDEST_Y(10,2)<4> uwAVS_RESPONSE_2(1,0)<4;4,1> mov (4) uwDEST_Y(11,2)<4> uwAVS_RESPONSE_2(1,8)<4;4,1> mov (4) uwDEST_Y(14,2)<4> uwAVS_RESPONSE_2(1,4)<4;4,1> mov (4) uwDEST_Y(15,2)<4> uwAVS_RESPONSE_2(1,12)<4;4,1> mov (4) uwDEST_Y(18,2)<4> uwAVS_RESPONSE_2(6,0)<4;4,1> mov (4) uwDEST_Y(19,2)<4> uwAVS_RESPONSE_2(6,8)<4;4,1> mov (4) uwDEST_Y(22,2)<4> uwAVS_RESPONSE_2(6,4)<4;4,1> mov (4) uwDEST_Y(23,2)<4> uwAVS_RESPONSE_2(6,12)<4;4,1> mov (4) uwDEST_Y(26,2)<4> uwAVS_RESPONSE_2(7,0)<4;4,1> mov (4) uwDEST_Y(27,2)<4> uwAVS_RESPONSE_2(7,8)<4;4,1> mov (4) uwDEST_Y(30,2)<4> uwAVS_RESPONSE_2(7,4)<4;4,1> mov (4) uwDEST_Y(31,2)<4> uwAVS_RESPONSE_2(7,12)<4;4,1> // Move second 8x8 words of A to dest GRF mov (4) uwDEST_Y(2,3)<4> 0:uw mov (4) uwDEST_Y(3,3)<4> 0:uw mov (4) uwDEST_Y(6,3)<4> 0:uw mov (4) uwDEST_Y(7,3)<4> 0:uw mov (4) uwDEST_Y(10,3)<4> 0:uw mov (4) uwDEST_Y(11,3)<4> 0:uw mov (4) uwDEST_Y(14,3)<4> 0:uw mov (4) uwDEST_Y(15,3)<4> 0:uw mov (4) uwDEST_Y(18,3)<4> 0:uw mov (4) uwDEST_Y(19,3)<4> 0:uw mov (4) uwDEST_Y(22,3)<4> 0:uw mov (4) uwDEST_Y(23,3)<4> 0:uw mov (4) uwDEST_Y(26,3)<4> 0:uw mov (4) uwDEST_Y(27,3)<4> 0:uw mov (4) uwDEST_Y(30,3)<4> 0:uw mov (4) uwDEST_Y(31,3)<4> 0:uw /* This section will be used if 16-bit output is needed in planar format -vK // Move first 8x8 words of Y to dest GRF mov (8) uwDEST_Y(0)<1> uwAVS_RESPONSE(2,0)<8;4,1> mov (8) uwDEST_Y(1)<1> uwAVS_RESPONSE(2,8)<8;4,1> mov (8) uwDEST_Y(2)<1> uwAVS_RESPONSE(3,0)<8;4,1> mov (8) uwDEST_Y(3)<1> uwAVS_RESPONSE(3,8)<8;4,1> mov (8) uwDEST_Y(4)<1> uwAVS_RESPONSE(8,0)<8;4,1> mov (8) uwDEST_Y(5)<1> uwAVS_RESPONSE(8,8)<8;4,1> mov (8) uwDEST_Y(6)<1> uwAVS_RESPONSE(9,0)<8;4,1> mov (8) uwDEST_Y(7)<1> uwAVS_RESPONSE(9,8)<8;4,1> // Move first 8x8 words of V to dest GRF mov (8) uwDEST_V(0)<1> ubAVS_RESPONSE(0,0)<8;4,1> mov (8) uwDEST_V(1)<1> ubAVS_RESPONSE(0,8)<8;4,1> mov (8) uwDEST_V(2)<1> ubAVS_RESPONSE(1,0)<8;4,1> mov (8) uwDEST_V(3)<1> ubAVS_RESPONSE(1,8)<8;4,1> mov (8) uwDEST_V(4)<1> ubAVS_RESPONSE(6,0)<8;4,1> mov (8) uwDEST_V(5)<1> ubAVS_RESPONSE(6,8)<8;4,1> mov (8) uwDEST_V(6)<1> ubAVS_RESPONSE(7,0)<8;4,1> mov (8) uwDEST_V(7)<1> ubAVS_RESPONSE(7,8)<8;4,1> // Move first 8x8 words of U to dest GRF mov (8) uwDEST_U(0)<1> ubAVS_RESPONSE(4,0)<8;4,1> mov (8) uwDEST_U(1)<1> ubAVS_RESPONSE(4,8)<8;4,1> mov (8) uwDEST_U(2)<1> ubAVS_RESPONSE(5,0)<8;4,1> mov (8) uwDEST_U(3)<1> ubAVS_RESPONSE(5,8)<8;4,1> mov (8) uwDEST_U(4)<1> ubAVS_RESPONSE(10,0)<8;4,1> mov (8) uwDEST_U(5)<1> ubAVS_RESPONSE(10,8)<8;4,1> mov (8) uwDEST_U(6)<1> ubAVS_RESPONSE(11,0)<8;4,1> mov (8) uwDEST_U(7)<1> ubAVS_RESPONSE(11,8)<8;4,1> // Move second 8x8 words of Y to dest GRF mov (8) uwDEST_Y(0,8)<1> uwAVS_RESPONSE_2(2,0)<8;4,1> mov (8) uwDEST_Y(1,8)<1> uwAVS_RESPONSE_2(2,8)<8;4,1> mov (8) uwDEST_Y(2,8)<1> uwAVS_RESPONSE_2(3,0)<8;4,1> mov (8) uwDEST_Y(3,8)<1> uwAVS_RESPONSE_2(3,8)<8;4,1> mov (8) uwDEST_Y(4,8)<1> uwAVS_RESPONSE_2(8,0)<8;4,1> mov (8) uwDEST_Y(5,8)<1> uwAVS_RESPONSE_2(8,8)<8;4,1> mov (8) uwDEST_Y(6,8)<1> uwAVS_RESPONSE_2(9,0)<8;4,1> mov (8) uwDEST_Y(7,8)<1> uwAVS_RESPONSE_2(9,8)<8;4,1> // Move second 8x8 words of V to dest GRF mov (8) uwDEST_V(0,8)<1> ubAVS_RESPONSE_2(0,0)<8;4,1> mov (8) uwDEST_V(1,8)<1> ubAVS_RESPONSE_2(0,8)<8;4,1> mov (8) uwDEST_V(2,8)<1> ubAVS_RESPONSE_2(1,0)<8;4,1> mov (8) uwDEST_V(3,8)<1> ubAVS_RESPONSE_2(1,8)<8;4,1> mov (8) uwDEST_V(4,8)<1> ubAVS_RESPONSE_2(6,0)<8;4,1> mov (8) uwDEST_V(5,8)<1> ubAVS_RESPONSE_2(6,8)<8;4,1> mov (8) uwDEST_V(6,8)<1> ubAVS_RESPONSE_2(7,0)<8;4,1> mov (8) uwDEST_V(7,8)<1> ubAVS_RESPONSE_2(7,8)<8;4,1> // Move second 8x8 words of U to dest GRF mov (8) uwDEST_U(0,8)<1> ubAVS_RESPONSE_2(4,0)<8;4,1> mov (8) uwDEST_U(1,8)<1> ubAVS_RESPONSE_2(4,8)<8;4,1> mov (8) uwDEST_U(2,8)<1> ubAVS_RESPONSE_2(5,0)<8;4,1> mov (8) uwDEST_U(3,8)<1> ubAVS_RESPONSE_2(5,8)<8;4,1> mov (8) uwDEST_U(4,8)<1> ubAVS_RESPONSE_2(10,0)<8;4,1> mov (8) uwDEST_U(5,8)<1> ubAVS_RESPONSE_2(10,8)<8;4,1> mov (8) uwDEST_U(6,8)<1> ubAVS_RESPONSE_2(11,0)<8;4,1> mov (8) uwDEST_U(7,8)<1> ubAVS_RESPONSE_2(11,8)<8;4,1> */ #else /* OUTPUT_8_BIT */ // Move first 8x8 words of Y to dest GRF mov (8) uwDEST_Y(0)<1> ubAVS_RESPONSE(2,1)<16;4,2> mov (8) uwDEST_Y(1)<1> ubAVS_RESPONSE(2,8+1)<16;4,2> mov (8) uwDEST_Y(2)<1> ubAVS_RESPONSE(3,1)<16;4,2> mov (8) uwDEST_Y(3)<1> ubAVS_RESPONSE(3,8+1)<16;4,2> mov (8) uwDEST_Y(4)<1> ubAVS_RESPONSE(8,1)<16;4,2> mov (8) uwDEST_Y(5)<1> ubAVS_RESPONSE(8,8+1)<16;4,2> mov (8) uwDEST_Y(6)<1> ubAVS_RESPONSE(9,1)<16;4,2> mov (8) uwDEST_Y(7)<1> ubAVS_RESPONSE(9,8+1)<16;4,2> // Move first 8x8 words of V to dest GRF mov (8) uwDEST_V(0)<1> ubAVS_RESPONSE(0,1)<16;4,2> mov (8) uwDEST_V(1)<1> ubAVS_RESPONSE(0,8+1)<16;4,2> mov (8) uwDEST_V(2)<1> ubAVS_RESPONSE(1,1)<16;4,2> mov (8) uwDEST_V(3)<1> ubAVS_RESPONSE(1,8+1)<16;4,2> mov (8) uwDEST_V(4)<1> ubAVS_RESPONSE(6,1)<16;4,2> mov (8) uwDEST_V(5)<1> ubAVS_RESPONSE(6,8+1)<16;4,2> mov (8) uwDEST_V(6)<1> ubAVS_RESPONSE(7,1)<16;4,2> mov (8) uwDEST_V(7)<1> ubAVS_RESPONSE(7,8+1)<16;4,2> // Move first 8x8 words of U to dest GRF mov (8) uwDEST_U(0)<1> ubAVS_RESPONSE(4,1)<16;4,2> mov (8) uwDEST_U(1)<1> ubAVS_RESPONSE(4,8+1)<16;4,2> mov (8) uwDEST_U(2)<1> ubAVS_RESPONSE(5,1)<16;4,2> mov (8) uwDEST_U(3)<1> ubAVS_RESPONSE(5,8+1)<16;4,2> mov (8) uwDEST_U(4)<1> ubAVS_RESPONSE(10,1)<16;4,2> mov (8) uwDEST_U(5)<1> ubAVS_RESPONSE(10,8+1)<16;4,2> mov (8) uwDEST_U(6)<1> ubAVS_RESPONSE(11,1)<16;4,2> mov (8) uwDEST_U(7)<1> ubAVS_RESPONSE(11,8+1)<16;4,2> // Move second 8x8 words of Y to dest GRF mov (8) uwDEST_Y(0,8)<1> ubAVS_RESPONSE_2(2,1)<16;4,2> mov (8) uwDEST_Y(1,8)<1> ubAVS_RESPONSE_2(2,8+1)<16;4,2> mov (8) uwDEST_Y(2,8)<1> ubAVS_RESPONSE_2(3,1)<16;4,2> mov (8) uwDEST_Y(3,8)<1> ubAVS_RESPONSE_2(3,8+1)<16;4,2> mov (8) uwDEST_Y(4,8)<1> ubAVS_RESPONSE_2(8,1)<16;4,2> mov (8) uwDEST_Y(5,8)<1> ubAVS_RESPONSE_2(8,8+1)<16;4,2> mov (8) uwDEST_Y(6,8)<1> ubAVS_RESPONSE_2(9,1)<16;4,2> mov (8) uwDEST_Y(7,8)<1> ubAVS_RESPONSE_2(9,8+1)<16;4,2> // Move second 8x8 words of V to dest GRF mov (8) uwDEST_V(0,8)<1> ubAVS_RESPONSE_2(0,1)<16;4,2> mov (8) uwDEST_V(1,8)<1> ubAVS_RESPONSE_2(0,8+1)<16;4,2> mov (8) uwDEST_V(2,8)<1> ubAVS_RESPONSE_2(1,1)<16;4,2> mov (8) uwDEST_V(3,8)<1> ubAVS_RESPONSE_2(1,8+1)<16;4,2> mov (8) uwDEST_V(4,8)<1> ubAVS_RESPONSE_2(6,1)<16;4,2> mov (8) uwDEST_V(5,8)<1> ubAVS_RESPONSE_2(6,8+1)<16;4,2> mov (8) uwDEST_V(6,8)<1> ubAVS_RESPONSE_2(7,1)<16;4,2> mov (8) uwDEST_V(7,8)<1> ubAVS_RESPONSE_2(7,8+1)<16;4,2> // Move second 8x8 words of U to dest GRF mov (8) uwDEST_U(0,8)<1> ubAVS_RESPONSE_2(4,1)<16;4,2> mov (8) uwDEST_U(1,8)<1> ubAVS_RESPONSE_2(4,8+1)<16;4,2> mov (8) uwDEST_U(2,8)<1> ubAVS_RESPONSE_2(5,1)<16;4,2> mov (8) uwDEST_U(3,8)<1> ubAVS_RESPONSE_2(5,8+1)<16;4,2> mov (8) uwDEST_U(4,8)<1> ubAVS_RESPONSE_2(10,1)<16;4,2> mov (8) uwDEST_U(5,8)<1> ubAVS_RESPONSE_2(10,8+1)<16;4,2> mov (8) uwDEST_U(6,8)<1> ubAVS_RESPONSE_2(11,1)<16;4,2> mov (8) uwDEST_U(7,8)<1> ubAVS_RESPONSE_2(11,8+1)<16;4,2> #endif //------------------------------------------------------------------------------ // Re-define new number of lines #undef nUV_NUM_OF_ROWS #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 #define nUV_NUM_OF_ROWS 8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PA_AVS_IEF_Unpack_8x4.asm000066400000000000000000000066361231401140700314240ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PA_AVS_IEF_Unpack_8x8.asm ---------- // Yoni: In order to optimize unpacking, 3 methods are being checked: // 1. AVS_ORIGINAL // 2. AVS_ROUND_TO_8_BITS // 3. AVS_INDIRECT_ACCESS // // Only 1 method should stay in the code //#define AVS_ROUND_TO_8_BITS //#define AVS_INDIRECT_ACCESS // Move first 8x8 words of Y to dest GRF mov (8) uwDEST_Y(0)<1> ubAVS_RESPONSE(2,1)<16;4,2> mov (8) uwDEST_Y(1)<1> ubAVS_RESPONSE(2,8+1)<16;4,2> mov (8) uwDEST_Y(2)<1> ubAVS_RESPONSE(3,1)<16;4,2> mov (8) uwDEST_Y(3)<1> ubAVS_RESPONSE(3,8+1)<16;4,2> mov (8) uwDEST_Y(4)<1> ubAVS_RESPONSE(8,1)<16;4,2> mov (8) uwDEST_Y(5)<1> ubAVS_RESPONSE(8,8+1)<16;4,2> mov (8) uwDEST_Y(6)<1> ubAVS_RESPONSE(9,1)<16;4,2> mov (8) uwDEST_Y(7)<1> ubAVS_RESPONSE(9,8+1)<16;4,2> // Move first 4x8 words of V to dest GRF mov (4) uwDEST_V(0)<1> ubAVS_RESPONSE(0,1)<16;2,4> mov (4) uwDEST_V(0,8)<1> ubAVS_RESPONSE(1,1)<16;2,4> mov (4) uwDEST_V(1)<1> ubAVS_RESPONSE(6,1)<16;2,4> mov (4) uwDEST_V(1,8)<1> ubAVS_RESPONSE(7,1)<16;2,4> // Move first 4x8 words of U to dest GRF mov (4) uwDEST_U(0)<1> ubAVS_RESPONSE(4,1)<16;2,4> mov (4) uwDEST_U(0,8)<1> ubAVS_RESPONSE(5,1)<16;2,4> mov (4) uwDEST_U(1)<1> ubAVS_RESPONSE(10,1)<16;2,4> mov (4) uwDEST_U(1,8)<1> ubAVS_RESPONSE(11,1)<16;2,4> // Move second 8x8 words of Y to dest GRF mov (8) uwDEST_Y(0,8)<1> ubAVS_RESPONSE_2(2,1)<16;4,2> mov (8) uwDEST_Y(1,8)<1> ubAVS_RESPONSE_2(2,8+1)<16;4,2> mov (8) uwDEST_Y(2,8)<1> ubAVS_RESPONSE_2(3,1)<16;4,2> mov (8) uwDEST_Y(3,8)<1> ubAVS_RESPONSE_2(3,8+1)<16;4,2> mov (8) uwDEST_Y(4,8)<1> ubAVS_RESPONSE_2(8,1)<16;4,2> mov (8) uwDEST_Y(5,8)<1> ubAVS_RESPONSE_2(8,8+1)<16;4,2> mov (8) uwDEST_Y(6,8)<1> ubAVS_RESPONSE_2(9,1)<16;4,2> mov (8) uwDEST_Y(7,8)<1> ubAVS_RESPONSE_2(9,8+1)<16;4,2> // Move second 4x8 words of V to dest GRF mov (4) uwDEST_V(0,4)<1> ubAVS_RESPONSE_2(0,1)<16;2,4> mov (4) uwDEST_V(0,12)<1> ubAVS_RESPONSE_2(1,1)<16;2,4> mov (4) uwDEST_V(1,4)<1> ubAVS_RESPONSE_2(6,1)<16;2,4> mov (4) uwDEST_V(1,12)<1> ubAVS_RESPONSE_2(7,1)<16;2,4> // Move second 4x8 words of U to dest GRF mov (4) uwDEST_U(0,4)<1> ubAVS_RESPONSE_2(4,1)<16;2,4> mov (4) uwDEST_U(0,12)<1> ubAVS_RESPONSE_2(5,1)<16;2,4> mov (4) uwDEST_U(1,4)<1> ubAVS_RESPONSE_2(10,1)<16;2,4> mov (4) uwDEST_U(1,12)<1> ubAVS_RESPONSE_2(11,1)<16;2,4> //------------------------------------------------------------------------------ // Re-define new number of lines #undef nUV_NUM_OF_ROWS #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 #define nUV_NUM_OF_ROWS 8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PA_AVS_IEF_Unpack_8x8.asm000066400000000000000000000111761231401140700314230ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PA_AVS_IEF_Unpack_8x8.asm ---------- // Yoni: In order to optimize unpacking, 3 methods are being checked: // 1. AVS_ORIGINAL // 2. AVS_ROUND_TO_8_BITS // 3. AVS_INDIRECT_ACCESS // // Only 1 method should stay in the code //#define AVS_ROUND_TO_8_BITS //#define AVS_INDIRECT_ACCESS // Move first 8x8 words of Y to dest GRF mov (8) uwDEST_Y(0)<1> ubAVS_RESPONSE(2,1)<16;4,2> mov (8) uwDEST_Y(1)<1> ubAVS_RESPONSE(2,8+1)<16;4,2> mov (8) uwDEST_Y(2)<1> ubAVS_RESPONSE(3,1)<16;4,2> mov (8) uwDEST_Y(3)<1> ubAVS_RESPONSE(3,8+1)<16;4,2> mov (8) uwDEST_Y(4)<1> ubAVS_RESPONSE(8,1)<16;4,2> mov (8) uwDEST_Y(5)<1> ubAVS_RESPONSE(8,8+1)<16;4,2> mov (8) uwDEST_Y(6)<1> ubAVS_RESPONSE(9,1)<16;4,2> mov (8) uwDEST_Y(7)<1> ubAVS_RESPONSE(9,8+1)<16;4,2> // Move first 4x8 words of V to dest GRF mov (4) uwDEST_V(0)<1> ubAVS_RESPONSE(0,1)<16;2,4> mov (4) uwDEST_V(0,8)<1> ubAVS_RESPONSE(0,8+1)<16;2,4> mov (4) uwDEST_V(1)<1> ubAVS_RESPONSE(1,1)<16;2,4> mov (4) uwDEST_V(1,8)<1> ubAVS_RESPONSE(1,8+1)<16;2,4> mov (4) uwDEST_V(2)<1> ubAVS_RESPONSE(6,1)<16;2,4> mov (4) uwDEST_V(2,8)<1> ubAVS_RESPONSE(6,8+1)<16;2,4> mov (4) uwDEST_V(3)<1> ubAVS_RESPONSE(7,1)<16;2,4> mov (4) uwDEST_V(3,8)<1> ubAVS_RESPONSE(7,8+1)<16;2,4> // Move first 4x8 words of U to dest GRF mov (4) uwDEST_U(0)<1> ubAVS_RESPONSE(4,1)<16;2,4> mov (4) uwDEST_U(0,8)<1> ubAVS_RESPONSE(4,8+1)<16;2,4> mov (4) uwDEST_U(1)<1> ubAVS_RESPONSE(5,1)<16;2,4> mov (4) uwDEST_U(1,8)<1> ubAVS_RESPONSE(5,8+1)<16;2,4> mov (4) uwDEST_U(2)<1> ubAVS_RESPONSE(10,1)<16;2,4> mov (4) uwDEST_U(2,8)<1> ubAVS_RESPONSE(10,8+1)<16;2,4> mov (4) uwDEST_U(3)<1> ubAVS_RESPONSE(11,1)<16;2,4> mov (4) uwDEST_U(3,8)<1> ubAVS_RESPONSE(11,8+1)<16;2,4> // Move second 8x8 words of Y to dest GRF mov (8) uwDEST_Y(0,8)<1> ubAVS_RESPONSE_2(2,1)<16;4,2> mov (8) uwDEST_Y(1,8)<1> ubAVS_RESPONSE_2(2,8+1)<16;4,2> mov (8) uwDEST_Y(2,8)<1> ubAVS_RESPONSE_2(3,1)<16;4,2> mov (8) uwDEST_Y(3,8)<1> ubAVS_RESPONSE_2(3,8+1)<16;4,2> mov (8) uwDEST_Y(4,8)<1> ubAVS_RESPONSE_2(8,1)<16;4,2> mov (8) uwDEST_Y(5,8)<1> ubAVS_RESPONSE_2(8,8+1)<16;4,2> mov (8) uwDEST_Y(6,8)<1> ubAVS_RESPONSE_2(9,1)<16;4,2> mov (8) uwDEST_Y(7,8)<1> ubAVS_RESPONSE_2(9,8+1)<16;4,2> // Move second 4x8 words of V to dest GRF mov (4) uwDEST_V(0,4)<1> ubAVS_RESPONSE_2(0,1)<16;2,4> mov (4) uwDEST_V(0,12)<1> ubAVS_RESPONSE_2(0,8+1)<16;2,4> mov (4) uwDEST_V(1,4)<1> ubAVS_RESPONSE_2(1,1)<16;2,4> mov (4) uwDEST_V(1,12)<1> ubAVS_RESPONSE_2(1,8+1)<16;2,4> mov (4) uwDEST_V(2,4)<1> ubAVS_RESPONSE_2(6,1)<16;2,4> mov (4) uwDEST_V(2,12)<1> ubAVS_RESPONSE_2(6,8+1)<16;2,4> mov (4) uwDEST_V(3,4)<1> ubAVS_RESPONSE_2(7,1)<16;2,4> mov (4) uwDEST_V(3,12)<1> ubAVS_RESPONSE_2(7,8+1)<16;2,4> // Move second 4x8 words of U to dest GRF mov (4) uwDEST_U(0,4)<1> ubAVS_RESPONSE_2(4,1)<16;2,4> mov (4) uwDEST_U(0,12)<1> ubAVS_RESPONSE_2(4,8+1)<16;2,4> mov (4) uwDEST_U(1,4)<1> ubAVS_RESPONSE_2(5,1)<16;2,4> mov (4) uwDEST_U(1,12)<1> ubAVS_RESPONSE_2(5,8+1)<16;2,4> mov (4) uwDEST_U(2,4)<1> ubAVS_RESPONSE_2(10,1)<16;2,4> mov (4) uwDEST_U(2,12)<1> ubAVS_RESPONSE_2(10,8+1)<16;2,4> mov (4) uwDEST_U(3,4)<1> ubAVS_RESPONSE_2(11,1)<16;2,4> mov (4) uwDEST_U(3,12)<1> ubAVS_RESPONSE_2(11,8+1)<16;2,4> //------------------------------------------------------------------------------ // Re-define new number of lines #undef nUV_NUM_OF_ROWS #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 #define nUV_NUM_OF_ROWS 8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PA_DNDI_ALG.asm000066400000000000000000000201461231401140700274750ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #define DI_ENABLE #include "DNDI.inc" #ifdef DI_ONLY #undef nSMPL_RESP_LEN #define nSMPL_RESP_LEN nSMPL_RESP_LEN_DI // set the number of GRF #else #undef nSMPL_RESP_LEN #define nSMPL_RESP_LEN nSMPL_RESP_LEN_DNDI // set the number of GRF #endif #undef nDPW_BLOCK_SIZE_HIST #define nDPW_BLOCK_SIZE_HIST nBLOCK_WIDTH_4+nBLOCK_HEIGHT_1 // HIST Block Size for Write is 4x2 #undef nDPW_BLOCK_SIZE_DN #define nDPW_BLOCK_SIZE_DN nBLOCK_WIDTH_32+nBLOCK_HEIGHT_4 // DN Block Size for Write is 32x4 ////////////////////////////////////// Run the DN Algorithm /////////////////////////////////////// #include "DNDI_Command.asm" ////////////////////////////////////// Rearrange for Internal Planar ////////////////////////////// //// move the previous frame Y component to internal planar format //$for (0; ubRESP(nDI_PREV_FRAME_LUMA_OFFSET,%1*16) //} //// move the previous frame U,V components to internal planar format //$for (0; ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels // mov (8) uwDEST_V(0,%1*8)<1> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //V pixels //} //// move the current frame Y component to internal planar format //$for (0; ubRESP(nDI_CURR_FRAME_LUMA_OFFSET,%1*16) //} //// move the current frame U,V components to internal planar format //$for (0; ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels // mov (8) uwDEST_V(2,%1*8)<1> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //V pixels //} ////////////////////////////////////// Save the STMM Data for Next Run ///////////////////////// // Write STMM to memory shr (1) rMSGSRC.0<1>:ud wORIX<0;1,0>:w 1:w NODDCLR // X origin / 2 mov (1) rMSGSRC.1<1>:ud wORIY<0;1,0>:w NODDCLR_NODDCHK // Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_STMM:ud NODDCHK // block width and height (8x4) mov (8) mudMSGHDR_STMM(0)<1> rMSGSRC.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udRESP(nDI_STMM_OFFSET,0) // Move STMM to MRF send (8) dNULLREG mMSGHDR_STMM udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_STMM+nBI_STMM_HISTORY_OUTPUT:ud ////////////////////////////////////// Save the History Data for Next Run ///////////////////////// #ifdef DI_ONLY #else #include "DI_Hist_Save.asm" ////////////////////////////////////// Pack and Save the DN Curr Frame for Next Run /////////////// // check top/bottom field first cmp.e.f0.0 (1) null<1>:w ubTFLD_FIRST<0;1,0>:ub 1:w add (4) pCF_Y_OFFSET<1>:uw ubSRC_CF_OFFSET<4;4,1>:ub npDN_YUV:uw //set the save DN position shl (1) rMSGSRC.0<1>:ud wORIX<0;1,0>:w 1:w NODDCLR // X origin * 2 mov (1) rMSGSRC.1<1>:ud wORIY<0;1,0>:w NODDCLR_NODDCHK // Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud NODDCHK // block width and height (8x4) mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud (f0.0) jmpi (1) TOP_FIELD_FIRST BOTTOM_FIELD_FIRST: //$for (0,0; :ub ubRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*16) // 2nd field luma from current frame (line 0,2) // mov (16) r[pCF_Y_OFFSET, %1+1*32]<2>:ub ubRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,16) // 1st field luma from current frame (line 1,3) // mov (8) r[pCF_U_OFFSET, %1*32]<4>:ub ubRESP(nDI_CURR_2ND_FIELD_CHROMA_OFFSET,%2*16+1)<16;8,2> // 2nd field U from current frame (line 0,2) // mov (8) r[pCF_V_OFFSET, %1*32]<4>:ub ubRESP(nDI_CURR_2ND_FIELD_CHROMA_OFFSET,%2*16)<16;8,2> // 2nd field V from current frame (line 0,2) // mov (8) r[pCF_U_OFFSET, %1+1*32]<4>:ub ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+%2,16+1)<16;8,2> // 1st field U from current frame (line 1,3) // mov (8) r[pCF_V_OFFSET, %1+1*32]<4>:ub ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+%2,16)<16;8,2> // 1st field U from current frame (line 1,3) //} $for (0,0; :ub ubRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*16) // 2nd field luma from current frame (line 0,2) mov (16) r[pCF_Y_OFFSET, %1+1*32]<2>:ub ubRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,16) // 1st field luma from current frame (line 1,3) } $for (0,0; :ub ubRESP(nDI_CURR_2ND_FIELD_CHROMA_OFFSET,%2*16+1)<16;8,2> // 2nd field U from current frame (line 0,2) mov (8) r[pCF_U_OFFSET, %1+1*32]<4>:ub ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+%2,16+1)<16;8,2> // 1st field U from current frame (line 1,3) } $for (0,0; :ub ubRESP(nDI_CURR_2ND_FIELD_CHROMA_OFFSET,%2*16)<16;8,2> // 2nd field V from current frame (line 0,2) mov (8) r[pCF_V_OFFSET, %1+1*32]<4>:ub ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+%2,16)<16;8,2> // 1st field U from current frame (line 1,3) } jmpi (1) SAVE_DN_CURR TOP_FIELD_FIRST: //$for (0,0; :ub ubRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,0) // 1st field luma from current frame (line 0,2) // mov (16) r[pCF_Y_OFFSET, %1+1*32]<2>:ub ubRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*16) // 2nd field luma from current frame (line 1,3) // mov (8) r[pCF_U_OFFSET, %1*32]<4>:ub ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+%2,1)<16;8,2> // 1st field U from current frame (line 0,2) // mov (8) r[pCF_V_OFFSET, %1*32]<4>:ub ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+%2,0)<16;8,2> // 1st field V from current frame (line 0,2) // mov (8) r[pCF_U_OFFSET, %1+1*32]<4>:ub ubRESP(nDI_CURR_2ND_FIELD_CHROMA_OFFSET,%2*16+1)<16;8,2> // 2nd field U from current frame (line 1,3) // mov (8) r[pCF_V_OFFSET, %1+1*32]<4>:ub ubRESP(nDI_CURR_2ND_FIELD_CHROMA_OFFSET,%2*16)<16;8,2> // 2nd field V from current frame (line 1,3) //} $for (0,0; :ub ubRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,0) // 1st field luma from current frame (line 0,2) mov (16) r[pCF_Y_OFFSET, %1+1*32]<2>:ub ubRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*16) // 2nd field luma from current frame (line 1,3) } $for (0,0; :ub ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+%2,1)<16;8,2> // 1st field U from current frame (line 0,2) mov (8) r[pCF_U_OFFSET, %1+1*32]<4>:ub ubRESP(nDI_CURR_2ND_FIELD_CHROMA_OFFSET,%2*16+1)<16;8,2> // 2nd field U from current frame (line 1,3) } $for (0,0; :ub ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+%2,0)<16;8,2> // 1st field V from current frame (line 0,2) mov (8) r[pCF_V_OFFSET, %1+1*32]<4>:ub ubRESP(nDI_CURR_2ND_FIELD_CHROMA_OFFSET,%2*16)<16;8,2> // 2nd field V from current frame (line 1,3) } SAVE_DN_CURR: $for(0; udDN_YUV(%1)REGION(8,1) } send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PA_DN_DI+nBI_DESTINATION_YUV:ud #endif // Save Processed frames #include "DI_Save_PA.asm" intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PA_DN_ALG.asm000066400000000000000000000045561231401140700272670ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #define DI_DISABLE #include "DNDI.inc" #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 // Number of Y rows per block #undef nUV_NUM_OF_ROWS #define nUV_NUM_OF_ROWS 8 // Number of U/V rows per block #undef nSMPL_RESP_LEN #define nSMPL_RESP_LEN nSMPL_RESP_LEN_DN_PA // Set the Number of GRFs in DNDI response #undef nDPW_BLOCK_SIZE_DN #define nDPW_BLOCK_SIZE_DN nBLOCK_WIDTH_32+nBLOCK_HEIGHT_8 // DN Curr Block Size for Write is 32x8 #undef nDPW_BLOCK_SIZE_HIST #define nDPW_BLOCK_SIZE_HIST nBLOCK_WIDTH_4+nBLOCK_HEIGHT_2 // HIST Block Size for Write is 4x2 ////////////////////////////////////// Run the DN Algorithm /////////////////////////////////////// #include "DNDI_COMMAND.asm" ////////////////////////////////////// Save the History Data for Next Run ///////////////////////// #include "DNDI_Hist_Save.asm" ////////////////////////////////////// Pack and Save the DN Curr Frame for Next Run /////////////// add (4) pCF_Y_OFFSET<1>:uw ubDEST_CF_OFFSET<4;4,1>:ub npDN_YUV:w $for (0; :ub ubRESP(nNODI_LUMA_OFFSET,%1*16)<16;16,1> // copy line of Y } $for (0; :ub ubRESP(nNODI_CHROMA_OFFSET,%1*16+1)<16;8,2> // copy line of U mov (8) r[pCF_V_OFFSET, %1*32]<4>:ub ubRESP(nNODI_CHROMA_OFFSET,%1*16)<16;8,2> // copy line of V } shl (1) rMSGSRC.0<1>:ud wORIX<0;1,0>:w 1:w // X origin * 2 (422 output) mov (1) rMSGSRC.1<1>:ud wORIY<0;1,0>:w // Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud // block width and height (32x8) mov (8) mMSGHDR_DN<1>:ud rMSGSRC<8;8,1>:ud // message header $for(0; udDN_YUV(%1)REGION(8,1) // Move DN Curr to MRF } send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PA_DN_NODI+nBI_DESTINATION_YUV:ud intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PA_Scaling.asm000066400000000000000000000061561231401140700276610ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PA_Scaling.asm ---------- #include "Scaling.inc" // Build 16 elements ramp in float32 and normalized it // mov (8) SAMPLER_RAMP(0)<1> 0x76543210:v // add (8) SAMPLER_RAMP(1)<1> SAMPLER_RAMP(0) 8.0:f mov (4) SAMPLER_RAMP(0)<1> 0x48403000:vf //3, 2, 1, 0 in float vector mov (4) SAMPLER_RAMP(0,4)<1> 0x5C585450:vf //7, 6, 5, 4 in float vector add (8) SAMPLER_RAMP(1)<1> SAMPLER_RAMP(0) 8.0:f //Module: PrepareScaleCoord.asm // Setup for sampler msg hdr mov (2) rMSGSRC.0<1>:ud 0:ud { NoDDClr } // Unused fields mov (1) rMSGSRC.2<1>:ud 0:ud { NoDDChk } // Write and offset // Calculate 16 v based on the step Y and vertical origin mov (16) mfMSGPAYLOAD(2)<1> fSRC_VID_V_ORI<0;1,0>:f mov (16) SCALE_COORD_Y<1>:f fSRC_VID_V_ORI<0;1,0>:f // Calculate 16 u based on the step X and hori origin // line (16) mfMSGPAYLOAD(0)<1> SCALE_STEP_X<0;1,0>:f SAMPLER_RAMP(0) // Assign to mrf directly mov (16) acc0:f fSRC_VID_H_ORI<0;1,0>:f { Compr } mac (16) mfMSGPAYLOAD(0)<1> fVIDEO_STEP_X<0;1,0>:f SAMPLER_RAMP(0) { Compr } //Setup the constants for line instruction mov (1) SCALE_LINE_P255<1>:f 255.0:f { NoDDClr } //{ NoDDClr, NoDDChk } mov (1) SCALE_LINE_P0_5<1>:f 0.5:f { NoDDChk } //------------------------------------------------------------------------------ $for (0; :ud // Copy msg header and payload mirrors to MRFs send (16) SCALE_RESPONSE_YW(0)<1> MSGHDR_SCALE udDUMMY_NULL nSMPL_ENGINE SMPLR_MSG_DSC+nSI_SRC_SIMD16_YUV+nBI_CURRENT_SRC_YUV // Calculate 16 v for next line add (16) mfMSGPAYLOAD(2)<1> SCALE_COORD_Y<8;8,1>:f fVIDEO_STEP_Y<0;1,0>:f // Assign to mrf directly add (16) SCALE_COORD_Y<1>:f SCALE_COORD_Y<8;8,1>:f fVIDEO_STEP_Y<0;1,0>:f // Assign to mrf directly // Scale back to [0, 255], convert f to ud line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(0) { Compr } // Process B, V mov (16) SCALE_RESPONSE_YD(0)<1> acc0:f { Compr } line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(2) { Compr } // Process B, V mov (16) SCALE_RESPONSE_YD(2)<1> acc0:f { Compr } line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(4) { Compr } // Process B, V mov (16) SCALE_RESPONSE_YD(4)<1> acc0:f { Compr } mov (16) DEST_V(%1)<1> SCALE_RESPONSE_YB(0) //possible error due to truncation - vK mov (16) DEST_Y(%1)<1> SCALE_RESPONSE_YB(2) //possible error due to truncation - vK mov (16) DEST_U(%1)<1> SCALE_RESPONSE_YB(4) //possible error due to truncation - vK } #define nSRC_REGION nREGION_1 //------------------------------------------------------------------------------ intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL2_AVS_IEF_16x8.asm000066400000000000000000000050751231401140700302770ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL2_AVS_IEF_16x8.asm ---------- #include "AVS_IEF.inc" //------------------------------------------------------------------------------ // 2 sampler reads for 8x8 Y each // 2 sampler read for 8x8 U and 8x8 V (NV11\P208 input surface) //------------------------------------------------------------------------------ // 1st 8x8 setup #include "AVS_SetupFirstBlock.asm" // Enable green channel only mov (1) rAVS_8x8_HDR.2:ud nAVS_GREEN_CHANNEL_ONLY:ud mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(0)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_Y+nBI_CURRENT_SRC_Y // Return Y in 4 GRFs // 8x8 U and V sampling // Enable red and blue channels mov (1) rAVS_8x8_HDR.2:ud nAVS_RED_BLUE_CHANNELS:ud mov (16) mAVS_8x8_HDR_UV.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(4)<1> mAVS_8x8_HDR_UV udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_2CH+nSI_SRC_UV+nBI_CURRENT_SRC_UV // Return U and V in 8 GRFs // 2nd 8x8 setup #include "AVS_SetupSecondBlock.asm" // 2nd 8x8 Y sampling // Enable green channel only mov (1) rAVS_8x8_HDR.2:ud nAVS_GREEN_CHANNEL_ONLY:ud mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE_2(0)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_Y+nBI_CURRENT_SRC_Y // 2nd 8x8 U and V sampling // Enable red and blue channels mov (1) rAVS_8x8_HDR.2:ud nAVS_RED_BLUE_CHANNELS:ud mov (16) mAVS_8x8_HDR_UV.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE_2(4)<1> mAVS_8x8_HDR_UV udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_2CH+nSI_SRC_UV+nBI_CURRENT_SRC_UV // Return U and V in 8 GRFs //------------------------------------------------------------------------------ // Unpacking sampler reads to 4:4:4 internal planar //------------------------------------------------------------------------------ #include "PL2_AVS_IEF_Unpack_16x8.asm" intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL2_AVS_IEF_8x4.asm000066400000000000000000000050151231401140700302060ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL2_AVS_IEF_8x4.asm ---------- #include "AVS_IEF.inc" //------------------------------------------------------------------------------ // 2 sampler reads for 8x8 Y each // 1 sampler read for 8x8 U and 8x8 V (NV11\NV12 input surface) //------------------------------------------------------------------------------ // 1st 8x8 setup #include "AVS_SetupFirstBlock.asm" // Enable green channel only mov (1) rAVS_8x8_HDR.2:ud nAVS_GREEN_CHANNEL_ONLY:ud mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(0)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_Y+nBI_CURRENT_SRC_Y // Return Y in 4 GRFs // 8x8 U and V sampling // Enable red and blue channels //Only 8x4 wil be used mov (1) rAVS_8x8_HDR.2:ud nAVS_RED_BLUE_CHANNELS:ud // Calculate Chroma Step Size: // for H direction: 16 Luma samples are covered by 8 Chroma samples. Thus Chroma_Step_X = 2 * Luma_Step_X // for V direction: 8 Luma samples are covered by 8 Chroma samples. Thus Chroma_Step_Y = Luma_Step_Y mul (1) rAVS_PAYLOAD.1:f fVIDEO_STEP_X:f 2.0:f // Step X for chroma mov (16) mAVS_8x8_HDR_UV.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(4)<1> mAVS_8x8_HDR_UV udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_2CH+nSI_SRC_UV+nBI_CURRENT_SRC_UV // Return U and V in 8 GRFs // 2nd 8x8 setup #include "AVS_SetupSecondBlock.asm" // 2nd 8x8 Y sampling // Enable green channel only mov (1) rAVS_8x8_HDR.2:ud nAVS_GREEN_CHANNEL_ONLY:ud mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE_2(0)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_Y+nBI_CURRENT_SRC_Y //------------------------------------------------------------------------------ // Unpacking sampler reads to 4:2:0 internal planar //------------------------------------------------------------------------------ #include "PL2_AVS_IEF_Unpack_8x4.asm" intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL2_AVS_IEF_8x8.asm000066400000000000000000000047621231401140700302220ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL2_AVS_IEF_8x8.asm ---------- #include "AVS_IEF.inc" //------------------------------------------------------------------------------ // 2 sampler reads for 8x8 Y each // 1 sampler read for 8x8 U and 8x8 V (NV11\NV12 input surface) //------------------------------------------------------------------------------ // 1st 8x8 setup #include "AVS_SetupFirstBlock.asm" // Enable green channel only mov (1) rAVS_8x8_HDR.2:ud nAVS_GREEN_CHANNEL_ONLY:ud mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(0)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_Y+nBI_CURRENT_SRC_Y // Return Y in 4 GRFs // 8x8 U and V sampling // Enable red and blue channels mov (1) rAVS_8x8_HDR.2:ud nAVS_RED_BLUE_CHANNELS:ud // Calculate Chroma Step Size: // for H direction: 16 Luma samples are covered by 8 Chroma samples. Thus Chroma_Step_X = 2 * Luma_Step_X // for V direction: 8 Luma samples are covered by 8 Chroma samples. Thus Chroma_Step_Y = Luma_Step_Y mul (1) rAVS_PAYLOAD.1:f fVIDEO_STEP_X:f 2.0:f // Step X for chroma mov (16) mAVS_8x8_HDR_UV.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(4)<1> mAVS_8x8_HDR_UV udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_2CH+nSI_SRC_UV+nBI_CURRENT_SRC_UV // Return U and V in 8 GRFs // 2nd 8x8 setup #include "AVS_SetupSecondBlock.asm" // 2nd 8x8 Y sampling // Enable green channel only mov (1) rAVS_8x8_HDR.2:ud nAVS_GREEN_CHANNEL_ONLY:ud mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE_2(0)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_Y+nBI_CURRENT_SRC_Y //------------------------------------------------------------------------------ // Unpacking sampler reads to 4:2:2 internal planar //------------------------------------------------------------------------------ #include "PL2_AVS_IEF_Unpack_8x8.asm" intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL2_AVS_IEF_Unpack_16x8.asm000066400000000000000000000454071231401140700316030ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL2_AVS_IEF_Unpack_16x8.asm ---------- #ifdef AVS_OUTPUT_16_BIT //Output is packed in AVYU format // Move first 8x8 words of Y to dest GRF (as packed) mov (4) uwDEST_Y(0,1)<4> uwAVS_RESPONSE(0,0)<4;4,1> mov (4) uwDEST_Y(1,1)<4> uwAVS_RESPONSE(0,8)<4;4,1> mov (4) uwDEST_Y(4,1)<4> uwAVS_RESPONSE(0,4)<4;4,1> mov (4) uwDEST_Y(5,1)<4> uwAVS_RESPONSE(0,12)<4;4,1> mov (4) uwDEST_Y(8,1)<4> uwAVS_RESPONSE(1,0)<4;4,1> mov (4) uwDEST_Y(9,1)<4> uwAVS_RESPONSE(1,8)<4;4,1> mov (4) uwDEST_Y(12,1)<4> uwAVS_RESPONSE(1,4)<4;4,1> mov (4) uwDEST_Y(13,1)<4> uwAVS_RESPONSE(1,12)<4;4,1> mov (4) uwDEST_Y(16,1)<4> uwAVS_RESPONSE(2,0)<4;4,1> mov (4) uwDEST_Y(17,1)<4> uwAVS_RESPONSE(2,8)<4;4,1> mov (4) uwDEST_Y(20,1)<4> uwAVS_RESPONSE(2,4)<4;4,1> mov (4) uwDEST_Y(21,1)<4> uwAVS_RESPONSE(2,12)<4;4,1> mov (4) uwDEST_Y(24,1)<4> uwAVS_RESPONSE(3,0)<4;4,1> mov (4) uwDEST_Y(25,1)<4> uwAVS_RESPONSE(3,8)<4;4,1> mov (4) uwDEST_Y(28,1)<4> uwAVS_RESPONSE(3,4)<4;4,1> mov (4) uwDEST_Y(29,1)<4> uwAVS_RESPONSE(3,12)<4;4,1> // Move first 8x8 words of U to dest GRF (as packed) mov (4) uwDEST_Y(0,0)<4> uwAVS_RESPONSE(4,0)<4;4,1> mov (4) uwDEST_Y(1,0)<4> uwAVS_RESPONSE(4,8)<4;4,1> mov (4) uwDEST_Y(4,0)<4> uwAVS_RESPONSE(4,4)<4;4,1> mov (4) uwDEST_Y(5,0)<4> uwAVS_RESPONSE(4,12)<4;4,1> mov (4) uwDEST_Y(8,0)<4> uwAVS_RESPONSE(5,0)<4;4,1> mov (4) uwDEST_Y(9,0)<4> uwAVS_RESPONSE(5,8)<4;4,1> mov (4) uwDEST_Y(12,0)<4> uwAVS_RESPONSE(5,4)<4;4,1> mov (4) uwDEST_Y(13,0)<4> uwAVS_RESPONSE(5,12)<4;4,1> mov (4) uwDEST_Y(16,0)<4> uwAVS_RESPONSE(8,0)<4;4,1> mov (4) uwDEST_Y(17,0)<4> uwAVS_RESPONSE(8,8)<4;4,1> mov (4) uwDEST_Y(20,0)<4> uwAVS_RESPONSE(8,4)<4;4,1> mov (4) uwDEST_Y(21,0)<4> uwAVS_RESPONSE(8,12)<4;4,1> mov (4) uwDEST_Y(24,0)<4> uwAVS_RESPONSE(9,0)<4;4,1> mov (4) uwDEST_Y(25,0)<4> uwAVS_RESPONSE(9,8)<4;4,1> mov (4) uwDEST_Y(28,0)<4> uwAVS_RESPONSE(9,4)<4;4,1> mov (4) uwDEST_Y(29,0)<4> uwAVS_RESPONSE(9,12)<4;4,1> // Move first 8x8 words of V to dest GRF (as packed) mov (4) uwDEST_Y(0,2)<4> uwAVS_RESPONSE(6,0)<4;4,1> mov (4) uwDEST_Y(1,2)<4> uwAVS_RESPONSE(6,8)<4;4,1> mov (4) uwDEST_Y(4,2)<4> uwAVS_RESPONSE(6,4)<4;4,1> mov (4) uwDEST_Y(5,2)<4> uwAVS_RESPONSE(6,12)<4;4,1> mov (4) uwDEST_Y(8,2)<4> uwAVS_RESPONSE(7,0)<4;4,1> mov (4) uwDEST_Y(9,2)<4> uwAVS_RESPONSE(7,8)<4;4,1> mov (4) uwDEST_Y(12,2)<4> uwAVS_RESPONSE(7,4)<4;4,1> mov (4) uwDEST_Y(13,2)<4> uwAVS_RESPONSE(7,12)<4;4,1> mov (4) uwDEST_Y(16,2)<4> uwAVS_RESPONSE(10,0)<4;4,1> mov (4) uwDEST_Y(17,2)<4> uwAVS_RESPONSE(10,8)<4;4,1> mov (4) uwDEST_Y(20,2)<4> uwAVS_RESPONSE(10,4)<4;4,1> mov (4) uwDEST_Y(21,2)<4> uwAVS_RESPONSE(10,12)<4;4,1> mov (4) uwDEST_Y(24,2)<4> uwAVS_RESPONSE(11,0)<4;4,1> mov (4) uwDEST_Y(25,2)<4> uwAVS_RESPONSE(11,8)<4;4,1> mov (4) uwDEST_Y(28,2)<4> uwAVS_RESPONSE(11,4)<4;4,1> mov (4) uwDEST_Y(29,2)<4> uwAVS_RESPONSE(11,12)<4;4,1> // Move first 8x8 words of A to dest GRF (as packed) mov (4) uwDEST_Y(0,3)<4> 0:uw mov (4) uwDEST_Y(1,3)<4> 0:uw mov (4) uwDEST_Y(4,3)<4> 0:uw mov (4) uwDEST_Y(5,3)<4> 0:uw mov (4) uwDEST_Y(8,3)<4> 0:uw mov (4) uwDEST_Y(9,3)<4> 0:uw mov (4) uwDEST_Y(12,3)<4> 0:uw mov (4) uwDEST_Y(13,3)<4> 0:uw mov (4) uwDEST_Y(16,3)<4> 0:uw mov (4) uwDEST_Y(17,3)<4> 0:uw mov (4) uwDEST_Y(20,3)<4> 0:uw mov (4) uwDEST_Y(21,3)<4> 0:uw mov (4) uwDEST_Y(24,3)<4> 0:uw mov (4) uwDEST_Y(25,3)<4> 0:uw mov (4) uwDEST_Y(28,3)<4> 0:uw mov (4) uwDEST_Y(29,3)<4> 0:uw // Move second 8x8 words of Y to dest GRF mov (4) uwDEST_Y(2,1)<4> uwAVS_RESPONSE_2(0,0)<4;4,1> mov (4) uwDEST_Y(3,1)<4> uwAVS_RESPONSE_2(0,8)<4;4,1> mov (4) uwDEST_Y(6,1)<4> uwAVS_RESPONSE_2(0,4)<4;4,1> mov (4) uwDEST_Y(7,1)<4> uwAVS_RESPONSE_2(0,12)<4;4,1> mov (4) uwDEST_Y(10,1)<4> uwAVS_RESPONSE_2(1,0)<4;4,1> mov (4) uwDEST_Y(11,1)<4> uwAVS_RESPONSE_2(1,8)<4;4,1> mov (4) uwDEST_Y(14,1)<4> uwAVS_RESPONSE_2(1,4)<4;4,1> mov (4) uwDEST_Y(15,1)<4> uwAVS_RESPONSE_2(1,12)<4;4,1> mov (4) uwDEST_Y(18,1)<4> uwAVS_RESPONSE_2(2,0)<4;4,1> mov (4) uwDEST_Y(19,1)<4> uwAVS_RESPONSE_2(2,8)<4;4,1> mov (4) uwDEST_Y(22,1)<4> uwAVS_RESPONSE_2(2,4)<4;4,1> mov (4) uwDEST_Y(23,1)<4> uwAVS_RESPONSE_2(2,12)<4;4,1> mov (4) uwDEST_Y(26,1)<4> uwAVS_RESPONSE_2(3,0)<4;4,1> mov (4) uwDEST_Y(27,1)<4> uwAVS_RESPONSE_2(3,8)<4;4,1> mov (4) uwDEST_Y(30,1)<4> uwAVS_RESPONSE_2(3,4)<4;4,1> mov (4) uwDEST_Y(31,1)<4> uwAVS_RESPONSE_2(3,12)<4;4,1> // Move second 8x8 words of U to dest GRF mov (4) uwDEST_Y(2,0)<4> uwAVS_RESPONSE_2(4,0)<4;4,1> mov (4) uwDEST_Y(3,0)<4> uwAVS_RESPONSE_2(4,8)<4;4,1> mov (4) uwDEST_Y(6,0)<4> uwAVS_RESPONSE_2(4,4)<4;4,1> mov (4) uwDEST_Y(7,0)<4> uwAVS_RESPONSE_2(4,12)<4;4,1> mov (4) uwDEST_Y(10,0)<4> uwAVS_RESPONSE_2(5,0)<4;4,1> mov (4) uwDEST_Y(11,0)<4> uwAVS_RESPONSE_2(5,8)<4;4,1> mov (4) uwDEST_Y(14,0)<4> uwAVS_RESPONSE_2(5,4)<4;4,1> mov (4) uwDEST_Y(15,0)<4> uwAVS_RESPONSE_2(5,12)<4;4,1> mov (4) uwDEST_Y(18,0)<4> uwAVS_RESPONSE_2(8,0)<4;4,1> mov (4) uwDEST_Y(19,0)<4> uwAVS_RESPONSE_2(8,8)<4;4,1> mov (4) uwDEST_Y(22,0)<4> uwAVS_RESPONSE_2(8,4)<4;4,1> mov (4) uwDEST_Y(23,0)<4> uwAVS_RESPONSE_2(8,12)<4;4,1> mov (4) uwDEST_Y(26,0)<4> uwAVS_RESPONSE_2(9,0)<4;4,1> mov (4) uwDEST_Y(27,0)<4> uwAVS_RESPONSE_2(9,8)<4;4,1> mov (4) uwDEST_Y(30,0)<4> uwAVS_RESPONSE_2(9,4)<4;4,1> mov (4) uwDEST_Y(31,0)<4> uwAVS_RESPONSE_2(9,12)<4;4,1> // Move second 8x8 words of V to dest GRF mov (4) uwDEST_Y(2,2)<4> uwAVS_RESPONSE_2(6,0)<4;4,1> mov (4) uwDEST_Y(3,2)<4> uwAVS_RESPONSE_2(6,8)<4;4,1> mov (4) uwDEST_Y(6,2)<4> uwAVS_RESPONSE_2(6,4)<4;4,1> mov (4) uwDEST_Y(7,2)<4> uwAVS_RESPONSE_2(6,12)<4;4,1> mov (4) uwDEST_Y(10,2)<4> uwAVS_RESPONSE_2(7,0)<4;4,1> mov (4) uwDEST_Y(11,2)<4> uwAVS_RESPONSE_2(7,8)<4;4,1> mov (4) uwDEST_Y(14,2)<4> uwAVS_RESPONSE_2(7,4)<4;4,1> mov (4) uwDEST_Y(15,2)<4> uwAVS_RESPONSE_2(7,12)<4;4,1> mov (4) uwDEST_Y(18,2)<4> uwAVS_RESPONSE_2(10,0)<4;4,1> mov (4) uwDEST_Y(19,2)<4> uwAVS_RESPONSE_2(10,8)<4;4,1> mov (4) uwDEST_Y(22,2)<4> uwAVS_RESPONSE_2(10,4)<4;4,1> mov (4) uwDEST_Y(23,2)<4> uwAVS_RESPONSE_2(10,12)<4;4,1> mov (4) uwDEST_Y(26,2)<4> uwAVS_RESPONSE_2(11,0)<4;4,1> mov (4) uwDEST_Y(27,2)<4> uwAVS_RESPONSE_2(11,8)<4;4,1> mov (4) uwDEST_Y(30,2)<4> uwAVS_RESPONSE_2(11,4)<4;4,1> mov (4) uwDEST_Y(31,2)<4> uwAVS_RESPONSE_2(11,12)<4;4,1> // Move second 8x8 words of A to dest GRF mov (4) uwDEST_Y(2,3)<4> 0:uw mov (4) uwDEST_Y(3,3)<4> 0:uw mov (4) uwDEST_Y(6,3)<4> 0:uw mov (4) uwDEST_Y(7,3)<4> 0:uw mov (4) uwDEST_Y(10,3)<4> 0:uw mov (4) uwDEST_Y(11,3)<4> 0:uw mov (4) uwDEST_Y(14,3)<4> 0:uw mov (4) uwDEST_Y(15,3)<4> 0:uw mov (4) uwDEST_Y(18,3)<4> 0:uw mov (4) uwDEST_Y(19,3)<4> 0:uw mov (4) uwDEST_Y(22,3)<4> 0:uw mov (4) uwDEST_Y(23,3)<4> 0:uw mov (4) uwDEST_Y(26,3)<4> 0:uw mov (4) uwDEST_Y(27,3)<4> 0:uw mov (4) uwDEST_Y(30,3)<4> 0:uw mov (4) uwDEST_Y(31,3)<4> 0:uw /* This section will be used if 16-bit output is needed in planar format -vK // Move 1st 8x8 words of Y to dest GRF at lower 8 words of each RGF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2)<1> uwAVS_RESPONSE(%1,0)<8;4,1> mov (8) uwDEST_Y(%1*2+1)<1> uwAVS_RESPONSE(%1,8)<8;4,1> } // Move 1st 8x8 words of U to dest GRF (Copy high byte in a word) mov (8) uwDEST_U(0)<1> uwAVS_RESPONSE(4,0)<8;4,1> mov (8) uwDEST_U(1)<1> uwAVS_RESPONSE(4,8)<8;4,1> mov (8) uwDEST_U(2)<1> uwAVS_RESPONSE(5,0)<8;4,1> mov (8) uwDEST_U(3)<1> uwAVS_RESPONSE(5,8)<8;4,1> mov (8) uwDEST_U(4)<1> uwAVS_RESPONSE(8,0)<8;4,1> mov (8) uwDEST_U(5)<1> uwAVS_RESPONSE(8,8)<8;4,1> mov (8) uwDEST_U(6)<1> uwAVS_RESPONSE(9,0)<8;4,1> mov (8) uwDEST_U(7)<1> uwAVS_RESPONSE(9,8)<8;4,1> // Move 1st 8x8 words of V to dest GRF mov (8) uwDEST_V(0)<1> uwAVS_RESPONSE(6,0)<8;4,1> mov (8) uwDEST_V(1)<1> uwAVS_RESPONSE(6,8)<8;4,1> mov (8) uwDEST_V(2)<1> uwAVS_RESPONSE(7,0)<8;4,1> mov (8) uwDEST_V(3)<1> uwAVS_RESPONSE(7,8)<8;4,1> mov (8) uwDEST_V(4)<1> uwAVS_RESPONSE(10,0)<8;4,1> mov (8) uwDEST_V(5)<1> uwAVS_RESPONSE(10,8)<8;4,1> mov (8) uwDEST_V(6)<1> uwAVS_RESPONSE(11,0)<8;4,1> mov (8) uwDEST_V(7)<1> uwAVS_RESPONSE(11,8)<8;4,1> // Move 2nd 8x8 words of Y to dest GRF at higher 8 words of each GRF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2,8)<1> uwAVS_RESPONSE_2(%1,0)<8;4,1> mov (8) uwDEST_Y(%1*2+1,8)<1> uwAVS_RESPONSE_2(%1,8)<8;4,1> } // Move 2st 8x8 words of U to dest GRF (Copy high byte in a word) mov (8) uwDEST_U(0,8)<1> uwAVS_RESPONSE_2(4,0)<8;4,1> mov (8) uwDEST_U(1,8)<1> uwAVS_RESPONSE_2(4,8)<8;4,1> mov (8) uwDEST_U(2,8)<1> uwAVS_RESPONSE_2(5,0)<8;4,1> mov (8) uwDEST_U(3,8)<1> uwAVS_RESPONSE_2(5,8)<8;4,1> mov (8) uwDEST_U(4,8)<1> uwAVS_RESPONSE_2(8,0)<8;4,1> mov (8) uwDEST_U(5,8)<1> uwAVS_RESPONSE_2(8,8)<8;4,1> mov (8) uwDEST_U(6,8)<1> uwAVS_RESPONSE_2(9,0)<8;4,1> mov (8) uwDEST_U(7,8)<1> uwAVS_RESPONSE_2(9,8)<8;4,1> // Move 2st 8x8 words of V to dest GRF mov (8) uwDEST_V(0,8)<1> uwAVS_RESPONSE_2(6,0)<8;4,1> mov (8) uwDEST_V(1,8)<1> uwAVS_RESPONSE_2(6,8)<8;4,1> mov (8) uwDEST_V(2,8)<1> uwAVS_RESPONSE_2(7,0)<8;4,1> mov (8) uwDEST_V(3,8)<1> uwAVS_RESPONSE_2(7,8)<8;4,1> mov (8) uwDEST_V(4,8)<1> uwAVS_RESPONSE_2(10,0)<8;4,1> mov (8) uwDEST_V(5,8)<1> uwAVS_RESPONSE_2(10,8)<8;4,1> mov (8) uwDEST_V(6,8)<1> uwAVS_RESPONSE_2(11,0)<8;4,1> mov (8) uwDEST_V(7,8)<1> uwAVS_RESPONSE_2(11,8)<8;4,1> */ #else // Move 1st 8x8 words of Y to dest GRF at lower 8 words of each RGF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2)<1> ubAVS_RESPONSE(%1,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_Y(%1*2+1)<1> ubAVS_RESPONSE(%1,8+1)<16;4,2> // Copy high byte in a word } // Move 1st 8x8 words of U to dest GRF (Copy high byte in a word) mov (8) uwDEST_U(0)<1> ubAVS_RESPONSE(4,1)<16;4,2> mov (8) uwDEST_U(1)<1> ubAVS_RESPONSE(4,8+1)<16;4,2> mov (8) uwDEST_U(2)<1> ubAVS_RESPONSE(5,1)<16;4,2> mov (8) uwDEST_U(3)<1> ubAVS_RESPONSE(5,8+1)<16;4,2> mov (8) uwDEST_U(4)<1> ubAVS_RESPONSE(8,1)<16;4,2> mov (8) uwDEST_U(5)<1> ubAVS_RESPONSE(8,8+1)<16;4,2> mov (8) uwDEST_U(6)<1> ubAVS_RESPONSE(9,1)<16;4,2> mov (8) uwDEST_U(7)<1> ubAVS_RESPONSE(9,8+1)<16;4,2> // Move 1st 8x8 words of V to dest GRF mov (8) uwDEST_V(0)<1> ubAVS_RESPONSE(6,1)<16;4,2> mov (8) uwDEST_V(1)<1> ubAVS_RESPONSE(6,8+1)<16;4,2> mov (8) uwDEST_V(2)<1> ubAVS_RESPONSE(7,1)<16;4,2> mov (8) uwDEST_V(3)<1> ubAVS_RESPONSE(7,8+1)<16;4,2> mov (8) uwDEST_V(4)<1> ubAVS_RESPONSE(10,1)<16;4,2> mov (8) uwDEST_V(5)<1> ubAVS_RESPONSE(10,8+1)<16;4,2> mov (8) uwDEST_V(6)<1> ubAVS_RESPONSE(11,1)<16;4,2> mov (8) uwDEST_V(7)<1> ubAVS_RESPONSE(11,8+1)<16;4,2> // Move 2nd 8x8 words of Y to dest GRF at higher 8 words of each GRF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2,8)<1> ubAVS_RESPONSE_2(%1,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_Y(%1*2+1,8)<1> ubAVS_RESPONSE_2(%1,8+1)<16;4,2> // Copy high byte in a word } // Move 2st 8x8 words of U to dest GRF (Copy high byte in a word) mov (8) uwDEST_U(0,8)<1> ubAVS_RESPONSE_2(4,1)<16;4,2> mov (8) uwDEST_U(1,8)<1> ubAVS_RESPONSE_2(4,8+1)<16;4,2> mov (8) uwDEST_U(2,8)<1> ubAVS_RESPONSE_2(5,1)<16;4,2> mov (8) uwDEST_U(3,8)<1> ubAVS_RESPONSE_2(5,8+1)<16;4,2> mov (8) uwDEST_U(4,8)<1> ubAVS_RESPONSE_2(8,1)<16;4,2> mov (8) uwDEST_U(5,8)<1> ubAVS_RESPONSE_2(8,8+1)<16;4,2> mov (8) uwDEST_U(6,8)<1> ubAVS_RESPONSE_2(9,1)<16;4,2> mov (8) uwDEST_U(7,8)<1> ubAVS_RESPONSE_2(9,8+1)<16;4,2> // Move 2st 8x8 words of V to dest GRF mov (8) uwDEST_V(0,8)<1> ubAVS_RESPONSE_2(6,1)<16;4,2> mov (8) uwDEST_V(1,8)<1> ubAVS_RESPONSE_2(6,8+1)<16;4,2> mov (8) uwDEST_V(2,8)<1> ubAVS_RESPONSE_2(7,1)<16;4,2> mov (8) uwDEST_V(3,8)<1> ubAVS_RESPONSE_2(7,8+1)<16;4,2> mov (8) uwDEST_V(4,8)<1> ubAVS_RESPONSE_2(10,1)<16;4,2> mov (8) uwDEST_V(5,8)<1> ubAVS_RESPONSE_2(10,8+1)<16;4,2> mov (8) uwDEST_V(6,8)<1> ubAVS_RESPONSE_2(11,1)<16;4,2> mov (8) uwDEST_V(7,8)<1> ubAVS_RESPONSE_2(11,8+1)<16;4,2> #endif // Re-define new # of lines #undef nUV_NUM_OF_ROWS #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 #define nUV_NUM_OF_ROWS 8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL2_AVS_IEF_Unpack_8x4.asm000066400000000000000000000035351231401140700315140ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL2_AVS_IEF_8x4.asm ---------- // Move first 8x8 words of Y to dest GRF at lower 8 words of each RGF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2)<1> ubAVS_RESPONSE(%1,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_Y(%1*2+1)<1> ubAVS_RESPONSE(%1,8+1)<16;4,2> // Copy high byte in a word } // Move 8x4 words of U to dest GRF (Copy high byte in a word) mov (8) uwDEST_U(0)<1> ubAVS_RESPONSE(4,1)<16;4,2> mov (8) uwDEST_U(0,8)<1> ubAVS_RESPONSE(5,1)<16;4,2> mov (8) uwDEST_U(1)<1> ubAVS_RESPONSE(8,1)<16;4,2> mov (8) uwDEST_U(1,8)<1> ubAVS_RESPONSE(9,1)<16;4,2> // Move 8x4 words of V to dest GRF mov (8) uwDEST_V(0)<1> ubAVS_RESPONSE(6,1)<16;4,2> mov (8) uwDEST_V(0,8)<1> ubAVS_RESPONSE(7,1)<16;4,2> mov (8) uwDEST_V(1)<1> ubAVS_RESPONSE(10,1)<16;4,2> mov (8) uwDEST_V(1,8)<1> ubAVS_RESPONSE(11,1)<16;4,2> // Move 2nd 8x8 words of Y to dest GRF at higher 8 words of each GRF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2,8)<1> ubAVS_RESPONSE_2(%1,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_Y(%1*2+1,8)<1> ubAVS_RESPONSE_2(%1,8+1)<16;4,2> // Copy high byte in a word } //------------------------------------------------------------------------------ // Re-define new # of lines #undef nUV_NUM_OF_ROWS #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 #define nUV_NUM_OF_ROWS 4 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL2_AVS_IEF_Unpack_8x8.asm000066400000000000000000000046431231401140700315210ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL2_AVS_IEF_8x8.asm ---------- // Move first 8x8 words of Y to dest GRF at lower 8 words of each RGF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2)<1> ubAVS_RESPONSE(%1,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_Y(%1*2+1)<1> ubAVS_RESPONSE(%1,8+1)<16;4,2> // Copy high byte in a word } // Move 8x8 words of U to dest GRF (Copy high byte in a word) mov (8) uwDEST_U(0)<1> ubAVS_RESPONSE(4,1)<16;4,2> mov (8) uwDEST_U(0,8)<1> ubAVS_RESPONSE(4,8+1)<16;4,2> mov (8) uwDEST_U(1)<1> ubAVS_RESPONSE(5,1)<16;4,2> mov (8) uwDEST_U(1,8)<1> ubAVS_RESPONSE(5,8+1)<16;4,2> mov (8) uwDEST_U(2)<1> ubAVS_RESPONSE(8,1)<16;4,2> mov (8) uwDEST_U(2,8)<1> ubAVS_RESPONSE(8,8+1)<16;4,2> mov (8) uwDEST_U(3)<1> ubAVS_RESPONSE(9,1)<16;4,2> mov (8) uwDEST_U(3,8)<1> ubAVS_RESPONSE(9,8+1)<16;4,2> // Move 8x8 words of V to dest GRF mov (8) uwDEST_V(0)<1> ubAVS_RESPONSE(6,1)<16;4,2> mov (8) uwDEST_V(0,8)<1> ubAVS_RESPONSE(6,8+1)<16;4,2> mov (8) uwDEST_V(1)<1> ubAVS_RESPONSE(7,1)<16;4,2> mov (8) uwDEST_V(1,8)<1> ubAVS_RESPONSE(7,8+1)<16;4,2> mov (8) uwDEST_V(2)<1> ubAVS_RESPONSE(10,1)<16;4,2> mov (8) uwDEST_V(2,8)<1> ubAVS_RESPONSE(10,8+1)<16;4,2> mov (8) uwDEST_V(3)<1> ubAVS_RESPONSE(11,1)<16;4,2> mov (8) uwDEST_V(3,8)<1> ubAVS_RESPONSE(11,8+1)<16;4,2> // Move 2nd 8x8 words of Y to dest GRF at higher 8 words of each GRF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2,8)<1> ubAVS_RESPONSE_2(%1,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_Y(%1*2+1,8)<1> ubAVS_RESPONSE_2(%1,8+1)<16;4,2> // Copy high byte in a word } //------------------------------------------------------------------------------ // Re-define new # of lines #undef nUV_NUM_OF_ROWS #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 #define nUV_NUM_OF_ROWS 8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL2_Scaling.asm000066400000000000000000000063541231401140700277560ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL2_Scaling.asm ---------- #include "Scaling.inc" // Build 16 elements ramp in float32 and normalized it // mov (8) SAMPLER_RAMP(0)<1> 0x76543210:v // add (8) SAMPLER_RAMP(1)<1> SAMPLER_RAMP(0) 8.0:f mov (4) SAMPLER_RAMP(0)<1> 0x48403000:vf //3, 2, 1, 0 in float vector mov (4) SAMPLER_RAMP(0,4)<1> 0x5C585450:vf //7, 6, 5, 4 in float vector add (8) SAMPLER_RAMP(1)<1> SAMPLER_RAMP(0) 8.0:f //Module: PrepareScaleCoord.asm // Setup for sampler msg hdr mov (2) rMSGSRC.0<1>:ud 0:ud { NoDDClr } // Unused fields mov (1) rMSGSRC.2<1>:ud 0:ud { NoDDChk } // Write and offset // Calculate 16 v based on the step Y and vertical origin mov (16) mfMSGPAYLOAD(2)<1> fSRC_VID_V_ORI<0;1,0>:f mov (16) SCALE_COORD_Y<1>:f fSRC_VID_V_ORI<0;1,0>:f // Calculate 16 u based on the step X and hori origin // line (16) mfMSGPAYLOAD(0)<1> SCALE_STEP_X<0;1,0>:f SAMPLER_RAMP(0) // Assign to mrf directly mov (16) acc0:f fSRC_VID_H_ORI<0;1,0>:f { Compr } mac (16) mfMSGPAYLOAD(0)<1> fVIDEO_STEP_X<0;1,0>:f SAMPLER_RAMP(0) { Compr } //Setup the constants for line instruction mov (1) SCALE_LINE_P255<1>:f 255.0:f { NoDDClr } //{ NoDDClr, NoDDChk } mov (1) SCALE_LINE_P0_5<1>:f 0.5:f { NoDDChk } //------------------------------------------------------------------------------ $for (0; :ud // Copy msg header and payload mirrors to MRFs send (16) SCALE_RESPONSE_YW(0)<1> MSGHDR_SCALE udDUMMY_NULL nSMPL_ENGINE SMPLR_MSG_DSC+nSI_SRC_SIMD16_Y+nBI_CURRENT_SRC_Y send (16) SCALE_RESPONSE_UW(0)<1> MSGHDR_SCALE udDUMMY_NULL nSMPL_ENGINE SMPLR_MSG_DSC+nSI_SRC_SIMD16_UV+nBI_CURRENT_SRC_UV // Calculate 16 v for next line add (16) mfMSGPAYLOAD(2)<1> SCALE_COORD_Y<8;8,1>:f fVIDEO_STEP_Y<0;1,0>:f // Assign to mrf directly add (16) SCALE_COORD_Y<1>:f SCALE_COORD_Y<8;8,1>:f fVIDEO_STEP_Y<0;1,0>:f // Assign to mrf directly // Scale back to [0, 255], convert f to ud line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(0) { Compr } // Process B, V mov (16) SCALE_RESPONSE_YD(0)<1> acc0:f { Compr } line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_UF(0) { Compr } // Process B, V mov (16) SCALE_RESPONSE_UD(0)<1> acc0:f { Compr } line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_UF(2) { Compr } // Process B, V mov (16) SCALE_RESPONSE_UD(2)<1> acc0:f { Compr } mov (16) DEST_Y(%1)<1> SCALE_RESPONSE_YB(0) //possible error due to truncation - vK mov (16) DEST_U(%1)<1> SCALE_RESPONSE_UB(0) //possible error due to truncation - vK mov (16) DEST_V(%1)<1> SCALE_RESPONSE_UB(2) //possible error due to truncation - vK } #define nSRC_REGION nREGION_1 //------------------------------------------------------------------------------ intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL3_AVS_IEF_16x8.asm000066400000000000000000000066261231401140700303030ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL3_AVS_IEF_16x8.asm ---------- #include "AVS_IEF.inc" //------------------------------------------------------------------------------ // 2 sampler reads for 8x8 Y surface // 2 sampler read for 8x8 U surface // 2 sampler read for 8x8 V surface //------------------------------------------------------------------------------ // 1st 8x8 setup #include "AVS_SetupFirstBlock.asm" // 1st 8x8 Y sampling mov (1) rAVS_8x8_HDR.2:ud nAVS_GREEN_CHANNEL_ONLY:ud // Enable green channel mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(0)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_Y+nBI_CURRENT_SRC_Y // Return Y in 4 GRFs // 1st 8x8 U sampling mov (1) rAVS_8x8_HDR.2:ud nAVS_RED_CHANNEL_ONLY:ud // Enable red channel mov (16) mAVS_8x8_HDR_UV.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(4)<1> mAVS_8x8_HDR_UV udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_U+nBI_CURRENT_SRC_U // Return U in 4 GRFs // 1st 8x8 V sampling mov (1) rAVS_8x8_HDR.2:ud nAVS_RED_CHANNEL_ONLY:ud // Dummy instruction to avoid back-2-back send instructions mov (16) mAVS_8x8_HDR_UV.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(8)<1> mAVS_8x8_HDR_UV udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_V+nBI_CURRENT_SRC_V // Return V in 4 GRFs // 2nd 8x8 setup #include "AVS_SetupSecondBlock.asm" // 2nd 8x8 Y sampling mov (1) rAVS_8x8_HDR.2:ud nAVS_GREEN_CHANNEL_ONLY:ud // Enable green channel mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE_2(0)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_Y+nBI_CURRENT_SRC_Y // Return Y in 4 GRFs // 2nd 8x8 U sampling mov (1) rAVS_8x8_HDR.2:ud nAVS_RED_CHANNEL_ONLY:ud // Enable red channel mov (16) mAVS_8x8_HDR_UV.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE_2(4)<1> mAVS_8x8_HDR_UV udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_U+nBI_CURRENT_SRC_U // Return U in 4 GRFs mov (1) rAVS_8x8_HDR.2:ud nAVS_RED_CHANNEL_ONLY:ud // Dummy instruction just in order to avoid back-2-back send instructions! // 2nd 8x8 V sampling mov (16) mAVS_8x8_HDR_UV.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE_2(8)<1> mAVS_8x8_HDR_UV udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_V+nBI_CURRENT_SRC_V // Return V in 4 GRFs //------------------------------------------------------------------------------ // Unpacking sampler reads to 4:4:4 internal planar //------------------------------------------------------------------------------ #include "PL3_AVS_IEF_Unpack_16x8.asm" intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL3_AVS_IEF_8x4.asm000066400000000000000000000055631231401140700302170ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL3_AVS_IEF_8x4.asm ---------- #include "AVS_IEF.inc" //------------------------------------------------------------------------------ // 2 sampler reads for 8x8 Y surface // 1 sampler read for 8x8 U surface // 1 sampler read for 8x8 V surface //------------------------------------------------------------------------------ // 1st 8x8 setup #include "AVS_SetupFirstBlock.asm" // 1st 8x8 Y sampling mov (1) rAVS_8x8_HDR.2:ud nAVS_GREEN_CHANNEL_ONLY:ud // Enable green channel mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(0)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_Y+nBI_CURRENT_SRC_Y // Return Y in 4 GRFs // 8x8 U sampling ; Only 8x4 will be used mov (1) rAVS_8x8_HDR.2:ud nAVS_RED_CHANNEL_ONLY:ud // Enable red channel mul (1) rAVS_PAYLOAD.1:f fVIDEO_STEP_X:f 2.0:f // Calculate Step X for chroma mov (16) mAVS_8x8_HDR_UV.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(4)<1> mAVS_8x8_HDR_UV udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_U+nBI_CURRENT_SRC_U // Return U in 4 GRFs // 8x8 V sampling ; Only 8x4 will be used mov (1) rAVS_8x8_HDR.2:ud nAVS_RED_CHANNEL_ONLY:ud // Dummy instruction just in order to avoid back-2-back send instructions! mov (16) mAVS_8x8_HDR_UV.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(8)<1> mAVS_8x8_HDR_UV udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_V+nBI_CURRENT_SRC_V // Return V in 4 GRFs // 2nd 8x8 setup #include "AVS_SetupSecondBlock.asm" // 2nd 8x8 Y sampling mov (1) rAVS_8x8_HDR.2:ud nAVS_GREEN_CHANNEL_ONLY:ud // Enable green channel mov (1) rAVS_PAYLOAD.1:f fVIDEO_STEP_X:f // Restore Step X for luma mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(12)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_Y+nBI_CURRENT_SRC_Y // Return Y in 4 GRFs //------------------------------------------------------------------------------ // Unpacking sampler reads to 4:2:0 internal planar //------------------------------------------------------------------------------ #include "PL3_AVS_IEF_Unpack_8x4.asm" intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL3_AVS_IEF_8x8.asm000066400000000000000000000055061231401140700302200ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL3_AVS_IEF_8x8.asm ---------- #include "AVS_IEF.inc" //------------------------------------------------------------------------------ // 2 sampler reads for 8x8 Y surface // 1 sampler read for 8x8 U surface // 1 sampler read for 8x8 V surface //------------------------------------------------------------------------------ // 1st 8x8 setup #include "AVS_SetupFirstBlock.asm" // 1st 8x8 Y sampling mov (1) rAVS_8x8_HDR.2:ud nAVS_GREEN_CHANNEL_ONLY:ud // Enable green channel mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(0)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_Y+nBI_CURRENT_SRC_Y // Return Y in 4 GRFs // 8x8 U sampling mov (1) rAVS_8x8_HDR.2:ud nAVS_RED_CHANNEL_ONLY:ud // Enable red channel mul (1) rAVS_PAYLOAD.1:f fVIDEO_STEP_X:f 2.0:f // Calculate Step X for chroma mov (16) mAVS_8x8_HDR_UV.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(4)<1> mAVS_8x8_HDR_UV udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_U+nBI_CURRENT_SRC_U // Return U in 4 GRFs // 8x8 V sampling mov (1) rAVS_8x8_HDR.2:ud nAVS_RED_CHANNEL_ONLY:ud // Dummy instruction just in order to avoid back-2-back send instructions! mov (16) mAVS_8x8_HDR_UV.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(8)<1> mAVS_8x8_HDR_UV udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_V+nBI_CURRENT_SRC_V // Return V in 4 GRFs // 2nd 8x8 setup #include "AVS_SetupSecondBlock.asm" // 2nd 8x8 Y sampling mov (1) rAVS_8x8_HDR.2:ud nAVS_GREEN_CHANNEL_ONLY:ud // Enable green channel mov (1) rAVS_PAYLOAD.1:f fVIDEO_STEP_X:f // Restore Step X for luma mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(12)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_1CH+nSI_SRC_Y+nBI_CURRENT_SRC_Y // Return Y in 4 GRFs //------------------------------------------------------------------------------ // Unpacking sampler reads to 4:2:2 internal planar //------------------------------------------------------------------------------ #include "PL3_AVS_IEF_Unpack_8x8.asm" intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL3_AVS_IEF_Unpack_16x8.asm000066400000000000000000000377661231401140700316150ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL3_AVS_IEF_Unpack_16x8.asm ---------- #ifdef AVS_OUTPUT_16_BIT //Output is packed in AVYU format // Move first 8x8 words of Y to dest GRF (as packed) mov (4) uwDEST_Y(0,1)<4> uwAVS_RESPONSE(0,0)<4;4,1> mov (4) uwDEST_Y(1,1)<4> uwAVS_RESPONSE(0,8)<4;4,1> mov (4) uwDEST_Y(4,1)<4> uwAVS_RESPONSE(0,4)<4;4,1> mov (4) uwDEST_Y(5,1)<4> uwAVS_RESPONSE(0,12)<4;4,1> mov (4) uwDEST_Y(8,1)<4> uwAVS_RESPONSE(1,0)<4;4,1> mov (4) uwDEST_Y(9,1)<4> uwAVS_RESPONSE(1,8)<4;4,1> mov (4) uwDEST_Y(12,1)<4> uwAVS_RESPONSE(1,4)<4;4,1> mov (4) uwDEST_Y(13,1)<4> uwAVS_RESPONSE(1,12)<4;4,1> mov (4) uwDEST_Y(16,1)<4> uwAVS_RESPONSE(2,0)<4;4,1> mov (4) uwDEST_Y(17,1)<4> uwAVS_RESPONSE(2,8)<4;4,1> mov (4) uwDEST_Y(20,1)<4> uwAVS_RESPONSE(2,4)<4;4,1> mov (4) uwDEST_Y(21,1)<4> uwAVS_RESPONSE(2,12)<4;4,1> mov (4) uwDEST_Y(24,1)<4> uwAVS_RESPONSE(3,0)<4;4,1> mov (4) uwDEST_Y(25,1)<4> uwAVS_RESPONSE(3,8)<4;4,1> mov (4) uwDEST_Y(28,1)<4> uwAVS_RESPONSE(3,4)<4;4,1> mov (4) uwDEST_Y(29,1)<4> uwAVS_RESPONSE(3,12)<4;4,1> // Move first 8x8 words of U to dest GRF (as packed) mov (4) uwDEST_Y(0,0)<4> uwAVS_RESPONSE(4,0)<4;4,1> mov (4) uwDEST_Y(1,0)<4> uwAVS_RESPONSE(4,8)<4;4,1> mov (4) uwDEST_Y(4,0)<4> uwAVS_RESPONSE(4,4)<4;4,1> mov (4) uwDEST_Y(5,0)<4> uwAVS_RESPONSE(4,12)<4;4,1> mov (4) uwDEST_Y(8,0)<4> uwAVS_RESPONSE(5,0)<4;4,1> mov (4) uwDEST_Y(9,0)<4> uwAVS_RESPONSE(5,8)<4;4,1> mov (4) uwDEST_Y(12,0)<4> uwAVS_RESPONSE(5,4)<4;4,1> mov (4) uwDEST_Y(13,0)<4> uwAVS_RESPONSE(5,12)<4;4,1> mov (4) uwDEST_Y(16,0)<4> uwAVS_RESPONSE(6,0)<4;4,1> mov (4) uwDEST_Y(17,0)<4> uwAVS_RESPONSE(6,8)<4;4,1> mov (4) uwDEST_Y(20,0)<4> uwAVS_RESPONSE(6,4)<4;4,1> mov (4) uwDEST_Y(21,0)<4> uwAVS_RESPONSE(6,12)<4;4,1> mov (4) uwDEST_Y(24,0)<4> uwAVS_RESPONSE(7,0)<4;4,1> mov (4) uwDEST_Y(25,0)<4> uwAVS_RESPONSE(7,8)<4;4,1> mov (4) uwDEST_Y(28,0)<4> uwAVS_RESPONSE(7,4)<4;4,1> mov (4) uwDEST_Y(29,0)<4> uwAVS_RESPONSE(7,12)<4;4,1> // Move first 8x8 words of V to dest GRF (as packed) mov (4) uwDEST_Y(0,2)<4> uwAVS_RESPONSE(8,0)<4;4,1> mov (4) uwDEST_Y(1,2)<4> uwAVS_RESPONSE(8,8)<4;4,1> mov (4) uwDEST_Y(4,2)<4> uwAVS_RESPONSE(8,4)<4;4,1> mov (4) uwDEST_Y(5,2)<4> uwAVS_RESPONSE(8,12)<4;4,1> mov (4) uwDEST_Y(8,2)<4> uwAVS_RESPONSE(9,0)<4;4,1> mov (4) uwDEST_Y(9,2)<4> uwAVS_RESPONSE(9,8)<4;4,1> mov (4) uwDEST_Y(12,2)<4> uwAVS_RESPONSE(9,4)<4;4,1> mov (4) uwDEST_Y(13,2)<4> uwAVS_RESPONSE(9,12)<4;4,1> mov (4) uwDEST_Y(16,2)<4> uwAVS_RESPONSE(10,0)<4;4,1> mov (4) uwDEST_Y(17,2)<4> uwAVS_RESPONSE(10,8)<4;4,1> mov (4) uwDEST_Y(20,2)<4> uwAVS_RESPONSE(10,4)<4;4,1> mov (4) uwDEST_Y(21,2)<4> uwAVS_RESPONSE(10,12)<4;4,1> mov (4) uwDEST_Y(24,2)<4> uwAVS_RESPONSE(11,0)<4;4,1> mov (4) uwDEST_Y(25,2)<4> uwAVS_RESPONSE(11,8)<4;4,1> mov (4) uwDEST_Y(28,2)<4> uwAVS_RESPONSE(11,4)<4;4,1> mov (4) uwDEST_Y(29,2)<4> uwAVS_RESPONSE(11,12)<4;4,1> // Move first 8x8 words of A to dest GRF (as packed) mov (4) uwDEST_Y(0,3)<4> 0:uw mov (4) uwDEST_Y(1,3)<4> 0:uw mov (4) uwDEST_Y(4,3)<4> 0:uw mov (4) uwDEST_Y(5,3)<4> 0:uw mov (4) uwDEST_Y(8,3)<4> 0:uw mov (4) uwDEST_Y(9,3)<4> 0:uw mov (4) uwDEST_Y(12,3)<4> 0:uw mov (4) uwDEST_Y(13,3)<4> 0:uw mov (4) uwDEST_Y(16,3)<4> 0:uw mov (4) uwDEST_Y(17,3)<4> 0:uw mov (4) uwDEST_Y(20,3)<4> 0:uw mov (4) uwDEST_Y(21,3)<4> 0:uw mov (4) uwDEST_Y(24,3)<4> 0:uw mov (4) uwDEST_Y(25,3)<4> 0:uw mov (4) uwDEST_Y(28,3)<4> 0:uw mov (4) uwDEST_Y(29,3)<4> 0:uw // Move second 8x8 words of Y to dest GRF mov (4) uwDEST_Y(2,1)<4> uwAVS_RESPONSE_2(0,0)<4;4,1> mov (4) uwDEST_Y(3,1)<4> uwAVS_RESPONSE_2(0,8)<4;4,1> mov (4) uwDEST_Y(6,1)<4> uwAVS_RESPONSE_2(0,4)<4;4,1> mov (4) uwDEST_Y(7,1)<4> uwAVS_RESPONSE_2(0,12)<4;4,1> mov (4) uwDEST_Y(10,1)<4> uwAVS_RESPONSE_2(1,0)<4;4,1> mov (4) uwDEST_Y(11,1)<4> uwAVS_RESPONSE_2(1,8)<4;4,1> mov (4) uwDEST_Y(14,1)<4> uwAVS_RESPONSE_2(1,4)<4;4,1> mov (4) uwDEST_Y(15,1)<4> uwAVS_RESPONSE_2(1,12)<4;4,1> mov (4) uwDEST_Y(18,1)<4> uwAVS_RESPONSE_2(2,0)<4;4,1> mov (4) uwDEST_Y(19,1)<4> uwAVS_RESPONSE_2(2,8)<4;4,1> mov (4) uwDEST_Y(22,1)<4> uwAVS_RESPONSE_2(2,4)<4;4,1> mov (4) uwDEST_Y(23,1)<4> uwAVS_RESPONSE_2(2,12)<4;4,1> mov (4) uwDEST_Y(26,1)<4> uwAVS_RESPONSE_2(3,0)<4;4,1> mov (4) uwDEST_Y(27,1)<4> uwAVS_RESPONSE_2(3,8)<4;4,1> mov (4) uwDEST_Y(30,1)<4> uwAVS_RESPONSE_2(3,4)<4;4,1> mov (4) uwDEST_Y(31,1)<4> uwAVS_RESPONSE_2(3,12)<4;4,1> // Move second 8x8 words of U to dest GRF mov (4) uwDEST_Y(2,0)<4> uwAVS_RESPONSE_2(4,0)<4;4,1> mov (4) uwDEST_Y(3,0)<4> uwAVS_RESPONSE_2(4,8)<4;4,1> mov (4) uwDEST_Y(6,0)<4> uwAVS_RESPONSE_2(4,4)<4;4,1> mov (4) uwDEST_Y(7,0)<4> uwAVS_RESPONSE_2(4,12)<4;4,1> mov (4) uwDEST_Y(10,0)<4> uwAVS_RESPONSE_2(5,0)<4;4,1> mov (4) uwDEST_Y(11,0)<4> uwAVS_RESPONSE_2(5,8)<4;4,1> mov (4) uwDEST_Y(14,0)<4> uwAVS_RESPONSE_2(5,4)<4;4,1> mov (4) uwDEST_Y(15,0)<4> uwAVS_RESPONSE_2(5,12)<4;4,1> mov (4) uwDEST_Y(18,0)<4> uwAVS_RESPONSE_2(6,0)<4;4,1> mov (4) uwDEST_Y(19,0)<4> uwAVS_RESPONSE_2(6,8)<4;4,1> mov (4) uwDEST_Y(22,0)<4> uwAVS_RESPONSE_2(6,4)<4;4,1> mov (4) uwDEST_Y(23,0)<4> uwAVS_RESPONSE_2(6,12)<4;4,1> mov (4) uwDEST_Y(26,0)<4> uwAVS_RESPONSE_2(7,0)<4;4,1> mov (4) uwDEST_Y(27,0)<4> uwAVS_RESPONSE_2(7,8)<4;4,1> mov (4) uwDEST_Y(30,0)<4> uwAVS_RESPONSE_2(7,4)<4;4,1> mov (4) uwDEST_Y(31,0)<4> uwAVS_RESPONSE_2(7,12)<4;4,1> // Move second 8x8 words of V to dest GRF mov (4) uwDEST_Y(2,2)<4> uwAVS_RESPONSE_2(8,0)<4;4,1> mov (4) uwDEST_Y(3,2)<4> uwAVS_RESPONSE_2(8,8)<4;4,1> mov (4) uwDEST_Y(6,2)<4> uwAVS_RESPONSE_2(8,4)<4;4,1> mov (4) uwDEST_Y(7,2)<4> uwAVS_RESPONSE_2(8,12)<4;4,1> mov (4) uwDEST_Y(10,2)<4> uwAVS_RESPONSE_2(9,0)<4;4,1> mov (4) uwDEST_Y(11,2)<4> uwAVS_RESPONSE_2(9,8)<4;4,1> mov (4) uwDEST_Y(14,2)<4> uwAVS_RESPONSE_2(9,4)<4;4,1> mov (4) uwDEST_Y(15,2)<4> uwAVS_RESPONSE_2(9,12)<4;4,1> mov (4) uwDEST_Y(18,2)<4> uwAVS_RESPONSE_2(10,0)<4;4,1> mov (4) uwDEST_Y(19,2)<4> uwAVS_RESPONSE_2(10,8)<4;4,1> mov (4) uwDEST_Y(22,2)<4> uwAVS_RESPONSE_2(10,4)<4;4,1> mov (4) uwDEST_Y(23,2)<4> uwAVS_RESPONSE_2(10,12)<4;4,1> mov (4) uwDEST_Y(26,2)<4> uwAVS_RESPONSE_2(11,0)<4;4,1> mov (4) uwDEST_Y(27,2)<4> uwAVS_RESPONSE_2(11,8)<4;4,1> mov (4) uwDEST_Y(30,2)<4> uwAVS_RESPONSE_2(11,4)<4;4,1> mov (4) uwDEST_Y(31,2)<4> uwAVS_RESPONSE_2(11,12)<4;4,1> // Move second 8x8 words of A to dest GRF mov (4) uwDEST_Y(2,3)<4> 0:uw mov (4) uwDEST_Y(3,3)<4> 0:uw mov (4) uwDEST_Y(6,3)<4> 0:uw mov (4) uwDEST_Y(7,3)<4> 0:uw mov (4) uwDEST_Y(10,3)<4> 0:uw mov (4) uwDEST_Y(11,3)<4> 0:uw mov (4) uwDEST_Y(14,3)<4> 0:uw mov (4) uwDEST_Y(15,3)<4> 0:uw mov (4) uwDEST_Y(18,3)<4> 0:uw mov (4) uwDEST_Y(19,3)<4> 0:uw mov (4) uwDEST_Y(22,3)<4> 0:uw mov (4) uwDEST_Y(23,3)<4> 0:uw mov (4) uwDEST_Y(26,3)<4> 0:uw mov (4) uwDEST_Y(27,3)<4> 0:uw mov (4) uwDEST_Y(30,3)<4> 0:uw mov (4) uwDEST_Y(31,3)<4> 0:uw /* This section will be used if 16-bit output is needed in planar format -vK // Move 1st 8x8 words of Y to dest GRF at lower 8 words of each RGF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2)<1> uwAVS_RESPONSE(%1)<8;4,1> mov (8) uwDEST_Y(%1*2+1)<1> uwAVS_RESPONSE(%1,8)<8;4,1> } // Move 8x8 words of U to dest GRF $for(0; <8/2; 1) { mov (8) uwDEST_U(%1*2)<1> uwAVS_RESPONSE(%1+4)<8;4,1> mov (8) uwDEST_U(%1*2+1)<1> uwAVS_RESPONSE(%1+4,8)<8;4,1> } // Move 8x8 words of V to dest GRF $for(0; <8/2; 1) { mov (8) uwDEST_V(%1*2)<1> uwAVS_RESPONSE(%1+8)<8;4,1> mov (8) uwDEST_V(%1*2+1)<1> uwAVS_RESPONSE(%1+8,8)<8;4,1> } // Move 2nd 8x8 words of Y to dest GRF $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2,8)<1> uwAVS_RESPONSE_2(%1)<8;4,1> mov (8) uwDEST_Y(%1*2+1,8)<1> uwAVS_RESPONSE_2(%1,8)<8;4,1> } // Move 2nd 8x8 words of U to dest GRF $for(0; <8/2; 1) { mov (8) uwDEST_U(%1*2,8)<1> uwAVS_RESPONSE_2(%1+4)<8;4,1> mov (8) uwDEST_U(%1*2+1,8)<1> uwAVS_RESPONSE_2(%1+4,8)<8;4,1> } // Move 2nd 8x8 words of V to dest GRF $for(0; <8/2; 1) { mov (8) uwDEST_V(%1*2,8)<1> uwAVS_RESPONSE_2(%1+8)<8;4,1> mov (8) uwDEST_V(%1*2+1,8)<1> uwAVS_RESPONSE_2(%1+8,8)<8;4,1> } */ #else /* OUTPUT_8_BIT */ // Move 1st 8x8 words of Y to dest GRF at lower 8 words of each RGF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2)<1> ubAVS_RESPONSE(%1,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_Y(%1*2+1)<1> ubAVS_RESPONSE(%1,8+1)<16;4,2> // Copy high byte in a word } // Move 8x8 words of U to dest GRF $for(0; <8/2; 1) { mov (8) uwDEST_U(%1*2)<1> ubAVS_RESPONSE(%1+4,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_U(%1*2+1)<1> ubAVS_RESPONSE(%1+4,8+1)<16;4,2> // Copy high byte in a word } // Move 8x8 words of V to dest GRF $for(0; <8/2; 1) { mov (8) uwDEST_V(%1*2)<1> ubAVS_RESPONSE(%1+8,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_V(%1*2+1)<1> ubAVS_RESPONSE(%1+8,8+1)<16;4,2> // Copy high byte in a word } // Move 2nd 8x8 words of Y to dest GRF at higher 8 words of each RGF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2,8)<1> ubAVS_RESPONSE_2(%1,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_Y(%1*2+1,8)<1> ubAVS_RESPONSE_2(%1,8+1)<16;4,2> // Copy high byte in a word } // Move 2nd 8x8 words of U to dest GRF $for(0; <8/2; 1) { mov (8) uwDEST_U(%1*2,8)<1> ubAVS_RESPONSE_2(%1+4,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_U(%1*2+1,8)<1> ubAVS_RESPONSE_2(%1+4,8+1)<16;4,2> // Copy high byte in a word } // Move 2nd 8x8 words of V to dest GRF $for(0; <8/2; 1) { mov (8) uwDEST_V(%1*2,8)<1> ubAVS_RESPONSE_2(%1+8,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_V(%1*2+1,8)<1> ubAVS_RESPONSE_2(%1+8,8+1)<16;4,2> // Copy high byte in a word } #endif //------------------------------------------------------------------------------ // Re-define new # of lines #undef nUV_NUM_OF_ROWS #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 #define nUV_NUM_OF_ROWS 8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL3_AVS_IEF_Unpack_8x4.asm000066400000000000000000000036041231401140700315120ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL3_AVS_IEF_Unpack_8x4.asm ---------- // Move 1st 8x8 words of Y to dest GRF at lower 8 words of each RGF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2)<1> ubAVS_RESPONSE(%1,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_Y(%1*2+1)<1> ubAVS_RESPONSE(%1,8+1)<16;4,2> // Copy high byte in a word } // Move 8x4 words of U to dest GRF (Copy high byte in a word) mov (8) uwDEST_U(0)<1> ubAVS_RESPONSE(4,1)<16;4,2> mov (8) uwDEST_U(0,8)<1> ubAVS_RESPONSE(4,9)<16;4,2> mov (8) uwDEST_U(1)<1> ubAVS_RESPONSE(5,1)<16;4,2> mov (8) uwDEST_U(1,8)<1> ubAVS_RESPONSE(5,9)<16;4,2> // Move 8x4 words of V to dest GRF mov (8) uwDEST_V(0)<1> ubAVS_RESPONSE(8,1)<16;4,2> mov (8) uwDEST_V(0,8)<1> ubAVS_RESPONSE(8,9)<16;4,2> mov (8) uwDEST_V(1)<1> ubAVS_RESPONSE(9,1)<16;4,2> mov (8) uwDEST_V(1,8)<1> ubAVS_RESPONSE(9,9)<16;4,2> // Move 2nd 8x8 words of Y to dest GRF at higher 8 words of each RGF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2,8)<1> ubAVS_RESPONSE(%1+12,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_Y(%1*2+1,8)<1> ubAVS_RESPONSE(%1+12,8+1)<16;4,2> // Copy high byte in a word } //------------------------------------------------------------------------------ // Re-define new # of lines #undef nUV_NUM_OF_ROWS #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 #define nUV_NUM_OF_ROWS 4 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL3_AVS_IEF_Unpack_8x8.asm000066400000000000000000000034311231401140700315140ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL3_AVS_IEF_Unpack_8x8.asm ---------- // Move 1st 8x8 words of Y to dest GRF at lower 8 words of each RGF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2)<1> ubAVS_RESPONSE(%1,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_Y(%1*2+1)<1> ubAVS_RESPONSE(%1,8+1)<16;4,2> // Copy high byte in a word } // Move 8x8 words of U to dest GRF $for(0; <8/2; 1) { mov (8) uwDEST_U(%1)<1> ubAVS_RESPONSE(%1+4,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_U(%1,8)<1> ubAVS_RESPONSE(%1+4,8+1)<16;4,2> // Copy high byte in a word } // Move 8x8 words of V to dest GRF $for(0; <8/2; 1) { mov (8) uwDEST_V(%1)<1> ubAVS_RESPONSE(%1+8,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_V(%1,8)<1> ubAVS_RESPONSE(%1+8,8+1)<16;4,2> // Copy high byte in a word } // Move 2nd 8x8 words of Y to dest GRF at higher 8 words of each RGF. $for(0; <8/2; 1) { mov (8) uwDEST_Y(%1*2,8)<1> ubAVS_RESPONSE(%1+12,1)<16;4,2> // Copy high byte in a word mov (8) uwDEST_Y(%1*2+1,8)<1> ubAVS_RESPONSE(%1+12,8+1)<16;4,2> // Copy high byte in a word } //------------------------------------------------------------------------------ // Re-define new # of lines #undef nUV_NUM_OF_ROWS #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 #define nUV_NUM_OF_ROWS 8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL3_Scaling.asm000066400000000000000000000065731231401140700277620ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- PL3_Scaling.asm ---------- #include "Scaling.inc" // Build 16 elements ramp in float32 and normalized it // mov (8) SAMPLER_RAMP(0)<1> 0x76543210:v // add (8) SAMPLER_RAMP(1)<1> SAMPLER_RAMP(0) 8.0:f mov (4) SAMPLER_RAMP(0)<1> 0x48403000:vf { NoDDClr }//3, 2, 1, 0 in float vector mov (4) SAMPLER_RAMP(0,4)<1> 0x5C585450:vf { NoDDChk }//7, 6, 5, 4 in float vector add (8) SAMPLER_RAMP(1)<1> SAMPLER_RAMP(0) 8.0:f //Module: PrepareScaleCoord.asm // Setup for sampler msg hdr mov (2) rMSGSRC.0<1>:ud 0:ud { NoDDClr } // Unused fields mov (1) rMSGSRC.2<1>:ud 0:ud { NoDDChk } // Write and offset // Calculate 16 v based on the step Y and vertical origin mov (16) mfMSGPAYLOAD(2)<1> fSRC_VID_V_ORI<0;1,0>:f mov (16) SCALE_COORD_Y<1>:f fSRC_VID_V_ORI<0;1,0>:f // Calculate 16 u based on the step X and hori origin // line (16) mfMSGPAYLOAD(0)<1> SCALE_STEP_X<0;1,0>:f SAMPLER_RAMP(0) // Assign to mrf directly mov (16) acc0:f fSRC_VID_H_ORI<0;1,0>:f { Compr } mac (16) mfMSGPAYLOAD(0)<1> fVIDEO_STEP_X<0;1,0>:f SAMPLER_RAMP(0) { Compr } //Setup the constants for line instruction mov (1) SCALE_LINE_P255<1>:f 255.0:f { NoDDClr } //{ NoDDClr, NoDDChk } mov (1) SCALE_LINE_P0_5<1>:f 0.5:f { NoDDChk } //------------------------------------------------------------------------------ $for (0; :ud rMSGSRC<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (16) SCALE_RESPONSE_VW(0)<1> MSGHDR_SCALE udDUMMY_NULL nSMPL_ENGINE SMPLR_MSG_DSC+nSI_SRC_SIMD16_V+nBI_CURRENT_SRC_V send (16) SCALE_RESPONSE_YW(0)<1> MSGHDR_SCALE udDUMMY_NULL nSMPL_ENGINE SMPLR_MSG_DSC+nSI_SRC_SIMD16_Y+nBI_CURRENT_SRC_Y send (16) SCALE_RESPONSE_UW(0)<1> MSGHDR_SCALE udDUMMY_NULL nSMPL_ENGINE SMPLR_MSG_DSC+nSI_SRC_SIMD16_U+nBI_CURRENT_SRC_U // Calculate 16 v for next line add (16) mfMSGPAYLOAD(2)<1> SCALE_COORD_Y<8;8,1>:f fVIDEO_STEP_Y<0;1,0>:f // Assign to mrf directly add (16) SCALE_COORD_Y<1>:f SCALE_COORD_Y<8;8,1>:f fVIDEO_STEP_Y<0;1,0>:f // Assign to mrf directly // Scale back to [0, 255], convert f to ud line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_VF(0) { Compr } // Process B, V mov (16) SCALE_RESPONSE_VD(0)<1> acc0:f { Compr } line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(0) { Compr } // Process B, V mov (16) SCALE_RESPONSE_YD(0)<1> acc0:f { Compr } line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_UF(0) { Compr } // Process B, V mov (16) SCALE_RESPONSE_UD(0)<1> acc0:f { Compr } mov (16) DEST_V(%1)<1> SCALE_RESPONSE_VB(0) //possible error due to truncation - vK mov (16) DEST_Y(%1)<1> SCALE_RESPONSE_YB(0) //possible error due to truncation - vK mov (16) DEST_U(%1)<1> SCALE_RESPONSE_UB(0) //possible error due to truncation - vK } #define nSRC_REGION nREGION_1 //------------------------------------------------------------------------------ intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG.asm000066400000000000000000000072371231401140700275160ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #define DI_ENABLE #include "DNDI.inc" #ifdef DI_ONLY #undef nSMPL_RESP_LEN #define nSMPL_RESP_LEN nSMPL_RESP_LEN_DI // set the number of GRF #else #undef nSMPL_RESP_LEN #define nSMPL_RESP_LEN nSMPL_RESP_LEN_DNDI // set the number of GRF #endif #undef nDPW_BLOCK_SIZE_HIST #define nDPW_BLOCK_SIZE_HIST nBLOCK_WIDTH_4+nBLOCK_HEIGHT_1 // HIST Block Size for Write is 4x2 #undef nDPW_BLOCK_SIZE_DN #define nDPW_BLOCK_SIZE_DN nBLOCK_WIDTH_16+nBLOCK_HEIGHT_4 // DN Block Size for Write is 16x4 ////////////////////////////////////// Run the DN Algorithm /////////////////////////////////////// #include "DNDI_Command.asm" ////////////////////////////////////// Rearrange for Internal Planar ////////////////////////////// ////////////////////////////////////// Save the STMM Data for Next Run ///////////////////////// // Write STMM to memory shr (1) rMSGSRC.0<1>:ud wORIX<0;1,0>:w 1:w NODDCLR_NODDCHK // X origin / 2 mov (1) rMSGSRC.1<1>:ud wORIY<0;1,0>:w NODDCLR_NODDCHK // Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_STMM:ud NODDCHK // block width and height (8x4) mov (8) mudMSGHDR_STMM(0)<1> rMSGSRC.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udRESP(nDI_STMM_OFFSET,0) // Move STMM to MRF send (8) dNULLREG mMSGHDR_STMM udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_STMM+nBI_STMM_HISTORY_OUTPUT:ud #ifdef DI_ONLY #else ////////////////////////////////////// Save the History Data for Next Run ///////////////////////// #include "DI_Hist_Save.asm" ////////////////////////////////////// Save the DN Curr Frame for Next Run //////////////////////// //set the save DN parameters mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w NODDCLR // X origin and Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud NODDCLR_NODDCHK // block width and height (16x4) mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud // check top/bottom field first cmp.e.f0.0 (1) null<1>:w ubTFLD_FIRST<0;1,0>:ub 1:w (f0.0) jmpi (1) TOP_FIELD_FIRST BOTTOM_FIELD_FIRST: $for (0,0; udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 2nd field luma from current frame (line 0,2) } $for (0,0; udRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,4)<4;4,1> // 1st field luma from current frame (line 1,3) } jmpi (1) SAVE_DN_CURR TOP_FIELD_FIRST: $for (0,0; udRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,0)<4;4,1> // 2nd field luma from current frame (line 0,2) } $for (0,0; udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 1st field luma from current frame (line 1,3) } SAVE_DN_CURR: send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PL_DN_DI+nBI_DESTINATION_Y:ud #endif // Save Processed frames #include "DI_Save_PA.asm" intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV11.asm000066400000000000000000000134251231401140700315240ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #define DI_ENABLE #include "DNDI.inc" #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 // Number of Y rows per block (4 rows for each frame) #undef nUV_NUM_OF_ROWS #define nUV_NUM_OF_ROWS 8 // Number of U/V rows per block #undef nSMPL_RESP_LEN #define nSMPL_RESP_LEN nSMPL_RESP_LEN_DNDI // set the number of GRF #undef nDPW_BLOCK_SIZE_HIST #define nDPW_BLOCK_SIZE_HIST nBLOCK_WIDTH_4+nBLOCK_HEIGHT_1 // HIST Block Size for Write is 4x2 #undef nDPW_BLOCK_SIZE_DN #define nDPW_BLOCK_SIZE_DN nBLOCK_WIDTH_16+nBLOCK_HEIGHT_4 // DN Block Size for Write is 16x4 #undef nDPR_BLOCK_SIZE_UV #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_8+nBLOCK_HEIGHT_4 // DN Block Size for UV Write/Read is 8x4 ////////////////////////////////////// Run the DN Algorithm /////////////////////////////////////// #include "DNDI_Command.asm" ////////////////////////////////////// Rearrange for Internal Planar ////////////////////////////// // move the previous frame Y component to internal planar format $for (0; ubRESP(nDI_PREV_FRAME_LUMA_OFFSET,%1*16) } // move the previous frame U,V components to internal planar format $for (0; ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels mov (8) uwDEST_V(0,%1*8)<1> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //V pixels } // move the current frame Y component to internal planar format $for (0; ubRESP(nDI_CURR_FRAME_LUMA_OFFSET,%1*16) } // move the current frame U,V components to internal planar format $for (0; ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels mov (8) uwDEST_V(2,%1*8)<1> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //V pixels } ////////////////////////////////////// Save the STMM Data for Next Run ///////////////////////// // Write STMM to memory shr (1) rMSGSRC.0<1>:ud wORIX<0;1,0>:w 1:w // X origin / 2 mov (1) rMSGSRC.1<1>:ud wORIY<0;1,0>:w // Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_STMM:ud // block width and height (8x4) mov (8) mudMSGHDR_STMM(0)<1> rMSGSRC.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udRESP(nDI_STMM_OFFSET,0) // Move STMM to MRF send (8) dNULLREG mMSGHDR_STMM udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_STMM+nBI_STMM_HISTORY_OUTPUT:ud ////////////////////////////////////// Save the History Data for Next Run ///////////////////////// #include "DI_Hist_Save.asm" ////////////////////////////////////// Save the DN Curr Frame for Next Run //////////////////////// add (4) pCF_Y_OFFSET<1>:uw ubSRC_CF_OFFSET<4;4,1>:ub npDN_YUV:w // check top/bottom field first cmp.e.f0.0 (1) null<1>:w ubTFLD_FIRST<0;1,0>:ub 1:w (f0.0) jmpi (1) TOP_FIELD_FIRST BOTTOM_FIELD_FIRST: $for (0,0; udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN(1,%1*4+4)<1> udRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,4)<4;4,1> // 1st field luma from current frame (line 1,3) } jmpi (1) SAVE_DN_CURR TOP_FIELD_FIRST: $for (0,0; udRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,0)<4;4,1> // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN(1,%1*4+4)<1> udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 1st field luma from current frame (line 1,3) } SAVE_DN_CURR: mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud // block width and height (16x4) mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PL_DN_DI+nBI_DESTINATION_Y:ud /////////////////////////////P208 UV Copy 422///////////////////////////////////////////////////// //Read UV through DATAPORT add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin asr (1) rMSGSRC.0<1>:d rMSGSRC.0<0;1,0>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // U/V block width and height (16x2) mov (8) mudMSGHDR_DN<1> rMSGSRC<8;8,1>:ud send (8) udBOT_U_IO(0)<1> mMSGHDR_DN udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nRESLEN_1+nBI_CURRENT_SRC_UV:ud //Write UV through DATAPORT mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin asr (1) rMSGSRC.0<1>:d rMSGSRC.0<0;1,0>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // block width and height (16x2) mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud mov (8) mudMSGHDR_DN(1)<1> udBOT_U_IO(0)<8;8,1> send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nMSGLEN_1+nBI_DESTINATION_UV:udintel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm000066400000000000000000000131721231401140700315240ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #define DI_ENABLE #include "DNDI.inc" #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 // Number of Y rows per block (4 rows for each frame) #undef nUV_NUM_OF_ROWS #define nUV_NUM_OF_ROWS 8 // Number of U/V rows per block #undef nSMPL_RESP_LEN #define nSMPL_RESP_LEN nSMPL_RESP_LEN_DNDI // set the number of GRF #undef nDPW_BLOCK_SIZE_HIST #define nDPW_BLOCK_SIZE_HIST nBLOCK_WIDTH_4+nBLOCK_HEIGHT_1 // HIST Block Size for Write is 4x2 #undef nDPW_BLOCK_SIZE_DN #define nDPW_BLOCK_SIZE_DN nBLOCK_WIDTH_16+nBLOCK_HEIGHT_4 // DN Block Size for Write is 16x4 #undef nDPR_BLOCK_SIZE_UV #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_16+nBLOCK_HEIGHT_2 // DN Block Size for UV Write/Read is 16x2 ////////////////////////////////////// Run the DN Algorithm /////////////////////////////////////// #include "DNDI_COMMAND.asm" ////////////////////////////////////// Rearrange for Internal Planar ////////////////////////////// // move the previous frame Y component to internal planar format $for (0; ubRESP(nDI_PREV_FRAME_LUMA_OFFSET,%1*16) } // move the previous frame U,V components to internal planar format $for (0; ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels mov (8) uwDEST_V(0,%1*8)<1> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //V pixels } // move the current frame Y component to internal planar format $for (0; ubRESP(nDI_CURR_FRAME_LUMA_OFFSET,%1*16) } // move the current frame U,V components to internal planar format $for (0; ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels mov (8) uwDEST_V(2,%1*8)<1> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //V pixels } ////////////////////////////////////// Save the STMM Data for Next Run ///////////////////////// // Write STMM to memory shr (1) rMSGSRC.0<1>:ud wORIX<0;1,0>:w 1:w // X origin / 2 mov (1) rMSGSRC.1<1>:ud wORIY<0;1,0>:w // Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_STMM:ud // block width and height (8x4) mov (8) mudMSGHDR_STMM(0)<1> rMSGSRC.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udRESP(nDI_STMM_OFFSET,0) // Move STMM to MRF send (8) dNULLREG mMSGHDR_STMM udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_STMM+nBI_STMM_HISTORY_OUTPUT:ud ////////////////////////////////////// Save the History Data for Next Run ///////////////////////// #include "DI_Hist_Save.asm" ////////////////////////////////////// Save the DN Curr Frame for Next Run //////////////////////// add (4) pCF_Y_OFFSET<1>:uw ubSRC_CF_OFFSET<4;4,1>:ub npDN_YUV:w // check top/bottom field first cmp.e.f0.0 (1) null<1>:w ubTFLD_FIRST<0;1,0>:ub 1:w (f0.0) jmpi (1) TOP_FIELD_FIRST BOTTOM_FIELD_FIRST: $for (0,0; udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN(1,%1*4+4)<1> udRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,4)<4;4,1> // 1st field luma from current frame (line 1,3) } jmpi (1) SAVE_DN_CURR TOP_FIELD_FIRST: $for (0,0; udRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,0)<4;4,1> // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN(1,%1*4+4)<1> udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 1st field luma from current frame (line 1,3) } SAVE_DN_CURR: $for (0; ubRESP(nDI_CURR_FRAME_LUMA_OFFSET,%1*16) } mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud // block width and height (16x4) mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PL_DN_DI+nBI_DESTINATION_Y:ud //Write UV through DATAPORT mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin asr (1) rMSGSRC.1<1>:d rMSGSRC.1<0;1,0>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // block width and height (16x2) mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud mov (8) mubMSGHDR_DN(1, 0)<2> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET, 1)<16 ;8,2> mov (8) mubMSGHDR_DN(1, 1)<2> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET, 16)<16 ;8,2> mov (8) mubMSGHDR_DN(1, 16)<2> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+1, 1)<16 ;8,2> mov (8) mubMSGHDR_DN(1, 17)<2> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+1, 16)<16 ;8,2> send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nMSGLEN_1+nBI_DESTINATION_UV:ud intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_P208.asm000066400000000000000000000130271231401140700314660ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #define DI_ENABLE #include "DNDI.inc" #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 // Number of Y rows per block (4 rows for each frame) #undef nUV_NUM_OF_ROWS #define nUV_NUM_OF_ROWS 8 // Number of U/V rows per block #undef nSMPL_RESP_LEN #define nSMPL_RESP_LEN nSMPL_RESP_LEN_DNDI // set the number of GRF #undef nDPW_BLOCK_SIZE_HIST #define nDPW_BLOCK_SIZE_HIST nBLOCK_WIDTH_4+nBLOCK_HEIGHT_1 // HIST Block Size for Write is 4x2 #undef nDPW_BLOCK_SIZE_DN #define nDPW_BLOCK_SIZE_DN nBLOCK_WIDTH_16+nBLOCK_HEIGHT_4 // DN Block Size for Write is 16x4 ////////////////////////////////////// Run the DN Algorithm /////////////////////////////////////// #include "DNDI_Command.asm" ////////////////////////////////////// Rearrange for Internal Planar ////////////////////////////// // move the previous frame Y component to internal planar format $for (0; ubRESP(nDI_PREV_FRAME_LUMA_OFFSET,%1*16) } // move the previous frame U,V components to internal planar format $for (0; ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels mov (8) uwDEST_V(0,%1*8)<1> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //V pixels } // move the current frame Y component to internal planar format $for (0; ubRESP(nDI_CURR_FRAME_LUMA_OFFSET,%1*16) } // move the current frame U,V components to internal planar format $for (0; ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels mov (8) uwDEST_V(2,%1*8)<1> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //V pixels } ////////////////////////////////////// Save the STMM Data for Next Run ///////////////////////// // Write STMM to memory shr (1) rMSGSRC.0<1>:ud wORIX<0;1,0>:w 1:w // X origin / 2 mov (1) rMSGSRC.1<1>:ud wORIY<0;1,0>:w // Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_STMM:ud // block width and height (8x4) mov (8) mudMSGHDR_STMM(0)<1> rMSGSRC.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udRESP(nDI_STMM_OFFSET,0) // Move STMM to MRF send (8) dNULLREG mMSGHDR_STMM udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_STMM+nBI_STMM_HISTORY_OUTPUT:ud ////////////////////////////////////// Save the History Data for Next Run ///////////////////////// #include "DI_Hist_Save.asm" ////////////////////////////////////// Save the DN Curr Frame for Next Run //////////////////////// add (4) pCF_Y_OFFSET<1>:uw ubSRC_CF_OFFSET<4;4,1>:ub npDN_YUV:w // check top/bottom field first cmp.e.f0.0 (1) null<1>:w ubTFLD_FIRST<0;1,0>:ub 1:w (f0.0) jmpi (1) TOP_FIELD_FIRST BOTTOM_FIELD_FIRST: $for (0,0; udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN(1,%1*4+4)<1> udRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,4)<4;4,1> // 1st field luma from current frame (line 1,3) } jmpi (1) SAVE_DN_CURR TOP_FIELD_FIRST: $for (0,0; udRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,0)<4;4,1> // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN(1,%1*4+4)<1> udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 1st field luma from current frame (line 1,3) } SAVE_DN_CURR: mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud // block width and height (16x4) mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PL_DN_DI+nBI_DESTINATION_Y:ud /////////////////////////////P208 UV Copy 422///////////////////////////////////////////////////// //Read UV through DATAPORT add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud // Y Block width and height (16x4) (U/V block size is the same) mov (8) mudMSGHDR_DN<1> rMSGSRC<8;8,1>:ud send (8) udBOT_U_IO(0)<1> mMSGHDR_DN udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nRESLEN_2+nBI_CURRENT_SRC_UV:ud //Write UV through DATAPORT mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud // block width and height (16x4) mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud mov (8) mudMSGHDR_DN(1)<1> udBOT_U_IO(0)<8;8,1> mov (8) mudMSGHDR_DN(2)<1> udBOT_U_IO(1)<8;8,1> send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PL_DN_DI+nBI_DESTINATION_UV:ud intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_PL3.asm000066400000000000000000000141031231401140700314270ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #define DI_ENABLE #include "DNDI.inc" #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 // Number of Y rows per block (4 rows for each frame) #undef nUV_NUM_OF_ROWS #define nUV_NUM_OF_ROWS 8 // Number of U/V rows per block #undef nSMPL_RESP_LEN #define nSMPL_RESP_LEN nSMPL_RESP_LEN_DNDI // set the number of GRF #undef nDPW_BLOCK_SIZE_HIST #define nDPW_BLOCK_SIZE_HIST nBLOCK_WIDTH_4+nBLOCK_HEIGHT_1 // HIST Block Size for Write is 4x2 #undef nDPW_BLOCK_SIZE_DN #define nDPW_BLOCK_SIZE_DN nBLOCK_WIDTH_16+nBLOCK_HEIGHT_4 // DN Block Size for Write is 16x4 #undef nDPR_BLOCK_SIZE_UV #define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_8+nBLOCK_HEIGHT_2 // DN Block Size for UV Write/Read is 8x2 ////////////////////////////////////// Run the DN Algorithm /////////////////////////////////////// #include "DNDI_Command.asm" ////////////////////////////////////// Rearrange for Internal Planar ////////////////////////////// // move the previous frame Y component to internal planar format $for (0; ubRESP(nDI_PREV_FRAME_LUMA_OFFSET,%1*16) } // move the previous frame U,V components to internal planar format $for (0; ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels mov (8) uwDEST_V(0,%1*8)<1> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //V pixels } // move the current frame Y component to internal planar format $for (0; ubRESP(nDI_CURR_FRAME_LUMA_OFFSET,%1*16) } // move the current frame U,V components to internal planar format $for (0; ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels mov (8) uwDEST_V(2,%1*8)<1> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //V pixels } ////////////////////////////////////// Save the STMM Data for Next Run ///////////////////////// // Write STMM to memory shr (1) rMSGSRC.0<1>:ud wORIX<0;1,0>:w 1:w // X origin / 2 mov (1) rMSGSRC.1<1>:ud wORIY<0;1,0>:w // Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_STMM:ud // block width and height (8x4) mov (8) mudMSGHDR_STMM(0)<1> rMSGSRC.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udRESP(nDI_STMM_OFFSET,0) // Move STMM to MRF send (8) dNULLREG mMSGHDR_STMM udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_STMM+nBI_STMM_HISTORY_OUTPUT:ud ////////////////////////////////////// Save the History Data for Next Run ///////////////////////// #include "DI_Hist_Save.asm" ////////////////////////////////////// Save the DN Curr Frame for Next Run //////////////////////// add (4) pCF_Y_OFFSET<1>:uw ubSRC_CF_OFFSET<4;4,1>:ub npDN_YUV:w // check top/bottom field first cmp.e.f0.0 (1) null<1>:w ubTFLD_FIRST<0;1,0>:ub 1:w (f0.0) jmpi (1) TOP_FIELD_FIRST BOTTOM_FIELD_FIRST: $for (0,0; udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN(1,%1*4+4)<1> udRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,4)<4;4,1> // 1st field luma from current frame (line 1,3) } jmpi (1) SAVE_DN_CURR TOP_FIELD_FIRST: $for (0,0; udRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,0)<4;4,1> // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN(1,%1*4+4)<1> udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 1st field luma from current frame (line 1,3) } SAVE_DN_CURR: mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud // block width and height (16x4) mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PL_DN_DI+nBI_DESTINATION_Y:ud /////////////////////////////IMC3 UV Copy 422///////////////////////////////////////////////////// //Read UV through DATAPORT add (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w wSRC_H_ORI_OFFSET<2;2,1>:w // Source Y Block origin asr (2) rMSGSRC.0<1>:d rMSGSRC.0<2;2,1>:d 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // U/V block width and height (8x2) mov (8) mudMSGHDR_DN<1> rMSGSRC<8;8,1>:ud send (4) udBOT_U_IO(0)<1> mMSGHDR_DN udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nRESLEN_1+nBI_CURRENT_SRC_U:ud send (4) udBOT_V_IO(0)<1> mMSGHDR_DN udDUMMY_NULL nDATAPORT_READ nDPMR_MSGDSC+nRESLEN_1+nBI_CURRENT_SRC_V:ud //Write UV through DATAPORT mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin asr (2) rMSGSRC.0<1>:d wORIX<2;2,1>:w 1:w // U/V block origin should be half of Y's mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // block width and height (8x2) mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud mov (4) mudMSGHDR_DN(1)<1> udBOT_U_IO(0)<4;4,1> send (4) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nMSGLEN_1+nBI_DESTINATION_U:ud mov (4) mudMSGHDR_DN(1)<1> udBOT_V_IO(0)<4;4,1> send (4) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nMSGLEN_1+nBI_DESTINATION_V:udintel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DN_ALG.asm000066400000000000000000000025011231401140700272660ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ #define DI_DISABLE #include "DNDI.inc" #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 // Number of Y rows per block #undef nSMPL_RESP_LEN #define nSMPL_RESP_LEN nSMPL_RESP_LEN_DN_PL // Set the Number of GRFs in DNDI response #undef nDPW_BLOCK_SIZE_DN #define nDPW_BLOCK_SIZE_DN nBLOCK_WIDTH_16+nBLOCK_HEIGHT_8 // DN Curr Block Size for Write is 16x8 #undef nDPW_BLOCK_SIZE_HIST #define nDPW_BLOCK_SIZE_HIST nBLOCK_WIDTH_4+nBLOCK_HEIGHT_2 // HIST Block Size for Write is 4x2 ////////////////////////////////////// Run the DN Algorithm /////////////////////////////////////// #include "DNDI_COMMAND.asm" ////////////////////////////////////// Rearrange for Internal Planar ////////////////////////////// $for (0; ubRESP(nNODI_LUMA_OFFSET,%1*16)<16;16,1> // copy line of Y } ////////////////////////////////////// Save the History Data for Next Run ///////////////////////// #include "DNDI_Hist_Save.asm" intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/RGB_AVS_IEF_16x8.asm000066400000000000000000000024611231401140700303100ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- RGB_AVS_IEF_16x8.asm ---------- #include "AVS_IEF.inc" //------------------------------------------------------------------------------ // 2 sampler reads for 8x8 ARGB packed //------------------------------------------------------------------------------ // 1st 8x8 setup #include "AVS_SetupFirstBlock.asm" mov (1) rAVS_8x8_HDR.2:ud nAVS_ALL_CHANNELS:ud // Enable ARGB channels mov (16) mAVS_8x8_HDR.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE(0)<1> mAVS_8x8_HDR udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_4CH+nSI_SRC_RGB+nBI_CURRENT_SRC_YUV // Return ARGB in 16 GRFs // 2nd 8x8 setup #include "AVS_SetupSecondBlock.asm" mov (16) mAVS_8x8_HDR_2.0:ud rAVS_8x8_HDR.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs send (1) uwAVS_RESPONSE_2(0)<1> mAVS_8x8_HDR_2 udDUMMY_NULL nSMPL_ENGINE nAVS_MSG_DSC_4CH+nSI_SRC_RGB+nBI_CURRENT_SRC_YUV // Return ARGB in 16 GRFs intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/RGB_AVS_IEF_Unpack_16x8.asm000066400000000000000000000477661231401140700316320ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- RGB_AVS_IEF_Unpack_16x8.asm ---------- #include "AVS_IEF.inc" #ifdef AVS_OUTPUT_16_BIT // Move first 8x8 words of B to dest GRF (as packed) mov (4) uwDEST_Y(0,2)<4> uwAVS_RESPONSE(4,0)<4;4,1> mov (4) uwDEST_Y(1,2)<4> uwAVS_RESPONSE(4,8)<4;4,1> mov (4) uwDEST_Y(4,2)<4> uwAVS_RESPONSE(4,4)<4;4,1> mov (4) uwDEST_Y(5,2)<4> uwAVS_RESPONSE(4,12)<4;4,1> mov (4) uwDEST_Y(8,2)<4> uwAVS_RESPONSE(5,0)<4;4,1> mov (4) uwDEST_Y(9,2)<4> uwAVS_RESPONSE(5,8)<4;4,1> mov (4) uwDEST_Y(12,2)<4> uwAVS_RESPONSE(5,4)<4;4,1> mov (4) uwDEST_Y(13,2)<4> uwAVS_RESPONSE(5,12)<4;4,1> mov (4) uwDEST_Y(16,2)<4> uwAVS_RESPONSE(12,0)<4;4,1> mov (4) uwDEST_Y(17,2)<4> uwAVS_RESPONSE(12,8)<4;4,1> mov (4) uwDEST_Y(20,2)<4> uwAVS_RESPONSE(12,4)<4;4,1> mov (4) uwDEST_Y(21,2)<4> uwAVS_RESPONSE(12,12)<4;4,1> mov (4) uwDEST_Y(24,2)<4> uwAVS_RESPONSE(13,0)<4;4,1> mov (4) uwDEST_Y(25,2)<4> uwAVS_RESPONSE(13,8)<4;4,1> mov (4) uwDEST_Y(28,2)<4> uwAVS_RESPONSE(13,4)<4;4,1> mov (4) uwDEST_Y(29,2)<4> uwAVS_RESPONSE(13,12)<4;4,1> // Move first 8x8 words of G to dest GRF (as packed) mov (4) uwDEST_Y(0,1)<4> uwAVS_RESPONSE(2,0)<4;4,1> mov (4) uwDEST_Y(1,1)<4> uwAVS_RESPONSE(2,8)<4;4,1> mov (4) uwDEST_Y(4,1)<4> uwAVS_RESPONSE(2,4)<4;4,1> mov (4) uwDEST_Y(5,1)<4> uwAVS_RESPONSE(2,12)<4;4,1> mov (4) uwDEST_Y(8,1)<4> uwAVS_RESPONSE(3,0)<4;4,1> mov (4) uwDEST_Y(9,1)<4> uwAVS_RESPONSE(3,8)<4;4,1> mov (4) uwDEST_Y(12,1)<4> uwAVS_RESPONSE(3,4)<4;4,1> mov (4) uwDEST_Y(13,1)<4> uwAVS_RESPONSE(3,12)<4;4,1> mov (4) uwDEST_Y(16,1)<4> uwAVS_RESPONSE(10,0)<4;4,1> mov (4) uwDEST_Y(17,1)<4> uwAVS_RESPONSE(10,8)<4;4,1> mov (4) uwDEST_Y(20,1)<4> uwAVS_RESPONSE(10,4)<4;4,1> mov (4) uwDEST_Y(21,1)<4> uwAVS_RESPONSE(10,12)<4;4,1> mov (4) uwDEST_Y(24,1)<4> uwAVS_RESPONSE(11,0)<4;4,1> mov (4) uwDEST_Y(25,1)<4> uwAVS_RESPONSE(11,8)<4;4,1> mov (4) uwDEST_Y(28,1)<4> uwAVS_RESPONSE(11,4)<4;4,1> mov (4) uwDEST_Y(29,1)<4> uwAVS_RESPONSE(11,12)<4;4,1> // Move first 8x8 words of R to dest GRF (as packed) mov (4) uwDEST_Y(0,0)<4> uwAVS_RESPONSE(0,0)<4;4,1> mov (4) uwDEST_Y(1,0)<4> uwAVS_RESPONSE(0,8)<4;4,1> mov (4) uwDEST_Y(4,0)<4> uwAVS_RESPONSE(0,4)<4;4,1> mov (4) uwDEST_Y(5,0)<4> uwAVS_RESPONSE(0,12)<4;4,1> mov (4) uwDEST_Y(8,0)<4> uwAVS_RESPONSE(1,0)<4;4,1> mov (4) uwDEST_Y(9,0)<4> uwAVS_RESPONSE(1,8)<4;4,1> mov (4) uwDEST_Y(12,0)<4> uwAVS_RESPONSE(1,4)<4;4,1> mov (4) uwDEST_Y(13,0)<4> uwAVS_RESPONSE(1,12)<4;4,1> mov (4) uwDEST_Y(16,0)<4> uwAVS_RESPONSE(8,0)<4;4,1> mov (4) uwDEST_Y(17,0)<4> uwAVS_RESPONSE(8,8)<4;4,1> mov (4) uwDEST_Y(20,0)<4> uwAVS_RESPONSE(8,4)<4;4,1> mov (4) uwDEST_Y(21,0)<4> uwAVS_RESPONSE(8,12)<4;4,1> mov (4) uwDEST_Y(24,0)<4> uwAVS_RESPONSE(9,0)<4;4,1> mov (4) uwDEST_Y(25,0)<4> uwAVS_RESPONSE(9,8)<4;4,1> mov (4) uwDEST_Y(28,0)<4> uwAVS_RESPONSE(9,4)<4;4,1> mov (4) uwDEST_Y(29,0)<4> uwAVS_RESPONSE(9,12)<4;4,1> // Move first 8x8 words of A to dest GRF (as packed) mov (4) uwDEST_Y(0,3)<4> uwAVS_RESPONSE(6,0)<4;4,1> mov (4) uwDEST_Y(1,3)<4> uwAVS_RESPONSE(6,8)<4;4,1> mov (4) uwDEST_Y(4,3)<4> uwAVS_RESPONSE(6,4)<4;4,1> mov (4) uwDEST_Y(5,3)<4> uwAVS_RESPONSE(6,12)<4;4,1> mov (4) uwDEST_Y(8,3)<4> uwAVS_RESPONSE(7,0)<4;4,1> mov (4) uwDEST_Y(9,3)<4> uwAVS_RESPONSE(7,8)<4;4,1> mov (4) uwDEST_Y(12,3)<4> uwAVS_RESPONSE(7,4)<4;4,1> mov (4) uwDEST_Y(13,3)<4> uwAVS_RESPONSE(7,12)<4;4,1> mov (4) uwDEST_Y(16,3)<4> uwAVS_RESPONSE(14,0)<4;4,1> mov (4) uwDEST_Y(17,3)<4> uwAVS_RESPONSE(14,8)<4;4,1> mov (4) uwDEST_Y(20,3)<4> uwAVS_RESPONSE(14,4)<4;4,1> mov (4) uwDEST_Y(21,3)<4> uwAVS_RESPONSE(14,12)<4;4,1> mov (4) uwDEST_Y(24,3)<4> uwAVS_RESPONSE(15,0)<4;4,1> mov (4) uwDEST_Y(25,3)<4> uwAVS_RESPONSE(15,8)<4;4,1> mov (4) uwDEST_Y(28,3)<4> uwAVS_RESPONSE(15,4)<4;4,1> mov (4) uwDEST_Y(29,3)<4> uwAVS_RESPONSE(15,12)<4;4,1> // Move second 8x8 words of B to dest GRF mov (4) uwDEST_Y(2,2)<4> uwAVS_RESPONSE_2(4,0)<4;4,1> mov (4) uwDEST_Y(3,2)<4> uwAVS_RESPONSE_2(4,8)<4;4,1> mov (4) uwDEST_Y(6,2)<4> uwAVS_RESPONSE_2(4,4)<4;4,1> mov (4) uwDEST_Y(7,2)<4> uwAVS_RESPONSE_2(4,12)<4;4,1> mov (4) uwDEST_Y(10,2)<4> uwAVS_RESPONSE_2(5,0)<4;4,1> mov (4) uwDEST_Y(11,2)<4> uwAVS_RESPONSE_2(5,8)<4;4,1> mov (4) uwDEST_Y(14,2)<4> uwAVS_RESPONSE_2(5,4)<4;4,1> mov (4) uwDEST_Y(15,2)<4> uwAVS_RESPONSE_2(5,12)<4;4,1> mov (4) uwDEST_Y(18,2)<4> uwAVS_RESPONSE_2(12,0)<4;4,1> mov (4) uwDEST_Y(19,2)<4> uwAVS_RESPONSE_2(12,8)<4;4,1> mov (4) uwDEST_Y(22,2)<4> uwAVS_RESPONSE_2(12,4)<4;4,1> mov (4) uwDEST_Y(23,2)<4> uwAVS_RESPONSE_2(12,12)<4;4,1> mov (4) uwDEST_Y(26,2)<4> uwAVS_RESPONSE_2(13,0)<4;4,1> mov (4) uwDEST_Y(27,2)<4> uwAVS_RESPONSE_2(13,8)<4;4,1> mov (4) uwDEST_Y(30,2)<4> uwAVS_RESPONSE_2(13,4)<4;4,1> mov (4) uwDEST_Y(31,2)<4> uwAVS_RESPONSE_2(13,12)<4;4,1> // Move second 8x8 words of G to dest GRF mov (4) uwDEST_Y(2,1)<4> uwAVS_RESPONSE_2(2,0)<4;4,1> mov (4) uwDEST_Y(3,1)<4> uwAVS_RESPONSE_2(2,8)<4;4,1> mov (4) uwDEST_Y(6,1)<4> uwAVS_RESPONSE_2(2,4)<4;4,1> mov (4) uwDEST_Y(7,1)<4> uwAVS_RESPONSE_2(2,12)<4;4,1> mov (4) uwDEST_Y(10,1)<4> uwAVS_RESPONSE_2(3,0)<4;4,1> mov (4) uwDEST_Y(11,1)<4> uwAVS_RESPONSE_2(3,8)<4;4,1> mov (4) uwDEST_Y(14,1)<4> uwAVS_RESPONSE_2(3,4)<4;4,1> mov (4) uwDEST_Y(15,1)<4> uwAVS_RESPONSE_2(3,12)<4;4,1> mov (4) uwDEST_Y(18,1)<4> uwAVS_RESPONSE_2(10,0)<4;4,1> mov (4) uwDEST_Y(19,1)<4> uwAVS_RESPONSE_2(10,8)<4;4,1> mov (4) uwDEST_Y(22,1)<4> uwAVS_RESPONSE_2(10,4)<4;4,1> mov (4) uwDEST_Y(23,1)<4> uwAVS_RESPONSE_2(10,12)<4;4,1> mov (4) uwDEST_Y(26,1)<4> uwAVS_RESPONSE_2(11,0)<4;4,1> mov (4) uwDEST_Y(27,1)<4> uwAVS_RESPONSE_2(11,8)<4;4,1> mov (4) uwDEST_Y(30,1)<4> uwAVS_RESPONSE_2(11,4)<4;4,1> mov (4) uwDEST_Y(31,1)<4> uwAVS_RESPONSE_2(11,12)<4;4,1> // Move second 8x8 words of R to dest GRF mov (4) uwDEST_Y(2,0)<4> uwAVS_RESPONSE_2(0,0)<4;4,1> mov (4) uwDEST_Y(3,0)<4> uwAVS_RESPONSE_2(0,8)<4;4,1> mov (4) uwDEST_Y(6,0)<4> uwAVS_RESPONSE_2(0,4)<4;4,1> mov (4) uwDEST_Y(7,0)<4> uwAVS_RESPONSE_2(0,12)<4;4,1> mov (4) uwDEST_Y(10,0)<4> uwAVS_RESPONSE_2(1,0)<4;4,1> mov (4) uwDEST_Y(11,0)<4> uwAVS_RESPONSE_2(1,8)<4;4,1> mov (4) uwDEST_Y(14,0)<4> uwAVS_RESPONSE_2(1,4)<4;4,1> mov (4) uwDEST_Y(15,0)<4> uwAVS_RESPONSE_2(1,12)<4;4,1> mov (4) uwDEST_Y(18,0)<4> uwAVS_RESPONSE_2(8,0)<4;4,1> mov (4) uwDEST_Y(19,0)<4> uwAVS_RESPONSE_2(8,8)<4;4,1> mov (4) uwDEST_Y(22,0)<4> uwAVS_RESPONSE_2(8,4)<4;4,1> mov (4) uwDEST_Y(23,0)<4> uwAVS_RESPONSE_2(8,12)<4;4,1> mov (4) uwDEST_Y(26,0)<4> uwAVS_RESPONSE_2(9,0)<4;4,1> mov (4) uwDEST_Y(27,0)<4> uwAVS_RESPONSE_2(9,8)<4;4,1> mov (4) uwDEST_Y(30,0)<4> uwAVS_RESPONSE_2(9,4)<4;4,1> mov (4) uwDEST_Y(31,0)<4> uwAVS_RESPONSE_2(9,12)<4;4,1> // Move second 8x8 words of A to dest GRF mov (4) uwDEST_Y(2,3)<4> uwAVS_RESPONSE_2(6,0)<4;4,1> mov (4) uwDEST_Y(3,3)<4> uwAVS_RESPONSE_2(6,8)<4;4,1> mov (4) uwDEST_Y(6,3)<4> uwAVS_RESPONSE_2(6,4)<4;4,1> mov (4) uwDEST_Y(7,3)<4> uwAVS_RESPONSE_2(6,12)<4;4,1> mov (4) uwDEST_Y(10,3)<4> uwAVS_RESPONSE_2(7,0)<4;4,1> mov (4) uwDEST_Y(11,3)<4> uwAVS_RESPONSE_2(7,8)<4;4,1> mov (4) uwDEST_Y(14,3)<4> uwAVS_RESPONSE_2(7,4)<4;4,1> mov (4) uwDEST_Y(15,3)<4> uwAVS_RESPONSE_2(7,12)<4;4,1> mov (4) uwDEST_Y(18,3)<4> uwAVS_RESPONSE_2(14,0)<4;4,1> mov (4) uwDEST_Y(19,3)<4> uwAVS_RESPONSE_2(14,8)<4;4,1> mov (4) uwDEST_Y(22,3)<4> uwAVS_RESPONSE_2(14,4)<4;4,1> mov (4) uwDEST_Y(23,3)<4> uwAVS_RESPONSE_2(14,12)<4;4,1> mov (4) uwDEST_Y(26,3)<4> uwAVS_RESPONSE_2(15,0)<4;4,1> mov (4) uwDEST_Y(27,3)<4> uwAVS_RESPONSE_2(15,8)<4;4,1> mov (4) uwDEST_Y(30,3)<4> uwAVS_RESPONSE_2(15,4)<4;4,1> mov (4) uwDEST_Y(31,3)<4> uwAVS_RESPONSE_2(15,12)<4;4,1> #else /* OUTPUT_8_BIT */ // Move first 8x8 words of B to dest GRF mov (8) ubDEST_Y(0,2)<4> ubAVS_RESPONSE(4,1)<16;4,2> mov (8) ubDEST_Y(2,2)<4> ubAVS_RESPONSE(4,8+1)<16;4,2> mov (8) ubDEST_Y(4,2)<4> ubAVS_RESPONSE(5,1)<16;4,2> mov (8) ubDEST_Y(6,2)<4> ubAVS_RESPONSE(5,8+1)<16;4,2> mov (8) ubDEST_Y(8,2)<4> ubAVS_RESPONSE(12,1)<16;4,2> mov (8) ubDEST_Y(10,2)<4> ubAVS_RESPONSE(12,8+1)<16;4,2> mov (8) ubDEST_Y(12,2)<4> ubAVS_RESPONSE(13,1)<16;4,2> mov (8) ubDEST_Y(14,2)<4> ubAVS_RESPONSE(13,8+1)<16;4,2> // Move first 8x8 words of G to dest GRF mov (8) ubDEST_Y(0,1)<4> ubAVS_RESPONSE(2,1)<16;4,2> mov (8) ubDEST_Y(2,1)<4> ubAVS_RESPONSE(2,8+1)<16;4,2> mov (8) ubDEST_Y(4,1)<4> ubAVS_RESPONSE(3,1)<16;4,2> mov (8) ubDEST_Y(6,1)<4> ubAVS_RESPONSE(3,8+1)<16;4,2> mov (8) ubDEST_Y(8,1)<4> ubAVS_RESPONSE(10,1)<16;4,2> mov (8) ubDEST_Y(10,1)<4> ubAVS_RESPONSE(10,8+1)<16;4,2> mov (8) ubDEST_Y(12,1)<4> ubAVS_RESPONSE(11,1)<16;4,2> mov (8) ubDEST_Y(14,1)<4> ubAVS_RESPONSE(11,8+1)<16;4,2> // Move first 8x8 words of R to dest GRF mov (8) ubDEST_Y(0,0)<4> ubAVS_RESPONSE(0,1)<16;4,2> mov (8) ubDEST_Y(2,0)<4> ubAVS_RESPONSE(0,8+1)<16;4,2> mov (8) ubDEST_Y(4,0)<4> ubAVS_RESPONSE(1,1)<16;4,2> mov (8) ubDEST_Y(6,0)<4> ubAVS_RESPONSE(1,8+1)<16;4,2> mov (8) ubDEST_Y(8,0)<4> ubAVS_RESPONSE(8,1)<16;4,2> mov (8) ubDEST_Y(10,0)<4> ubAVS_RESPONSE(8,8+1)<16;4,2> mov (8) ubDEST_Y(12,0)<4> ubAVS_RESPONSE(9,1)<16;4,2> mov (8) ubDEST_Y(14,0)<4> ubAVS_RESPONSE(9,8+1)<16;4,2> // Move first 8x8 words of A to dest GRF mov (8) ubDEST_Y(0,3)<4> ubAVS_RESPONSE(6,1)<16;4,2> mov (8) ubDEST_Y(2,3)<4> ubAVS_RESPONSE(6,8+1)<16;4,2> mov (8) ubDEST_Y(4,3)<4> ubAVS_RESPONSE(7,1)<16;4,2> mov (8) ubDEST_Y(6,3)<4> ubAVS_RESPONSE(7,8+1)<16;4,2> mov (8) ubDEST_Y(8,3)<4> ubAVS_RESPONSE(14,1)<16;4,2> mov (8) ubDEST_Y(10,3)<4> ubAVS_RESPONSE(14,8+1)<16;4,2> mov (8) ubDEST_Y(12,3)<4> ubAVS_RESPONSE(15,1)<16;4,2> mov (8) ubDEST_Y(14,3)<4> ubAVS_RESPONSE(15,8+1)<16;4,2> // Move second 8x8 words of B to dest GRF mov (8) ubDEST_Y(1,2)<4> ubAVS_RESPONSE_2(4,1)<16;4,2> mov (8) ubDEST_Y(3,2)<4> ubAVS_RESPONSE_2(4,8+1)<16;4,2> mov (8) ubDEST_Y(5,2)<4> ubAVS_RESPONSE_2(5,1)<16;4,2> mov (8) ubDEST_Y(7,2)<4> ubAVS_RESPONSE_2(5,8+1)<16;4,2> mov (8) ubDEST_Y(9,2)<4> ubAVS_RESPONSE_2(12,1)<16;4,2> mov (8) ubDEST_Y(11,2)<4> ubAVS_RESPONSE_2(12,8+1)<16;4,2> mov (8) ubDEST_Y(13,2)<4> ubAVS_RESPONSE_2(13,1)<16;4,2> mov (8) ubDEST_Y(15,2)<4> ubAVS_RESPONSE_2(13,8+1)<16;4,2> // Move second 8x8 words of G to dest GRF mov (8) ubDEST_Y(1,1)<4> ubAVS_RESPONSE_2(2,1)<16;4,2> mov (8) ubDEST_Y(3,1)<4> ubAVS_RESPONSE_2(2,8+1)<16;4,2> mov (8) ubDEST_Y(5,1)<4> ubAVS_RESPONSE_2(3,1)<16;4,2> mov (8) ubDEST_Y(7,1)<4> ubAVS_RESPONSE_2(3,8+1)<16;4,2> mov (8) ubDEST_Y(9,1)<4> ubAVS_RESPONSE_2(10,1)<16;4,2> mov (8) ubDEST_Y(11,1)<4> ubAVS_RESPONSE_2(10,8+1)<16;4,2> mov (8) ubDEST_Y(13,1)<4> ubAVS_RESPONSE_2(11,1)<16;4,2> mov (8) ubDEST_Y(15,1)<4> ubAVS_RESPONSE_2(11,8+1)<16;4,2> // Move second 8x8 words of R to dest GRF mov (8) ubDEST_Y(1,0)<4> ubAVS_RESPONSE_2(0,1)<16;4,2> mov (8) ubDEST_Y(3,0)<4> ubAVS_RESPONSE_2(0,8+1)<16;4,2> mov (8) ubDEST_Y(5,0)<4> ubAVS_RESPONSE_2(1,1)<16;4,2> mov (8) ubDEST_Y(7,0)<4> ubAVS_RESPONSE_2(1,8+1)<16;4,2> mov (8) ubDEST_Y(9,0)<4> ubAVS_RESPONSE_2(8,1)<16;4,2> mov (8) ubDEST_Y(11,0)<4> ubAVS_RESPONSE_2(8,8+1)<16;4,2> mov (8) ubDEST_Y(13,0)<4> ubAVS_RESPONSE_2(9,1)<16;4,2> mov (8) ubDEST_Y(15,0)<4> ubAVS_RESPONSE_2(9,8+1)<16;4,2> // Move second 8x8 words of A to dest GRF mov (8) ubDEST_Y(1,3)<4> ubAVS_RESPONSE_2(6,1)<16;4,2> mov (8) ubDEST_Y(3,3)<4> ubAVS_RESPONSE_2(6,8+1)<16;4,2> mov (8) ubDEST_Y(5,3)<4> ubAVS_RESPONSE_2(7,1)<16;4,2> mov (8) ubDEST_Y(7,3)<4> ubAVS_RESPONSE_2(7,8+1)<16;4,2> mov (8) ubDEST_Y(9,3)<4> ubAVS_RESPONSE_2(14,1)<16;4,2> mov (8) ubDEST_Y(11,3)<4> ubAVS_RESPONSE_2(14,8+1)<16;4,2> mov (8) ubDEST_Y(13,3)<4> ubAVS_RESPONSE_2(15,1)<16;4,2> mov (8) ubDEST_Y(15,3)<4> ubAVS_RESPONSE_2(15,8+1)<16;4,2> #endif //------------------------------------------------------------------------------ // Set to write bottom region to memory #define SRC_REGION REGION_2 // Re-define new # of lines #undef nUV_NUM_OF_ROWS #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 #define nUV_NUM_OF_ROWS 8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/RGB_AVS_IEF_Unscramble_16x8.asm000066400000000000000000000505201231401140700324620ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- RGB_AVS_IEF_Unpack_16x8.asm ---------- #include "AVS_IEF.inc" .declare DEST_B Base=REG(r,10) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare DEST_G Base=REG(r,18) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare DEST_R Base=REG(r,26) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare DEST_A Base=REG(r,34) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw #ifdef AVS_OUTPUT_16_BIT //This portion will need to be changed if unpacking is required for Y416 kernels (in case of blending etc) - vK //// Move first 8x8 words of B to dest GRF (as packed) // mov (4) uwDEST_Y(0,2)<4> uwAVS_RESPONSE(4,0)<4;4,1> // mov (4) uwDEST_Y(1,2)<4> uwAVS_RESPONSE(4,8)<4;4,1> // mov (4) uwDEST_Y(4,2)<4> uwAVS_RESPONSE(4,4)<4;4,1> // mov (4) uwDEST_Y(5,2)<4> uwAVS_RESPONSE(4,12)<4;4,1> // mov (4) uwDEST_Y(8,2)<4> uwAVS_RESPONSE(5,0)<4;4,1> // mov (4) uwDEST_Y(9,2)<4> uwAVS_RESPONSE(5,8)<4;4,1> // mov (4) uwDEST_Y(12,2)<4> uwAVS_RESPONSE(5,4)<4;4,1> // mov (4) uwDEST_Y(13,2)<4> uwAVS_RESPONSE(5,12)<4;4,1> // mov (4) uwDEST_Y(16,2)<4> uwAVS_RESPONSE(12,0)<4;4,1> // mov (4) uwDEST_Y(17,2)<4> uwAVS_RESPONSE(12,8)<4;4,1> // mov (4) uwDEST_Y(20,2)<4> uwAVS_RESPONSE(12,4)<4;4,1> // mov (4) uwDEST_Y(21,2)<4> uwAVS_RESPONSE(12,12)<4;4,1> // mov (4) uwDEST_Y(24,2)<4> uwAVS_RESPONSE(13,0)<4;4,1> // mov (4) uwDEST_Y(25,2)<4> uwAVS_RESPONSE(13,8)<4;4,1> // mov (4) uwDEST_Y(28,2)<4> uwAVS_RESPONSE(13,4)<4;4,1> // mov (4) uwDEST_Y(29,2)<4> uwAVS_RESPONSE(13,12)<4;4,1> // //// Move first 8x8 words of G to dest GRF (as packed) // mov (4) uwDEST_Y(0,1)<4> uwAVS_RESPONSE(2,0)<4;4,1> // mov (4) uwDEST_Y(1,1)<4> uwAVS_RESPONSE(2,8)<4;4,1> // mov (4) uwDEST_Y(4,1)<4> uwAVS_RESPONSE(2,4)<4;4,1> // mov (4) uwDEST_Y(5,1)<4> uwAVS_RESPONSE(2,12)<4;4,1> // mov (4) uwDEST_Y(8,1)<4> uwAVS_RESPONSE(3,0)<4;4,1> // mov (4) uwDEST_Y(9,1)<4> uwAVS_RESPONSE(3,8)<4;4,1> // mov (4) uwDEST_Y(12,1)<4> uwAVS_RESPONSE(3,4)<4;4,1> // mov (4) uwDEST_Y(13,1)<4> uwAVS_RESPONSE(3,12)<4;4,1> // mov (4) uwDEST_Y(16,1)<4> uwAVS_RESPONSE(10,0)<4;4,1> // mov (4) uwDEST_Y(17,1)<4> uwAVS_RESPONSE(10,8)<4;4,1> // mov (4) uwDEST_Y(20,1)<4> uwAVS_RESPONSE(10,4)<4;4,1> // mov (4) uwDEST_Y(21,1)<4> uwAVS_RESPONSE(10,12)<4;4,1> // mov (4) uwDEST_Y(24,1)<4> uwAVS_RESPONSE(11,0)<4;4,1> // mov (4) uwDEST_Y(25,1)<4> uwAVS_RESPONSE(11,8)<4;4,1> // mov (4) uwDEST_Y(28,1)<4> uwAVS_RESPONSE(11,4)<4;4,1> // mov (4) uwDEST_Y(29,1)<4> uwAVS_RESPONSE(11,12)<4;4,1> // //// Move first 8x8 words of R to dest GRF (as packed) // mov (4) uwDEST_Y(0,0)<4> uwAVS_RESPONSE(0,0)<4;4,1> // mov (4) uwDEST_Y(1,0)<4> uwAVS_RESPONSE(0,8)<4;4,1> // mov (4) uwDEST_Y(4,0)<4> uwAVS_RESPONSE(0,4)<4;4,1> // mov (4) uwDEST_Y(5,0)<4> uwAVS_RESPONSE(0,12)<4;4,1> // mov (4) uwDEST_Y(8,0)<4> uwAVS_RESPONSE(1,0)<4;4,1> // mov (4) uwDEST_Y(9,0)<4> uwAVS_RESPONSE(1,8)<4;4,1> // mov (4) uwDEST_Y(12,0)<4> uwAVS_RESPONSE(1,4)<4;4,1> // mov (4) uwDEST_Y(13,0)<4> uwAVS_RESPONSE(1,12)<4;4,1> // mov (4) uwDEST_Y(16,0)<4> uwAVS_RESPONSE(8,0)<4;4,1> // mov (4) uwDEST_Y(17,0)<4> uwAVS_RESPONSE(8,8)<4;4,1> // mov (4) uwDEST_Y(20,0)<4> uwAVS_RESPONSE(8,4)<4;4,1> // mov (4) uwDEST_Y(21,0)<4> uwAVS_RESPONSE(8,12)<4;4,1> // mov (4) uwDEST_Y(24,0)<4> uwAVS_RESPONSE(9,0)<4;4,1> // mov (4) uwDEST_Y(25,0)<4> uwAVS_RESPONSE(9,8)<4;4,1> // mov (4) uwDEST_Y(28,0)<4> uwAVS_RESPONSE(9,4)<4;4,1> // mov (4) uwDEST_Y(29,0)<4> uwAVS_RESPONSE(9,12)<4;4,1> // //// Move first 8x8 words of A to dest GRF (as packed) // mov (4) uwDEST_Y(0,3)<4> uwAVS_RESPONSE(6,0)<4;4,1> // mov (4) uwDEST_Y(1,3)<4> uwAVS_RESPONSE(6,8)<4;4,1> // mov (4) uwDEST_Y(4,3)<4> uwAVS_RESPONSE(6,4)<4;4,1> // mov (4) uwDEST_Y(5,3)<4> uwAVS_RESPONSE(6,12)<4;4,1> // mov (4) uwDEST_Y(8,3)<4> uwAVS_RESPONSE(7,0)<4;4,1> // mov (4) uwDEST_Y(9,3)<4> uwAVS_RESPONSE(7,8)<4;4,1> // mov (4) uwDEST_Y(12,3)<4> uwAVS_RESPONSE(7,4)<4;4,1> // mov (4) uwDEST_Y(13,3)<4> uwAVS_RESPONSE(7,12)<4;4,1> // mov (4) uwDEST_Y(16,3)<4> uwAVS_RESPONSE(14,0)<4;4,1> // mov (4) uwDEST_Y(17,3)<4> uwAVS_RESPONSE(14,8)<4;4,1> // mov (4) uwDEST_Y(20,3)<4> uwAVS_RESPONSE(14,4)<4;4,1> // mov (4) uwDEST_Y(21,3)<4> uwAVS_RESPONSE(14,12)<4;4,1> // mov (4) uwDEST_Y(24,3)<4> uwAVS_RESPONSE(15,0)<4;4,1> // mov (4) uwDEST_Y(25,3)<4> uwAVS_RESPONSE(15,8)<4;4,1> // mov (4) uwDEST_Y(28,3)<4> uwAVS_RESPONSE(15,4)<4;4,1> // mov (4) uwDEST_Y(29,3)<4> uwAVS_RESPONSE(15,12)<4;4,1> // //// Move second 8x8 words of B to dest GRF // mov (4) uwDEST_Y(2,2)<4> uwAVS_RESPONSE_2(4,0)<4;4,1> // mov (4) uwDEST_Y(3,2)<4> uwAVS_RESPONSE_2(4,8)<4;4,1> // mov (4) uwDEST_Y(6,2)<4> uwAVS_RESPONSE_2(4,4)<4;4,1> // mov (4) uwDEST_Y(7,2)<4> uwAVS_RESPONSE_2(4,12)<4;4,1> // mov (4) uwDEST_Y(10,2)<4> uwAVS_RESPONSE_2(5,0)<4;4,1> // mov (4) uwDEST_Y(11,2)<4> uwAVS_RESPONSE_2(5,8)<4;4,1> // mov (4) uwDEST_Y(14,2)<4> uwAVS_RESPONSE_2(5,4)<4;4,1> // mov (4) uwDEST_Y(15,2)<4> uwAVS_RESPONSE_2(5,12)<4;4,1> // mov (4) uwDEST_Y(18,2)<4> uwAVS_RESPONSE_2(12,0)<4;4,1> // mov (4) uwDEST_Y(19,2)<4> uwAVS_RESPONSE_2(12,8)<4;4,1> // mov (4) uwDEST_Y(22,2)<4> uwAVS_RESPONSE_2(12,4)<4;4,1> // mov (4) uwDEST_Y(23,2)<4> uwAVS_RESPONSE_2(12,12)<4;4,1> // mov (4) uwDEST_Y(26,2)<4> uwAVS_RESPONSE_2(13,0)<4;4,1> // mov (4) uwDEST_Y(27,2)<4> uwAVS_RESPONSE_2(13,8)<4;4,1> // mov (4) uwDEST_Y(30,2)<4> uwAVS_RESPONSE_2(13,4)<4;4,1> // mov (4) uwDEST_Y(31,2)<4> uwAVS_RESPONSE_2(13,12)<4;4,1> // //// Move second 8x8 words of G to dest GRF // mov (4) uwDEST_Y(2,1)<4> uwAVS_RESPONSE_2(2,0)<4;4,1> // mov (4) uwDEST_Y(3,1)<4> uwAVS_RESPONSE_2(2,8)<4;4,1> // mov (4) uwDEST_Y(6,1)<4> uwAVS_RESPONSE_2(2,4)<4;4,1> // mov (4) uwDEST_Y(7,1)<4> uwAVS_RESPONSE_2(2,12)<4;4,1> // mov (4) uwDEST_Y(10,1)<4> uwAVS_RESPONSE_2(3,0)<4;4,1> // mov (4) uwDEST_Y(11,1)<4> uwAVS_RESPONSE_2(3,8)<4;4,1> // mov (4) uwDEST_Y(14,1)<4> uwAVS_RESPONSE_2(3,4)<4;4,1> // mov (4) uwDEST_Y(15,1)<4> uwAVS_RESPONSE_2(3,12)<4;4,1> // mov (4) uwDEST_Y(18,1)<4> uwAVS_RESPONSE_2(10,0)<4;4,1> // mov (4) uwDEST_Y(19,1)<4> uwAVS_RESPONSE_2(10,8)<4;4,1> // mov (4) uwDEST_Y(22,1)<4> uwAVS_RESPONSE_2(10,4)<4;4,1> // mov (4) uwDEST_Y(23,1)<4> uwAVS_RESPONSE_2(10,12)<4;4,1> // mov (4) uwDEST_Y(26,1)<4> uwAVS_RESPONSE_2(11,0)<4;4,1> // mov (4) uwDEST_Y(27,1)<4> uwAVS_RESPONSE_2(11,8)<4;4,1> // mov (4) uwDEST_Y(30,1)<4> uwAVS_RESPONSE_2(11,4)<4;4,1> // mov (4) uwDEST_Y(31,1)<4> uwAVS_RESPONSE_2(11,12)<4;4,1> // //// Move second 8x8 words of R to dest GRF // mov (4) uwDEST_Y(2,0)<4> uwAVS_RESPONSE_2(0,0)<4;4,1> // mov (4) uwDEST_Y(3,0)<4> uwAVS_RESPONSE_2(0,8)<4;4,1> // mov (4) uwDEST_Y(6,0)<4> uwAVS_RESPONSE_2(0,4)<4;4,1> // mov (4) uwDEST_Y(7,0)<4> uwAVS_RESPONSE_2(0,12)<4;4,1> // mov (4) uwDEST_Y(10,0)<4> uwAVS_RESPONSE_2(1,0)<4;4,1> // mov (4) uwDEST_Y(11,0)<4> uwAVS_RESPONSE_2(1,8)<4;4,1> // mov (4) uwDEST_Y(14,0)<4> uwAVS_RESPONSE_2(1,4)<4;4,1> // mov (4) uwDEST_Y(15,0)<4> uwAVS_RESPONSE_2(1,12)<4;4,1> // mov (4) uwDEST_Y(18,0)<4> uwAVS_RESPONSE_2(8,0)<4;4,1> // mov (4) uwDEST_Y(19,0)<4> uwAVS_RESPONSE_2(8,8)<4;4,1> // mov (4) uwDEST_Y(22,0)<4> uwAVS_RESPONSE_2(8,4)<4;4,1> // mov (4) uwDEST_Y(23,0)<4> uwAVS_RESPONSE_2(8,12)<4;4,1> // mov (4) uwDEST_Y(26,0)<4> uwAVS_RESPONSE_2(9,0)<4;4,1> // mov (4) uwDEST_Y(27,0)<4> uwAVS_RESPONSE_2(9,8)<4;4,1> // mov (4) uwDEST_Y(30,0)<4> uwAVS_RESPONSE_2(9,4)<4;4,1> // mov (4) uwDEST_Y(31,0)<4> uwAVS_RESPONSE_2(9,12)<4;4,1> // //// Move second 8x8 words of A to dest GRF // mov (4) uwDEST_Y(2,3)<4> uwAVS_RESPONSE_2(6,0)<4;4,1> // mov (4) uwDEST_Y(3,3)<4> uwAVS_RESPONSE_2(6,8)<4;4,1> // mov (4) uwDEST_Y(6,3)<4> uwAVS_RESPONSE_2(6,4)<4;4,1> // mov (4) uwDEST_Y(7,3)<4> uwAVS_RESPONSE_2(6,12)<4;4,1> // mov (4) uwDEST_Y(10,3)<4> uwAVS_RESPONSE_2(7,0)<4;4,1> // mov (4) uwDEST_Y(11,3)<4> uwAVS_RESPONSE_2(7,8)<4;4,1> // mov (4) uwDEST_Y(14,3)<4> uwAVS_RESPONSE_2(7,4)<4;4,1> // mov (4) uwDEST_Y(15,3)<4> uwAVS_RESPONSE_2(7,12)<4;4,1> // mov (4) uwDEST_Y(18,3)<4> uwAVS_RESPONSE_2(14,0)<4;4,1> // mov (4) uwDEST_Y(19,3)<4> uwAVS_RESPONSE_2(14,8)<4;4,1> // mov (4) uwDEST_Y(22,3)<4> uwAVS_RESPONSE_2(14,4)<4;4,1> // mov (4) uwDEST_Y(23,3)<4> uwAVS_RESPONSE_2(14,12)<4;4,1> // mov (4) uwDEST_Y(26,3)<4> uwAVS_RESPONSE_2(15,0)<4;4,1> // mov (4) uwDEST_Y(27,3)<4> uwAVS_RESPONSE_2(15,8)<4;4,1> // mov (4) uwDEST_Y(30,3)<4> uwAVS_RESPONSE_2(15,4)<4;4,1> // mov (4) uwDEST_Y(31,3)<4> uwAVS_RESPONSE_2(15,12)<4;4,1> #else /* OUTPUT_8_BIT */ // Move first 8x8 words of B to dest GRF mov (8) DEST_B(0)<1> ubAVS_RESPONSE(4,1)<16;4,2> mov (8) DEST_B(1)<1> ubAVS_RESPONSE(4,8+1)<16;4,2> mov (8) DEST_B(2)<1> ubAVS_RESPONSE(5,1)<16;4,2> mov (8) DEST_B(3)<1> ubAVS_RESPONSE(5,8+1)<16;4,2> mov (8) DEST_B(4)<1> ubAVS_RESPONSE(12,1)<16;4,2> mov (8) DEST_B(5)<1> ubAVS_RESPONSE(12,8+1)<16;4,2> mov (8) DEST_B(6)<1> ubAVS_RESPONSE(13,1)<16;4,2> mov (8) DEST_B(7)<1> ubAVS_RESPONSE(13,8+1)<16;4,2> // Move first 8x8 words of G to dest GRF mov (8) DEST_G(0)<1> ubAVS_RESPONSE(2,1)<16;4,2> mov (8) DEST_G(1)<1> ubAVS_RESPONSE(2,8+1)<16;4,2> mov (8) DEST_G(2)<1> ubAVS_RESPONSE(3,1)<16;4,2> mov (8) DEST_G(3)<1> ubAVS_RESPONSE(3,8+1)<16;4,2> mov (8) DEST_G(4)<1> ubAVS_RESPONSE(10,1)<16;4,2> mov (8) DEST_G(5)<1> ubAVS_RESPONSE(10,8+1)<16;4,2> mov (8) DEST_G(6)<1> ubAVS_RESPONSE(11,1)<16;4,2> mov (8) DEST_G(7)<1> ubAVS_RESPONSE(11,8+1)<16;4,2> // Move first 8x8 words of R to dest GRF mov (8) DEST_R(0)<1> ubAVS_RESPONSE(0,1)<16;4,2> mov (8) DEST_R(1)<1> ubAVS_RESPONSE(0,8+1)<16;4,2> mov (8) DEST_R(2)<1> ubAVS_RESPONSE(1,1)<16;4,2> mov (8) DEST_R(3)<1> ubAVS_RESPONSE(1,8+1)<16;4,2> mov (8) DEST_R(4)<1> ubAVS_RESPONSE(8,1)<16;4,2> mov (8) DEST_R(5)<1> ubAVS_RESPONSE(8,8+1)<16;4,2> mov (8) DEST_R(6)<1> ubAVS_RESPONSE(9,1)<16;4,2> mov (8) DEST_R(7)<1> ubAVS_RESPONSE(9,8+1)<16;4,2> // Move first 8x8 words of A to dest GRF mov (8) DEST_A(0)<1> ubAVS_RESPONSE(6,1)<16;4,2> mov (8) DEST_A(1)<1> ubAVS_RESPONSE(6,8+1)<16;4,2> mov (8) DEST_A(2)<1> ubAVS_RESPONSE(7,1)<16;4,2> mov (8) DEST_A(3)<1> ubAVS_RESPONSE(7,8+1)<16;4,2> mov (8) DEST_A(4)<1> ubAVS_RESPONSE(14,1)<16;4,2> mov (8) DEST_A(5)<1> ubAVS_RESPONSE(14,8+1)<16;4,2> mov (8) DEST_A(6)<1> ubAVS_RESPONSE(15,1)<16;4,2> mov (8) DEST_A(7)<1> ubAVS_RESPONSE(15,8+1)<16;4,2> // Move second 8x8 words of B to dest GRF mov (8) DEST_B(0,8)<1> ubAVS_RESPONSE_2(4,1)<16;4,2> mov (8) DEST_B(1,8)<1> ubAVS_RESPONSE_2(4,8+1)<16;4,2> mov (8) DEST_B(2,8)<1> ubAVS_RESPONSE_2(5,1)<16;4,2> mov (8) DEST_B(3,8)<1> ubAVS_RESPONSE_2(5,8+1)<16;4,2> mov (8) DEST_B(4,8)<1> ubAVS_RESPONSE_2(12,1)<16;4,2> mov (8) DEST_B(5,8)<1> ubAVS_RESPONSE_2(12,8+1)<16;4,2> mov (8) DEST_B(6,8)<1> ubAVS_RESPONSE_2(13,1)<16;4,2> mov (8) DEST_B(7,8)<1> ubAVS_RESPONSE_2(13,8+1)<16;4,2> // Move second 8x8 words of G to dest GRF mov (8) DEST_G(0,8)<1> ubAVS_RESPONSE_2(2,1)<16;4,2> mov (8) DEST_G(1,8)<1> ubAVS_RESPONSE_2(2,8+1)<16;4,2> mov (8) DEST_G(2,8)<1> ubAVS_RESPONSE_2(3,1)<16;4,2> mov (8) DEST_G(3,8)<1> ubAVS_RESPONSE_2(3,8+1)<16;4,2> mov (8) DEST_G(4,8)<1> ubAVS_RESPONSE_2(10,1)<16;4,2> mov (8) DEST_G(5,8)<1> ubAVS_RESPONSE_2(10,8+1)<16;4,2> mov (8) DEST_G(6,8)<1> ubAVS_RESPONSE_2(11,1)<16;4,2> mov (8) DEST_G(7,8)<1> ubAVS_RESPONSE_2(11,8+1)<16;4,2> // Move second 8x8 words of R to dest GRF mov (8) DEST_R(0,8)<1> ubAVS_RESPONSE_2(0,1)<16;4,2> mov (8) DEST_R(1,8)<1> ubAVS_RESPONSE_2(0,8+1)<16;4,2> mov (8) DEST_R(2,8)<1> ubAVS_RESPONSE_2(1,1)<16;4,2> mov (8) DEST_R(3,8)<1> ubAVS_RESPONSE_2(1,8+1)<16;4,2> mov (8) DEST_R(4,8)<1> ubAVS_RESPONSE_2(8,1)<16;4,2> mov (8) DEST_R(5,8)<1> ubAVS_RESPONSE_2(8,8+1)<16;4,2> mov (8) DEST_R(6,8)<1> ubAVS_RESPONSE_2(9,1)<16;4,2> mov (8) DEST_R(7,8)<1> ubAVS_RESPONSE_2(9,8+1)<16;4,2> // Move second 8x8 words of A to dest GRF mov (8) DEST_A(0,8)<1> ubAVS_RESPONSE_2(6,1)<16;4,2> mov (8) DEST_A(1,8)<1> ubAVS_RESPONSE_2(6,8+1)<16;4,2> mov (8) DEST_A(2,8)<1> ubAVS_RESPONSE_2(7,1)<16;4,2> mov (8) DEST_A(3,8)<1> ubAVS_RESPONSE_2(7,8+1)<16;4,2> mov (8) DEST_A(4,8)<1> ubAVS_RESPONSE_2(14,1)<16;4,2> mov (8) DEST_A(5,8)<1> ubAVS_RESPONSE_2(14,8+1)<16;4,2> mov (8) DEST_A(6,8)<1> ubAVS_RESPONSE_2(15,1)<16;4,2> mov (8) DEST_A(7,8)<1> ubAVS_RESPONSE_2(15,8+1)<16;4,2> #endif //------------------------------------------------------------------------------ // Set to write bottom region to memory #define SRC_REGION REGION_1 // Re-define new # of lines #undef nUV_NUM_OF_ROWS #undef nY_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 #define nUV_NUM_OF_ROWS 8 intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/RGB_Scaling.asm000066400000000000000000000065321231401140700277710ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ //---------- RGB_Scaling.asm ---------- #include "Scaling.inc" // Build 16 elements ramp in float32 and normalized it // mov (8) SAMPLER_RAMP(0)<1> 0x76543210:v // add (8) SAMPLER_RAMP(1)<1> SAMPLER_RAMP(0) 8.0:f mov (4) SAMPLER_RAMP(0)<1> 0x48403000:vf //3, 2, 1, 0 in float vector mov (4) SAMPLER_RAMP(0,4)<1> 0x5C585450:vf //7, 6, 5, 4 in float vector add (8) SAMPLER_RAMP(1)<1> SAMPLER_RAMP(0) 8.0:f //Module: PrepareScaleCoord.asm // Setup for sampler msg hdr mov (2) rMSGSRC.0<1>:ud 0:ud { NoDDClr } // Unused fields mov (1) rMSGSRC.2<1>:ud 0:ud { NoDDChk } // Write and offset // Calculate 16 v based on the step Y and vertical origin mov (16) mfMSGPAYLOAD(2)<1> fSRC_VID_V_ORI<0;1,0>:f mov (16) SCALE_COORD_Y<1>:f fSRC_VID_V_ORI<0;1,0>:f // Calculate 16 u based on the step X and hori origin // line (16) mfMSGPAYLOAD(0)<1> SCALE_STEP_X<0;1,0>:f SAMPLER_RAMP(0) // Assign to mrf directly mov (16) acc0:f fSRC_VID_H_ORI<0;1,0>:f { Compr } mac (16) mfMSGPAYLOAD(0)<1> fVIDEO_STEP_X<0;1,0>:f SAMPLER_RAMP(0) { Compr } //Setup the constants for line instruction mov (1) SCALE_LINE_P255<1>:f 255.0:f { NoDDClr } //{ NoDDClr, NoDDChk } mov (1) SCALE_LINE_P0_5<1>:f 0.5:f { NoDDChk } //------------------------------------------------------------------------------ $for (0; :ud // Copy msg header and payload mirrors to MRFs send (16) SCALE_RESPONSE_YW(0)<1> MSGHDR_SCALE udDUMMY_NULL nSMPL_ENGINE SMPLR_MSG_DSC+nSI_SRC_SIMD16_RGB+nBI_CURRENT_SRC_RGB // Calculate 16 v for next line add (16) mfMSGPAYLOAD(2)<1> SCALE_COORD_Y<8;8,1>:f fVIDEO_STEP_Y<0;1,0>:f // Assign to mrf directly add (16) SCALE_COORD_Y<1>:f SCALE_COORD_Y<8;8,1>:f fVIDEO_STEP_Y<0;1,0>:f // Assign to mrf directly // Scale back to [0, 255], convert f to ud line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(0) { Compr } // Process B, V mov (16) SCALE_RESPONSE_YD(0)<1> acc0:f { Compr } line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(2) { Compr } // Process B, V mov (16) SCALE_RESPONSE_YD(2)<1> acc0:f { Compr } line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(4) { Compr } // Process B, V mov (16) SCALE_RESPONSE_YD(4)<1> acc0:f { Compr } //#if defined(SAVE_ARGB) //Only needed if Alpha value is written to the destination line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(6) { Compr } // Process B, V mov (16) SCALE_RESPONSE_YD(6)<1> acc0:f { Compr } //#endif mov (16) DEST_R(%1)<1> SCALE_RESPONSE_YB(0) //possible error due to truncation - vK mov (16) DEST_G(%1)<1> SCALE_RESPONSE_YB(2) //possible error due to truncation - vK mov (16) DEST_B(%1)<1> SCALE_RESPONSE_YB(4) //possible error due to truncation - vK mov (16) DEST_A(%1)<1> SCALE_RESPONSE_YB(6) //possible error due to truncation - vK } intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Core_Kernels/Scaling.inc000066400000000000000000000064051231401140700272670ustar00rootroot00000000000000/* * All Video Processing kernels * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // File name: Scaling.inc #ifndef _SCALING_INC_ #define _SCALING_INC_ // Local variables---------------------------------------------------------------------------------- #define MSGHDR_SCALE m1 // Message Payload Header (Uses m2, m3, m4, m5 implicitly) //-------------------------------------------------------------------------------------------------- //r10.0 thru r33.0; Primary surface read from sampler (16x8) #define DEST_Y uwTOP_Y #define DEST_U uwTOP_U #define DEST_V uwTOP_V //r10.0 thru r41.0 .declare DEST_B Base=REG(r,10) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare DEST_G Base=REG(r,18) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare DEST_R Base=REG(r,26) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw .declare DEST_A Base=REG(r,34) ElementSize=2 SrcRegion=REGION(8,1) DstRegion=<1> Type=uw //r56.0 thru r79.0 .declare SCALE_RESPONSE_YF Base=REG(r,nBOT_Y) ElementSize=4 SrcRegion=REGION(8,1) Type=f .declare SCALE_RESPONSE_UF Base=REG(r,nBOT_U) ElementSize=4 SrcRegion=REGION(8,1) Type=f .declare SCALE_RESPONSE_VF Base=REG(r,nBOT_V) ElementSize=4 SrcRegion=REGION(8,1) Type=f .declare SCALE_RESPONSE_YW Base=REG(r,nBOT_Y) ElementSize=2 SrcRegion=REGION(16,1) Type=uw .declare SCALE_RESPONSE_UW Base=REG(r,nBOT_U) ElementSize=2 SrcRegion=REGION(16,1) Type=uw .declare SCALE_RESPONSE_VW Base=REG(r,nBOT_V) ElementSize=2 SrcRegion=REGION(16,1) Type=uw .declare SCALE_RESPONSE_YD Base=REG(r,nBOT_Y) ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare SCALE_RESPONSE_UD Base=REG(r,nBOT_U) ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare SCALE_RESPONSE_VD Base=REG(r,nBOT_V) ElementSize=4 SrcRegion=REGION(8,1) Type=ud .declare SCALE_RESPONSE_YB Base=REG(r,nBOT_Y) ElementSize=1 SrcRegion=REGION(8,4) Type=ub .declare SCALE_RESPONSE_UB Base=REG(r,nBOT_U) ElementSize=1 SrcRegion=REGION(8,4) Type=ub .declare SCALE_RESPONSE_VB Base=REG(r,nBOT_V) ElementSize=1 SrcRegion=REGION(8,4) Type=ub .declare SAMPLER_RAMP Base=REG(r,42) ElementSize=4 SrcRegion=<8;8,1> Type=f // 2 GRFs, 16 elements //#define SCALE_STEP_X REG2(r,43,0) //#define SCALE_COORD_X REG2(r,43,3) #define SCALE_LINE_P255 REG2(r,43,4) // = 255.0 Used in 'line' inst to multiply 255, add 0.5, and round to int. #define SCALE_LINE_P0_5 REG2(r,43,7) // = 0.5 //r44.0 thru r45.0 #define SCALE_COORD_Y REG(r,44) //2GRF // Send Message [DevILK] Message Descriptor // MBZ MsgL=5 MsgR=8 H MBZ SIMD MsgType SmplrIndx BindTab // 000 0 101 0 1000 1 0 10 0000 0000 00000000 // 0 A 8 A 0 0 0 0 // MsgL=1+2*2(u,v)=5 MsgR=8 #define SMPLR_MSG_DSC 0x0A8A0000 // ILK Sampler Message Descriptor // Re-define new number of lines #undef nY_NUM_OF_ROWS #undef nUV_NUM_OF_ROWS #define nY_NUM_OF_ROWS 8 #define nUV_NUM_OF_ROWS 8 #endif //_SCALING_INC_ intel-driver-1.3.0/src/shaders/post_processing/gen5_6/Makefile.am000077500000000000000000000145321231401140700247000ustar00rootroot00000000000000 INTEL_G4I = INTEL_G4A = null.g4a INTEL_G4B = null.g4b INTEL_G4B_GEN5 = null.g4b.gen5 INTEL_G6A = null.g6a INTEL_G6B = null.g6b INTEL_PP_G4B_GEN5 = \ nv12_avs_nv12.g4b.gen5 \ nv12_dn_nv12.g4b.gen5 \ nv12_dndi_nv12.g4b.gen5 \ nv12_load_save_nv12.g4b.gen5 \ nv12_load_save_pa.g4b.gen5 \ nv12_load_save_pl3.g4b.gen5 \ nv12_load_save_rgbx.g4b.gen5 \ nv12_scaling_nv12.g4b.gen5 \ pa_load_save_pa.g4b.gen5 \ pa_load_save_nv12.g4b.gen5 \ pa_load_save_pl3.g4b.gen5 \ pl3_load_save_nv12.g4b.gen5 \ pl3_load_save_pa.g4b.gen5 \ pl3_load_save_pl3.g4b.gen5 \ rgbx_load_save_nv12.g4b.gen5 \ $(NULL) INTEL_PP_G6B = \ nv12_avs_nv12.g6b \ nv12_dn_nv12.g6b \ nv12_dndi_nv12.g6b \ nv12_load_save_nv12.g6b \ nv12_load_save_pa.g6b \ nv12_load_save_pl3.g6b \ nv12_load_save_rgbx.g6b \ nv12_scaling_nv12.g6b \ pa_load_save_pa.g6b \ pa_load_save_nv12.g6b \ pa_load_save_pl3.g6b \ pl3_load_save_nv12.g6b \ pl3_load_save_pl3.g6b \ pl3_load_save_pa.g6b \ rgbx_load_save_nv12.g6b \ $(NULL) INTEL_PP_ASM = \ nv12_avs_nv12.asm \ nv12_dn_nv12.asm \ nv12_dndi_nv12.asm \ nv12_load_save_nv12.asm \ nv12_load_save_pa.asm \ nv12_load_save_pl3.asm \ nv12_load_save_rgbx.asm \ nv12_scaling_nv12.asm \ pa_load_save_pa.asm \ pa_load_save_nv12.asm \ pa_load_save_pl3.asm \ pl3_load_save_nv12.asm \ pl3_load_save_pl3.asm \ pl3_load_save_pa.asm \ rgbx_load_save_nv12.asm \ $(NULL) INTEL_PP_ASM += \ Common/AYUV_Load_16x8.asm \ Common/IMC3_Load_8x4.asm \ Common/IMC3_Load_8x5.asm \ Common/IMC3_Load_9x5.asm \ Common/Init_All_Regs.asm \ Common/Multiple_Loop.asm \ Common/Multiple_Loop_Head.asm \ Common/NV11_Load_4x8.asm \ Common/NV11_Load_5x8.asm \ Common/NV12_Load_8x4.asm \ Common/NV12_Load_8x5.asm \ Common/NV12_Load_9x5.asm \ Common/P208_Load_8x8.asm \ Common/P208_Load_9x8.asm \ Common/PA_Load_8x8.asm \ Common/PA_Load_9x8.asm \ Common/PL16x8_PL8x4.asm \ Common/PL16x8_PL8x8.asm \ Common/PL4x8_Save_NV11.asm \ Common/PL5x8_PL16x8.asm \ Common/PL5x8_PL8x8.asm \ Common/PL8x4_Save_IMC3.asm \ Common/PL8x4_Save_NV12.asm \ Common/PL8x5_PL8x8.asm \ Common/PL8x8_PL8x4.asm \ Common/PL8x8_Save_P208.asm \ Common/PL8x8_Save_PA.asm \ Common/PL9x5_PL16x8.asm \ Common/PL9x8_PL16x8.asm \ Common/RGB16x8_Save_RGB.asm \ Common/RGB16x8_Save_RGB16.asm \ Common/RGB16x8_Save_Y416.asm \ Common/RGB_Pack.asm \ Common/RGBX_Load_16x8.asm \ Common/RGBX_to_YUV_Coef.asm \ Common/RGBX_Save_YUV_Fix.asm \ Common/RGBX_Save_YUV_Float.asm \ Common/YUV_to_RGBX_Coef.asm \ Common/YUVX_Save_RGBX_Fix.asm \ Common/YUVX_Save_RGBX_Float.asm \ Common/SetupVPKernel.asm \ Common/readSampler16x1.asm \ Core_Kernels/AVS_SetupFirstBlock.asm \ Core_Kernels/AVS_SetupSecondBlock.asm \ Core_Kernels/DI_Hist_Save.asm \ Core_Kernels/DI_SAVE_PA.asm \ Core_Kernels/DNDI_COMMAND.asm \ Core_Kernels/DNDI_Hist_Save.asm \ Core_Kernels/PA_AVS_IEF_16x8.asm \ Core_Kernels/PA_AVS_IEF_8x4.asm \ Core_Kernels/PA_AVS_IEF_8x8.asm \ Core_Kernels/PA_AVS_IEF_Sample.asm \ Core_Kernels/PA_AVS_IEF_Unpack_16x8.asm \ Core_Kernels/PA_AVS_IEF_Unpack_8x4.asm \ Core_Kernels/PA_AVS_IEF_Unpack_8x8.asm \ Core_Kernels/PA_DNDI_ALG.asm \ Core_Kernels/PA_DN_ALG.asm \ Core_Kernels/PA_Scaling.asm \ Core_Kernels/PL2_AVS_IEF_16x8.asm \ Core_Kernels/PL2_AVS_IEF_8x4.asm \ Core_Kernels/PL2_AVS_IEF_8x8.asm \ Core_Kernels/PL2_AVS_IEF_Unpack_16x8.asm \ Core_Kernels/PL2_AVS_IEF_Unpack_8x4.asm \ Core_Kernels/PL2_AVS_IEF_Unpack_8x8.asm \ Core_Kernels/PL2_Scaling.asm \ Core_Kernels/PL3_AVS_IEF_16x8.asm \ Core_Kernels/PL3_AVS_IEF_8x4.asm \ Core_Kernels/PL3_AVS_IEF_8x8.asm \ Core_Kernels/PL3_AVS_IEF_Unpack_16x8.asm \ Core_Kernels/PL3_AVS_IEF_Unpack_8x4.asm \ Core_Kernels/PL3_AVS_IEF_Unpack_8x8.asm \ Core_Kernels/PL3_Scaling.asm \ Core_Kernels/PL_DNDI_ALG.asm \ Core_Kernels/PL_DNDI_ALG_UVCopy_NV11.asm \ Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm \ Core_Kernels/PL_DNDI_ALG_UVCopy_P208.asm \ Core_Kernels/PL_DNDI_ALG_UVCopy_PL3.asm \ Core_Kernels/PL_DN_ALG.asm \ Core_Kernels/RGB_AVS_IEF_16x8.asm \ Core_Kernels/RGB_AVS_IEF_Unpack_16x8.asm \ Core_Kernels/RGB_AVS_IEF_Unscramble_16x8.asm \ Core_Kernels/RGB_Scaling.asm \ $(NULL) INTEL_PP_INC = \ Common/AYUV_Load_16x8.inc \ Common/Expansion.inc \ Common/PA_Load.inc \ Common/PL2_Load.inc \ Common/PL3_Load.inc \ Common/PL4x8_Save_NV11.inc \ Common/PL8x4_Save_IMC3.inc \ Common/PL8x4_Save_NV12.inc \ Common/PL8x8_PL8x4.inc \ Common/PL8x8_Save_P208.inc \ Common/PL8x8_Save_PA.inc \ Common/RGB16x8_Save_RGB.inc \ Common/RGB16x8_Save_RGB16.inc \ Common/RGB16x8_Save_Y416.inc \ Common/RGBX_Load_16x8.inc \ Common/common.inc \ Common/undefall.inc \ Core_Kernels/AVS_IEF.inc \ Core_Kernels/DI.inc \ Core_Kernels/DNDI.inc \ Core_Kernels/Scaling.inc $(NULL) INTEL_PP_GEN5_ASM = $(INTEL_PP_G4B_GEN5:%.g4b.gen5=%.g5s) INTEL_PP_GEN6_ASM = $(INTEL_PP_G6B:%.g6b=%.g6s) TARGETS = if HAVE_GEN4ASM TARGETS += $(INTEL_PP_G4B_GEN5) TARGETS += $(INTEL_PP_G6B) endif all-local: $(TARGETS) SUFFIXES = .g4a .g4b .g4b.gen5 .g6a .g6b .g5s .g6s .asm if HAVE_GEN4ASM .g4a.g4b: $(AM_V_GEN)m4 $*.g4a > $*.g4m && \ $(AM_V_GEN)$(GEN4ASM) -o $@ $*.g4m && \ $(AM_V_GEN)$(GEN4ASM) -g 5 -o $@.gen5 $*.g4m && \ rm $*.g4m .g6a.g6b: $(AM_V_GEN)m4 $< > $*.g6m && \ $(AM_V_GEN)$(GEN4ASM) -g 6 -o $@ $*.g6m && \ rm $*.g6m $(INTEL_G4B): $(INTEL_G4I) $(INTEL_PP_GEN5_ASM): $(INTEL_PP_ASM) .asm.g5s: $(AM_V_GEN)cpp -D DEV_ILK -I Common/ -I Core_Kernels $< > _pp0.$@; \ ../../gpp.py _pp0.$@ $@; \ rm _pp0.$@ .g5s.g4b.gen5: $(AM_V_GEN)$(GEN4ASM) -a -o $@ -g 5 $< $(INTEL_PP_GEN6_ASM): $(INTEL_PP_ASM) .asm.g6s: $(AM_V_GEN)cpp -D GT -I Common/ -I Core_Kernels $< > _pp0.$@; \ ../../gpp.py _pp0.$@ $@; \ rm _pp0.$@ .g6s.g6b: $(AM_V_GEN)$(GEN4ASM) -a -o $@ -g 6 $< endif CLEANFILES = $(INTEL_PP_GEN5_ASM) $(INTEL_PP_GEN6_ASM) EXTRA_DIST = \ $(INTEL_G4A) \ $(INTEL_G4B) \ $(INTEL_G4B_GEN5) \ $(INTEL_G4I) \ $(INTEL_G6B) \ $(INTEL_PP_ASM) \ $(INTEL_PP_G4B_GEN5) \ $(INTEL_PP_G6B) \ $(INTEL_PP_INC) \ $(NULL) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/post_processing/gen5_6/null.g4a000066400000000000000000000001521231401140700242010ustar00rootroot00000000000000/* Just for test */ send(16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 {align1 EOT}; intel-driver-1.3.0/src/shaders/post_processing/gen5_6/null.g4b000066400000000000000000000000671231401140700242070ustar00rootroot00000000000000 { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/null.g4b.gen5000066400000000000000000000000671231401140700250440ustar00rootroot00000000000000 { 0x00800031, 0x24001d28, 0x748d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/null.g6a000066400000000000000000000001521231401140700242030ustar00rootroot00000000000000/* Just for test */ send(16) 0 acc0<1>UW g0<8,8,1>UW thread_spawner(0, 0, 0) mlen 1 rlen 0 {align1 EOT}; intel-driver-1.3.0/src/shaders/post_processing/gen5_6/null.g6b000066400000000000000000000000671231401140700242110ustar00rootroot00000000000000 { 0x07800031, 0x24001cc8, 0x00000000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_avs_nv12.asm000066400000000000000000000005541231401140700256470ustar00rootroot00000000000000// Module name: NV12_AVS_NV12 .kernel NV12_AVS_NV12 .code #define INC_SCALING #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #include "PL2_AVS_IEF_16x8.asm" #include "PL16x8_PL8x4.asm" #include "PL8x4_Save_NV12.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of nv12_avs_nv12.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5000066400000000000000000000225421231401140700264010ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x01000005, 0x20002d2c, 0x00000088, 0x80008000 }, { 0x00010001, 0x20c003fd, 0x00000000, 0x00000000 }, { 0x00000001, 0x212003bd, 0x000000c0, 0x00000000 }, { 0x00000001, 0x212403bd, 0x000000bc, 0x00000000 }, { 0x00000001, 0x213403bd, 0x00000038, 0x00000000 }, { 0x00200001, 0x612803bd, 0x004500a4, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0000d000 }, { 0x00802001, 0x20000022, 0x008d0100, 0x00000000 }, { 0x00000031, 0x25401c09, 0x208d0000, 0x044bb401 }, { 0x00000001, 0x21080061, 0x00000000, 0x0000a000 }, { 0x00802001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x02000031, 0x25c01c09, 0x208d0000, 0x048bb802 }, { 0x00000001, 0x240803bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x000000bc, 0x41000000 }, { 0x00000048, 0x21287fbd, 0x000000c0, 0x41e00000 }, { 0x00000001, 0x240403bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x21247fbd, 0x000000c0, 0x41000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0000d000 }, { 0x00802001, 0x20000022, 0x008d0100, 0x00000000 }, { 0x00000031, 0x27401c09, 0x208d0000, 0x044bb401 }, { 0x00000001, 0x21080061, 0x00000000, 0x0000a000 }, { 0x00802001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x02000031, 0x27c01c09, 0x208d0000, 0x048bb802 }, { 0x00600001, 0x21400229, 0x00aa0541, 0x00000000 }, { 0x00600001, 0x21600229, 0x00aa0549, 0x00000000 }, { 0x00600001, 0x21800229, 0x00aa0561, 0x00000000 }, { 0x00600001, 0x21a00229, 0x00aa0569, 0x00000000 }, { 0x00600001, 0x21c00229, 0x00aa0581, 0x00000000 }, { 0x00600001, 0x21e00229, 0x00aa0589, 0x00000000 }, { 0x00600001, 0x22000229, 0x00aa05a1, 0x00000000 }, { 0x00600001, 0x22200229, 0x00aa05a9, 0x00000000 }, { 0x00600001, 0x22400229, 0x00aa05c1, 0x00000000 }, { 0x00600001, 0x22600229, 0x00aa05c9, 0x00000000 }, { 0x00600001, 0x22800229, 0x00aa05e1, 0x00000000 }, { 0x00600001, 0x22a00229, 0x00aa05e9, 0x00000000 }, { 0x00600001, 0x22c00229, 0x00aa0641, 0x00000000 }, { 0x00600001, 0x22e00229, 0x00aa0649, 0x00000000 }, { 0x00600001, 0x23000229, 0x00aa0661, 0x00000000 }, { 0x00600001, 0x23200229, 0x00aa0669, 0x00000000 }, { 0x00600001, 0x23400229, 0x00aa0601, 0x00000000 }, { 0x00600001, 0x23600229, 0x00aa0609, 0x00000000 }, { 0x00600001, 0x23800229, 0x00aa0621, 0x00000000 }, { 0x00600001, 0x23a00229, 0x00aa0629, 0x00000000 }, { 0x00600001, 0x23c00229, 0x00aa0681, 0x00000000 }, { 0x00600001, 0x23e00229, 0x00aa0689, 0x00000000 }, { 0x00600001, 0x24000229, 0x00aa06a1, 0x00000000 }, { 0x00600001, 0x24200229, 0x00aa06a9, 0x00000000 }, { 0x00600001, 0x21500229, 0x00aa0741, 0x00000000 }, { 0x00600001, 0x21700229, 0x00aa0749, 0x00000000 }, { 0x00600001, 0x21900229, 0x00aa0761, 0x00000000 }, { 0x00600001, 0x21b00229, 0x00aa0769, 0x00000000 }, { 0x00600001, 0x21d00229, 0x00aa0781, 0x00000000 }, { 0x00600001, 0x21f00229, 0x00aa0789, 0x00000000 }, { 0x00600001, 0x22100229, 0x00aa07a1, 0x00000000 }, { 0x00600001, 0x22300229, 0x00aa07a9, 0x00000000 }, { 0x00600001, 0x22500229, 0x00aa07c1, 0x00000000 }, { 0x00600001, 0x22700229, 0x00aa07c9, 0x00000000 }, { 0x00600001, 0x22900229, 0x00aa07e1, 0x00000000 }, { 0x00600001, 0x22b00229, 0x00aa07e9, 0x00000000 }, { 0x00600001, 0x22d00229, 0x00aa0841, 0x00000000 }, { 0x00600001, 0x22f00229, 0x00aa0849, 0x00000000 }, { 0x00600001, 0x23100229, 0x00aa0861, 0x00000000 }, { 0x00600001, 0x23300229, 0x00aa0869, 0x00000000 }, { 0x00600001, 0x23500229, 0x00aa0801, 0x00000000 }, { 0x00600001, 0x23700229, 0x00aa0809, 0x00000000 }, { 0x00600001, 0x23900229, 0x00aa0821, 0x00000000 }, { 0x00600001, 0x23b00229, 0x00aa0829, 0x00000000 }, { 0x00600001, 0x23d00229, 0x00aa0881, 0x00000000 }, { 0x00600001, 0x23f00229, 0x00aa0889, 0x00000000 }, { 0x00600001, 0x24100229, 0x00aa08a1, 0x00000000 }, { 0x00600001, 0x24300229, 0x00aa08a9, 0x00000000 }, { 0x00600001, 0x22400129, 0x00ae0240, 0x00000000 }, { 0x00600001, 0x23400129, 0x00ae0340, 0x00000000 }, { 0x00600001, 0x22500129, 0x00ae0280, 0x00000000 }, { 0x00600001, 0x23500129, 0x00ae0380, 0x00000000 }, { 0x00600001, 0x22600129, 0x00ae02c0, 0x00000000 }, { 0x00600001, 0x23600129, 0x00ae03c0, 0x00000000 }, { 0x00600001, 0x22700129, 0x00ae0300, 0x00000000 }, { 0x00600001, 0x23700129, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x28000c01, 0x408d0000, 0x0228a008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x0a082007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x06082008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00000041, 0x24407fbd, 0x000000bc, 0x41800000 }, { 0x00000040, 0x20a477bd, 0x00000440, 0x000000a4 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xfffffec6 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000001, 0x20a403bd, 0x00000094, 0x00000000 }, { 0x00000041, 0x24407fbd, 0x00000038, 0x41000000 }, { 0x00000040, 0x20a877bd, 0x00000440, 0x000000a8 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffeba }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b000066400000000000000000000324211231401140700255430ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x01000005, 0x20002d2c, 0x00000088, 0x80008000 }, { 0x00010001, 0x20c003fd, 0x00000000, 0x00000000 }, { 0x00000001, 0x212003bd, 0x000000c0, 0x00000000 }, { 0x00000001, 0x212403bd, 0x000000bc, 0x00000000 }, { 0x00000001, 0x213403bd, 0x00000038, 0x00000000 }, { 0x00200001, 0x612803bd, 0x004500a4, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0000d000 }, { 0x00800001, 0x20000022, 0x008d0100, 0x00000000 }, { 0x02000031, 0x25401cc9, 0x00000000, 0x044bb401 }, { 0x00000001, 0x21080061, 0x00000000, 0x0000a000 }, { 0x00800001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x02000031, 0x25c01cc9, 0x00000040, 0x048bb802 }, { 0x00000001, 0x240803bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x000000bc, 0x41000000 }, { 0x00000048, 0x21287fbd, 0x000000c0, 0x41e00000 }, { 0x00000001, 0x240403bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x21247fbd, 0x000000c0, 0x41000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0000d000 }, { 0x00800001, 0x20000022, 0x008d0100, 0x00000000 }, { 0x02000031, 0x27401cc9, 0x00000000, 0x044bb401 }, { 0x00000001, 0x21080061, 0x00000000, 0x0000a000 }, { 0x00800001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x02000031, 0x27c01cc9, 0x00000040, 0x048bb802 }, { 0x00600001, 0x21400229, 0x00aa0541, 0x00000000 }, { 0x00600001, 0x21600229, 0x00aa0549, 0x00000000 }, { 0x00600001, 0x21800229, 0x00aa0561, 0x00000000 }, { 0x00600001, 0x21a00229, 0x00aa0569, 0x00000000 }, { 0x00600001, 0x21c00229, 0x00aa0581, 0x00000000 }, { 0x00600001, 0x21e00229, 0x00aa0589, 0x00000000 }, { 0x00600001, 0x22000229, 0x00aa05a1, 0x00000000 }, { 0x00600001, 0x22200229, 0x00aa05a9, 0x00000000 }, { 0x00600001, 0x22400229, 0x00aa05c1, 0x00000000 }, { 0x00600001, 0x22600229, 0x00aa05c9, 0x00000000 }, { 0x00600001, 0x22800229, 0x00aa05e1, 0x00000000 }, { 0x00600001, 0x22a00229, 0x00aa05e9, 0x00000000 }, { 0x00600001, 0x22c00229, 0x00aa0641, 0x00000000 }, { 0x00600001, 0x22e00229, 0x00aa0649, 0x00000000 }, { 0x00600001, 0x23000229, 0x00aa0661, 0x00000000 }, { 0x00600001, 0x23200229, 0x00aa0669, 0x00000000 }, { 0x00600001, 0x23400229, 0x00aa0601, 0x00000000 }, { 0x00600001, 0x23600229, 0x00aa0609, 0x00000000 }, { 0x00600001, 0x23800229, 0x00aa0621, 0x00000000 }, { 0x00600001, 0x23a00229, 0x00aa0629, 0x00000000 }, { 0x00600001, 0x23c00229, 0x00aa0681, 0x00000000 }, { 0x00600001, 0x23e00229, 0x00aa0689, 0x00000000 }, { 0x00600001, 0x24000229, 0x00aa06a1, 0x00000000 }, { 0x00600001, 0x24200229, 0x00aa06a9, 0x00000000 }, { 0x00600001, 0x21500229, 0x00aa0741, 0x00000000 }, { 0x00600001, 0x21700229, 0x00aa0749, 0x00000000 }, { 0x00600001, 0x21900229, 0x00aa0761, 0x00000000 }, { 0x00600001, 0x21b00229, 0x00aa0769, 0x00000000 }, { 0x00600001, 0x21d00229, 0x00aa0781, 0x00000000 }, { 0x00600001, 0x21f00229, 0x00aa0789, 0x00000000 }, { 0x00600001, 0x22100229, 0x00aa07a1, 0x00000000 }, { 0x00600001, 0x22300229, 0x00aa07a9, 0x00000000 }, { 0x00600001, 0x22500229, 0x00aa07c1, 0x00000000 }, { 0x00600001, 0x22700229, 0x00aa07c9, 0x00000000 }, { 0x00600001, 0x22900229, 0x00aa07e1, 0x00000000 }, { 0x00600001, 0x22b00229, 0x00aa07e9, 0x00000000 }, { 0x00600001, 0x22d00229, 0x00aa0841, 0x00000000 }, { 0x00600001, 0x22f00229, 0x00aa0849, 0x00000000 }, { 0x00600001, 0x23100229, 0x00aa0861, 0x00000000 }, { 0x00600001, 0x23300229, 0x00aa0869, 0x00000000 }, { 0x00600001, 0x23500229, 0x00aa0801, 0x00000000 }, { 0x00600001, 0x23700229, 0x00aa0809, 0x00000000 }, { 0x00600001, 0x23900229, 0x00aa0821, 0x00000000 }, { 0x00600001, 0x23b00229, 0x00aa0829, 0x00000000 }, { 0x00600001, 0x23d00229, 0x00aa0881, 0x00000000 }, { 0x00600001, 0x23f00229, 0x00aa0889, 0x00000000 }, { 0x00600001, 0x24100229, 0x00aa08a1, 0x00000000 }, { 0x00600001, 0x24300229, 0x00aa08a9, 0x00000000 }, { 0x00600001, 0x22400129, 0x00ae0240, 0x00000000 }, { 0x00600001, 0x23400129, 0x00ae0340, 0x00000000 }, { 0x00600001, 0x22500129, 0x00ae0280, 0x00000000 }, { 0x00600001, 0x23500129, 0x00ae0380, 0x00000000 }, { 0x00600001, 0x22600129, 0x00ae02c0, 0x00000000 }, { 0x00600001, 0x23600129, 0x00ae03c0, 0x00000000 }, { 0x00600001, 0x22700129, 0x00ae0300, 0x00000000 }, { 0x00600001, 0x23700129, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000020, 0x02298008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x0a094007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x06094008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00000041, 0x24407fbd, 0x000000bc, 0x41800000 }, { 0x00000040, 0x20a477bd, 0x00000440, 0x000000a4 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xfffffec6 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000001, 0x20a403bd, 0x00000094, 0x00000000 }, { 0x00000041, 0x24407fbd, 0x00000038, 0x41000000 }, { 0x00000040, 0x20a877bd, 0x00000440, 0x000000a8 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffeba }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_dn_nv12.asm000066400000000000000000000006331231401140700254550ustar00rootroot00000000000000// Module name: NV12_DN_NV12 .kernel NV12_DN_NV12 .code #define INC_DN #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #define LOAD_UV_ONLY #include "NV12_Load_8x4.asm" #undef LOAD_UV_ONLY #include "PL_DN_ALG.asm" #include "PL8x4_Save_NV12.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of nv12_dn_nv12.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5000066400000000000000000000144431231401140700262120ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x02600031, 0x28000c01, 0x408d0000, 0x0228a002 }, { 0x00800001, 0x22600229, 0x00d20820, 0x00000000 }, { 0x00800001, 0x23600229, 0x00d20821, 0x00000000 }, { 0x00800001, 0x22400229, 0x00d20800, 0x00000000 }, { 0x00800001, 0x23400229, 0x00d20801, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x204801aa, 0x000000a0, 0x00000000 }, { 0x00000001, 0x205801aa, 0x000000a2, 0x00000000 }, { 0x01600031, 0x24400c01, 0x208d0000, 0x045b8004 }, { 0x00800001, 0x21400229, 0x00b10440, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10450, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10460, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10470, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10480, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10490, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b104a0, 0x00000000 }, { 0x00800001, 0x22200229, 0x00b104b0, 0x00000000 }, { 0x00200008, 0x21003da1, 0x004500a0, 0x00020002 }, { 0x00000040, 0x21002421, 0x00000100, 0x00000034 }, { 0x00000001, 0x21080061, 0x00000000, 0x00010003 }, { 0x00600001, 0x21a00022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x21c00022, 0x004504c0, 0x00000000 }, { 0x0d600031, 0x20000c04, 0x508d0000, 0x04082014 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x28000c01, 0x408d0000, 0x0228a008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x0a082007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x06082008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff32 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff2c }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b000066400000000000000000000243221231401140700253540ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000040, 0x02298002 }, { 0x00800001, 0x22600229, 0x00d20820, 0x00000000 }, { 0x00800001, 0x23600229, 0x00d20821, 0x00000000 }, { 0x00800001, 0x22400229, 0x00d20800, 0x00000000 }, { 0x00800001, 0x23400229, 0x00d20801, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x204801aa, 0x000000a0, 0x00000000 }, { 0x00000001, 0x205801aa, 0x000000a2, 0x00000000 }, { 0x02600031, 0x24400cc1, 0x00000020, 0x045b8004 }, { 0x00800001, 0x21400229, 0x00b10440, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10450, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10460, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10470, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10480, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10490, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b104a0, 0x00000000 }, { 0x00800001, 0x22200229, 0x00b104b0, 0x00000000 }, { 0x00200008, 0x21003da1, 0x004500a0, 0x00020002 }, { 0x00000040, 0x21002421, 0x00000100, 0x00000034 }, { 0x00000001, 0x21080061, 0x00000000, 0x00010003 }, { 0x00600001, 0x21a00022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x21c00022, 0x004504c0, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x000001a0, 0x04094014 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000020, 0x02298008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x0a094007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x06094008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff32 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff2c }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.asm000066400000000000000000000004601231401140700257700ustar00rootroot00000000000000// Module name: NV12_DNDI_NV12 .kernel NV12_DNDI_NV12 .code #define INC_DNDI #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #include "PL_DNDI_ALG_UVCopy_NV12.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of nv12_dndi_nv12.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5000066400000000000000000000117041231401140700265240ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x204801aa, 0x000000a0, 0x00000000 }, { 0x00000001, 0x205801aa, 0x000000a2, 0x00000000 }, { 0x01600031, 0x24400c01, 0x208d0000, 0x04cb8004 }, { 0x00800001, 0x21400229, 0x00b10440, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10450, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10460, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10470, 0x00000000 }, { 0x00600001, 0x22400229, 0x00ae0481, 0x00000000 }, { 0x00600001, 0x23400229, 0x00ae0480, 0x00000000 }, { 0x00600001, 0x22500229, 0x00ae0491, 0x00000000 }, { 0x00600001, 0x23500229, 0x00ae0490, 0x00000000 }, { 0x00600001, 0x22600229, 0x00ae04a1, 0x00000000 }, { 0x00600001, 0x23600229, 0x00ae04a0, 0x00000000 }, { 0x00600001, 0x22700229, 0x00ae04b1, 0x00000000 }, { 0x00600001, 0x23700229, 0x00ae04b0, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b104d0, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b104e0, 0x00000000 }, { 0x00800001, 0x22200229, 0x00b104f0, 0x00000000 }, { 0x00600001, 0x22800229, 0x00ae0501, 0x00000000 }, { 0x00600001, 0x23800229, 0x00ae0500, 0x00000000 }, { 0x00600001, 0x22900229, 0x00ae0511, 0x00000000 }, { 0x00600001, 0x23900229, 0x00ae0510, 0x00000000 }, { 0x00600001, 0x22a00229, 0x00ae0521, 0x00000000 }, { 0x00600001, 0x23a00229, 0x00ae0520, 0x00000000 }, { 0x00600001, 0x22b00229, 0x00ae0531, 0x00000000 }, { 0x00600001, 0x23b00229, 0x00ae0530, 0x00000000 }, { 0x00000008, 0x21003da1, 0x000000a0, 0x00010001 }, { 0x00000001, 0x210401a1, 0x000000a2, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x21600022, 0x008d0100, 0x00000000 }, { 0x00600001, 0x21800022, 0x008d0540, 0x00000000 }, { 0x0b600031, 0x20000c04, 0x508d0000, 0x04082014 }, { 0x00200008, 0x21003da1, 0x004500a0, 0x00020002 }, { 0x00000040, 0x21002421, 0x00000100, 0x00000034 }, { 0x00000001, 0x21080061, 0x00000000, 0x00000003 }, { 0x00600001, 0x21a00022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x21c00022, 0x00000560, 0x00000000 }, { 0x0d600031, 0x20000c04, 0x508d0000, 0x04082014 }, { 0x00400040, 0x22083e28, 0x00690024, 0x07000700 }, { 0x01000010, 0x20003e2c, 0x0000003b, 0x00010001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00400001, 0x20400022, 0x00690580, 0x00000000 }, { 0x00400001, 0x20500022, 0x006904d0, 0x00000000 }, { 0x00400001, 0x20600022, 0x00690590, 0x00000000 }, { 0x00400001, 0x20700022, 0x006904f0, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00400001, 0x20400022, 0x006904c0, 0x00000000 }, { 0x00400001, 0x20500022, 0x00690580, 0x00000000 }, { 0x00400001, 0x20600022, 0x006904e0, 0x00000000 }, { 0x00400001, 0x20700022, 0x00690590, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b104d0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b104e0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b104f0, 0x00000000 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x06082007 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0001000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00600001, 0x40400232, 0x00ae0501, 0x00000000 }, { 0x00600001, 0x40410232, 0x00ae0510, 0x00000000 }, { 0x00600001, 0x40500232, 0x00ae0521, 0x00000000 }, { 0x00600001, 0x40510232, 0x00ae0530, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x04082008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff64 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff5e }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b000066400000000000000000000215631231401140700256750ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x204801aa, 0x000000a0, 0x00000000 }, { 0x00000001, 0x205801aa, 0x000000a2, 0x00000000 }, { 0x02600031, 0x24400cc1, 0x00000020, 0x04cb8004 }, { 0x00800001, 0x21400229, 0x00b10440, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10450, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10460, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10470, 0x00000000 }, { 0x00600001, 0x22400229, 0x00ae0481, 0x00000000 }, { 0x00600001, 0x23400229, 0x00ae0480, 0x00000000 }, { 0x00600001, 0x22500229, 0x00ae0491, 0x00000000 }, { 0x00600001, 0x23500229, 0x00ae0490, 0x00000000 }, { 0x00600001, 0x22600229, 0x00ae04a1, 0x00000000 }, { 0x00600001, 0x23600229, 0x00ae04a0, 0x00000000 }, { 0x00600001, 0x22700229, 0x00ae04b1, 0x00000000 }, { 0x00600001, 0x23700229, 0x00ae04b0, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b104d0, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b104e0, 0x00000000 }, { 0x00800001, 0x22200229, 0x00b104f0, 0x00000000 }, { 0x00600001, 0x22800229, 0x00ae0501, 0x00000000 }, { 0x00600001, 0x23800229, 0x00ae0500, 0x00000000 }, { 0x00600001, 0x22900229, 0x00ae0511, 0x00000000 }, { 0x00600001, 0x23900229, 0x00ae0510, 0x00000000 }, { 0x00600001, 0x22a00229, 0x00ae0521, 0x00000000 }, { 0x00600001, 0x23a00229, 0x00ae0520, 0x00000000 }, { 0x00600001, 0x22b00229, 0x00ae0531, 0x00000000 }, { 0x00600001, 0x23b00229, 0x00ae0530, 0x00000000 }, { 0x00000008, 0x21003da1, 0x000000a0, 0x00010001 }, { 0x00000001, 0x210401a1, 0x000000a2, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x21600022, 0x008d0100, 0x00000000 }, { 0x00600001, 0x21800022, 0x008d0540, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000160, 0x04094014 }, { 0x00200008, 0x21003da1, 0x004500a0, 0x00020002 }, { 0x00000040, 0x21002421, 0x00000100, 0x00000034 }, { 0x00000001, 0x21080061, 0x00000000, 0x00000003 }, { 0x00600001, 0x21a00022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x21c00022, 0x00000560, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x000001a0, 0x04094014 }, { 0x00400040, 0x22083e28, 0x00690024, 0x07000700 }, { 0x01000010, 0x20003e2c, 0x0000003b, 0x00010001 }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00400001, 0x20400022, 0x00690580, 0x00000000 }, { 0x00400001, 0x20500022, 0x006904d0, 0x00000000 }, { 0x00400001, 0x20600022, 0x00690590, 0x00000000 }, { 0x00400001, 0x20700022, 0x006904f0, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00400001, 0x20400022, 0x006904c0, 0x00000000 }, { 0x00400001, 0x20500022, 0x00690580, 0x00000000 }, { 0x00400001, 0x20600022, 0x006904e0, 0x00000000 }, { 0x00400001, 0x20700022, 0x00690590, 0x00000000 }, { 0x00800001, 0x20400232, 0x00b104c0, 0x00000000 }, { 0x00800001, 0x20500232, 0x00b104d0, 0x00000000 }, { 0x00800001, 0x20600232, 0x00b104e0, 0x00000000 }, { 0x00800001, 0x20700232, 0x00b104f0, 0x00000000 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x06094007 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0001000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00600001, 0x40400232, 0x00ae0501, 0x00000000 }, { 0x00600001, 0x40410232, 0x00ae0510, 0x00000000 }, { 0x00600001, 0x40500232, 0x00ae0521, 0x00000000 }, { 0x00600001, 0x40510232, 0x00ae0530, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x04094008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff64 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff5e }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_load_save_nv12.asm000066400000000000000000000005021231401140700270040ustar00rootroot00000000000000// Module name: NV12_LOAD_SAVE_NV12 .kernel NV12_LOAD_SAVE_NV12 .code #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #include "NV12_Load_8x4.asm" #include "PL8x4_Save_NV12.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of nv12_load_save_nv12.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5000066400000000000000000000136421231401140700275460ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a001 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x02600031, 0x28000c01, 0x408d0000, 0x0228a002 }, { 0x00800001, 0x22200229, 0x00b10770, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b10760, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10750, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10740, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10730, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10720, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10710, 0x00000000 }, { 0x00800001, 0x21400229, 0x00b10700, 0x00000000 }, { 0x00800001, 0x22600229, 0x00d20820, 0x00000000 }, { 0x00800001, 0x23600229, 0x00d20821, 0x00000000 }, { 0x00800001, 0x22400229, 0x00d20800, 0x00000000 }, { 0x00800001, 0x23400229, 0x00d20801, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x28000c01, 0x408d0000, 0x0228a008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x0a082007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x06082008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff40 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff3a }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b000066400000000000000000000235211231401140700267100ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498001 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000040, 0x02298002 }, { 0x00800001, 0x22200229, 0x00b10770, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b10760, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10750, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10740, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10730, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10720, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10710, 0x00000000 }, { 0x00800001, 0x21400229, 0x00b10700, 0x00000000 }, { 0x00800001, 0x22600229, 0x00d20820, 0x00000000 }, { 0x00800001, 0x23600229, 0x00d20821, 0x00000000 }, { 0x00800001, 0x22400229, 0x00d20800, 0x00000000 }, { 0x00800001, 0x23400229, 0x00d20801, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000020, 0x02298008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x0a094007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x06094008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff40 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff3a }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_load_save_pa.asm000077500000000000000000000005741231401140700266320ustar00rootroot00000000000000// Module name: NV12_LOAD_SAVE_pl1 .kernel NV12_LOAD_SAVE_PL1 // what's usage of it? just a name? .code #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #include "NV12_Load_8x5.asm" #include "PL8x5_PL8x8.asm" #include "PL8x8_Save_PA.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of nv12_load_save_pl1.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5000066400000000000000000000147771231401140700273720ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a001 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0004000f }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x02600031, 0x28000c01, 0x408d0000, 0x0238a002 }, { 0x00800001, 0x22200229, 0x00b10770, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b10760, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10750, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10740, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10730, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10720, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10710, 0x00000000 }, { 0x00800001, 0x21400229, 0x00b10700, 0x00000000 }, { 0x00800001, 0x22800229, 0x00ae0840, 0x00000000 }, { 0x00800001, 0x23800229, 0x00ae0841, 0x00000000 }, { 0x00800001, 0x22600229, 0x00ae0820, 0x00000000 }, { 0x00800001, 0x23600229, 0x00ae0821, 0x00000000 }, { 0x00800001, 0x22400229, 0x00ae0800, 0x00000000 }, { 0x00800001, 0x23400229, 0x00ae0801, 0x00000000 }, { 0x80600042, 0x22b02529, 0x008d0270, 0x008d0280 }, { 0x80600042, 0x23b02529, 0x008d0370, 0x008d0380 }, { 0x00600001, 0x22a00129, 0x008d0270, 0x00000000 }, { 0x80600042, 0x22902529, 0x008d0260, 0x008d0270 }, { 0x00600001, 0x23a00129, 0x008d0370, 0x00000000 }, { 0x80600042, 0x23902529, 0x008d0360, 0x008d0370 }, { 0x00600001, 0x22800129, 0x008d0260, 0x00000000 }, { 0x80600042, 0x22702529, 0x008d0250, 0x008d0260 }, { 0x00600001, 0x23800129, 0x008d0360, 0x00000000 }, { 0x80600042, 0x23702529, 0x008d0350, 0x008d0360 }, { 0x00600001, 0x22600129, 0x008d0250, 0x00000000 }, { 0x80600042, 0x22502529, 0x008d0240, 0x008d0250 }, { 0x00600001, 0x23600129, 0x008d0350, 0x00000000 }, { 0x80600042, 0x23502529, 0x008d0340, 0x008d0350 }, { 0x00400040, 0x22083e28, 0x00690028, 0x07000700 }, { 0x00800001, 0xd0000231, 0x00d20140, 0x00000000 }, { 0x00800001, 0xd0200231, 0x00d20160, 0x00000000 }, { 0x00800001, 0xd0400231, 0x00d20180, 0x00000000 }, { 0x00800001, 0xd0600231, 0x00d201a0, 0x00000000 }, { 0x00800001, 0xd0800231, 0x00d201c0, 0x00000000 }, { 0x00800001, 0xd0a00231, 0x00d201e0, 0x00000000 }, { 0x00800001, 0xd0c00231, 0x00d20200, 0x00000000 }, { 0x00800001, 0xd0e00231, 0x00d20220, 0x00000000 }, { 0x00600001, 0xf4000231, 0x00ae0240, 0x00000000 }, { 0x00600001, 0xf8000231, 0x00ae0340, 0x00000000 }, { 0x00600001, 0xf4200231, 0x00ae0250, 0x00000000 }, { 0x00600001, 0xf8200231, 0x00ae0350, 0x00000000 }, { 0x00600001, 0xf4400231, 0x00ae0260, 0x00000000 }, { 0x00600001, 0xf8400231, 0x00ae0360, 0x00000000 }, { 0x00600001, 0xf4600231, 0x00ae0270, 0x00000000 }, { 0x00600001, 0xf8600231, 0x00ae0370, 0x00000000 }, { 0x00600001, 0xf4800231, 0x00ae0280, 0x00000000 }, { 0x00600001, 0xf8800231, 0x00ae0380, 0x00000000 }, { 0x00600001, 0xf4a00231, 0x00ae0290, 0x00000000 }, { 0x00600001, 0xf8a00231, 0x00ae0390, 0x00000000 }, { 0x00600001, 0xf4c00231, 0x00ae02a0, 0x00000000 }, { 0x00600001, 0xf8c00231, 0x00ae03a0, 0x00000000 }, { 0x00600001, 0xf4e00231, 0x00ae02b0, 0x00000000 }, { 0x00600001, 0xf8e00231, 0x00ae03b0, 0x00000000 }, { 0x00000409, 0x21003da5, 0x000000a0, 0x00010001 }, { 0x00000c01, 0x210401a5, 0x000000a2, 0x00000000 }, { 0x00000801, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000002a }, { 0x01600031, 0x21400c01, 0x408d0000, 0x0288a007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x27000129, 0x02b10140, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x27200129, 0x02b10160, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x27400129, 0x02b10180, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x27600129, 0x02b101a0, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x27800129, 0x02b101c0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x27a00129, 0x02b101e0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x27c00129, 0x02b10200, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x27e00129, 0x02b10220, 0x00000000 }, { 0x00600001, 0x20400022, 0x008d0700, 0x00000000 }, { 0x00600001, 0x20600022, 0x008d0720, 0x00000000 }, { 0x00600001, 0x20800022, 0x008d0740, 0x00000000 }, { 0x00600001, 0x20a00022, 0x008d0760, 0x00000000 }, { 0x00600001, 0x20c00022, 0x008d0780, 0x00000000 }, { 0x00600001, 0x20e00022, 0x008d07a0, 0x00000000 }, { 0x00600001, 0x21000022, 0x008d07c0, 0x00000000 }, { 0x00600001, 0x21200022, 0x008d07e0, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x12082007 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff2a }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff24 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b000066400000000000000000000246561231401140700265340ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498001 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0004000f }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000040, 0x02398002 }, { 0x00800001, 0x22200229, 0x00b10770, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b10760, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10750, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10740, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10730, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10720, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10710, 0x00000000 }, { 0x00800001, 0x21400229, 0x00b10700, 0x00000000 }, { 0x00800001, 0x22800229, 0x00ae0840, 0x00000000 }, { 0x00800001, 0x23800229, 0x00ae0841, 0x00000000 }, { 0x00800001, 0x22600229, 0x00ae0820, 0x00000000 }, { 0x00800001, 0x23600229, 0x00ae0821, 0x00000000 }, { 0x00800001, 0x22400229, 0x00ae0800, 0x00000000 }, { 0x00800001, 0x23400229, 0x00ae0801, 0x00000000 }, { 0x80600042, 0x22b02529, 0x008d0270, 0x008d0280 }, { 0x80600042, 0x23b02529, 0x008d0370, 0x008d0380 }, { 0x00600001, 0x22a00129, 0x008d0270, 0x00000000 }, { 0x80600042, 0x22902529, 0x008d0260, 0x008d0270 }, { 0x00600001, 0x23a00129, 0x008d0370, 0x00000000 }, { 0x80600042, 0x23902529, 0x008d0360, 0x008d0370 }, { 0x00600001, 0x22800129, 0x008d0260, 0x00000000 }, { 0x80600042, 0x22702529, 0x008d0250, 0x008d0260 }, { 0x00600001, 0x23800129, 0x008d0360, 0x00000000 }, { 0x80600042, 0x23702529, 0x008d0350, 0x008d0360 }, { 0x00600001, 0x22600129, 0x008d0250, 0x00000000 }, { 0x80600042, 0x22502529, 0x008d0240, 0x008d0250 }, { 0x00600001, 0x23600129, 0x008d0350, 0x00000000 }, { 0x80600042, 0x23502529, 0x008d0340, 0x008d0350 }, { 0x00400040, 0x22083e28, 0x00690028, 0x07000700 }, { 0x00800001, 0xd0000231, 0x00d20140, 0x00000000 }, { 0x00800001, 0xd0200231, 0x00d20160, 0x00000000 }, { 0x00800001, 0xd0400231, 0x00d20180, 0x00000000 }, { 0x00800001, 0xd0600231, 0x00d201a0, 0x00000000 }, { 0x00800001, 0xd0800231, 0x00d201c0, 0x00000000 }, { 0x00800001, 0xd0a00231, 0x00d201e0, 0x00000000 }, { 0x00800001, 0xd0c00231, 0x00d20200, 0x00000000 }, { 0x00800001, 0xd0e00231, 0x00d20220, 0x00000000 }, { 0x00600001, 0xf4000231, 0x00ae0240, 0x00000000 }, { 0x00600001, 0xf8000231, 0x00ae0340, 0x00000000 }, { 0x00600001, 0xf4200231, 0x00ae0250, 0x00000000 }, { 0x00600001, 0xf8200231, 0x00ae0350, 0x00000000 }, { 0x00600001, 0xf4400231, 0x00ae0260, 0x00000000 }, { 0x00600001, 0xf8400231, 0x00ae0360, 0x00000000 }, { 0x00600001, 0xf4600231, 0x00ae0270, 0x00000000 }, { 0x00600001, 0xf8600231, 0x00ae0370, 0x00000000 }, { 0x00600001, 0xf4800231, 0x00ae0280, 0x00000000 }, { 0x00600001, 0xf8800231, 0x00ae0380, 0x00000000 }, { 0x00600001, 0xf4a00231, 0x00ae0290, 0x00000000 }, { 0x00600001, 0xf8a00231, 0x00ae0390, 0x00000000 }, { 0x00600001, 0xf4c00231, 0x00ae02a0, 0x00000000 }, { 0x00600001, 0xf8c00231, 0x00ae03a0, 0x00000000 }, { 0x00600001, 0xf4e00231, 0x00ae02b0, 0x00000000 }, { 0x00600001, 0xf8e00231, 0x00ae03b0, 0x00000000 }, { 0x00000409, 0x21003da5, 0x000000a0, 0x00010001 }, { 0x00000c01, 0x210401a5, 0x000000a2, 0x00000000 }, { 0x00000801, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000002a }, { 0x04600031, 0x21400cc1, 0x00000020, 0x02898007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x27000129, 0x02b10140, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x27200129, 0x02b10160, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x27400129, 0x02b10180, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x27600129, 0x02b101a0, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x27800129, 0x02b101c0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x27a00129, 0x02b101e0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x27c00129, 0x02b10200, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x27e00129, 0x02b10220, 0x00000000 }, { 0x00600001, 0x20400022, 0x008d0700, 0x00000000 }, { 0x00600001, 0x20600022, 0x008d0720, 0x00000000 }, { 0x00600001, 0x20800022, 0x008d0740, 0x00000000 }, { 0x00600001, 0x20a00022, 0x008d0760, 0x00000000 }, { 0x00600001, 0x20c00022, 0x008d0780, 0x00000000 }, { 0x00600001, 0x20e00022, 0x008d07a0, 0x00000000 }, { 0x00600001, 0x21000022, 0x008d07c0, 0x00000000 }, { 0x00600001, 0x21200022, 0x008d07e0, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x12094007 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff2a }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff24 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_load_save_pl3.asm000066400000000000000000000004771231401140700267270ustar00rootroot00000000000000// Module name: NV12_LOAD_SAVE_PL3 .kernel NV12_LOAD_SAVE_PL3 .code #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #include "NV12_Load_8x4.asm" #include "PL8x4_Save_IMC3.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of nv12_load_save_pl3.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5000066400000000000000000000135531231401140700274570ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a001 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x02600031, 0x28000c01, 0x408d0000, 0x0228a002 }, { 0x00800001, 0x22200229, 0x00b10770, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b10760, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10750, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10740, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10730, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10720, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10710, 0x00000000 }, { 0x00800001, 0x21400229, 0x00b10700, 0x00000000 }, { 0x00800001, 0x22600229, 0x00d20820, 0x00000000 }, { 0x00800001, 0x23600229, 0x00d20821, 0x00000000 }, { 0x00800001, 0x22400229, 0x00d20800, 0x00000000 }, { 0x00800001, 0x23400229, 0x00d20801, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a007 }, { 0x0020000c, 0x21003da5, 0x004500a0, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x28000c01, 0x408d0000, 0x0218a008 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x29000c01, 0x408d0000, 0x0218a009 }, { 0x00800001, 0x28200229, 0x008d0810, 0x00000000 }, { 0x00800001, 0x29200229, 0x008d0910, 0x00000000 }, { 0x00800001, 0x28000229, 0x008d0800, 0x00000000 }, { 0x00800001, 0x29000229, 0x008d0900, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x00910001, 0x22400231, 0x028d0800, 0x00000000 }, { 0x00910001, 0x23400231, 0x028d0900, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x00910001, 0x22500231, 0x028d0810, 0x00000000 }, { 0x00910001, 0x23500231, 0x028d0910, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x00910001, 0x22600231, 0x028d0820, 0x00000000 }, { 0x00910001, 0x23600231, 0x028d0920, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x00910001, 0x22700231, 0x028d0830, 0x00000000 }, { 0x00910001, 0x23700231, 0x028d0930, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x0a082007 }, { 0x0020000c, 0x21003da5, 0x004500a0, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20260, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x04082008 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20360, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x04082009 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff42 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff3c }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b000066400000000000000000000234321231401140700266210ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498001 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000040, 0x02298002 }, { 0x00800001, 0x22200229, 0x00b10770, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b10760, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10750, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10740, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10730, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10720, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10710, 0x00000000 }, { 0x00800001, 0x21400229, 0x00b10700, 0x00000000 }, { 0x00800001, 0x22600229, 0x00d20820, 0x00000000 }, { 0x00800001, 0x23600229, 0x00d20821, 0x00000000 }, { 0x00800001, 0x22400229, 0x00d20800, 0x00000000 }, { 0x00800001, 0x23400229, 0x00d20801, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498007 }, { 0x0020000c, 0x21003da5, 0x004500a0, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000020, 0x02198008 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x29000cc1, 0x00000020, 0x02198009 }, { 0x00800001, 0x28200229, 0x008d0810, 0x00000000 }, { 0x00800001, 0x29200229, 0x008d0910, 0x00000000 }, { 0x00800001, 0x28000229, 0x008d0800, 0x00000000 }, { 0x00800001, 0x29000229, 0x008d0900, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x00910001, 0x22400231, 0x028d0800, 0x00000000 }, { 0x00910001, 0x23400231, 0x028d0900, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x00910001, 0x22500231, 0x028d0810, 0x00000000 }, { 0x00910001, 0x23500231, 0x028d0910, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x00910001, 0x22600231, 0x028d0820, 0x00000000 }, { 0x00910001, 0x23600231, 0x028d0920, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x00910001, 0x22700231, 0x028d0830, 0x00000000 }, { 0x00910001, 0x23700231, 0x028d0930, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x0a094007 }, { 0x0020000c, 0x21003da5, 0x004500a0, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20260, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x04094008 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20360, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x04094009 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff42 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff3c }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_load_save_rgbx.asm000077500000000000000000000010151231401140700271630ustar00rootroot00000000000000// Module name: NV12_LOAD_SAVE_RGBX .kernel NV12_LOAD_SAVE_RGBX .code #define FIX_POINT_CONVERSION // #define FLOAT_POINT_CONVERSION #include "SetupVPKernel.asm" #include "YUV_to_RGBX_Coef.asm" #include "Multiple_Loop_Head.asm" #include "NV12_Load_8x4.asm" #ifdef FIX_POINT_CONVERSION #include "YUVX_Save_RGBX_Fix.asm" #else #include "YUVX_Save_RGBX_Float.asm" #endif #include "RGB16x8_Save_RGB.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of nv12_load_save_rgbx.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_load_save_rgbx.g4b.gen5000066400000000000000000001153471231401140700277270ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x02000005, 0x20000c24, 0x02000028, 0xff000000 }, { 0x00110001, 0x24400061, 0x02000000, 0x0000012a }, { 0x00110001, 0x24440061, 0x02000000, 0x00000199 }, { 0x00010001, 0x24500061, 0x02000000, 0x0000012a }, { 0x00010001, 0x24540061, 0x02000000, 0x00000199 }, { 0x00000001, 0x24480061, 0x00000000, 0xff9c012a }, { 0x00000001, 0x244c0061, 0x00000000, 0x0000ff30 }, { 0x00110001, 0x24500061, 0x02000000, 0x0204012a }, { 0x00110001, 0x24540061, 0x02000000, 0x00000000 }, { 0x00010001, 0x24400061, 0x02000000, 0x0204012a }, { 0x00010001, 0x24440061, 0x02000000, 0x00000000 }, { 0x8060000c, 0x24403dad, 0x000d0440, 0x00010001 }, { 0x8040000c, 0x24503dad, 0x00090450, 0x00010001 }, { 0x00000001, 0x24580061, 0x00000000, 0x008080f0 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a001 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x02600031, 0x28000c01, 0x408d0000, 0x0228a002 }, { 0x00600001, 0x63000231, 0x000d0770, 0x00000000 }, { 0x00600001, 0x63200231, 0x000d0778, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0830, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0830, 0x00000000 }, { 0x00600001, 0x63010231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x63210231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x63020231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x63220231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x62c00231, 0x000d0760, 0x00000000 }, { 0x00600001, 0x62e00231, 0x000d0768, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0830, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0830, 0x00000000 }, { 0x00600001, 0x62c10231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x62e10231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x62c20231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x62e20231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x62800231, 0x000d0750, 0x00000000 }, { 0x00600001, 0x62a00231, 0x000d0758, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0820, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0820, 0x00000000 }, { 0x00600001, 0x62810231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x62a10231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x62820231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x62a20231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x62400231, 0x000d0740, 0x00000000 }, { 0x00600001, 0x62600231, 0x000d0748, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0820, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0820, 0x00000000 }, { 0x00600001, 0x62410231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x62610231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x62420231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x62620231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x62000231, 0x000d0730, 0x00000000 }, { 0x00600001, 0x62200231, 0x000d0738, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0810, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0810, 0x00000000 }, { 0x00600001, 0x62010231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x62210231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x62020231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x62220231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x61c00231, 0x000d0720, 0x00000000 }, { 0x00600001, 0x61e00231, 0x000d0728, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0810, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0810, 0x00000000 }, { 0x00600001, 0x61c10231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x61e10231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x61c20231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x61e20231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x61800231, 0x000d0710, 0x00000000 }, { 0x00600001, 0x61a00231, 0x000d0718, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0800, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0800, 0x00000000 }, { 0x00600001, 0x61810231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x61a10231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x61820231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x61a20231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x61400231, 0x000d0700, 0x00000000 }, { 0x00600001, 0x61600231, 0x000d0708, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0800, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0800, 0x00000000 }, { 0x00600001, 0x61410231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x61610231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x61420231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x61620231, 0x000e0691, 0x00000000 }, { 0x00800040, 0x2580562d, 0x00110140, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x00110150, 0x00090458 }, { 0x00800040, 0x2600562d, 0x00110160, 0x00090458 }, { 0x00800040, 0x2640562d, 0x00110170, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x61400231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x61600231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x61410231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x61610231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x61420231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x61620231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x00110180, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x00110190, 0x00090458 }, { 0x00800040, 0x2600562d, 0x001101a0, 0x00090458 }, { 0x00800040, 0x2640562d, 0x001101b0, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x61800231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x61a00231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x61810231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x61a10231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x61820231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x61a20231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x001101c0, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x001101d0, 0x00090458 }, { 0x00800040, 0x2600562d, 0x001101e0, 0x00090458 }, { 0x00800040, 0x2640562d, 0x001101f0, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x61c00231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x61e00231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x61c10231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x61e10231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x61c20231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x61e20231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x00110200, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x00110210, 0x00090458 }, { 0x00800040, 0x2600562d, 0x00110220, 0x00090458 }, { 0x00800040, 0x2640562d, 0x00110230, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x62000231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x62200231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x62010231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x62210231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x62020231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x62220231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x00110240, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x00110250, 0x00090458 }, { 0x00800040, 0x2600562d, 0x00110260, 0x00090458 }, { 0x00800040, 0x2640562d, 0x00110270, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x62400231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x62600231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x62410231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x62610231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x62420231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x62620231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x00110280, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x00110290, 0x00090458 }, { 0x00800040, 0x2600562d, 0x001102a0, 0x00090458 }, { 0x00800040, 0x2640562d, 0x001102b0, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x62800231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x62a00231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x62810231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x62a10231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x62820231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x62a20231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x001102c0, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x001102d0, 0x00090458 }, { 0x00800040, 0x2600562d, 0x001102e0, 0x00090458 }, { 0x00800040, 0x2640562d, 0x001102f0, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x62c00231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x62e00231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x62c10231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x62e10231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x62c20231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x62e20231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x00110300, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x00110310, 0x00090458 }, { 0x00800040, 0x2600562d, 0x00110320, 0x00090458 }, { 0x00800040, 0x2640562d, 0x00110330, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x63000231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x63200231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x63010231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x63210231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x63020231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x63220231, 0x000d0468, 0x00000000 }, { 0x00000409, 0x21003da5, 0x000000a0, 0x00020002 }, { 0x00000c01, 0x210401a5, 0x000000a2, 0x00000000 }, { 0x00000801, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000062 }, { 0x00000006, 0x24000c20, 0x000000b8, 0xff00ff00 }, { 0x01000010, 0x20000c04, 0x00000400, 0xffffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000002a }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0288a007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00710001, 0x21400021, 0x028d0700, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00710001, 0x21800021, 0x028d0720, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00710001, 0x21c00021, 0x028d0740, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00710001, 0x22000021, 0x028d0760, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00710001, 0x22400021, 0x028d0780, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00710001, 0x22800021, 0x028d07a0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00710001, 0x22c00021, 0x028d07c0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00710001, 0x23000021, 0x028d07e0, 0x00000000 }, { 0x00000006, 0x24000c20, 0x000000b8, 0xff0000ff }, { 0x01000010, 0x20000c04, 0x00000400, 0xffffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000002c }, { 0x00000040, 0x20201ca6, 0x00000100, 0x00000020 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0288a007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610008, 0x24402d29, 0x000000b8, 0x00080008 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00710001, 0x21600021, 0x028d0700, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00710001, 0x21a00021, 0x028d0720, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00710001, 0x21e00021, 0x028d0740, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00710001, 0x22200021, 0x028d0760, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00710001, 0x22600021, 0x028d0780, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00710001, 0x22a00021, 0x028d07a0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00710001, 0x22e00021, 0x028d07c0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00710001, 0x23200021, 0x028d07e0, 0x00000000 }, { 0x00600001, 0x20400022, 0x008d0140, 0x00000000 }, { 0x00600001, 0x20600022, 0x008d0180, 0x00000000 }, { 0x00600001, 0x20800022, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x20a00022, 0x008d0200, 0x00000000 }, { 0x00600001, 0x20c00022, 0x008d0240, 0x00000000 }, { 0x00600001, 0x20e00022, 0x008d0280, 0x00000000 }, { 0x00600001, 0x21000022, 0x008d02c0, 0x00000000 }, { 0x00600001, 0x21200022, 0x008d0300, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x12082007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000040, 0x20201ca6, 0x00000100, 0x00000020 }, { 0x00600001, 0x20400022, 0x008d0160, 0x00000000 }, { 0x00600001, 0x20600022, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x20800022, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x20a00022, 0x008d0220, 0x00000000 }, { 0x00600001, 0x20c00022, 0x008d0260, 0x00000000 }, { 0x00600001, 0x20e00022, 0x008d02a0, 0x00000000 }, { 0x00600001, 0x21000022, 0x008d02e0, 0x00000000 }, { 0x00600001, 0x21200022, 0x008d0320, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x12082007 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xfffffa96 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffa90 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_load_save_rgbx.g6b000066400000000000000000001252261231401140700270710ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x02000005, 0x20000c24, 0x02000028, 0xff000000 }, { 0x00110001, 0x24400061, 0x02000000, 0x0000012a }, { 0x00110001, 0x24440061, 0x02000000, 0x00000199 }, { 0x00010001, 0x24500061, 0x02000000, 0x0000012a }, { 0x00010001, 0x24540061, 0x02000000, 0x00000199 }, { 0x00000001, 0x24480061, 0x00000000, 0xff9c012a }, { 0x00000001, 0x244c0061, 0x00000000, 0x0000ff30 }, { 0x00110001, 0x24500061, 0x02000000, 0x0204012a }, { 0x00110001, 0x24540061, 0x02000000, 0x00000000 }, { 0x00010001, 0x24400061, 0x02000000, 0x0204012a }, { 0x00010001, 0x24440061, 0x02000000, 0x00000000 }, { 0x8060000c, 0x24403dad, 0x000d0440, 0x00010001 }, { 0x8040000c, 0x24503dad, 0x00090450, 0x00010001 }, { 0x00000001, 0x24580061, 0x00000000, 0x008080f0 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498001 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000040, 0x02298002 }, { 0x00600001, 0x63000231, 0x000d0770, 0x00000000 }, { 0x00600001, 0x63200231, 0x000d0778, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0830, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0830, 0x00000000 }, { 0x00600001, 0x63010231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x63210231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x63020231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x63220231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x62c00231, 0x000d0760, 0x00000000 }, { 0x00600001, 0x62e00231, 0x000d0768, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0830, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0830, 0x00000000 }, { 0x00600001, 0x62c10231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x62e10231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x62c20231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x62e20231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x62800231, 0x000d0750, 0x00000000 }, { 0x00600001, 0x62a00231, 0x000d0758, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0820, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0820, 0x00000000 }, { 0x00600001, 0x62810231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x62a10231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x62820231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x62a20231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x62400231, 0x000d0740, 0x00000000 }, { 0x00600001, 0x62600231, 0x000d0748, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0820, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0820, 0x00000000 }, { 0x00600001, 0x62410231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x62610231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x62420231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x62620231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x62000231, 0x000d0730, 0x00000000 }, { 0x00600001, 0x62200231, 0x000d0738, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0810, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0810, 0x00000000 }, { 0x00600001, 0x62010231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x62210231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x62020231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x62220231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x61c00231, 0x000d0720, 0x00000000 }, { 0x00600001, 0x61e00231, 0x000d0728, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0810, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0810, 0x00000000 }, { 0x00600001, 0x61c10231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x61e10231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x61c20231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x61e20231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x61800231, 0x000d0710, 0x00000000 }, { 0x00600001, 0x61a00231, 0x000d0718, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0800, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0800, 0x00000000 }, { 0x00600001, 0x61810231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x61a10231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x61820231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x61a20231, 0x000e0691, 0x00000000 }, { 0x00600001, 0x61400231, 0x000d0700, 0x00000000 }, { 0x00600001, 0x61600231, 0x000d0708, 0x00000000 }, { 0x00600001, 0x46800129, 0x000d0800, 0x00000000 }, { 0x00600001, 0x46820129, 0x000d0800, 0x00000000 }, { 0x00600001, 0x61410231, 0x000e0680, 0x00000000 }, { 0x00600001, 0x61610231, 0x000e0690, 0x00000000 }, { 0x00600001, 0x61420231, 0x000e0681, 0x00000000 }, { 0x00600001, 0x61620231, 0x000e0691, 0x00000000 }, { 0x00800040, 0x2580562d, 0x00110140, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x00110150, 0x00090458 }, { 0x00800040, 0x2600562d, 0x00110160, 0x00090458 }, { 0x00800040, 0x2640562d, 0x00110170, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x61400231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x61600231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x61410231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x61610231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x61420231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x61620231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x00110180, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x00110190, 0x00090458 }, { 0x00800040, 0x2600562d, 0x001101a0, 0x00090458 }, { 0x00800040, 0x2640562d, 0x001101b0, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x61800231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x61a00231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x61810231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x61a10231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x61820231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x61a20231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x001101c0, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x001101d0, 0x00090458 }, { 0x00800040, 0x2600562d, 0x001101e0, 0x00090458 }, { 0x00800040, 0x2640562d, 0x001101f0, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x61c00231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x61e00231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x61c10231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x61e10231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x61c20231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x61e20231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x00110200, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x00110210, 0x00090458 }, { 0x00800040, 0x2600562d, 0x00110220, 0x00090458 }, { 0x00800040, 0x2640562d, 0x00110230, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x62000231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x62200231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x62010231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x62210231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x62020231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x62220231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x00110240, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x00110250, 0x00090458 }, { 0x00800040, 0x2600562d, 0x00110260, 0x00090458 }, { 0x00800040, 0x2640562d, 0x00110270, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x62400231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x62600231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x62410231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x62610231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x62420231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x62620231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x00110280, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x00110290, 0x00090458 }, { 0x00800040, 0x2600562d, 0x001102a0, 0x00090458 }, { 0x00800040, 0x2640562d, 0x001102b0, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x62800231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x62a00231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x62810231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x62a10231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x62820231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x62a20231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x001102c0, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x001102d0, 0x00090458 }, { 0x00800040, 0x2600562d, 0x001102e0, 0x00090458 }, { 0x00800040, 0x2640562d, 0x001102f0, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x62c00231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x62e00231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x62c10231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x62e10231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x62c20231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x62e20231, 0x000d0468, 0x00000000 }, { 0x00800040, 0x2580562d, 0x00110300, 0x00090458 }, { 0x00800040, 0x25c0562d, 0x00110310, 0x00090458 }, { 0x00800040, 0x2600562d, 0x00110320, 0x00090458 }, { 0x00800040, 0x2640562d, 0x00110330, 0x00090458 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090440 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090440 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090440 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090440 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24600231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090448 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090448 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090448 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090448 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24800231, 0x00120541, 0x00000000 }, { 0x80800041, 0x24c035ad, 0x00110580, 0x00090450 }, { 0x80800041, 0x24e035ad, 0x001105c0, 0x00090450 }, { 0x80800041, 0x250035ad, 0x00110600, 0x00090450 }, { 0x80800041, 0x252035ad, 0x00110640, 0x00090450 }, { 0x80400040, 0x64c035a9, 0x000b04c0, 0x000b04c2 }, { 0x80400040, 0x64e035a9, 0x000b04e0, 0x000b04e2 }, { 0x80400040, 0x650035a9, 0x000b0500, 0x000b0502 }, { 0x80400040, 0x652035a9, 0x000b0520, 0x000b0522 }, { 0x80400040, 0x64c03529, 0x000b04c0, 0x000b04c4 }, { 0x80400040, 0x64e03529, 0x000b04e0, 0x000b04e4 }, { 0x80400040, 0x65003529, 0x000b0500, 0x000b0504 }, { 0x80400040, 0x65203529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x80800040, 0x25402d29, 0x00110540, 0x00800080 }, { 0x80800009, 0x25403d29, 0x00110540, 0x00010001 }, { 0x00800001, 0x24a00231, 0x00120541, 0x00000000 }, { 0x00600001, 0x63000231, 0x000d04a0, 0x00000000 }, { 0x00600001, 0x63200231, 0x000d04a8, 0x00000000 }, { 0x00600001, 0x63010231, 0x000d0480, 0x00000000 }, { 0x00600001, 0x63210231, 0x000d0488, 0x00000000 }, { 0x00600001, 0x63020231, 0x000d0460, 0x00000000 }, { 0x00600001, 0x63220231, 0x000d0468, 0x00000000 }, { 0x00000409, 0x21003da5, 0x000000a0, 0x00020002 }, { 0x00000c01, 0x210401a5, 0x000000a2, 0x00000000 }, { 0x00000801, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000062 }, { 0x00000006, 0x24000c20, 0x000000b8, 0xff00ff00 }, { 0x01000010, 0x20000c04, 0x00000400, 0xffffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000002a }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02898007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00710001, 0x21400021, 0x028d0700, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00710001, 0x21800021, 0x028d0720, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00710001, 0x21c00021, 0x028d0740, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00710001, 0x22000021, 0x028d0760, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00710001, 0x22400021, 0x028d0780, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00710001, 0x22800021, 0x028d07a0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00710001, 0x22c00021, 0x028d07c0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00710001, 0x23000021, 0x028d07e0, 0x00000000 }, { 0x00000006, 0x24000c20, 0x000000b8, 0xff0000ff }, { 0x01000010, 0x20000c04, 0x00000400, 0xffffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000002c }, { 0x00000040, 0x20201ca6, 0x00000100, 0x00000020 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02898007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610008, 0x24402d29, 0x000000b8, 0x00080008 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00710001, 0x21600021, 0x028d0700, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00710001, 0x21a00021, 0x028d0720, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00710001, 0x21e00021, 0x028d0740, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00710001, 0x22200021, 0x028d0760, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00710001, 0x22600021, 0x028d0780, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00710001, 0x22a00021, 0x028d07a0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00710001, 0x22e00021, 0x028d07c0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00710001, 0x23200021, 0x028d07e0, 0x00000000 }, { 0x00600001, 0x20400022, 0x008d0140, 0x00000000 }, { 0x00600001, 0x20600022, 0x008d0180, 0x00000000 }, { 0x00600001, 0x20800022, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x20a00022, 0x008d0200, 0x00000000 }, { 0x00600001, 0x20c00022, 0x008d0240, 0x00000000 }, { 0x00600001, 0x20e00022, 0x008d0280, 0x00000000 }, { 0x00600001, 0x21000022, 0x008d02c0, 0x00000000 }, { 0x00600001, 0x21200022, 0x008d0300, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x12094007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000040, 0x20201ca6, 0x00000100, 0x00000020 }, { 0x00600001, 0x20400022, 0x008d0160, 0x00000000 }, { 0x00600001, 0x20600022, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x20800022, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x20a00022, 0x008d0220, 0x00000000 }, { 0x00600001, 0x20c00022, 0x008d0260, 0x00000000 }, { 0x00600001, 0x20e00022, 0x008d02a0, 0x00000000 }, { 0x00600001, 0x21000022, 0x008d02e0, 0x00000000 }, { 0x00600001, 0x21200022, 0x008d0320, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x12094007 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xfffffa96 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffa90 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_scaling_nv12.asm000066400000000000000000000005631231401140700264760ustar00rootroot00000000000000// Module name: NV12_SCALING_NV12 .kernel NV12_SCALING_NV12 .code #define INC_SCALING #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #include "PL2_Scaling.asm" #include "PL16x8_PL8x4.asm" #include "PL8x4_Save_NV12.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of nv12_scaling_nv12.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5000066400000000000000000000302161231401140700272250ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00400001, 0x254002fd, 0x00000000, 0x48403000 }, { 0x00400001, 0x255002fd, 0x00000000, 0x5c585450 }, { 0x00600040, 0x25607fbd, 0x008d0540, 0x41000000 }, { 0x00200401, 0x21000061, 0x00000000, 0x00000000 }, { 0x00000801, 0x21080061, 0x00000000, 0x00000000 }, { 0x00802001, 0x208003be, 0x000000a8, 0x00000000 }, { 0x00802001, 0x258003bd, 0x000000a8, 0x00000000 }, { 0x00802001, 0x240003bc, 0x000000a4, 0x00000000 }, { 0x00802048, 0x204077be, 0x000000bc, 0x008d0540 }, { 0x00000401, 0x257003fd, 0x00000000, 0x437f0000 }, { 0x00000801, 0x257c03fd, 0x00000000, 0x3f000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01800031, 0x27001c09, 0x208d0000, 0x0a8a0101 }, { 0x01800031, 0x28001c09, 0x208d0000, 0x0a8a0202 }, { 0x00802040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00802040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00802001, 0x27000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00802001, 0x28000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00802001, 0x28400381, 0x00b10400, 0x00000000 }, { 0x00800001, 0x21400229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x22400229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x23400229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01800031, 0x27001c09, 0x208d0000, 0x0a8a0101 }, { 0x01800031, 0x28001c09, 0x208d0000, 0x0a8a0202 }, { 0x00802040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00802040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00802001, 0x27000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00802001, 0x28000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00802001, 0x28400381, 0x00b10400, 0x00000000 }, { 0x00800001, 0x21600229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x22600229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x23600229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01800031, 0x27001c09, 0x208d0000, 0x0a8a0101 }, { 0x01800031, 0x28001c09, 0x208d0000, 0x0a8a0202 }, { 0x00802040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00802040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00802001, 0x27000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00802001, 0x28000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00802001, 0x28400381, 0x00b10400, 0x00000000 }, { 0x00800001, 0x21800229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x22800229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x23800229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01800031, 0x27001c09, 0x208d0000, 0x0a8a0101 }, { 0x01800031, 0x28001c09, 0x208d0000, 0x0a8a0202 }, { 0x00802040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00802040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00802001, 0x27000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00802001, 0x28000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00802001, 0x28400381, 0x00b10400, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x22a00229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x23a00229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01800031, 0x27001c09, 0x208d0000, 0x0a8a0101 }, { 0x01800031, 0x28001c09, 0x208d0000, 0x0a8a0202 }, { 0x00802040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00802040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00802001, 0x27000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00802001, 0x28000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00802001, 0x28400381, 0x00b10400, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x22c00229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x23c00229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01800031, 0x27001c09, 0x208d0000, 0x0a8a0101 }, { 0x01800031, 0x28001c09, 0x208d0000, 0x0a8a0202 }, { 0x00802040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00802040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00802001, 0x27000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00802001, 0x28000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00802001, 0x28400381, 0x00b10400, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x22e00229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x23e00229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01800031, 0x27001c09, 0x208d0000, 0x0a8a0101 }, { 0x01800031, 0x28001c09, 0x208d0000, 0x0a8a0202 }, { 0x00802040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00802040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00802001, 0x27000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00802001, 0x28000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00802001, 0x28400381, 0x00b10400, 0x00000000 }, { 0x00800001, 0x22000229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x23000229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x24000229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01800031, 0x27001c09, 0x208d0000, 0x0a8a0101 }, { 0x01800031, 0x28001c09, 0x208d0000, 0x0a8a0202 }, { 0x00802040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00802040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00802001, 0x27000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00802001, 0x28000381, 0x00b10400, 0x00000000 }, { 0x00802059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00802001, 0x28400381, 0x00b10400, 0x00000000 }, { 0x00800001, 0x22200229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x23200229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x24200229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x22400129, 0x00ae0240, 0x00000000 }, { 0x00600001, 0x23400129, 0x00ae0340, 0x00000000 }, { 0x00600001, 0x22500129, 0x00ae0280, 0x00000000 }, { 0x00600001, 0x23500129, 0x00ae0380, 0x00000000 }, { 0x00600001, 0x22600129, 0x00ae02c0, 0x00000000 }, { 0x00600001, 0x23600129, 0x00ae03c0, 0x00000000 }, { 0x00600001, 0x22700129, 0x00ae0300, 0x00000000 }, { 0x00600001, 0x23700129, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x28000c01, 0x408d0000, 0x0228a008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x0a082007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x06082008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00000041, 0x24407fbd, 0x000000bc, 0x41800000 }, { 0x00000040, 0x20a477bd, 0x00000440, 0x000000a4 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xfffffe5e }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000001, 0x20a403bd, 0x00000094, 0x00000000 }, { 0x00000041, 0x24407fbd, 0x00000038, 0x41000000 }, { 0x00000040, 0x20a877bd, 0x00000440, 0x000000a8 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffe52 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/nv12_scaling_nv12.g6b000066400000000000000000000400751231401140700263760ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00400001, 0x254002fd, 0x00000000, 0x48403000 }, { 0x00400001, 0x255002fd, 0x00000000, 0x5c585450 }, { 0x00600040, 0x25607fbd, 0x008d0540, 0x41000000 }, { 0x00200401, 0x21000061, 0x00000000, 0x00000000 }, { 0x00000801, 0x21080061, 0x00000000, 0x00000000 }, { 0x00800001, 0x208003be, 0x000000a8, 0x00000000 }, { 0x00800001, 0x258003bd, 0x000000a8, 0x00000000 }, { 0x00800001, 0x240003bc, 0x000000a4, 0x00000000 }, { 0x00800048, 0x204077be, 0x000000bc, 0x008d0540 }, { 0x00000401, 0x257003fd, 0x00000000, 0x437f0000 }, { 0x00000801, 0x257c03fd, 0x00000000, 0x3f000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x02800031, 0x27001cc9, 0x00000020, 0x0a8a0101 }, { 0x02800031, 0x28001cc9, 0x00000020, 0x0a8a0202 }, { 0x00800040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00800040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00800001, 0x27000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00800001, 0x28000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00800001, 0x28400381, 0x008d0400, 0x00000000 }, { 0x00800001, 0x21400229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x22400229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x23400229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x02800031, 0x27001cc9, 0x00000020, 0x0a8a0101 }, { 0x02800031, 0x28001cc9, 0x00000020, 0x0a8a0202 }, { 0x00800040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00800040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00800001, 0x27000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00800001, 0x28000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00800001, 0x28400381, 0x008d0400, 0x00000000 }, { 0x00800001, 0x21600229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x22600229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x23600229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x02800031, 0x27001cc9, 0x00000020, 0x0a8a0101 }, { 0x02800031, 0x28001cc9, 0x00000020, 0x0a8a0202 }, { 0x00800040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00800040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00800001, 0x27000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00800001, 0x28000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00800001, 0x28400381, 0x008d0400, 0x00000000 }, { 0x00800001, 0x21800229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x22800229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x23800229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x02800031, 0x27001cc9, 0x00000020, 0x0a8a0101 }, { 0x02800031, 0x28001cc9, 0x00000020, 0x0a8a0202 }, { 0x00800040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00800040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00800001, 0x27000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00800001, 0x28000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00800001, 0x28400381, 0x008d0400, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x22a00229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x23a00229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x02800031, 0x27001cc9, 0x00000020, 0x0a8a0101 }, { 0x02800031, 0x28001cc9, 0x00000020, 0x0a8a0202 }, { 0x00800040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00800040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00800001, 0x27000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00800001, 0x28000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00800001, 0x28400381, 0x008d0400, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x22c00229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x23c00229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x02800031, 0x27001cc9, 0x00000020, 0x0a8a0101 }, { 0x02800031, 0x28001cc9, 0x00000020, 0x0a8a0202 }, { 0x00800040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00800040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00800001, 0x27000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00800001, 0x28000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00800001, 0x28400381, 0x008d0400, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x22e00229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x23e00229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x02800031, 0x27001cc9, 0x00000020, 0x0a8a0101 }, { 0x02800031, 0x28001cc9, 0x00000020, 0x0a8a0202 }, { 0x00800040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00800040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00800001, 0x27000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00800001, 0x28000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00800001, 0x28400381, 0x008d0400, 0x00000000 }, { 0x00800001, 0x22000229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x23000229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x24000229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x02800031, 0x27001cc9, 0x00000020, 0x0a8a0101 }, { 0x02800031, 0x28001cc9, 0x00000020, 0x0a8a0202 }, { 0x00800040, 0x208077be, 0x008d0580, 0x00000038 }, { 0x00800040, 0x258077bd, 0x008d0580, 0x00000038 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0700 }, { 0x00800001, 0x27000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0800 }, { 0x00800001, 0x28000381, 0x008d0400, 0x00000000 }, { 0x00800059, 0x240077bc, 0x00000570, 0x008d0840 }, { 0x00800001, 0x28400381, 0x008d0400, 0x00000000 }, { 0x00800001, 0x22200229, 0x00cf0700, 0x00000000 }, { 0x00800001, 0x23200229, 0x00cf0800, 0x00000000 }, { 0x00800001, 0x24200229, 0x00cf0840, 0x00000000 }, { 0x00600001, 0x22400129, 0x00ae0240, 0x00000000 }, { 0x00600001, 0x23400129, 0x00ae0340, 0x00000000 }, { 0x00600001, 0x22500129, 0x00ae0280, 0x00000000 }, { 0x00600001, 0x23500129, 0x00ae0380, 0x00000000 }, { 0x00600001, 0x22600129, 0x00ae02c0, 0x00000000 }, { 0x00600001, 0x23600129, 0x00ae03c0, 0x00000000 }, { 0x00600001, 0x22700129, 0x00ae0300, 0x00000000 }, { 0x00600001, 0x23700129, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000020, 0x02298008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x0a094007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x06094008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00000041, 0x24407fbd, 0x000000bc, 0x41800000 }, { 0x00000040, 0x20a477bd, 0x00000440, 0x000000a4 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xfffffe5e }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000001, 0x20a403bd, 0x00000094, 0x00000000 }, { 0x00000041, 0x24407fbd, 0x00000038, 0x41000000 }, { 0x00000040, 0x20a877bd, 0x00000440, 0x000000a8 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffe52 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pa_load_save_nv12.asm000077500000000000000000000005271231401140700266300ustar00rootroot00000000000000// Module name: PA_LOAD_SAVE_NV12 .kernel PA_LOAD_SAVE_NV12 .code #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #include "PA_Load_8x8.asm" #include "PL8x8_PL8x4.asm" #include "PL8x4_Save_NV12.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of nv12_load_save_pl1.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5000066400000000000000000000152441231401140700273600ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000009, 0x21003da5, 0x00000100, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0288a001 }, { 0x00400040, 0x22083e28, 0x00690024, 0x07000700 }, { 0x00800001, 0x21400229, 0x00d29000, 0x00000000 }, { 0x00600001, 0x22400229, 0x00cf9400, 0x00000000 }, { 0x00600001, 0x23400229, 0x00cf9800, 0x00000000 }, { 0x00800001, 0x21600229, 0x00d29020, 0x00000000 }, { 0x00600001, 0x22500229, 0x00cf9420, 0x00000000 }, { 0x00600001, 0x23500229, 0x00cf9820, 0x00000000 }, { 0x00800001, 0x21800229, 0x00d29040, 0x00000000 }, { 0x00600001, 0x22600229, 0x00cf9440, 0x00000000 }, { 0x00600001, 0x23600229, 0x00cf9840, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00d29060, 0x00000000 }, { 0x00600001, 0x22700229, 0x00cf9460, 0x00000000 }, { 0x00600001, 0x23700229, 0x00cf9860, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00d29080, 0x00000000 }, { 0x00600001, 0x22800229, 0x00cf9480, 0x00000000 }, { 0x00600001, 0x23800229, 0x00cf9880, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00d290a0, 0x00000000 }, { 0x00600001, 0x22900229, 0x00cf94a0, 0x00000000 }, { 0x00600001, 0x23900229, 0x00cf98a0, 0x00000000 }, { 0x00800001, 0x22000229, 0x00d290c0, 0x00000000 }, { 0x00600001, 0x22a00229, 0x00cf94c0, 0x00000000 }, { 0x00600001, 0x23a00229, 0x00cf98c0, 0x00000000 }, { 0x00800001, 0x22200229, 0x00d290e0, 0x00000000 }, { 0x00600001, 0x22b00229, 0x00cf94e0, 0x00000000 }, { 0x00600001, 0x23b00229, 0x00cf98e0, 0x00000000 }, { 0x00600001, 0x42500231, 0x00ae0260, 0x00000000 }, { 0x00800001, 0x42600231, 0x00ce0280, 0x00000000 }, { 0x00600001, 0x43500231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0x43600231, 0x00ce0380, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x28000c01, 0x408d0000, 0x0228a008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x0a082007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x06082008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff24 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff1e }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b000066400000000000000000000251231231401140700265220ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000009, 0x21003da5, 0x00000100, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02898001 }, { 0x00400040, 0x22083e28, 0x00690024, 0x07000700 }, { 0x00800001, 0x21400229, 0x00d29000, 0x00000000 }, { 0x00600001, 0x22400229, 0x00cf9400, 0x00000000 }, { 0x00600001, 0x23400229, 0x00cf9800, 0x00000000 }, { 0x00800001, 0x21600229, 0x00d29020, 0x00000000 }, { 0x00600001, 0x22500229, 0x00cf9420, 0x00000000 }, { 0x00600001, 0x23500229, 0x00cf9820, 0x00000000 }, { 0x00800001, 0x21800229, 0x00d29040, 0x00000000 }, { 0x00600001, 0x22600229, 0x00cf9440, 0x00000000 }, { 0x00600001, 0x23600229, 0x00cf9840, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00d29060, 0x00000000 }, { 0x00600001, 0x22700229, 0x00cf9460, 0x00000000 }, { 0x00600001, 0x23700229, 0x00cf9860, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00d29080, 0x00000000 }, { 0x00600001, 0x22800229, 0x00cf9480, 0x00000000 }, { 0x00600001, 0x23800229, 0x00cf9880, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00d290a0, 0x00000000 }, { 0x00600001, 0x22900229, 0x00cf94a0, 0x00000000 }, { 0x00600001, 0x23900229, 0x00cf98a0, 0x00000000 }, { 0x00800001, 0x22000229, 0x00d290c0, 0x00000000 }, { 0x00600001, 0x22a00229, 0x00cf94c0, 0x00000000 }, { 0x00600001, 0x23a00229, 0x00cf98c0, 0x00000000 }, { 0x00800001, 0x22200229, 0x00d290e0, 0x00000000 }, { 0x00600001, 0x22b00229, 0x00cf94e0, 0x00000000 }, { 0x00600001, 0x23b00229, 0x00cf98e0, 0x00000000 }, { 0x00600001, 0x42500231, 0x00ae0260, 0x00000000 }, { 0x00800001, 0x42600231, 0x00ce0280, 0x00000000 }, { 0x00600001, 0x43500231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0x43600231, 0x00ce0380, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000020, 0x02298008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x0a094007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x06094008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff24 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff1e }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pa_load_save_pa.asm000066400000000000000000000004501231401140700264320ustar00rootroot00000000000000// Module name: PA_LOAD_SAVE_PA .kernel PA_LOAD_SAVE_PA .code #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #include "PA_Load_8x8.asm" #include "PL8x8_Save_PA.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of pa_load_save_pa.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pa_load_save_pa.g4b.gen5000066400000000000000000000142651231401140700271740ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000009, 0x21003da5, 0x00000100, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0288a001 }, { 0x00400040, 0x22083e28, 0x00690024, 0x07000700 }, { 0x00800001, 0x21400229, 0x00d29000, 0x00000000 }, { 0x00600001, 0x22400229, 0x00cf9400, 0x00000000 }, { 0x00600001, 0x23400229, 0x00cf9800, 0x00000000 }, { 0x00800001, 0x21600229, 0x00d29020, 0x00000000 }, { 0x00600001, 0x22500229, 0x00cf9420, 0x00000000 }, { 0x00600001, 0x23500229, 0x00cf9820, 0x00000000 }, { 0x00800001, 0x21800229, 0x00d29040, 0x00000000 }, { 0x00600001, 0x22600229, 0x00cf9440, 0x00000000 }, { 0x00600001, 0x23600229, 0x00cf9840, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00d29060, 0x00000000 }, { 0x00600001, 0x22700229, 0x00cf9460, 0x00000000 }, { 0x00600001, 0x23700229, 0x00cf9860, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00d29080, 0x00000000 }, { 0x00600001, 0x22800229, 0x00cf9480, 0x00000000 }, { 0x00600001, 0x23800229, 0x00cf9880, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00d290a0, 0x00000000 }, { 0x00600001, 0x22900229, 0x00cf94a0, 0x00000000 }, { 0x00600001, 0x23900229, 0x00cf98a0, 0x00000000 }, { 0x00800001, 0x22000229, 0x00d290c0, 0x00000000 }, { 0x00600001, 0x22a00229, 0x00cf94c0, 0x00000000 }, { 0x00600001, 0x23a00229, 0x00cf98c0, 0x00000000 }, { 0x00800001, 0x22200229, 0x00d290e0, 0x00000000 }, { 0x00600001, 0x22b00229, 0x00cf94e0, 0x00000000 }, { 0x00600001, 0x23b00229, 0x00cf98e0, 0x00000000 }, { 0x00400040, 0x22083e28, 0x00690028, 0x07000700 }, { 0x00800001, 0xd0000231, 0x00d20140, 0x00000000 }, { 0x00800001, 0xd0200231, 0x00d20160, 0x00000000 }, { 0x00800001, 0xd0400231, 0x00d20180, 0x00000000 }, { 0x00800001, 0xd0600231, 0x00d201a0, 0x00000000 }, { 0x00800001, 0xd0800231, 0x00d201c0, 0x00000000 }, { 0x00800001, 0xd0a00231, 0x00d201e0, 0x00000000 }, { 0x00800001, 0xd0c00231, 0x00d20200, 0x00000000 }, { 0x00800001, 0xd0e00231, 0x00d20220, 0x00000000 }, { 0x00600001, 0xf4000231, 0x00ae0240, 0x00000000 }, { 0x00600001, 0xf8000231, 0x00ae0340, 0x00000000 }, { 0x00600001, 0xf4200231, 0x00ae0250, 0x00000000 }, { 0x00600001, 0xf8200231, 0x00ae0350, 0x00000000 }, { 0x00600001, 0xf4400231, 0x00ae0260, 0x00000000 }, { 0x00600001, 0xf8400231, 0x00ae0360, 0x00000000 }, { 0x00600001, 0xf4600231, 0x00ae0270, 0x00000000 }, { 0x00600001, 0xf8600231, 0x00ae0370, 0x00000000 }, { 0x00600001, 0xf4800231, 0x00ae0280, 0x00000000 }, { 0x00600001, 0xf8800231, 0x00ae0380, 0x00000000 }, { 0x00600001, 0xf4a00231, 0x00ae0290, 0x00000000 }, { 0x00600001, 0xf8a00231, 0x00ae0390, 0x00000000 }, { 0x00600001, 0xf4c00231, 0x00ae02a0, 0x00000000 }, { 0x00600001, 0xf8c00231, 0x00ae03a0, 0x00000000 }, { 0x00600001, 0xf4e00231, 0x00ae02b0, 0x00000000 }, { 0x00600001, 0xf8e00231, 0x00ae03b0, 0x00000000 }, { 0x00000409, 0x21003da5, 0x000000a0, 0x00010001 }, { 0x00000c01, 0x210401a5, 0x000000a2, 0x00000000 }, { 0x00000801, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000002a }, { 0x01600031, 0x21400c01, 0x408d0000, 0x0288a007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x27000129, 0x02b10140, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x27200129, 0x02b10160, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x27400129, 0x02b10180, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x27600129, 0x02b101a0, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x27800129, 0x02b101c0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x27a00129, 0x02b101e0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x27c00129, 0x02b10200, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x27e00129, 0x02b10220, 0x00000000 }, { 0x00600001, 0x20400022, 0x008d0700, 0x00000000 }, { 0x00600001, 0x20600022, 0x008d0720, 0x00000000 }, { 0x00600001, 0x20800022, 0x008d0740, 0x00000000 }, { 0x00600001, 0x20a00022, 0x008d0760, 0x00000000 }, { 0x00600001, 0x20c00022, 0x008d0780, 0x00000000 }, { 0x00600001, 0x20e00022, 0x008d07a0, 0x00000000 }, { 0x00600001, 0x21000022, 0x008d07c0, 0x00000000 }, { 0x00600001, 0x21200022, 0x008d07e0, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x12082007 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff36 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff30 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pa_load_save_pa.g6b000066400000000000000000000241441231401140700263360ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000009, 0x21003da5, 0x00000100, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02898001 }, { 0x00400040, 0x22083e28, 0x00690024, 0x07000700 }, { 0x00800001, 0x21400229, 0x00d29000, 0x00000000 }, { 0x00600001, 0x22400229, 0x00cf9400, 0x00000000 }, { 0x00600001, 0x23400229, 0x00cf9800, 0x00000000 }, { 0x00800001, 0x21600229, 0x00d29020, 0x00000000 }, { 0x00600001, 0x22500229, 0x00cf9420, 0x00000000 }, { 0x00600001, 0x23500229, 0x00cf9820, 0x00000000 }, { 0x00800001, 0x21800229, 0x00d29040, 0x00000000 }, { 0x00600001, 0x22600229, 0x00cf9440, 0x00000000 }, { 0x00600001, 0x23600229, 0x00cf9840, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00d29060, 0x00000000 }, { 0x00600001, 0x22700229, 0x00cf9460, 0x00000000 }, { 0x00600001, 0x23700229, 0x00cf9860, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00d29080, 0x00000000 }, { 0x00600001, 0x22800229, 0x00cf9480, 0x00000000 }, { 0x00600001, 0x23800229, 0x00cf9880, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00d290a0, 0x00000000 }, { 0x00600001, 0x22900229, 0x00cf94a0, 0x00000000 }, { 0x00600001, 0x23900229, 0x00cf98a0, 0x00000000 }, { 0x00800001, 0x22000229, 0x00d290c0, 0x00000000 }, { 0x00600001, 0x22a00229, 0x00cf94c0, 0x00000000 }, { 0x00600001, 0x23a00229, 0x00cf98c0, 0x00000000 }, { 0x00800001, 0x22200229, 0x00d290e0, 0x00000000 }, { 0x00600001, 0x22b00229, 0x00cf94e0, 0x00000000 }, { 0x00600001, 0x23b00229, 0x00cf98e0, 0x00000000 }, { 0x00400040, 0x22083e28, 0x00690028, 0x07000700 }, { 0x00800001, 0xd0000231, 0x00d20140, 0x00000000 }, { 0x00800001, 0xd0200231, 0x00d20160, 0x00000000 }, { 0x00800001, 0xd0400231, 0x00d20180, 0x00000000 }, { 0x00800001, 0xd0600231, 0x00d201a0, 0x00000000 }, { 0x00800001, 0xd0800231, 0x00d201c0, 0x00000000 }, { 0x00800001, 0xd0a00231, 0x00d201e0, 0x00000000 }, { 0x00800001, 0xd0c00231, 0x00d20200, 0x00000000 }, { 0x00800001, 0xd0e00231, 0x00d20220, 0x00000000 }, { 0x00600001, 0xf4000231, 0x00ae0240, 0x00000000 }, { 0x00600001, 0xf8000231, 0x00ae0340, 0x00000000 }, { 0x00600001, 0xf4200231, 0x00ae0250, 0x00000000 }, { 0x00600001, 0xf8200231, 0x00ae0350, 0x00000000 }, { 0x00600001, 0xf4400231, 0x00ae0260, 0x00000000 }, { 0x00600001, 0xf8400231, 0x00ae0360, 0x00000000 }, { 0x00600001, 0xf4600231, 0x00ae0270, 0x00000000 }, { 0x00600001, 0xf8600231, 0x00ae0370, 0x00000000 }, { 0x00600001, 0xf4800231, 0x00ae0280, 0x00000000 }, { 0x00600001, 0xf8800231, 0x00ae0380, 0x00000000 }, { 0x00600001, 0xf4a00231, 0x00ae0290, 0x00000000 }, { 0x00600001, 0xf8a00231, 0x00ae0390, 0x00000000 }, { 0x00600001, 0xf4c00231, 0x00ae02a0, 0x00000000 }, { 0x00600001, 0xf8c00231, 0x00ae03a0, 0x00000000 }, { 0x00600001, 0xf4e00231, 0x00ae02b0, 0x00000000 }, { 0x00600001, 0xf8e00231, 0x00ae03b0, 0x00000000 }, { 0x00000409, 0x21003da5, 0x000000a0, 0x00010001 }, { 0x00000c01, 0x210401a5, 0x000000a2, 0x00000000 }, { 0x00000801, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000002a }, { 0x04600031, 0x21400cc1, 0x00000020, 0x02898007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x27000129, 0x02b10140, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x27200129, 0x02b10160, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x27400129, 0x02b10180, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x27600129, 0x02b101a0, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x27800129, 0x02b101c0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x27a00129, 0x02b101e0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x27c00129, 0x02b10200, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x27e00129, 0x02b10220, 0x00000000 }, { 0x00600001, 0x20400022, 0x008d0700, 0x00000000 }, { 0x00600001, 0x20600022, 0x008d0720, 0x00000000 }, { 0x00600001, 0x20800022, 0x008d0740, 0x00000000 }, { 0x00600001, 0x20a00022, 0x008d0760, 0x00000000 }, { 0x00600001, 0x20c00022, 0x008d0780, 0x00000000 }, { 0x00600001, 0x20e00022, 0x008d07a0, 0x00000000 }, { 0x00600001, 0x21000022, 0x008d07c0, 0x00000000 }, { 0x00600001, 0x21200022, 0x008d07e0, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x12094007 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff36 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff30 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pa_load_save_pl3.asm000077500000000000000000000005231231401140700265340ustar00rootroot00000000000000// Module name: PA_LOAD_SAVE_PL3 .kernel PA_LOAD_SAVE_PL3 .code #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #include "PA_Load_8x8.asm" #include "PL8x8_PL8x4.asm" #include "PL8x4_Save_IMC3.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of pa_load_save_pl3.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5000077500000000000000000000155111231401140700272700ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000009, 0x21003da5, 0x00000100, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0288a001 }, { 0x00400040, 0x22083e28, 0x00690024, 0x07000700 }, { 0x00800001, 0x21400229, 0x00d29000, 0x00000000 }, { 0x00600001, 0x22400229, 0x00cf9400, 0x00000000 }, { 0x00600001, 0x23400229, 0x00cf9800, 0x00000000 }, { 0x00800001, 0x21600229, 0x00d29020, 0x00000000 }, { 0x00600001, 0x22500229, 0x00cf9420, 0x00000000 }, { 0x00600001, 0x23500229, 0x00cf9820, 0x00000000 }, { 0x00800001, 0x21800229, 0x00d29040, 0x00000000 }, { 0x00600001, 0x22600229, 0x00cf9440, 0x00000000 }, { 0x00600001, 0x23600229, 0x00cf9840, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00d29060, 0x00000000 }, { 0x00600001, 0x22700229, 0x00cf9460, 0x00000000 }, { 0x00600001, 0x23700229, 0x00cf9860, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00d29080, 0x00000000 }, { 0x00600001, 0x22800229, 0x00cf9480, 0x00000000 }, { 0x00600001, 0x23800229, 0x00cf9880, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00d290a0, 0x00000000 }, { 0x00600001, 0x22900229, 0x00cf94a0, 0x00000000 }, { 0x00600001, 0x23900229, 0x00cf98a0, 0x00000000 }, { 0x00800001, 0x22000229, 0x00d290c0, 0x00000000 }, { 0x00600001, 0x22a00229, 0x00cf94c0, 0x00000000 }, { 0x00600001, 0x23a00229, 0x00cf98c0, 0x00000000 }, { 0x00800001, 0x22200229, 0x00d290e0, 0x00000000 }, { 0x00600001, 0x22b00229, 0x00cf94e0, 0x00000000 }, { 0x00600001, 0x23b00229, 0x00cf98e0, 0x00000000 }, { 0x00600001, 0x42500231, 0x00ae0260, 0x00000000 }, { 0x00800001, 0x42600231, 0x00ce0280, 0x00000000 }, { 0x00600001, 0x43500231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0x43600231, 0x00ce0380, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000005a }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a007 }, { 0x0020000c, 0x21003da5, 0x004500a0, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x28000c01, 0x408d0000, 0x0218a008 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x29000c01, 0x408d0000, 0x0218a009 }, { 0x00800001, 0x28600229, 0x008d0830, 0x00000000 }, { 0x00800001, 0x29600229, 0x008d0930, 0x00000000 }, { 0x00800001, 0x28400229, 0x008d0820, 0x00000000 }, { 0x00800001, 0x29400229, 0x008d0920, 0x00000000 }, { 0x00800001, 0x28200229, 0x008d0810, 0x00000000 }, { 0x00800001, 0x29200229, 0x008d0910, 0x00000000 }, { 0x00800001, 0x28000229, 0x008d0800, 0x00000000 }, { 0x00800001, 0x29000229, 0x008d0900, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x00910001, 0x22400231, 0x028d0800, 0x00000000 }, { 0x00910001, 0x23400231, 0x028d0900, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x00910001, 0x22500231, 0x028d0810, 0x00000000 }, { 0x00910001, 0x23500231, 0x028d0910, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x00910001, 0x22600231, 0x028d0820, 0x00000000 }, { 0x00910001, 0x23600231, 0x028d0920, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x00910001, 0x22700231, 0x028d0830, 0x00000000 }, { 0x00910001, 0x23700231, 0x028d0930, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x0a082007 }, { 0x0020000c, 0x21003da5, 0x004500a0, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20260, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x04082008 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20360, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x04082009 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff1e }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff18 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b000077500000000000000000000253701231401140700264410ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000009, 0x21003da5, 0x00000100, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02898001 }, { 0x00400040, 0x22083e28, 0x00690024, 0x07000700 }, { 0x00800001, 0x21400229, 0x00d29000, 0x00000000 }, { 0x00600001, 0x22400229, 0x00cf9400, 0x00000000 }, { 0x00600001, 0x23400229, 0x00cf9800, 0x00000000 }, { 0x00800001, 0x21600229, 0x00d29020, 0x00000000 }, { 0x00600001, 0x22500229, 0x00cf9420, 0x00000000 }, { 0x00600001, 0x23500229, 0x00cf9820, 0x00000000 }, { 0x00800001, 0x21800229, 0x00d29040, 0x00000000 }, { 0x00600001, 0x22600229, 0x00cf9440, 0x00000000 }, { 0x00600001, 0x23600229, 0x00cf9840, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00d29060, 0x00000000 }, { 0x00600001, 0x22700229, 0x00cf9460, 0x00000000 }, { 0x00600001, 0x23700229, 0x00cf9860, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00d29080, 0x00000000 }, { 0x00600001, 0x22800229, 0x00cf9480, 0x00000000 }, { 0x00600001, 0x23800229, 0x00cf9880, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00d290a0, 0x00000000 }, { 0x00600001, 0x22900229, 0x00cf94a0, 0x00000000 }, { 0x00600001, 0x23900229, 0x00cf98a0, 0x00000000 }, { 0x00800001, 0x22000229, 0x00d290c0, 0x00000000 }, { 0x00600001, 0x22a00229, 0x00cf94c0, 0x00000000 }, { 0x00600001, 0x23a00229, 0x00cf98c0, 0x00000000 }, { 0x00800001, 0x22200229, 0x00d290e0, 0x00000000 }, { 0x00600001, 0x22b00229, 0x00cf94e0, 0x00000000 }, { 0x00600001, 0x23b00229, 0x00cf98e0, 0x00000000 }, { 0x00600001, 0x42500231, 0x00ae0260, 0x00000000 }, { 0x00800001, 0x42600231, 0x00ce0280, 0x00000000 }, { 0x00600001, 0x43500231, 0x00ae0360, 0x00000000 }, { 0x00800001, 0x43600231, 0x00ce0380, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000005a }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498007 }, { 0x0020000c, 0x21003da5, 0x004500a0, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000020, 0x02198008 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x29000cc1, 0x00000020, 0x02198009 }, { 0x00800001, 0x28600229, 0x008d0830, 0x00000000 }, { 0x00800001, 0x29600229, 0x008d0930, 0x00000000 }, { 0x00800001, 0x28400229, 0x008d0820, 0x00000000 }, { 0x00800001, 0x29400229, 0x008d0920, 0x00000000 }, { 0x00800001, 0x28200229, 0x008d0810, 0x00000000 }, { 0x00800001, 0x29200229, 0x008d0910, 0x00000000 }, { 0x00800001, 0x28000229, 0x008d0800, 0x00000000 }, { 0x00800001, 0x29000229, 0x008d0900, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x00910001, 0x22400231, 0x028d0800, 0x00000000 }, { 0x00910001, 0x23400231, 0x028d0900, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x00910001, 0x22500231, 0x028d0810, 0x00000000 }, { 0x00910001, 0x23500231, 0x028d0910, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x00910001, 0x22600231, 0x028d0820, 0x00000000 }, { 0x00910001, 0x23600231, 0x028d0920, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x00910001, 0x22700231, 0x028d0830, 0x00000000 }, { 0x00910001, 0x23700231, 0x028d0930, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x0a094007 }, { 0x0020000c, 0x21003da5, 0x004500a0, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20260, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x04094008 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20360, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x04094009 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff1e }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff18 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pl3_load_save_nv12.asm000066400000000000000000000004771231401140700267270ustar00rootroot00000000000000// Module name: PL3_LOAD_SAVE_NV12 .kernel PL3_LOAD_SAVE_NV12 .code #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #include "IMC3_Load_8x4.asm" #include "PL8x4_Save_NV12.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of pl3_load_save_nv12.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5000066400000000000000000000140201231401140700274450ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a001 }, { 0x0020000c, 0x21003ca5, 0x00450100, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x02600031, 0x28000c01, 0x408d0000, 0x0218a002 }, { 0x00600001, 0x20600022, 0x008d0100, 0x00000000 }, { 0x02600031, 0x29000c01, 0x408d0000, 0x0218a003 }, { 0x00800001, 0x22200229, 0x00b10770, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b10760, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10750, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10740, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10730, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10720, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10710, 0x00000000 }, { 0x00800001, 0x21400229, 0x00b10700, 0x00000000 }, { 0x00800001, 0x22600229, 0x008d0810, 0x00000000 }, { 0x00800001, 0x23600229, 0x008d0910, 0x00000000 }, { 0x00800001, 0x22400229, 0x008d0800, 0x00000000 }, { 0x00800001, 0x23400229, 0x008d0900, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x28000c01, 0x408d0000, 0x0228a008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x0a082007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x06082008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff3c }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff36 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b000066400000000000000000000236771231401140700266340ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498001 }, { 0x0020000c, 0x21003ca5, 0x00450100, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000040, 0x02198002 }, { 0x00600001, 0x20600022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x29000cc1, 0x00000040, 0x02198003 }, { 0x00800001, 0x22200229, 0x00b10770, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b10760, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10750, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10740, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10730, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10720, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10710, 0x00000000 }, { 0x00800001, 0x21400229, 0x00b10700, 0x00000000 }, { 0x00800001, 0x22600229, 0x008d0810, 0x00000000 }, { 0x00800001, 0x23600229, 0x008d0910, 0x00000000 }, { 0x00800001, 0x22400229, 0x008d0800, 0x00000000 }, { 0x00800001, 0x23400229, 0x008d0900, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000020, 0x02298008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x0a094007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x06094008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff3c }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff36 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pl3_load_save_pa.asm000077500000000000000000000005661231401140700265430ustar00rootroot00000000000000// Module name: PL3_LOAD_SAVE_pa .kernel PL3_LOAD_SAVE_PA // what's usage of it? just a name? .code #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #include "IMC3_Load_8x5.asm" #include "PL8x5_PL8x8.asm" #include "PL8x8_Save_PA.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of pl3_load_save_pa.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5000066400000000000000000000151551231401140700272710ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a001 }, { 0x0020000c, 0x21003ca5, 0x00450100, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00040007 }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x02600031, 0x28000c01, 0x408d0000, 0x0228a002 }, { 0x00600001, 0x20600022, 0x008d0100, 0x00000000 }, { 0x02600031, 0x29000c01, 0x408d0000, 0x0228a003 }, { 0x00800001, 0x22200229, 0x00b10770, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b10760, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10750, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10740, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10730, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10720, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10710, 0x00000000 }, { 0x00800001, 0x21400229, 0x00b10700, 0x00000000 }, { 0x00800001, 0x22800229, 0x008d0820, 0x00000000 }, { 0x00800001, 0x23800229, 0x008d0920, 0x00000000 }, { 0x00800001, 0x22600229, 0x008d0810, 0x00000000 }, { 0x00800001, 0x23600229, 0x008d0910, 0x00000000 }, { 0x00800001, 0x22400229, 0x008d0800, 0x00000000 }, { 0x00800001, 0x23400229, 0x008d0900, 0x00000000 }, { 0x80600042, 0x22b02529, 0x008d0270, 0x008d0280 }, { 0x80600042, 0x23b02529, 0x008d0370, 0x008d0380 }, { 0x00600001, 0x22a00129, 0x008d0270, 0x00000000 }, { 0x80600042, 0x22902529, 0x008d0260, 0x008d0270 }, { 0x00600001, 0x23a00129, 0x008d0370, 0x00000000 }, { 0x80600042, 0x23902529, 0x008d0360, 0x008d0370 }, { 0x00600001, 0x22800129, 0x008d0260, 0x00000000 }, { 0x80600042, 0x22702529, 0x008d0250, 0x008d0260 }, { 0x00600001, 0x23800129, 0x008d0360, 0x00000000 }, { 0x80600042, 0x23702529, 0x008d0350, 0x008d0360 }, { 0x00600001, 0x22600129, 0x008d0250, 0x00000000 }, { 0x80600042, 0x22502529, 0x008d0240, 0x008d0250 }, { 0x00600001, 0x23600129, 0x008d0350, 0x00000000 }, { 0x80600042, 0x23502529, 0x008d0340, 0x008d0350 }, { 0x00400040, 0x22083e28, 0x00690028, 0x07000700 }, { 0x00800001, 0xd0000231, 0x00d20140, 0x00000000 }, { 0x00800001, 0xd0200231, 0x00d20160, 0x00000000 }, { 0x00800001, 0xd0400231, 0x00d20180, 0x00000000 }, { 0x00800001, 0xd0600231, 0x00d201a0, 0x00000000 }, { 0x00800001, 0xd0800231, 0x00d201c0, 0x00000000 }, { 0x00800001, 0xd0a00231, 0x00d201e0, 0x00000000 }, { 0x00800001, 0xd0c00231, 0x00d20200, 0x00000000 }, { 0x00800001, 0xd0e00231, 0x00d20220, 0x00000000 }, { 0x00600001, 0xf4000231, 0x00ae0240, 0x00000000 }, { 0x00600001, 0xf8000231, 0x00ae0340, 0x00000000 }, { 0x00600001, 0xf4200231, 0x00ae0250, 0x00000000 }, { 0x00600001, 0xf8200231, 0x00ae0350, 0x00000000 }, { 0x00600001, 0xf4400231, 0x00ae0260, 0x00000000 }, { 0x00600001, 0xf8400231, 0x00ae0360, 0x00000000 }, { 0x00600001, 0xf4600231, 0x00ae0270, 0x00000000 }, { 0x00600001, 0xf8600231, 0x00ae0370, 0x00000000 }, { 0x00600001, 0xf4800231, 0x00ae0280, 0x00000000 }, { 0x00600001, 0xf8800231, 0x00ae0380, 0x00000000 }, { 0x00600001, 0xf4a00231, 0x00ae0290, 0x00000000 }, { 0x00600001, 0xf8a00231, 0x00ae0390, 0x00000000 }, { 0x00600001, 0xf4c00231, 0x00ae02a0, 0x00000000 }, { 0x00600001, 0xf8c00231, 0x00ae03a0, 0x00000000 }, { 0x00600001, 0xf4e00231, 0x00ae02b0, 0x00000000 }, { 0x00600001, 0xf8e00231, 0x00ae03b0, 0x00000000 }, { 0x00000409, 0x21003da5, 0x000000a0, 0x00010001 }, { 0x00000c01, 0x210401a5, 0x000000a2, 0x00000000 }, { 0x00000801, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000002a }, { 0x01600031, 0x21400c01, 0x408d0000, 0x0288a007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x27000129, 0x02b10140, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x27200129, 0x02b10160, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x27400129, 0x02b10180, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x27600129, 0x02b101a0, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x27800129, 0x02b101c0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x27a00129, 0x02b101e0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x27c00129, 0x02b10200, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x27e00129, 0x02b10220, 0x00000000 }, { 0x00600001, 0x20400022, 0x008d0700, 0x00000000 }, { 0x00600001, 0x20600022, 0x008d0720, 0x00000000 }, { 0x00600001, 0x20800022, 0x008d0740, 0x00000000 }, { 0x00600001, 0x20a00022, 0x008d0760, 0x00000000 }, { 0x00600001, 0x20c00022, 0x008d0780, 0x00000000 }, { 0x00600001, 0x20e00022, 0x008d07a0, 0x00000000 }, { 0x00600001, 0x21000022, 0x008d07c0, 0x00000000 }, { 0x00600001, 0x21200022, 0x008d07e0, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x12082007 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff26 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff20 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b000066400000000000000000000250341231401140700264330ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498001 }, { 0x0020000c, 0x21003ca5, 0x00450100, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00040007 }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000040, 0x02298002 }, { 0x00600001, 0x20600022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x29000cc1, 0x00000040, 0x02298003 }, { 0x00800001, 0x22200229, 0x00b10770, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b10760, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10750, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10740, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10730, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10720, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10710, 0x00000000 }, { 0x00800001, 0x21400229, 0x00b10700, 0x00000000 }, { 0x00800001, 0x22800229, 0x008d0820, 0x00000000 }, { 0x00800001, 0x23800229, 0x008d0920, 0x00000000 }, { 0x00800001, 0x22600229, 0x008d0810, 0x00000000 }, { 0x00800001, 0x23600229, 0x008d0910, 0x00000000 }, { 0x00800001, 0x22400229, 0x008d0800, 0x00000000 }, { 0x00800001, 0x23400229, 0x008d0900, 0x00000000 }, { 0x80600042, 0x22b02529, 0x008d0270, 0x008d0280 }, { 0x80600042, 0x23b02529, 0x008d0370, 0x008d0380 }, { 0x00600001, 0x22a00129, 0x008d0270, 0x00000000 }, { 0x80600042, 0x22902529, 0x008d0260, 0x008d0270 }, { 0x00600001, 0x23a00129, 0x008d0370, 0x00000000 }, { 0x80600042, 0x23902529, 0x008d0360, 0x008d0370 }, { 0x00600001, 0x22800129, 0x008d0260, 0x00000000 }, { 0x80600042, 0x22702529, 0x008d0250, 0x008d0260 }, { 0x00600001, 0x23800129, 0x008d0360, 0x00000000 }, { 0x80600042, 0x23702529, 0x008d0350, 0x008d0360 }, { 0x00600001, 0x22600129, 0x008d0250, 0x00000000 }, { 0x80600042, 0x22502529, 0x008d0240, 0x008d0250 }, { 0x00600001, 0x23600129, 0x008d0350, 0x00000000 }, { 0x80600042, 0x23502529, 0x008d0340, 0x008d0350 }, { 0x00400040, 0x22083e28, 0x00690028, 0x07000700 }, { 0x00800001, 0xd0000231, 0x00d20140, 0x00000000 }, { 0x00800001, 0xd0200231, 0x00d20160, 0x00000000 }, { 0x00800001, 0xd0400231, 0x00d20180, 0x00000000 }, { 0x00800001, 0xd0600231, 0x00d201a0, 0x00000000 }, { 0x00800001, 0xd0800231, 0x00d201c0, 0x00000000 }, { 0x00800001, 0xd0a00231, 0x00d201e0, 0x00000000 }, { 0x00800001, 0xd0c00231, 0x00d20200, 0x00000000 }, { 0x00800001, 0xd0e00231, 0x00d20220, 0x00000000 }, { 0x00600001, 0xf4000231, 0x00ae0240, 0x00000000 }, { 0x00600001, 0xf8000231, 0x00ae0340, 0x00000000 }, { 0x00600001, 0xf4200231, 0x00ae0250, 0x00000000 }, { 0x00600001, 0xf8200231, 0x00ae0350, 0x00000000 }, { 0x00600001, 0xf4400231, 0x00ae0260, 0x00000000 }, { 0x00600001, 0xf8400231, 0x00ae0360, 0x00000000 }, { 0x00600001, 0xf4600231, 0x00ae0270, 0x00000000 }, { 0x00600001, 0xf8600231, 0x00ae0370, 0x00000000 }, { 0x00600001, 0xf4800231, 0x00ae0280, 0x00000000 }, { 0x00600001, 0xf8800231, 0x00ae0380, 0x00000000 }, { 0x00600001, 0xf4a00231, 0x00ae0290, 0x00000000 }, { 0x00600001, 0xf8a00231, 0x00ae0390, 0x00000000 }, { 0x00600001, 0xf4c00231, 0x00ae02a0, 0x00000000 }, { 0x00600001, 0xf8c00231, 0x00ae03a0, 0x00000000 }, { 0x00600001, 0xf4e00231, 0x00ae02b0, 0x00000000 }, { 0x00600001, 0xf8e00231, 0x00ae03b0, 0x00000000 }, { 0x00000409, 0x21003da5, 0x000000a0, 0x00010001 }, { 0x00000c01, 0x210401a5, 0x000000a2, 0x00000000 }, { 0x00000801, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x0000002a }, { 0x04600031, 0x21400cc1, 0x00000020, 0x02898007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x27000129, 0x02b10140, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x27200129, 0x02b10160, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x27400129, 0x02b10180, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x27600129, 0x02b101a0, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x27800129, 0x02b101c0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x27a00129, 0x02b101e0, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x27c00129, 0x02b10200, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x27e00129, 0x02b10220, 0x00000000 }, { 0x00600001, 0x20400022, 0x008d0700, 0x00000000 }, { 0x00600001, 0x20600022, 0x008d0720, 0x00000000 }, { 0x00600001, 0x20800022, 0x008d0740, 0x00000000 }, { 0x00600001, 0x20a00022, 0x008d0760, 0x00000000 }, { 0x00600001, 0x20c00022, 0x008d0780, 0x00000000 }, { 0x00600001, 0x20e00022, 0x008d07a0, 0x00000000 }, { 0x00600001, 0x21000022, 0x008d07c0, 0x00000000 }, { 0x00600001, 0x21200022, 0x008d07e0, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x12094007 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff26 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff20 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pl3_load_save_pl3.asm000066400000000000000000000004741231401140700266340ustar00rootroot00000000000000// Module name: PL3_LOAD_SAVE_pl3 .kernel PL3_LOAD_SAVE_PL3 .code #include "SetupVPKernel.asm" #include "Multiple_Loop_Head.asm" #include "IMC3_Load_8x4.asm" #include "PL8x4_Save_IMC3.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of pl3_load_save_pl3.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5000066400000000000000000000137311231401140700273650ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a001 }, { 0x0020000c, 0x21003ca5, 0x00450100, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x02600031, 0x28000c01, 0x408d0000, 0x0218a002 }, { 0x00600001, 0x20600022, 0x008d0100, 0x00000000 }, { 0x02600031, 0x29000c01, 0x408d0000, 0x0218a003 }, { 0x00800001, 0x22200229, 0x00b10770, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b10760, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10750, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10740, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10730, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10720, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10710, 0x00000000 }, { 0x00800001, 0x21400229, 0x00b10700, 0x00000000 }, { 0x00800001, 0x22600229, 0x008d0810, 0x00000000 }, { 0x00800001, 0x23600229, 0x008d0910, 0x00000000 }, { 0x00800001, 0x22400229, 0x008d0800, 0x00000000 }, { 0x00800001, 0x23400229, 0x008d0900, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a007 }, { 0x0020000c, 0x21003da5, 0x004500a0, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x28000c01, 0x408d0000, 0x0218a008 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x29000c01, 0x408d0000, 0x0218a009 }, { 0x00800001, 0x28200229, 0x008d0810, 0x00000000 }, { 0x00800001, 0x29200229, 0x008d0910, 0x00000000 }, { 0x00800001, 0x28000229, 0x008d0800, 0x00000000 }, { 0x00800001, 0x29000229, 0x008d0900, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x00910001, 0x22400231, 0x028d0800, 0x00000000 }, { 0x00910001, 0x23400231, 0x028d0900, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x00910001, 0x22500231, 0x028d0810, 0x00000000 }, { 0x00910001, 0x23500231, 0x028d0910, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x00910001, 0x22600231, 0x028d0820, 0x00000000 }, { 0x00910001, 0x23600231, 0x028d0920, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x00910001, 0x22700231, 0x028d0830, 0x00000000 }, { 0x00910001, 0x23700231, 0x028d0930, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x0a082007 }, { 0x0020000c, 0x21003da5, 0x004500a0, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20260, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x04082008 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20360, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x04082009 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff3e }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff38 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b000066400000000000000000000236101231401140700265270ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498001 }, { 0x0020000c, 0x21003ca5, 0x00450100, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20400022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000040, 0x02198002 }, { 0x00600001, 0x20600022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x29000cc1, 0x00000040, 0x02198003 }, { 0x00800001, 0x22200229, 0x00b10770, 0x00000000 }, { 0x00800001, 0x22000229, 0x00b10760, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00b10750, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00b10740, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00b10730, 0x00000000 }, { 0x00800001, 0x21800229, 0x00b10720, 0x00000000 }, { 0x00800001, 0x21600229, 0x00b10710, 0x00000000 }, { 0x00800001, 0x21400229, 0x00b10700, 0x00000000 }, { 0x00800001, 0x22600229, 0x008d0810, 0x00000000 }, { 0x00800001, 0x23600229, 0x008d0910, 0x00000000 }, { 0x00800001, 0x22400229, 0x008d0800, 0x00000000 }, { 0x00800001, 0x23400229, 0x008d0900, 0x00000000 }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000052 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498007 }, { 0x0020000c, 0x21003da5, 0x004500a0, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000020, 0x02198008 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x29000cc1, 0x00000020, 0x02198009 }, { 0x00800001, 0x28200229, 0x008d0810, 0x00000000 }, { 0x00800001, 0x29200229, 0x008d0910, 0x00000000 }, { 0x00800001, 0x28000229, 0x008d0800, 0x00000000 }, { 0x00800001, 0x29000229, 0x008d0900, 0x00000000 }, { 0x00000001, 0x26000228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x000000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x00000000, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x00910001, 0x22400231, 0x028d0800, 0x00000000 }, { 0x00910001, 0x23400231, 0x028d0900, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x00910001, 0x22500231, 0x028d0810, 0x00000000 }, { 0x00910001, 0x23500231, 0x028d0910, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x00910001, 0x22600231, 0x028d0820, 0x00000000 }, { 0x00910001, 0x23600231, 0x028d0920, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x00910001, 0x22700231, 0x028d0830, 0x00000000 }, { 0x00910001, 0x23700231, 0x028d0930, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x0a094007 }, { 0x0020000c, 0x21003da5, 0x004500a0, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x00030007 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20260, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x04094008 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20360, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x04094009 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xffffff3e }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xffffff38 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/rgbx_load_save_nv12.asm000077500000000000000000000010601231401140700271630ustar00rootroot00000000000000// Module name: RGBX_LOAD_SAVE_NV12 .kernel RGBX_LOAD_SAVE_NV12 .code #define FIX_POINT_CONVERSION // #define FLOAT_POINT_CONVERSION #include "SetupVPKernel.asm" #include "RGBX_to_YUV_Coef.asm" #include "Multiple_Loop_Head.asm" #include "RGBX_Load_16x8.asm" #ifdef FIX_POINT_CONVERSION #include "RGBX_Save_YUV_Fix.asm" #else #include "RGBX_Save_YUV_Float.asm" #endif #include "PL16x8_PL8x4.asm" #include "PL8x4_Save_NV12.asm" #include "Multiple_Loop.asm" END_THREAD // End of Thread .end_code .end_kernel // end of rgbx_load_save_nv12.asm intel-driver-1.3.0/src/shaders/post_processing/gen5_6/rgbx_load_save_nv12.g4b.gen5000066400000000000000000000751661231401140700277330ustar00rootroot00000000000000 { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x02000005, 0x20000c24, 0x02000024, 0xff000000 }, { 0x00110001, 0x24400061, 0x02000000, 0x00428119 }, { 0x00010001, 0x24400061, 0x02000000, 0x00198142 }, { 0x00110001, 0x24440061, 0x02000000, 0x00dab670 }, { 0x00010001, 0x24440061, 0x02000000, 0x0070b6da }, { 0x00110001, 0x24480061, 0x02000000, 0x0070a2ee }, { 0x00010001, 0x24480061, 0x02000000, 0x00eea270 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000409, 0x21003da5, 0x00000100, 0x00020002 }, { 0x00000801, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0288a001 }, { 0x00000040, 0x21003ca5, 0x00000100, 0x00200020 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x28000c01, 0x408d0000, 0x0288a001 }, { 0x00000001, 0x22000060, 0x00000000, 0x08000700 }, { 0x00800041, 0x24c04629, 0x00118000, 0x00090440 }, { 0x00800041, 0x24e04629, 0x00118010, 0x00090440 }, { 0x00800041, 0x25004629, 0x00118400, 0x00090440 }, { 0x00800041, 0x25204629, 0x00118410, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x21400229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118000, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x00118010, 0x00090444 }, { 0x00800041, 0x2500562d, 0x00118400, 0x00090444 }, { 0x00800041, 0x2520562d, 0x00118410, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22400229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118000, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x00118010, 0x00090448 }, { 0x00800041, 0x2500562d, 0x00118400, 0x00090448 }, { 0x00800041, 0x2520562d, 0x00118410, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23400229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x00118020, 0x00090440 }, { 0x00800041, 0x24e04629, 0x00118030, 0x00090440 }, { 0x00800041, 0x25004629, 0x00118420, 0x00090440 }, { 0x00800041, 0x25204629, 0x00118430, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x21600229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118020, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x00118030, 0x00090444 }, { 0x00800041, 0x2500562d, 0x00118420, 0x00090444 }, { 0x00800041, 0x2520562d, 0x00118430, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22600229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118020, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x00118030, 0x00090448 }, { 0x00800041, 0x2500562d, 0x00118420, 0x00090448 }, { 0x00800041, 0x2520562d, 0x00118430, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23600229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x00118040, 0x00090440 }, { 0x00800041, 0x24e04629, 0x00118050, 0x00090440 }, { 0x00800041, 0x25004629, 0x00118440, 0x00090440 }, { 0x00800041, 0x25204629, 0x00118450, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x21800229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118040, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x00118050, 0x00090444 }, { 0x00800041, 0x2500562d, 0x00118440, 0x00090444 }, { 0x00800041, 0x2520562d, 0x00118450, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22800229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118040, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x00118050, 0x00090448 }, { 0x00800041, 0x2500562d, 0x00118440, 0x00090448 }, { 0x00800041, 0x2520562d, 0x00118450, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23800229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x00118060, 0x00090440 }, { 0x00800041, 0x24e04629, 0x00118070, 0x00090440 }, { 0x00800041, 0x25004629, 0x00118460, 0x00090440 }, { 0x00800041, 0x25204629, 0x00118470, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118060, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x00118070, 0x00090444 }, { 0x00800041, 0x2500562d, 0x00118460, 0x00090444 }, { 0x00800041, 0x2520562d, 0x00118470, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22a00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118060, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x00118070, 0x00090448 }, { 0x00800041, 0x2500562d, 0x00118460, 0x00090448 }, { 0x00800041, 0x2520562d, 0x00118470, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23a00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x00118080, 0x00090440 }, { 0x00800041, 0x24e04629, 0x00118090, 0x00090440 }, { 0x00800041, 0x25004629, 0x00118480, 0x00090440 }, { 0x00800041, 0x25204629, 0x00118490, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118080, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x00118090, 0x00090444 }, { 0x00800041, 0x2500562d, 0x00118480, 0x00090444 }, { 0x00800041, 0x2520562d, 0x00118490, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22c00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118080, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x00118090, 0x00090448 }, { 0x00800041, 0x2500562d, 0x00118480, 0x00090448 }, { 0x00800041, 0x2520562d, 0x00118490, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23c00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x001180a0, 0x00090440 }, { 0x00800041, 0x24e04629, 0x001180b0, 0x00090440 }, { 0x00800041, 0x25004629, 0x001184a0, 0x00090440 }, { 0x00800041, 0x25204629, 0x001184b0, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x001180a0, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x001180b0, 0x00090444 }, { 0x00800041, 0x2500562d, 0x001184a0, 0x00090444 }, { 0x00800041, 0x2520562d, 0x001184b0, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22e00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x001180a0, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x001180b0, 0x00090448 }, { 0x00800041, 0x2500562d, 0x001184a0, 0x00090448 }, { 0x00800041, 0x2520562d, 0x001184b0, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23e00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x001180c0, 0x00090440 }, { 0x00800041, 0x24e04629, 0x001180d0, 0x00090440 }, { 0x00800041, 0x25004629, 0x001184c0, 0x00090440 }, { 0x00800041, 0x25204629, 0x001184d0, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22000229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x001180c0, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x001180d0, 0x00090444 }, { 0x00800041, 0x2500562d, 0x001184c0, 0x00090444 }, { 0x00800041, 0x2520562d, 0x001184d0, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23000229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x001180c0, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x001180d0, 0x00090448 }, { 0x00800041, 0x2500562d, 0x001184c0, 0x00090448 }, { 0x00800041, 0x2520562d, 0x001184d0, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x24000229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x001180e0, 0x00090440 }, { 0x00800041, 0x24e04629, 0x001180f0, 0x00090440 }, { 0x00800041, 0x25004629, 0x001184e0, 0x00090440 }, { 0x00800041, 0x25204629, 0x001184f0, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22200229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x001180e0, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x001180f0, 0x00090444 }, { 0x00800041, 0x2500562d, 0x001184e0, 0x00090444 }, { 0x00800041, 0x2520562d, 0x001184f0, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23200229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x001180e0, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x001180f0, 0x00090448 }, { 0x00800041, 0x2500562d, 0x001184e0, 0x00090448 }, { 0x00800041, 0x2520562d, 0x001184f0, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x24200229, 0x00110540, 0x00000000 }, { 0x00600001, 0x22400129, 0x00ae0240, 0x00000000 }, { 0x00600001, 0x23400129, 0x00ae0340, 0x00000000 }, { 0x00600001, 0x22500129, 0x00ae0280, 0x00000000 }, { 0x00600001, 0x23500129, 0x00ae0380, 0x00000000 }, { 0x00600001, 0x22600129, 0x00ae02c0, 0x00000000 }, { 0x00600001, 0x23600129, 0x00ae03c0, 0x00000000 }, { 0x00600001, 0x22700129, 0x00ae0300, 0x00000000 }, { 0x00600001, 0x23700129, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x01600031, 0x27000c01, 0x408d0000, 0x0248a007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x01600031, 0x28000c01, 0x408d0000, 0x0228a008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x0a082007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x01600031, 0x20000c04, 0x508d0000, 0x06082008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xfffffbb6 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffbb0 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen5_6/rgbx_load_save_nv12.g6b000066400000000000000000001050451231401140700270660ustar00rootroot00000000000000 { 0x00600001, 0x20e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x22e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x25e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x26e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x27e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29a00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x29e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21000021, 0x008d0000, 0x00000000 }, { 0x02000005, 0x20000c24, 0x02000024, 0xff000000 }, { 0x00110001, 0x24400061, 0x02000000, 0x00428119 }, { 0x00010001, 0x24400061, 0x02000000, 0x00198142 }, { 0x00110001, 0x24440061, 0x02000000, 0x00dab670 }, { 0x00010001, 0x24440061, 0x02000000, 0x0070b6da }, { 0x00110001, 0x24480061, 0x02000000, 0x0070a2ee }, { 0x00010001, 0x24480061, 0x02000000, 0x00eea270 }, { 0x00000441, 0x20842e2d, 0x000000b7, 0x00100010 }, { 0x00000c01, 0x2086022d, 0x000000bb, 0x00000000 }, { 0x00000801, 0x208a01ad, 0x000000a0, 0x00000000 }, { 0x00200001, 0x209403bd, 0x006600a4, 0x00000000 }, { 0x00000040, 0x208435ad, 0x00000084, 0x000000a0 }, { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 }, { 0x00000409, 0x21003da5, 0x00000100, 0x00020002 }, { 0x00000801, 0x21080061, 0x00000000, 0x0007001f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02898001 }, { 0x00000040, 0x21003ca5, 0x00000100, 0x00200020 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000020, 0x02898001 }, { 0x00000001, 0x22000060, 0x00000000, 0x08000700 }, { 0x00800041, 0x24c04629, 0x00118000, 0x00090440 }, { 0x00800041, 0x24e04629, 0x00118010, 0x00090440 }, { 0x00800041, 0x25004629, 0x00118400, 0x00090440 }, { 0x00800041, 0x25204629, 0x00118410, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x21400229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118000, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x00118010, 0x00090444 }, { 0x00800041, 0x2500562d, 0x00118400, 0x00090444 }, { 0x00800041, 0x2520562d, 0x00118410, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22400229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118000, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x00118010, 0x00090448 }, { 0x00800041, 0x2500562d, 0x00118400, 0x00090448 }, { 0x00800041, 0x2520562d, 0x00118410, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23400229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x00118020, 0x00090440 }, { 0x00800041, 0x24e04629, 0x00118030, 0x00090440 }, { 0x00800041, 0x25004629, 0x00118420, 0x00090440 }, { 0x00800041, 0x25204629, 0x00118430, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x21600229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118020, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x00118030, 0x00090444 }, { 0x00800041, 0x2500562d, 0x00118420, 0x00090444 }, { 0x00800041, 0x2520562d, 0x00118430, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22600229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118020, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x00118030, 0x00090448 }, { 0x00800041, 0x2500562d, 0x00118420, 0x00090448 }, { 0x00800041, 0x2520562d, 0x00118430, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23600229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x00118040, 0x00090440 }, { 0x00800041, 0x24e04629, 0x00118050, 0x00090440 }, { 0x00800041, 0x25004629, 0x00118440, 0x00090440 }, { 0x00800041, 0x25204629, 0x00118450, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x21800229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118040, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x00118050, 0x00090444 }, { 0x00800041, 0x2500562d, 0x00118440, 0x00090444 }, { 0x00800041, 0x2520562d, 0x00118450, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22800229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118040, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x00118050, 0x00090448 }, { 0x00800041, 0x2500562d, 0x00118440, 0x00090448 }, { 0x00800041, 0x2520562d, 0x00118450, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23800229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x00118060, 0x00090440 }, { 0x00800041, 0x24e04629, 0x00118070, 0x00090440 }, { 0x00800041, 0x25004629, 0x00118460, 0x00090440 }, { 0x00800041, 0x25204629, 0x00118470, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x21a00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118060, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x00118070, 0x00090444 }, { 0x00800041, 0x2500562d, 0x00118460, 0x00090444 }, { 0x00800041, 0x2520562d, 0x00118470, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22a00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118060, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x00118070, 0x00090448 }, { 0x00800041, 0x2500562d, 0x00118460, 0x00090448 }, { 0x00800041, 0x2520562d, 0x00118470, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23a00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x00118080, 0x00090440 }, { 0x00800041, 0x24e04629, 0x00118090, 0x00090440 }, { 0x00800041, 0x25004629, 0x00118480, 0x00090440 }, { 0x00800041, 0x25204629, 0x00118490, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x21c00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118080, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x00118090, 0x00090444 }, { 0x00800041, 0x2500562d, 0x00118480, 0x00090444 }, { 0x00800041, 0x2520562d, 0x00118490, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22c00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x00118080, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x00118090, 0x00090448 }, { 0x00800041, 0x2500562d, 0x00118480, 0x00090448 }, { 0x00800041, 0x2520562d, 0x00118490, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23c00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x001180a0, 0x00090440 }, { 0x00800041, 0x24e04629, 0x001180b0, 0x00090440 }, { 0x00800041, 0x25004629, 0x001184a0, 0x00090440 }, { 0x00800041, 0x25204629, 0x001184b0, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x21e00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x001180a0, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x001180b0, 0x00090444 }, { 0x00800041, 0x2500562d, 0x001184a0, 0x00090444 }, { 0x00800041, 0x2520562d, 0x001184b0, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22e00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x001180a0, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x001180b0, 0x00090448 }, { 0x00800041, 0x2500562d, 0x001184a0, 0x00090448 }, { 0x00800041, 0x2520562d, 0x001184b0, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23e00229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x001180c0, 0x00090440 }, { 0x00800041, 0x24e04629, 0x001180d0, 0x00090440 }, { 0x00800041, 0x25004629, 0x001184c0, 0x00090440 }, { 0x00800041, 0x25204629, 0x001184d0, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22000229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x001180c0, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x001180d0, 0x00090444 }, { 0x00800041, 0x2500562d, 0x001184c0, 0x00090444 }, { 0x00800041, 0x2520562d, 0x001184d0, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23000229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x001180c0, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x001180d0, 0x00090448 }, { 0x00800041, 0x2500562d, 0x001184c0, 0x00090448 }, { 0x00800041, 0x2520562d, 0x001184d0, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x24000229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c04629, 0x001180e0, 0x00090440 }, { 0x00800041, 0x24e04629, 0x001180f0, 0x00090440 }, { 0x00800041, 0x25004629, 0x001184e0, 0x00090440 }, { 0x00800041, 0x25204629, 0x001184f0, 0x00090440 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c02529, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e02529, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x65002529, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x65202529, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x25400129, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x25480129, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x25500129, 0x000b0500, 0x00000000 }, { 0x00400001, 0x25580129, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402d29, 0x00110540, 0x10801080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x22200229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x001180e0, 0x00090444 }, { 0x00800041, 0x24e0562d, 0x001180f0, 0x00090444 }, { 0x00800041, 0x2500562d, 0x001184e0, 0x00090444 }, { 0x00800041, 0x2520562d, 0x001184f0, 0x00090444 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x23200229, 0x00110540, 0x00000000 }, { 0x00800041, 0x24c0562d, 0x001180e0, 0x00090448 }, { 0x00800041, 0x24e0562d, 0x001180f0, 0x00090448 }, { 0x00800041, 0x2500562d, 0x001184e0, 0x00090448 }, { 0x00800041, 0x2520562d, 0x001184f0, 0x00090448 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c2 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e2 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0502 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0522 }, { 0x00400040, 0x64c035ad, 0x000b04c0, 0x000b04c4 }, { 0x00400040, 0x64e035ad, 0x000b04e0, 0x000b04e4 }, { 0x00400040, 0x650035ad, 0x000b0500, 0x000b0504 }, { 0x00400040, 0x652035ad, 0x000b0520, 0x000b0524 }, { 0x00400001, 0x254001ad, 0x000b04c0, 0x00000000 }, { 0x00400001, 0x254801ad, 0x000b04e0, 0x00000000 }, { 0x00400001, 0x255001ad, 0x000b0500, 0x00000000 }, { 0x00400001, 0x255801ad, 0x000b0520, 0x00000000 }, { 0x00800040, 0x25402da9, 0x00110540, 0x80808080 }, { 0x00800001, 0x25400231, 0x00120541, 0x00000000 }, { 0x00800001, 0x24200229, 0x00110540, 0x00000000 }, { 0x00600001, 0x22400129, 0x00ae0240, 0x00000000 }, { 0x00600001, 0x23400129, 0x00ae0340, 0x00000000 }, { 0x00600001, 0x22500129, 0x00ae0280, 0x00000000 }, { 0x00600001, 0x23500129, 0x00ae0380, 0x00000000 }, { 0x00600001, 0x22600129, 0x00ae02c0, 0x00000000 }, { 0x00600001, 0x23600129, 0x00ae03c0, 0x00000000 }, { 0x00600001, 0x22700129, 0x00ae0300, 0x00000000 }, { 0x00600001, 0x23700129, 0x00ae0400, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00200001, 0x202001a6, 0x004500a0, 0x00000000 }, { 0x00000001, 0x20280062, 0x00000000, 0x0007000f }, { 0x00000005, 0x24000c20, 0x000000b8, 0x00ffffff }, { 0x04000010, 0x20000c04, 0x00000400, 0x00ffffff }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000056 }, { 0x04600031, 0x27000cc1, 0x00000020, 0x02498007 }, { 0x0000040c, 0x21043da1, 0x000000a2, 0x00010001 }, { 0x00000801, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x04600031, 0x28000cc1, 0x00000020, 0x02298008 }, { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 }, { 0x00000001, 0x21080061, 0x00000000, 0x0007000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00000001, 0x26020228, 0x000000ba, 0x00000000 }, { 0x00610001, 0x24400129, 0x020000b8, 0x00000000 }, { 0x00710001, 0x24400169, 0x02000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00040001 }, { 0x00000001, 0x24640061, 0x00000000, 0x00400010 }, { 0x00000001, 0x24680061, 0x00000000, 0x04000100 }, { 0x00000001, 0x246c0061, 0x00000000, 0x40001000 }, { 0x00000001, 0x26020128, 0x00000440, 0x00000000 }, { 0x00910001, 0x41400231, 0x02b10700, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000440, 0x008d0460 }, { 0x00710001, 0x42400231, 0x02ae0800, 0x00000000 }, { 0x00710001, 0x43400231, 0x02ae0801, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000442, 0x00000000 }, { 0x00910001, 0x41600231, 0x02b10710, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000444, 0x00000000 }, { 0x00910001, 0x41800231, 0x02b10720, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000444, 0x008d0460 }, { 0x00710001, 0x42500231, 0x02ae0810, 0x00000000 }, { 0x00710001, 0x43500231, 0x02ae0811, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000446, 0x00000000 }, { 0x00910001, 0x41a00231, 0x02b10730, 0x00000000 }, { 0x00000001, 0x26020128, 0x00000448, 0x00000000 }, { 0x00910001, 0x41c00231, 0x02b10740, 0x00000000 }, { 0x02600005, 0x2000252c, 0x02000448, 0x008d0460 }, { 0x00710001, 0x42600231, 0x02ae0820, 0x00000000 }, { 0x00710001, 0x43600231, 0x02ae0821, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044a, 0x00000000 }, { 0x00910001, 0x41e00231, 0x02b10750, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044c, 0x00000000 }, { 0x00910001, 0x42000231, 0x02b10760, 0x00000000 }, { 0x02600005, 0x2000252c, 0x0200044c, 0x008d0460 }, { 0x00710001, 0x42700231, 0x02ae0830, 0x00000000 }, { 0x00710001, 0x43700231, 0x02ae0831, 0x00000000 }, { 0x00000001, 0x26020128, 0x0000044e, 0x00000000 }, { 0x00910001, 0x42200231, 0x02b10770, 0x00000000 }, { 0x00800001, 0x20400232, 0x00d20140, 0x00000000 }, { 0x00800001, 0x20500232, 0x00d20160, 0x00000000 }, { 0x00800001, 0x20600232, 0x00d20180, 0x00000000 }, { 0x00800001, 0x20700232, 0x00d201a0, 0x00000000 }, { 0x00800001, 0x20800232, 0x00d201c0, 0x00000000 }, { 0x00800001, 0x20900232, 0x00d201e0, 0x00000000 }, { 0x00800001, 0x20a00232, 0x00d20200, 0x00000000 }, { 0x00800001, 0x20b00232, 0x00d20220, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x0a094007 }, { 0x00200001, 0x210001a5, 0x004500a0, 0x00000000 }, { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 }, { 0x00000001, 0x21080061, 0x00000000, 0x0003000f }, { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 }, { 0x00800001, 0x40400232, 0x00d20240, 0x00000000 }, { 0x00800001, 0x40410232, 0x00d20340, 0x00000000 }, { 0x00800001, 0x40600232, 0x00d20260, 0x00000000 }, { 0x00800001, 0x40610232, 0x00d20360, 0x00000000 }, { 0x05600031, 0x20000cc4, 0x00000020, 0x06094008 }, { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff }, { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 }, { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000001, 0x20b80129, 0x000000c8, 0x00000000 }, { 0x01000010, 0x20003dac, 0x00000086, 0x00010001 }, { 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 }, { 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0xfffffbb6 }, { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 }, { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 }, { 0x00000220, 0x34001c00, 0x00001400, 0xfffffbb0 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/000077500000000000000000000000001231401140700224115ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/post_processing/gen7/DI_Core.g4a000066400000000000000000000261341231401140700242600ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 22 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // End of common.inc // FileName: DI.asm // Author: Vivek Kumar // Description: Tasks for DI only case (16x4 block) // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x4AE8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(9,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DI_STMM_Save.asm // Author: Vivek Kumar // Description: Saves DI STMM Data to statistics surface in case of DI enabled (for 16x4 block) // Write STMM to memory mov (8) mudMSGHDR_STMM(0)<1> r0.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udDNDI_RESP(8,0) // Move STMM to MRF shr (1) mudMSGHDR_STMM(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin / 2 mov (1) mudMSGHDR_STMM(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_STMM(0,2)<1> 0x30007:ud { NoDDChk } // block width and height (8x4) send (8) null<1>:d r20 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x20007:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | MCNT | FCNT | TCNT | X | X | X | X | //---------------------------------------------------- //| DcTpT | SVCM | DcBpT | DcTpB | //---------------------------------------------------- //| SHCM | STAD | DcTcB | DcBpB | //---------------------------------------------------- mov (1) mudMSGHDR_ENC_STATS(1,0)<1> udDNDI_RESP(9,1)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,3)<2> udDNDI_RESP(9,3)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,2)<2> udDNDI_RESP(9,5)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud intel-driver-1.3.0/src/shaders/post_processing/gen7/DI_Save_NV12_16x4.g4a000066400000000000000000000222151231401140700256120ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 20 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // End of common.inc // FileName: DI_Save_NV12_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in NV12 format // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled mov (2) r27.0<1>:d r7.0<2;2,1>:w { NoDDClr } mov (1) r27.2<1>:ud 0x3000F:ud { NoDDChk } // Block width and height (16x4) //Bottom field Y mov (8) mudMSGHDR_DI_OUT1(1)<1> udDNDI_RESP(0,0) mov (8) mudMSGHDR_DI_OUT1(2)<1> udDNDI_RESP(0,8) // Top field Y mov (8) mudMSGHDR_DI_OUT2(1)<1> udDNDI_RESP(4,0) mov (8) mudMSGHDR_DI_OUT2(2)<1> udDNDI_RESP(4,8) //copy message desrcptor to the message header mov (8) r18.0<1>:ud r27<8;8,1>:ud mov (8) r23.0<1>:ud r27<8;8,1>:ud //Change origin to U/V block asr (1) r27.1<1>:d r27.1<0;1,0>:d 1:w { NoDDClr } // U/V block origin should be half of Y's mov (1) r27.2<1>:ud 0x1000F:ud { NoDDChk } // Block width and height (16x2) // Bottom field U/V mov (16) r21.0<2>:ub ubDNDI_RESP(2, 1)<32;8,2> { NoDDClr } mov (16) r21.1<2>:ub ubDNDI_RESP(2, 0)<32;8,2> { NoDDChk } // Top field U/V mov (16) r26.0<2>:ub ubDNDI_RESP(6, 1)<32;8,2> { NoDDClr } mov (16) r26.1<2>:ub ubDNDI_RESP(6, 0)<32;8,2> { NoDDChk } //copy message desrcptor to the message header mov (8) r21<1>:ud r27<8;8,1>:ud mov (8) r26<1>:ud r27<8;8,1>:ud //Send out Y component on previous frame to surface send (8) null<1>:d r18.0 0x5 0x60A801B:ud //Send out Y component on current frame to surface send (8) null<1>:d r23.0 0x5 0x60A801E:ud //Send out U/V component on previous frame to surface send (8) null<1>:d r21 0x5 0x40A801C:ud //Send out U/V component on current frame to surface send (8) null<1>:d r26 0x5 0x40A801F:ud intel-driver-1.3.0/src/shaders/post_processing/gen7/DI_Save_PA_16x4.g4a000066400000000000000000000250351231401140700254270ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 33 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // End of common.inc // FileName: DI_Save_PA_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in Packed format // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled add (4) a0.4<1>:uw r2.28<4;4,1>:ub 608:w // Initial Y,U,V offset in YUV422 block; it starts at m20 mov (8) r27.0<1>:ud r0.0<8;8,1>:ud shl (1) r27.0<1>:d r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be doubled mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) r27.2<1>:ud 0x3001F:ud { NoDDChk } // Block width and height (32x8) //prepare the message headers mov (8) r18.0<1>:ud r27<8;8,1>:ud mov (8) r23.0<1>:ud r27<8;8,1>:ud // Pack 2nd field Y mov (16) r[a0.4, 0]<2> ubDNDI_RESP(0,0) { NoDDClr } mov (16) r[a0.4, 32]<2> ubDNDI_RESP(0,16) { NoDDClr } mov (16) r[a0.4, 64]<2> ubDNDI_RESP(0,32) { NoDDClr } mov (16) r[a0.4, 96]<2> ubDNDI_RESP(0,48) { NoDDClr } // Pack 2nd field U mov (8) r[a0.5, 0]<4> ubDNDI_RESP(2,1)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 32]<4> ubDNDI_RESP(2,17)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 64]<4> ubDNDI_RESP(2,33)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 96]<4> ubDNDI_RESP(2,49)<16;8,2> { NoDDClr, NoDDChk } //U pixels // Pack 2nd field V mov (8) r[a0.6, 0]<4> ubDNDI_RESP(2,0)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 32]<4> ubDNDI_RESP(2,16)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 64]<4> ubDNDI_RESP(2,32)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 96]<4> ubDNDI_RESP(2,48)<16;8,2> { NoDDChk } //Vpixels // Pack 1st field Y mov (16) r[a0.4, 160]<2> ubDNDI_RESP(4,0) { NoDDClr } mov (16) r[a0.4, 192]<2> ubDNDI_RESP(4,16) { NoDDClr } mov (16) r[a0.4, 224]<2> ubDNDI_RESP(4,32) { NoDDClr } mov (16) r[a0.4, 256]<2> ubDNDI_RESP(4,48) { NoDDClr } // Pack 1st field U mov (8) r[a0.5, 160]<4> ubDNDI_RESP(6,1)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 192]<4> ubDNDI_RESP(6,17)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 224]<4> ubDNDI_RESP(6,33)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 256]<4> ubDNDI_RESP(6,49)<16;8,2> { NoDDClr, NoDDChk } //U pixels // Pack 1st field V mov (8) r[a0.6, 160]<4> ubDNDI_RESP(6,0)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 192]<4> ubDNDI_RESP(6,16)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 224]<4> ubDNDI_RESP(6,32)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 256]<4> ubDNDI_RESP(6,48)<16;8,2> { NoDDChk } //Vpixels //save the previous frame send (8) null<1>:d r18.0 0x5 0xA0A801B:ud //save the current frame send (8) null<1>:d r23.0 0x5 0xA0A801E:ud intel-driver-1.3.0/src/shaders/post_processing/gen7/EOT.g4a000066400000000000000000000113411231401140700234350ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 2 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 intel-driver-1.3.0/src/shaders/post_processing/gen7/Makefile.am000066400000000000000000000041451231401140700244510ustar00rootroot00000000000000INTEL_PP_G7B = \ avs.g7b \ dndi.g7b \ nv12_dn_nv12.g7b \ pa_to_pl2.g7b \ pa_to_pl3.g7b \ pa_to_pa.g7b \ pl2_to_pa.g7b \ pl2_to_pl2.g7b \ pl2_to_pl3.g7b \ pl2_to_rgbx.g7b \ pl3_to_pa.g7b \ pl3_to_pl2.g7b \ pl3_to_pl3.g7b \ rgbx_to_nv12.g7b \ $(NULL) INTEL_PP_G4A = \ DI_Core.g4a \ DI_Save_NV12_16x4.g4a \ DI_Save_PA_16x4.g4a \ EOT.g4a \ NV12_DI_NV12.g4a \ NV12_DNDI_422CP.g4a \ NV12_DNDI_PA.g4a \ NV12_DNUV_NV12.g4a \ NV12_DN_422CP.g4a \ NV12_DN_NV12.g4a \ PA_AVS_Buf_0.g4a \ PA_AVS_Buf_1.g4a \ PA_AVS_Buf_2.g4a \ PA_AVS_Buf_3.g4a \ PA_DI_422CP.g4a \ PA_DI_PA.g4a \ PA_DNDI_422CP.g4a \ PA_DNDI_PA.g4a \ PA_DNUV_PA.g4a \ PA_DN_422CP.g4a \ PA_DN_PA.g4a \ PL2_AVS_Buf_0.g4a \ PL2_AVS_Buf_1.g4a \ PL2_AVS_Buf_2.g4a \ PL2_AVS_Buf_3.g4a \ PL3_AVS_Buf_0.g4a \ PL3_AVS_Buf_1.g4a \ PL3_AVS_Buf_2.g4a \ PL3_AVS_Buf_3.g4a \ PL3_DNDI_422CP.g4a \ PL3_DNDI_PA.g4a \ PL3_DNUV_PL3.g4a \ PL3_DN_422CP.g4a \ PL3_DN_PL3.g4a \ PL_DI_422CP.g4a \ PL_DI_PA.g4a \ RGB_to_YUV.g4a \ Save_AVS_PA.g4a \ Save_AVS_PL3.g4a \ Save_AVS_NV12.g4a \ Save_AVS_RGB.g4a \ Save_AVS_RGBX.g4a \ Set_AVS_Buf_0123_BGRA.g4a \ Set_AVS_Buf_0123_PL2.g4a \ Set_AVS_Buf_0123_PL3.g4a \ Set_AVS_Buf_0123_VUYA.g4a \ Set_AVS_Buf_0123_VYUA.g4a \ Set_Layer_0.g4a \ VP_Setup.g4a \ YUV_to_RGB.g4a \ $(NULL) INTEL_PP_ASM = $(INTEL_PP_G7B:%.g7b=%.asm) INTEL_PP_GEN7_ASM = $(INTEL_PP_G7B:%.g7b=%.g7s) INTEL_PP_G75B = $(INTEL_PP_G7B:%.g7b=%.g75b) TARGETS = if HAVE_GEN4ASM TARGETS += $(INTEL_PP_G7B) $(INTEL_PP_G75B) endif all-local: $(TARGETS) SUFFIXES = .g7b .g7s .asm $(INTEL_PP_GEN7_ASM): $(INTEL_PP_ASM) $(INTEL_PP_G4A) .asm.g7s: $(AM_V_GEN)cpp $< > _pp0.$@; \ ../../gpp.py _pp0.$@ $@; \ rm _pp0.$@ .g7s.g7b: $(AM_V_GEN)intel-gen4asm -a -o $@ -g 7 $< .g7s.g75b: $(AM_V_GEN)intel-gen4asm -a -o $@ -g 7.5 $< CLEANFILES = $(INTEL_PP_GEN7_ASM) EXTRA_DIST = \ $(INTEL_PP_ASM) \ $(INTEL_PP_G4A) \ $(INTEL_PP_G75B) \ $(INTEL_PP_G7B) \ $(NULL) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/post_processing/gen7/NV12_DI_NV12.g4a000066400000000000000000000332401231401140700246200ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 57 // Total instruction count // 1 // Total kernel count .kernel NV12_DI_NV12 .code // FileName: DI.asm // Author: Vivek Kumar // Description: Tasks for DI only case (16x4 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x4AE8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(9,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DI_STMM_Save.asm // Author: Vivek Kumar // Description: Saves DI STMM Data to statistics surface in case of DI enabled (for 16x4 block) // Write STMM to memory mov (8) mudMSGHDR_STMM(0)<1> r0.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udDNDI_RESP(8,0) // Move STMM to MRF shr (1) mudMSGHDR_STMM(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin / 2 mov (1) mudMSGHDR_STMM(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_STMM(0,2)<1> 0x30007:ud { NoDDChk } // block width and height (8x4) send (8) null<1>:d r20 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x20007:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | MCNT | FCNT | TCNT | X | X | X | X | //---------------------------------------------------- //| DcTpT | SVCM | DcBpT | DcTpB | //---------------------------------------------------- //| SHCM | STAD | DcTcB | DcBpB | //---------------------------------------------------- mov (1) mudMSGHDR_ENC_STATS(1,0)<1> udDNDI_RESP(9,1)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,3)<2> udDNDI_RESP(9,3)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,2)<2> udDNDI_RESP(9,5)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DI_Save_NV12_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in Packed format // add (4) a0.4<1>:uw r2.28<4;4,1>:ub 608:w // Initial Y,U,V offset in YUV422 block; it starts at m20 mov (8) r28.0<1>:ud r0.0<8;8,1>:ud mov (1) r28.0<1>:d r7.0<0;1,0>:w { NoDDClr } // H. block origin need to be doubled mov (1) r28.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) r28.2<1>:ud 0x3000F:ud { NoDDChk } // Block width and height (32x8) //prepare the message headers mov (8) r18.0<1>:ud r28<8;8,1>:ud mov (8) r23.0<1>:ud r28<8;8,1>:ud //Bottom field Y mov (8) mudMSGHDR_DI_OUT1(1)<1> udDNDI_RESP(0,0) mov (8) mudMSGHDR_DI_OUT1(2)<1> udDNDI_RESP(0,8) // Top field Y mov (8) mudMSGHDR_DI_OUT2(1)<1> udDNDI_RESP(4,0) mov (8) mudMSGHDR_DI_OUT2(2)<1> udDNDI_RESP(4,8) //Change origin to U/V block asr (1) r28.1<1>:d r28.1<0;1,0>:d 1:w { NoDDClr } // U/V block origin should be half of Y's mov (1) r28.2<1>:ud 0x1000F:ud { NoDDChk } // Block width and height (16x2) // Bottom field U/V mov (16) r22.0<2>:ub ubDNDI_RESP(2, 1)<32;8,2> { NoDDClr } mov (16) r22.1<2>:ub ubDNDI_RESP(2, 0)<32;8,2> { NoDDChk } // Top field U/V mov (16) r27.0<2>:ub ubDNDI_RESP(6, 1)<32;8,2> { NoDDClr } mov (16) r27.1<2>:ub ubDNDI_RESP(6, 0)<32;8,2> { NoDDChk } //copy message desrcptor to the message header mov (8) r21<1>:ud r28<8;8,1>:ud mov (8) r26<1>:ud r28<8;8,1>:ud //Send out Y component on previous frame to surface send (8) null<1>:d r18 0x5 0x60A801B:ud //Send out Y component on current frame to surface send (8) null<1>:d r23 0x5 0x60A801E:ud //Send out U/V component on previous frame to surface send (8) null<1>:d r21 0x5 0x40A801C:ud //Send out U/V component on current frame to surface send (8) null<1>:d r26 0x5 0x40A801F:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/NV12_DNDI_422CP.g4a000066400000000000000000000571021231401140700251110ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 116 // Total instruction count // 1 // Total kernel count .kernel NV12_DNDI_422CP .code // FileName: DNDI_PL_Core.asm // Author: Tatiya, Rupesh // FileName: DNDI_Core.asm // Author: Vivek Kumar // Description: Tasks for DN+DI case (16x4 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x4BE8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(9,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DI_STMM_Save.asm // Author: Vivek Kumar // Description: Saves DI STMM Data to statistics surface in case of DI enabled (for 16x4 block) // Write STMM to memory mov (8) mudMSGHDR_STMM(0)<1> r0.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udDNDI_RESP(8,0) // Move STMM to MRF shr (1) mudMSGHDR_STMM(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin / 2 mov (1) mudMSGHDR_STMM(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_STMM(0,2)<1> 0x30007:ud { NoDDChk } // block width and height (8x4) send (8) null<1>:d r20 0x5 0x40A8021:ud // FileName: DN_Hist_Save.asm // Author: Vivek Kumar // Description: Saves DN history data to statistics surface // Write denoise history to memory mov (8) r27<1>:ud r0.0<8;8,1>:ud // message header mov (1) mudMSGHDR_HIST(1)<1> udDNDI_RESP(9,0)<0;1,0> // Move denoise history to MRF (4x1) shr (2) r27.0<1>:ud r7.0<2;2,1>:w 2:w // X,Y origin / 4 add (1) r27.0<1>:ud r27.0<0;1,0>:ud r1.12<0;1,0>:uw { NoDDClr } // Add pitch to X origin mov (1) r27.2<1>:ud 0x3:ud { NoDDChk } // block width and height mov (8) mudMSGHDR_HIST(0)<1> r27.0<8;8,1>:ud send (8) null<1>:d r22 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x20007:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | MCNT | FCNT | TCNT | X | X | X | X | //---------------------------------------------------- //| DcTpT | SVCM | DcBpT | DcTpB | //---------------------------------------------------- //| SHCM | STAD | DcTcB | DcBpB | //---------------------------------------------------- mov (1) mudMSGHDR_ENC_STATS(1,0)<1> udDNDI_RESP(9,1)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,3)<2> udDNDI_RESP(9,3)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,2)<2> udDNDI_RESP(9,5)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DN_Load_UV_NV12_16x4.asm // Author: Vivek Kumar // Description: Read UV for 16x4 block through DATAPORT // FileName: UVCopy_Load_16x4.asm // Author: Vivek Kumar // Description: Read UV for 16x4 block through DATAPORT add (2) r27.0<1>:d r7.0<2;2,1>:w r4.4<2;2,1>:w // Source Y Block origin asr (1) r27.1<1>:d r27.1<0;1,0>:d 1:w { NoDDClr } // U/V block origin should be half of Y's mov (1) r27.2<1>:ud 0x1000F:ud { NoDDChk } // U/V block width and height (8x4) mov (8) mudMSGHDR_UVCOPY(0)<1> r27.0<8;8,1>:ud send (8) udDNDI_UV_RESP(0)<1> r36 0x4 0x2190001:ud // FileName: DN_Save_Y_16x4.asm // Author: Vivek Kumar // Description: Save one 16x4 blocks of Y channel of DN output for reference // check top/bottom field first cmp.e.f0.0 (1) null<1>:w r1.28<0;1,0>:ub 1:w mov (8) mudMSGHDR_DN_OUT(0)<1> r0<8;8,1>:ud // message header mov (2) mdMSGHDR_DN_OUT(0,0)<1> r7.0<2;2,1>:w { NoDDClr } // X origin * 2 (422 output) mov (1) mudMSGHDR_DN_OUT(0,2)<1> 0x3000F:ud { NoDDChk } // block width and height (32x8) (f0.0) jmpi (1) TOP_FIELD_FIRST BOTTOM_FIELD_FIRST: mov (4) mudMSGHDR_DN_OUT(1,0)<1> udDNDI_RESP(10,0)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(1,4)<1> udDNDI_RESP(4,4)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) mov (4) mudMSGHDR_DN_OUT(2,0)<1> udDNDI_RESP(10,4)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(2,4)<1> udDNDI_RESP(5,4)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) jmpi (1) SAVE_DN_CURR TOP_FIELD_FIRST: mov (4) mudMSGHDR_DN_OUT(1,0)<1> udDNDI_RESP(4,0)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(1,4)<1> udDNDI_RESP(10,0)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) mov (4) mudMSGHDR_DN_OUT(2,0)<1> udDNDI_RESP(5,0)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(2,4)<1> udDNDI_RESP(10,4)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) SAVE_DN_CURR: //send out data through data port send (8) null<1>:d r31.0 0x5 0x60A8018:ud // FileName: DI_Save_422CP_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in 422 format to Color Pipe (IECP) .declare mubMSGHDR_DI_OUT1_1 Base=r18.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT1_2 Base=r21.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT2_1 Base=r24.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT2_2 Base=r27.0 ElementSize=1 Type=ub mov (8) r27.0<1>:ud r0.0<8;8,1>:ud shl (1) r27.0<1>:ud r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be doubled mov (1) r27.1<1>:ud r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) r27.2<1>:ud 0x3000F:ud { NoDDClr, NoDDChk } // Block width and height (16x8) //M0.3 - 0 - CP Enable, 1 - Area of Interest, 3:2 Message Format(TBD), 4:3 - Ignored, 31:5 CP state pointer //Compose area-of-interest bit + color pipe state pointer or (1) r27.3<1>:ud r2.4<0;1,0>:ud r7.26<0;1,0>:b { NoDDChk } //prepare the message headers mov (8) r18.0<1>:ud r27<8;8,1>:ud mov (8) r24.0<1>:ud r27<8;8,1>:ud // Pack 2nd field Y; First 8x4 block mov (8) mubMSGHDR_DI_OUT1_1(1)<2> ubDNDI_RESP(0,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(1,16)<2> ubDNDI_RESP(0,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(2)<2> ubDNDI_RESP(0,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(2,16)<2> ubDNDI_RESP(0,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 2nd field U, V; First 8x4 block mov (4) mubMSGHDR_DI_OUT1_1(1,1)<4> ubDNDI_RESP(2,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,17)<4> ubDNDI_RESP(2,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,3)<4> ubDNDI_RESP(2,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,19)<4> ubDNDI_RESP(2,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,1)<4> ubDNDI_RESP(2,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,17)<4> ubDNDI_RESP(2,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,3)<4> ubDNDI_RESP(2,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,19)<4> ubDNDI_RESP(2,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Pack 2nd field Y; Second 8x4 block mov (8) r21.0<1>:ud r18.0<8;8,1>:ud add (1) r21.0<1>:ud r21.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DI_OUT1_2(1)<2> ubDNDI_RESP(0,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(1,16)<2> ubDNDI_RESP(0,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(2)<2> ubDNDI_RESP(0,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(2,16)<2> ubDNDI_RESP(0,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 2nd field U, V; Second 8x4 block mov (4) mubMSGHDR_DI_OUT1_2(1,1)<4> ubDNDI_RESP(2,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,17)<4> ubDNDI_RESP(2,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,3)<4> ubDNDI_RESP(2,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,19)<4> ubDNDI_RESP(2,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,1)<4> ubDNDI_RESP(2,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,17)<4> ubDNDI_RESP(2,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,3)<4> ubDNDI_RESP(2,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,19)<4> ubDNDI_RESP(2,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization send (8) null<1>:d r18.0 0x5 0x60A801B:ud send (8) null<1>:d r21.0 0x5 0x60A801B:ud // Pack 1st field Y; 1st 8x4 block mov (8) mubMSGHDR_DI_OUT2_1(1)<2> ubDNDI_RESP(4,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(1,16)<2> ubDNDI_RESP(4,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(2)<2> ubDNDI_RESP(4,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(2,16)<2> ubDNDI_RESP(4,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 1st field U,V; 1st 8x4 block mov (4) mubMSGHDR_DI_OUT2_1(1,1)<4> ubDNDI_RESP(6,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,17)<4> ubDNDI_RESP(6,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,3)<4> ubDNDI_RESP(6,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,19)<4> ubDNDI_RESP(6,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,1)<4> ubDNDI_RESP(6,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,17)<4> ubDNDI_RESP(6,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,3)<4> ubDNDI_RESP(6,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,19)<4> ubDNDI_RESP(6,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Pack 1st field Y; 2nd 8x4 block mov (8) r27.0<1>:ud r24.0<8;8,1>:ud add (1) r27.0<1>:ud r27.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DI_OUT2_2(1)<2> ubDNDI_RESP(4,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(1,16)<2> ubDNDI_RESP(4,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(2)<2> ubDNDI_RESP(4,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(2,16)<2> ubDNDI_RESP(4,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 1st field U, V; 2nd 8x4 block mov (4) mubMSGHDR_DI_OUT2_2(1,1)<4> ubDNDI_RESP(6,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,17)<4> ubDNDI_RESP(6,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,3)<4> ubDNDI_RESP(6,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,19)<4> ubDNDI_RESP(6,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,1)<4> ubDNDI_RESP(6,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,17)<4> ubDNDI_RESP(6,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,3)<4> ubDNDI_RESP(6,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,19)<4> ubDNDI_RESP(6,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization send (8) null<1>:d r24.0 0x5 0x60A801E:ud send (8) null<1>:d r27.0 0x5 0x60A801E:ud // FileName: DN_Save_UV_NV12_16x4.asm // Author: Vivek Kumar // Description: Save UV for 16x4 block through DATAPORT // FileName: UVCopy_Save_16x4.asm // Author: Vivek Kumar // Description: Save UV for 16x4 block through DATAPORT //Reuse the header from Load component mov (8) mudMSGHDR_UVCOPY(1)<1> udDNDI_UV_RESP(0)<8;8,1> send (8) null<1>:d r36 0x5 0x40A8019:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/NV12_DNDI_PA.g4a000066400000000000000000000443571231401140700246670ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 86 // Total instruction count // 1 // Total kernel count .kernel NV12_DNDI_PA .code // FileName: DNDI_PL_Core.asm // Author: Tatiya, Rupesh // FileName: DNDI_Core.asm // Author: Vivek Kumar // Description: Tasks for DN+DI case (16x4 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x4BE8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(9,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DI_STMM_Save.asm // Author: Vivek Kumar // Description: Saves DI STMM Data to statistics surface in case of DI enabled (for 16x4 block) // Write STMM to memory mov (8) mudMSGHDR_STMM(0)<1> r0.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udDNDI_RESP(8,0) // Move STMM to MRF shr (1) mudMSGHDR_STMM(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin / 2 mov (1) mudMSGHDR_STMM(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_STMM(0,2)<1> 0x30007:ud { NoDDChk } // block width and height (8x4) send (8) null<1>:d r20 0x5 0x40A8021:ud // FileName: DN_Hist_Save.asm // Author: Vivek Kumar // Description: Saves DN history data to statistics surface // Write denoise history to memory mov (8) r27<1>:ud r0.0<8;8,1>:ud // message header mov (1) mudMSGHDR_HIST(1)<1> udDNDI_RESP(9,0)<0;1,0> // Move denoise history to MRF (4x1) shr (2) r27.0<1>:ud r7.0<2;2,1>:w 2:w // X,Y origin / 4 add (1) r27.0<1>:ud r27.0<0;1,0>:ud r1.12<0;1,0>:uw { NoDDClr } // Add pitch to X origin mov (1) r27.2<1>:ud 0x3:ud { NoDDChk } // block width and height mov (8) mudMSGHDR_HIST(0)<1> r27.0<8;8,1>:ud send (8) null<1>:d r22 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x20007:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | MCNT | FCNT | TCNT | X | X | X | X | //---------------------------------------------------- //| DcTpT | SVCM | DcBpT | DcTpB | //---------------------------------------------------- //| SHCM | STAD | DcTcB | DcBpB | //---------------------------------------------------- mov (1) mudMSGHDR_ENC_STATS(1,0)<1> udDNDI_RESP(9,1)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,3)<2> udDNDI_RESP(9,3)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,2)<2> udDNDI_RESP(9,5)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DN_Load_UV_NV12_16x4.asm // Author: Vivek Kumar // Description: Read UV for 16x4 block through DATAPORT // FileName: UVCopy_Load_16x4.asm // Author: Vivek Kumar // Description: Read UV for 16x4 block through DATAPORT add (2) r27.0<1>:d r7.0<2;2,1>:w r4.4<2;2,1>:w // Source Y Block origin asr (1) r27.1<1>:d r27.1<0;1,0>:d 1:w { NoDDClr } // U/V block origin should be half of Y's mov (1) r27.2<1>:ud 0x1000F:ud { NoDDChk } // U/V block width and height (8x4) mov (8) mudMSGHDR_UVCOPY(0)<1> r27.0<8;8,1>:ud send (8) udDNDI_UV_RESP(0)<1> r36 0x4 0x2190001:ud // FileName: DN_Save_Y_16x4.asm // Author: Vivek Kumar // Description: Save one 16x4 blocks of Y channel of DN output for reference // check top/bottom field first cmp.e.f0.0 (1) null<1>:w r1.28<0;1,0>:ub 1:w mov (8) mudMSGHDR_DN_OUT(0)<1> r0<8;8,1>:ud // message header mov (2) mdMSGHDR_DN_OUT(0,0)<1> r7.0<2;2,1>:w { NoDDClr } // X origin * 2 (422 output) mov (1) mudMSGHDR_DN_OUT(0,2)<1> 0x3000F:ud { NoDDChk } // block width and height (32x8) (f0.0) jmpi (1) TOP_FIELD_FIRST BOTTOM_FIELD_FIRST: mov (4) mudMSGHDR_DN_OUT(1,0)<1> udDNDI_RESP(10,0)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(1,4)<1> udDNDI_RESP(4,4)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) mov (4) mudMSGHDR_DN_OUT(2,0)<1> udDNDI_RESP(10,4)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(2,4)<1> udDNDI_RESP(5,4)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) jmpi (1) SAVE_DN_CURR TOP_FIELD_FIRST: mov (4) mudMSGHDR_DN_OUT(1,0)<1> udDNDI_RESP(4,0)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(1,4)<1> udDNDI_RESP(10,0)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) mov (4) mudMSGHDR_DN_OUT(2,0)<1> udDNDI_RESP(5,0)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(2,4)<1> udDNDI_RESP(10,4)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) SAVE_DN_CURR: //send out data through data port send (8) null<1>:d r31.0 0x5 0x60A8018:ud // FileName: DI_Save_PA_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in Packed format add (4) a0.4<1>:uw r2.28<4;4,1>:ub 608:w // Initial Y,U,V offset in YUV422 block; it starts at m20 mov (8) r27.0<1>:ud r0.0<8;8,1>:ud shl (1) r27.0<1>:d r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be doubled mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) r27.2<1>:ud 0x3001F:ud { NoDDChk } // Block width and height (32x8) //prepare the message headers mov (8) r18.0<1>:ud r27<8;8,1>:ud mov (8) r23.0<1>:ud r27<8;8,1>:ud // Pack 2nd field Y mov (16) r[a0.4, 0]<2> ubDNDI_RESP(0,0) { NoDDClr } mov (16) r[a0.4, 32]<2> ubDNDI_RESP(0,16) { NoDDClr } mov (16) r[a0.4, 64]<2> ubDNDI_RESP(0,32) { NoDDClr } mov (16) r[a0.4, 96]<2> ubDNDI_RESP(0,48) { NoDDClr } // Pack 2nd field U mov (8) r[a0.5, 0]<4> ubDNDI_RESP(2,1)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 32]<4> ubDNDI_RESP(2,17)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 64]<4> ubDNDI_RESP(2,33)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 96]<4> ubDNDI_RESP(2,49)<16;8,2> { NoDDClr, NoDDChk } //U pixels // Pack 2nd field V mov (8) r[a0.6, 0]<4> ubDNDI_RESP(2,0)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 32]<4> ubDNDI_RESP(2,16)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 64]<4> ubDNDI_RESP(2,32)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 96]<4> ubDNDI_RESP(2,48)<16;8,2> { NoDDChk } //Vpixels // Pack 1st field Y mov (16) r[a0.4, 160]<2> ubDNDI_RESP(4,0) { NoDDClr } mov (16) r[a0.4, 192]<2> ubDNDI_RESP(4,16) { NoDDClr } mov (16) r[a0.4, 224]<2> ubDNDI_RESP(4,32) { NoDDClr } mov (16) r[a0.4, 256]<2> ubDNDI_RESP(4,48) { NoDDClr } // Pack 1st field U mov (8) r[a0.5, 160]<4> ubDNDI_RESP(6,1)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 192]<4> ubDNDI_RESP(6,17)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 224]<4> ubDNDI_RESP(6,33)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 256]<4> ubDNDI_RESP(6,49)<16;8,2> { NoDDClr, NoDDChk } //U pixels // Pack 1st field V mov (8) r[a0.6, 160]<4> ubDNDI_RESP(6,0)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 192]<4> ubDNDI_RESP(6,16)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 224]<4> ubDNDI_RESP(6,32)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 256]<4> ubDNDI_RESP(6,48)<16;8,2> { NoDDChk } //Vpixels //save the previous frame send (8) null<1>:d r18.0 0x5 0xA0A801B:ud //save the current frame send (8) null<1>:d r23.0 0x5 0xA0A801E:ud // FileName: DN_Save_UV_NV12_16x4.asm // Author: Vivek Kumar // Description: Save UV for 16x4 block through DATAPORT // FileName: UVCopy_Save_16x4.asm // Author: Vivek Kumar // Description: Save UV for 16x4 block through DATAPORT //Reuse the header from Load component mov (8) mudMSGHDR_UVCOPY(1)<1> udDNDI_UV_RESP(0)<8;8,1> send (8) null<1>:d r36 0x5 0x40A8019:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/NV12_DNUV_NV12.g4a000066400000000000000000003330121231401140700251000ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 1153 // Total instruction count // 1 // Total kernel count .kernel NV12_DNUV_NV12 .code //Module : DN_UV_Setup //Author : Tatiya, Rupesh //Description : Initial Set-up for DN_UV // Module name : ChromaDenoise.inc // Author : Tatiya, Rupesh // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Interface: //Static Parameters: //r1 //====================================================== //Interface for serpent mode Chroma Denoise, added by Le //====================================================== //r1 //noise history thresholds (low and high) //temporal difference thresholds (high and low) //noise history thresholds (low and high) //#define ubNoiseHistMaxHigh r1.22 //#define ubNoiseHistMaxLow r1.23 //#define ubNoiseHistDeltaHigh r1.24 //#define ubNoiseHistDeltaLow r1.25 //Gaussian thresholds //temporal difference thresholds (default) //r2 //history thresholds (default) //denoise factor (0-63) //====================== Binding table (Explicit To DNUV)========================================= //Used by DN_UV kernels //Pointer to Current Frame UV //r1-r6 //CURBE GRFs used as TEMP : Used for max computation and storing max temporarily. : r1-r6 .declare ubCURBE_TEMP Base=r1.0 ElementSize=1 Type=ub .declare uwCURBE_TEMP Base=r1.0 ElementSize=2 Type=uw .declare wCURBE_TEMP Base=r1.0 ElementSize=2 Type=w .declare fCURBE_TEMP Base=r1.0 ElementSize=4 Type=f .declare udCURBE_TEMP Base=r1.0 ElementSize=4 Type=ud .declare uwMAX_ABS_DIFF Base=r5.0 ElementSize=2 Type=uw //r1 //r3 //r4 //r7 //All of the following has to defined in Same GRF for optimal performance. //r8-24 //Previous Frame UV .declare udPREV_UV Base=r8.0 ElementSize=4 Type=ud .declare ubPREV_UV Base=r8.0 ElementSize=1 Type=ub //r25-48 //TEMP Space for any Usage. //========================================================================= //Definations and declarations for serpent mode Chroma Denoise, added by Le //========================================================================= .declare udGNE_UV Base=r24.0 ElementSize=4 Type=ud .declare fGNE_UV Base=r24.0 ElementSize=4 Type=f .declare ubGNE_UV Base=r24.0 ElementSize=1 Type=ub .declare udMSGHDR_BNE_SERP Base=r25.0 ElementSize=4 Type=ud .declare udMSGSRC_BNE_SERP Base=r26.0 ElementSize=4 Type=ud .declare ubDN_UV_Thresholds Base=r26.0 ElementSize=1 Type=ub .declare ubDN_UV_Thresholds_Temp Base=r27.0 ElementSize=1 Type=ub .declare udDN_UV_Thresholds Base=r26.0 ElementSize=4 Type=ud .declare udDN_UV_Thresholds_Temp Base=r27.0 ElementSize=4 Type=ud .declare fDN_UV_Thresholds Base=r26.0 ElementSize=4 Type=f .declare fDN_UV_Thresholds_Temp Base=r27.0 ElementSize=4 Type=f //==================================================================================== //TEMP23: To hold V data for PL3 surfaces .declare udCURR_V_TEMP Base=r25.0 ElementSize=4 Type=ud .declare ubCURR_V_TEMP Base=r25.0 ElementSize=1 Type=ub //GRFs to calculate Median: r25-r42 .declare ubMEDIAN_TEMP Base=r25.0 ElementSize=1 Type=ub //18 GRFs to hold difference : r25-r42 .declare wDIFF Base=r25.0 ElementSize=2 Type=w .declare uwDIFF Base=r25.0 ElementSize=2 Type=uw //Temporal Diff .declare wDIFF_TEMPORAL Base=r25.0 ElementSize=2 Type=w .declare ubDIFF_TEMPORAL Base=r25.0 ElementSize=1 Type=ub //4 GRFs to hold Sobel Value : r43-46 .declare wSOBEL_X Base=r43.0 ElementSize=2 Type=w .declare uwSOBEL Base=r43.0 ElementSize=2 Type=uw //2 GRFs to hold SOAD temporarily: r47-48 .declare uwSOAD Base=r47.0 ElementSize=2 Type=uw //Temp GRFs to hold extra YUYV pixels: r43-r48 .declare ubTEMP5 Base=r43.0 ElementSize=1 Type=ub //Temp GRFs in Median Calculation: r47-r48 .declare ubTEMP1 Base=r47.0 ElementSize=1 Type=ub .declare uwTEMP0 Base=r48.0 ElementSize=2 Type=uw .declare ubTEMP0 Base=r48.0 ElementSize=1 Type=ub //Temp Space to store Median : r49-50 .declare ubMEDIAN Base=r49.0 ElementSize=1 Type=ub //r49 //r50 //Message Source //r51 //DN_UV History Surface .declare udHIST_UV Base=r51.0 ElementSize=4 Type=ud .declare ubHIST_UV Base=r51.0 ElementSize=1 Type=ub //r52 - r91 //r52 //Current Frame UV .declare udCURR_UV Base=r52.0 ElementSize=4 Type=ud .declare ubCURR_UV Base=r52.0 ElementSize=1 Type=ub //r54 //CURBE COPY //r55 .declare uwSOAD_MIN_8x4 Base=r56.0 ElementSize=2 Type=uw //r61 //r62 //History Surface Temp Origin //r63 //Current Frame Y Temp Origin //BNE Surface Origin //r70 .declare uwDIFF_TEMPORAL_SUM4x4 Base=r70.0 ElementSize=2 Type=uw //4 GRFs //r74-91 : For Saving Dest UV (PL2/PL3) .declare ubMSGPAYLOAD_UV0 Base=r75.0 ElementSize=1 Type=ub .declare ubMSGPAYLOAD_U Base=r75.0 ElementSize=1 Type=ub .declare ubMSGPAYLOAD_UV1 Base=r84.0 ElementSize=1 Type=ub .declare ubMSGPAYLOAD_V Base=r84.0 ElementSize=1 Type=ub //r90 .declare uwDIFF_TEMPORAL_SUM4x4_FINAL Base=r90.0 ElementSize=2 Type=uw //2 GRFs //r92-127 //Current Frame Y //r92 .declare uwDIFF_TEMPORAL_SUM4x4_TEMP_0 Base=r92 ElementSize=2 Type=uw //r101 .declare uwDIFF_TEMPORAL_SUM4x4_TEMP_1 Base=r101 ElementSize=2 Type=uw //r110 .declare uwDIFF_TEMPORAL_SUM4x4_TEMP_2 Base=r110 ElementSize=2 Type=uw //r119 .declare uwDIFF_TEMPORAL_SUM4x4_TEMP_3 Base=r119 ElementSize=2 Type=uw .declare udCURR_Y0 Base=r93.0 ElementSize=4 Type=ud .declare ubCURR_Y0 Base=r93.0 ElementSize=1 Type=ub .declare udCURR_Y1 Base=r102.0 ElementSize=4 Type=ud .declare ubCURR_Y1 Base=r102.0 ElementSize=1 Type=ub .declare udCURR_Y2 Base=r111.0 ElementSize=4 Type=ud .declare ubCURR_Y2 Base=r111.0 ElementSize=1 Type=ub .declare udCURR_Y3 Base=r120.0 ElementSize=4 Type=ud .declare ubCURR_Y3 Base=r120.0 ElementSize=1 Type=ub //r92: To hold U data for PL3 surfaces .declare udCURR_U_TEMP Base=r92.0 ElementSize=4 Type=ud .declare ubCURR_U_TEMP Base=r92.0 ElementSize=1 Type=ub //r112: To hold U data for PL3 surfaces .declare udPREV_U_TEMP Base=r112.0 ElementSize=4 Type=ud .declare ubPREV_U_TEMP Base=r112.0 ElementSize=1 Type=ub //r120: To hold U data for PL3 surfaces .declare udPREV_V_TEMP Base=r120.0 ElementSize=4 Type=ud .declare ubPREV_V_TEMP Base=r120.0 ElementSize=1 Type=ub // Initialize message source with r0. mov (8) r50.0<1>:ud r0.0<8;8,1>:ud mov (8) r92.0<1>:ud r0.0<8;8,1>:ud mov (8) r101.0<1>:ud r0.0<8;8,1>:ud mov (8) r110.0<1>:ud r0.0<8;8,1>:ud mov (8) r119.0<1>:ud r0.0<8;8,1>:ud //Module Name : DN_UV_PL2_Load_Curr_Frame_UV //Author : Tatiya, Rupesh //Description : Loads Current Frame UV data for PL2 input. //Module name : DN_UV_Load_Curr_Frame_UV //Author : Tatiya, Rupesh //Description : Loads Current Frame (UV only). // We need 4 extra rows (2 per field) and 2 extra pixel (1 each side) for both U and V each. // The processing size is 16x16 U and V each. So we need : U size - 18x20, V size - 18x20, UV size - 36x20, YUYV size - 72x20. //36x20 interleaved UV block is partitioned as follows: // <------ 18 --------> <--------18 -------> // ----------------------------------------- // | 20x8 A !| 20x8 D ! // | (overlapped) !| (overlapped) ! // |-------------------!|------------------! // | 20x8 B !| 20x8 E ! // | (overlapped) !| (overlapped) ! // |-------------------!|------------------! // | 20x4 C !| 20x4 F ! // | (overlapped) !| (overlapped) ! // ----------------------------------------- // // Cordinates: (x-2, y-2), (x+14, y-2), (x-2, y+6), (x+14, y+6), (x-2, y+14), (x+14, y+14) //UV surface origin: (ORIX, ORIY/2) add (2) r7.4<1>:w r7.0<2;2,1>:w r4.4<2;2,1>:w { AccWrEn } // Source Block origin shr (1) r7.5<1>:w acc0.5<0;1,0>:w 1:w mov (2) acc0.0<1>:d r7.4<2;2,1>:w //A add (2) r50.0<1>:d acc0.0<2;2,1>:d -2:d { AccWrEn } mov (1) r50.2<1>:ud 0x70013:ud send (8) udCURR_UV(0)<1> r50 0x4 0x2890004:ud //B add (1) r50.1<1>:d acc0.1<0;1,0>:d 8:d send (8) udCURR_UV(8)<1> r50 0x4 0x2890004:ud //C add (1) r50.1<1>:d acc0.1<0;1,0>:d 16:d mov (1) r50.2<1>:ud 0x30013:ud send (8) udCURR_UV(16)<1> r50 0x4 0x2490004:ud //D add (1) r50.0<1>:d acc0.0<0;1,0>:d 16:d { AccWrEn } mov (1) r50.1<1>:d acc0.1<0;1,0>:d mov (1) r50.2<1>:ud 0x70013:ud send (8) udCURR_UV(20)<1> r50 0x4 0x2890004:ud //E add (1) r50.1<1>:d acc0.1<0;1,0>:d 8:d send (8) udCURR_UV(28)<1> r50 0x4 0x2890004:ud //F add (1) r50.1<1>:d acc0.1<0;1,0>:d 16:d mov (1) r50.2<1>:ud 0x30013:ud send (8) udCURR_UV(36)<1> r50 0x4 0x2490004:ud //History Origin, Current Y origin and BNE surface origin - all are in inline GRF. Use , . -rT. //Calculate Origin For History Surface: (ORIX/4, ORIY/8) mov (16) acc0.0<1>:w r7.0<0;2,1>:w shr (1) r7.2<1>:w acc0.2<0;1,0>:w 2:w shr (1) r7.3<1>:w acc0.3<0;1,0>:w 3:w //Calculate Origin For BNE Surface: (ORIX/8, ORIY/16) shr (1) r7.6<1>:w acc0.6<0;1,0>:w 3:w shr (1) r7.7<1>:w acc0.7<0;1,0>:w 4:w //Module Name : DN_UV_PL2_Load_Prev_Frame_UV //Author : Tatiya, Rupesh //Description : Loads Pevious Frame UV data for PL2 input. //Module Name : DN_UV_Load_Prev_Frame_UV //Author : Tatiya, Rupesh //Description : Loads Prev Frame (UV only). U size - 16x16, V size - 16x16, UV size - 32x16, YUYV size - 64x16. mov (2) r50.0<1>:d r7.4<2;2,1>:w { AccWrEn } // Source lock origin mov (1) r50.2<1>:ud 0xF000F:ud // U/V block width and height (16x16) send (8) udPREV_UV(0)<1> r50 0x4 0x2890001:ud add (1) r50.0<1>:ud acc0.0<0;1,0>:d 16:w // Add 16 to X origin send (8) udPREV_UV(8)<1> r50 0x4 0x2890001:ud //TODO - See if History loading can be combined with Prev Frame Load. - rT //Module name : DN_UV_Load_Hist_UV //Author : Tatiya, Rupesh //Description : Load DN History for UV denoise. 4x4 for each U & V. mov (2) r50.0<1>:d r7.2<2;2,1>:w mov (1) r50.2<1>:ud 0x30007:ud send (8) udHIST_UV(0)<1> r50 0x4 0x2190022:ud //Module Name : DN_UV_420_Load_Curr_Frame_Y //Author : Tatiya, Rupesh //Description : Load Curr Frame Y data for 420 Input //Module Name : DN_UV_Load_Curr_Frame_Y //Author : Tatiya, Rupesh //Description : Loads Y of Current frame. //For 16x16 U and 16x16 V for 420, we need to read 32x32 Y. mov (8) acc0.0<1>:ud r0.0<8;8,1>:ud mov (1) acc0.2<1>:ud 0xF000F:ud add (2) acc0.0<1>:ud r7.0<2;2,1>:w r4.4<2;2,1>:w mov (8) r92.0<1>:ud acc0.0<8;8,1>:ud mov (8) r101.0<1>:ud acc0.0<8;8,1>:ud mov (8) r110.0<1>:ud acc0.0<8;8,1>:ud mov (8) r119.0<1>:ud acc0.0<8;8,1>:ud add (1) r101.1<1>:d acc0.1<0;1,0>:d 16:d add (1) r110.0<1>:d acc0.0<0;1,0>:d 16:d add (2) r119.0<1>:d acc0.0<2;2,1>:d 16:d send (8) udCURR_Y0(0)<1> r92 0x4 0x2890003:ud send (8) udCURR_Y1(0)<1> r101 0x4 0x2890003:ud send (8) udCURR_Y2(0)<1> r110 0x4 0x2890003:ud send (8) udCURR_Y3(0)<1> r119 0x4 0x2890003:ud //Module Name : DN_UV_Noise_Detection_UV //Author : Tatiya, Rupesh //Description : Performs noise detection on 16x16 U and 16x16 V each. //Module Name : DN_UV_Move_CURBE_Inline_UV.asm //Author : Tatiya, Rupesh //Mov CURBE data to another space - so that it can be used as Temp Space --> r1 - r6 mov (4) r54.28<1>:ub r2.28<4;4,1>:ub //Dest. YUY2 offset mov (2) r54.5<1>:ud r4.0<4;2,2>:ud //Src YUY2 offset and Origin offset mov (4) r55.28<1>:ub r1.0<4;4,1>:ub mov (8) r61.20<1>:ub r1.4<8;8,1>:ub mov (4) r61.28<1>:ub r1.12<4;4,1>:ub //Move Inline Data to another space - so that it can be used as Temp Space --> r7 mov (4) r62.10<1>:w r7.0<4;4,1>:w mov (4) r63.10<1>:w r7.4<4;4,1>:w //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. mov (1) a0.0:uw 1664:uw mov (1) a0.1:uw 1816:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 1792:uw mov (1) a0.1:uw 1820:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 1920:uw mov (1) a0.1:uw 1848:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 2048:uw mov (1) a0.1:uw 1852:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. mov (1) a0.0:uw 2304:uw mov (1) a0.1:uw 1880:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 2432:uw mov (1) a0.1:uw 1884:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 2560:uw mov (1) a0.1:uw 1912:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 2688:uw mov (1) a0.1:uw 1916:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module : DN_UV_Noise_Reduction_UV //Author : Tatiya, Rupesh //Description : Performs Noise Reduction on 16x16 U and 16x16 V. //Tasks : 1. Update weight history // 2. Find if it block is motion block // 3. Compute Denoised Pixel. //History is 1+1 byte every 4x4 U and 4x4 V. cmp.l.f0.0 (16) null<1>:w ubHIST_UV(0,0)<16;16,1> r61.20<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w ubHIST_UV(0,0)<16;16,1> r61.22<0;2,1>:ub mov (16) uwCURBE_TEMP(0)<1> 0:w mov (16) uwCURBE_TEMP(1)<1> 0:w //Compute diff betn curr and prev. - First 16 lines // 8 lines here add (16) wDIFF_TEMPORAL(0)<1> ubCURR_UV(2,2)<16;16,1> -ubPREV_UV(0,0)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(1)<1> ubCURR_UV(3,2)<16;16,1> -ubPREV_UV(0,16)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(2)<1> ubCURR_UV(4,2)<16;16,1> -ubPREV_UV(0,32)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(3)<1> ubCURR_UV(5,2)<16;16,1> -ubPREV_UV(0,48)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(4)<1> ubCURR_UV(6,2)<16;16,1> -ubPREV_UV(0,64)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(5)<1> ubCURR_UV(7,2)<16;16,1> -ubPREV_UV(0,80)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(6)<1> ubCURR_UV(8,2)<16;16,1> -ubPREV_UV(0,96)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(7)<1> ubCURR_UV(9,2)<16;16,1> -ubPREV_UV(0,112)<16;16,1> //Diff UV interleaved //Update WT HIST (-f0.0) shr (16) uwCURBE_TEMP(0)<1> ubHIST_UV(0,0)<16;16,1> 1:w (f1.0) add (16) uwCURBE_TEMP(2)<1> ubHIST_UV(0,0)<16;16,1> r61.24<0;2,1>:ub (f0.0) mov (16) uwCURBE_TEMP(2)<1> r61.20<0;2,1>:ub (-f0.0.anyv) mov (16) uwCURBE_TEMP(2)<1> ubHIST_UV(0,0)<16;16,1> cmp.l.f0.0 (16) null<1>:w ubHIST_UV(0,16)<16;16,1> r61.20<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w ubHIST_UV(0,16)<16;16,1> r61.22<0;2,1>:ub //Compute diff betn curr and prev. - First 16 lines // 8 more lines here add (16) wDIFF_TEMPORAL(8)<1> ubCURR_UV(10,2)<16;16,1> -ubPREV_UV(0,128)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(9)<1> ubCURR_UV(11,2)<16;16,1> -ubPREV_UV(0,144)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(10)<1> ubCURR_UV(12,2)<16;16,1> -ubPREV_UV(0,160)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(11)<1> ubCURR_UV(13,2)<16;16,1> -ubPREV_UV(0,176)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(12)<1> ubCURR_UV(14,2)<16;16,1> -ubPREV_UV(0,192)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(13)<1> ubCURR_UV(15,2)<16;16,1> -ubPREV_UV(0,208)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(14)<1> ubCURR_UV(16,2)<16;16,1> -ubPREV_UV(0,224)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(15)<1> ubCURR_UV(17,2)<16;16,1> -ubPREV_UV(0,240)<16;16,1> //Diff UV interleaved (-f0.0) shr (16) uwCURBE_TEMP(1)<1> ubHIST_UV(0,16)<16;16,1> 1:w (f1.0) add (16) uwCURBE_TEMP(3)<1> ubHIST_UV(0,16)<16;16,1> r61.24<0;2,1>:ub (f0.0) mov (16) uwCURBE_TEMP(3)<1> r61.20<0;2,1>:ub (-f0.0.anyv) mov(16) uwCURBE_TEMP(3)<1> ubHIST_UV(0,16)<16;16,1> //16x16 to 16x4 - First 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(0)<16;16,1> (abs)wDIFF_TEMPORAL(1)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(2)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(0)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(3)<16;16,1> //16x16 to 16x4 - First 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(4)<16;16,1> (abs)wDIFF_TEMPORAL(5)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(6)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(1)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(7)<16;16,1> //16x16 to 16x4 - First 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(8)<16;16,1> (abs)wDIFF_TEMPORAL(9)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(10)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(2)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(11)<16;16,1> //16x16 to 16x4 - First 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(12)<16;16,1> (abs)wDIFF_TEMPORAL(13)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(14)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(3)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(15)<16;16,1> //Compute diff betn curr and prev. - Second 16 lines //13 lines. add (16) wDIFF_TEMPORAL(16)<1> ubCURR_UV(22,2)<16;16,1> -ubPREV_UV(8,0)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(17)<1> ubCURR_UV(23,2)<16;16,1> -ubPREV_UV(8,16)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(18)<1> ubCURR_UV(24,2)<16;16,1> -ubPREV_UV(8,32)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(19)<1> ubCURR_UV(25,2)<16;16,1> -ubPREV_UV(8,48)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(20)<1> ubCURR_UV(26,2)<16;16,1> -ubPREV_UV(8,64)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(21)<1> ubCURR_UV(27,2)<16;16,1> -ubPREV_UV(8,80)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(22)<1> ubCURR_UV(28,2)<16;16,1> -ubPREV_UV(8,96)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(23)<1> ubCURR_UV(29,2)<16;16,1> -ubPREV_UV(8,112)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(24)<1> ubCURR_UV(30,2)<16;16,1> -ubPREV_UV(8,128)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(25)<1> ubCURR_UV(31,2)<16;16,1> -ubPREV_UV(8,144)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(26)<1> ubCURR_UV(32,2)<16;16,1> -ubPREV_UV(8,160)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(27)<1> ubCURR_UV(33,2)<16;16,1> -ubPREV_UV(8,176)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(28)<1> ubCURR_UV(34,2)<16;16,1> -ubPREV_UV(8,192)<16;16,1> //Diff UV interleaved //3 more lines add (16) wCURBE_TEMP(4)<1> ubCURR_UV(35,2)<16;16,1> -ubPREV_UV(8,208)<16;16,1> //Diff UV interleaved add (16) wCURBE_TEMP(5)<1> ubCURR_UV(36,2)<16;16,1> -ubPREV_UV(8,224)<16;16,1> //Diff UV interleaved add (16) wCURBE_TEMP(6)<1> ubCURR_UV(37,2)<16;16,1> -ubPREV_UV(8,240)<16;16,1> //Diff UV interleaved //16x4 to 8x4 - First 16 lines add (16) uwDIFF_TEMPORAL_SUM4x4(0)<1> uwDIFF_TEMPORAL_SUM4x4(0,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(0,2)<4;2,1> add (16) uwDIFF_TEMPORAL_SUM4x4(1)<1> uwDIFF_TEMPORAL_SUM4x4(2,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(2,2)<4;2,1> //8x4 to 4x4 - First 16 lines add (16) uwDIFF_TEMPORAL_SUM4x4_FINAL(0)<1> uwDIFF_TEMPORAL_SUM4x4(0,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(0,2)<4;2,1> { AccWrEn } //16x16 to 16x4 - Second 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(16)<16;16,1> (abs)wDIFF_TEMPORAL(17)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(18)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(0)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(19)<16;16,1> //16x16 to 16x4 - Second 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(20)<16;16,1> (abs)wDIFF_TEMPORAL(21)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(22)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(1)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(23)<16;16,1> //16x16 to 16x4 - Second 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(24)<16;16,1> (abs)wDIFF_TEMPORAL(25)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(26)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(2)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(27)<16;16,1> //16x16 to 16x4 - Second 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(28)<16;16,1> (abs)wCURBE_TEMP(4)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wCURBE_TEMP(5)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(3)<1> acc0.0<16;16,1>:uw (abs)wCURBE_TEMP(6)<16;16,1> //Find if block is motion block - First 16 lines cmp.g.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_FINAL(0)<16;16,1> r61.26<0;2,1>:ub //Move TEMPORAL_SUM4x4 for SIMD16 use later. mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,0)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,2)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,4)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,6)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,8)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,10)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,12)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,14)<0;2,1> //Pick Appropriate Weight History Based on motion. - First 16 lines (-f0.0) mov (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(2)<16;16,1> //Actual DN - First 16 lines cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(0)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(0)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(2,2)<8;8,1> -uwCURBE_TEMP(0,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(2,10)<8;8,1> -uwCURBE_TEMP(0,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(2,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,0)<8;8,1> uwCURBE_TEMP(0,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,8)<8;8,1> uwCURBE_TEMP(0,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(0)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(0)<1> ubCURR_UV(2,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(0)<1> wDIFF_TEMPORAL(0)<16;16,1> ubCURR_UV(2,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(1)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(1)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(3,2)<8;8,1> -uwCURBE_TEMP(0,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(3,10)<8;8,1> -uwCURBE_TEMP(0,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(3,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,16)<8;8,1> uwCURBE_TEMP(0,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,24)<8;8,1> uwCURBE_TEMP(0,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(1)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(1)<1> ubCURR_UV(3,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(1)<1> wDIFF_TEMPORAL(1)<16;16,1> ubCURR_UV(3,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(2)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(2)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(4,2)<8;8,1> -uwCURBE_TEMP(0,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(4,10)<8;8,1> -uwCURBE_TEMP(0,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(4,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,32)<8;8,1> uwCURBE_TEMP(0,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,40)<8;8,1> uwCURBE_TEMP(0,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(2)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(2)<1> ubCURR_UV(4,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(2)<1> wDIFF_TEMPORAL(2)<16;16,1> ubCURR_UV(4,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(3)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(3)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(5,2)<8;8,1> -uwCURBE_TEMP(0,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(5,10)<8;8,1> -uwCURBE_TEMP(0,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(5,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,48)<8;8,1> uwCURBE_TEMP(0,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,56)<8;8,1> uwCURBE_TEMP(0,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(3)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(3)<1> ubCURR_UV(5,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(3)<1> wDIFF_TEMPORAL(3)<16;16,1> ubCURR_UV(5,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(4)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(4)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(6,2)<8;8,1> -uwCURBE_TEMP(0,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(6,10)<8;8,1> -uwCURBE_TEMP(0,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(6,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,64)<8;8,1> uwCURBE_TEMP(0,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,72)<8;8,1> uwCURBE_TEMP(0,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(4)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(4)<1> ubCURR_UV(6,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(4)<1> wDIFF_TEMPORAL(4)<16;16,1> ubCURR_UV(6,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(5)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(5)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(7,2)<8;8,1> -uwCURBE_TEMP(0,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(7,10)<8;8,1> -uwCURBE_TEMP(0,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(7,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,80)<8;8,1> uwCURBE_TEMP(0,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,88)<8;8,1> uwCURBE_TEMP(0,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(5)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(5)<1> ubCURR_UV(7,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(5)<1> wDIFF_TEMPORAL(5)<16;16,1> ubCURR_UV(7,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(6)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(6)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(8,2)<8;8,1> -uwCURBE_TEMP(0,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(8,10)<8;8,1> -uwCURBE_TEMP(0,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(8,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,96)<8;8,1> uwCURBE_TEMP(0,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,104)<8;8,1> uwCURBE_TEMP(0,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(6)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(6)<1> ubCURR_UV(8,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(6)<1> wDIFF_TEMPORAL(6)<16;16,1> ubCURR_UV(8,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(7)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(7)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(9,2)<8;8,1> -uwCURBE_TEMP(0,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(9,10)<8;8,1> -uwCURBE_TEMP(0,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(9,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,112)<8;8,1> uwCURBE_TEMP(0,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,120)<8;8,1> uwCURBE_TEMP(0,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(7)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(7)<1> ubCURR_UV(9,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(7)<1> wDIFF_TEMPORAL(7)<16;16,1> ubCURR_UV(9,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(8)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(8)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(10,2)<8;8,1> -uwCURBE_TEMP(0,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(10,10)<8;8,1> -uwCURBE_TEMP(0,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(10,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,128)<8;8,1> uwCURBE_TEMP(0,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,136)<8;8,1> uwCURBE_TEMP(0,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(8)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(8)<1> ubCURR_UV(10,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(8)<1> wDIFF_TEMPORAL(8)<16;16,1> ubCURR_UV(10,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(9)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(9)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(11,2)<8;8,1> -uwCURBE_TEMP(0,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(11,10)<8;8,1> -uwCURBE_TEMP(0,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(11,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,144)<8;8,1> uwCURBE_TEMP(0,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,152)<8;8,1> uwCURBE_TEMP(0,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(9)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(9)<1> ubCURR_UV(11,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(9)<1> wDIFF_TEMPORAL(9)<16;16,1> ubCURR_UV(11,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(10)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(10)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(12,2)<8;8,1> -uwCURBE_TEMP(0,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(12,10)<8;8,1> -uwCURBE_TEMP(0,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(12,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,160)<8;8,1> uwCURBE_TEMP(0,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,168)<8;8,1> uwCURBE_TEMP(0,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(10)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(10)<1> ubCURR_UV(12,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(10)<1> wDIFF_TEMPORAL(10)<16;16,1> ubCURR_UV(12,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(11)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(11)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(13,2)<8;8,1> -uwCURBE_TEMP(0,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(13,10)<8;8,1> -uwCURBE_TEMP(0,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(13,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,176)<8;8,1> uwCURBE_TEMP(0,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,184)<8;8,1> uwCURBE_TEMP(0,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(11)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(11)<1> ubCURR_UV(13,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(11)<1> wDIFF_TEMPORAL(11)<16;16,1> ubCURR_UV(13,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(12)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(12)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(14,2)<8;8,1> -uwCURBE_TEMP(0,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(14,10)<8;8,1> -uwCURBE_TEMP(0,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(14,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,192)<8;8,1> uwCURBE_TEMP(0,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,200)<8;8,1> uwCURBE_TEMP(0,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(12)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(12)<1> ubCURR_UV(14,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(12)<1> wDIFF_TEMPORAL(12)<16;16,1> ubCURR_UV(14,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(13)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(13)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(15,2)<8;8,1> -uwCURBE_TEMP(0,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(15,10)<8;8,1> -uwCURBE_TEMP(0,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(15,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,208)<8;8,1> uwCURBE_TEMP(0,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,216)<8;8,1> uwCURBE_TEMP(0,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(13)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(13)<1> ubCURR_UV(15,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(13)<1> wDIFF_TEMPORAL(13)<16;16,1> ubCURR_UV(15,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(14)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(14)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(16,2)<8;8,1> -uwCURBE_TEMP(0,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(16,10)<8;8,1> -uwCURBE_TEMP(0,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(16,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,224)<8;8,1> uwCURBE_TEMP(0,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,232)<8;8,1> uwCURBE_TEMP(0,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(14)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(14)<1> ubCURR_UV(16,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(14)<1> wDIFF_TEMPORAL(14)<16;16,1> ubCURR_UV(16,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(15)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(15)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(17,2)<8;8,1> -uwCURBE_TEMP(0,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(17,10)<8;8,1> -uwCURBE_TEMP(0,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(17,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,240)<8;8,1> uwCURBE_TEMP(0,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,248)<8;8,1> uwCURBE_TEMP(0,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(15)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(15)<1> ubCURR_UV(17,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(15)<1> wDIFF_TEMPORAL(15)<16;16,1> ubCURR_UV(17,2)<16;16,1> //16x4 to 8x4 - Second 16 lines add (16) uwDIFF_TEMPORAL_SUM4x4(0)<1> uwDIFF_TEMPORAL_SUM4x4(0,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(0,2)<4;2,1> add (16) uwDIFF_TEMPORAL_SUM4x4(1)<1> uwDIFF_TEMPORAL_SUM4x4(2,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(2,2)<4;2,1> //8x4 to 4x4 - Second 16 lines add (16) uwDIFF_TEMPORAL_SUM4x4_FINAL(1)<1> uwDIFF_TEMPORAL_SUM4x4(0,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(0,2)<4;2,1> { AccWrEn } //Find if block is motion block - Second 16 lines cmp.g.f1.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_FINAL(1)<16;16,1> r61.26<0;2,1>:ub //Move TEMPORAL_SUM4x4 for SIMD16 use later. mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,0)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,2)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,4)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,6)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,8)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,10)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,12)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,14)<0;2,1> //Pick Appropriate Weight History Based on motion. - Second 16 lines (-f1.0) mov (16) uwCURBE_TEMP(1)<1> uwCURBE_TEMP(3)<16;16,1> //Actual DN - Second 16 lines cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(16)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(16)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(22,2)<8;8,1> -uwCURBE_TEMP(1,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(22,10)<8;8,1> -uwCURBE_TEMP(1,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(22,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,0)<8;8,1> uwCURBE_TEMP(1,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,8)<8;8,1> uwCURBE_TEMP(1,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(16)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(16)<1> ubCURR_UV(22,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(16)<1> wDIFF_TEMPORAL(16)<16;16,1> ubCURR_UV(22,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(17)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(17)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(23,2)<8;8,1> -uwCURBE_TEMP(1,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(23,10)<8;8,1> -uwCURBE_TEMP(1,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(23,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,16)<8;8,1> uwCURBE_TEMP(1,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,24)<8;8,1> uwCURBE_TEMP(1,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(17)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(17)<1> ubCURR_UV(23,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(17)<1> wDIFF_TEMPORAL(17)<16;16,1> ubCURR_UV(23,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(18)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(18)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(24,2)<8;8,1> -uwCURBE_TEMP(1,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(24,10)<8;8,1> -uwCURBE_TEMP(1,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(24,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,32)<8;8,1> uwCURBE_TEMP(1,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,40)<8;8,1> uwCURBE_TEMP(1,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(18)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(18)<1> ubCURR_UV(24,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(18)<1> wDIFF_TEMPORAL(18)<16;16,1> ubCURR_UV(24,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(19)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(19)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(25,2)<8;8,1> -uwCURBE_TEMP(1,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(25,10)<8;8,1> -uwCURBE_TEMP(1,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(25,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,48)<8;8,1> uwCURBE_TEMP(1,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,56)<8;8,1> uwCURBE_TEMP(1,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(19)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(19)<1> ubCURR_UV(25,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(19)<1> wDIFF_TEMPORAL(19)<16;16,1> ubCURR_UV(25,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(20)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(20)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(26,2)<8;8,1> -uwCURBE_TEMP(1,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(26,10)<8;8,1> -uwCURBE_TEMP(1,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(26,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,64)<8;8,1> uwCURBE_TEMP(1,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,72)<8;8,1> uwCURBE_TEMP(1,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(20)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(20)<1> ubCURR_UV(26,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(20)<1> wDIFF_TEMPORAL(20)<16;16,1> ubCURR_UV(26,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(21)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(21)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(27,2)<8;8,1> -uwCURBE_TEMP(1,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(27,10)<8;8,1> -uwCURBE_TEMP(1,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(27,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,80)<8;8,1> uwCURBE_TEMP(1,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,88)<8;8,1> uwCURBE_TEMP(1,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(21)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(21)<1> ubCURR_UV(27,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(21)<1> wDIFF_TEMPORAL(21)<16;16,1> ubCURR_UV(27,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(22)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(22)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(28,2)<8;8,1> -uwCURBE_TEMP(1,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(28,10)<8;8,1> -uwCURBE_TEMP(1,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(28,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,96)<8;8,1> uwCURBE_TEMP(1,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,104)<8;8,1> uwCURBE_TEMP(1,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(22)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(22)<1> ubCURR_UV(28,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(22)<1> wDIFF_TEMPORAL(22)<16;16,1> ubCURR_UV(28,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(23)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(23)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(29,2)<8;8,1> -uwCURBE_TEMP(1,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(29,10)<8;8,1> -uwCURBE_TEMP(1,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(29,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,112)<8;8,1> uwCURBE_TEMP(1,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,120)<8;8,1> uwCURBE_TEMP(1,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(23)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(23)<1> ubCURR_UV(29,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(23)<1> wDIFF_TEMPORAL(23)<16;16,1> ubCURR_UV(29,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(24)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(24)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(30,2)<8;8,1> -uwCURBE_TEMP(1,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(30,10)<8;8,1> -uwCURBE_TEMP(1,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(30,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,128)<8;8,1> uwCURBE_TEMP(1,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,136)<8;8,1> uwCURBE_TEMP(1,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(24)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(24)<1> ubCURR_UV(30,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(24)<1> wDIFF_TEMPORAL(24)<16;16,1> ubCURR_UV(30,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(25)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(25)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(31,2)<8;8,1> -uwCURBE_TEMP(1,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(31,10)<8;8,1> -uwCURBE_TEMP(1,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(31,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,144)<8;8,1> uwCURBE_TEMP(1,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,152)<8;8,1> uwCURBE_TEMP(1,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(25)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(25)<1> ubCURR_UV(31,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(25)<1> wDIFF_TEMPORAL(25)<16;16,1> ubCURR_UV(31,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(26)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(26)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(32,2)<8;8,1> -uwCURBE_TEMP(1,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(32,10)<8;8,1> -uwCURBE_TEMP(1,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(32,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,160)<8;8,1> uwCURBE_TEMP(1,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,168)<8;8,1> uwCURBE_TEMP(1,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(26)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(26)<1> ubCURR_UV(32,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(26)<1> wDIFF_TEMPORAL(26)<16;16,1> ubCURR_UV(32,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(27)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(27)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(33,2)<8;8,1> -uwCURBE_TEMP(1,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(33,10)<8;8,1> -uwCURBE_TEMP(1,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(33,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,176)<8;8,1> uwCURBE_TEMP(1,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,184)<8;8,1> uwCURBE_TEMP(1,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(27)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(27)<1> ubCURR_UV(33,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(27)<1> wDIFF_TEMPORAL(27)<16;16,1> ubCURR_UV(33,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(28)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(28)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(34,2)<8;8,1> -uwCURBE_TEMP(1,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(34,10)<8;8,1> -uwCURBE_TEMP(1,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(34,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,192)<8;8,1> uwCURBE_TEMP(1,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,200)<8;8,1> uwCURBE_TEMP(1,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(28)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(28)<1> ubCURR_UV(34,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(28)<1> wDIFF_TEMPORAL(28)<16;16,1> ubCURR_UV(34,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wCURBE_TEMP(4)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wCURBE_TEMP(4)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(35,2)<8;8,1> -uwCURBE_TEMP(1,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(35,10)<8;8,1> -uwCURBE_TEMP(1,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(35,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,208)<8;8,1> uwCURBE_TEMP(1,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,216)<8;8,1> uwCURBE_TEMP(1,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wCURBE_TEMP(4)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wCURBE_TEMP(4)<1> ubCURR_UV(35,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wCURBE_TEMP(4)<1> wCURBE_TEMP(4)<16;16,1> ubCURR_UV(35,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wCURBE_TEMP(5)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wCURBE_TEMP(5)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(36,2)<8;8,1> -uwCURBE_TEMP(1,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(36,10)<8;8,1> -uwCURBE_TEMP(1,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(36,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,224)<8;8,1> uwCURBE_TEMP(1,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,232)<8;8,1> uwCURBE_TEMP(1,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wCURBE_TEMP(5)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wCURBE_TEMP(5)<1> ubCURR_UV(36,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wCURBE_TEMP(5)<1> wCURBE_TEMP(5)<16;16,1> ubCURR_UV(36,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wCURBE_TEMP(6)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wCURBE_TEMP(6)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(37,2)<8;8,1> -uwCURBE_TEMP(1,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(37,10)<8;8,1> -uwCURBE_TEMP(1,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(37,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,240)<8;8,1> uwCURBE_TEMP(1,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,248)<8;8,1> uwCURBE_TEMP(1,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wCURBE_TEMP(6)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wCURBE_TEMP(6)<1> ubCURR_UV(37,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wCURBE_TEMP(6)<1> wCURBE_TEMP(6)<16;16,1> ubCURR_UV(37,2)<16;16,1> //Pack Weight History WORD -> BYTE mov (16) ubCURBE_TEMP(3,0)<1> ubCURBE_TEMP(0)<32;16,2> mov (16) ubCURBE_TEMP(3,16)<1> ubCURBE_TEMP(1)<32;16,2> //Module Name : DN_UV_Compute_BNE_UV //Author : Tatiya, Rupesh //Description : Computes minimum SOAD for each 16x4 block. cmp.l.f0.0 (8) null:w uwSOAD_MIN_8x4(0,12)<16;4,1> uwSOAD_MIN_8x4(2,12)<16;4,1> (f0.0)sel (8) uwCURBE_TEMP(1,0)<1> uwSOAD_MIN_8x4(0,12)<16;4,1> uwSOAD_MIN_8x4(2,12)<16;4,1> mov (8) ubCURBE_TEMP(1)<1> ubCURBE_TEMP(1)<16;8,2> //Module Name : DN_UV_PL2_Pack_Denoised_UV //Name : Tatiya, Rupesh //Description : Pack UV denoised data based on PL2 input. //Module Name : DN_UV_Pack_Denoised_UV //Name : Tatiya, Rupesh //Description : Pack UV denoised data based on PL2/PL3/PA. //First 16 lines. mov (16) ubMSGPAYLOAD_UV0(0,0)<1> ubDIFF_TEMPORAL(0)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(0,16)<1> ubDIFF_TEMPORAL(1)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(1,0)<1> ubDIFF_TEMPORAL(2)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(1,16)<1> ubDIFF_TEMPORAL(3)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(2,0)<1> ubDIFF_TEMPORAL(4)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(2,16)<1> ubDIFF_TEMPORAL(5)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(3,0)<1> ubDIFF_TEMPORAL(6)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(3,16)<1> ubDIFF_TEMPORAL(7)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(4,0)<1> ubDIFF_TEMPORAL(8)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(4,16)<1> ubDIFF_TEMPORAL(9)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(5,0)<1> ubDIFF_TEMPORAL(10)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(5,16)<1> ubDIFF_TEMPORAL(11)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(6,0)<1> ubDIFF_TEMPORAL(12)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(6,16)<1> ubDIFF_TEMPORAL(13)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(7,0)<1> ubDIFF_TEMPORAL(14)<32;16,2> mov (16) ubMSGPAYLOAD_UV0(7,16)<1> ubDIFF_TEMPORAL(15)<32;16,2> //Second 16 lines. //12 lines first mov (16) ubMSGPAYLOAD_UV1(0,0)<1> ubDIFF_TEMPORAL(16)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(0,16)<1> ubDIFF_TEMPORAL(17)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(1,0)<1> ubDIFF_TEMPORAL(18)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(1,16)<1> ubDIFF_TEMPORAL(19)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(2,0)<1> ubDIFF_TEMPORAL(20)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(2,16)<1> ubDIFF_TEMPORAL(21)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(3,0)<1> ubDIFF_TEMPORAL(22)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(3,16)<1> ubDIFF_TEMPORAL(23)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(4,0)<1> ubDIFF_TEMPORAL(24)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(4,16)<1> ubDIFF_TEMPORAL(25)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(5,0)<1> ubDIFF_TEMPORAL(26)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(5,16)<1> ubDIFF_TEMPORAL(27)<32;16,2> //3 lines next mov (16) ubMSGPAYLOAD_UV1(6,0)<1> ubDIFF_TEMPORAL(28)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(6,16)<1> ubCURBE_TEMP(4)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(7,0)<1> ubCURBE_TEMP(5)<32;16,2> mov (16) ubMSGPAYLOAD_UV1(7,16)<1> ubCURBE_TEMP(6)<32;16,2> //Module Name : DN_UV_420_Save_Curr_Frame_Y //Author : Tatiya, Rupesh //Description : Save Curr Frame Y data for 420 Input //Module Name : DN_UV_Load_Curr_Frame_Y //Author : Tatiya, Rupesh //Description : Saves Y or YUY2 of Current frame. mov (8) acc0.0<1>:ud r0.0<8;8,1>:ud mov (2) acc0.0<1>:d r62.10<2;2,1>:w mov (1) acc0.2<1>:d 0xF000F:ud mov (8) r92.0<1>:ud acc0.0<8;8,1>:ud mov (8) r101.0<1>:ud acc0.0<8;8,1>:ud mov (8) r110.0<1>:ud acc0.0<8;8,1>:ud mov (8) r119.0<1>:ud acc0.0<8;8,1>:ud add (1) r101.1<1>:d acc0.1<0;1,0>:d 16:d add (1) r110.0<1>:d acc0.0<0;1,0>:d 16:d add (2) r119.0<1>:d acc0.0<2;2,1>:d 16:d send (8) null<1>:d r92 0x5 0x120A8018:ud send (8) null<1>:d r101 0x5 0x120A8018:ud send (8) null<1>:d r110 0x5 0x120A8018:ud send (8) null<1>:d r119 0x5 0x120A8018:ud //TODO - See if History saving can be combined with Curr Frame Save. - rT //Module Name : DN_UV_Save_Hist_UV //Author : Tatiya, Rupesh //Description : Saves DN history for UV data. mov (8) r3.0<1>:ud r0.0<8;8,1>:ud mov (2) r3.0<1>:d r62.12<2;2,1>:w mov (1) r3.2<1>:d 0x30007:ud send (8) null<1>:d r3 0x5 0x40A8021:ud //Module Name : DN_UV_Save_BNE_UV //Author : Tatiya, Rupesh //Description : Saves BNE values for 16x16 U and 16x16 V. mov (8) r1.0<1>:ud r0.0<8;8,1>:ud mov (2) r1.0<1>:d r63.12<2;2,1>:w mov (1) r1.2<1>:d 0x10003:ud send (8) null<1>:d r1 0x5 0x40A8023:ud //Module Name : DN_UV_PL2_Save_Curr_Frame_UV //Author : Tatiya, Rupesh //Module name : DN_UV_Save_Curr_Frame_UV //Author : Tatiya, Rupesh //Description : Saves Current Frame (UV only). mov (8) r74<1>:ud r0.0<8;8,1>:ud mov (8) r83<1>:ud r0.0<8;8,1>:ud mov (1) r74.0<1>:d r62.10<0;1,0>:w shr (1) r74.1<1>:d r62.11<0;1,0>:w 1:w mov (1) r74.2<1>:d 0xF000F:ud add (1) r83.0<1>:d r62.10<0;1,0>:w 16:d shr (1) r83.1<1>:d r62.11<0;1,0>:w 1:w mov (1) r83.2<1>:d 0xF000F:ud send (8) null<1>:d r74 0x5 0x120A8019:ud send (8) null<1>:d r83 0x5 0x120A8019:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 //All sub-routines here // Module Name : Noise_Detection // Author : Tatiya, Rupesh // Description : Performs noise detection on 32 pixels of U (8x4) and 32 pixels of V (8x4). DN_UV_NOISE_DETECTION_UV: // Find Field Block Median // // Purpose : Find the median value of the nine pixels in the same field // which are centered at current pixel. // // Works on 9 pixels centered at the current pixel // NOTE: pixels are within same field. // v4 - current pixel // // v2 v1 v0 // * * * <--- Different field - not used // v5 v4 v3 // * * * <--- Different field - not used // v8 v7 v6 // Algorithm to find median modifies the data. // Copy the data needed to calculate median so the original source data stays intact. // //TODO - Change Interleaved implementation to separated one if - , does not work on predication. - rT //Delete Later - rT //mov (1) pCUR_UV:uw 52*32:uw // v0 mov (16) ubMEDIAN_TEMP(0,0)<1> r[a0.0,0]<16;16,1> // v0 mov (16) ubMEDIAN_TEMP(0,16)<1> r[a0.0,32]<16;16,1> // v1 mov (16) ubMEDIAN_TEMP(1,0)<1> r[a0.0,2]<16;16,1> // v1 mov (16) ubMEDIAN_TEMP(1,16)<1> r[a0.0,34]<16;16,1> // v2 mov (16) ubMEDIAN_TEMP(2,0)<1> r[a0.0,4]<16;16,1> // v2 mov (16) ubMEDIAN_TEMP(2,16)<1> r[a0.0,36]<16;16,1> // v3 mov (16) ubMEDIAN_TEMP(3,0)<1> r[a0.0,64]<16;16,1> // v3 mov (16) ubMEDIAN_TEMP(3,16)<1> r[a0.0,96]<16;16,1> // v4 mov (16) ubMEDIAN_TEMP(4,0)<1> r[a0.0,66]<16;16,1> // v4 mov (16) ubMEDIAN_TEMP(4,16)<1> r[a0.0,98]<16;16,1> // v5 mov (16) ubMEDIAN_TEMP(5,0)<1> r[a0.0,68]<16;16,1> // v5 mov (16) ubMEDIAN_TEMP(5,16)<1> r[a0.0,100]<16;16,1> // v6 mov (16) ubMEDIAN_TEMP(6,0)<1> r[a0.0,128]<16;16,1> // v6 mov (16) ubMEDIAN_TEMP(6,16)<1> r[a0.0,160]<16;16,1> // v7 mov (16) ubMEDIAN_TEMP(7,0)<1> r[a0.0,130]<16;16,1> // v7 mov (16) ubMEDIAN_TEMP(7,16)<1> r[a0.0,162]<16;16,1> // v8 mov (16) ubMEDIAN_TEMP(8,0)<1> r[a0.0,132]<16;16,1> // v8 mov (16) ubMEDIAN_TEMP(8,16)<1> r[a0.0,164]<16;16,1> //TODO - Optimize one instruction here. add (1) a0.0:uw a0.0<0;1,0>:uw 64:uw // v0 mov (16) ubMEDIAN_TEMP(9,0)<1> r[a0.0,0]<16;16,1> // v0 mov (16) ubMEDIAN_TEMP(9,16)<1> r[a0.0,32]<16;16,1> // v1 mov (16) ubMEDIAN_TEMP(10,0)<1> r[a0.0,2]<16;16,1> // v1 mov (16) ubMEDIAN_TEMP(10,16)<1> r[a0.0,34]<16;16,1> // v2 mov (16) ubMEDIAN_TEMP(11,0)<1> r[a0.0,4]<16;16,1> // v2 mov (16) ubMEDIAN_TEMP(11,16)<1> r[a0.0,36]<16;16,1> // v3 mov (16) ubMEDIAN_TEMP(12,0)<1> r[a0.0,64]<16;16,1> // v3 mov (16) ubMEDIAN_TEMP(12,16)<1> r[a0.0,96]<16;16,1> // v4 mov (16) ubMEDIAN_TEMP(13,0)<1> r[a0.0,66]<16;16,1> // v4 mov (16) ubMEDIAN_TEMP(13,16)<1> r[a0.0,98]<16;16,1> // v5 mov (16) ubMEDIAN_TEMP(14,0)<1> r[a0.0,68]<16;16,1> // v5 mov (16) ubMEDIAN_TEMP(14,16)<1> r[a0.0,100]<16;16,1> // v6 mov (16) ubMEDIAN_TEMP(15,0)<1> r[a0.0,128]<16;16,1> // v6 mov (16) ubMEDIAN_TEMP(15,16)<1> r[a0.0,160]<16;16,1> // v7 mov (16) ubMEDIAN_TEMP(16,0)<1> r[a0.0,130]<16;16,1> // v7 mov (16) ubMEDIAN_TEMP(16,16)<1> r[a0.0,162]<16;16,1> // v8 mov (16) ubMEDIAN_TEMP(17,0)<1> r[a0.0,132]<16;16,1> // v8 mov (16) ubMEDIAN_TEMP(17,16)<1> r[a0.0,164]<16;16,1> //TODO - Optimize one instruction here. add (1) a0.0:uw a0.0<0;1,0>:uw 64:uw // MedianSwap // // MedianSwap(inOutLeft, inOutRight) // { // if (inOutLeft > inOutRight) // { // temp = inOutLeft // inOutLeft = inOutRight // inOutRight = temp // } // } // MedianSwap(v1, v2) - U // MedianSwap(v4, v5) - U // MedianSwap(v1, v2) - V // MedianSwap(v4, v5) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(1,0)<32;16,2> ubMEDIAN_TEMP(2,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(5,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(1,1)<32;16,2> ubMEDIAN_TEMP(2,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(5,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(1,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(4,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(1,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(1,0)<2> ubMEDIAN_TEMP(2,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(5,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(1,1)<2> ubMEDIAN_TEMP(2,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(5,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(2,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(5,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(2,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(5,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v7, v8) - U // MedianSwap(v0, v1) - U // MedianSwap(v7, v8) - V // MedianSwap(v0, v1) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(7,0)<32;16,2> ubMEDIAN_TEMP(8,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(0,0)<32;16,2> ubMEDIAN_TEMP(1,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(7,1)<32;16,2> ubMEDIAN_TEMP(8,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(0,1)<32;16,2> ubMEDIAN_TEMP(1,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(7,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(0,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(7,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(0,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(7,0)<2> ubMEDIAN_TEMP(8,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(0,0)<2> ubMEDIAN_TEMP(1,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(7,1)<2> ubMEDIAN_TEMP(8,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(0,1)<2> ubMEDIAN_TEMP(1,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(8,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(1,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(8,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(1,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v3, v4) - U // MedianSwap(v6, v7) - U // MedianSwap(v3, v4) - V // MedianSwap(v6, v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(3,0)<32;16,2> ubMEDIAN_TEMP(4,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(6,0)<32;16,2> ubMEDIAN_TEMP(7,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(3,1)<32;16,2> ubMEDIAN_TEMP(4,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(6,1)<32;16,2> ubMEDIAN_TEMP(7,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(3,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(6,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(3,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(6,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(3,0)<2> ubMEDIAN_TEMP(4,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(6,0)<2> ubMEDIAN_TEMP(7,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(3,1)<2> ubMEDIAN_TEMP(4,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(6,1)<2> ubMEDIAN_TEMP(7,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(4,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(7,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(4,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(7,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v1, v2) - U // MedianSwap(v4, v5) - U // MedianSwap(v1, v2) - V // MedianSwap(v4, v5) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(1,0)<32;16,2> ubMEDIAN_TEMP(2,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(5,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(1,1)<32;16,2> ubMEDIAN_TEMP(2,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(5,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(1,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(4,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(1,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(1,0)<2> ubMEDIAN_TEMP(2,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(5,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(1,1)<2> ubMEDIAN_TEMP(2,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(5,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(2,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(5,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(2,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(5,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v7, v8) - U // MedianSwap(v0, v3) - U // MedianSwap(v7, v8) - V // MedianSwap(v0, v3) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(7,0)<32;16,2> ubMEDIAN_TEMP(8,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(0,0)<32;16,2> ubMEDIAN_TEMP(3,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(7,1)<32;16,2> ubMEDIAN_TEMP(8,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(0,1)<32;16,2> ubMEDIAN_TEMP(3,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(7,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(0,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(7,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(0,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(7,0)<2> ubMEDIAN_TEMP(8,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(0,0)<2> ubMEDIAN_TEMP(3,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(7,1)<2> ubMEDIAN_TEMP(8,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(0,1)<2> ubMEDIAN_TEMP(3,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(8,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(3,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(8,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(3,1)<2> ubTEMP1(1,16)<16;16,1> // NOTE: // Compare v0 to v6 to find the minimum. // Store the minimum for future use. //TODO - Find if MIN is needed. //cmp.l.f0.0 (16) null:w ubMEDIAN_TEMP(%1+0,0)<32;16,2> ubMEDIAN_TEMP(%1+6,0)<32;16,2> //cmp.l.f1.0 (16) null:w ubMEDIAN_TEMP(%1+0,1)<32;16,2> ubMEDIAN_TEMP(%1+6,1)<32;16,2> //(f0.0) mov (16) ubCURR_MIN(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+0,0)<32;16,2> //(f1.0) mov (16) ubCURR_MIN(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+0,1)<32;16,2> //(-f0.0) mov (16) ubCURR_MIN(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+6,0)<32;16,2> //(-f1.0) mov (16) ubCURR_MIN(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+6,1)<32;16,2> // MedianSwap(v5, v8) - U // MedianSwap(v4, v7) - U // MedianSwap(v5, v8) - V // MedianSwap(v4, v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(5,0)<32;16,2> ubMEDIAN_TEMP(8,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(7,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(5,1)<32;16,2> ubMEDIAN_TEMP(8,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(7,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(5,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(4,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(5,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(5,0)<2> ubMEDIAN_TEMP(8,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(7,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(5,1)<2> ubMEDIAN_TEMP(8,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(7,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(8,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(7,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(8,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(7,1)<2> ubTEMP1(1,16)<16;16,1> // NOTE: // Compare v2 to v8 to find the maximum. // Store the maximum for future use. //TODO - Find if MAX is needed. // cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(%1+2,0)<32;16,2> ubMEDIAN_TEMP(%1+8,0)<32;16,2> // cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(%1+2,1)<32;16,2> ubMEDIAN_TEMP(%1+8,1)<32;16,2> //(f0.0) mov (16) ubCURR_MAX(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+2,0)<32;16,2> //(f1.0) mov (16) ubCURR_MAX(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+2,1)<32;16,2> //(-f0.0) mov (16) ubCURR_MAX(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+8,0)<32;16,2> //(-f1.0) mov (16) ubCURR_MAX(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+8,1)<32;16,2> // MedianSwap(v3, v6) - U // MedianSwap(v1, v4) - U // MedianSwap(v3, v6) - V // MedianSwap(v1, v4) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(3,0)<32;16,2> ubMEDIAN_TEMP(6,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(1,0)<32;16,2> ubMEDIAN_TEMP(4,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(3,1)<32;16,2> ubMEDIAN_TEMP(6,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(1,1)<32;16,2> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(6,0)<2> ubMEDIAN_TEMP(3,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(1,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(6,1)<2> ubMEDIAN_TEMP(3,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(1,1)<32;16,2> // MedianSwap(v2,v5) - U // MedianSwap(v4,v7) - U // MedianSwap(v2,v5) - V // MedianSwap(v4,v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(2,0)<32;16,2> ubMEDIAN_TEMP(5,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(7,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(2,1)<32;16,2> ubMEDIAN_TEMP(5,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(7,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(2,0)<2> ubMEDIAN_TEMP(5,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(7,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(2,1)<2> ubMEDIAN_TEMP(5,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(7,1)<32;16,2> // MedianSwap(v4,v2) - U // MedianSwap(v4,v2) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(2,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(2,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(4,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(2,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(2,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(2,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(2,1)<2> ubTEMP1(0,16)<16;16,1> // MedianSwap(v6,v4) - U // MedianSwap(v6,v4) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(6,0)<32;16,2> ubMEDIAN_TEMP(4,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(6,1)<32;16,2> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(6,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(6,1)<32;16,2> // MedianSwap(v4,v2) - U // MedianSwap(v4,v2) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(2,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(2,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(2,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(2,1)<32;16,2> cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(10,0)<32;16,2> ubMEDIAN_TEMP(11,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(14,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(10,1)<32;16,2> ubMEDIAN_TEMP(11,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(14,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(10,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(13,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(10,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(10,0)<2> ubMEDIAN_TEMP(11,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(14,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(10,1)<2> ubMEDIAN_TEMP(11,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(14,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(11,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(14,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(11,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(14,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v7, v8) - U // MedianSwap(v0, v1) - U // MedianSwap(v7, v8) - V // MedianSwap(v0, v1) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(16,0)<32;16,2> ubMEDIAN_TEMP(17,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(9,0)<32;16,2> ubMEDIAN_TEMP(10,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(16,1)<32;16,2> ubMEDIAN_TEMP(17,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(9,1)<32;16,2> ubMEDIAN_TEMP(10,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(16,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(9,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(16,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(9,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(16,0)<2> ubMEDIAN_TEMP(17,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(9,0)<2> ubMEDIAN_TEMP(10,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(16,1)<2> ubMEDIAN_TEMP(17,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(9,1)<2> ubMEDIAN_TEMP(10,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(17,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(10,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(17,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(10,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v3, v4) - U // MedianSwap(v6, v7) - U // MedianSwap(v3, v4) - V // MedianSwap(v6, v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(12,0)<32;16,2> ubMEDIAN_TEMP(13,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(15,0)<32;16,2> ubMEDIAN_TEMP(16,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(12,1)<32;16,2> ubMEDIAN_TEMP(13,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(15,1)<32;16,2> ubMEDIAN_TEMP(16,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(12,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(15,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(12,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(15,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(12,0)<2> ubMEDIAN_TEMP(13,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(15,0)<2> ubMEDIAN_TEMP(16,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(12,1)<2> ubMEDIAN_TEMP(13,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(15,1)<2> ubMEDIAN_TEMP(16,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(13,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(16,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(13,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(16,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v1, v2) - U // MedianSwap(v4, v5) - U // MedianSwap(v1, v2) - V // MedianSwap(v4, v5) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(10,0)<32;16,2> ubMEDIAN_TEMP(11,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(14,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(10,1)<32;16,2> ubMEDIAN_TEMP(11,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(14,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(10,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(13,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(10,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(10,0)<2> ubMEDIAN_TEMP(11,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(14,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(10,1)<2> ubMEDIAN_TEMP(11,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(14,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(11,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(14,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(11,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(14,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v7, v8) - U // MedianSwap(v0, v3) - U // MedianSwap(v7, v8) - V // MedianSwap(v0, v3) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(16,0)<32;16,2> ubMEDIAN_TEMP(17,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(9,0)<32;16,2> ubMEDIAN_TEMP(12,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(16,1)<32;16,2> ubMEDIAN_TEMP(17,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(9,1)<32;16,2> ubMEDIAN_TEMP(12,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(16,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(9,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(16,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(9,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(16,0)<2> ubMEDIAN_TEMP(17,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(9,0)<2> ubMEDIAN_TEMP(12,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(16,1)<2> ubMEDIAN_TEMP(17,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(9,1)<2> ubMEDIAN_TEMP(12,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(17,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(12,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(17,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(12,1)<2> ubTEMP1(1,16)<16;16,1> // NOTE: // Compare v0 to v6 to find the minimum. // Store the minimum for future use. //TODO - Find if MIN is needed. //cmp.l.f0.0 (16) null:w ubMEDIAN_TEMP(%1+0,0)<32;16,2> ubMEDIAN_TEMP(%1+6,0)<32;16,2> //cmp.l.f1.0 (16) null:w ubMEDIAN_TEMP(%1+0,1)<32;16,2> ubMEDIAN_TEMP(%1+6,1)<32;16,2> //(f0.0) mov (16) ubCURR_MIN(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+0,0)<32;16,2> //(f1.0) mov (16) ubCURR_MIN(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+0,1)<32;16,2> //(-f0.0) mov (16) ubCURR_MIN(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+6,0)<32;16,2> //(-f1.0) mov (16) ubCURR_MIN(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+6,1)<32;16,2> // MedianSwap(v5, v8) - U // MedianSwap(v4, v7) - U // MedianSwap(v5, v8) - V // MedianSwap(v4, v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(14,0)<32;16,2> ubMEDIAN_TEMP(17,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(16,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(14,1)<32;16,2> ubMEDIAN_TEMP(17,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(16,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(14,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(13,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(14,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(14,0)<2> ubMEDIAN_TEMP(17,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(16,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(14,1)<2> ubMEDIAN_TEMP(17,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(16,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(17,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(16,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(17,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(16,1)<2> ubTEMP1(1,16)<16;16,1> // NOTE: // Compare v2 to v8 to find the maximum. // Store the maximum for future use. //TODO - Find if MAX is needed. // cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(%1+2,0)<32;16,2> ubMEDIAN_TEMP(%1+8,0)<32;16,2> // cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(%1+2,1)<32;16,2> ubMEDIAN_TEMP(%1+8,1)<32;16,2> //(f0.0) mov (16) ubCURR_MAX(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+2,0)<32;16,2> //(f1.0) mov (16) ubCURR_MAX(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+2,1)<32;16,2> //(-f0.0) mov (16) ubCURR_MAX(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+8,0)<32;16,2> //(-f1.0) mov (16) ubCURR_MAX(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+8,1)<32;16,2> // MedianSwap(v3, v6) - U // MedianSwap(v1, v4) - U // MedianSwap(v3, v6) - V // MedianSwap(v1, v4) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(12,0)<32;16,2> ubMEDIAN_TEMP(15,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(10,0)<32;16,2> ubMEDIAN_TEMP(13,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(12,1)<32;16,2> ubMEDIAN_TEMP(15,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(10,1)<32;16,2> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(15,0)<2> ubMEDIAN_TEMP(12,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(10,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(15,1)<2> ubMEDIAN_TEMP(12,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(10,1)<32;16,2> // MedianSwap(v2,v5) - U // MedianSwap(v4,v7) - U // MedianSwap(v2,v5) - V // MedianSwap(v4,v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(11,0)<32;16,2> ubMEDIAN_TEMP(14,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(16,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(11,1)<32;16,2> ubMEDIAN_TEMP(14,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(16,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(11,0)<2> ubMEDIAN_TEMP(14,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(16,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(11,1)<2> ubMEDIAN_TEMP(14,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(16,1)<32;16,2> // MedianSwap(v4,v2) - U // MedianSwap(v4,v2) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(11,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(11,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(13,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(11,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(11,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(11,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(11,1)<2> ubTEMP1(0,16)<16;16,1> // MedianSwap(v6,v4) - U // MedianSwap(v6,v4) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(15,0)<32;16,2> ubMEDIAN_TEMP(13,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(15,1)<32;16,2> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(15,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(15,1)<32;16,2> // MedianSwap(v4,v2) - U // MedianSwap(v4,v2) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(11,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(11,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(11,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(11,1)<32;16,2> // Sobel Value calculation for the current pixel v4 // v2 v1 v0 // * * * <--- Different field - not used // v5 v4 v3 // * * * <--- Different field - not used // v8 v7 v6 // // Gx = -v0 - 2*v3 - v6 + v2 + 2*v5 + v8 // Gy = v0 + 2*v1 + v2 - v6 - 2*v7 - v8 // // Sobel = (|Gx| + |Gy|) >> 3 //TODO - Change Later - rT add (1) a0.0:uw a0.0<0;1,0>:uw -128:uw // - 2 * v3 mul (16) acc0.0<1>:w r[a0.0,64]<16;16,1>:ub -2:w // + v8 mac (16) acc0.0<1>:w r[a0.0,132]<16;16,1>:ub 1:w // - v0 mac (16) acc0.0<1>:w r[a0.0,0]<16;16,1>:ub -1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,128]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,4]<16;16,1>:ub 1:w // + 2 * v5 mac (16) wSOBEL_X(0)<1> r[a0.0,68]<16;16,1>:ub 2:w // - 2 * v3 mul (16) acc0.0<1>:w r[a0.0,96]<16;16,1>:ub -2:w // + v8 mac (16) acc0.0<1>:w r[a0.0,164]<16;16,1>:ub 1:w // - v0 mac (16) acc0.0<1>:w r[a0.0,32]<16;16,1>:ub -1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,160]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,36]<16;16,1>:ub 1:w // + 2 * v5 mac (16) wSOBEL_X(1)<1> r[a0.0,100]<16;16,1>:ub 2:w // - 2 * v3 mul (16) acc0.0<1>:w r[a0.0,128]<16;16,1>:ub -2:w // + v8 mac (16) acc0.0<1>:w r[a0.0,196]<16;16,1>:ub 1:w // - v0 mac (16) acc0.0<1>:w r[a0.0,64]<16;16,1>:ub -1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,192]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,68]<16;16,1>:ub 1:w // + 2 * v5 mac (16) wSOBEL_X(2)<1> r[a0.0,132]<16;16,1>:ub 2:w // - 2 * v3 mul (16) acc0.0<1>:w r[a0.0,160]<16;16,1>:ub -2:w // + v8 mac (16) acc0.0<1>:w r[a0.0,228]<16;16,1>:ub 1:w // - v0 mac (16) acc0.0<1>:w r[a0.0,96]<16;16,1>:ub -1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,224]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,100]<16;16,1>:ub 1:w // + 2 * v5 mac (16) wSOBEL_X(3)<1> r[a0.0,164]<16;16,1>:ub 2:w // + 2 * v1 mul (16) acc0.0<1>:w r[a0.0,2]<16;16,1>:ub 2:w // + v0 mac (16) acc0.0<1>:w r[a0.0,0]<16;16,1>:ub 1:w // - v8 mac (16) acc0.0<1>:w r[a0.0,132]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,4]<16;16,1>:ub 1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,128]<16;16,1>:ub -1:w // - 2 * v7 mac (16) acc0.0<1>:w r[a0.0,130]<16;16,1>:ub -2:w add (16) acc0.0<1>:uw (abs)acc0.0<16;16,1>:w (abs)wSOBEL_X(0)<16;16,1> shr (16) uwSOBEL(0)<1> acc0.0<16;16,1>:uw 3:uw // + 2 * v1 mul (16) acc0.0<1>:w r[a0.0,34]<16;16,1>:ub 2:w // + v0 mac (16) acc0.0<1>:w r[a0.0,32]<16;16,1>:ub 1:w // - v8 mac (16) acc0.0<1>:w r[a0.0,164]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,36]<16;16,1>:ub 1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,160]<16;16,1>:ub -1:w // - 2 * v7 mac (16) acc0.0<1>:w r[a0.0,162]<16;16,1>:ub -2:w add (16) acc0.0<1>:uw (abs)acc0.0<16;16,1>:w (abs)wSOBEL_X(1)<16;16,1> shr (16) uwSOBEL(1)<1> acc0.0<16;16,1>:uw 3:uw // + 2 * v1 mul (16) acc0.0<1>:w r[a0.0,66]<16;16,1>:ub 2:w // + v0 mac (16) acc0.0<1>:w r[a0.0,64]<16;16,1>:ub 1:w // - v8 mac (16) acc0.0<1>:w r[a0.0,196]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,68]<16;16,1>:ub 1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,192]<16;16,1>:ub -1:w // - 2 * v7 mac (16) acc0.0<1>:w r[a0.0,194]<16;16,1>:ub -2:w add (16) acc0.0<1>:uw (abs)acc0.0<16;16,1>:w (abs)wSOBEL_X(2)<16;16,1> shr (16) uwSOBEL(2)<1> acc0.0<16;16,1>:uw 3:uw // + 2 * v1 mul (16) acc0.0<1>:w r[a0.0,98]<16;16,1>:ub 2:w // + v0 mac (16) acc0.0<1>:w r[a0.0,96]<16;16,1>:ub 1:w // - v8 mac (16) acc0.0<1>:w r[a0.0,228]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,100]<16;16,1>:ub 1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,224]<16;16,1>:ub -1:w // - 2 * v7 mac (16) acc0.0<1>:w r[a0.0,226]<16;16,1>:ub -2:w add (16) acc0.0<1>:uw (abs)acc0.0<16;16,1>:w (abs)wSOBEL_X(3)<16;16,1> shr (16) uwSOBEL(3)<1> acc0.0<16;16,1>:uw 3:uw //Mov Median in CURBE_TEMP to free up temp space. mov (16) ubMEDIAN(0,0)<1> ubMEDIAN_TEMP(4,0)<16;16,1> mov (16) ubMEDIAN(0,16)<1> ubMEDIAN_TEMP(4,16)<16;16,1> mov (16) ubMEDIAN(0,32)<1> ubMEDIAN_TEMP(13,0)<16;16,1> mov (16) ubMEDIAN(0,48)<1> ubMEDIAN_TEMP(13,16)<16;16,1> // Find: // absDiff = abs(ubCurY - ubMedian) // Find the difference between pixel and median value. //Median is interleaved. So difference is also interleaved. //------------------------------------------------------------------------------------------ //Process 16 U and 16 V pixels here and rest later. // first row - v0,v1,v2 add (16) wDIFF(0)<1> r[a0.0,0]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(1)<1> r[a0.0,2]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(2)<1> r[a0.0,4]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> // second row - v3,v4,v5 add (16) wDIFF(3)<1> r[a0.0,64]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(4)<1> r[a0.0,66]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(5)<1> r[a0.0,68]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> // third row - v6,v7,v8 add (16) wDIFF(6)<1> r[a0.0,128]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(7)<1> r[a0.0,130]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(8)<1> r[a0.0,132]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> // first row - v0,v1,v2 add (16) wDIFF(9)<1> r[a0.0,32]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(10)<1> r[a0.0,34]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(11)<1> r[a0.0,36]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> // second row - v3,v4,v5 add (16) wDIFF(12)<1> r[a0.0,96]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(13)<1> r[a0.0,98]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(14)<1> r[a0.0,100]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> // third row - v6,v7,v8 add (16) wDIFF(15)<1> r[a0.0,160]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(16)<1> r[a0.0,162]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(17)<1> r[a0.0,164]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> //TODO - Change Later - rT add (1) a0.0:uw a0.0<0;1,0>:uw 64:uw // Find sum of all absolute differences AND // maximum absolute difference for 16 U and 16 V here. //First 2 rows of 8x4 //Compare 0-1, 2-3, 4-5, 6-7 cmp.g.f0.0 (16) null:uw (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> cmp.g.f0.1 (16) null:uw (abs)wDIFF(2)<16;16,1> (abs)wDIFF(3)<16;16,1> cmp.g.f1.0 (16) null:uw (abs)wDIFF(4)<16;16,1> (abs)wDIFF(5)<16;16,1> cmp.g.f1.1 (16) null:uw (abs)wDIFF(6)<16;16,1> (abs)wDIFF(7)<16;16,1> //Calculate SAD add (16) acc0.0<1>:uw (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(2)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(3)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(4)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(5)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(6)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(7)<16;16,1> add (16) uwSOAD(0)<1> acc0.0<16;16,1>:uw (abs)wDIFF(8)<16;16,1> (f0.0) sel (16) uwCURBE_TEMP(0)<1> (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> (f0.1) sel (16) uwCURBE_TEMP(1)<1> (abs)wDIFF(2)<16;16,1> (abs)wDIFF(3)<16;16,1> (f1.0) sel (16) uwCURBE_TEMP(2)<1> (abs)wDIFF(4)<16;16,1> (abs)wDIFF(5)<16;16,1> (f1.1) sel (16) uwCURBE_TEMP(3)<1> (abs)wDIFF(6)<16;16,1> (abs)wDIFF(7)<16;16,1> //------------ //DIFF(0-7) is not needed here. Populate it. // first row - v0,v1,v2 add (16) wDIFF(0)<1> r[a0.0,0]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(1)<1> r[a0.0,2]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(2)<1> r[a0.0,4]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> // second row - v3,v4,v5 add (16) wDIFF(3)<1> r[a0.0,64]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(4)<1> r[a0.0,66]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(5)<1> r[a0.0,68]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> // third row - v6,v7 add (16) wDIFF(6)<1> r[a0.0,128]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(7)<1> r[a0.0,130]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> //------------ //Compare Max(0,1) - Max(2,3), Max(4,5) - Max(6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> cmp.g.f0.1 (16) null:uw uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> (f0.1)sel (16) uwCURBE_TEMP(2)<1> uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> //Compare Max(0,1,2,3) - Max(4,5,6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> //Compare Max(0,1,2,3,4,5,6,7) - 8 cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(8)<16;16,1> (f0.0)sel (16) uwMAX_ABS_DIFF(0)<1> uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(8)<16;16,1> //------------ //Load v8 - DIFF(8) add (16) wDIFF(8)<1> r[a0.0,132]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> //------------ //Compare 0-1, 2-3, 4-5, 6-7 cmp.g.f0.0 (16) null:uw (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> cmp.g.f0.1 (16) null:uw (abs)wDIFF(11)<16;16,1> (abs)wDIFF(12)<16;16,1> cmp.g.f1.0 (16) null:uw (abs)wDIFF(13)<16;16,1> (abs)wDIFF(14)<16;16,1> cmp.g.f1.1 (16) null:uw (abs)wDIFF(15)<16;16,1> (abs)wDIFF(16)<16;16,1> //Calculate SAD add (16) acc0.0<1>:uw (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(11)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(12)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(13)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(14)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(15)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(16)<16;16,1> add (16) uwSOAD(1)<1> acc0.0<16;16,1>:uw (abs)wDIFF(17)<16;16,1> (f0.0) sel (16) uwCURBE_TEMP(0)<1> (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> (f0.1) sel (16) uwCURBE_TEMP(1)<1> (abs)wDIFF(11)<16;16,1> (abs)wDIFF(12)<16;16,1> (f1.0) sel (16) uwCURBE_TEMP(2)<1> (abs)wDIFF(13)<16;16,1> (abs)wDIFF(14)<16;16,1> (f1.1) sel (16) uwCURBE_TEMP(3)<1> (abs)wDIFF(15)<16;16,1> (abs)wDIFF(16)<16;16,1> //------------ //DIFF(0-7) is not needed here. Populate it. // first row - v0,v1,v2 add (16) wDIFF(9)<1> r[a0.0,32]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(10)<1> r[a0.0,34]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(11)<1> r[a0.0,36]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> // second row - v3,v4,v5 add (16) wDIFF(12)<1> r[a0.0,96]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(13)<1> r[a0.0,98]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(14)<1> r[a0.0,100]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> // third row - v6,v7 add (16) wDIFF(15)<1> r[a0.0,160]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(16)<1> r[a0.0,162]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> //------------ //Compare Max(0,1) - Max(2,3), Max(4,5) - Max(6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> cmp.g.f0.1 (16) null:uw uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> (f0.1)sel (16) uwCURBE_TEMP(2)<1> uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> //Compare Max(0,1,2,3) - Max(4,5,6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> //Compare Max(0,1,2,3,4,5,6,7) - 8 cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(17)<16;16,1> (f0.0)sel (16) uwMAX_ABS_DIFF(1)<1> uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(17)<16;16,1> //------------ //Load v8 - DIFF(8) add (16) wDIFF(17)<1> r[a0.0,164]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> //------------ //if ((sobel_edge_measure < m_SobelEdgeThreshold) && ((block_max-block_min) < m_LocalDiffThreshold)) // if (sigma_mb_min > sigma) // sigma_mb_min = sigma; //NOTE: block_min is always zero as median is one of the value in 3x3 block. So no need o calculate it. // So just do - //if ((sobel_edge_measure < m_SobelEdgeThreshold) && ((block_max) < m_LocalDiffThreshold) && ( sigma < sigma_mb_min)) // sigma_mb_min = sigma; //We are processing 32 bytes of U and 32 bytes of V - each of size 8x4. //Compare first 8 bytes with max possible (255). //Start above condition from second 8 bytes. //TODO - Change Later - rT // mov (1) pCUR_MIN_SOAD_8x4:uw 1752:uw //r54.24:ub //First row of 8x4 cmp.l.f0.0 (16) null:uw uwSOBEL(0)<16;16,1> r55.30<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwMAX_ABS_DIFF(0)<16;16,1> r55.28<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwSOAD(0)<16;16,1> 255:uw (f0.0) sel (16) uwSOBEL(0)<1> uwSOAD(0)<16;16,1> 255:uw //Second row of 8x4 cmp.l.f0.0 (16) null:uw uwSOBEL(1)<16;16,1> r55.30<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwMAX_ABS_DIFF(1)<16;16,1> r55.28<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwSOAD(1)<16;16,1> uwSOBEL(0)<16;16,1> (f0.0) mov (16) uwSOBEL(0)<1> uwSOAD(1)<16;16,1> // Find sum of all absolute differences AND // maximum absolute difference for 16 U and 16 V here. //Second 2 rows of 8x4 //Compare 0-1, 2-3, 4-5, 6-7 cmp.g.f0.0 (16) null:uw (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> cmp.g.f0.1 (16) null:uw (abs)wDIFF(2)<16;16,1> (abs)wDIFF(3)<16;16,1> cmp.g.f1.0 (16) null:uw (abs)wDIFF(4)<16;16,1> (abs)wDIFF(5)<16;16,1> cmp.g.f1.1 (16) null:uw (abs)wDIFF(6)<16;16,1> (abs)wDIFF(7)<16;16,1> //Calculate SAD add (16) acc0.0<1>:uw (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(2)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(3)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(4)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(5)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(6)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(7)<16;16,1> add (16) uwSOAD(0)<1> acc0.0<16;16,1>:uw (abs)wDIFF(8)<16;16,1> (f0.0) sel (16) uwCURBE_TEMP(0)<1> (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> (f0.1) sel (16) uwCURBE_TEMP(1)<1> (abs)wDIFF(2)<16;16,1> (abs)wDIFF(3)<16;16,1> (f1.0) sel (16) uwCURBE_TEMP(2)<1> (abs)wDIFF(4)<16;16,1> (abs)wDIFF(5)<16;16,1> (f1.1) sel (16) uwCURBE_TEMP(3)<1> (abs)wDIFF(6)<16;16,1> (abs)wDIFF(7)<16;16,1> //Compare Max(0,1) - Max(2,3), Max(4,5) - Max(6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> cmp.g.f0.1 (16) null:uw uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> (f0.1)sel (16) uwCURBE_TEMP(2)<1> uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> //Compare Max(0,1,2,3) - Max(4,5,6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> //Compare Max(0,1,2,3,4,5,6,7) - 8 cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(8)<16;16,1> (f0.0)sel (16) uwMAX_ABS_DIFF(0)<1> uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(8)<16;16,1> //Compare 0-1, 2-3, 4-5, 6-7 cmp.g.f0.0 (16) null:uw (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> cmp.g.f0.1 (16) null:uw (abs)wDIFF(11)<16;16,1> (abs)wDIFF(12)<16;16,1> cmp.g.f1.0 (16) null:uw (abs)wDIFF(13)<16;16,1> (abs)wDIFF(14)<16;16,1> cmp.g.f1.1 (16) null:uw (abs)wDIFF(15)<16;16,1> (abs)wDIFF(16)<16;16,1> //Calculate SAD add (16) acc0.0<1>:uw (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(11)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(12)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(13)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(14)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(15)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(16)<16;16,1> add (16) uwSOAD(1)<1> acc0.0<16;16,1>:uw (abs)wDIFF(17)<16;16,1> (f0.0) sel (16) uwCURBE_TEMP(0)<1> (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> (f0.1) sel (16) uwCURBE_TEMP(1)<1> (abs)wDIFF(11)<16;16,1> (abs)wDIFF(12)<16;16,1> (f1.0) sel (16) uwCURBE_TEMP(2)<1> (abs)wDIFF(13)<16;16,1> (abs)wDIFF(14)<16;16,1> (f1.1) sel (16) uwCURBE_TEMP(3)<1> (abs)wDIFF(15)<16;16,1> (abs)wDIFF(16)<16;16,1> //Compare Max(0,1) - Max(2,3), Max(4,5) - Max(6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> cmp.g.f0.1 (16) null:uw uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> (f0.1)sel (16) uwCURBE_TEMP(2)<1> uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> //Compare Max(0,1,2,3) - Max(4,5,6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> //Compare Max(0,1,2,3,4,5,6,7) - 8 cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(17)<16;16,1> (f0.0)sel (16) uwMAX_ABS_DIFF(1)<1> uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(17)<16;16,1> //Third row of 8x4 cmp.l.f0.0 (16) null:uw uwSOBEL(2)<16;16,1> r55.30<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwMAX_ABS_DIFF(0)<16;16,1> r55.28<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwSOAD(0)<16;16,1> uwSOBEL(0)<16;16,1> (f0.0) mov (16) uwSOBEL(0)<1> uwSOAD(0)<16;16,1> //Fourth row of 8x4 cmp.l.f0.0 (16) null:uw uwSOBEL(3)<16;16,1> r55.30<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwMAX_ABS_DIFF(1)<16;16,1> r55.28<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwSOAD(1)<16;16,1> uwSOBEL(0)<16;16,1> (f0.0) mov (16) uwSOBEL(0)<1> uwSOAD(1)<16;16,1> cmp.l.f0.0 (8) null:uw uwSOBEL(0,0)<8;8,1> uwSOBEL(0,8)<8;8,1> (f0.0) sel (8) uwSOBEL(0)<1> uwSOBEL(0,0)<8;8,1> uwSOBEL(0,8)<8;8,1> cmp.l.f0.0 (4) null:uw uwSOBEL(0,0)<4;4,1> uwSOBEL(0,4)<4;4,1> (f0.0) sel (4) uwSOBEL(0)<1> uwSOBEL(0,0)<4;4,1> uwSOBEL(0,4)<4;4,1> cmp.l.f0.0 (2) null:uw uwSOBEL(0,0)<2;2,1> uwSOBEL(0,2)<2;2,1> (f0.0) sel (2) r[a0.1,0]<1>:uw uwSOBEL(0,0)<2;2,1> uwSOBEL(0,2)<2;2,1> // End of common.inc mov (1) ip:ud r7.7<0;1,0>:d .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/NV12_DN_422CP.g4a000066400000000000000000000573301231401140700246770ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 113 // Total instruction count // 1 // Total kernel count .kernel NV12_DN_422CP .code // FileName: DN_PL_Core.asm // Author: Vivek Kumar // Description: Tasks for DN only case (16x8 block) for planar format // FileName: DN.asm // Author: Vivek Kumar // Description: Tasks for DN only case (16x8 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x45E8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(4,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DN_Hist_Save.asm // Author: Vivek Kumar // Description: Saves DN history data to statistics surface // Write denoise history to memory mov (8) r27<1>:ud r0.0<8;8,1>:ud // message header mov (2) mudMSGHDR_HIST(1)<1> udDNDI_RESP(4,0)<2;2,1> // Move denoise history to MRF (4x2) shr (2) r27.0<1>:ud r7.0<2;2,1>:w 2:w // X,Y origin / 4 add (1) r27.0<1>:ud r27.0<0;1,0>:ud r1.12<0;1,0>:uw { NoDDClr } // Add pitch to X origin mov (1) r27.2<1>:ud 0x10003:ud { NoDDChk } // block width and height mov (8) mudMSGHDR_HIST(0)<1> r27.0<8;8,1>:ud send (8) null<1>:d r22 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x50003:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | X | X | X | X | //---------------------------------------------------- //| X | SVCM | X | //---------------------------------------------------- //| SHCM | STAD | X | //---------------------------------------------------- //| X | X | //---------------------------------------------------- //| X | SVCM | X | //---------------------------------------------------- //| SHCM | STAD | X | //---------------------------------------------------- mov (1) mubMSGHDR_ENC_STATS(1,0)<1> ubDNDI_RESP(4,8)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (1) muwMSGHDR_ENC_STATS(1,3)<1> uwDNDI_RESP(4,11)<0;1,0> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) muwMSGHDR_ENC_STATS(1,4)<1> uwDNDI_RESP(4,12)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (1) muwMSGHDR_ENC_STATS(1,9)<1> uwDNDI_RESP(4,8)<0;1,0> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) muwMSGHDR_ENC_STATS(1,10)<1> uwDNDI_RESP(4,9)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DN_Load_UV_NV12_16x8.asm // Author: Vivek Kumar // Description: Read UV for 16x8 block through DATAPORT // FileName: UVCopy_Load_16x8.asm // Author: Vivek Kumar // Description: Read UV for 16x8 block through DATAPORT //CHANGE : Read extra UV data to convert to 422. -rT //we are reading extra data in ALL cases irrespective of whether upsampling is reqd or not later on, to keep things simple. add (2) r27.0<1>:d r7.0<2;2,1>:w r4.4<2;2,1>:w // Source Y Block origin asr (1) r27.1<1>:d r27.1<0;1,0>:d 1:w { NoDDClr } // U/V block origin should be half of Y's mov (1) r27.2<1>:ud 0x4000F:ud { NoDDChk } // U/V block width and height (8x5) mov (8) mudMSGHDR_UVCOPY(0)<1> r27.0<8;8,1>:ud send (8) udDNDI_UV_RESP(0)<1> r36 0x4 0x2390001:ud //Update Header for Save mov (1) mudMSGHDR_UVCOPY(0,2)<1> 0x3000F:ud // U/V block width and height (8x4) // FileName: DN_Save_Y_16x8.asm // Author: Vivek Kumar // Description: Save one 16x8 blocks of Y channel of DN output for reference mov (8) mudDN_Y_OUT(0,0)<1> r0<8;8,1>:ud // message header mov (2) mudDN_Y_OUT(0,0)<1> r7.0<2;2,1>:w { NoDDClr } // X origin mov (1) mudDN_Y_OUT(0,2)<1> 0x7000F:ud { NoDDChk } // block width and height (16x8) //send out data through data port send (8) null<1>:d mudDN_Y_OUT 0x5 0xA0A8018:ud // FileName: DN_Save_UV_NV12_16x8.asm // Author: Vivek Kumar // Description: Save UV for 16x8 block through DATAPORT // FileName: UVCopy_Save_16x8.asm // Author: Vivek Kumar // Description: Save UV for 16x8 block through DATAPORT //Reuse the header from Load component //Header is modified at the end of load - to be usable for save. mov (8) mudMSGHDR_UVCOPY(1)<1> udDNDI_UV_RESP(0)<8;8,1> mov (8) mudMSGHDR_UVCOPY(2)<1> udDNDI_UV_RESP(1)<8;8,1> send (8) null<1>:d r36 0x5 0x60A8019:ud // FileName: DN_Upsample_UV_NV12_16x8.asm // Author: Tatiya, Rupesh // Description: Upconvert 420 UV to 422 // FileName: UVCopy_Upsample_UV_16x8.asm // Author: Tatiya, Rupesh // Description: Convert 42X UV to 422 - to be used for IECP. avg.sat (16) uwDNDI_UVCOPY_TEMP(0) ubDNDI_UV_RESP(0,0)<16;16,1> ubDNDI_UV_RESP(0,0)<16;16,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(1) ubDNDI_UV_RESP(0,0)<16;16,1> ubDNDI_UV_RESP(0,16)<16;16,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(2) ubDNDI_UV_RESP(0,16)<16;16,1> ubDNDI_UV_RESP(0,16)<16;16,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(3) ubDNDI_UV_RESP(0,16)<16;16,1> ubDNDI_UV_RESP(0,32)<16;16,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(4) ubDNDI_UV_RESP(0,32)<16;16,1> ubDNDI_UV_RESP(0,32)<16;16,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(5) ubDNDI_UV_RESP(0,32)<16;16,1> ubDNDI_UV_RESP(0,48)<16;16,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(6) ubDNDI_UV_RESP(0,48)<16;16,1> ubDNDI_UV_RESP(0,48)<16;16,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(7) ubDNDI_UV_RESP(0,48)<16;16,1> ubDNDI_UV_RESP(0,64)<16;16,1> mov (16) ubDNDI_RESP(5,1)<2> ubDNDI_UVCOPY_TEMP(0,0)<32;8,4> { NoDDClr } //Copy U data mov (16) ubDNDI_RESP(5,0)<2> ubDNDI_UVCOPY_TEMP(0,2)<32;8,4> { NoDDChk } //Copy V data mov (16) ubDNDI_RESP(5,33)<2> ubDNDI_UVCOPY_TEMP(2,0)<32;8,4> { NoDDClr } //Copy U data mov (16) ubDNDI_RESP(5,32)<2> ubDNDI_UVCOPY_TEMP(2,2)<32;8,4> { NoDDChk } //Copy V data mov (16) ubDNDI_RESP(5,65)<2> ubDNDI_UVCOPY_TEMP(4,0)<32;8,4> { NoDDClr } //Copy U data mov (16) ubDNDI_RESP(5,64)<2> ubDNDI_UVCOPY_TEMP(4,2)<32;8,4> { NoDDChk } //Copy V data mov (16) ubDNDI_RESP(5,97)<2> ubDNDI_UVCOPY_TEMP(6,0)<32;8,4> { NoDDClr } //Copy U data mov (16) ubDNDI_RESP(5,96)<2> ubDNDI_UVCOPY_TEMP(6,2)<32;8,4> { NoDDChk } //Copy V data // FileName: DN_Save_422CP_16x8.asm // Author: Vivek Kumar // Description: Save one 16x8 blocks of DN output to the color pipe in 4-2-2 format .declare mubMSGHDR_DN_OUT_2 Base=r36.0 ElementSize=1 Type=ub mov (8) mudMSGHDR_DN_OUT(0)<1> r0<8;8,1>:ud // message header shl (1) mdMSGHDR_DN_OUT(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin * 2 (422 output) mov (1) mdMSGHDR_DN_OUT(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_DN_OUT(0,2)<1> 0x7000F:ud { NoDDClr, NoDDChk } // block width and height (16x8) //M0.3 - 0 - CP Enable, 1 - Area of Interest, 3:2 Message Format(TBD), 4:3 - Ignored, 31:5 CP state pointer //Compose area-of-interest bit + color pipe state pointer or (1) mudMSGHDR_DN_OUT(0,3)<1> r2.4<0;1,0>:ud r7.26<0;1,0>:b { NoDDChk } // First 8 x 8 Block mov (8) mubMSGHDR_DN_OUT(1)<2> ubDNDI_RESP(0,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(1,16)<2> ubDNDI_RESP(0,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(2)<2> ubDNDI_RESP(0,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(2,16)<2> ubDNDI_RESP(0,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(3)<2> ubDNDI_RESP(0,64)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(3,16)<2> ubDNDI_RESP(0,80)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(4)<2> ubDNDI_RESP(0,96)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(4,16)<2> ubDNDI_RESP(0,112)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(1,1)<4> ubDNDI_RESP(5,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(1,17)<4> ubDNDI_RESP(5,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(1,3)<4> ubDNDI_RESP(5,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(1,19)<4> ubDNDI_RESP(5,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(2,1)<4> ubDNDI_RESP(5,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(2,17)<4> ubDNDI_RESP(5,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(2,3)<4> ubDNDI_RESP(5,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(2,19)<4> ubDNDI_RESP(5,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(3,1)<4> ubDNDI_RESP(5,65)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(3,17)<4> ubDNDI_RESP(5,81)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(3,3)<4> ubDNDI_RESP(5,64)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(3,19)<4> ubDNDI_RESP(5,80)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(4,1)<4> ubDNDI_RESP(5,97)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(4,17)<4> ubDNDI_RESP(5,113)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(4,3)<4> ubDNDI_RESP(5,96)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(4,19)<4> ubDNDI_RESP(5,112)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Second 8 x 8 Block mov (8) r36.0<1>:ud r31.0<8;8,1>:ud add (1) r36.0<1>:ud r36.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DN_OUT_2(1)<2> ubDNDI_RESP(0,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(1,16)<2> ubDNDI_RESP(0,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(2)<2> ubDNDI_RESP(0,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(2,16)<2> ubDNDI_RESP(0,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(3)<2> ubDNDI_RESP(0,72)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(3,16)<2> ubDNDI_RESP(0,88)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(4)<2> ubDNDI_RESP(0,104)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(4,16)<2> ubDNDI_RESP(0,120)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(1,1)<4> ubDNDI_RESP(5,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(1,17)<4> ubDNDI_RESP(5,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(1,3)<4> ubDNDI_RESP(5,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(1,19)<4> ubDNDI_RESP(5,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(2,1)<4> ubDNDI_RESP(5,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(2,17)<4> ubDNDI_RESP(5,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(2,3)<4> ubDNDI_RESP(5,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(2,19)<4> ubDNDI_RESP(5,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(3,1)<4> ubDNDI_RESP(5,73)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(3,17)<4> ubDNDI_RESP(5,89)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(3,3)<4> ubDNDI_RESP(5,72)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(3,19)<4> ubDNDI_RESP(5,88)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(4,1)<4> ubDNDI_RESP(5,105)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(4,17)<4> ubDNDI_RESP(5,121)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(4,3)<4> ubDNDI_RESP(5,104)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(4,19)<4> ubDNDI_RESP(5,120)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization //send out data through data port send (8) null<1>:d r31.0 0x5 0xA0A801B:ud send (8) null<1>:d r36.0 0x5 0xA0A801B:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/NV12_DN_NV12.g4a000066400000000000000000000345341231401140700246340ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 40 // Total instruction count // 1 // Total kernel count .kernel NV12_DN_NV12 .code // FileName: DN_PL_Core.asm // Author: Vivek Kumar // Description: Tasks for DN only case (16x8 block) for planar format // FileName: DN.asm // Author: Vivek Kumar // Description: Tasks for DN only case (16x8 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x45E8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(4,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DN_Hist_Save.asm // Author: Vivek Kumar // Description: Saves DN history data to statistics surface // Write denoise history to memory mov (8) r27<1>:ud r0.0<8;8,1>:ud // message header mov (2) mudMSGHDR_HIST(1)<1> udDNDI_RESP(4,0)<2;2,1> // Move denoise history to MRF (4x2) shr (2) r27.0<1>:ud r7.0<2;2,1>:w 2:w // X,Y origin / 4 add (1) r27.0<1>:ud r27.0<0;1,0>:ud r1.12<0;1,0>:uw { NoDDClr } // Add pitch to X origin mov (1) r27.2<1>:ud 0x10003:ud { NoDDChk } // block width and height mov (8) mudMSGHDR_HIST(0)<1> r27.0<8;8,1>:ud send (8) null<1>:d r22 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x50003:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | X | X | X | X | //---------------------------------------------------- //| X | SVCM | X | //---------------------------------------------------- //| SHCM | STAD | X | //---------------------------------------------------- //| X | X | //---------------------------------------------------- //| X | SVCM | X | //---------------------------------------------------- //| SHCM | STAD | X | //---------------------------------------------------- mov (1) mubMSGHDR_ENC_STATS(1,0)<1> ubDNDI_RESP(4,8)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (1) muwMSGHDR_ENC_STATS(1,3)<1> uwDNDI_RESP(4,11)<0;1,0> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) muwMSGHDR_ENC_STATS(1,4)<1> uwDNDI_RESP(4,12)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (1) muwMSGHDR_ENC_STATS(1,9)<1> uwDNDI_RESP(4,8)<0;1,0> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) muwMSGHDR_ENC_STATS(1,10)<1> uwDNDI_RESP(4,9)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DN_Load_UV_NV12_16x8.asm // Author: Vivek Kumar // Description: Read UV for 16x8 block through DATAPORT // FileName: UVCopy_Load_16x8.asm // Author: Vivek Kumar // Description: Read UV for 16x8 block through DATAPORT //CHANGE : Read extra UV data to convert to 422. -rT //we are reading extra data in ALL cases irrespective of whether upsampling is reqd or not later on, to keep things simple. add (2) r27.0<1>:d r7.0<2;2,1>:w r4.4<2;2,1>:w // Source Y Block origin asr (1) r27.1<1>:d r27.1<0;1,0>:d 1:w { NoDDClr } // U/V block origin should be half of Y's mov (1) r27.2<1>:ud 0x4000F:ud { NoDDChk } // U/V block width and height (8x5) mov (8) mudMSGHDR_UVCOPY(0)<1> r27.0<8;8,1>:ud send (8) udDNDI_UV_RESP(0)<1> r36 0x4 0x2390001:ud //Update Header for Save mov (1) mudMSGHDR_UVCOPY(0,2)<1> 0x3000F:ud // U/V block width and height (8x4) // FileName: DN_Save_Y_16x8.asm // Author: Vivek Kumar // Description: Save one 16x8 blocks of Y channel of DN output for reference mov (8) mudDN_Y_OUT(0,0)<1> r0<8;8,1>:ud // message header mov (2) mudDN_Y_OUT(0,0)<1> r7.0<2;2,1>:w { NoDDClr } // X origin mov (1) mudDN_Y_OUT(0,2)<1> 0x7000F:ud { NoDDChk } // block width and height (16x8) //send out data through data port send (8) null<1>:d mudDN_Y_OUT 0x5 0xA0A8018:ud // FileName: DN_Save_UV_NV12_16x8.asm // Author: Vivek Kumar // Description: Save UV for 16x8 block through DATAPORT // FileName: UVCopy_Save_16x8.asm // Author: Vivek Kumar // Description: Save UV for 16x8 block through DATAPORT //Reuse the header from Load component //Header is modified at the end of load - to be usable for save. mov (8) mudMSGHDR_UVCOPY(1)<1> udDNDI_UV_RESP(0)<8;8,1> mov (8) mudMSGHDR_UVCOPY(2)<1> udDNDI_UV_RESP(1)<8;8,1> send (8) null<1>:d r36 0x5 0x60A8019:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a000066400000000000000000000461771231401140700250510ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 39 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PA_AVS_Buf_0.asm // Author: Vivek Kumar // Description: Loads 8x8 AVS/IEF Packed data into Buffer 0 // FileName : PA_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF Packed data into Buffer N //On IVB, for AVS module - set buffer pointers offset according to AVS Layout. //Change it to Sample Unorm layout in Shuffle modules. // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. mov (1) r22.4<1>:ud 0x400040:ud //Check if layer is to be skipped // f0.1 pre-computed in Set_Layer_0 (-f0.1) jmpi (1) SKIP_AVS_LOAD_L0_0_ //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0:ud r23.5<0;1,0>:ud 0x50EB400:ud //msg desc mov (1) r16.2:ud 0x00000000:ud // Enable ARGB channels //OPT: rAVS_PAYLOAD.1 and .7 --> use NODDCLR, NODDCHK -rT mov (1) r25.7<1>:ud r7.7:ud { NoDDClr } mov (1) r25.1<1>:ud r7.12:uw { NoDDChk } // set the vertical block number mov (8) r17.0:ud r25.0<8;8,1>:ud // Gen7 AVS WA Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces // if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) // { // modified_u_coord = u_coord – 5.0/(256*width); //floating point // } // else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) // { // modified_u_coord = u_coord + 1.0/(256*width); //floating point // } // else{ // modified_u_coord = u_coord; // } // Where u_left = u – 2*du + 3*ddu for IEF On // And u_left = u for IEF Off case // // check whether Gen7 AVS WA is enabled, mov (1) r14.8:uw f0.0:uw // save f0.0 and.nz.f0.0 (1) null<1>:uw r2.3:uw 0x2:uw (-f0.0)jmpi (1) GEN7_AVS_WA_DONE_L0_0_ // Gen7 AVS WA, check if IEF is ON for choosing Gen7 AVS WA formula and.nz.f0.0 (8) null<1>:uw r2.3<0;1,0>:uw 0x4:uw (f0.0)mov (8) acc0.0:f r17.2<0;1,0>:f (f0.0)mac (8) acc0.0:f r17.4<0;1,0>:f -2.0:f (f0.0)mac (8) acc0.0:f r17.6<0;1,0>:f 3.0:f (f0.0)mov (1) r14.2:f acc0:f // IEF ON, rTEMP3.2 = u_left (-f0.0)mov (1) r14.2:f r17.2<0;1,0>:f // IEF OFF, rTEMP3.2 = u_left and (1) r14.1:ud r2.3:uw 0xFFF8:uw asr (1) r14.1:ud r14.1:ud 3:d mov (1) r14.1:f r14.1:ud // Gen7 AVS WA, if (int)(u_left*width + 5.0/256) > (int)(u_left*width) mul (1) r14.0:f r14.2:f r14.1:f // rTEMP3.0 = u_left*width add (1) r14.2:f r14.0:f 0.01953125:f // rTEMP3.2 = u_left*width + 5.0/256 add (1) r14.3:f r14.0:f 0.99609375:f // rTEMP3.3 = u_left*width + 255.0/256 //Check if the values are < 0 and account for (int) cast of negative numbers //(int)(u_left*width) cmp.l.f0.0 (1) null<1>:f r14.0:f 0.00000000:f mov (1) r14.0:d r14.0:f (f0.0)add (1) r14.0:d r14.0<0;1,0>:d -1:d //(int)(u_left*width + 5.0/256) cmp.l.f0.0 (1) null<1>:f r14.2:f 0.00000000:f mov (1) r14.2:d r14.2:f (f0.0)add (1) r14.2:d r14.2<0;1,0>:d -1:d //(int)(u_left*width + 255.0/256) cmp.l.f0.0 (1) null<1>:f r14.3:f 0.00000000:f mov (1) r14.3:d r14.3:f (f0.0)add (1) r14.3:d r14.3<0;1,0>:d -1:d mov (1) f0.0:uw 0:uw // clear flag //if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) cmp.g.f1.0 (1) null<1>:d r14.2:d r14.0:d // modified_u_coord = u_coord – 5.0/(256*width); //floating point (f1.0) add (1) r17.2:f r17.2<0;1,0>:f -r2.3:f //else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) (-f1.0) cmp.e.f0.0 (1) null<1>:d r14.3:d r14.0:d // modified_u_coord = u_coord + 1.0/(256*width); //floating point (f0.0) add (1) r17.2:f r17.2<0;1,0>:f r2.2:f GEN7_AVS_WA_DONE_L0_0_: mov (1) f0.0:uw r14.8:uw // restore f0.0 send (1) uwBUFFER_0(0)<1> r16 0x2 a0.0:ud // Returns packed data in 16 GRFs in scrambled order SKIP_AVS_LOAD_L0_0_: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a000066400000000000000000000454071231401140700250450ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 37 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PA_AVS_Buf_1.asm // Author: Vivek Kumar // Description: Loads 8x8 AVS/IEF Packed data into Buffer 1 // FileName : PA_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF Packed data into Buffer N //On IVB, for AVS module - set buffer pointers offset according to AVS Layout. //Change it to Sample Unorm layout in Shuffle modules. // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //Check if layer is to be skipped // f0.1 pre-computed in Set_Layer_0 (-f0.1) jmpi (1) SKIP_AVS_LOAD_L0_1_ //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0:ud r23.5<0;1,0>:ud 0x50EB400:ud //msg desc mov (1) r16.2:ud 0x00000000:ud // Enable ARGB channels // set the vertical block number add (1) r25.1<1>:ud r7.12:uw 1:ud mov (8) r17.0:ud r25.0<8;8,1>:ud // Gen7 AVS WA Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces // if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) // { // modified_u_coord = u_coord – 5.0/(256*width); //floating point // } // else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) // { // modified_u_coord = u_coord + 1.0/(256*width); //floating point // } // else{ // modified_u_coord = u_coord; // } // Where u_left = u – 2*du + 3*ddu for IEF On // And u_left = u for IEF Off case // // check whether Gen7 AVS WA is enabled, mov (1) r14.8:uw f0.0:uw // save f0.0 and.nz.f0.0 (1) null<1>:uw r2.3:uw 0x2:uw (-f0.0)jmpi (1) GEN7_AVS_WA_DONE_L0_1_ // Gen7 AVS WA, check if IEF is ON for choosing Gen7 AVS WA formula and.nz.f0.0 (8) null<1>:uw r2.3<0;1,0>:uw 0x4:uw (f0.0)mov (8) acc0.0:f r17.2<0;1,0>:f (f0.0)mac (8) acc0.0:f r17.4<0;1,0>:f -2.0:f (f0.0)mac (8) acc0.0:f r17.6<0;1,0>:f 3.0:f (f0.0)mov (1) r14.2:f acc0:f // IEF ON, rTEMP3.2 = u_left (-f0.0)mov (1) r14.2:f r17.2<0;1,0>:f // IEF OFF, rTEMP3.2 = u_left and (1) r14.1:ud r2.3:uw 0xFFF8:uw asr (1) r14.1:ud r14.1:ud 3:d mov (1) r14.1:f r14.1:ud // Gen7 AVS WA, if (int)(u_left*width + 5.0/256) > (int)(u_left*width) mul (1) r14.0:f r14.2:f r14.1:f // rTEMP3.0 = u_left*width add (1) r14.2:f r14.0:f 0.01953125:f // rTEMP3.2 = u_left*width + 5.0/256 add (1) r14.3:f r14.0:f 0.99609375:f // rTEMP3.3 = u_left*width + 255.0/256 //Check if the values are < 0 and account for (int) cast of negative numbers //(int)(u_left*width) cmp.l.f0.0 (1) null<1>:f r14.0:f 0.00000000:f mov (1) r14.0:d r14.0:f (f0.0)add (1) r14.0:d r14.0<0;1,0>:d -1:d //(int)(u_left*width + 5.0/256) cmp.l.f0.0 (1) null<1>:f r14.2:f 0.00000000:f mov (1) r14.2:d r14.2:f (f0.0)add (1) r14.2:d r14.2<0;1,0>:d -1:d //(int)(u_left*width + 255.0/256) cmp.l.f0.0 (1) null<1>:f r14.3:f 0.00000000:f mov (1) r14.3:d r14.3:f (f0.0)add (1) r14.3:d r14.3<0;1,0>:d -1:d mov (1) f0.0:uw 0:uw // clear flag //if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) cmp.g.f1.0 (1) null<1>:d r14.2:d r14.0:d // modified_u_coord = u_coord – 5.0/(256*width); //floating point (f1.0) add (1) r17.2:f r17.2<0;1,0>:f -r2.3:f //else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) (-f1.0) cmp.e.f0.0 (1) null<1>:d r14.3:d r14.0:d // modified_u_coord = u_coord + 1.0/(256*width); //floating point (f0.0) add (1) r17.2:f r17.2<0;1,0>:f r2.2:f GEN7_AVS_WA_DONE_L0_1_: mov (1) f0.0:uw r14.8:uw // restore f0.0 send (1) uwBUFFER_1(0)<1> r16 0x2 a0.0:ud // Returns packed data in 16 GRFs in scrambled order SKIP_AVS_LOAD_L0_1_: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a000066400000000000000000000454111231401140700250410ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 37 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PA_AVS_Buf_2.asm // Author: Vivek Kumar // Description: Loads 8x8 AVS/IEF Packed data into Buffer 2 // FileName : PA_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF Packed data into Buffer N //On IVB, for AVS module - set buffer pointers offset according to AVS Layout. //Change it to Sample Unorm layout in Shuffle modules. // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //Check if layer is to be skipped // f0.1 pre-computed in Set_Layer_0 (-f0.1) jmpi (1) SKIP_AVS_LOAD_L0_2_ //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0:ud r23.5<0;1,0>:ud 0x50EB400:ud //msg desc mov (1) r16.2:ud 0x00000000:ud // Enable ARGB channels // set the vertical block number add (1) r25.1<1>:ud r7.12:uw 2:ud mov (8) r17.0:ud r25.0<8;8,1>:ud // Gen7 AVS WA Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces // if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) // { // modified_u_coord = u_coord – 5.0/(256*width); //floating point // } // else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) // { // modified_u_coord = u_coord + 1.0/(256*width); //floating point // } // else{ // modified_u_coord = u_coord; // } // Where u_left = u – 2*du + 3*ddu for IEF On // And u_left = u for IEF Off case // // check whether Gen7 AVS WA is enabled, mov (1) r14.8:uw f0.0:uw // save f0.0 and.nz.f0.0 (1) null<1>:uw r2.3:uw 0x2:uw (-f0.0)jmpi (1) GEN7_AVS_WA_DONE_L0_2_ // Gen7 AVS WA, check if IEF is ON for choosing Gen7 AVS WA formula and.nz.f0.0 (8) null<1>:uw r2.3<0;1,0>:uw 0x4:uw (f0.0)mov (8) acc0.0:f r17.2<0;1,0>:f (f0.0)mac (8) acc0.0:f r17.4<0;1,0>:f -2.0:f (f0.0)mac (8) acc0.0:f r17.6<0;1,0>:f 3.0:f (f0.0)mov (1) r14.2:f acc0:f // IEF ON, rTEMP3.2 = u_left (-f0.0)mov (1) r14.2:f r17.2<0;1,0>:f // IEF OFF, rTEMP3.2 = u_left and (1) r14.1:ud r2.3:uw 0xFFF8:uw asr (1) r14.1:ud r14.1:ud 3:d mov (1) r14.1:f r14.1:ud // Gen7 AVS WA, if (int)(u_left*width + 5.0/256) > (int)(u_left*width) mul (1) r14.0:f r14.2:f r14.1:f // rTEMP3.0 = u_left*width add (1) r14.2:f r14.0:f 0.01953125:f // rTEMP3.2 = u_left*width + 5.0/256 add (1) r14.3:f r14.0:f 0.99609375:f // rTEMP3.3 = u_left*width + 255.0/256 //Check if the values are < 0 and account for (int) cast of negative numbers //(int)(u_left*width) cmp.l.f0.0 (1) null<1>:f r14.0:f 0.00000000:f mov (1) r14.0:d r14.0:f (f0.0)add (1) r14.0:d r14.0<0;1,0>:d -1:d //(int)(u_left*width + 5.0/256) cmp.l.f0.0 (1) null<1>:f r14.2:f 0.00000000:f mov (1) r14.2:d r14.2:f (f0.0)add (1) r14.2:d r14.2<0;1,0>:d -1:d //(int)(u_left*width + 255.0/256) cmp.l.f0.0 (1) null<1>:f r14.3:f 0.00000000:f mov (1) r14.3:d r14.3:f (f0.0)add (1) r14.3:d r14.3<0;1,0>:d -1:d mov (1) f0.0:uw 0:uw // clear flag //if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) cmp.g.f1.0 (1) null<1>:d r14.2:d r14.0:d // modified_u_coord = u_coord – 5.0/(256*width); //floating point (f1.0) add (1) r17.2:f r17.2<0;1,0>:f -r2.3:f //else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) (-f1.0) cmp.e.f0.0 (1) null<1>:d r14.3:d r14.0:d // modified_u_coord = u_coord + 1.0/(256*width); //floating point (f0.0) add (1) r17.2:f r17.2<0;1,0>:f r2.2:f GEN7_AVS_WA_DONE_L0_2_: mov (1) f0.0:uw r14.8:uw // restore f0.0 send (1) uwBUFFER_2(0)<1> r16 0x2 a0.0:ud // Returns packed data in 16 GRFs in scrambled order SKIP_AVS_LOAD_L0_2_: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a000066400000000000000000000454111231401140700250420ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 37 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PA_AVS_Buf_3.asm // Author: Vivek Kumar // Description: Loads 8x8 AVS/IEF Packed data into Buffer 3 // FileName : PA_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF Packed data into Buffer N //On IVB, for AVS module - set buffer pointers offset according to AVS Layout. //Change it to Sample Unorm layout in Shuffle modules. // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //Check if layer is to be skipped // f0.1 pre-computed in Set_Layer_0 (-f0.1) jmpi (1) SKIP_AVS_LOAD_L0_3_ //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0:ud r23.5<0;1,0>:ud 0x50EB400:ud //msg desc mov (1) r16.2:ud 0x00000000:ud // Enable ARGB channels // set the vertical block number add (1) r25.1<1>:ud r7.12:uw 3:ud mov (8) r17.0:ud r25.0<8;8,1>:ud // Gen7 AVS WA Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces // if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) // { // modified_u_coord = u_coord – 5.0/(256*width); //floating point // } // else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) // { // modified_u_coord = u_coord + 1.0/(256*width); //floating point // } // else{ // modified_u_coord = u_coord; // } // Where u_left = u – 2*du + 3*ddu for IEF On // And u_left = u for IEF Off case // // check whether Gen7 AVS WA is enabled, mov (1) r14.8:uw f0.0:uw // save f0.0 and.nz.f0.0 (1) null<1>:uw r2.3:uw 0x2:uw (-f0.0)jmpi (1) GEN7_AVS_WA_DONE_L0_3_ // Gen7 AVS WA, check if IEF is ON for choosing Gen7 AVS WA formula and.nz.f0.0 (8) null<1>:uw r2.3<0;1,0>:uw 0x4:uw (f0.0)mov (8) acc0.0:f r17.2<0;1,0>:f (f0.0)mac (8) acc0.0:f r17.4<0;1,0>:f -2.0:f (f0.0)mac (8) acc0.0:f r17.6<0;1,0>:f 3.0:f (f0.0)mov (1) r14.2:f acc0:f // IEF ON, rTEMP3.2 = u_left (-f0.0)mov (1) r14.2:f r17.2<0;1,0>:f // IEF OFF, rTEMP3.2 = u_left and (1) r14.1:ud r2.3:uw 0xFFF8:uw asr (1) r14.1:ud r14.1:ud 3:d mov (1) r14.1:f r14.1:ud // Gen7 AVS WA, if (int)(u_left*width + 5.0/256) > (int)(u_left*width) mul (1) r14.0:f r14.2:f r14.1:f // rTEMP3.0 = u_left*width add (1) r14.2:f r14.0:f 0.01953125:f // rTEMP3.2 = u_left*width + 5.0/256 add (1) r14.3:f r14.0:f 0.99609375:f // rTEMP3.3 = u_left*width + 255.0/256 //Check if the values are < 0 and account for (int) cast of negative numbers //(int)(u_left*width) cmp.l.f0.0 (1) null<1>:f r14.0:f 0.00000000:f mov (1) r14.0:d r14.0:f (f0.0)add (1) r14.0:d r14.0<0;1,0>:d -1:d //(int)(u_left*width + 5.0/256) cmp.l.f0.0 (1) null<1>:f r14.2:f 0.00000000:f mov (1) r14.2:d r14.2:f (f0.0)add (1) r14.2:d r14.2<0;1,0>:d -1:d //(int)(u_left*width + 255.0/256) cmp.l.f0.0 (1) null<1>:f r14.3:f 0.00000000:f mov (1) r14.3:d r14.3:f (f0.0)add (1) r14.3:d r14.3<0;1,0>:d -1:d mov (1) f0.0:uw 0:uw // clear flag //if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) cmp.g.f1.0 (1) null<1>:d r14.2:d r14.0:d // modified_u_coord = u_coord – 5.0/(256*width); //floating point (f1.0) add (1) r17.2:f r17.2<0;1,0>:f -r2.3:f //else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) (-f1.0) cmp.e.f0.0 (1) null<1>:d r14.3:d r14.0:d // modified_u_coord = u_coord + 1.0/(256*width); //floating point (f0.0) add (1) r17.2:f r17.2<0;1,0>:f r2.2:f GEN7_AVS_WA_DONE_L0_3_: mov (1) f0.0:uw r14.8:uw // restore f0.0 send (1) uwBUFFER_3(0)<1> r16 0x2 a0.0:ud // Returns packed data in 16 GRFs in scrambled order SKIP_AVS_LOAD_L0_3_: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/PA_DI_422CP.g4a000066400000000000000000000501311231401140700244740ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 87 // Total instruction count // 1 // Total kernel count .kernel PA_DI_422CP .code // FileName: DI.asm // Author: Vivek Kumar // Description: Tasks for DI only case (16x4 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x4AE8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(9,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DI_STMM_Save.asm // Author: Vivek Kumar // Description: Saves DI STMM Data to statistics surface in case of DI enabled (for 16x4 block) // Write STMM to memory mov (8) mudMSGHDR_STMM(0)<1> r0.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udDNDI_RESP(8,0) // Move STMM to MRF shr (1) mudMSGHDR_STMM(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin / 2 mov (1) mudMSGHDR_STMM(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_STMM(0,2)<1> 0x30007:ud { NoDDChk } // block width and height (8x4) send (8) null<1>:d r20 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x20007:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | MCNT | FCNT | TCNT | X | X | X | X | //---------------------------------------------------- //| DcTpT | SVCM | DcBpT | DcTpB | //---------------------------------------------------- //| SHCM | STAD | DcTcB | DcBpB | //---------------------------------------------------- mov (1) mudMSGHDR_ENC_STATS(1,0)<1> udDNDI_RESP(9,1)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,3)<2> udDNDI_RESP(9,3)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,2)<2> udDNDI_RESP(9,5)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DI_Save_422CP_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in 422 format to Color Pipe (IECP) .declare mubMSGHDR_DI_OUT1_1 Base=r18.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT1_2 Base=r21.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT2_1 Base=r24.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT2_2 Base=r27.0 ElementSize=1 Type=ub mov (8) r27.0<1>:ud r0.0<8;8,1>:ud shl (1) r27.0<1>:ud r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be doubled mov (1) r27.1<1>:ud r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) r27.2<1>:ud 0x3000F:ud { NoDDClr, NoDDChk } // Block width and height (16x8) //M0.3 - 0 - CP Enable, 1 - Area of Interest, 3:2 Message Format(TBD), 4:3 - Ignored, 31:5 CP state pointer //Compose area-of-interest bit + color pipe state pointer or (1) r27.3<1>:ud r2.4<0;1,0>:ud r7.26<0;1,0>:b { NoDDChk } //prepare the message headers mov (8) r18.0<1>:ud r27<8;8,1>:ud mov (8) r24.0<1>:ud r27<8;8,1>:ud // Pack 2nd field Y; First 8x4 block mov (8) mubMSGHDR_DI_OUT1_1(1)<2> ubDNDI_RESP(0,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(1,16)<2> ubDNDI_RESP(0,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(2)<2> ubDNDI_RESP(0,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(2,16)<2> ubDNDI_RESP(0,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 2nd field U, V; First 8x4 block mov (4) mubMSGHDR_DI_OUT1_1(1,1)<4> ubDNDI_RESP(2,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,17)<4> ubDNDI_RESP(2,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,3)<4> ubDNDI_RESP(2,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,19)<4> ubDNDI_RESP(2,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,1)<4> ubDNDI_RESP(2,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,17)<4> ubDNDI_RESP(2,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,3)<4> ubDNDI_RESP(2,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,19)<4> ubDNDI_RESP(2,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Pack 2nd field Y; Second 8x4 block mov (8) r21.0<1>:ud r18.0<8;8,1>:ud add (1) r21.0<1>:ud r21.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DI_OUT1_2(1)<2> ubDNDI_RESP(0,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(1,16)<2> ubDNDI_RESP(0,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(2)<2> ubDNDI_RESP(0,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(2,16)<2> ubDNDI_RESP(0,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 2nd field U, V; Second 8x4 block mov (4) mubMSGHDR_DI_OUT1_2(1,1)<4> ubDNDI_RESP(2,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,17)<4> ubDNDI_RESP(2,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,3)<4> ubDNDI_RESP(2,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,19)<4> ubDNDI_RESP(2,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,1)<4> ubDNDI_RESP(2,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,17)<4> ubDNDI_RESP(2,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,3)<4> ubDNDI_RESP(2,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,19)<4> ubDNDI_RESP(2,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization send (8) null<1>:d r18.0 0x5 0x60A801B:ud send (8) null<1>:d r21.0 0x5 0x60A801B:ud // Pack 1st field Y; 1st 8x4 block mov (8) mubMSGHDR_DI_OUT2_1(1)<2> ubDNDI_RESP(4,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(1,16)<2> ubDNDI_RESP(4,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(2)<2> ubDNDI_RESP(4,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(2,16)<2> ubDNDI_RESP(4,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 1st field U,V; 1st 8x4 block mov (4) mubMSGHDR_DI_OUT2_1(1,1)<4> ubDNDI_RESP(6,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,17)<4> ubDNDI_RESP(6,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,3)<4> ubDNDI_RESP(6,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,19)<4> ubDNDI_RESP(6,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,1)<4> ubDNDI_RESP(6,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,17)<4> ubDNDI_RESP(6,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,3)<4> ubDNDI_RESP(6,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,19)<4> ubDNDI_RESP(6,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Pack 1st field Y; 2nd 8x4 block mov (8) r27.0<1>:ud r24.0<8;8,1>:ud add (1) r27.0<1>:ud r27.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DI_OUT2_2(1)<2> ubDNDI_RESP(4,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(1,16)<2> ubDNDI_RESP(4,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(2)<2> ubDNDI_RESP(4,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(2,16)<2> ubDNDI_RESP(4,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 1st field U, V; 2nd 8x4 block mov (4) mubMSGHDR_DI_OUT2_2(1,1)<4> ubDNDI_RESP(6,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,17)<4> ubDNDI_RESP(6,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,3)<4> ubDNDI_RESP(6,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,19)<4> ubDNDI_RESP(6,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,1)<4> ubDNDI_RESP(6,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,17)<4> ubDNDI_RESP(6,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,3)<4> ubDNDI_RESP(6,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,19)<4> ubDNDI_RESP(6,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization send (8) null<1>:d r24.0 0x5 0x60A801E:ud send (8) null<1>:d r27.0 0x5 0x60A801E:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PA_DI_PA.g4a000066400000000000000000000354061231401140700242520ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 57 // Total instruction count // 1 // Total kernel count .kernel PA_DI_PA .code // FileName: DI.asm // Author: Vivek Kumar // Description: Tasks for DI only case (16x4 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x4AE8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(9,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DI_STMM_Save.asm // Author: Vivek Kumar // Description: Saves DI STMM Data to statistics surface in case of DI enabled (for 16x4 block) // Write STMM to memory mov (8) mudMSGHDR_STMM(0)<1> r0.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udDNDI_RESP(8,0) // Move STMM to MRF shr (1) mudMSGHDR_STMM(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin / 2 mov (1) mudMSGHDR_STMM(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_STMM(0,2)<1> 0x30007:ud { NoDDChk } // block width and height (8x4) send (8) null<1>:d r20 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x20007:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | MCNT | FCNT | TCNT | X | X | X | X | //---------------------------------------------------- //| DcTpT | SVCM | DcBpT | DcTpB | //---------------------------------------------------- //| SHCM | STAD | DcTcB | DcBpB | //---------------------------------------------------- mov (1) mudMSGHDR_ENC_STATS(1,0)<1> udDNDI_RESP(9,1)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,3)<2> udDNDI_RESP(9,3)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,2)<2> udDNDI_RESP(9,5)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DI_Save_PA_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in Packed format add (4) a0.4<1>:uw r2.28<4;4,1>:ub 608:w // Initial Y,U,V offset in YUV422 block; it starts at m20 mov (8) r27.0<1>:ud r0.0<8;8,1>:ud shl (1) r27.0<1>:d r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be doubled mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) r27.2<1>:ud 0x3001F:ud { NoDDChk } // Block width and height (32x8) //prepare the message headers mov (8) r18.0<1>:ud r27<8;8,1>:ud mov (8) r23.0<1>:ud r27<8;8,1>:ud // Pack 2nd field Y mov (16) r[a0.4, 0]<2> ubDNDI_RESP(0,0) { NoDDClr } mov (16) r[a0.4, 32]<2> ubDNDI_RESP(0,16) { NoDDClr } mov (16) r[a0.4, 64]<2> ubDNDI_RESP(0,32) { NoDDClr } mov (16) r[a0.4, 96]<2> ubDNDI_RESP(0,48) { NoDDClr } // Pack 2nd field U mov (8) r[a0.5, 0]<4> ubDNDI_RESP(2,1)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 32]<4> ubDNDI_RESP(2,17)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 64]<4> ubDNDI_RESP(2,33)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 96]<4> ubDNDI_RESP(2,49)<16;8,2> { NoDDClr, NoDDChk } //U pixels // Pack 2nd field V mov (8) r[a0.6, 0]<4> ubDNDI_RESP(2,0)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 32]<4> ubDNDI_RESP(2,16)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 64]<4> ubDNDI_RESP(2,32)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 96]<4> ubDNDI_RESP(2,48)<16;8,2> { NoDDChk } //Vpixels // Pack 1st field Y mov (16) r[a0.4, 160]<2> ubDNDI_RESP(4,0) { NoDDClr } mov (16) r[a0.4, 192]<2> ubDNDI_RESP(4,16) { NoDDClr } mov (16) r[a0.4, 224]<2> ubDNDI_RESP(4,32) { NoDDClr } mov (16) r[a0.4, 256]<2> ubDNDI_RESP(4,48) { NoDDClr } // Pack 1st field U mov (8) r[a0.5, 160]<4> ubDNDI_RESP(6,1)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 192]<4> ubDNDI_RESP(6,17)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 224]<4> ubDNDI_RESP(6,33)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 256]<4> ubDNDI_RESP(6,49)<16;8,2> { NoDDClr, NoDDChk } //U pixels // Pack 1st field V mov (8) r[a0.6, 160]<4> ubDNDI_RESP(6,0)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 192]<4> ubDNDI_RESP(6,16)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 224]<4> ubDNDI_RESP(6,32)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 256]<4> ubDNDI_RESP(6,48)<16;8,2> { NoDDChk } //Vpixels //save the previous frame send (8) null<1>:d r18.0 0x5 0xA0A801B:ud //save the current frame send (8) null<1>:d r23.0 0x5 0xA0A801E:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PA_DNDI_422CP.g4a000066400000000000000000000611471231401140700247270ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 127 // Total instruction count // 1 // Total kernel count .kernel PA_DNDI_422CP .code // FileName: DNDI_PL_Core.asm // Author: Tatiya, Rupesh // FileName: DNDI_Core.asm // Author: Vivek Kumar // Description: Tasks for DN+DI case (16x4 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x4CE8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(9,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DI_STMM_Save.asm // Author: Vivek Kumar // Description: Saves DI STMM Data to statistics surface in case of DI enabled (for 16x4 block) // Write STMM to memory mov (8) mudMSGHDR_STMM(0)<1> r0.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udDNDI_RESP(8,0) // Move STMM to MRF shr (1) mudMSGHDR_STMM(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin / 2 mov (1) mudMSGHDR_STMM(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_STMM(0,2)<1> 0x30007:ud { NoDDChk } // block width and height (8x4) send (8) null<1>:d r20 0x5 0x40A8021:ud // FileName: DN_Hist_Save.asm // Author: Vivek Kumar // Description: Saves DN history data to statistics surface // Write denoise history to memory mov (8) r27<1>:ud r0.0<8;8,1>:ud // message header mov (1) mudMSGHDR_HIST(1)<1> udDNDI_RESP(9,0)<0;1,0> // Move denoise history to MRF (4x1) shr (2) r27.0<1>:ud r7.0<2;2,1>:w 2:w // X,Y origin / 4 add (1) r27.0<1>:ud r27.0<0;1,0>:ud r1.12<0;1,0>:uw { NoDDClr } // Add pitch to X origin mov (1) r27.2<1>:ud 0x3:ud { NoDDChk } // block width and height mov (8) mudMSGHDR_HIST(0)<1> r27.0<8;8,1>:ud send (8) null<1>:d r22 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x20007:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | MCNT | FCNT | TCNT | X | X | X | X | //---------------------------------------------------- //| DcTpT | SVCM | DcBpT | DcTpB | //---------------------------------------------------- //| SHCM | STAD | DcTcB | DcBpB | //---------------------------------------------------- mov (1) mudMSGHDR_ENC_STATS(1,0)<1> udDNDI_RESP(9,1)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,3)<2> udDNDI_RESP(9,3)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,2)<2> udDNDI_RESP(9,5)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DN_Save_PA_16x4.asm // Author: Vivek Kumar // Description: Save one 16x4 blocks of DN output in Packed format for reference // check top/bottom field first cmp.e.f0.0 (1) null<1>:w r1.28<0;1,0>:ub 1:w add (4) a0.4<1>:uw r4.0<4;4,1>:ub 1024:w // Initial Y,U,V offset in YUV422 block; it starts at m14 mov (8) mudMSGHDR_DN_OUT(0)<1> r0<8;8,1>:ud // message header shl (1) mdMSGHDR_DN_OUT(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin * 2 (422 output) mov (1) mdMSGHDR_DN_OUT(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_DN_OUT(0,2)<1> 0x3001F:ud { NoDDChk } // block width and height (32x8) (f0.0) jmpi (1) TOP_FIELD_FIRST BOTTOM_FIELD_FIRST: mov (16) r[a0.4, 0]<2>:ub ubDNDI_RESP(10,0) { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (16) r[a0.4, 32]<2>:ub ubDNDI_RESP(4,16) { NoDDClr } // 1st field luma from current frame (line 1,3) mov (16) r[a0.4, 64]<2>:ub ubDNDI_RESP(10,16) { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (16) r[a0.4, 96]<2>:ub ubDNDI_RESP(5,16) { NoDDClr } // 1st field luma from current frame (line 1,3) mov (8) r[a0.5, 0]<4>:ub ubDNDI_RESP(11,1)<16;8,2> { NoDDClr, NoDDChk } // 2nd field U from current frame (line 0,2) mov (8) r[a0.5, 32]<4>:ub ubDNDI_RESP(6,17)<16;8,2> { NoDDClr, NoDDChk } // 1st field U from current frame (line 1,3) mov (8) r[a0.5, 64]<4>:ub ubDNDI_RESP(11,17)<16;8,2> { NoDDClr, NoDDChk } // 2nd field U from current frame (line 0,2) mov (8) r[a0.5, 96]<4>:ub ubDNDI_RESP(7,17)<16;8,2> { NoDDClr, NoDDChk } // 1st field U from current frame (line 1,3) mov (8) r[a0.6, 0]<4>:ub ubDNDI_RESP(11,0)<16;8,2> { NoDDChk } // 2nd field V from current frame (line 0,2) mov (8) r[a0.6, 32]<4>:ub ubDNDI_RESP(6,16)<16;8,2> { NoDDChk } // 1st field U from current frame (line 1,3) mov (8) r[a0.6, 64]<4>:ub ubDNDI_RESP(11,16)<16;8,2> { NoDDChk } // 2nd field V from current frame (line 0,2) mov (8) r[a0.6, 96]<4>:ub ubDNDI_RESP(7,16)<16;8,2> { NoDDChk } // 1st field U from current frame (line 1,3) jmpi (1) SAVE_DN_CURR TOP_FIELD_FIRST: mov (16) r[a0.4, 0]<2>:ub ubDNDI_RESP(4,0) { NoDDClr } // 1st field luma from current frame (line 0,2) mov (16) r[a0.4, 32]<2>:ub ubDNDI_RESP(10,0) { NoDDClr } // 2nd field luma from current frame (line 1,3) mov (16) r[a0.4, 64]<2>:ub ubDNDI_RESP(5,0) { NoDDClr } // 1st field luma from current frame (line 0,2) mov (16) r[a0.4, 96]<2>:ub ubDNDI_RESP(10,16) { NoDDClr } // 2nd field luma from current frame (line 1,3) mov (8) r[a0.5, 0]<4>:ub ubDNDI_RESP(6,1)<16;8,2> { NoDDClr, NoDDChk } // 1st field U from current frame (line 0,2) mov (8) r[a0.5, 32]<4>:ub ubDNDI_RESP(11,1)<16;8,2> { NoDDClr, NoDDChk } // 2nd field U from current frame (line 1,3) mov (8) r[a0.5, 64]<4>:ub ubDNDI_RESP(7,1)<16;8,2> { NoDDClr, NoDDChk } // 1st field U from current frame (line 0,2) mov (8) r[a0.5, 96]<4>:ub ubDNDI_RESP(11,17)<16;8,2> { NoDDClr, NoDDChk } // 2nd field U from current frame (line 1,3) mov (8) r[a0.6, 0]<4>:ub ubDNDI_RESP(6,0)<16;8,2> { NoDDChk } // 1st field V from current frame (line 0,2) mov (8) r[a0.6, 32]<4>:ub ubDNDI_RESP(11,0)<16;8,2> { NoDDChk } // 2nd field V from current frame (line 1,3) mov (8) r[a0.6, 64]<4>:ub ubDNDI_RESP(7,0)<16;8,2> { NoDDChk } // 1st field V from current frame (line 0,2) mov (8) r[a0.6, 96]<4>:ub ubDNDI_RESP(11,16)<16;8,2> { NoDDChk } // 2nd field V from current frame (line 1,3) SAVE_DN_CURR: //send out data through data port send (8) null<1>:d r31.0 0x5 0xA0A8018:ud // FileName: DI_Save_422CP_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in 422 format to Color Pipe (IECP) .declare mubMSGHDR_DI_OUT1_1 Base=r18.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT1_2 Base=r21.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT2_1 Base=r24.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT2_2 Base=r27.0 ElementSize=1 Type=ub mov (8) r27.0<1>:ud r0.0<8;8,1>:ud shl (1) r27.0<1>:ud r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be doubled mov (1) r27.1<1>:ud r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) r27.2<1>:ud 0x3000F:ud { NoDDClr, NoDDChk } // Block width and height (16x8) //M0.3 - 0 - CP Enable, 1 - Area of Interest, 3:2 Message Format(TBD), 4:3 - Ignored, 31:5 CP state pointer //Compose area-of-interest bit + color pipe state pointer or (1) r27.3<1>:ud r2.4<0;1,0>:ud r7.26<0;1,0>:b { NoDDChk } //prepare the message headers mov (8) r18.0<1>:ud r27<8;8,1>:ud mov (8) r24.0<1>:ud r27<8;8,1>:ud // Pack 2nd field Y; First 8x4 block mov (8) mubMSGHDR_DI_OUT1_1(1)<2> ubDNDI_RESP(0,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(1,16)<2> ubDNDI_RESP(0,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(2)<2> ubDNDI_RESP(0,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(2,16)<2> ubDNDI_RESP(0,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 2nd field U, V; First 8x4 block mov (4) mubMSGHDR_DI_OUT1_1(1,1)<4> ubDNDI_RESP(2,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,17)<4> ubDNDI_RESP(2,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,3)<4> ubDNDI_RESP(2,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,19)<4> ubDNDI_RESP(2,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,1)<4> ubDNDI_RESP(2,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,17)<4> ubDNDI_RESP(2,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,3)<4> ubDNDI_RESP(2,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,19)<4> ubDNDI_RESP(2,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Pack 2nd field Y; Second 8x4 block mov (8) r21.0<1>:ud r18.0<8;8,1>:ud add (1) r21.0<1>:ud r21.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DI_OUT1_2(1)<2> ubDNDI_RESP(0,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(1,16)<2> ubDNDI_RESP(0,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(2)<2> ubDNDI_RESP(0,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(2,16)<2> ubDNDI_RESP(0,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 2nd field U, V; Second 8x4 block mov (4) mubMSGHDR_DI_OUT1_2(1,1)<4> ubDNDI_RESP(2,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,17)<4> ubDNDI_RESP(2,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,3)<4> ubDNDI_RESP(2,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,19)<4> ubDNDI_RESP(2,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,1)<4> ubDNDI_RESP(2,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,17)<4> ubDNDI_RESP(2,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,3)<4> ubDNDI_RESP(2,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,19)<4> ubDNDI_RESP(2,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization send (8) null<1>:d r18.0 0x5 0x60A801B:ud send (8) null<1>:d r21.0 0x5 0x60A801B:ud // Pack 1st field Y; 1st 8x4 block mov (8) mubMSGHDR_DI_OUT2_1(1)<2> ubDNDI_RESP(4,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(1,16)<2> ubDNDI_RESP(4,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(2)<2> ubDNDI_RESP(4,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(2,16)<2> ubDNDI_RESP(4,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 1st field U,V; 1st 8x4 block mov (4) mubMSGHDR_DI_OUT2_1(1,1)<4> ubDNDI_RESP(6,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,17)<4> ubDNDI_RESP(6,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,3)<4> ubDNDI_RESP(6,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,19)<4> ubDNDI_RESP(6,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,1)<4> ubDNDI_RESP(6,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,17)<4> ubDNDI_RESP(6,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,3)<4> ubDNDI_RESP(6,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,19)<4> ubDNDI_RESP(6,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Pack 1st field Y; 2nd 8x4 block mov (8) r27.0<1>:ud r24.0<8;8,1>:ud add (1) r27.0<1>:ud r27.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DI_OUT2_2(1)<2> ubDNDI_RESP(4,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(1,16)<2> ubDNDI_RESP(4,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(2)<2> ubDNDI_RESP(4,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(2,16)<2> ubDNDI_RESP(4,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 1st field U, V; 2nd 8x4 block mov (4) mubMSGHDR_DI_OUT2_2(1,1)<4> ubDNDI_RESP(6,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,17)<4> ubDNDI_RESP(6,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,3)<4> ubDNDI_RESP(6,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,19)<4> ubDNDI_RESP(6,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,1)<4> ubDNDI_RESP(6,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,17)<4> ubDNDI_RESP(6,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,3)<4> ubDNDI_RESP(6,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,19)<4> ubDNDI_RESP(6,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization send (8) null<1>:d r24.0 0x5 0x60A801E:ud send (8) null<1>:d r27.0 0x5 0x60A801E:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PA_DNDI_PA.g4a000066400000000000000000000464241231401140700244760ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 97 // Total instruction count // 1 // Total kernel count .kernel PA_DNDI_PA .code // FileName: DNDI_PL_Core.asm // Author: Tatiya, Rupesh // FileName: DNDI_Core.asm // Author: Vivek Kumar // Description: Tasks for DN+DI case (16x4 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x4CE8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(9,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DI_STMM_Save.asm // Author: Vivek Kumar // Description: Saves DI STMM Data to statistics surface in case of DI enabled (for 16x4 block) // Write STMM to memory mov (8) mudMSGHDR_STMM(0)<1> r0.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udDNDI_RESP(8,0) // Move STMM to MRF shr (1) mudMSGHDR_STMM(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin / 2 mov (1) mudMSGHDR_STMM(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_STMM(0,2)<1> 0x30007:ud { NoDDChk } // block width and height (8x4) send (8) null<1>:d r20 0x5 0x40A8021:ud // FileName: DN_Hist_Save.asm // Author: Vivek Kumar // Description: Saves DN history data to statistics surface // Write denoise history to memory mov (8) r27<1>:ud r0.0<8;8,1>:ud // message header mov (1) mudMSGHDR_HIST(1)<1> udDNDI_RESP(9,0)<0;1,0> // Move denoise history to MRF (4x1) shr (2) r27.0<1>:ud r7.0<2;2,1>:w 2:w // X,Y origin / 4 add (1) r27.0<1>:ud r27.0<0;1,0>:ud r1.12<0;1,0>:uw { NoDDClr } // Add pitch to X origin mov (1) r27.2<1>:ud 0x3:ud { NoDDChk } // block width and height mov (8) mudMSGHDR_HIST(0)<1> r27.0<8;8,1>:ud send (8) null<1>:d r22 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x20007:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | MCNT | FCNT | TCNT | X | X | X | X | //---------------------------------------------------- //| DcTpT | SVCM | DcBpT | DcTpB | //---------------------------------------------------- //| SHCM | STAD | DcTcB | DcBpB | //---------------------------------------------------- mov (1) mudMSGHDR_ENC_STATS(1,0)<1> udDNDI_RESP(9,1)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,3)<2> udDNDI_RESP(9,3)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,2)<2> udDNDI_RESP(9,5)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DN_Save_PA_16x4.asm // Author: Vivek Kumar // Description: Save one 16x4 blocks of DN output in Packed format for reference // check top/bottom field first cmp.e.f0.0 (1) null<1>:w r1.28<0;1,0>:ub 1:w add (4) a0.4<1>:uw r4.0<4;4,1>:ub 1024:w // Initial Y,U,V offset in YUV422 block; it starts at m14 mov (8) mudMSGHDR_DN_OUT(0)<1> r0<8;8,1>:ud // message header shl (1) mdMSGHDR_DN_OUT(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin * 2 (422 output) mov (1) mdMSGHDR_DN_OUT(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_DN_OUT(0,2)<1> 0x3001F:ud { NoDDChk } // block width and height (32x8) (f0.0) jmpi (1) TOP_FIELD_FIRST BOTTOM_FIELD_FIRST: mov (16) r[a0.4, 0]<2>:ub ubDNDI_RESP(10,0) { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (16) r[a0.4, 32]<2>:ub ubDNDI_RESP(4,16) { NoDDClr } // 1st field luma from current frame (line 1,3) mov (16) r[a0.4, 64]<2>:ub ubDNDI_RESP(10,16) { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (16) r[a0.4, 96]<2>:ub ubDNDI_RESP(5,16) { NoDDClr } // 1st field luma from current frame (line 1,3) mov (8) r[a0.5, 0]<4>:ub ubDNDI_RESP(11,1)<16;8,2> { NoDDClr, NoDDChk } // 2nd field U from current frame (line 0,2) mov (8) r[a0.5, 32]<4>:ub ubDNDI_RESP(6,17)<16;8,2> { NoDDClr, NoDDChk } // 1st field U from current frame (line 1,3) mov (8) r[a0.5, 64]<4>:ub ubDNDI_RESP(11,17)<16;8,2> { NoDDClr, NoDDChk } // 2nd field U from current frame (line 0,2) mov (8) r[a0.5, 96]<4>:ub ubDNDI_RESP(7,17)<16;8,2> { NoDDClr, NoDDChk } // 1st field U from current frame (line 1,3) mov (8) r[a0.6, 0]<4>:ub ubDNDI_RESP(11,0)<16;8,2> { NoDDChk } // 2nd field V from current frame (line 0,2) mov (8) r[a0.6, 32]<4>:ub ubDNDI_RESP(6,16)<16;8,2> { NoDDChk } // 1st field U from current frame (line 1,3) mov (8) r[a0.6, 64]<4>:ub ubDNDI_RESP(11,16)<16;8,2> { NoDDChk } // 2nd field V from current frame (line 0,2) mov (8) r[a0.6, 96]<4>:ub ubDNDI_RESP(7,16)<16;8,2> { NoDDChk } // 1st field U from current frame (line 1,3) jmpi (1) SAVE_DN_CURR TOP_FIELD_FIRST: mov (16) r[a0.4, 0]<2>:ub ubDNDI_RESP(4,0) { NoDDClr } // 1st field luma from current frame (line 0,2) mov (16) r[a0.4, 32]<2>:ub ubDNDI_RESP(10,0) { NoDDClr } // 2nd field luma from current frame (line 1,3) mov (16) r[a0.4, 64]<2>:ub ubDNDI_RESP(5,0) { NoDDClr } // 1st field luma from current frame (line 0,2) mov (16) r[a0.4, 96]<2>:ub ubDNDI_RESP(10,16) { NoDDClr } // 2nd field luma from current frame (line 1,3) mov (8) r[a0.5, 0]<4>:ub ubDNDI_RESP(6,1)<16;8,2> { NoDDClr, NoDDChk } // 1st field U from current frame (line 0,2) mov (8) r[a0.5, 32]<4>:ub ubDNDI_RESP(11,1)<16;8,2> { NoDDClr, NoDDChk } // 2nd field U from current frame (line 1,3) mov (8) r[a0.5, 64]<4>:ub ubDNDI_RESP(7,1)<16;8,2> { NoDDClr, NoDDChk } // 1st field U from current frame (line 0,2) mov (8) r[a0.5, 96]<4>:ub ubDNDI_RESP(11,17)<16;8,2> { NoDDClr, NoDDChk } // 2nd field U from current frame (line 1,3) mov (8) r[a0.6, 0]<4>:ub ubDNDI_RESP(6,0)<16;8,2> { NoDDChk } // 1st field V from current frame (line 0,2) mov (8) r[a0.6, 32]<4>:ub ubDNDI_RESP(11,0)<16;8,2> { NoDDChk } // 2nd field V from current frame (line 1,3) mov (8) r[a0.6, 64]<4>:ub ubDNDI_RESP(7,0)<16;8,2> { NoDDChk } // 1st field V from current frame (line 0,2) mov (8) r[a0.6, 96]<4>:ub ubDNDI_RESP(11,16)<16;8,2> { NoDDChk } // 2nd field V from current frame (line 1,3) SAVE_DN_CURR: //send out data through data port send (8) null<1>:d r31.0 0x5 0xA0A8018:ud // FileName: DI_Save_PA_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in Packed format add (4) a0.4<1>:uw r2.28<4;4,1>:ub 608:w // Initial Y,U,V offset in YUV422 block; it starts at m20 mov (8) r27.0<1>:ud r0.0<8;8,1>:ud shl (1) r27.0<1>:d r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be doubled mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) r27.2<1>:ud 0x3001F:ud { NoDDChk } // Block width and height (32x8) //prepare the message headers mov (8) r18.0<1>:ud r27<8;8,1>:ud mov (8) r23.0<1>:ud r27<8;8,1>:ud // Pack 2nd field Y mov (16) r[a0.4, 0]<2> ubDNDI_RESP(0,0) { NoDDClr } mov (16) r[a0.4, 32]<2> ubDNDI_RESP(0,16) { NoDDClr } mov (16) r[a0.4, 64]<2> ubDNDI_RESP(0,32) { NoDDClr } mov (16) r[a0.4, 96]<2> ubDNDI_RESP(0,48) { NoDDClr } // Pack 2nd field U mov (8) r[a0.5, 0]<4> ubDNDI_RESP(2,1)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 32]<4> ubDNDI_RESP(2,17)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 64]<4> ubDNDI_RESP(2,33)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 96]<4> ubDNDI_RESP(2,49)<16;8,2> { NoDDClr, NoDDChk } //U pixels // Pack 2nd field V mov (8) r[a0.6, 0]<4> ubDNDI_RESP(2,0)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 32]<4> ubDNDI_RESP(2,16)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 64]<4> ubDNDI_RESP(2,32)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 96]<4> ubDNDI_RESP(2,48)<16;8,2> { NoDDChk } //Vpixels // Pack 1st field Y mov (16) r[a0.4, 160]<2> ubDNDI_RESP(4,0) { NoDDClr } mov (16) r[a0.4, 192]<2> ubDNDI_RESP(4,16) { NoDDClr } mov (16) r[a0.4, 224]<2> ubDNDI_RESP(4,32) { NoDDClr } mov (16) r[a0.4, 256]<2> ubDNDI_RESP(4,48) { NoDDClr } // Pack 1st field U mov (8) r[a0.5, 160]<4> ubDNDI_RESP(6,1)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 192]<4> ubDNDI_RESP(6,17)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 224]<4> ubDNDI_RESP(6,33)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 256]<4> ubDNDI_RESP(6,49)<16;8,2> { NoDDClr, NoDDChk } //U pixels // Pack 1st field V mov (8) r[a0.6, 160]<4> ubDNDI_RESP(6,0)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 192]<4> ubDNDI_RESP(6,16)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 224]<4> ubDNDI_RESP(6,32)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 256]<4> ubDNDI_RESP(6,48)<16;8,2> { NoDDChk } //Vpixels //save the previous frame send (8) null<1>:d r18.0 0x5 0xA0A801B:ud //save the current frame send (8) null<1>:d r23.0 0x5 0xA0A801E:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PA_DNUV_PA.g4a000066400000000000000000003567451231401140700245460ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 1319 // Total instruction count // 1 // Total kernel count .kernel YUY2_DNUV_YUY2 .code //Module : DN_UV_Setup //Author : Tatiya, Rupesh //Description : Initial Set-up for DN_UV // Module name : ChromaDenoise.inc // Author : Tatiya, Rupesh // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Interface: //Static Parameters: //r1 //====================================================== //Interface for serpent mode Chroma Denoise, added by Le //====================================================== //r1 //noise history thresholds (low and high) //temporal difference thresholds (high and low) //noise history thresholds (low and high) //#define ubNoiseHistMaxHigh r1.22 //#define ubNoiseHistMaxLow r1.23 //#define ubNoiseHistDeltaHigh r1.24 //#define ubNoiseHistDeltaLow r1.25 //Gaussian thresholds //temporal difference thresholds (default) //r2 //history thresholds (default) //denoise factor (0-63) //====================== Binding table (Explicit To DNUV)========================================= //Used by DN_UV kernels //Pointer to Current Frame UV //r1-r6 //CURBE GRFs used as TEMP : Used for max computation and storing max temporarily. : r1-r6 .declare ubCURBE_TEMP Base=r1.0 ElementSize=1 Type=ub .declare uwCURBE_TEMP Base=r1.0 ElementSize=2 Type=uw .declare wCURBE_TEMP Base=r1.0 ElementSize=2 Type=w .declare fCURBE_TEMP Base=r1.0 ElementSize=4 Type=f .declare udCURBE_TEMP Base=r1.0 ElementSize=4 Type=ud .declare uwMAX_ABS_DIFF Base=r5.0 ElementSize=2 Type=uw //r1 //r3 //r4 //r7 //All of the following has to defined in Same GRF for optimal performance. //r8-24 //Previous Frame UV .declare udPREV_UV Base=r8.0 ElementSize=4 Type=ud .declare ubPREV_UV Base=r8.0 ElementSize=1 Type=ub //r25-48 //TEMP Space for any Usage. //========================================================================= //Definations and declarations for serpent mode Chroma Denoise, added by Le //========================================================================= .declare udGNE_UV Base=r24.0 ElementSize=4 Type=ud .declare fGNE_UV Base=r24.0 ElementSize=4 Type=f .declare ubGNE_UV Base=r24.0 ElementSize=1 Type=ub .declare udMSGHDR_BNE_SERP Base=r25.0 ElementSize=4 Type=ud .declare udMSGSRC_BNE_SERP Base=r26.0 ElementSize=4 Type=ud .declare ubDN_UV_Thresholds Base=r26.0 ElementSize=1 Type=ub .declare ubDN_UV_Thresholds_Temp Base=r27.0 ElementSize=1 Type=ub .declare udDN_UV_Thresholds Base=r26.0 ElementSize=4 Type=ud .declare udDN_UV_Thresholds_Temp Base=r27.0 ElementSize=4 Type=ud .declare fDN_UV_Thresholds Base=r26.0 ElementSize=4 Type=f .declare fDN_UV_Thresholds_Temp Base=r27.0 ElementSize=4 Type=f //==================================================================================== //TEMP23: To hold V data for PL3 surfaces .declare udCURR_V_TEMP Base=r25.0 ElementSize=4 Type=ud .declare ubCURR_V_TEMP Base=r25.0 ElementSize=1 Type=ub //GRFs to calculate Median: r25-r42 .declare ubMEDIAN_TEMP Base=r25.0 ElementSize=1 Type=ub //18 GRFs to hold difference : r25-r42 .declare wDIFF Base=r25.0 ElementSize=2 Type=w .declare uwDIFF Base=r25.0 ElementSize=2 Type=uw //Temporal Diff .declare wDIFF_TEMPORAL Base=r25.0 ElementSize=2 Type=w .declare ubDIFF_TEMPORAL Base=r25.0 ElementSize=1 Type=ub //4 GRFs to hold Sobel Value : r43-46 .declare wSOBEL_X Base=r43.0 ElementSize=2 Type=w .declare uwSOBEL Base=r43.0 ElementSize=2 Type=uw //2 GRFs to hold SOAD temporarily: r47-48 .declare uwSOAD Base=r47.0 ElementSize=2 Type=uw //Temp GRFs to hold extra YUYV pixels: r43-r48 .declare ubTEMP5 Base=r43.0 ElementSize=1 Type=ub //Temp GRFs in Median Calculation: r47-r48 .declare ubTEMP1 Base=r47.0 ElementSize=1 Type=ub .declare uwTEMP0 Base=r48.0 ElementSize=2 Type=uw .declare ubTEMP0 Base=r48.0 ElementSize=1 Type=ub //Temp Space to store Median : r49-50 .declare ubMEDIAN Base=r49.0 ElementSize=1 Type=ub //r49 //r50 //Message Source //r51 //DN_UV History Surface .declare udHIST_UV Base=r51.0 ElementSize=4 Type=ud .declare ubHIST_UV Base=r51.0 ElementSize=1 Type=ub //r52 - r91 //r52 //Current Frame UV .declare udCURR_UV Base=r52.0 ElementSize=4 Type=ud .declare ubCURR_UV Base=r52.0 ElementSize=1 Type=ub //r54 //CURBE COPY //r55 .declare uwSOAD_MIN_8x4 Base=r56.0 ElementSize=2 Type=uw //r61 //r62 //History Surface Temp Origin //r63 //Current Frame Y Temp Origin //BNE Surface Origin //r70 .declare uwDIFF_TEMPORAL_SUM4x4 Base=r70.0 ElementSize=2 Type=uw //4 GRFs //r74-91 : For Saving Dest UV (PL2/PL3) .declare ubMSGPAYLOAD_UV0 Base=r75.0 ElementSize=1 Type=ub .declare ubMSGPAYLOAD_U Base=r75.0 ElementSize=1 Type=ub .declare ubMSGPAYLOAD_UV1 Base=r84.0 ElementSize=1 Type=ub .declare ubMSGPAYLOAD_V Base=r84.0 ElementSize=1 Type=ub //r90 .declare uwDIFF_TEMPORAL_SUM4x4_FINAL Base=r90.0 ElementSize=2 Type=uw //2 GRFs //r92-127 //Current Frame Y //r92 .declare uwDIFF_TEMPORAL_SUM4x4_TEMP_0 Base=r92 ElementSize=2 Type=uw //r101 .declare uwDIFF_TEMPORAL_SUM4x4_TEMP_1 Base=r101 ElementSize=2 Type=uw //r110 .declare uwDIFF_TEMPORAL_SUM4x4_TEMP_2 Base=r110 ElementSize=2 Type=uw //r119 .declare uwDIFF_TEMPORAL_SUM4x4_TEMP_3 Base=r119 ElementSize=2 Type=uw .declare udCURR_Y0 Base=r93.0 ElementSize=4 Type=ud .declare ubCURR_Y0 Base=r93.0 ElementSize=1 Type=ub .declare udCURR_Y1 Base=r102.0 ElementSize=4 Type=ud .declare ubCURR_Y1 Base=r102.0 ElementSize=1 Type=ub .declare udCURR_Y2 Base=r111.0 ElementSize=4 Type=ud .declare ubCURR_Y2 Base=r111.0 ElementSize=1 Type=ub .declare udCURR_Y3 Base=r120.0 ElementSize=4 Type=ud .declare ubCURR_Y3 Base=r120.0 ElementSize=1 Type=ub //r92: To hold U data for PL3 surfaces .declare udCURR_U_TEMP Base=r92.0 ElementSize=4 Type=ud .declare ubCURR_U_TEMP Base=r92.0 ElementSize=1 Type=ub //r112: To hold U data for PL3 surfaces .declare udPREV_U_TEMP Base=r112.0 ElementSize=4 Type=ud .declare ubPREV_U_TEMP Base=r112.0 ElementSize=1 Type=ub //r120: To hold U data for PL3 surfaces .declare udPREV_V_TEMP Base=r120.0 ElementSize=4 Type=ud .declare ubPREV_V_TEMP Base=r120.0 ElementSize=1 Type=ub // Initialize message source with r0. mov (8) r50.0<1>:ud r0.0<8;8,1>:ud mov (8) r92.0<1>:ud r0.0<8;8,1>:ud mov (8) r101.0<1>:ud r0.0<8;8,1>:ud mov (8) r110.0<1>:ud r0.0<8;8,1>:ud mov (8) r119.0<1>:ud r0.0<8;8,1>:ud //Module Name : DN_UV_YUY2_Load_Curr_Frame_YUV //Author : Tatiya, Rupesh //Description : Loads Current Frame YUV data for YUY2 input. //Module name : DN_UV_Load_Curr_Frame_UV //Author : Tatiya, Rupesh //Description : Loads Current Frame (UV only). // We need 4 extra rows (2 per field) and 2 extra pixel (1 each side) for both U and V each. // The processing size is 16x16 U and V each. So we need : U size - 18x20, V size - 18x20, UV size - 36x20, YUYV size - 72x20. //72x20 interleaved YUYV block is partitioned as follows: // <------ 36 --------> <--------36 -------> // ------------------------------------------ // | | 32x2 B1 | 32x2 B2 | | // | 4 |--------------------------------| 4 | // | x | | | x | // |20 | 32x8 A1 | 32x8 A3 | 20| // | |---------------|----------------| | // | C1| 32x8 A2 | 32x8 A4 | C2| // | | | | | // | |--------------------------------| | // | | 32x2 B3 | 32x2 B4 | | // ------------------------------------------ // // Cordinates: (x, y), (x, y+8), (x+32, y), (x+32, y+8), (x-4, y-2), (x+64, y-2),(x, y-2), (x+32, y-2), (x, y+16), (x+32, y+16) //UV surface origin: (2xORIX, ORIY) add (2) r7.4<1>:w r7.0<2;2,1>:w r4.4<2;2,1>:w { AccWrEn } // Source Block origin shl (1) r7.4<1>:w acc0.4<0;1,0>:w 1:w //A1 mov (2) r92.0<1>:d r7.4<2;2,1>:w { AccWrEn } // Source Block origin mov (1) r92.2<1>:ud 0x7001F:ud send (8) udCURR_Y0(0)<1> r92 0x4 0x2890003:ud //A2 mov (1) r101.0<1>:d acc0.0<0;1,0>:d add (1) r101.1<1>:d acc0.1<0;1,0>:d 8:d mov (1) r101.2<1>:ud 0x7001F:ud send (8) udCURR_Y1(0)<1> r101 0x4 0x2890003:ud //B1 mov (1) r50.0<1>:d acc0.0<0;1,0>:d add (1) r50.1<1>:d acc0.1<0;1,0>:d -2:d mov (1) r50.2<1>:ud 0x1001F:ud send (8) udCURR_UV(0)<1> r50 0x4 0x2290003:ud //B3 mov (1) r50.0<1>:d acc0.0<0;1,0>:d add (1) r50.1<1>:d acc0.1<0;1,0>:d 16:d send (8) udCURR_UV(18)<1> r50 0x4 0x2290003:ud //C1 add (1) r50.0<1>:d acc0.0<0;1,0>:d -4:d add (1) r50.1<1>:d acc0.1<0;1,0>:d -2:d mov (1) r50.2<1>:ud 0x130003:ud send (8) ubTEMP5(0)<1> r50 0x4 0x2390003:ud //A3 add (1) r110.0<1>:d acc0.0<0;1,0>:d 32:d mov (1) r110.1<1>:d acc0.1<0;1,0>:d mov (1) r110.2<1>:ud 0x7001F:ud send (8) udCURR_Y2(0)<1> r110 0x4 0x2890003:ud //A4 add (1) r119.0<1>:d acc0.0<0;1,0>:d 32:d add (1) r119.1<1>:d acc0.1<0;1,0>:d 8:d mov (1) r119.2<1>:ud 0x7001F:ud send (8) udCURR_Y3(0)<1> r119 0x4 0x2890003:ud //B2 add (1) r50.0<1>:d acc0.0<0;1,0>:d 32:d add (1) r50.1<1>:d acc0.1<0;1,0>:d -2:d mov (1) r50.2<1>:ud 0x1001F:ud send (8) udCURR_UV(20)<1> r50 0x4 0x2290003:ud //B4 add (1) r50.0<1>:d acc0.0<0;1,0>:d 32:d add (1) r50.1<1>:d acc0.1<0;1,0>:d 16:d send (8) udCURR_UV(38)<1> r50 0x4 0x2290003:ud //C2 add (1) r50.0<1>:d acc0.0<0;1,0>:d 64:d add (1) r50.1<1>:d acc0.1<0;1,0>:d -2:d mov (1) r50.2<1>:ud 0x130003:ud send (8) ubTEMP5(3)<1> r50 0x4 0x2390003:ud //History Origin, Current Y origin and BNE surface origin - all are in inline GRF. Use , . -rT. //Calculate Origin For History Surface: (ORIX/4, ORIY/4) shr (2) r7.2<1>:w r7.0<2;2,1>:w 2:w //Calculate Origin For BNE Surface: (ORIX/8, ORIY/8) shr (2) r7.6<1>:w r7.0<2;2,1>:w 3:w //Module Name : DN_UV_YUY2_Load_Prev_Frame_YUV.asm //Author : Tatiya, Rupesh //Description : Loads Pevious Frame YUV data for YUY2 input. //Module Name : DN_UV_Load_Prev_Frame_UV //Author : Tatiya, Rupesh //Description : Loads Prev Frame (UV only). U size - 16x16, V size - 16x16, UV size - 32x16, YUYV size - 64x16. mov (2) r50.0<1>:d r7.4<2;2,1>:w { AccWrEn } // Source lock origin mov (1) r50.2<1>:ud 0x7001F:ud // U/V block width and height (16x16) send (8) udPREV_UV(0)<1> r50 0x4 0x2890000:ud add (1) r50.1<1>:ud acc0.1<0;1,0>:d 8:w // Add 16 to X origin send (8) udPREV_UV(8)<1> r50 0x4 0x2890000:ud add (1) r50.0<1>:ud acc0.0<0;1,0>:d 32:w mov (1) r50.1<1>:ud acc0.1<0;1,0>:d send (8) udPREV_UV(16)<1> r50 0x4 0x2890000:ud add (1) r50.1<1>:ud acc0.0<0;1,0>:d 8:w send (8) udPREV_UV(24)<1> r50 0x4 0x2890000:ud //TODO - See if History loading can be combined with Prev Frame Load. - rT //Module name : DN_UV_Load_Hist_UV //Author : Tatiya, Rupesh //Description : Load DN History for UV denoise. 4x4 for each U & V. mov (2) r50.0<1>:d r7.2<2;2,1>:w mov (1) r50.2<1>:ud 0x30007:ud send (8) udHIST_UV(0)<1> r50 0x4 0x2190022:ud //Module Name: DN_UV_YUY2_Extract_Curr_Frame_UV //Author : Tatiya, Rupesh //Description: Extract UV data from current YUY2 frame. //72x20 interleaved YUYV block is partitioned as follows: // <------ 36 --------> <--------36 -------> // ------------------------------------------ // | | 32x2 B1 | 32x2 B2 | | // | 4 |--------------------------------| 4 | // | x | | | x | // |20 | 32x8 A1 | 32x8 A3 | 20| // | |---------------|----------------| | // | C1| 32x8 A2 | 32x8 A4 | C2| // | | | | | // | |--------------------------------| | // | | 32x2 B3 | 32x2 B4 | | // ------------------------------------------ // Set SRC pointers according to Input packing i.e. YUYV, YVYU, UYVY, VYUY add (1) a0.0<1>:uw r4.1<0;1,0>:ub 2976:w //A1 add (1) a0.1<1>:uw r4.1<0;1,0>:ub 3264:w //A2 add (1) a0.2<1>:uw r4.1<0;1,0>:ub 3552:w //A3 add (1) a0.3<1>:uw r4.1<0;1,0>:ub 3840:w //A4 add (1) a0.4<1>:uw r4.1<0;1,0>:ub 1664:w //B1 add (1) a0.5<1>:uw r4.1<0;1,0>:ub 2240:w //B3B2 add (1) a0.6<1>:uw r4.1<0;1,0>:ub 2880:w //B4 add (1) a0.7<1>:uw r4.1<0;1,0>:ub 1376:w //C1C2 //Left 20x20 UV : 16x16 UV (Original)+4 extra rows(2 per field on top/bottom)+4 extra pixels(2 on left/right) //A1 mov (16) ubCURR_UV(2,2)<1> r[a0.0, 0]<32;16,2> mov (16) ubCURR_UV(3,2)<1> r[a0.0, 32]<32;16,2> mov (16) ubCURR_UV(4,2)<1> r[a0.0, 64]<32;16,2> mov (16) ubCURR_UV(5,2)<1> r[a0.0, 96]<32;16,2> mov (16) ubCURR_UV(6,2)<1> r[a0.0, 128]<32;16,2> mov (16) ubCURR_UV(7,2)<1> r[a0.0, 160]<32;16,2> mov (16) ubCURR_UV(8,2)<1> r[a0.0, 192]<32;16,2> mov (16) ubCURR_UV(9,2)<1> r[a0.0, 224]<32;16,2> //A2 mov (16) ubCURR_UV(10,2)<1> r[a0.1, 0]<32;16,2> mov (16) ubCURR_UV(11,2)<1> r[a0.1, 32]<32;16,2> mov (16) ubCURR_UV(12,2)<1> r[a0.1, 64]<32;16,2> mov (16) ubCURR_UV(13,2)<1> r[a0.1, 96]<32;16,2> mov (16) ubCURR_UV(14,2)<1> r[a0.1, 128]<32;16,2> mov (16) ubCURR_UV(15,2)<1> r[a0.1, 160]<32;16,2> mov (16) ubCURR_UV(16,2)<1> r[a0.1, 192]<32;16,2> mov (16) ubCURR_UV(17,2)<1> r[a0.1, 224]<32;16,2> //B1 mov (16) ubCURR_UV(0,2)<1> r[a0.4, 0]<32;16,2> mov (16) ubCURR_UV(1,2)<1> r[a0.4, 32]<32;16,2> //B3 mov (16) ubCURR_UV(18,2)<1> r[a0.5, 0]<32;16,2> mov (16) ubCURR_UV(19,2)<1> r[a0.5, 32]<32;16,2> //TODO - Find a way to reduce this 40 SIMD2 instructions - rT //C1 mov (2) ubCURR_UV(0,0)<1> r[a0.7, 0]<4;2,2> mov (2) ubCURR_UV(1,0)<1> r[a0.7, 4]<4;2,2> mov (2) ubCURR_UV(2,0)<1> r[a0.7, 8]<4;2,2> mov (2) ubCURR_UV(3,0)<1> r[a0.7, 12]<4;2,2> mov (2) ubCURR_UV(4,0)<1> r[a0.7, 16]<4;2,2> mov (2) ubCURR_UV(5,0)<1> r[a0.7, 20]<4;2,2> mov (2) ubCURR_UV(6,0)<1> r[a0.7, 24]<4;2,2> mov (2) ubCURR_UV(7,0)<1> r[a0.7, 28]<4;2,2> mov (2) ubCURR_UV(8,0)<1> r[a0.7, 32]<4;2,2> mov (2) ubCURR_UV(9,0)<1> r[a0.7, 36]<4;2,2> mov (2) ubCURR_UV(10,0)<1> r[a0.7, 40]<4;2,2> mov (2) ubCURR_UV(11,0)<1> r[a0.7, 44]<4;2,2> mov (2) ubCURR_UV(12,0)<1> r[a0.7, 48]<4;2,2> mov (2) ubCURR_UV(13,0)<1> r[a0.7, 52]<4;2,2> mov (2) ubCURR_UV(14,0)<1> r[a0.7, 56]<4;2,2> mov (2) ubCURR_UV(15,0)<1> r[a0.7, 60]<4;2,2> mov (2) ubCURR_UV(16,0)<1> r[a0.7, 64]<4;2,2> mov (2) ubCURR_UV(17,0)<1> r[a0.7, 68]<4;2,2> mov (2) ubCURR_UV(18,0)<1> r[a0.7, 72]<4;2,2> mov (2) ubCURR_UV(19,0)<1> r[a0.7, 76]<4;2,2> //2 right bytes from B2 - 2 rows mov (2) ubCURR_UV(0,18)<1> r[a0.5, 64]<4;2,2> mov (2) ubCURR_UV(1,18)<1> r[a0.5, 96]<4;2,2> //2 right bytes from A3 - 8 rows mov (2) ubCURR_UV(2,18)<1> r[a0.2, 0]<4;2,2> mov (2) ubCURR_UV(3,18)<1> r[a0.2, 32]<4;2,2> mov (2) ubCURR_UV(4,18)<1> r[a0.2, 64]<4;2,2> mov (2) ubCURR_UV(5,18)<1> r[a0.2, 96]<4;2,2> mov (2) ubCURR_UV(6,18)<1> r[a0.2, 128]<4;2,2> mov (2) ubCURR_UV(7,18)<1> r[a0.2, 160]<4;2,2> mov (2) ubCURR_UV(8,18)<1> r[a0.2, 192]<4;2,2> mov (2) ubCURR_UV(9,18)<1> r[a0.2, 224]<4;2,2> //2 right bytes from A4 - 8 rows mov (2) ubCURR_UV(10,18)<1> r[a0.3, 0]<4;2,2> mov (2) ubCURR_UV(11,18)<1> r[a0.3, 32]<4;2,2> mov (2) ubCURR_UV(12,18)<1> r[a0.3, 64]<4;2,2> mov (2) ubCURR_UV(13,18)<1> r[a0.3, 96]<4;2,2> mov (2) ubCURR_UV(14,18)<1> r[a0.3, 128]<4;2,2> mov (2) ubCURR_UV(15,18)<1> r[a0.3, 160]<4;2,2> mov (2) ubCURR_UV(16,18)<1> r[a0.3, 192]<4;2,2> mov (2) ubCURR_UV(17,18)<1> r[a0.3, 224]<4;2,2> //2 right bytes from B4 - 2 rows mov (2) ubCURR_UV(18,18)<1> r[a0.6, 0]<4;2,2> mov (2) ubCURR_UV(19,18)<1> r[a0.6, 32]<4;2,2> //Right 20x20 UV : 16x16 UV (Original)+4 extra rows(2 per field on top/bottom)+4 extra pixels(2 on left/right) //A3 mov (16) ubCURR_UV(22,2)<1> r[a0.2, 0]<32;16,2> mov (16) ubCURR_UV(23,2)<1> r[a0.2, 32]<32;16,2> mov (16) ubCURR_UV(24,2)<1> r[a0.2, 64]<32;16,2> mov (16) ubCURR_UV(25,2)<1> r[a0.2, 96]<32;16,2> mov (16) ubCURR_UV(26,2)<1> r[a0.2, 128]<32;16,2> mov (16) ubCURR_UV(27,2)<1> r[a0.2, 160]<32;16,2> mov (16) ubCURR_UV(28,2)<1> r[a0.2, 192]<32;16,2> mov (16) ubCURR_UV(29,2)<1> r[a0.2, 224]<32;16,2> //A4 mov (16) ubCURR_UV(30,2)<1> r[a0.3, 0]<32;16,2> mov (16) ubCURR_UV(31,2)<1> r[a0.3, 32]<32;16,2> mov (16) ubCURR_UV(32,2)<1> r[a0.3, 64]<32;16,2> mov (16) ubCURR_UV(33,2)<1> r[a0.3, 96]<32;16,2> mov (16) ubCURR_UV(34,2)<1> r[a0.3, 128]<32;16,2> mov (16) ubCURR_UV(35,2)<1> r[a0.3, 160]<32;16,2> mov (16) ubCURR_UV(36,2)<1> r[a0.3, 192]<32;16,2> mov (16) ubCURR_UV(37,2)<1> r[a0.3, 224]<32;16,2> //B2 mov (16) ubCURR_UV(20,2)<1> r[a0.5, 64]<32;16,2> mov (16) ubCURR_UV(21,2)<1> r[a0.5, 96]<32;16,2> //B4 mov (16) ubCURR_UV(38,2)<1> r[a0.6, 0]<32;16,2> mov (16) ubCURR_UV(39,2)<1> r[a0.6, 32]<32;16,2> //TODO - Find a way to reduce this 40 SIMD2 instructions - rT //C2 mov (2) ubCURR_UV(20,18)<1> r[a0.7, 96]<4;2,2> mov (2) ubCURR_UV(21,18)<1> r[a0.7, 100]<4;2,2> mov (2) ubCURR_UV(22,18)<1> r[a0.7, 104]<4;2,2> mov (2) ubCURR_UV(23,18)<1> r[a0.7, 108]<4;2,2> mov (2) ubCURR_UV(24,18)<1> r[a0.7, 112]<4;2,2> mov (2) ubCURR_UV(25,18)<1> r[a0.7, 116]<4;2,2> mov (2) ubCURR_UV(26,18)<1> r[a0.7, 120]<4;2,2> mov (2) ubCURR_UV(27,18)<1> r[a0.7, 124]<4;2,2> mov (2) ubCURR_UV(28,18)<1> r[a0.7, 128]<4;2,2> mov (2) ubCURR_UV(29,18)<1> r[a0.7, 132]<4;2,2> mov (2) ubCURR_UV(30,18)<1> r[a0.7, 136]<4;2,2> mov (2) ubCURR_UV(31,18)<1> r[a0.7, 140]<4;2,2> mov (2) ubCURR_UV(32,18)<1> r[a0.7, 144]<4;2,2> mov (2) ubCURR_UV(33,18)<1> r[a0.7, 148]<4;2,2> mov (2) ubCURR_UV(34,18)<1> r[a0.7, 152]<4;2,2> mov (2) ubCURR_UV(35,18)<1> r[a0.7, 156]<4;2,2> mov (2) ubCURR_UV(36,18)<1> r[a0.7, 160]<4;2,2> mov (2) ubCURR_UV(37,18)<1> r[a0.7, 164]<4;2,2> mov (2) ubCURR_UV(38,18)<1> r[a0.7, 168]<4;2,2> mov (2) ubCURR_UV(39,18)<1> r[a0.7, 172]<4;2,2> //2 left bytes from B1 - 2 rows mov (2) ubCURR_UV(20,0)<1> r[a0.4, 28]<4;2,2> mov (2) ubCURR_UV(21,0)<1> r[a0.4, 60]<4;2,2> //2 left bytes from A1 - 8 rows mov (2) ubCURR_UV(22,0)<1> r[a0.0, 28]<4;2,2> mov (2) ubCURR_UV(23,0)<1> r[a0.0, 60]<4;2,2> mov (2) ubCURR_UV(24,0)<1> r[a0.0, 92]<4;2,2> mov (2) ubCURR_UV(25,0)<1> r[a0.0, 124]<4;2,2> mov (2) ubCURR_UV(26,0)<1> r[a0.0, 156]<4;2,2> mov (2) ubCURR_UV(27,0)<1> r[a0.0, 188]<4;2,2> mov (2) ubCURR_UV(28,0)<1> r[a0.0, 220]<4;2,2> mov (2) ubCURR_UV(29,0)<1> r[a0.0, 252]<4;2,2> //2 left bytes from A2 - 8 rows mov (2) ubCURR_UV(30,0)<1> r[a0.1, 28]<4;2,2> mov (2) ubCURR_UV(31,0)<1> r[a0.1, 60]<4;2,2> mov (2) ubCURR_UV(32,0)<1> r[a0.1, 92]<4;2,2> mov (2) ubCURR_UV(33,0)<1> r[a0.1, 124]<4;2,2> mov (2) ubCURR_UV(34,0)<1> r[a0.1, 156]<4;2,2> mov (2) ubCURR_UV(35,0)<1> r[a0.1, 188]<4;2,2> mov (2) ubCURR_UV(36,0)<1> r[a0.1, 220]<4;2,2> mov (2) ubCURR_UV(37,0)<1> r[a0.1, 252]<4;2,2> //2 left bytes from B3 - 2 rows mov (2) ubCURR_UV(38,0)<1> r[a0.5, 28]<4;2,2> mov (2) ubCURR_UV(39,0)<1> r[a0.5, 60]<4;2,2> // Module Name : DN_UV_YUY2_Extract_Prev_Frame_UV // Author : Tatiya, Rupesh // Description : Extract UV from previous frame YUY2. // Set SRC pointers according to Input packing i.e. YUYV, YVYU, UYVY, VYUY add (1) a0.0<1>:uw r4.1<0;1,0>:ub 256:w add (1) a0.1<1>:uw r4.1<0;1,0>:ub 768:w mov (16) ubPREV_UV(0,0)<1> r[a0.0, 0]<32;16,2>:ub mov (16) ubPREV_UV(0,16)<1> r[a0.0, 32]<32;16,2>:ub mov (16) ubPREV_UV(1,0)<1> r[a0.0, 64]<32;16,2>:ub mov (16) ubPREV_UV(1,16)<1> r[a0.0, 96]<32;16,2>:ub mov (16) ubPREV_UV(2,0)<1> r[a0.0, 128]<32;16,2>:ub mov (16) ubPREV_UV(2,16)<1> r[a0.0, 160]<32;16,2>:ub mov (16) ubPREV_UV(3,0)<1> r[a0.0, 192]<32;16,2>:ub mov (16) ubPREV_UV(3,16)<1> r[a0.0, 224]<32;16,2>:ub mov (16) ubPREV_UV(4,0)<1> r[a0.0, 256]<32;16,2>:ub mov (16) ubPREV_UV(4,16)<1> r[a0.0, 288]<32;16,2>:ub mov (16) ubPREV_UV(5,0)<1> r[a0.0, 320]<32;16,2>:ub mov (16) ubPREV_UV(5,16)<1> r[a0.0, 352]<32;16,2>:ub mov (16) ubPREV_UV(6,0)<1> r[a0.0, 384]<32;16,2>:ub mov (16) ubPREV_UV(6,16)<1> r[a0.0, 416]<32;16,2>:ub mov (16) ubPREV_UV(7,0)<1> r[a0.0, 448]<32;16,2>:ub mov (16) ubPREV_UV(7,16)<1> r[a0.0, 480]<32;16,2>:ub mov (16) ubPREV_UV(8,0)<1> r[a0.1, 0]<32;16,2>:ub mov (16) ubPREV_UV(8,16)<1> r[a0.1, 32]<32;16,2>:ub mov (16) ubPREV_UV(9,0)<1> r[a0.1, 64]<32;16,2>:ub mov (16) ubPREV_UV(9,16)<1> r[a0.1, 96]<32;16,2>:ub mov (16) ubPREV_UV(10,0)<1> r[a0.1, 128]<32;16,2>:ub mov (16) ubPREV_UV(10,16)<1> r[a0.1, 160]<32;16,2>:ub mov (16) ubPREV_UV(11,0)<1> r[a0.1, 192]<32;16,2>:ub mov (16) ubPREV_UV(11,16)<1> r[a0.1, 224]<32;16,2>:ub mov (16) ubPREV_UV(12,0)<1> r[a0.1, 256]<32;16,2>:ub mov (16) ubPREV_UV(12,16)<1> r[a0.1, 288]<32;16,2>:ub mov (16) ubPREV_UV(13,0)<1> r[a0.1, 320]<32;16,2>:ub mov (16) ubPREV_UV(13,16)<1> r[a0.1, 352]<32;16,2>:ub mov (16) ubPREV_UV(14,0)<1> r[a0.1, 384]<32;16,2>:ub mov (16) ubPREV_UV(14,16)<1> r[a0.1, 416]<32;16,2>:ub mov (16) ubPREV_UV(15,0)<1> r[a0.1, 448]<32;16,2>:ub mov (16) ubPREV_UV(15,16)<1> r[a0.1, 480]<32;16,2>:ub //Module Name : DN_UV_Noise_Detection_UV //Author : Tatiya, Rupesh //Description : Performs noise detection on 16x16 U and 16x16 V each. //Module Name : DN_UV_Move_CURBE_Inline_UV.asm //Author : Tatiya, Rupesh //Mov CURBE data to another space - so that it can be used as Temp Space --> r1 - r6 mov (4) r54.28<1>:ub r2.28<4;4,1>:ub //Dest. YUY2 offset mov (2) r54.5<1>:ud r4.0<4;2,2>:ud //Src YUY2 offset and Origin offset mov (4) r55.28<1>:ub r1.0<4;4,1>:ub mov (8) r61.20<1>:ub r1.4<8;8,1>:ub mov (4) r61.28<1>:ub r1.12<4;4,1>:ub //Move Inline Data to another space - so that it can be used as Temp Space --> r7 mov (4) r62.10<1>:w r7.0<4;4,1>:w mov (4) r63.10<1>:w r7.4<4;4,1>:w //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. mov (1) a0.0:uw 1664:uw mov (1) a0.1:uw 1816:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 1792:uw mov (1) a0.1:uw 1820:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 1920:uw mov (1) a0.1:uw 1848:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 2048:uw mov (1) a0.1:uw 1852:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. mov (1) a0.0:uw 2304:uw mov (1) a0.1:uw 1880:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 2432:uw mov (1) a0.1:uw 1884:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 2560:uw mov (1) a0.1:uw 1912:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 2688:uw mov (1) a0.1:uw 1916:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module : DN_UV_Noise_Reduction_UV //Author : Tatiya, Rupesh //Description : Performs Noise Reduction on 16x16 U and 16x16 V. //Tasks : 1. Update weight history // 2. Find if it block is motion block // 3. Compute Denoised Pixel. //History is 1+1 byte every 4x4 U and 4x4 V. cmp.l.f0.0 (16) null<1>:w ubHIST_UV(0,0)<16;16,1> r61.20<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w ubHIST_UV(0,0)<16;16,1> r61.22<0;2,1>:ub mov (16) uwCURBE_TEMP(0)<1> 0:w mov (16) uwCURBE_TEMP(1)<1> 0:w //Compute diff betn curr and prev. - First 16 lines // 8 lines here add (16) wDIFF_TEMPORAL(0)<1> ubCURR_UV(2,2)<16;16,1> -ubPREV_UV(0,0)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(1)<1> ubCURR_UV(3,2)<16;16,1> -ubPREV_UV(0,16)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(2)<1> ubCURR_UV(4,2)<16;16,1> -ubPREV_UV(0,32)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(3)<1> ubCURR_UV(5,2)<16;16,1> -ubPREV_UV(0,48)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(4)<1> ubCURR_UV(6,2)<16;16,1> -ubPREV_UV(0,64)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(5)<1> ubCURR_UV(7,2)<16;16,1> -ubPREV_UV(0,80)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(6)<1> ubCURR_UV(8,2)<16;16,1> -ubPREV_UV(0,96)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(7)<1> ubCURR_UV(9,2)<16;16,1> -ubPREV_UV(0,112)<16;16,1> //Diff UV interleaved //Update WT HIST (-f0.0) shr (16) uwCURBE_TEMP(0)<1> ubHIST_UV(0,0)<16;16,1> 1:w (f1.0) add (16) uwCURBE_TEMP(2)<1> ubHIST_UV(0,0)<16;16,1> r61.24<0;2,1>:ub (f0.0) mov (16) uwCURBE_TEMP(2)<1> r61.20<0;2,1>:ub (-f0.0.anyv) mov (16) uwCURBE_TEMP(2)<1> ubHIST_UV(0,0)<16;16,1> cmp.l.f0.0 (16) null<1>:w ubHIST_UV(0,16)<16;16,1> r61.20<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w ubHIST_UV(0,16)<16;16,1> r61.22<0;2,1>:ub //Compute diff betn curr and prev. - First 16 lines // 8 more lines here add (16) wDIFF_TEMPORAL(8)<1> ubCURR_UV(10,2)<16;16,1> -ubPREV_UV(0,128)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(9)<1> ubCURR_UV(11,2)<16;16,1> -ubPREV_UV(0,144)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(10)<1> ubCURR_UV(12,2)<16;16,1> -ubPREV_UV(0,160)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(11)<1> ubCURR_UV(13,2)<16;16,1> -ubPREV_UV(0,176)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(12)<1> ubCURR_UV(14,2)<16;16,1> -ubPREV_UV(0,192)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(13)<1> ubCURR_UV(15,2)<16;16,1> -ubPREV_UV(0,208)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(14)<1> ubCURR_UV(16,2)<16;16,1> -ubPREV_UV(0,224)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(15)<1> ubCURR_UV(17,2)<16;16,1> -ubPREV_UV(0,240)<16;16,1> //Diff UV interleaved (-f0.0) shr (16) uwCURBE_TEMP(1)<1> ubHIST_UV(0,16)<16;16,1> 1:w (f1.0) add (16) uwCURBE_TEMP(3)<1> ubHIST_UV(0,16)<16;16,1> r61.24<0;2,1>:ub (f0.0) mov (16) uwCURBE_TEMP(3)<1> r61.20<0;2,1>:ub (-f0.0.anyv) mov(16) uwCURBE_TEMP(3)<1> ubHIST_UV(0,16)<16;16,1> //16x16 to 16x4 - First 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(0)<16;16,1> (abs)wDIFF_TEMPORAL(1)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(2)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(0)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(3)<16;16,1> //16x16 to 16x4 - First 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(4)<16;16,1> (abs)wDIFF_TEMPORAL(5)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(6)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(1)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(7)<16;16,1> //16x16 to 16x4 - First 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(8)<16;16,1> (abs)wDIFF_TEMPORAL(9)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(10)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(2)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(11)<16;16,1> //16x16 to 16x4 - First 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(12)<16;16,1> (abs)wDIFF_TEMPORAL(13)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(14)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(3)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(15)<16;16,1> //Compute diff betn curr and prev. - Second 16 lines //13 lines. add (16) wDIFF_TEMPORAL(16)<1> ubCURR_UV(22,2)<16;16,1> -ubPREV_UV(8,0)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(17)<1> ubCURR_UV(23,2)<16;16,1> -ubPREV_UV(8,16)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(18)<1> ubCURR_UV(24,2)<16;16,1> -ubPREV_UV(8,32)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(19)<1> ubCURR_UV(25,2)<16;16,1> -ubPREV_UV(8,48)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(20)<1> ubCURR_UV(26,2)<16;16,1> -ubPREV_UV(8,64)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(21)<1> ubCURR_UV(27,2)<16;16,1> -ubPREV_UV(8,80)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(22)<1> ubCURR_UV(28,2)<16;16,1> -ubPREV_UV(8,96)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(23)<1> ubCURR_UV(29,2)<16;16,1> -ubPREV_UV(8,112)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(24)<1> ubCURR_UV(30,2)<16;16,1> -ubPREV_UV(8,128)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(25)<1> ubCURR_UV(31,2)<16;16,1> -ubPREV_UV(8,144)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(26)<1> ubCURR_UV(32,2)<16;16,1> -ubPREV_UV(8,160)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(27)<1> ubCURR_UV(33,2)<16;16,1> -ubPREV_UV(8,176)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(28)<1> ubCURR_UV(34,2)<16;16,1> -ubPREV_UV(8,192)<16;16,1> //Diff UV interleaved //3 more lines add (16) wCURBE_TEMP(4)<1> ubCURR_UV(35,2)<16;16,1> -ubPREV_UV(8,208)<16;16,1> //Diff UV interleaved add (16) wCURBE_TEMP(5)<1> ubCURR_UV(36,2)<16;16,1> -ubPREV_UV(8,224)<16;16,1> //Diff UV interleaved add (16) wCURBE_TEMP(6)<1> ubCURR_UV(37,2)<16;16,1> -ubPREV_UV(8,240)<16;16,1> //Diff UV interleaved //16x4 to 8x4 - First 16 lines add (16) uwDIFF_TEMPORAL_SUM4x4(0)<1> uwDIFF_TEMPORAL_SUM4x4(0,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(0,2)<4;2,1> add (16) uwDIFF_TEMPORAL_SUM4x4(1)<1> uwDIFF_TEMPORAL_SUM4x4(2,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(2,2)<4;2,1> //8x4 to 4x4 - First 16 lines add (16) uwDIFF_TEMPORAL_SUM4x4_FINAL(0)<1> uwDIFF_TEMPORAL_SUM4x4(0,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(0,2)<4;2,1> { AccWrEn } //16x16 to 16x4 - Second 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(16)<16;16,1> (abs)wDIFF_TEMPORAL(17)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(18)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(0)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(19)<16;16,1> //16x16 to 16x4 - Second 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(20)<16;16,1> (abs)wDIFF_TEMPORAL(21)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(22)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(1)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(23)<16;16,1> //16x16 to 16x4 - Second 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(24)<16;16,1> (abs)wDIFF_TEMPORAL(25)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(26)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(2)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(27)<16;16,1> //16x16 to 16x4 - Second 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(28)<16;16,1> (abs)wCURBE_TEMP(4)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wCURBE_TEMP(5)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(3)<1> acc0.0<16;16,1>:uw (abs)wCURBE_TEMP(6)<16;16,1> //Find if block is motion block - First 16 lines cmp.g.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_FINAL(0)<16;16,1> r61.26<0;2,1>:ub //Move TEMPORAL_SUM4x4 for SIMD16 use later. mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,0)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,2)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,4)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,6)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,8)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,10)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,12)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,14)<0;2,1> //Pick Appropriate Weight History Based on motion. - First 16 lines (-f0.0) mov (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(2)<16;16,1> //Actual DN - First 16 lines cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(0)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(0)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(2,2)<8;8,1> -uwCURBE_TEMP(0,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(2,10)<8;8,1> -uwCURBE_TEMP(0,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(2,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,0)<8;8,1> uwCURBE_TEMP(0,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,8)<8;8,1> uwCURBE_TEMP(0,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(0)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(0)<1> ubCURR_UV(2,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(0)<1> wDIFF_TEMPORAL(0)<16;16,1> ubCURR_UV(2,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(1)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(1)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(3,2)<8;8,1> -uwCURBE_TEMP(0,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(3,10)<8;8,1> -uwCURBE_TEMP(0,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(3,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,16)<8;8,1> uwCURBE_TEMP(0,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,24)<8;8,1> uwCURBE_TEMP(0,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(1)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(1)<1> ubCURR_UV(3,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(1)<1> wDIFF_TEMPORAL(1)<16;16,1> ubCURR_UV(3,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(2)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(2)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(4,2)<8;8,1> -uwCURBE_TEMP(0,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(4,10)<8;8,1> -uwCURBE_TEMP(0,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(4,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,32)<8;8,1> uwCURBE_TEMP(0,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,40)<8;8,1> uwCURBE_TEMP(0,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(2)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(2)<1> ubCURR_UV(4,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(2)<1> wDIFF_TEMPORAL(2)<16;16,1> ubCURR_UV(4,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(3)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(3)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(5,2)<8;8,1> -uwCURBE_TEMP(0,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(5,10)<8;8,1> -uwCURBE_TEMP(0,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(5,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,48)<8;8,1> uwCURBE_TEMP(0,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,56)<8;8,1> uwCURBE_TEMP(0,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(3)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(3)<1> ubCURR_UV(5,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(3)<1> wDIFF_TEMPORAL(3)<16;16,1> ubCURR_UV(5,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(4)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(4)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(6,2)<8;8,1> -uwCURBE_TEMP(0,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(6,10)<8;8,1> -uwCURBE_TEMP(0,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(6,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,64)<8;8,1> uwCURBE_TEMP(0,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,72)<8;8,1> uwCURBE_TEMP(0,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(4)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(4)<1> ubCURR_UV(6,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(4)<1> wDIFF_TEMPORAL(4)<16;16,1> ubCURR_UV(6,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(5)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(5)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(7,2)<8;8,1> -uwCURBE_TEMP(0,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(7,10)<8;8,1> -uwCURBE_TEMP(0,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(7,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,80)<8;8,1> uwCURBE_TEMP(0,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,88)<8;8,1> uwCURBE_TEMP(0,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(5)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(5)<1> ubCURR_UV(7,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(5)<1> wDIFF_TEMPORAL(5)<16;16,1> ubCURR_UV(7,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(6)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(6)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(8,2)<8;8,1> -uwCURBE_TEMP(0,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(8,10)<8;8,1> -uwCURBE_TEMP(0,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(8,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,96)<8;8,1> uwCURBE_TEMP(0,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,104)<8;8,1> uwCURBE_TEMP(0,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(6)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(6)<1> ubCURR_UV(8,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(6)<1> wDIFF_TEMPORAL(6)<16;16,1> ubCURR_UV(8,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(7)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(7)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(9,2)<8;8,1> -uwCURBE_TEMP(0,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(9,10)<8;8,1> -uwCURBE_TEMP(0,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(9,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,112)<8;8,1> uwCURBE_TEMP(0,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,120)<8;8,1> uwCURBE_TEMP(0,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(7)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(7)<1> ubCURR_UV(9,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(7)<1> wDIFF_TEMPORAL(7)<16;16,1> ubCURR_UV(9,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(8)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(8)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(10,2)<8;8,1> -uwCURBE_TEMP(0,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(10,10)<8;8,1> -uwCURBE_TEMP(0,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(10,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,128)<8;8,1> uwCURBE_TEMP(0,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,136)<8;8,1> uwCURBE_TEMP(0,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(8)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(8)<1> ubCURR_UV(10,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(8)<1> wDIFF_TEMPORAL(8)<16;16,1> ubCURR_UV(10,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(9)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(9)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(11,2)<8;8,1> -uwCURBE_TEMP(0,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(11,10)<8;8,1> -uwCURBE_TEMP(0,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(11,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,144)<8;8,1> uwCURBE_TEMP(0,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,152)<8;8,1> uwCURBE_TEMP(0,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(9)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(9)<1> ubCURR_UV(11,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(9)<1> wDIFF_TEMPORAL(9)<16;16,1> ubCURR_UV(11,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(10)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(10)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(12,2)<8;8,1> -uwCURBE_TEMP(0,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(12,10)<8;8,1> -uwCURBE_TEMP(0,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(12,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,160)<8;8,1> uwCURBE_TEMP(0,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,168)<8;8,1> uwCURBE_TEMP(0,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(10)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(10)<1> ubCURR_UV(12,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(10)<1> wDIFF_TEMPORAL(10)<16;16,1> ubCURR_UV(12,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(11)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(11)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(13,2)<8;8,1> -uwCURBE_TEMP(0,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(13,10)<8;8,1> -uwCURBE_TEMP(0,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(13,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,176)<8;8,1> uwCURBE_TEMP(0,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,184)<8;8,1> uwCURBE_TEMP(0,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(11)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(11)<1> ubCURR_UV(13,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(11)<1> wDIFF_TEMPORAL(11)<16;16,1> ubCURR_UV(13,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(12)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(12)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(14,2)<8;8,1> -uwCURBE_TEMP(0,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(14,10)<8;8,1> -uwCURBE_TEMP(0,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(14,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,192)<8;8,1> uwCURBE_TEMP(0,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,200)<8;8,1> uwCURBE_TEMP(0,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(12)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(12)<1> ubCURR_UV(14,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(12)<1> wDIFF_TEMPORAL(12)<16;16,1> ubCURR_UV(14,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(13)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(13)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(15,2)<8;8,1> -uwCURBE_TEMP(0,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(15,10)<8;8,1> -uwCURBE_TEMP(0,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(15,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,208)<8;8,1> uwCURBE_TEMP(0,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,216)<8;8,1> uwCURBE_TEMP(0,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(13)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(13)<1> ubCURR_UV(15,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(13)<1> wDIFF_TEMPORAL(13)<16;16,1> ubCURR_UV(15,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(14)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(14)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(16,2)<8;8,1> -uwCURBE_TEMP(0,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(16,10)<8;8,1> -uwCURBE_TEMP(0,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(16,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,224)<8;8,1> uwCURBE_TEMP(0,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,232)<8;8,1> uwCURBE_TEMP(0,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(14)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(14)<1> ubCURR_UV(16,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(14)<1> wDIFF_TEMPORAL(14)<16;16,1> ubCURR_UV(16,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(15)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(15)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(17,2)<8;8,1> -uwCURBE_TEMP(0,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(17,10)<8;8,1> -uwCURBE_TEMP(0,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(17,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,240)<8;8,1> uwCURBE_TEMP(0,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,248)<8;8,1> uwCURBE_TEMP(0,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(15)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(15)<1> ubCURR_UV(17,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(15)<1> wDIFF_TEMPORAL(15)<16;16,1> ubCURR_UV(17,2)<16;16,1> //16x4 to 8x4 - Second 16 lines add (16) uwDIFF_TEMPORAL_SUM4x4(0)<1> uwDIFF_TEMPORAL_SUM4x4(0,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(0,2)<4;2,1> add (16) uwDIFF_TEMPORAL_SUM4x4(1)<1> uwDIFF_TEMPORAL_SUM4x4(2,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(2,2)<4;2,1> //8x4 to 4x4 - Second 16 lines add (16) uwDIFF_TEMPORAL_SUM4x4_FINAL(1)<1> uwDIFF_TEMPORAL_SUM4x4(0,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(0,2)<4;2,1> { AccWrEn } //Find if block is motion block - Second 16 lines cmp.g.f1.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_FINAL(1)<16;16,1> r61.26<0;2,1>:ub //Move TEMPORAL_SUM4x4 for SIMD16 use later. mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,0)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,2)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,4)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,6)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,8)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,10)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,12)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,14)<0;2,1> //Pick Appropriate Weight History Based on motion. - Second 16 lines (-f1.0) mov (16) uwCURBE_TEMP(1)<1> uwCURBE_TEMP(3)<16;16,1> //Actual DN - Second 16 lines cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(16)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(16)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(22,2)<8;8,1> -uwCURBE_TEMP(1,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(22,10)<8;8,1> -uwCURBE_TEMP(1,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(22,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,0)<8;8,1> uwCURBE_TEMP(1,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,8)<8;8,1> uwCURBE_TEMP(1,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(16)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(16)<1> ubCURR_UV(22,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(16)<1> wDIFF_TEMPORAL(16)<16;16,1> ubCURR_UV(22,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(17)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(17)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(23,2)<8;8,1> -uwCURBE_TEMP(1,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(23,10)<8;8,1> -uwCURBE_TEMP(1,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(23,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,16)<8;8,1> uwCURBE_TEMP(1,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,24)<8;8,1> uwCURBE_TEMP(1,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(17)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(17)<1> ubCURR_UV(23,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(17)<1> wDIFF_TEMPORAL(17)<16;16,1> ubCURR_UV(23,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(18)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(18)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(24,2)<8;8,1> -uwCURBE_TEMP(1,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(24,10)<8;8,1> -uwCURBE_TEMP(1,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(24,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,32)<8;8,1> uwCURBE_TEMP(1,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,40)<8;8,1> uwCURBE_TEMP(1,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(18)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(18)<1> ubCURR_UV(24,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(18)<1> wDIFF_TEMPORAL(18)<16;16,1> ubCURR_UV(24,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(19)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(19)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(25,2)<8;8,1> -uwCURBE_TEMP(1,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(25,10)<8;8,1> -uwCURBE_TEMP(1,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(25,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,48)<8;8,1> uwCURBE_TEMP(1,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,56)<8;8,1> uwCURBE_TEMP(1,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(19)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(19)<1> ubCURR_UV(25,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(19)<1> wDIFF_TEMPORAL(19)<16;16,1> ubCURR_UV(25,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(20)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(20)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(26,2)<8;8,1> -uwCURBE_TEMP(1,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(26,10)<8;8,1> -uwCURBE_TEMP(1,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(26,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,64)<8;8,1> uwCURBE_TEMP(1,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,72)<8;8,1> uwCURBE_TEMP(1,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(20)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(20)<1> ubCURR_UV(26,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(20)<1> wDIFF_TEMPORAL(20)<16;16,1> ubCURR_UV(26,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(21)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(21)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(27,2)<8;8,1> -uwCURBE_TEMP(1,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(27,10)<8;8,1> -uwCURBE_TEMP(1,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(27,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,80)<8;8,1> uwCURBE_TEMP(1,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,88)<8;8,1> uwCURBE_TEMP(1,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(21)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(21)<1> ubCURR_UV(27,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(21)<1> wDIFF_TEMPORAL(21)<16;16,1> ubCURR_UV(27,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(22)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(22)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(28,2)<8;8,1> -uwCURBE_TEMP(1,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(28,10)<8;8,1> -uwCURBE_TEMP(1,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(28,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,96)<8;8,1> uwCURBE_TEMP(1,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,104)<8;8,1> uwCURBE_TEMP(1,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(22)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(22)<1> ubCURR_UV(28,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(22)<1> wDIFF_TEMPORAL(22)<16;16,1> ubCURR_UV(28,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(23)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(23)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(29,2)<8;8,1> -uwCURBE_TEMP(1,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(29,10)<8;8,1> -uwCURBE_TEMP(1,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(29,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,112)<8;8,1> uwCURBE_TEMP(1,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,120)<8;8,1> uwCURBE_TEMP(1,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(23)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(23)<1> ubCURR_UV(29,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(23)<1> wDIFF_TEMPORAL(23)<16;16,1> ubCURR_UV(29,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(24)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(24)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(30,2)<8;8,1> -uwCURBE_TEMP(1,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(30,10)<8;8,1> -uwCURBE_TEMP(1,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(30,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,128)<8;8,1> uwCURBE_TEMP(1,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,136)<8;8,1> uwCURBE_TEMP(1,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(24)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(24)<1> ubCURR_UV(30,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(24)<1> wDIFF_TEMPORAL(24)<16;16,1> ubCURR_UV(30,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(25)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(25)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(31,2)<8;8,1> -uwCURBE_TEMP(1,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(31,10)<8;8,1> -uwCURBE_TEMP(1,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(31,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,144)<8;8,1> uwCURBE_TEMP(1,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,152)<8;8,1> uwCURBE_TEMP(1,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(25)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(25)<1> ubCURR_UV(31,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(25)<1> wDIFF_TEMPORAL(25)<16;16,1> ubCURR_UV(31,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(26)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(26)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(32,2)<8;8,1> -uwCURBE_TEMP(1,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(32,10)<8;8,1> -uwCURBE_TEMP(1,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(32,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,160)<8;8,1> uwCURBE_TEMP(1,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,168)<8;8,1> uwCURBE_TEMP(1,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(26)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(26)<1> ubCURR_UV(32,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(26)<1> wDIFF_TEMPORAL(26)<16;16,1> ubCURR_UV(32,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(27)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(27)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(33,2)<8;8,1> -uwCURBE_TEMP(1,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(33,10)<8;8,1> -uwCURBE_TEMP(1,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(33,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,176)<8;8,1> uwCURBE_TEMP(1,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,184)<8;8,1> uwCURBE_TEMP(1,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(27)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(27)<1> ubCURR_UV(33,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(27)<1> wDIFF_TEMPORAL(27)<16;16,1> ubCURR_UV(33,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(28)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(28)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(34,2)<8;8,1> -uwCURBE_TEMP(1,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(34,10)<8;8,1> -uwCURBE_TEMP(1,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(34,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,192)<8;8,1> uwCURBE_TEMP(1,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,200)<8;8,1> uwCURBE_TEMP(1,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(28)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(28)<1> ubCURR_UV(34,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(28)<1> wDIFF_TEMPORAL(28)<16;16,1> ubCURR_UV(34,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wCURBE_TEMP(4)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wCURBE_TEMP(4)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(35,2)<8;8,1> -uwCURBE_TEMP(1,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(35,10)<8;8,1> -uwCURBE_TEMP(1,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(35,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,208)<8;8,1> uwCURBE_TEMP(1,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,216)<8;8,1> uwCURBE_TEMP(1,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wCURBE_TEMP(4)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wCURBE_TEMP(4)<1> ubCURR_UV(35,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wCURBE_TEMP(4)<1> wCURBE_TEMP(4)<16;16,1> ubCURR_UV(35,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wCURBE_TEMP(5)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wCURBE_TEMP(5)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(36,2)<8;8,1> -uwCURBE_TEMP(1,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(36,10)<8;8,1> -uwCURBE_TEMP(1,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(36,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,224)<8;8,1> uwCURBE_TEMP(1,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,232)<8;8,1> uwCURBE_TEMP(1,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wCURBE_TEMP(5)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wCURBE_TEMP(5)<1> ubCURR_UV(36,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wCURBE_TEMP(5)<1> wCURBE_TEMP(5)<16;16,1> ubCURR_UV(36,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wCURBE_TEMP(6)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wCURBE_TEMP(6)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(37,2)<8;8,1> -uwCURBE_TEMP(1,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(37,10)<8;8,1> -uwCURBE_TEMP(1,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(37,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,240)<8;8,1> uwCURBE_TEMP(1,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,248)<8;8,1> uwCURBE_TEMP(1,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wCURBE_TEMP(6)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wCURBE_TEMP(6)<1> ubCURR_UV(37,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wCURBE_TEMP(6)<1> wCURBE_TEMP(6)<16;16,1> ubCURR_UV(37,2)<16;16,1> //Pack Weight History WORD -> BYTE mov (16) ubCURBE_TEMP(3,0)<1> ubCURBE_TEMP(0)<32;16,2> mov (16) ubCURBE_TEMP(3,16)<1> ubCURBE_TEMP(1)<32;16,2> //Module Name : DN_UV_Compute_BNE_UV //Author : Tatiya, Rupesh //Description : Computes minimum SOAD for each 16x4 block. cmp.l.f0.0 (8) null:w uwSOAD_MIN_8x4(0,12)<16;4,1> uwSOAD_MIN_8x4(2,12)<16;4,1> (f0.0)sel (8) uwCURBE_TEMP(1,0)<1> uwSOAD_MIN_8x4(0,12)<16;4,1> uwSOAD_MIN_8x4(2,12)<16;4,1> mov (8) ubCURBE_TEMP(1)<1> ubCURBE_TEMP(1)<16;8,2> //Module Name : DN_UV_YUY2_Pack_Denoised_UV //Name : Tatiya, Rupesh //Description : Pack UV denoised data based on YUY2 input. //Module Name : DN_UV_Pack_Denoised_UV //Name : Tatiya, Rupesh //Description : Pack UV denoised data based on PL2/PL3/PA. add (1) a0.0<1>:uw r54.21<0;1,0>:ub 2976:w add (1) a0.1<1>:uw r54.21<0;1,0>:ub 3264:w add (1) a0.2<1>:uw r54.21<0;1,0>:ub 3552:w add (1) a0.3<1>:uw r54.21<0;1,0>:ub 3840:w //First 8 lines. mov (16) r[a0.0, 0]<2>:ub ubDIFF_TEMPORAL(0)<32;16,2> mov (16) r[a0.0, 32]<2>:ub ubDIFF_TEMPORAL(1)<32;16,2> mov (16) r[a0.0, 64]<2>:ub ubDIFF_TEMPORAL(2)<32;16,2> mov (16) r[a0.0, 96]<2>:ub ubDIFF_TEMPORAL(3)<32;16,2> mov (16) r[a0.0, 128]<2>:ub ubDIFF_TEMPORAL(4)<32;16,2> mov (16) r[a0.0, 160]<2>:ub ubDIFF_TEMPORAL(5)<32;16,2> mov (16) r[a0.0, 192]<2>:ub ubDIFF_TEMPORAL(6)<32;16,2> mov (16) r[a0.0, 224]<2>:ub ubDIFF_TEMPORAL(7)<32;16,2> //Second 8 lines mov (16) r[a0.1, 0]<2>:ub ubDIFF_TEMPORAL(8)<32;16,2> mov (16) r[a0.1, 32]<2>:ub ubDIFF_TEMPORAL(9)<32;16,2> mov (16) r[a0.1, 64]<2>:ub ubDIFF_TEMPORAL(10)<32;16,2> mov (16) r[a0.1, 96]<2>:ub ubDIFF_TEMPORAL(11)<32;16,2> mov (16) r[a0.1, 128]<2>:ub ubDIFF_TEMPORAL(12)<32;16,2> mov (16) r[a0.1, 160]<2>:ub ubDIFF_TEMPORAL(13)<32;16,2> mov (16) r[a0.1, 192]<2>:ub ubDIFF_TEMPORAL(14)<32;16,2> mov (16) r[a0.1, 224]<2>:ub ubDIFF_TEMPORAL(15)<32;16,2> //Third 8 lines mov (16) r[a0.2, 0]<2>:ub ubDIFF_TEMPORAL(16)<32;16,2> mov (16) r[a0.2, 32]<2>:ub ubDIFF_TEMPORAL(17)<32;16,2> mov (16) r[a0.2, 64]<2>:ub ubDIFF_TEMPORAL(18)<32;16,2> mov (16) r[a0.2, 96]<2>:ub ubDIFF_TEMPORAL(19)<32;16,2> mov (16) r[a0.2, 128]<2>:ub ubDIFF_TEMPORAL(20)<32;16,2> mov (16) r[a0.2, 160]<2>:ub ubDIFF_TEMPORAL(21)<32;16,2> mov (16) r[a0.2, 192]<2>:ub ubDIFF_TEMPORAL(22)<32;16,2> mov (16) r[a0.2, 224]<2>:ub ubDIFF_TEMPORAL(23)<32;16,2> //Fourth 8 lines //5 lines first mov (16) r[a0.3, 0]<2>:ub ubDIFF_TEMPORAL(24)<32;16,2> mov (16) r[a0.3, 32]<2>:ub ubDIFF_TEMPORAL(25)<32;16,2> mov (16) r[a0.3, 64]<2>:ub ubDIFF_TEMPORAL(26)<32;16,2> mov (16) r[a0.3, 96]<2>:ub ubDIFF_TEMPORAL(27)<32;16,2> mov (16) r[a0.3, 128]<2>:ub ubDIFF_TEMPORAL(28)<32;16,2> //3 more lines mov (16) r[a0.3, 160]<2>:ub ubCURBE_TEMP(4)<32;16,2> mov (16) r[a0.3, 192]<2>:ub ubCURBE_TEMP(5)<32;16,2> mov (16) r[a0.3, 224]<2>:ub ubCURBE_TEMP(6)<32;16,2> //TODO - See if History saving can be combined with Curr Frame Save. - rT //Module Name : DN_UV_Save_Hist_UV //Author : Tatiya, Rupesh //Description : Saves DN history for UV data. mov (8) r3.0<1>:ud r0.0<8;8,1>:ud mov (2) r3.0<1>:d r62.12<2;2,1>:w mov (1) r3.2<1>:d 0x30007:ud send (8) null<1>:d r3 0x5 0x40A8021:ud //Module Name : DN_UV_Save_BNE_UV //Author : Tatiya, Rupesh //Description : Saves BNE values for 16x16 U and 16x16 V. mov (8) r1.0<1>:ud r0.0<8;8,1>:ud mov (2) r1.0<1>:d r63.12<2;2,1>:w mov (1) r1.2<1>:d 0x10003:ud send (8) null<1>:d r1 0x5 0x40A8023:ud //Module Name : DN_UV_YUY2_Save_Curr_Frame_YUV //Author : Tatiya, Rupesh //Module Name : DN_UV_Load_Curr_Frame_Y //Author : Tatiya, Rupesh //Description : Saves Y or YUY2 of Current frame. mov (8) acc0.0<1>:ud r0.0<8;8,1>:ud shl (1) r62.10<1>:w r62.10<0;1,0>:w 1:w mov (1) acc0.0<1>:d r62.10<0;1,0>:w mov (1) acc0.1<1>:d r62.11<0;1,0>:w mov (1) acc0.2<1>:d 0x7001F:ud mov (8) r92.0<1>:ud acc0.0<8;8,1>:ud mov (8) r101.0<1>:ud acc0.0<8;8,1>:ud mov (8) r110.0<1>:ud acc0.0<8;8,1>:ud mov (8) r119.0<1>:ud acc0.0<8;8,1>:ud add (1) r101.1<1>:d acc0.1<0;1,0>:d 8:d add (1) r110.0<1>:d acc0.0<0;1,0>:d 32:d add (1) r119.0<1>:d acc0.0<0;1,0>:d 32:d add (1) r119.1<1>:d acc0.1<0;1,0>:d 8:d send (8) null<1>:d r92 0x5 0x120A8018:ud send (8) null<1>:d r101 0x5 0x120A8018:ud send (8) null<1>:d r110 0x5 0x120A8018:ud send (8) null<1>:d r119 0x5 0x120A8018:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 //All sub-routines here // Module Name : Noise_Detection // Author : Tatiya, Rupesh // Description : Performs noise detection on 32 pixels of U (8x4) and 32 pixels of V (8x4). DN_UV_NOISE_DETECTION_UV: // Find Field Block Median // // Purpose : Find the median value of the nine pixels in the same field // which are centered at current pixel. // // Works on 9 pixels centered at the current pixel // NOTE: pixels are within same field. // v4 - current pixel // // v2 v1 v0 // * * * <--- Different field - not used // v5 v4 v3 // * * * <--- Different field - not used // v8 v7 v6 // Algorithm to find median modifies the data. // Copy the data needed to calculate median so the original source data stays intact. // //TODO - Change Interleaved implementation to separated one if - , does not work on predication. - rT //Delete Later - rT //mov (1) pCUR_UV:uw 52*32:uw // v0 mov (16) ubMEDIAN_TEMP(0,0)<1> r[a0.0,0]<16;16,1> // v0 mov (16) ubMEDIAN_TEMP(0,16)<1> r[a0.0,32]<16;16,1> // v1 mov (16) ubMEDIAN_TEMP(1,0)<1> r[a0.0,2]<16;16,1> // v1 mov (16) ubMEDIAN_TEMP(1,16)<1> r[a0.0,34]<16;16,1> // v2 mov (16) ubMEDIAN_TEMP(2,0)<1> r[a0.0,4]<16;16,1> // v2 mov (16) ubMEDIAN_TEMP(2,16)<1> r[a0.0,36]<16;16,1> // v3 mov (16) ubMEDIAN_TEMP(3,0)<1> r[a0.0,64]<16;16,1> // v3 mov (16) ubMEDIAN_TEMP(3,16)<1> r[a0.0,96]<16;16,1> // v4 mov (16) ubMEDIAN_TEMP(4,0)<1> r[a0.0,66]<16;16,1> // v4 mov (16) ubMEDIAN_TEMP(4,16)<1> r[a0.0,98]<16;16,1> // v5 mov (16) ubMEDIAN_TEMP(5,0)<1> r[a0.0,68]<16;16,1> // v5 mov (16) ubMEDIAN_TEMP(5,16)<1> r[a0.0,100]<16;16,1> // v6 mov (16) ubMEDIAN_TEMP(6,0)<1> r[a0.0,128]<16;16,1> // v6 mov (16) ubMEDIAN_TEMP(6,16)<1> r[a0.0,160]<16;16,1> // v7 mov (16) ubMEDIAN_TEMP(7,0)<1> r[a0.0,130]<16;16,1> // v7 mov (16) ubMEDIAN_TEMP(7,16)<1> r[a0.0,162]<16;16,1> // v8 mov (16) ubMEDIAN_TEMP(8,0)<1> r[a0.0,132]<16;16,1> // v8 mov (16) ubMEDIAN_TEMP(8,16)<1> r[a0.0,164]<16;16,1> //TODO - Optimize one instruction here. add (1) a0.0:uw a0.0<0;1,0>:uw 64:uw // v0 mov (16) ubMEDIAN_TEMP(9,0)<1> r[a0.0,0]<16;16,1> // v0 mov (16) ubMEDIAN_TEMP(9,16)<1> r[a0.0,32]<16;16,1> // v1 mov (16) ubMEDIAN_TEMP(10,0)<1> r[a0.0,2]<16;16,1> // v1 mov (16) ubMEDIAN_TEMP(10,16)<1> r[a0.0,34]<16;16,1> // v2 mov (16) ubMEDIAN_TEMP(11,0)<1> r[a0.0,4]<16;16,1> // v2 mov (16) ubMEDIAN_TEMP(11,16)<1> r[a0.0,36]<16;16,1> // v3 mov (16) ubMEDIAN_TEMP(12,0)<1> r[a0.0,64]<16;16,1> // v3 mov (16) ubMEDIAN_TEMP(12,16)<1> r[a0.0,96]<16;16,1> // v4 mov (16) ubMEDIAN_TEMP(13,0)<1> r[a0.0,66]<16;16,1> // v4 mov (16) ubMEDIAN_TEMP(13,16)<1> r[a0.0,98]<16;16,1> // v5 mov (16) ubMEDIAN_TEMP(14,0)<1> r[a0.0,68]<16;16,1> // v5 mov (16) ubMEDIAN_TEMP(14,16)<1> r[a0.0,100]<16;16,1> // v6 mov (16) ubMEDIAN_TEMP(15,0)<1> r[a0.0,128]<16;16,1> // v6 mov (16) ubMEDIAN_TEMP(15,16)<1> r[a0.0,160]<16;16,1> // v7 mov (16) ubMEDIAN_TEMP(16,0)<1> r[a0.0,130]<16;16,1> // v7 mov (16) ubMEDIAN_TEMP(16,16)<1> r[a0.0,162]<16;16,1> // v8 mov (16) ubMEDIAN_TEMP(17,0)<1> r[a0.0,132]<16;16,1> // v8 mov (16) ubMEDIAN_TEMP(17,16)<1> r[a0.0,164]<16;16,1> //TODO - Optimize one instruction here. add (1) a0.0:uw a0.0<0;1,0>:uw 64:uw // MedianSwap // // MedianSwap(inOutLeft, inOutRight) // { // if (inOutLeft > inOutRight) // { // temp = inOutLeft // inOutLeft = inOutRight // inOutRight = temp // } // } // MedianSwap(v1, v2) - U // MedianSwap(v4, v5) - U // MedianSwap(v1, v2) - V // MedianSwap(v4, v5) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(1,0)<32;16,2> ubMEDIAN_TEMP(2,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(5,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(1,1)<32;16,2> ubMEDIAN_TEMP(2,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(5,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(1,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(4,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(1,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(1,0)<2> ubMEDIAN_TEMP(2,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(5,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(1,1)<2> ubMEDIAN_TEMP(2,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(5,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(2,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(5,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(2,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(5,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v7, v8) - U // MedianSwap(v0, v1) - U // MedianSwap(v7, v8) - V // MedianSwap(v0, v1) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(7,0)<32;16,2> ubMEDIAN_TEMP(8,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(0,0)<32;16,2> ubMEDIAN_TEMP(1,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(7,1)<32;16,2> ubMEDIAN_TEMP(8,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(0,1)<32;16,2> ubMEDIAN_TEMP(1,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(7,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(0,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(7,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(0,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(7,0)<2> ubMEDIAN_TEMP(8,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(0,0)<2> ubMEDIAN_TEMP(1,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(7,1)<2> ubMEDIAN_TEMP(8,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(0,1)<2> ubMEDIAN_TEMP(1,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(8,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(1,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(8,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(1,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v3, v4) - U // MedianSwap(v6, v7) - U // MedianSwap(v3, v4) - V // MedianSwap(v6, v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(3,0)<32;16,2> ubMEDIAN_TEMP(4,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(6,0)<32;16,2> ubMEDIAN_TEMP(7,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(3,1)<32;16,2> ubMEDIAN_TEMP(4,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(6,1)<32;16,2> ubMEDIAN_TEMP(7,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(3,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(6,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(3,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(6,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(3,0)<2> ubMEDIAN_TEMP(4,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(6,0)<2> ubMEDIAN_TEMP(7,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(3,1)<2> ubMEDIAN_TEMP(4,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(6,1)<2> ubMEDIAN_TEMP(7,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(4,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(7,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(4,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(7,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v1, v2) - U // MedianSwap(v4, v5) - U // MedianSwap(v1, v2) - V // MedianSwap(v4, v5) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(1,0)<32;16,2> ubMEDIAN_TEMP(2,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(5,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(1,1)<32;16,2> ubMEDIAN_TEMP(2,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(5,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(1,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(4,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(1,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(1,0)<2> ubMEDIAN_TEMP(2,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(5,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(1,1)<2> ubMEDIAN_TEMP(2,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(5,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(2,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(5,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(2,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(5,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v7, v8) - U // MedianSwap(v0, v3) - U // MedianSwap(v7, v8) - V // MedianSwap(v0, v3) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(7,0)<32;16,2> ubMEDIAN_TEMP(8,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(0,0)<32;16,2> ubMEDIAN_TEMP(3,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(7,1)<32;16,2> ubMEDIAN_TEMP(8,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(0,1)<32;16,2> ubMEDIAN_TEMP(3,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(7,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(0,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(7,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(0,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(7,0)<2> ubMEDIAN_TEMP(8,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(0,0)<2> ubMEDIAN_TEMP(3,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(7,1)<2> ubMEDIAN_TEMP(8,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(0,1)<2> ubMEDIAN_TEMP(3,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(8,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(3,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(8,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(3,1)<2> ubTEMP1(1,16)<16;16,1> // NOTE: // Compare v0 to v6 to find the minimum. // Store the minimum for future use. //TODO - Find if MIN is needed. //cmp.l.f0.0 (16) null:w ubMEDIAN_TEMP(%1+0,0)<32;16,2> ubMEDIAN_TEMP(%1+6,0)<32;16,2> //cmp.l.f1.0 (16) null:w ubMEDIAN_TEMP(%1+0,1)<32;16,2> ubMEDIAN_TEMP(%1+6,1)<32;16,2> //(f0.0) mov (16) ubCURR_MIN(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+0,0)<32;16,2> //(f1.0) mov (16) ubCURR_MIN(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+0,1)<32;16,2> //(-f0.0) mov (16) ubCURR_MIN(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+6,0)<32;16,2> //(-f1.0) mov (16) ubCURR_MIN(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+6,1)<32;16,2> // MedianSwap(v5, v8) - U // MedianSwap(v4, v7) - U // MedianSwap(v5, v8) - V // MedianSwap(v4, v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(5,0)<32;16,2> ubMEDIAN_TEMP(8,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(7,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(5,1)<32;16,2> ubMEDIAN_TEMP(8,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(7,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(5,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(4,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(5,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(5,0)<2> ubMEDIAN_TEMP(8,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(7,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(5,1)<2> ubMEDIAN_TEMP(8,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(7,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(8,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(7,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(8,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(7,1)<2> ubTEMP1(1,16)<16;16,1> // NOTE: // Compare v2 to v8 to find the maximum. // Store the maximum for future use. //TODO - Find if MAX is needed. // cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(%1+2,0)<32;16,2> ubMEDIAN_TEMP(%1+8,0)<32;16,2> // cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(%1+2,1)<32;16,2> ubMEDIAN_TEMP(%1+8,1)<32;16,2> //(f0.0) mov (16) ubCURR_MAX(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+2,0)<32;16,2> //(f1.0) mov (16) ubCURR_MAX(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+2,1)<32;16,2> //(-f0.0) mov (16) ubCURR_MAX(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+8,0)<32;16,2> //(-f1.0) mov (16) ubCURR_MAX(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+8,1)<32;16,2> // MedianSwap(v3, v6) - U // MedianSwap(v1, v4) - U // MedianSwap(v3, v6) - V // MedianSwap(v1, v4) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(3,0)<32;16,2> ubMEDIAN_TEMP(6,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(1,0)<32;16,2> ubMEDIAN_TEMP(4,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(3,1)<32;16,2> ubMEDIAN_TEMP(6,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(1,1)<32;16,2> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(6,0)<2> ubMEDIAN_TEMP(3,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(1,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(6,1)<2> ubMEDIAN_TEMP(3,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(1,1)<32;16,2> // MedianSwap(v2,v5) - U // MedianSwap(v4,v7) - U // MedianSwap(v2,v5) - V // MedianSwap(v4,v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(2,0)<32;16,2> ubMEDIAN_TEMP(5,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(7,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(2,1)<32;16,2> ubMEDIAN_TEMP(5,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(7,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(2,0)<2> ubMEDIAN_TEMP(5,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(7,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(2,1)<2> ubMEDIAN_TEMP(5,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(7,1)<32;16,2> // MedianSwap(v4,v2) - U // MedianSwap(v4,v2) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(2,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(2,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(4,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(2,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(2,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(2,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(2,1)<2> ubTEMP1(0,16)<16;16,1> // MedianSwap(v6,v4) - U // MedianSwap(v6,v4) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(6,0)<32;16,2> ubMEDIAN_TEMP(4,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(6,1)<32;16,2> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(6,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(6,1)<32;16,2> // MedianSwap(v4,v2) - U // MedianSwap(v4,v2) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(2,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(2,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(2,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(2,1)<32;16,2> cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(10,0)<32;16,2> ubMEDIAN_TEMP(11,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(14,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(10,1)<32;16,2> ubMEDIAN_TEMP(11,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(14,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(10,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(13,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(10,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(10,0)<2> ubMEDIAN_TEMP(11,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(14,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(10,1)<2> ubMEDIAN_TEMP(11,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(14,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(11,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(14,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(11,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(14,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v7, v8) - U // MedianSwap(v0, v1) - U // MedianSwap(v7, v8) - V // MedianSwap(v0, v1) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(16,0)<32;16,2> ubMEDIAN_TEMP(17,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(9,0)<32;16,2> ubMEDIAN_TEMP(10,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(16,1)<32;16,2> ubMEDIAN_TEMP(17,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(9,1)<32;16,2> ubMEDIAN_TEMP(10,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(16,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(9,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(16,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(9,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(16,0)<2> ubMEDIAN_TEMP(17,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(9,0)<2> ubMEDIAN_TEMP(10,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(16,1)<2> ubMEDIAN_TEMP(17,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(9,1)<2> ubMEDIAN_TEMP(10,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(17,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(10,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(17,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(10,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v3, v4) - U // MedianSwap(v6, v7) - U // MedianSwap(v3, v4) - V // MedianSwap(v6, v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(12,0)<32;16,2> ubMEDIAN_TEMP(13,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(15,0)<32;16,2> ubMEDIAN_TEMP(16,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(12,1)<32;16,2> ubMEDIAN_TEMP(13,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(15,1)<32;16,2> ubMEDIAN_TEMP(16,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(12,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(15,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(12,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(15,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(12,0)<2> ubMEDIAN_TEMP(13,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(15,0)<2> ubMEDIAN_TEMP(16,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(12,1)<2> ubMEDIAN_TEMP(13,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(15,1)<2> ubMEDIAN_TEMP(16,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(13,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(16,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(13,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(16,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v1, v2) - U // MedianSwap(v4, v5) - U // MedianSwap(v1, v2) - V // MedianSwap(v4, v5) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(10,0)<32;16,2> ubMEDIAN_TEMP(11,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(14,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(10,1)<32;16,2> ubMEDIAN_TEMP(11,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(14,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(10,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(13,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(10,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(10,0)<2> ubMEDIAN_TEMP(11,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(14,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(10,1)<2> ubMEDIAN_TEMP(11,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(14,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(11,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(14,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(11,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(14,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v7, v8) - U // MedianSwap(v0, v3) - U // MedianSwap(v7, v8) - V // MedianSwap(v0, v3) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(16,0)<32;16,2> ubMEDIAN_TEMP(17,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(9,0)<32;16,2> ubMEDIAN_TEMP(12,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(16,1)<32;16,2> ubMEDIAN_TEMP(17,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(9,1)<32;16,2> ubMEDIAN_TEMP(12,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(16,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(9,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(16,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(9,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(16,0)<2> ubMEDIAN_TEMP(17,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(9,0)<2> ubMEDIAN_TEMP(12,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(16,1)<2> ubMEDIAN_TEMP(17,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(9,1)<2> ubMEDIAN_TEMP(12,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(17,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(12,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(17,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(12,1)<2> ubTEMP1(1,16)<16;16,1> // NOTE: // Compare v0 to v6 to find the minimum. // Store the minimum for future use. //TODO - Find if MIN is needed. //cmp.l.f0.0 (16) null:w ubMEDIAN_TEMP(%1+0,0)<32;16,2> ubMEDIAN_TEMP(%1+6,0)<32;16,2> //cmp.l.f1.0 (16) null:w ubMEDIAN_TEMP(%1+0,1)<32;16,2> ubMEDIAN_TEMP(%1+6,1)<32;16,2> //(f0.0) mov (16) ubCURR_MIN(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+0,0)<32;16,2> //(f1.0) mov (16) ubCURR_MIN(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+0,1)<32;16,2> //(-f0.0) mov (16) ubCURR_MIN(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+6,0)<32;16,2> //(-f1.0) mov (16) ubCURR_MIN(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+6,1)<32;16,2> // MedianSwap(v5, v8) - U // MedianSwap(v4, v7) - U // MedianSwap(v5, v8) - V // MedianSwap(v4, v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(14,0)<32;16,2> ubMEDIAN_TEMP(17,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(16,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(14,1)<32;16,2> ubMEDIAN_TEMP(17,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(16,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(14,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(13,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(14,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(14,0)<2> ubMEDIAN_TEMP(17,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(16,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(14,1)<2> ubMEDIAN_TEMP(17,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(16,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(17,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(16,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(17,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(16,1)<2> ubTEMP1(1,16)<16;16,1> // NOTE: // Compare v2 to v8 to find the maximum. // Store the maximum for future use. //TODO - Find if MAX is needed. // cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(%1+2,0)<32;16,2> ubMEDIAN_TEMP(%1+8,0)<32;16,2> // cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(%1+2,1)<32;16,2> ubMEDIAN_TEMP(%1+8,1)<32;16,2> //(f0.0) mov (16) ubCURR_MAX(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+2,0)<32;16,2> //(f1.0) mov (16) ubCURR_MAX(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+2,1)<32;16,2> //(-f0.0) mov (16) ubCURR_MAX(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+8,0)<32;16,2> //(-f1.0) mov (16) ubCURR_MAX(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+8,1)<32;16,2> // MedianSwap(v3, v6) - U // MedianSwap(v1, v4) - U // MedianSwap(v3, v6) - V // MedianSwap(v1, v4) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(12,0)<32;16,2> ubMEDIAN_TEMP(15,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(10,0)<32;16,2> ubMEDIAN_TEMP(13,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(12,1)<32;16,2> ubMEDIAN_TEMP(15,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(10,1)<32;16,2> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(15,0)<2> ubMEDIAN_TEMP(12,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(10,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(15,1)<2> ubMEDIAN_TEMP(12,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(10,1)<32;16,2> // MedianSwap(v2,v5) - U // MedianSwap(v4,v7) - U // MedianSwap(v2,v5) - V // MedianSwap(v4,v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(11,0)<32;16,2> ubMEDIAN_TEMP(14,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(16,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(11,1)<32;16,2> ubMEDIAN_TEMP(14,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(16,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(11,0)<2> ubMEDIAN_TEMP(14,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(16,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(11,1)<2> ubMEDIAN_TEMP(14,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(16,1)<32;16,2> // MedianSwap(v4,v2) - U // MedianSwap(v4,v2) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(11,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(11,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(13,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(11,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(11,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(11,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(11,1)<2> ubTEMP1(0,16)<16;16,1> // MedianSwap(v6,v4) - U // MedianSwap(v6,v4) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(15,0)<32;16,2> ubMEDIAN_TEMP(13,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(15,1)<32;16,2> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(15,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(15,1)<32;16,2> // MedianSwap(v4,v2) - U // MedianSwap(v4,v2) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(11,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(11,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(11,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(11,1)<32;16,2> // Sobel Value calculation for the current pixel v4 // v2 v1 v0 // * * * <--- Different field - not used // v5 v4 v3 // * * * <--- Different field - not used // v8 v7 v6 // // Gx = -v0 - 2*v3 - v6 + v2 + 2*v5 + v8 // Gy = v0 + 2*v1 + v2 - v6 - 2*v7 - v8 // // Sobel = (|Gx| + |Gy|) >> 3 //TODO - Change Later - rT add (1) a0.0:uw a0.0<0;1,0>:uw -128:uw // - 2 * v3 mul (16) acc0.0<1>:w r[a0.0,64]<16;16,1>:ub -2:w // + v8 mac (16) acc0.0<1>:w r[a0.0,132]<16;16,1>:ub 1:w // - v0 mac (16) acc0.0<1>:w r[a0.0,0]<16;16,1>:ub -1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,128]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,4]<16;16,1>:ub 1:w // + 2 * v5 mac (16) wSOBEL_X(0)<1> r[a0.0,68]<16;16,1>:ub 2:w // - 2 * v3 mul (16) acc0.0<1>:w r[a0.0,96]<16;16,1>:ub -2:w // + v8 mac (16) acc0.0<1>:w r[a0.0,164]<16;16,1>:ub 1:w // - v0 mac (16) acc0.0<1>:w r[a0.0,32]<16;16,1>:ub -1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,160]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,36]<16;16,1>:ub 1:w // + 2 * v5 mac (16) wSOBEL_X(1)<1> r[a0.0,100]<16;16,1>:ub 2:w // - 2 * v3 mul (16) acc0.0<1>:w r[a0.0,128]<16;16,1>:ub -2:w // + v8 mac (16) acc0.0<1>:w r[a0.0,196]<16;16,1>:ub 1:w // - v0 mac (16) acc0.0<1>:w r[a0.0,64]<16;16,1>:ub -1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,192]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,68]<16;16,1>:ub 1:w // + 2 * v5 mac (16) wSOBEL_X(2)<1> r[a0.0,132]<16;16,1>:ub 2:w // - 2 * v3 mul (16) acc0.0<1>:w r[a0.0,160]<16;16,1>:ub -2:w // + v8 mac (16) acc0.0<1>:w r[a0.0,228]<16;16,1>:ub 1:w // - v0 mac (16) acc0.0<1>:w r[a0.0,96]<16;16,1>:ub -1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,224]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,100]<16;16,1>:ub 1:w // + 2 * v5 mac (16) wSOBEL_X(3)<1> r[a0.0,164]<16;16,1>:ub 2:w // + 2 * v1 mul (16) acc0.0<1>:w r[a0.0,2]<16;16,1>:ub 2:w // + v0 mac (16) acc0.0<1>:w r[a0.0,0]<16;16,1>:ub 1:w // - v8 mac (16) acc0.0<1>:w r[a0.0,132]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,4]<16;16,1>:ub 1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,128]<16;16,1>:ub -1:w // - 2 * v7 mac (16) acc0.0<1>:w r[a0.0,130]<16;16,1>:ub -2:w add (16) acc0.0<1>:uw (abs)acc0.0<16;16,1>:w (abs)wSOBEL_X(0)<16;16,1> shr (16) uwSOBEL(0)<1> acc0.0<16;16,1>:uw 3:uw // + 2 * v1 mul (16) acc0.0<1>:w r[a0.0,34]<16;16,1>:ub 2:w // + v0 mac (16) acc0.0<1>:w r[a0.0,32]<16;16,1>:ub 1:w // - v8 mac (16) acc0.0<1>:w r[a0.0,164]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,36]<16;16,1>:ub 1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,160]<16;16,1>:ub -1:w // - 2 * v7 mac (16) acc0.0<1>:w r[a0.0,162]<16;16,1>:ub -2:w add (16) acc0.0<1>:uw (abs)acc0.0<16;16,1>:w (abs)wSOBEL_X(1)<16;16,1> shr (16) uwSOBEL(1)<1> acc0.0<16;16,1>:uw 3:uw // + 2 * v1 mul (16) acc0.0<1>:w r[a0.0,66]<16;16,1>:ub 2:w // + v0 mac (16) acc0.0<1>:w r[a0.0,64]<16;16,1>:ub 1:w // - v8 mac (16) acc0.0<1>:w r[a0.0,196]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,68]<16;16,1>:ub 1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,192]<16;16,1>:ub -1:w // - 2 * v7 mac (16) acc0.0<1>:w r[a0.0,194]<16;16,1>:ub -2:w add (16) acc0.0<1>:uw (abs)acc0.0<16;16,1>:w (abs)wSOBEL_X(2)<16;16,1> shr (16) uwSOBEL(2)<1> acc0.0<16;16,1>:uw 3:uw // + 2 * v1 mul (16) acc0.0<1>:w r[a0.0,98]<16;16,1>:ub 2:w // + v0 mac (16) acc0.0<1>:w r[a0.0,96]<16;16,1>:ub 1:w // - v8 mac (16) acc0.0<1>:w r[a0.0,228]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,100]<16;16,1>:ub 1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,224]<16;16,1>:ub -1:w // - 2 * v7 mac (16) acc0.0<1>:w r[a0.0,226]<16;16,1>:ub -2:w add (16) acc0.0<1>:uw (abs)acc0.0<16;16,1>:w (abs)wSOBEL_X(3)<16;16,1> shr (16) uwSOBEL(3)<1> acc0.0<16;16,1>:uw 3:uw //Mov Median in CURBE_TEMP to free up temp space. mov (16) ubMEDIAN(0,0)<1> ubMEDIAN_TEMP(4,0)<16;16,1> mov (16) ubMEDIAN(0,16)<1> ubMEDIAN_TEMP(4,16)<16;16,1> mov (16) ubMEDIAN(0,32)<1> ubMEDIAN_TEMP(13,0)<16;16,1> mov (16) ubMEDIAN(0,48)<1> ubMEDIAN_TEMP(13,16)<16;16,1> // Find: // absDiff = abs(ubCurY - ubMedian) // Find the difference between pixel and median value. //Median is interleaved. So difference is also interleaved. //------------------------------------------------------------------------------------------ //Process 16 U and 16 V pixels here and rest later. // first row - v0,v1,v2 add (16) wDIFF(0)<1> r[a0.0,0]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(1)<1> r[a0.0,2]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(2)<1> r[a0.0,4]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> // second row - v3,v4,v5 add (16) wDIFF(3)<1> r[a0.0,64]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(4)<1> r[a0.0,66]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(5)<1> r[a0.0,68]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> // third row - v6,v7,v8 add (16) wDIFF(6)<1> r[a0.0,128]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(7)<1> r[a0.0,130]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(8)<1> r[a0.0,132]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> // first row - v0,v1,v2 add (16) wDIFF(9)<1> r[a0.0,32]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(10)<1> r[a0.0,34]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(11)<1> r[a0.0,36]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> // second row - v3,v4,v5 add (16) wDIFF(12)<1> r[a0.0,96]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(13)<1> r[a0.0,98]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(14)<1> r[a0.0,100]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> // third row - v6,v7,v8 add (16) wDIFF(15)<1> r[a0.0,160]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(16)<1> r[a0.0,162]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(17)<1> r[a0.0,164]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> //TODO - Change Later - rT add (1) a0.0:uw a0.0<0;1,0>:uw 64:uw // Find sum of all absolute differences AND // maximum absolute difference for 16 U and 16 V here. //First 2 rows of 8x4 //Compare 0-1, 2-3, 4-5, 6-7 cmp.g.f0.0 (16) null:uw (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> cmp.g.f0.1 (16) null:uw (abs)wDIFF(2)<16;16,1> (abs)wDIFF(3)<16;16,1> cmp.g.f1.0 (16) null:uw (abs)wDIFF(4)<16;16,1> (abs)wDIFF(5)<16;16,1> cmp.g.f1.1 (16) null:uw (abs)wDIFF(6)<16;16,1> (abs)wDIFF(7)<16;16,1> //Calculate SAD add (16) acc0.0<1>:uw (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(2)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(3)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(4)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(5)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(6)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(7)<16;16,1> add (16) uwSOAD(0)<1> acc0.0<16;16,1>:uw (abs)wDIFF(8)<16;16,1> (f0.0) sel (16) uwCURBE_TEMP(0)<1> (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> (f0.1) sel (16) uwCURBE_TEMP(1)<1> (abs)wDIFF(2)<16;16,1> (abs)wDIFF(3)<16;16,1> (f1.0) sel (16) uwCURBE_TEMP(2)<1> (abs)wDIFF(4)<16;16,1> (abs)wDIFF(5)<16;16,1> (f1.1) sel (16) uwCURBE_TEMP(3)<1> (abs)wDIFF(6)<16;16,1> (abs)wDIFF(7)<16;16,1> //------------ //DIFF(0-7) is not needed here. Populate it. // first row - v0,v1,v2 add (16) wDIFF(0)<1> r[a0.0,0]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(1)<1> r[a0.0,2]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(2)<1> r[a0.0,4]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> // second row - v3,v4,v5 add (16) wDIFF(3)<1> r[a0.0,64]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(4)<1> r[a0.0,66]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(5)<1> r[a0.0,68]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> // third row - v6,v7 add (16) wDIFF(6)<1> r[a0.0,128]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(7)<1> r[a0.0,130]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> //------------ //Compare Max(0,1) - Max(2,3), Max(4,5) - Max(6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> cmp.g.f0.1 (16) null:uw uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> (f0.1)sel (16) uwCURBE_TEMP(2)<1> uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> //Compare Max(0,1,2,3) - Max(4,5,6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> //Compare Max(0,1,2,3,4,5,6,7) - 8 cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(8)<16;16,1> (f0.0)sel (16) uwMAX_ABS_DIFF(0)<1> uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(8)<16;16,1> //------------ //Load v8 - DIFF(8) add (16) wDIFF(8)<1> r[a0.0,132]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> //------------ //Compare 0-1, 2-3, 4-5, 6-7 cmp.g.f0.0 (16) null:uw (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> cmp.g.f0.1 (16) null:uw (abs)wDIFF(11)<16;16,1> (abs)wDIFF(12)<16;16,1> cmp.g.f1.0 (16) null:uw (abs)wDIFF(13)<16;16,1> (abs)wDIFF(14)<16;16,1> cmp.g.f1.1 (16) null:uw (abs)wDIFF(15)<16;16,1> (abs)wDIFF(16)<16;16,1> //Calculate SAD add (16) acc0.0<1>:uw (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(11)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(12)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(13)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(14)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(15)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(16)<16;16,1> add (16) uwSOAD(1)<1> acc0.0<16;16,1>:uw (abs)wDIFF(17)<16;16,1> (f0.0) sel (16) uwCURBE_TEMP(0)<1> (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> (f0.1) sel (16) uwCURBE_TEMP(1)<1> (abs)wDIFF(11)<16;16,1> (abs)wDIFF(12)<16;16,1> (f1.0) sel (16) uwCURBE_TEMP(2)<1> (abs)wDIFF(13)<16;16,1> (abs)wDIFF(14)<16;16,1> (f1.1) sel (16) uwCURBE_TEMP(3)<1> (abs)wDIFF(15)<16;16,1> (abs)wDIFF(16)<16;16,1> //------------ //DIFF(0-7) is not needed here. Populate it. // first row - v0,v1,v2 add (16) wDIFF(9)<1> r[a0.0,32]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(10)<1> r[a0.0,34]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(11)<1> r[a0.0,36]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> // second row - v3,v4,v5 add (16) wDIFF(12)<1> r[a0.0,96]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(13)<1> r[a0.0,98]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(14)<1> r[a0.0,100]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> // third row - v6,v7 add (16) wDIFF(15)<1> r[a0.0,160]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(16)<1> r[a0.0,162]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> //------------ //Compare Max(0,1) - Max(2,3), Max(4,5) - Max(6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> cmp.g.f0.1 (16) null:uw uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> (f0.1)sel (16) uwCURBE_TEMP(2)<1> uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> //Compare Max(0,1,2,3) - Max(4,5,6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> //Compare Max(0,1,2,3,4,5,6,7) - 8 cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(17)<16;16,1> (f0.0)sel (16) uwMAX_ABS_DIFF(1)<1> uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(17)<16;16,1> //------------ //Load v8 - DIFF(8) add (16) wDIFF(17)<1> r[a0.0,164]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> //------------ //if ((sobel_edge_measure < m_SobelEdgeThreshold) && ((block_max-block_min) < m_LocalDiffThreshold)) // if (sigma_mb_min > sigma) // sigma_mb_min = sigma; //NOTE: block_min is always zero as median is one of the value in 3x3 block. So no need o calculate it. // So just do - //if ((sobel_edge_measure < m_SobelEdgeThreshold) && ((block_max) < m_LocalDiffThreshold) && ( sigma < sigma_mb_min)) // sigma_mb_min = sigma; //We are processing 32 bytes of U and 32 bytes of V - each of size 8x4. //Compare first 8 bytes with max possible (255). //Start above condition from second 8 bytes. //TODO - Change Later - rT // mov (1) pCUR_MIN_SOAD_8x4:uw 1752:uw //r54.24:ub //First row of 8x4 cmp.l.f0.0 (16) null:uw uwSOBEL(0)<16;16,1> r55.30<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwMAX_ABS_DIFF(0)<16;16,1> r55.28<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwSOAD(0)<16;16,1> 255:uw (f0.0) sel (16) uwSOBEL(0)<1> uwSOAD(0)<16;16,1> 255:uw //Second row of 8x4 cmp.l.f0.0 (16) null:uw uwSOBEL(1)<16;16,1> r55.30<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwMAX_ABS_DIFF(1)<16;16,1> r55.28<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwSOAD(1)<16;16,1> uwSOBEL(0)<16;16,1> (f0.0) mov (16) uwSOBEL(0)<1> uwSOAD(1)<16;16,1> // Find sum of all absolute differences AND // maximum absolute difference for 16 U and 16 V here. //Second 2 rows of 8x4 //Compare 0-1, 2-3, 4-5, 6-7 cmp.g.f0.0 (16) null:uw (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> cmp.g.f0.1 (16) null:uw (abs)wDIFF(2)<16;16,1> (abs)wDIFF(3)<16;16,1> cmp.g.f1.0 (16) null:uw (abs)wDIFF(4)<16;16,1> (abs)wDIFF(5)<16;16,1> cmp.g.f1.1 (16) null:uw (abs)wDIFF(6)<16;16,1> (abs)wDIFF(7)<16;16,1> //Calculate SAD add (16) acc0.0<1>:uw (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(2)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(3)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(4)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(5)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(6)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(7)<16;16,1> add (16) uwSOAD(0)<1> acc0.0<16;16,1>:uw (abs)wDIFF(8)<16;16,1> (f0.0) sel (16) uwCURBE_TEMP(0)<1> (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> (f0.1) sel (16) uwCURBE_TEMP(1)<1> (abs)wDIFF(2)<16;16,1> (abs)wDIFF(3)<16;16,1> (f1.0) sel (16) uwCURBE_TEMP(2)<1> (abs)wDIFF(4)<16;16,1> (abs)wDIFF(5)<16;16,1> (f1.1) sel (16) uwCURBE_TEMP(3)<1> (abs)wDIFF(6)<16;16,1> (abs)wDIFF(7)<16;16,1> //Compare Max(0,1) - Max(2,3), Max(4,5) - Max(6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> cmp.g.f0.1 (16) null:uw uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> (f0.1)sel (16) uwCURBE_TEMP(2)<1> uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> //Compare Max(0,1,2,3) - Max(4,5,6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> //Compare Max(0,1,2,3,4,5,6,7) - 8 cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(8)<16;16,1> (f0.0)sel (16) uwMAX_ABS_DIFF(0)<1> uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(8)<16;16,1> //Compare 0-1, 2-3, 4-5, 6-7 cmp.g.f0.0 (16) null:uw (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> cmp.g.f0.1 (16) null:uw (abs)wDIFF(11)<16;16,1> (abs)wDIFF(12)<16;16,1> cmp.g.f1.0 (16) null:uw (abs)wDIFF(13)<16;16,1> (abs)wDIFF(14)<16;16,1> cmp.g.f1.1 (16) null:uw (abs)wDIFF(15)<16;16,1> (abs)wDIFF(16)<16;16,1> //Calculate SAD add (16) acc0.0<1>:uw (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(11)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(12)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(13)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(14)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(15)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(16)<16;16,1> add (16) uwSOAD(1)<1> acc0.0<16;16,1>:uw (abs)wDIFF(17)<16;16,1> (f0.0) sel (16) uwCURBE_TEMP(0)<1> (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> (f0.1) sel (16) uwCURBE_TEMP(1)<1> (abs)wDIFF(11)<16;16,1> (abs)wDIFF(12)<16;16,1> (f1.0) sel (16) uwCURBE_TEMP(2)<1> (abs)wDIFF(13)<16;16,1> (abs)wDIFF(14)<16;16,1> (f1.1) sel (16) uwCURBE_TEMP(3)<1> (abs)wDIFF(15)<16;16,1> (abs)wDIFF(16)<16;16,1> //Compare Max(0,1) - Max(2,3), Max(4,5) - Max(6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> cmp.g.f0.1 (16) null:uw uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> (f0.1)sel (16) uwCURBE_TEMP(2)<1> uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> //Compare Max(0,1,2,3) - Max(4,5,6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> //Compare Max(0,1,2,3,4,5,6,7) - 8 cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(17)<16;16,1> (f0.0)sel (16) uwMAX_ABS_DIFF(1)<1> uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(17)<16;16,1> //Third row of 8x4 cmp.l.f0.0 (16) null:uw uwSOBEL(2)<16;16,1> r55.30<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwMAX_ABS_DIFF(0)<16;16,1> r55.28<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwSOAD(0)<16;16,1> uwSOBEL(0)<16;16,1> (f0.0) mov (16) uwSOBEL(0)<1> uwSOAD(0)<16;16,1> //Fourth row of 8x4 cmp.l.f0.0 (16) null:uw uwSOBEL(3)<16;16,1> r55.30<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwMAX_ABS_DIFF(1)<16;16,1> r55.28<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwSOAD(1)<16;16,1> uwSOBEL(0)<16;16,1> (f0.0) mov (16) uwSOBEL(0)<1> uwSOAD(1)<16;16,1> cmp.l.f0.0 (8) null:uw uwSOBEL(0,0)<8;8,1> uwSOBEL(0,8)<8;8,1> (f0.0) sel (8) uwSOBEL(0)<1> uwSOBEL(0,0)<8;8,1> uwSOBEL(0,8)<8;8,1> cmp.l.f0.0 (4) null:uw uwSOBEL(0,0)<4;4,1> uwSOBEL(0,4)<4;4,1> (f0.0) sel (4) uwSOBEL(0)<1> uwSOBEL(0,0)<4;4,1> uwSOBEL(0,4)<4;4,1> cmp.l.f0.0 (2) null:uw uwSOBEL(0,0)<2;2,1> uwSOBEL(0,2)<2;2,1> (f0.0) sel (2) r[a0.1,0]<1>:uw uwSOBEL(0,0)<2;2,1> uwSOBEL(0,2)<2;2,1> // End of common.inc mov (1) ip:ud r7.7<0;1,0>:d .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PA_DN_422CP.g4a000066400000000000000000000574451231401140700245200ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 114 // Total instruction count // 1 // Total kernel count .kernel PA_DN_422CP .code // FileName: DN_PA_Core.asm // Author: Vivek Kumar // Description: Tasks for DN only case (16x8 block) for Packed format // FileName: DN.asm // Author: Vivek Kumar // Description: Tasks for DN only case (16x8 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x49E8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(4,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DN_Hist_Save.asm // Author: Vivek Kumar // Description: Saves DN history data to statistics surface // Write denoise history to memory mov (8) r27<1>:ud r0.0<8;8,1>:ud // message header mov (2) mudMSGHDR_HIST(1)<1> udDNDI_RESP(4,0)<2;2,1> // Move denoise history to MRF (4x2) shr (2) r27.0<1>:ud r7.0<2;2,1>:w 2:w // X,Y origin / 4 add (1) r27.0<1>:ud r27.0<0;1,0>:ud r1.12<0;1,0>:uw { NoDDClr } // Add pitch to X origin mov (1) r27.2<1>:ud 0x10003:ud { NoDDChk } // block width and height mov (8) mudMSGHDR_HIST(0)<1> r27.0<8;8,1>:ud send (8) null<1>:d r22 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x50003:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | X | X | X | X | //---------------------------------------------------- //| X | SVCM | X | //---------------------------------------------------- //| SHCM | STAD | X | //---------------------------------------------------- //| X | X | //---------------------------------------------------- //| X | SVCM | X | //---------------------------------------------------- //| SHCM | STAD | X | //---------------------------------------------------- mov (1) mubMSGHDR_ENC_STATS(1,0)<1> ubDNDI_RESP(4,8)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (1) muwMSGHDR_ENC_STATS(1,3)<1> uwDNDI_RESP(4,11)<0;1,0> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) muwMSGHDR_ENC_STATS(1,4)<1> uwDNDI_RESP(4,12)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (1) muwMSGHDR_ENC_STATS(1,9)<1> uwDNDI_RESP(4,8)<0;1,0> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) muwMSGHDR_ENC_STATS(1,10)<1> uwDNDI_RESP(4,9)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DN_Save_PA.asm // Author: Vivek Kumar // Description: Save one 16x8 blocks of DN output in Packed format add (4) a0.4<1>:uw r2.28<4;4,1>:ub 1024:w // Initial Y,U,V offset in YUV422 block; it starts at m14 mov (8) mudMSGHDR_DN_OUT(0)<1> r0<8;8,1>:ud // message header shl (1) mdMSGHDR_DN_OUT(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin * 2 (422 output) mov (1) mdMSGHDR_DN_OUT(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_DN_OUT(0,2)<1> 0x7001F:ud { NoDDChk } // block width and height (32x8) mov (16) r[a0.4,0]<2>:ub ubDNDI_RESP(0,0)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,32]<2>:ub ubDNDI_RESP(0,16)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,64]<2>:ub ubDNDI_RESP(0,32)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,96]<2>:ub ubDNDI_RESP(0,48)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,128]<2>:ub ubDNDI_RESP(0,64)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,160]<2>:ub ubDNDI_RESP(0,80)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,192]<2>:ub ubDNDI_RESP(0,96)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,224]<2>:ub ubDNDI_RESP(0,112)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) r[a0.5,0]<4>:ub ubDNDI_RESP(5,1)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,0]<4>:ub ubDNDI_RESP(5,0)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,32]<4>:ub ubDNDI_RESP(5,17)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,32]<4>:ub ubDNDI_RESP(5,16)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,64]<4>:ub ubDNDI_RESP(5,33)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,64]<4>:ub ubDNDI_RESP(5,32)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,96]<4>:ub ubDNDI_RESP(5,49)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,96]<4>:ub ubDNDI_RESP(5,48)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,128]<4>:ub ubDNDI_RESP(5,65)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,128]<4>:ub ubDNDI_RESP(5,64)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,160]<4>:ub ubDNDI_RESP(5,81)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,160]<4>:ub ubDNDI_RESP(5,80)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,192]<4>:ub ubDNDI_RESP(5,97)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,192]<4>:ub ubDNDI_RESP(5,96)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,224]<4>:ub ubDNDI_RESP(5,113)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,224]<4>:ub ubDNDI_RESP(5,112)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization //send out data through data port send (8) null<1>:d r31.0 0x5 0x120A8018:ud // FileName: DN_Save_422CP_16x8.asm // Author: Vivek Kumar // Description: Save one 16x8 blocks of DN output to the color pipe in 4-2-2 format .declare mubMSGHDR_DN_OUT_2 Base=r36.0 ElementSize=1 Type=ub mov (8) mudMSGHDR_DN_OUT(0)<1> r0<8;8,1>:ud // message header shl (1) mdMSGHDR_DN_OUT(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin * 2 (422 output) mov (1) mdMSGHDR_DN_OUT(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_DN_OUT(0,2)<1> 0x7000F:ud { NoDDClr, NoDDChk } // block width and height (16x8) //M0.3 - 0 - CP Enable, 1 - Area of Interest, 3:2 Message Format(TBD), 4:3 - Ignored, 31:5 CP state pointer //Compose area-of-interest bit + color pipe state pointer or (1) mudMSGHDR_DN_OUT(0,3)<1> r2.4<0;1,0>:ud r7.26<0;1,0>:b { NoDDChk } // First 8 x 8 Block mov (8) mubMSGHDR_DN_OUT(1)<2> ubDNDI_RESP(0,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(1,16)<2> ubDNDI_RESP(0,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(2)<2> ubDNDI_RESP(0,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(2,16)<2> ubDNDI_RESP(0,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(3)<2> ubDNDI_RESP(0,64)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(3,16)<2> ubDNDI_RESP(0,80)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(4)<2> ubDNDI_RESP(0,96)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(4,16)<2> ubDNDI_RESP(0,112)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(1,1)<4> ubDNDI_RESP(5,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(1,17)<4> ubDNDI_RESP(5,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(1,3)<4> ubDNDI_RESP(5,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(1,19)<4> ubDNDI_RESP(5,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(2,1)<4> ubDNDI_RESP(5,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(2,17)<4> ubDNDI_RESP(5,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(2,3)<4> ubDNDI_RESP(5,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(2,19)<4> ubDNDI_RESP(5,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(3,1)<4> ubDNDI_RESP(5,65)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(3,17)<4> ubDNDI_RESP(5,81)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(3,3)<4> ubDNDI_RESP(5,64)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(3,19)<4> ubDNDI_RESP(5,80)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(4,1)<4> ubDNDI_RESP(5,97)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(4,17)<4> ubDNDI_RESP(5,113)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(4,3)<4> ubDNDI_RESP(5,96)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(4,19)<4> ubDNDI_RESP(5,112)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Second 8 x 8 Block mov (8) r36.0<1>:ud r31.0<8;8,1>:ud add (1) r36.0<1>:ud r36.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DN_OUT_2(1)<2> ubDNDI_RESP(0,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(1,16)<2> ubDNDI_RESP(0,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(2)<2> ubDNDI_RESP(0,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(2,16)<2> ubDNDI_RESP(0,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(3)<2> ubDNDI_RESP(0,72)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(3,16)<2> ubDNDI_RESP(0,88)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(4)<2> ubDNDI_RESP(0,104)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(4,16)<2> ubDNDI_RESP(0,120)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(1,1)<4> ubDNDI_RESP(5,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(1,17)<4> ubDNDI_RESP(5,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(1,3)<4> ubDNDI_RESP(5,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(1,19)<4> ubDNDI_RESP(5,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(2,1)<4> ubDNDI_RESP(5,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(2,17)<4> ubDNDI_RESP(5,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(2,3)<4> ubDNDI_RESP(5,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(2,19)<4> ubDNDI_RESP(5,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(3,1)<4> ubDNDI_RESP(5,73)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(3,17)<4> ubDNDI_RESP(5,89)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(3,3)<4> ubDNDI_RESP(5,72)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(3,19)<4> ubDNDI_RESP(5,88)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(4,1)<4> ubDNDI_RESP(5,105)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(4,17)<4> ubDNDI_RESP(5,121)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(4,3)<4> ubDNDI_RESP(5,104)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(4,19)<4> ubDNDI_RESP(5,120)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization //send out data through data port send (8) null<1>:d r31.0 0x5 0xA0A801B:ud send (8) null<1>:d r36.0 0x5 0xA0A801B:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PA_DN_PA.g4a000066400000000000000000000402451231401140700242540ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 57 // Total instruction count // 1 // Total kernel count .kernel PA_DN_PA .code // FileName: DN_PA_Core.asm // Author: Vivek Kumar // Description: Tasks for DN only case (16x8 block) for Packed format // FileName: DN.asm // Author: Vivek Kumar // Description: Tasks for DN only case (16x8 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x49E8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(4,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DN_Hist_Save.asm // Author: Vivek Kumar // Description: Saves DN history data to statistics surface // Write denoise history to memory mov (8) r27<1>:ud r0.0<8;8,1>:ud // message header mov (2) mudMSGHDR_HIST(1)<1> udDNDI_RESP(4,0)<2;2,1> // Move denoise history to MRF (4x2) shr (2) r27.0<1>:ud r7.0<2;2,1>:w 2:w // X,Y origin / 4 add (1) r27.0<1>:ud r27.0<0;1,0>:ud r1.12<0;1,0>:uw { NoDDClr } // Add pitch to X origin mov (1) r27.2<1>:ud 0x10003:ud { NoDDChk } // block width and height mov (8) mudMSGHDR_HIST(0)<1> r27.0<8;8,1>:ud send (8) null<1>:d r22 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x50003:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | X | X | X | X | //---------------------------------------------------- //| X | SVCM | X | //---------------------------------------------------- //| SHCM | STAD | X | //---------------------------------------------------- //| X | X | //---------------------------------------------------- //| X | SVCM | X | //---------------------------------------------------- //| SHCM | STAD | X | //---------------------------------------------------- mov (1) mubMSGHDR_ENC_STATS(1,0)<1> ubDNDI_RESP(4,8)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (1) muwMSGHDR_ENC_STATS(1,3)<1> uwDNDI_RESP(4,11)<0;1,0> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) muwMSGHDR_ENC_STATS(1,4)<1> uwDNDI_RESP(4,12)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (1) muwMSGHDR_ENC_STATS(1,9)<1> uwDNDI_RESP(4,8)<0;1,0> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) muwMSGHDR_ENC_STATS(1,10)<1> uwDNDI_RESP(4,9)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DN_Save_PA.asm // Author: Vivek Kumar // Description: Save one 16x8 blocks of DN output in Packed format add (4) a0.4<1>:uw r2.28<4;4,1>:ub 1024:w // Initial Y,U,V offset in YUV422 block; it starts at m14 mov (8) mudMSGHDR_DN_OUT(0)<1> r0<8;8,1>:ud // message header shl (1) mdMSGHDR_DN_OUT(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin * 2 (422 output) mov (1) mdMSGHDR_DN_OUT(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_DN_OUT(0,2)<1> 0x7001F:ud { NoDDChk } // block width and height (32x8) mov (16) r[a0.4,0]<2>:ub ubDNDI_RESP(0,0)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,32]<2>:ub ubDNDI_RESP(0,16)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,64]<2>:ub ubDNDI_RESP(0,32)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,96]<2>:ub ubDNDI_RESP(0,48)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,128]<2>:ub ubDNDI_RESP(0,64)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,160]<2>:ub ubDNDI_RESP(0,80)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,192]<2>:ub ubDNDI_RESP(0,96)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (16) r[a0.4,224]<2>:ub ubDNDI_RESP(0,112)<16;16,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) r[a0.5,0]<4>:ub ubDNDI_RESP(5,1)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,0]<4>:ub ubDNDI_RESP(5,0)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,32]<4>:ub ubDNDI_RESP(5,17)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,32]<4>:ub ubDNDI_RESP(5,16)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,64]<4>:ub ubDNDI_RESP(5,33)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,64]<4>:ub ubDNDI_RESP(5,32)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,96]<4>:ub ubDNDI_RESP(5,49)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,96]<4>:ub ubDNDI_RESP(5,48)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,128]<4>:ub ubDNDI_RESP(5,65)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,128]<4>:ub ubDNDI_RESP(5,64)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,160]<4>:ub ubDNDI_RESP(5,81)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,160]<4>:ub ubDNDI_RESP(5,80)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,192]<4>:ub ubDNDI_RESP(5,97)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,192]<4>:ub ubDNDI_RESP(5,96)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization mov (8) r[a0.5,224]<4>:ub ubDNDI_RESP(5,113)<16;8,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (8) r[a0.6,224]<4>:ub ubDNDI_RESP(5,112)<16;8,2> { NoDDChk } // copy line of V directly to memory as optimization //send out data through data port send (8) null<1>:d r31.0 0x5 0x120A8018:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a000066400000000000000000000471231231401140700251360ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 44 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_0.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. mov (1) r22.4<1>:ud 0x400040:ud //Check if layer is to be skipped // f0.1 pre-computed in Set_Layer_0 (-f0.1) jmpi (1) SKIP_AVS_LOAD_L0_0_ //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EB400:ud //msg desc mov (1) r16.2:ud 0x0000D000:ud // Enable Red channel mov (1) r25.7<1>:ud r7.7:ud { NoDDClr } mov (1) r25.1<1>:ud r7.12:uw { NoDDChk } // set the vertical block number mov (8) r17.0:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs // Gen7 AVS WA Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces // if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) // { // modified_u_coord = u_coord – 5.0/(256*width); //floating point // } // else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) // { // modified_u_coord = u_coord + 1.0/(256*width); //floating point // } // else{ // modified_u_coord = u_coord; // } // Where u_left = u – 2*du + 3*ddu for IEF On // And u_left = u for IEF Off case // // check whether Gen7 AVS WA is enabled, mov (1) r14.8:uw f0.0:uw // save f0.0 mov (1) r14.5:f r17.2<0;1,0>:f // save pixel 0 U for chroma and.nz.f0.0 (1) null<1>:uw r2.3:uw 0x2:uw (-f0.0)jmpi (1) GEN7_PL2_AVS_WA_DONE_L0_0_ // Gen7 AVS WA, check if IEF is ON for choosing Gen7 AVS WA formula and.nz.f0.0 (8) null<1>:uw r2.3<0;1,0>:uw 0x4:uw (f0.0)mov (8) acc0.0:f r17.2<0;1,0>:f (f0.0)mac (8) acc0.0:f r17.4<0;1,0>:f -2.0:f (f0.0)mac (8) acc0.0:f r17.6<0;1,0>:f 3.0:f (f0.0)mov (1) r14.2:f acc0:f // IEF ON, rTEMP3.2 = u_left (-f0.0)mov (1) r14.2:f r17.2<0;1,0>:f // IEF OFF, rTEMP3.2 = u_left and (1) r14.1:ud r2.3:uw 0xFFF8:uw asr (1) r14.1:ud r14.1:ud 3:d mov (1) r14.1:f r14.1:ud // Gen7 AVS WA, if (int)(u_left*width + 5.0/256) > (int)(u_left*width) mul (1) r14.0:f r14.2:f r14.1:f // rTEMP3.0 = u_left*width add (1) r14.2:f r14.0:f 0.01953125:f // rTEMP3.2 = u_left*width + 5.0/256 add (1) r14.3:f r14.0:f 0.99609375:f // rTEMP3.3 = u_left*width + 255.0/256 //Check if the values are < 0 and account for (int) cast of negative numbers //(int)(u_left*width) cmp.l.f0.0 (1) null<1>:f r14.0:f 0.00000000:f mov (1) r14.0:d r14.0:f (f0.0)add (1) r14.0:d r14.0<0;1,0>:d -1:d //(int)(u_left*width + 5.0/256) cmp.l.f0.0 (1) null<1>:f r14.2:f 0.00000000:f mov (1) r14.2:d r14.2:f (f0.0)add (1) r14.2:d r14.2<0;1,0>:d -1:d //(int)(u_left*width + 255.0/256) cmp.l.f0.0 (1) null<1>:f r14.3:f 0.00000000:f mov (1) r14.3:d r14.3:f (f0.0)add (1) r14.3:d r14.3<0;1,0>:d -1:d mov (1) f0.0:uw 0:uw // clear flag //if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) cmp.g.f1.0 (1) null<1>:d r14.2:d r14.0:d // modified_u_coord = u_coord – 5.0/(256*width); //floating point (f1.0) add (1) r17.2:f r17.2<0;1,0>:f -r2.3:f //else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) (-f1.0) cmp.e.f0.0 (1) null<1>:d r14.3:d r14.0:d // modified_u_coord = u_coord + 1.0/(256*width); //floating point (f0.0) add (1) r17.2:f r17.2<0;1,0>:f r2.2:f GEN7_PL2_AVS_WA_DONE_L0_0_: mov (1) f0.0:uw r14.8:uw // restore f0.0 send (1) uwBUFFER_0(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order mov (1) r17.2:f r14.5:f // restore pixel 0 U for chroma, No AVS WA for chroma add (1) a0.0:ud r23.5<0;1,0>:ud 0x48EB801:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2:ud 0x0000A000:ud // Enable Red+Blue channel send (1) uwBUFFER_0(4)<1> r16 0x2 a0.0:ud // Returns UV data in 8 GRFs in scrambled order SKIP_AVS_LOAD_L0_0_: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a000066400000000000000000000464341231401140700251430ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 42 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_1.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 1 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //Check if layer is to be skipped // f0.1 pre-computed in Set_Layer_0 (-f0.1) jmpi (1) SKIP_AVS_LOAD_L0_1_ //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EB400:ud //msg desc mov (1) r16.2:ud 0x0000D000:ud // Enable Red channel // set the vertical block number add (1) r25.1<1>:ud r7.12:uw 1:ud mov (8) r17.0:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs // Gen7 AVS WA Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces // if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) // { // modified_u_coord = u_coord – 5.0/(256*width); //floating point // } // else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) // { // modified_u_coord = u_coord + 1.0/(256*width); //floating point // } // else{ // modified_u_coord = u_coord; // } // Where u_left = u – 2*du + 3*ddu for IEF On // And u_left = u for IEF Off case // // check whether Gen7 AVS WA is enabled, mov (1) r14.8:uw f0.0:uw // save f0.0 mov (1) r14.5:f r17.2<0;1,0>:f // save pixel 0 U for chroma and.nz.f0.0 (1) null<1>:uw r2.3:uw 0x2:uw (-f0.0)jmpi (1) GEN7_PL2_AVS_WA_DONE_L0_1_ // Gen7 AVS WA, check if IEF is ON for choosing Gen7 AVS WA formula and.nz.f0.0 (8) null<1>:uw r2.3<0;1,0>:uw 0x4:uw (f0.0)mov (8) acc0.0:f r17.2<0;1,0>:f (f0.0)mac (8) acc0.0:f r17.4<0;1,0>:f -2.0:f (f0.0)mac (8) acc0.0:f r17.6<0;1,0>:f 3.0:f (f0.0)mov (1) r14.2:f acc0:f // IEF ON, rTEMP3.2 = u_left (-f0.0)mov (1) r14.2:f r17.2<0;1,0>:f // IEF OFF, rTEMP3.2 = u_left and (1) r14.1:ud r2.3:uw 0xFFF8:uw asr (1) r14.1:ud r14.1:ud 3:d mov (1) r14.1:f r14.1:ud // Gen7 AVS WA, if (int)(u_left*width + 5.0/256) > (int)(u_left*width) mul (1) r14.0:f r14.2:f r14.1:f // rTEMP3.0 = u_left*width add (1) r14.2:f r14.0:f 0.01953125:f // rTEMP3.2 = u_left*width + 5.0/256 add (1) r14.3:f r14.0:f 0.99609375:f // rTEMP3.3 = u_left*width + 255.0/256 //Check if the values are < 0 and account for (int) cast of negative numbers //(int)(u_left*width) cmp.l.f0.0 (1) null<1>:f r14.0:f 0.00000000:f mov (1) r14.0:d r14.0:f (f0.0)add (1) r14.0:d r14.0<0;1,0>:d -1:d //(int)(u_left*width + 5.0/256) cmp.l.f0.0 (1) null<1>:f r14.2:f 0.00000000:f mov (1) r14.2:d r14.2:f (f0.0)add (1) r14.2:d r14.2<0;1,0>:d -1:d //(int)(u_left*width + 255.0/256) cmp.l.f0.0 (1) null<1>:f r14.3:f 0.00000000:f mov (1) r14.3:d r14.3:f (f0.0)add (1) r14.3:d r14.3<0;1,0>:d -1:d mov (1) f0.0:uw 0:uw // clear flag //if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) cmp.g.f1.0 (1) null<1>:d r14.2:d r14.0:d // modified_u_coord = u_coord – 5.0/(256*width); //floating point (f1.0) add (1) r17.2:f r17.2<0;1,0>:f -r2.3:f //else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) (-f1.0) cmp.e.f0.0 (1) null<1>:d r14.3:d r14.0:d // modified_u_coord = u_coord + 1.0/(256*width); //floating point (f0.0) add (1) r17.2:f r17.2<0;1,0>:f r2.2:f GEN7_PL2_AVS_WA_DONE_L0_1_: mov (1) f0.0:uw r14.8:uw // restore f0.0 send (1) uwBUFFER_1(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order mov (1) r17.2:f r14.5:f // restore pixel 0 U for chroma, No AVS WA for chroma add (1) a0.0:ud r23.5<0;1,0>:ud 0x48EB801:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2:ud 0x0000A000:ud // Enable Red+Blue channel send (1) uwBUFFER_1(4)<1> r16 0x2 a0.0:ud // Returns UV data in 8 GRFs in scrambled order SKIP_AVS_LOAD_L0_1_: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a000066400000000000000000000464351231401140700251450ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 42 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_2.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 2 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //Check if layer is to be skipped // f0.1 pre-computed in Set_Layer_0 (-f0.1) jmpi (1) SKIP_AVS_LOAD_L0_2_ //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EB400:ud //msg desc mov (1) r16.2:ud 0x0000D000:ud // Enable Red channel // set the vertical block number add (1) r25.1<1>:ud r7.12:uw 2:ud mov (8) r17.0:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs // Gen7 AVS WA Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces // if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) // { // modified_u_coord = u_coord – 5.0/(256*width); //floating point // } // else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) // { // modified_u_coord = u_coord + 1.0/(256*width); //floating point // } // else{ // modified_u_coord = u_coord; // } // Where u_left = u – 2*du + 3*ddu for IEF On // And u_left = u for IEF Off case // // check whether Gen7 AVS WA is enabled, mov (1) r14.8:uw f0.0:uw // save f0.0 mov (1) r14.5:f r17.2<0;1,0>:f // save pixel 0 U for chroma and.nz.f0.0 (1) null<1>:uw r2.3:uw 0x2:uw (-f0.0)jmpi (1) GEN7_PL2_AVS_WA_DONE_L0_2_ // Gen7 AVS WA, check if IEF is ON for choosing Gen7 AVS WA formula and.nz.f0.0 (8) null<1>:uw r2.3<0;1,0>:uw 0x4:uw (f0.0)mov (8) acc0.0:f r17.2<0;1,0>:f (f0.0)mac (8) acc0.0:f r17.4<0;1,0>:f -2.0:f (f0.0)mac (8) acc0.0:f r17.6<0;1,0>:f 3.0:f (f0.0)mov (1) r14.2:f acc0:f // IEF ON, rTEMP3.2 = u_left (-f0.0)mov (1) r14.2:f r17.2<0;1,0>:f // IEF OFF, rTEMP3.2 = u_left and (1) r14.1:ud r2.3:uw 0xFFF8:uw asr (1) r14.1:ud r14.1:ud 3:d mov (1) r14.1:f r14.1:ud // Gen7 AVS WA, if (int)(u_left*width + 5.0/256) > (int)(u_left*width) mul (1) r14.0:f r14.2:f r14.1:f // rTEMP3.0 = u_left*width add (1) r14.2:f r14.0:f 0.01953125:f // rTEMP3.2 = u_left*width + 5.0/256 add (1) r14.3:f r14.0:f 0.99609375:f // rTEMP3.3 = u_left*width + 255.0/256 //Check if the values are < 0 and account for (int) cast of negative numbers //(int)(u_left*width) cmp.l.f0.0 (1) null<1>:f r14.0:f 0.00000000:f mov (1) r14.0:d r14.0:f (f0.0)add (1) r14.0:d r14.0<0;1,0>:d -1:d //(int)(u_left*width + 5.0/256) cmp.l.f0.0 (1) null<1>:f r14.2:f 0.00000000:f mov (1) r14.2:d r14.2:f (f0.0)add (1) r14.2:d r14.2<0;1,0>:d -1:d //(int)(u_left*width + 255.0/256) cmp.l.f0.0 (1) null<1>:f r14.3:f 0.00000000:f mov (1) r14.3:d r14.3:f (f0.0)add (1) r14.3:d r14.3<0;1,0>:d -1:d mov (1) f0.0:uw 0:uw // clear flag //if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) cmp.g.f1.0 (1) null<1>:d r14.2:d r14.0:d // modified_u_coord = u_coord – 5.0/(256*width); //floating point (f1.0) add (1) r17.2:f r17.2<0;1,0>:f -r2.3:f //else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) (-f1.0) cmp.e.f0.0 (1) null<1>:d r14.3:d r14.0:d // modified_u_coord = u_coord + 1.0/(256*width); //floating point (f0.0) add (1) r17.2:f r17.2<0;1,0>:f r2.2:f GEN7_PL2_AVS_WA_DONE_L0_2_: mov (1) f0.0:uw r14.8:uw // restore f0.0 send (1) uwBUFFER_2(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order mov (1) r17.2:f r14.5:f // restore pixel 0 U for chroma, No AVS WA for chroma add (1) a0.0:ud r23.5<0;1,0>:ud 0x48EB801:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2:ud 0x0000A000:ud // Enable Red+Blue channel send (1) uwBUFFER_2(4)<1> r16 0x2 a0.0:ud // Returns UV data in 8 GRFs in scrambled order SKIP_AVS_LOAD_L0_2_: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a000066400000000000000000000464351231401140700251460ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 42 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_3.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //Check if layer is to be skipped // f0.1 pre-computed in Set_Layer_0 (-f0.1) jmpi (1) SKIP_AVS_LOAD_L0_3_ //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EB400:ud //msg desc mov (1) r16.2:ud 0x0000D000:ud // Enable Red channel // set the vertical block number add (1) r25.1<1>:ud r7.12:uw 3:ud mov (8) r17.0:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs // Gen7 AVS WA Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces // if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) // { // modified_u_coord = u_coord – 5.0/(256*width); //floating point // } // else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) // { // modified_u_coord = u_coord + 1.0/(256*width); //floating point // } // else{ // modified_u_coord = u_coord; // } // Where u_left = u – 2*du + 3*ddu for IEF On // And u_left = u for IEF Off case // // check whether Gen7 AVS WA is enabled, mov (1) r14.8:uw f0.0:uw // save f0.0 mov (1) r14.5:f r17.2<0;1,0>:f // save pixel 0 U for chroma and.nz.f0.0 (1) null<1>:uw r2.3:uw 0x2:uw (-f0.0)jmpi (1) GEN7_PL2_AVS_WA_DONE_L0_3_ // Gen7 AVS WA, check if IEF is ON for choosing Gen7 AVS WA formula and.nz.f0.0 (8) null<1>:uw r2.3<0;1,0>:uw 0x4:uw (f0.0)mov (8) acc0.0:f r17.2<0;1,0>:f (f0.0)mac (8) acc0.0:f r17.4<0;1,0>:f -2.0:f (f0.0)mac (8) acc0.0:f r17.6<0;1,0>:f 3.0:f (f0.0)mov (1) r14.2:f acc0:f // IEF ON, rTEMP3.2 = u_left (-f0.0)mov (1) r14.2:f r17.2<0;1,0>:f // IEF OFF, rTEMP3.2 = u_left and (1) r14.1:ud r2.3:uw 0xFFF8:uw asr (1) r14.1:ud r14.1:ud 3:d mov (1) r14.1:f r14.1:ud // Gen7 AVS WA, if (int)(u_left*width + 5.0/256) > (int)(u_left*width) mul (1) r14.0:f r14.2:f r14.1:f // rTEMP3.0 = u_left*width add (1) r14.2:f r14.0:f 0.01953125:f // rTEMP3.2 = u_left*width + 5.0/256 add (1) r14.3:f r14.0:f 0.99609375:f // rTEMP3.3 = u_left*width + 255.0/256 //Check if the values are < 0 and account for (int) cast of negative numbers //(int)(u_left*width) cmp.l.f0.0 (1) null<1>:f r14.0:f 0.00000000:f mov (1) r14.0:d r14.0:f (f0.0)add (1) r14.0:d r14.0<0;1,0>:d -1:d //(int)(u_left*width + 5.0/256) cmp.l.f0.0 (1) null<1>:f r14.2:f 0.00000000:f mov (1) r14.2:d r14.2:f (f0.0)add (1) r14.2:d r14.2<0;1,0>:d -1:d //(int)(u_left*width + 255.0/256) cmp.l.f0.0 (1) null<1>:f r14.3:f 0.00000000:f mov (1) r14.3:d r14.3:f (f0.0)add (1) r14.3:d r14.3<0;1,0>:d -1:d mov (1) f0.0:uw 0:uw // clear flag //if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) cmp.g.f1.0 (1) null<1>:d r14.2:d r14.0:d // modified_u_coord = u_coord – 5.0/(256*width); //floating point (f1.0) add (1) r17.2:f r17.2<0;1,0>:f -r2.3:f //else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) (-f1.0) cmp.e.f0.0 (1) null<1>:d r14.3:d r14.0:d // modified_u_coord = u_coord + 1.0/(256*width); //floating point (f0.0) add (1) r17.2:f r17.2<0;1,0>:f r2.2:f GEN7_PL2_AVS_WA_DONE_L0_3_: mov (1) f0.0:uw r14.8:uw // restore f0.0 send (1) uwBUFFER_3(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order mov (1) r17.2:f r14.5:f // restore pixel 0 U for chroma, No AVS WA for chroma add (1) a0.0:ud r23.5<0;1,0>:ud 0x48EB801:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2:ud 0x0000A000:ud // Enable Red+Blue channel send (1) uwBUFFER_3(4)<1> r16 0x2 a0.0:ud // Returns UV data in 8 GRFs in scrambled order SKIP_AVS_LOAD_L0_3_: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a000066400000000000000000000474621231401140700251450ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 47 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL3_AVS_Buf_0.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL3 data into Buffer 0 // FileName : PL3_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL3 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. mov (1) r22.4<1>:ud 0x400040:ud //Check if layer is to be skipped // f0.1 pre-computed in Set_Layer_0 (-f0.1) jmpi (1) SKIP_AVS_LOAD_L0_0_ //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EB400:ud //msg desc mov (1) r16.2:ud 0x0000D000:ud // Enable Red channel mov (1) r25.7<1>:ud r7.7:ud { NoDDClr } mov (1) r25.1<1>:ud r7.12:uw { NoDDChk } // set the vertical block number mov (8) r17.0:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs // Gen7 AVS WA Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces // if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) // { // modified_u_coord = u_coord – 5.0/(256*width); //floating point // } // else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) // { // modified_u_coord = u_coord + 1.0/(256*width); //floating point // } // else{ // modified_u_coord = u_coord; // } // Where u_left = u – 2*du + 3*ddu for IEF On // And u_left = u for IEF Off case // // check whether Gen7 AVS WA is enabled, mov (1) r14.8:uw f0.0:uw // save f0.0 mov (1) r14.5:f r17.2<0;1,0>:f // save pixel 0 U for chroma and.nz.f0.0 (1) null<1>:uw r2.3:uw 0x2:uw (-f0.0)jmpi (1) GEN7_PL3_AVS_WA_DONE_L0_0_ // Gen7 AVS WA, check if IEF is ON for choosing Gen7 AVS WA formula and.nz.f0.0 (8) null<1>:uw r2.3<0;1,0>:uw 0x4:uw (f0.0)mov (8) acc0.0:f r17.2<0;1,0>:f (f0.0)mac (8) acc0.0:f r17.4<0;1,0>:f -2.0:f (f0.0)mac (8) acc0.0:f r17.6<0;1,0>:f 3.0:f (f0.0)mov (1) r14.2:f acc0:f // IEF ON, rTEMP3.2 = u_left (-f0.0)mov (1) r14.2:f r17.2<0;1,0>:f // IEF OFF, rTEMP3.2 = u_left and (1) r14.1:ud r2.3:uw 0xFFF8:uw asr (1) r14.1:ud r14.1:ud 3:d mov (1) r14.1:f r14.1:ud // Gen7 AVS WA, if (int)(u_left*width + 5.0/256) > (int)(u_left*width) mul (1) r14.0:f r14.2:f r14.1:f // rTEMP3.0 = u_left*width add (1) r14.2:f r14.0:f 0.01953125:f // rTEMP3.2 = u_left*width + 5.0/256 add (1) r14.3:f r14.0:f 0.99609375:f // rTEMP3.3 = u_left*width + 255.0/256 //Check if the values are < 0 and account for (int) cast of negative numbers //(int)(u_left*width) cmp.l.f0.0 (1) null<1>:f r14.0:f 0.00000000:f mov (1) r14.0:d r14.0:f (f0.0)add (1) r14.0:d r14.0<0;1,0>:d -1:d //(int)(u_left*width + 5.0/256) cmp.l.f0.0 (1) null<1>:f r14.2:f 0.00000000:f mov (1) r14.2:d r14.2:f (f0.0)add (1) r14.2:d r14.2<0;1,0>:d -1:d //(int)(u_left*width + 255.0/256) cmp.l.f0.0 (1) null<1>:f r14.3:f 0.00000000:f mov (1) r14.3:d r14.3:f (f0.0)add (1) r14.3:d r14.3<0;1,0>:d -1:d mov (1) f0.0:uw 0:uw // clear flag //if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) cmp.g.f1.0 (1) null<1>:d r14.2:d r14.0:d // modified_u_coord = u_coord – 5.0/(256*width); //floating point (f1.0) add (1) r17.2:f r17.2<0;1,0>:f -r2.3:f //else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) (-f1.0) cmp.e.f0.0 (1) null<1>:d r14.3:d r14.0:d // modified_u_coord = u_coord + 1.0/(256*width); //floating point (f0.0) add (1) r17.2:f r17.2<0;1,0>:f r2.2:f GEN7_PL3_AVS_WA_DONE_L0_0_: mov (1) f0.0:uw r14.8:uw // restore f0.0 send (1) uwBUFFER_0(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order mov (1) r17.2:f r14.5:f // restore pixel 0 U for chroma, No AVS WA for chroma add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EB801:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_0(4)<1> r16 0x2 a0.0:ud // Returns U data in 4 GRFs in scrambled order add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EBC02:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_0(8)<1> r16 0x2 a0.0:ud // Returns V data in 4 GRFs in scrambled order SKIP_AVS_LOAD_L0_0_: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a000066400000000000000000000467731231401140700251520ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 45 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL3_AVS_Buf_1.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL3 data into Buffer 1 // FileName : PL3_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL3 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //Check if layer is to be skipped // f0.1 pre-computed in Set_Layer_0 (-f0.1) jmpi (1) SKIP_AVS_LOAD_L0_1_ //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EB400:ud //msg desc mov (1) r16.2:ud 0x0000D000:ud // Enable Red channel // set the vertical block number add (1) r25.1<1>:ud r7.12:uw 1:ud mov (8) r17.0:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs // Gen7 AVS WA Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces // if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) // { // modified_u_coord = u_coord – 5.0/(256*width); //floating point // } // else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) // { // modified_u_coord = u_coord + 1.0/(256*width); //floating point // } // else{ // modified_u_coord = u_coord; // } // Where u_left = u – 2*du + 3*ddu for IEF On // And u_left = u for IEF Off case // // check whether Gen7 AVS WA is enabled, mov (1) r14.8:uw f0.0:uw // save f0.0 mov (1) r14.5:f r17.2<0;1,0>:f // save pixel 0 U for chroma and.nz.f0.0 (1) null<1>:uw r2.3:uw 0x2:uw (-f0.0)jmpi (1) GEN7_PL3_AVS_WA_DONE_L0_1_ // Gen7 AVS WA, check if IEF is ON for choosing Gen7 AVS WA formula and.nz.f0.0 (8) null<1>:uw r2.3<0;1,0>:uw 0x4:uw (f0.0)mov (8) acc0.0:f r17.2<0;1,0>:f (f0.0)mac (8) acc0.0:f r17.4<0;1,0>:f -2.0:f (f0.0)mac (8) acc0.0:f r17.6<0;1,0>:f 3.0:f (f0.0)mov (1) r14.2:f acc0:f // IEF ON, rTEMP3.2 = u_left (-f0.0)mov (1) r14.2:f r17.2<0;1,0>:f // IEF OFF, rTEMP3.2 = u_left and (1) r14.1:ud r2.3:uw 0xFFF8:uw asr (1) r14.1:ud r14.1:ud 3:d mov (1) r14.1:f r14.1:ud // Gen7 AVS WA, if (int)(u_left*width + 5.0/256) > (int)(u_left*width) mul (1) r14.0:f r14.2:f r14.1:f // rTEMP3.0 = u_left*width add (1) r14.2:f r14.0:f 0.01953125:f // rTEMP3.2 = u_left*width + 5.0/256 add (1) r14.3:f r14.0:f 0.99609375:f // rTEMP3.3 = u_left*width + 255.0/256 //Check if the values are < 0 and account for (int) cast of negative numbers //(int)(u_left*width) cmp.l.f0.0 (1) null<1>:f r14.0:f 0.00000000:f mov (1) r14.0:d r14.0:f (f0.0)add (1) r14.0:d r14.0<0;1,0>:d -1:d //(int)(u_left*width + 5.0/256) cmp.l.f0.0 (1) null<1>:f r14.2:f 0.00000000:f mov (1) r14.2:d r14.2:f (f0.0)add (1) r14.2:d r14.2<0;1,0>:d -1:d //(int)(u_left*width + 255.0/256) cmp.l.f0.0 (1) null<1>:f r14.3:f 0.00000000:f mov (1) r14.3:d r14.3:f (f0.0)add (1) r14.3:d r14.3<0;1,0>:d -1:d mov (1) f0.0:uw 0:uw // clear flag //if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) cmp.g.f1.0 (1) null<1>:d r14.2:d r14.0:d // modified_u_coord = u_coord – 5.0/(256*width); //floating point (f1.0) add (1) r17.2:f r17.2<0;1,0>:f -r2.3:f //else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) (-f1.0) cmp.e.f0.0 (1) null<1>:d r14.3:d r14.0:d // modified_u_coord = u_coord + 1.0/(256*width); //floating point (f0.0) add (1) r17.2:f r17.2<0;1,0>:f r2.2:f GEN7_PL3_AVS_WA_DONE_L0_1_: mov (1) f0.0:uw r14.8:uw // restore f0.0 send (1) uwBUFFER_1(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order mov (1) r17.2:f r14.5:f // restore pixel 0 U for chroma, No AVS WA for chroma add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EB801:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_1(4)<1> r16 0x2 a0.0:ud // Returns U data in 4 GRFs in scrambled order add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EBC02:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_1(8)<1> r16 0x2 a0.0:ud // Returns V data in 4 GRFs in scrambled order SKIP_AVS_LOAD_L0_1_: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a000066400000000000000000000467741231401140700251540ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 45 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL3_AVS_Buf_2.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL3 data into Buffer 2 // FileName : PL3_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL3 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //Check if layer is to be skipped // f0.1 pre-computed in Set_Layer_0 (-f0.1) jmpi (1) SKIP_AVS_LOAD_L0_2_ //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EB400:ud //msg desc mov (1) r16.2:ud 0x0000D000:ud // Enable Red channel // set the vertical block number add (1) r25.1<1>:ud r7.12:uw 2:ud mov (8) r17.0:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs // Gen7 AVS WA Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces // if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) // { // modified_u_coord = u_coord – 5.0/(256*width); //floating point // } // else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) // { // modified_u_coord = u_coord + 1.0/(256*width); //floating point // } // else{ // modified_u_coord = u_coord; // } // Where u_left = u – 2*du + 3*ddu for IEF On // And u_left = u for IEF Off case // // check whether Gen7 AVS WA is enabled, mov (1) r14.8:uw f0.0:uw // save f0.0 mov (1) r14.5:f r17.2<0;1,0>:f // save pixel 0 U for chroma and.nz.f0.0 (1) null<1>:uw r2.3:uw 0x2:uw (-f0.0)jmpi (1) GEN7_PL3_AVS_WA_DONE_L0_2_ // Gen7 AVS WA, check if IEF is ON for choosing Gen7 AVS WA formula and.nz.f0.0 (8) null<1>:uw r2.3<0;1,0>:uw 0x4:uw (f0.0)mov (8) acc0.0:f r17.2<0;1,0>:f (f0.0)mac (8) acc0.0:f r17.4<0;1,0>:f -2.0:f (f0.0)mac (8) acc0.0:f r17.6<0;1,0>:f 3.0:f (f0.0)mov (1) r14.2:f acc0:f // IEF ON, rTEMP3.2 = u_left (-f0.0)mov (1) r14.2:f r17.2<0;1,0>:f // IEF OFF, rTEMP3.2 = u_left and (1) r14.1:ud r2.3:uw 0xFFF8:uw asr (1) r14.1:ud r14.1:ud 3:d mov (1) r14.1:f r14.1:ud // Gen7 AVS WA, if (int)(u_left*width + 5.0/256) > (int)(u_left*width) mul (1) r14.0:f r14.2:f r14.1:f // rTEMP3.0 = u_left*width add (1) r14.2:f r14.0:f 0.01953125:f // rTEMP3.2 = u_left*width + 5.0/256 add (1) r14.3:f r14.0:f 0.99609375:f // rTEMP3.3 = u_left*width + 255.0/256 //Check if the values are < 0 and account for (int) cast of negative numbers //(int)(u_left*width) cmp.l.f0.0 (1) null<1>:f r14.0:f 0.00000000:f mov (1) r14.0:d r14.0:f (f0.0)add (1) r14.0:d r14.0<0;1,0>:d -1:d //(int)(u_left*width + 5.0/256) cmp.l.f0.0 (1) null<1>:f r14.2:f 0.00000000:f mov (1) r14.2:d r14.2:f (f0.0)add (1) r14.2:d r14.2<0;1,0>:d -1:d //(int)(u_left*width + 255.0/256) cmp.l.f0.0 (1) null<1>:f r14.3:f 0.00000000:f mov (1) r14.3:d r14.3:f (f0.0)add (1) r14.3:d r14.3<0;1,0>:d -1:d mov (1) f0.0:uw 0:uw // clear flag //if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) cmp.g.f1.0 (1) null<1>:d r14.2:d r14.0:d // modified_u_coord = u_coord – 5.0/(256*width); //floating point (f1.0) add (1) r17.2:f r17.2<0;1,0>:f -r2.3:f //else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) (-f1.0) cmp.e.f0.0 (1) null<1>:d r14.3:d r14.0:d // modified_u_coord = u_coord + 1.0/(256*width); //floating point (f0.0) add (1) r17.2:f r17.2<0;1,0>:f r2.2:f GEN7_PL3_AVS_WA_DONE_L0_2_: mov (1) f0.0:uw r14.8:uw // restore f0.0 send (1) uwBUFFER_2(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order mov (1) r17.2:f r14.5:f // restore pixel 0 U for chroma, No AVS WA for chroma add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EB801:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_2(4)<1> r16 0x2 a0.0:ud // Returns U data in 4 GRFs in scrambled order add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EBC02:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_2(8)<1> r16 0x2 a0.0:ud // Returns V data in 4 GRFs in scrambled order SKIP_AVS_LOAD_L0_2_: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a000066400000000000000000000467741231401140700251550ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 45 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL3_AVS_Buf_3.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL3 data into Buffer 3 // FileName : PL3_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL3 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //Check if layer is to be skipped // f0.1 pre-computed in Set_Layer_0 (-f0.1) jmpi (1) SKIP_AVS_LOAD_L0_3_ //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EB400:ud //msg desc mov (1) r16.2:ud 0x0000D000:ud // Enable Red channel // set the vertical block number add (1) r25.1<1>:ud r7.12:uw 3:ud mov (8) r17.0:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs // Gen7 AVS WA Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces // if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) // { // modified_u_coord = u_coord – 5.0/(256*width); //floating point // } // else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) // { // modified_u_coord = u_coord + 1.0/(256*width); //floating point // } // else{ // modified_u_coord = u_coord; // } // Where u_left = u – 2*du + 3*ddu for IEF On // And u_left = u for IEF Off case // // check whether Gen7 AVS WA is enabled, mov (1) r14.8:uw f0.0:uw // save f0.0 mov (1) r14.5:f r17.2<0;1,0>:f // save pixel 0 U for chroma and.nz.f0.0 (1) null<1>:uw r2.3:uw 0x2:uw (-f0.0)jmpi (1) GEN7_PL3_AVS_WA_DONE_L0_3_ // Gen7 AVS WA, check if IEF is ON for choosing Gen7 AVS WA formula and.nz.f0.0 (8) null<1>:uw r2.3<0;1,0>:uw 0x4:uw (f0.0)mov (8) acc0.0:f r17.2<0;1,0>:f (f0.0)mac (8) acc0.0:f r17.4<0;1,0>:f -2.0:f (f0.0)mac (8) acc0.0:f r17.6<0;1,0>:f 3.0:f (f0.0)mov (1) r14.2:f acc0:f // IEF ON, rTEMP3.2 = u_left (-f0.0)mov (1) r14.2:f r17.2<0;1,0>:f // IEF OFF, rTEMP3.2 = u_left and (1) r14.1:ud r2.3:uw 0xFFF8:uw asr (1) r14.1:ud r14.1:ud 3:d mov (1) r14.1:f r14.1:ud // Gen7 AVS WA, if (int)(u_left*width + 5.0/256) > (int)(u_left*width) mul (1) r14.0:f r14.2:f r14.1:f // rTEMP3.0 = u_left*width add (1) r14.2:f r14.0:f 0.01953125:f // rTEMP3.2 = u_left*width + 5.0/256 add (1) r14.3:f r14.0:f 0.99609375:f // rTEMP3.3 = u_left*width + 255.0/256 //Check if the values are < 0 and account for (int) cast of negative numbers //(int)(u_left*width) cmp.l.f0.0 (1) null<1>:f r14.0:f 0.00000000:f mov (1) r14.0:d r14.0:f (f0.0)add (1) r14.0:d r14.0<0;1,0>:d -1:d //(int)(u_left*width + 5.0/256) cmp.l.f0.0 (1) null<1>:f r14.2:f 0.00000000:f mov (1) r14.2:d r14.2:f (f0.0)add (1) r14.2:d r14.2<0;1,0>:d -1:d //(int)(u_left*width + 255.0/256) cmp.l.f0.0 (1) null<1>:f r14.3:f 0.00000000:f mov (1) r14.3:d r14.3:f (f0.0)add (1) r14.3:d r14.3<0;1,0>:d -1:d mov (1) f0.0:uw 0:uw // clear flag //if (((int)(u_left*width + 5.0/256) > (int)(u_left*width)) cmp.g.f1.0 (1) null<1>:d r14.2:d r14.0:d // modified_u_coord = u_coord – 5.0/(256*width); //floating point (f1.0) add (1) r17.2:f r17.2<0;1,0>:f -r2.3:f //else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) (-f1.0) cmp.e.f0.0 (1) null<1>:d r14.3:d r14.0:d // modified_u_coord = u_coord + 1.0/(256*width); //floating point (f0.0) add (1) r17.2:f r17.2<0;1,0>:f r2.2:f GEN7_PL3_AVS_WA_DONE_L0_3_: mov (1) f0.0:uw r14.8:uw // restore f0.0 send (1) uwBUFFER_3(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order mov (1) r17.2:f r14.5:f // restore pixel 0 U for chroma, No AVS WA for chroma add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EB801:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_3(4)<1> r16 0x2 a0.0:ud // Returns U data in 4 GRFs in scrambled order add (1) a0.0:ud r23.5<0;1,0>:ud 0x44EBC02:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_3(8)<1> r16 0x2 a0.0:ud // Returns V data in 4 GRFs in scrambled order SKIP_AVS_LOAD_L0_3_: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/PL3_DNDI_422CP.g4a000066400000000000000000000574101231401140700250230ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 120 // Total instruction count // 1 // Total kernel count .kernel PL3_DNDI_422CP .code // FileName: DNDI_PL_Core.asm // Author: Tatiya, Rupesh // FileName: DNDI_Core.asm // Author: Vivek Kumar // Description: Tasks for DN+DI case (16x4 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x4BE8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(9,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DI_STMM_Save.asm // Author: Vivek Kumar // Description: Saves DI STMM Data to statistics surface in case of DI enabled (for 16x4 block) // Write STMM to memory mov (8) mudMSGHDR_STMM(0)<1> r0.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udDNDI_RESP(8,0) // Move STMM to MRF shr (1) mudMSGHDR_STMM(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin / 2 mov (1) mudMSGHDR_STMM(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_STMM(0,2)<1> 0x30007:ud { NoDDChk } // block width and height (8x4) send (8) null<1>:d r20 0x5 0x40A8021:ud // FileName: DN_Hist_Save.asm // Author: Vivek Kumar // Description: Saves DN history data to statistics surface // Write denoise history to memory mov (8) r27<1>:ud r0.0<8;8,1>:ud // message header mov (1) mudMSGHDR_HIST(1)<1> udDNDI_RESP(9,0)<0;1,0> // Move denoise history to MRF (4x1) shr (2) r27.0<1>:ud r7.0<2;2,1>:w 2:w // X,Y origin / 4 add (1) r27.0<1>:ud r27.0<0;1,0>:ud r1.12<0;1,0>:uw { NoDDClr } // Add pitch to X origin mov (1) r27.2<1>:ud 0x3:ud { NoDDChk } // block width and height mov (8) mudMSGHDR_HIST(0)<1> r27.0<8;8,1>:ud send (8) null<1>:d r22 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x20007:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | MCNT | FCNT | TCNT | X | X | X | X | //---------------------------------------------------- //| DcTpT | SVCM | DcBpT | DcTpB | //---------------------------------------------------- //| SHCM | STAD | DcTcB | DcBpB | //---------------------------------------------------- mov (1) mudMSGHDR_ENC_STATS(1,0)<1> udDNDI_RESP(9,1)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,3)<2> udDNDI_RESP(9,3)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,2)<2> udDNDI_RESP(9,5)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DN_Load_UV_IMC3_16x4.asm // Author: Vivek Kumar // Description: Read UV for 16x4 block through DATAPORT // FileName: UVCopy_Load_16x4.asm // Author: Vivek Kumar // Description: Read UV for 16x4 block through DATAPORT add (2) r27.0<1>:d r7.0<2;2,1>:w r4.4<2;2,1>:w // Source Y Block origin asr (2) r27.0<1>:d r27.0<2;2,1>:d 1:w { NoDDClr } // U/V block origin should be half of Y's mov (1) r27.2<1>:ud 0x10007:ud { NoDDChk } // U/V block width and height (8x2) mov (8) r36<1>:ud r27.0<8;8,1>:ud mov (8) r38<1>:ud r27.0<8;8,1>:ud send (8) udDNDI_UV_RESP(0)<1> r36 0x4 0x2190001:ud send (8) udDNDI_UV_RESP(1)<1> r38 0x4 0x2190002:ud // FileName: DN_Save_Y_16x4.asm // Author: Vivek Kumar // Description: Save one 16x4 blocks of Y channel of DN output for reference // check top/bottom field first cmp.e.f0.0 (1) null<1>:w r1.28<0;1,0>:ub 1:w mov (8) mudMSGHDR_DN_OUT(0)<1> r0<8;8,1>:ud // message header mov (2) mdMSGHDR_DN_OUT(0,0)<1> r7.0<2;2,1>:w { NoDDClr } // X origin * 2 (422 output) mov (1) mudMSGHDR_DN_OUT(0,2)<1> 0x3000F:ud { NoDDChk } // block width and height (32x8) (f0.0) jmpi (1) TOP_FIELD_FIRST BOTTOM_FIELD_FIRST: mov (4) mudMSGHDR_DN_OUT(1,0)<1> udDNDI_RESP(10,0)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(1,4)<1> udDNDI_RESP(4,4)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) mov (4) mudMSGHDR_DN_OUT(2,0)<1> udDNDI_RESP(10,4)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(2,4)<1> udDNDI_RESP(5,4)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) jmpi (1) SAVE_DN_CURR TOP_FIELD_FIRST: mov (4) mudMSGHDR_DN_OUT(1,0)<1> udDNDI_RESP(4,0)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(1,4)<1> udDNDI_RESP(10,0)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) mov (4) mudMSGHDR_DN_OUT(2,0)<1> udDNDI_RESP(5,0)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(2,4)<1> udDNDI_RESP(10,4)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) SAVE_DN_CURR: //send out data through data port send (8) null<1>:d r31.0 0x5 0x60A8018:ud // FileName: DI_Save_422CP_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in 422 format to Color Pipe (IECP) .declare mubMSGHDR_DI_OUT1_1 Base=r18.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT1_2 Base=r21.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT2_1 Base=r24.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT2_2 Base=r27.0 ElementSize=1 Type=ub mov (8) r27.0<1>:ud r0.0<8;8,1>:ud shl (1) r27.0<1>:ud r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be doubled mov (1) r27.1<1>:ud r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) r27.2<1>:ud 0x3000F:ud { NoDDClr, NoDDChk } // Block width and height (16x8) //M0.3 - 0 - CP Enable, 1 - Area of Interest, 3:2 Message Format(TBD), 4:3 - Ignored, 31:5 CP state pointer //Compose area-of-interest bit + color pipe state pointer or (1) r27.3<1>:ud r2.4<0;1,0>:ud r7.26<0;1,0>:b { NoDDChk } //prepare the message headers mov (8) r18.0<1>:ud r27<8;8,1>:ud mov (8) r24.0<1>:ud r27<8;8,1>:ud // Pack 2nd field Y; First 8x4 block mov (8) mubMSGHDR_DI_OUT1_1(1)<2> ubDNDI_RESP(0,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(1,16)<2> ubDNDI_RESP(0,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(2)<2> ubDNDI_RESP(0,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(2,16)<2> ubDNDI_RESP(0,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 2nd field U, V; First 8x4 block mov (4) mubMSGHDR_DI_OUT1_1(1,1)<4> ubDNDI_RESP(2,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,17)<4> ubDNDI_RESP(2,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,3)<4> ubDNDI_RESP(2,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,19)<4> ubDNDI_RESP(2,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,1)<4> ubDNDI_RESP(2,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,17)<4> ubDNDI_RESP(2,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,3)<4> ubDNDI_RESP(2,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,19)<4> ubDNDI_RESP(2,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Pack 2nd field Y; Second 8x4 block mov (8) r21.0<1>:ud r18.0<8;8,1>:ud add (1) r21.0<1>:ud r21.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DI_OUT1_2(1)<2> ubDNDI_RESP(0,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(1,16)<2> ubDNDI_RESP(0,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(2)<2> ubDNDI_RESP(0,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(2,16)<2> ubDNDI_RESP(0,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 2nd field U, V; Second 8x4 block mov (4) mubMSGHDR_DI_OUT1_2(1,1)<4> ubDNDI_RESP(2,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,17)<4> ubDNDI_RESP(2,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,3)<4> ubDNDI_RESP(2,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,19)<4> ubDNDI_RESP(2,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,1)<4> ubDNDI_RESP(2,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,17)<4> ubDNDI_RESP(2,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,3)<4> ubDNDI_RESP(2,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,19)<4> ubDNDI_RESP(2,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization send (8) null<1>:d r18.0 0x5 0x60A801B:ud send (8) null<1>:d r21.0 0x5 0x60A801B:ud // Pack 1st field Y; 1st 8x4 block mov (8) mubMSGHDR_DI_OUT2_1(1)<2> ubDNDI_RESP(4,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(1,16)<2> ubDNDI_RESP(4,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(2)<2> ubDNDI_RESP(4,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(2,16)<2> ubDNDI_RESP(4,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 1st field U,V; 1st 8x4 block mov (4) mubMSGHDR_DI_OUT2_1(1,1)<4> ubDNDI_RESP(6,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,17)<4> ubDNDI_RESP(6,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,3)<4> ubDNDI_RESP(6,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,19)<4> ubDNDI_RESP(6,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,1)<4> ubDNDI_RESP(6,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,17)<4> ubDNDI_RESP(6,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,3)<4> ubDNDI_RESP(6,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,19)<4> ubDNDI_RESP(6,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Pack 1st field Y; 2nd 8x4 block mov (8) r27.0<1>:ud r24.0<8;8,1>:ud add (1) r27.0<1>:ud r27.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DI_OUT2_2(1)<2> ubDNDI_RESP(4,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(1,16)<2> ubDNDI_RESP(4,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(2)<2> ubDNDI_RESP(4,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(2,16)<2> ubDNDI_RESP(4,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 1st field U, V; 2nd 8x4 block mov (4) mubMSGHDR_DI_OUT2_2(1,1)<4> ubDNDI_RESP(6,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,17)<4> ubDNDI_RESP(6,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,3)<4> ubDNDI_RESP(6,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,19)<4> ubDNDI_RESP(6,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,1)<4> ubDNDI_RESP(6,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,17)<4> ubDNDI_RESP(6,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,3)<4> ubDNDI_RESP(6,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,19)<4> ubDNDI_RESP(6,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization send (8) null<1>:d r24.0 0x5 0x60A801E:ud send (8) null<1>:d r27.0 0x5 0x60A801E:ud // FileName: DN_Save_UV_IMC3_16x4.asm // Author: Vivek Kumar // Description: Save UV for 16x4 block through DATAPORT // FileName: UVCopy_Save_16x4.asm // Author: Vivek Kumar // Description: Save UV for 16x4 block through DATAPORT //Reuse the header from Load component mov (4) mudMSGHDR_UCOPY(1)<1> udDNDI_UV_RESP(0)<4;4,1> mov (4) mudMSGHDR_VCOPY(1)<1> udDNDI_UV_RESP(1)<4;4,1> send (4) null<1>:d r36 0x5 0x40A8019:ud send (4) null<1>:d r38 0x5 0x40A801A:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PL3_DNDI_PA.g4a000066400000000000000000000446651231401140700246010ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 90 // Total instruction count // 1 // Total kernel count .kernel PL3_DNDI_PA .code // FileName: DNDI_PL_Core.asm // Author: Tatiya, Rupesh // FileName: DNDI_Core.asm // Author: Vivek Kumar // Description: Tasks for DN+DI case (16x4 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x4BE8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(9,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DI_STMM_Save.asm // Author: Vivek Kumar // Description: Saves DI STMM Data to statistics surface in case of DI enabled (for 16x4 block) // Write STMM to memory mov (8) mudMSGHDR_STMM(0)<1> r0.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udDNDI_RESP(8,0) // Move STMM to MRF shr (1) mudMSGHDR_STMM(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin / 2 mov (1) mudMSGHDR_STMM(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_STMM(0,2)<1> 0x30007:ud { NoDDChk } // block width and height (8x4) send (8) null<1>:d r20 0x5 0x40A8021:ud // FileName: DN_Hist_Save.asm // Author: Vivek Kumar // Description: Saves DN history data to statistics surface // Write denoise history to memory mov (8) r27<1>:ud r0.0<8;8,1>:ud // message header mov (1) mudMSGHDR_HIST(1)<1> udDNDI_RESP(9,0)<0;1,0> // Move denoise history to MRF (4x1) shr (2) r27.0<1>:ud r7.0<2;2,1>:w 2:w // X,Y origin / 4 add (1) r27.0<1>:ud r27.0<0;1,0>:ud r1.12<0;1,0>:uw { NoDDClr } // Add pitch to X origin mov (1) r27.2<1>:ud 0x3:ud { NoDDChk } // block width and height mov (8) mudMSGHDR_HIST(0)<1> r27.0<8;8,1>:ud send (8) null<1>:d r22 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x20007:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | MCNT | FCNT | TCNT | X | X | X | X | //---------------------------------------------------- //| DcTpT | SVCM | DcBpT | DcTpB | //---------------------------------------------------- //| SHCM | STAD | DcTcB | DcBpB | //---------------------------------------------------- mov (1) mudMSGHDR_ENC_STATS(1,0)<1> udDNDI_RESP(9,1)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,3)<2> udDNDI_RESP(9,3)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,2)<2> udDNDI_RESP(9,5)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DN_Load_UV_IMC3_16x4.asm // Author: Vivek Kumar // Description: Read UV for 16x4 block through DATAPORT // FileName: UVCopy_Load_16x4.asm // Author: Vivek Kumar // Description: Read UV for 16x4 block through DATAPORT add (2) r27.0<1>:d r7.0<2;2,1>:w r4.4<2;2,1>:w // Source Y Block origin asr (2) r27.0<1>:d r27.0<2;2,1>:d 1:w { NoDDClr } // U/V block origin should be half of Y's mov (1) r27.2<1>:ud 0x10007:ud { NoDDChk } // U/V block width and height (8x2) mov (8) r36<1>:ud r27.0<8;8,1>:ud mov (8) r38<1>:ud r27.0<8;8,1>:ud send (8) udDNDI_UV_RESP(0)<1> r36 0x4 0x2190001:ud send (8) udDNDI_UV_RESP(1)<1> r38 0x4 0x2190002:ud // FileName: DN_Save_Y_16x4.asm // Author: Vivek Kumar // Description: Save one 16x4 blocks of Y channel of DN output for reference // check top/bottom field first cmp.e.f0.0 (1) null<1>:w r1.28<0;1,0>:ub 1:w mov (8) mudMSGHDR_DN_OUT(0)<1> r0<8;8,1>:ud // message header mov (2) mdMSGHDR_DN_OUT(0,0)<1> r7.0<2;2,1>:w { NoDDClr } // X origin * 2 (422 output) mov (1) mudMSGHDR_DN_OUT(0,2)<1> 0x3000F:ud { NoDDChk } // block width and height (32x8) (f0.0) jmpi (1) TOP_FIELD_FIRST BOTTOM_FIELD_FIRST: mov (4) mudMSGHDR_DN_OUT(1,0)<1> udDNDI_RESP(10,0)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(1,4)<1> udDNDI_RESP(4,4)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) mov (4) mudMSGHDR_DN_OUT(2,0)<1> udDNDI_RESP(10,4)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(2,4)<1> udDNDI_RESP(5,4)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) jmpi (1) SAVE_DN_CURR TOP_FIELD_FIRST: mov (4) mudMSGHDR_DN_OUT(1,0)<1> udDNDI_RESP(4,0)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(1,4)<1> udDNDI_RESP(10,0)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) mov (4) mudMSGHDR_DN_OUT(2,0)<1> udDNDI_RESP(5,0)<4;4,1> { NoDDClr } // 2nd field luma from current frame (line 0,2) mov (4) mudMSGHDR_DN_OUT(2,4)<1> udDNDI_RESP(10,4)<4;4,1> { NoDDChk } // 1st field luma from current frame (line 1,3) SAVE_DN_CURR: //send out data through data port send (8) null<1>:d r31.0 0x5 0x60A8018:ud // FileName: DI_Save_PA_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in Packed format add (4) a0.4<1>:uw r2.28<4;4,1>:ub 608:w // Initial Y,U,V offset in YUV422 block; it starts at m20 mov (8) r27.0<1>:ud r0.0<8;8,1>:ud shl (1) r27.0<1>:d r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be doubled mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) r27.2<1>:ud 0x3001F:ud { NoDDChk } // Block width and height (32x8) //prepare the message headers mov (8) r18.0<1>:ud r27<8;8,1>:ud mov (8) r23.0<1>:ud r27<8;8,1>:ud // Pack 2nd field Y mov (16) r[a0.4, 0]<2> ubDNDI_RESP(0,0) { NoDDClr } mov (16) r[a0.4, 32]<2> ubDNDI_RESP(0,16) { NoDDClr } mov (16) r[a0.4, 64]<2> ubDNDI_RESP(0,32) { NoDDClr } mov (16) r[a0.4, 96]<2> ubDNDI_RESP(0,48) { NoDDClr } // Pack 2nd field U mov (8) r[a0.5, 0]<4> ubDNDI_RESP(2,1)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 32]<4> ubDNDI_RESP(2,17)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 64]<4> ubDNDI_RESP(2,33)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 96]<4> ubDNDI_RESP(2,49)<16;8,2> { NoDDClr, NoDDChk } //U pixels // Pack 2nd field V mov (8) r[a0.6, 0]<4> ubDNDI_RESP(2,0)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 32]<4> ubDNDI_RESP(2,16)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 64]<4> ubDNDI_RESP(2,32)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 96]<4> ubDNDI_RESP(2,48)<16;8,2> { NoDDChk } //Vpixels // Pack 1st field Y mov (16) r[a0.4, 160]<2> ubDNDI_RESP(4,0) { NoDDClr } mov (16) r[a0.4, 192]<2> ubDNDI_RESP(4,16) { NoDDClr } mov (16) r[a0.4, 224]<2> ubDNDI_RESP(4,32) { NoDDClr } mov (16) r[a0.4, 256]<2> ubDNDI_RESP(4,48) { NoDDClr } // Pack 1st field U mov (8) r[a0.5, 160]<4> ubDNDI_RESP(6,1)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 192]<4> ubDNDI_RESP(6,17)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 224]<4> ubDNDI_RESP(6,33)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 256]<4> ubDNDI_RESP(6,49)<16;8,2> { NoDDClr, NoDDChk } //U pixels // Pack 1st field V mov (8) r[a0.6, 160]<4> ubDNDI_RESP(6,0)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 192]<4> ubDNDI_RESP(6,16)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 224]<4> ubDNDI_RESP(6,32)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 256]<4> ubDNDI_RESP(6,48)<16;8,2> { NoDDChk } //Vpixels //save the previous frame send (8) null<1>:d r18.0 0x5 0xA0A801B:ud //save the current frame send (8) null<1>:d r23.0 0x5 0xA0A801E:ud // FileName: DN_Save_UV_IMC3_16x4.asm // Author: Vivek Kumar // Description: Save UV for 16x4 block through DATAPORT // FileName: UVCopy_Save_16x4.asm // Author: Vivek Kumar // Description: Save UV for 16x4 block through DATAPORT //Reuse the header from Load component mov (4) mudMSGHDR_UCOPY(1)<1> udDNDI_UV_RESP(0)<4;4,1> mov (4) mudMSGHDR_VCOPY(1)<1> udDNDI_UV_RESP(1)<4;4,1> send (4) null<1>:d r36 0x5 0x40A8019:ud send (4) null<1>:d r38 0x5 0x40A801A:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PL3_DNUV_PL3.g4a000066400000000000000000003556041231401140700247330ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 1295 // Total instruction count // 1 // Total kernel count .kernel PL3_DNUV_PL3 .code //Module : DN_UV_Setup //Author : Tatiya, Rupesh //Description : Initial Set-up for DN_UV // Module name : ChromaDenoise.inc // Author : Tatiya, Rupesh // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Interface: //Static Parameters: //r1 //====================================================== //Interface for serpent mode Chroma Denoise, added by Le //====================================================== //r1 //noise history thresholds (low and high) //temporal difference thresholds (high and low) //noise history thresholds (low and high) //#define ubNoiseHistMaxHigh r1.22 //#define ubNoiseHistMaxLow r1.23 //#define ubNoiseHistDeltaHigh r1.24 //#define ubNoiseHistDeltaLow r1.25 //Gaussian thresholds //temporal difference thresholds (default) //r2 //history thresholds (default) //denoise factor (0-63) //====================== Binding table (Explicit To DNUV)========================================= //Used by DN_UV kernels //Pointer to Current Frame UV //r1-r6 //CURBE GRFs used as TEMP : Used for max computation and storing max temporarily. : r1-r6 .declare ubCURBE_TEMP Base=r1.0 ElementSize=1 Type=ub .declare uwCURBE_TEMP Base=r1.0 ElementSize=2 Type=uw .declare wCURBE_TEMP Base=r1.0 ElementSize=2 Type=w .declare fCURBE_TEMP Base=r1.0 ElementSize=4 Type=f .declare udCURBE_TEMP Base=r1.0 ElementSize=4 Type=ud .declare uwMAX_ABS_DIFF Base=r5.0 ElementSize=2 Type=uw //r1 //r3 //r4 //r7 //All of the following has to defined in Same GRF for optimal performance. //r8-24 //Previous Frame UV .declare udPREV_UV Base=r8.0 ElementSize=4 Type=ud .declare ubPREV_UV Base=r8.0 ElementSize=1 Type=ub //r25-48 //TEMP Space for any Usage. //========================================================================= //Definations and declarations for serpent mode Chroma Denoise, added by Le //========================================================================= .declare udGNE_UV Base=r24.0 ElementSize=4 Type=ud .declare fGNE_UV Base=r24.0 ElementSize=4 Type=f .declare ubGNE_UV Base=r24.0 ElementSize=1 Type=ub .declare udMSGHDR_BNE_SERP Base=r25.0 ElementSize=4 Type=ud .declare udMSGSRC_BNE_SERP Base=r26.0 ElementSize=4 Type=ud .declare ubDN_UV_Thresholds Base=r26.0 ElementSize=1 Type=ub .declare ubDN_UV_Thresholds_Temp Base=r27.0 ElementSize=1 Type=ub .declare udDN_UV_Thresholds Base=r26.0 ElementSize=4 Type=ud .declare udDN_UV_Thresholds_Temp Base=r27.0 ElementSize=4 Type=ud .declare fDN_UV_Thresholds Base=r26.0 ElementSize=4 Type=f .declare fDN_UV_Thresholds_Temp Base=r27.0 ElementSize=4 Type=f //==================================================================================== //TEMP23: To hold V data for PL3 surfaces .declare udCURR_V_TEMP Base=r25.0 ElementSize=4 Type=ud .declare ubCURR_V_TEMP Base=r25.0 ElementSize=1 Type=ub //GRFs to calculate Median: r25-r42 .declare ubMEDIAN_TEMP Base=r25.0 ElementSize=1 Type=ub //18 GRFs to hold difference : r25-r42 .declare wDIFF Base=r25.0 ElementSize=2 Type=w .declare uwDIFF Base=r25.0 ElementSize=2 Type=uw //Temporal Diff .declare wDIFF_TEMPORAL Base=r25.0 ElementSize=2 Type=w .declare ubDIFF_TEMPORAL Base=r25.0 ElementSize=1 Type=ub //4 GRFs to hold Sobel Value : r43-46 .declare wSOBEL_X Base=r43.0 ElementSize=2 Type=w .declare uwSOBEL Base=r43.0 ElementSize=2 Type=uw //2 GRFs to hold SOAD temporarily: r47-48 .declare uwSOAD Base=r47.0 ElementSize=2 Type=uw //Temp GRFs to hold extra YUYV pixels: r43-r48 .declare ubTEMP5 Base=r43.0 ElementSize=1 Type=ub //Temp GRFs in Median Calculation: r47-r48 .declare ubTEMP1 Base=r47.0 ElementSize=1 Type=ub .declare uwTEMP0 Base=r48.0 ElementSize=2 Type=uw .declare ubTEMP0 Base=r48.0 ElementSize=1 Type=ub //Temp Space to store Median : r49-50 .declare ubMEDIAN Base=r49.0 ElementSize=1 Type=ub //r49 //r50 //Message Source //r51 //DN_UV History Surface .declare udHIST_UV Base=r51.0 ElementSize=4 Type=ud .declare ubHIST_UV Base=r51.0 ElementSize=1 Type=ub //r52 - r91 //r52 //Current Frame UV .declare udCURR_UV Base=r52.0 ElementSize=4 Type=ud .declare ubCURR_UV Base=r52.0 ElementSize=1 Type=ub //r54 //CURBE COPY //r55 .declare uwSOAD_MIN_8x4 Base=r56.0 ElementSize=2 Type=uw //r61 //r62 //History Surface Temp Origin //r63 //Current Frame Y Temp Origin //BNE Surface Origin //r70 .declare uwDIFF_TEMPORAL_SUM4x4 Base=r70.0 ElementSize=2 Type=uw //4 GRFs //r74-91 : For Saving Dest UV (PL2/PL3) .declare ubMSGPAYLOAD_UV0 Base=r75.0 ElementSize=1 Type=ub .declare ubMSGPAYLOAD_U Base=r75.0 ElementSize=1 Type=ub .declare ubMSGPAYLOAD_UV1 Base=r84.0 ElementSize=1 Type=ub .declare ubMSGPAYLOAD_V Base=r84.0 ElementSize=1 Type=ub //r90 .declare uwDIFF_TEMPORAL_SUM4x4_FINAL Base=r90.0 ElementSize=2 Type=uw //2 GRFs //r92-127 //Current Frame Y //r92 .declare uwDIFF_TEMPORAL_SUM4x4_TEMP_0 Base=r92 ElementSize=2 Type=uw //r101 .declare uwDIFF_TEMPORAL_SUM4x4_TEMP_1 Base=r101 ElementSize=2 Type=uw //r110 .declare uwDIFF_TEMPORAL_SUM4x4_TEMP_2 Base=r110 ElementSize=2 Type=uw //r119 .declare uwDIFF_TEMPORAL_SUM4x4_TEMP_3 Base=r119 ElementSize=2 Type=uw .declare udCURR_Y0 Base=r93.0 ElementSize=4 Type=ud .declare ubCURR_Y0 Base=r93.0 ElementSize=1 Type=ub .declare udCURR_Y1 Base=r102.0 ElementSize=4 Type=ud .declare ubCURR_Y1 Base=r102.0 ElementSize=1 Type=ub .declare udCURR_Y2 Base=r111.0 ElementSize=4 Type=ud .declare ubCURR_Y2 Base=r111.0 ElementSize=1 Type=ub .declare udCURR_Y3 Base=r120.0 ElementSize=4 Type=ud .declare ubCURR_Y3 Base=r120.0 ElementSize=1 Type=ub //r92: To hold U data for PL3 surfaces .declare udCURR_U_TEMP Base=r92.0 ElementSize=4 Type=ud .declare ubCURR_U_TEMP Base=r92.0 ElementSize=1 Type=ub //r112: To hold U data for PL3 surfaces .declare udPREV_U_TEMP Base=r112.0 ElementSize=4 Type=ud .declare ubPREV_U_TEMP Base=r112.0 ElementSize=1 Type=ub //r120: To hold U data for PL3 surfaces .declare udPREV_V_TEMP Base=r120.0 ElementSize=4 Type=ud .declare ubPREV_V_TEMP Base=r120.0 ElementSize=1 Type=ub // Initialize message source with r0. mov (8) r50.0<1>:ud r0.0<8;8,1>:ud mov (8) r92.0<1>:ud r0.0<8;8,1>:ud mov (8) r101.0<1>:ud r0.0<8;8,1>:ud mov (8) r110.0<1>:ud r0.0<8;8,1>:ud mov (8) r119.0<1>:ud r0.0<8;8,1>:ud //Module Name : DN_UV_PL3_Load_Curr_Frame_UV //Author : Tatiya, Rupesh //Description : Loads Current Frame U/V data for PL3 input. //Module name : DN_UV_Load_Curr_Frame_UV //Author : Tatiya, Rupesh //Description : Loads Current Frame (UV only). // We need 4 extra rows (2 per field) and 2 extra pixel (1 each side) for both U and V each. // The processing size is 16x16 U and V each. So we need : U size - 18x20, V size - 18x20, UV size - 36x20, YUYV size - 72x20. //18x20 U/V block is partitioned as follows: // <------ 18 ------> // ------------------ // | 18x8 A1 | // | | // |----------------| // | 18x8 A2 | // | | // |----------------| // | 18x4 A2 | // |----------------| // // Cordinates: (x-1, y-2), (x-1, y+6), (x-1, y+14) //1. Load U data into starting at CURR_Y0 (r93-r122) //2. Load V data into TEMP space (r25-r44) //U/V surface origin: (ORIX/2, ORIY/2) add (2) r7.4<1>:w r7.0<2;2,1>:w r4.4<2;2,1>:w { AccWrEn } // Source Block origin shr (2) r7.4<1>:w acc0.4<2;2,1>:w 1:w //U Data mov (2) acc0.0<1>:d r7.4<2;2,1>:w //A1 add (1) r50.0<1>:d acc0.0<0;1,0>:d -1:d add (1) r50.1<1>:d acc0.1<0;1,0>:d -2:d mov (1) r50.2<1>:ud 0x70011:ud send (8) udCURR_U_TEMP(0)<1> r50 0x4 0x2890004:ud //A2 add (1) r50.1<1>:d acc0.1<0;1,0>:d 6:d send (8) udCURR_U_TEMP(8)<1> r50 0x4 0x2890004:ud //A3 add (1) r50.1<1>:d acc0.1<0;1,0>:d 14:d mov (1) r50.2<1>:ud 0x30011:ud send (8) udCURR_U_TEMP(16)<1> r50 0x4 0x2490004:ud //V Data //A1 add (1) r50.0<1>:d acc0.0<0;1,0>:d -1:d add (1) r50.1<1>:d acc0.1<0;1,0>:d -2:d mov (1) r50.2<1>:ud 0x70011:ud send (8) udCURR_V_TEMP(0)<1> r50 0x4 0x2890005:ud //A2 add (1) r50.1<1>:d acc0.1<0;1,0>:d 6:d send (8) udCURR_V_TEMP(8)<1> r50 0x4 0x2890005:ud //A3 add (1) r50.1<1>:d acc0.1<0;1,0>:d 14:d mov (1) r50.2<1>:ud 0x30011:ud send (8) udCURR_V_TEMP(16)<1> r50 0x4 0x2490005:ud //History Origin, Current Y origin and BNE surface origin - all are in inline GRF. Use , . -rT. //Calculate Origin For History Surface: (ORIX/4, ORIY/8) mov (16) acc0.0<1>:w r7.0<0;2,1>:w { AccWrEn } shr (1) r7.2<1>:w acc0.2<0;1,0>:w 2:w shr (1) r7.3<1>:w acc0.3<0;1,0>:w 3:w //Calculate Origin For BNE Surface: (ORIX/8, ORIY/16) shr (1) r7.6<1>:w acc0.6<0;1,0>:w 3:w shr (1) r7.7<1>:w acc0.7<0;1,0>:w 4:w //Module Name : DN_UV_PL3_Load_Prev_Frame_UV.asm //Author : Tatiya, Rupesh //Description : Loads Pevious Frame UV data for PL3 input. //Module Name : DN_UV_Load_Prev_Frame_UV //Author : Tatiya, Rupesh //Description : Loads Prev Frame (UV only). U size - 16x16, V size - 16x16, UV size - 32x16, YUYV size - 64x16. //1. Load U in bottom half of UV space for prev frame (r17-r24) //2. Load V in bottom quarter of Y space for curr frame (r120-r127) mov (2) r50.0<1>:d r7.4<2;2,1>:w { AccWrEn } // Source lock origin mov (1) r50.2<1>:ud 0xF000F:ud // U/V block width and height (16x16) mov (8) r49.0<1>:ud r50<8;8,1>:ud send (8) udPREV_U_TEMP(0)<1> r50 0x4 0x2890001:ud //U data send (8) udPREV_V_TEMP(0)<1> r49 0x4 0x2890002:ud //V data //TODO - See if History loading can be combined with Prev Frame Load. - rT //Module name : DN_UV_Load_Hist_UV //Author : Tatiya, Rupesh //Description : Load DN History for UV denoise. 4x4 for each U & V. mov (2) r50.0<1>:d r7.2<2;2,1>:w mov (1) r50.2<1>:ud 0x30007:ud send (8) udHIST_UV(0)<1> r50 0x4 0x2190022:ud //File Name : DN_UV_PL3_Interleave_Curr_Frame_UV.asm //Author : Tatiya, Rupesh //Description : Interleave separately loaded U and V for PL3 format. // This is needed because Noise Detection and Noise Reduction works on interleaved UV data. //1. U data: Starting at CURR_Y0 (r93-r122) //2. V data: TEMP space (r25-r44) //In one GRF, we need 10 U (1+8+1) bytes, but there's no SIMD10. So use SIMD16 and discard last 6 bytes. //Move U data mov (16) ubCURR_UV(0,0)<2> ubCURR_U_TEMP(0,0)<16;16,1> mov (16) ubCURR_UV(20,0)<2> ubCURR_U_TEMP(0,8)<16;16,1> mov (16) ubCURR_UV(1,0)<2> ubCURR_U_TEMP(1,0)<16;16,1> mov (16) ubCURR_UV(21,0)<2> ubCURR_U_TEMP(1,8)<16;16,1> mov (16) ubCURR_UV(2,0)<2> ubCURR_U_TEMP(2,0)<16;16,1> mov (16) ubCURR_UV(22,0)<2> ubCURR_U_TEMP(2,8)<16;16,1> mov (16) ubCURR_UV(3,0)<2> ubCURR_U_TEMP(3,0)<16;16,1> mov (16) ubCURR_UV(23,0)<2> ubCURR_U_TEMP(3,8)<16;16,1> mov (16) ubCURR_UV(4,0)<2> ubCURR_U_TEMP(4,0)<16;16,1> mov (16) ubCURR_UV(24,0)<2> ubCURR_U_TEMP(4,8)<16;16,1> mov (16) ubCURR_UV(5,0)<2> ubCURR_U_TEMP(5,0)<16;16,1> mov (16) ubCURR_UV(25,0)<2> ubCURR_U_TEMP(5,8)<16;16,1> mov (16) ubCURR_UV(6,0)<2> ubCURR_U_TEMP(6,0)<16;16,1> mov (16) ubCURR_UV(26,0)<2> ubCURR_U_TEMP(6,8)<16;16,1> mov (16) ubCURR_UV(7,0)<2> ubCURR_U_TEMP(7,0)<16;16,1> mov (16) ubCURR_UV(27,0)<2> ubCURR_U_TEMP(7,8)<16;16,1> mov (16) ubCURR_UV(8,0)<2> ubCURR_U_TEMP(8,0)<16;16,1> mov (16) ubCURR_UV(28,0)<2> ubCURR_U_TEMP(8,8)<16;16,1> mov (16) ubCURR_UV(9,0)<2> ubCURR_U_TEMP(9,0)<16;16,1> mov (16) ubCURR_UV(29,0)<2> ubCURR_U_TEMP(9,8)<16;16,1> mov (16) ubCURR_UV(10,0)<2> ubCURR_U_TEMP(10,0)<16;16,1> mov (16) ubCURR_UV(30,0)<2> ubCURR_U_TEMP(10,8)<16;16,1> mov (16) ubCURR_UV(11,0)<2> ubCURR_U_TEMP(11,0)<16;16,1> mov (16) ubCURR_UV(31,0)<2> ubCURR_U_TEMP(11,8)<16;16,1> mov (16) ubCURR_UV(12,0)<2> ubCURR_U_TEMP(12,0)<16;16,1> mov (16) ubCURR_UV(32,0)<2> ubCURR_U_TEMP(12,8)<16;16,1> mov (16) ubCURR_UV(13,0)<2> ubCURR_U_TEMP(13,0)<16;16,1> mov (16) ubCURR_UV(33,0)<2> ubCURR_U_TEMP(13,8)<16;16,1> mov (16) ubCURR_UV(14,0)<2> ubCURR_U_TEMP(14,0)<16;16,1> mov (16) ubCURR_UV(34,0)<2> ubCURR_U_TEMP(14,8)<16;16,1> mov (16) ubCURR_UV(15,0)<2> ubCURR_U_TEMP(15,0)<16;16,1> mov (16) ubCURR_UV(35,0)<2> ubCURR_U_TEMP(15,8)<16;16,1> mov (16) ubCURR_UV(16,0)<2> ubCURR_U_TEMP(16,0)<16;16,1> mov (16) ubCURR_UV(36,0)<2> ubCURR_U_TEMP(16,8)<16;16,1> mov (16) ubCURR_UV(17,0)<2> ubCURR_U_TEMP(17,0)<16;16,1> mov (16) ubCURR_UV(37,0)<2> ubCURR_U_TEMP(17,8)<16;16,1> mov (16) ubCURR_UV(18,0)<2> ubCURR_U_TEMP(18,0)<16;16,1> mov (16) ubCURR_UV(38,0)<2> ubCURR_U_TEMP(18,8)<16;16,1> mov (16) ubCURR_UV(19,0)<2> ubCURR_U_TEMP(19,0)<16;16,1> mov (16) ubCURR_UV(39,0)<2> ubCURR_U_TEMP(19,8)<16;16,1> //Move V data mov (16) ubCURR_UV(0,1)<2> ubCURR_V_TEMP(0,0)<16;16,1> mov (16) ubCURR_UV(20,1)<2> ubCURR_V_TEMP(0,8)<16;16,1> mov (16) ubCURR_UV(1,1)<2> ubCURR_V_TEMP(1,0)<16;16,1> mov (16) ubCURR_UV(21,1)<2> ubCURR_V_TEMP(1,8)<16;16,1> mov (16) ubCURR_UV(2,1)<2> ubCURR_V_TEMP(2,0)<16;16,1> mov (16) ubCURR_UV(22,1)<2> ubCURR_V_TEMP(2,8)<16;16,1> mov (16) ubCURR_UV(3,1)<2> ubCURR_V_TEMP(3,0)<16;16,1> mov (16) ubCURR_UV(23,1)<2> ubCURR_V_TEMP(3,8)<16;16,1> mov (16) ubCURR_UV(4,1)<2> ubCURR_V_TEMP(4,0)<16;16,1> mov (16) ubCURR_UV(24,1)<2> ubCURR_V_TEMP(4,8)<16;16,1> mov (16) ubCURR_UV(5,1)<2> ubCURR_V_TEMP(5,0)<16;16,1> mov (16) ubCURR_UV(25,1)<2> ubCURR_V_TEMP(5,8)<16;16,1> mov (16) ubCURR_UV(6,1)<2> ubCURR_V_TEMP(6,0)<16;16,1> mov (16) ubCURR_UV(26,1)<2> ubCURR_V_TEMP(6,8)<16;16,1> mov (16) ubCURR_UV(7,1)<2> ubCURR_V_TEMP(7,0)<16;16,1> mov (16) ubCURR_UV(27,1)<2> ubCURR_V_TEMP(7,8)<16;16,1> mov (16) ubCURR_UV(8,1)<2> ubCURR_V_TEMP(8,0)<16;16,1> mov (16) ubCURR_UV(28,1)<2> ubCURR_V_TEMP(8,8)<16;16,1> mov (16) ubCURR_UV(9,1)<2> ubCURR_V_TEMP(9,0)<16;16,1> mov (16) ubCURR_UV(29,1)<2> ubCURR_V_TEMP(9,8)<16;16,1> mov (16) ubCURR_UV(10,1)<2> ubCURR_V_TEMP(10,0)<16;16,1> mov (16) ubCURR_UV(30,1)<2> ubCURR_V_TEMP(10,8)<16;16,1> mov (16) ubCURR_UV(11,1)<2> ubCURR_V_TEMP(11,0)<16;16,1> mov (16) ubCURR_UV(31,1)<2> ubCURR_V_TEMP(11,8)<16;16,1> mov (16) ubCURR_UV(12,1)<2> ubCURR_V_TEMP(12,0)<16;16,1> mov (16) ubCURR_UV(32,1)<2> ubCURR_V_TEMP(12,8)<16;16,1> mov (16) ubCURR_UV(13,1)<2> ubCURR_V_TEMP(13,0)<16;16,1> mov (16) ubCURR_UV(33,1)<2> ubCURR_V_TEMP(13,8)<16;16,1> mov (16) ubCURR_UV(14,1)<2> ubCURR_V_TEMP(14,0)<16;16,1> mov (16) ubCURR_UV(34,1)<2> ubCURR_V_TEMP(14,8)<16;16,1> mov (16) ubCURR_UV(15,1)<2> ubCURR_V_TEMP(15,0)<16;16,1> mov (16) ubCURR_UV(35,1)<2> ubCURR_V_TEMP(15,8)<16;16,1> mov (16) ubCURR_UV(16,1)<2> ubCURR_V_TEMP(16,0)<16;16,1> mov (16) ubCURR_UV(36,1)<2> ubCURR_V_TEMP(16,8)<16;16,1> mov (16) ubCURR_UV(17,1)<2> ubCURR_V_TEMP(17,0)<16;16,1> mov (16) ubCURR_UV(37,1)<2> ubCURR_V_TEMP(17,8)<16;16,1> mov (16) ubCURR_UV(18,1)<2> ubCURR_V_TEMP(18,0)<16;16,1> mov (16) ubCURR_UV(38,1)<2> ubCURR_V_TEMP(18,8)<16;16,1> mov (16) ubCURR_UV(19,1)<2> ubCURR_V_TEMP(19,0)<16;16,1> mov (16) ubCURR_UV(39,1)<2> ubCURR_V_TEMP(19,8)<16;16,1> //File Name : DN_UV_PL3_Interleave_Prev_Frame_UV.asm //Author : Tatiya, Rupesh //Description : Interleave separately loaded U and V for PL3 format. // This is needed because Noise Detection and Noise Reduction works on interleaved UV data. //1.U Data: bottom half of UV space for prev frame (r17-r24) //2.V Data: bottom quarter of Y space for curr frame (r120-r127) mov (16) ubPREV_UV(0,0)<2> ubPREV_U_TEMP(0,0)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(8,0)<2> ubPREV_U_TEMP(0,8)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(1,0)<2> ubPREV_U_TEMP(1,0)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(9,0)<2> ubPREV_U_TEMP(1,8)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(2,0)<2> ubPREV_U_TEMP(2,0)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(10,0)<2> ubPREV_U_TEMP(2,8)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(3,0)<2> ubPREV_U_TEMP(3,0)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(11,0)<2> ubPREV_U_TEMP(3,8)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(4,0)<2> ubPREV_U_TEMP(4,0)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(12,0)<2> ubPREV_U_TEMP(4,8)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(5,0)<2> ubPREV_U_TEMP(5,0)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(13,0)<2> ubPREV_U_TEMP(5,8)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(6,0)<2> ubPREV_U_TEMP(6,0)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(14,0)<2> ubPREV_U_TEMP(6,8)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(7,0)<2> ubPREV_U_TEMP(7,0)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(15,0)<2> ubPREV_U_TEMP(7,8)<16;8,1> { NoDDClr } mov (16) ubPREV_UV(0,1)<2> ubPREV_V_TEMP(0,0)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(8,1)<2> ubPREV_V_TEMP(0,8)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(1,1)<2> ubPREV_V_TEMP(1,0)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(9,1)<2> ubPREV_V_TEMP(1,8)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(2,1)<2> ubPREV_V_TEMP(2,0)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(10,1)<2> ubPREV_V_TEMP(2,8)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(3,1)<2> ubPREV_V_TEMP(3,0)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(11,1)<2> ubPREV_V_TEMP(3,8)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(4,1)<2> ubPREV_V_TEMP(4,0)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(12,1)<2> ubPREV_V_TEMP(4,8)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(5,1)<2> ubPREV_V_TEMP(5,0)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(13,1)<2> ubPREV_V_TEMP(5,8)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(6,1)<2> ubPREV_V_TEMP(6,0)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(14,1)<2> ubPREV_V_TEMP(6,8)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(7,1)<2> ubPREV_V_TEMP(7,0)<16;8,1> { NoDDChk } mov (16) ubPREV_UV(15,1)<2> ubPREV_V_TEMP(7,8)<16;8,1> { NoDDChk } //Module Name : DN_UV_420_Load_Curr_Frame_Y //Author : Tatiya, Rupesh //Description : Load Curr Frame Y data for 420 Input //Module Name : DN_UV_Load_Curr_Frame_Y //Author : Tatiya, Rupesh //Description : Loads Y of Current frame. //For 16x16 U and 16x16 V for 420, we need to read 32x32 Y. mov (8) acc0.0<1>:ud r0.0<8;8,1>:ud mov (1) acc0.2<1>:ud 0xF000F:ud add (2) acc0.0<1>:ud r7.0<2;2,1>:w r4.4<2;2,1>:w mov (8) r92.0<1>:ud acc0.0<8;8,1>:ud mov (8) r101.0<1>:ud acc0.0<8;8,1>:ud mov (8) r110.0<1>:ud acc0.0<8;8,1>:ud mov (8) r119.0<1>:ud acc0.0<8;8,1>:ud add (1) r101.1<1>:d acc0.1<0;1,0>:d 16:d add (1) r110.0<1>:d acc0.0<0;1,0>:d 16:d add (2) r119.0<1>:d acc0.0<2;2,1>:d 16:d send (8) udCURR_Y0(0)<1> r92 0x4 0x2890003:ud send (8) udCURR_Y1(0)<1> r101 0x4 0x2890003:ud send (8) udCURR_Y2(0)<1> r110 0x4 0x2890003:ud send (8) udCURR_Y3(0)<1> r119 0x4 0x2890003:ud //Module Name : DN_UV_Noise_Detection_UV //Author : Tatiya, Rupesh //Description : Performs noise detection on 16x16 U and 16x16 V each. //Module Name : DN_UV_Move_CURBE_Inline_UV.asm //Author : Tatiya, Rupesh //Mov CURBE data to another space - so that it can be used as Temp Space --> r1 - r6 mov (4) r54.28<1>:ub r2.28<4;4,1>:ub //Dest. YUY2 offset mov (2) r54.5<1>:ud r4.0<4;2,2>:ud //Src YUY2 offset and Origin offset mov (4) r55.28<1>:ub r1.0<4;4,1>:ub mov (8) r61.20<1>:ub r1.4<8;8,1>:ub mov (4) r61.28<1>:ub r1.12<4;4,1>:ub //Move Inline Data to another space - so that it can be used as Temp Space --> r7 mov (4) r62.10<1>:w r7.0<4;4,1>:w mov (4) r63.10<1>:w r7.4<4;4,1>:w //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. mov (1) a0.0:uw 1664:uw mov (1) a0.1:uw 1816:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 1792:uw mov (1) a0.1:uw 1820:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 1920:uw mov (1) a0.1:uw 1848:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 2048:uw mov (1) a0.1:uw 1852:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. mov (1) a0.0:uw 2304:uw mov (1) a0.1:uw 1880:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 2432:uw mov (1) a0.1:uw 1884:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 2560:uw mov (1) a0.1:uw 1912:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module Name : DN_UV_Noise_Detection_Set_Top_Region_N //Author : Tatiya, Rupesh //Description : Sets sub-region region N from Top region. //TODO - remove one instruction here using arithmatic. -rT mov (1) a0.0:uw 2688:uw mov (1) a0.1:uw 1916:uw add (1) r7.7<1>:d ip:ud 32:d { NoCompact } jmpi (1) DN_UV_NOISE_DETECTION_UV { NoCompact } //Module : DN_UV_Noise_Reduction_UV //Author : Tatiya, Rupesh //Description : Performs Noise Reduction on 16x16 U and 16x16 V. //Tasks : 1. Update weight history // 2. Find if it block is motion block // 3. Compute Denoised Pixel. //History is 1+1 byte every 4x4 U and 4x4 V. cmp.l.f0.0 (16) null<1>:w ubHIST_UV(0,0)<16;16,1> r61.20<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w ubHIST_UV(0,0)<16;16,1> r61.22<0;2,1>:ub mov (16) uwCURBE_TEMP(0)<1> 0:w mov (16) uwCURBE_TEMP(1)<1> 0:w //Compute diff betn curr and prev. - First 16 lines // 8 lines here add (16) wDIFF_TEMPORAL(0)<1> ubCURR_UV(2,2)<16;16,1> -ubPREV_UV(0,0)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(1)<1> ubCURR_UV(3,2)<16;16,1> -ubPREV_UV(0,16)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(2)<1> ubCURR_UV(4,2)<16;16,1> -ubPREV_UV(0,32)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(3)<1> ubCURR_UV(5,2)<16;16,1> -ubPREV_UV(0,48)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(4)<1> ubCURR_UV(6,2)<16;16,1> -ubPREV_UV(0,64)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(5)<1> ubCURR_UV(7,2)<16;16,1> -ubPREV_UV(0,80)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(6)<1> ubCURR_UV(8,2)<16;16,1> -ubPREV_UV(0,96)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(7)<1> ubCURR_UV(9,2)<16;16,1> -ubPREV_UV(0,112)<16;16,1> //Diff UV interleaved //Update WT HIST (-f0.0) shr (16) uwCURBE_TEMP(0)<1> ubHIST_UV(0,0)<16;16,1> 1:w (f1.0) add (16) uwCURBE_TEMP(2)<1> ubHIST_UV(0,0)<16;16,1> r61.24<0;2,1>:ub (f0.0) mov (16) uwCURBE_TEMP(2)<1> r61.20<0;2,1>:ub (-f0.0.anyv) mov (16) uwCURBE_TEMP(2)<1> ubHIST_UV(0,0)<16;16,1> cmp.l.f0.0 (16) null<1>:w ubHIST_UV(0,16)<16;16,1> r61.20<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w ubHIST_UV(0,16)<16;16,1> r61.22<0;2,1>:ub //Compute diff betn curr and prev. - First 16 lines // 8 more lines here add (16) wDIFF_TEMPORAL(8)<1> ubCURR_UV(10,2)<16;16,1> -ubPREV_UV(0,128)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(9)<1> ubCURR_UV(11,2)<16;16,1> -ubPREV_UV(0,144)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(10)<1> ubCURR_UV(12,2)<16;16,1> -ubPREV_UV(0,160)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(11)<1> ubCURR_UV(13,2)<16;16,1> -ubPREV_UV(0,176)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(12)<1> ubCURR_UV(14,2)<16;16,1> -ubPREV_UV(0,192)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(13)<1> ubCURR_UV(15,2)<16;16,1> -ubPREV_UV(0,208)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(14)<1> ubCURR_UV(16,2)<16;16,1> -ubPREV_UV(0,224)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(15)<1> ubCURR_UV(17,2)<16;16,1> -ubPREV_UV(0,240)<16;16,1> //Diff UV interleaved (-f0.0) shr (16) uwCURBE_TEMP(1)<1> ubHIST_UV(0,16)<16;16,1> 1:w (f1.0) add (16) uwCURBE_TEMP(3)<1> ubHIST_UV(0,16)<16;16,1> r61.24<0;2,1>:ub (f0.0) mov (16) uwCURBE_TEMP(3)<1> r61.20<0;2,1>:ub (-f0.0.anyv) mov(16) uwCURBE_TEMP(3)<1> ubHIST_UV(0,16)<16;16,1> //16x16 to 16x4 - First 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(0)<16;16,1> (abs)wDIFF_TEMPORAL(1)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(2)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(0)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(3)<16;16,1> //16x16 to 16x4 - First 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(4)<16;16,1> (abs)wDIFF_TEMPORAL(5)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(6)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(1)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(7)<16;16,1> //16x16 to 16x4 - First 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(8)<16;16,1> (abs)wDIFF_TEMPORAL(9)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(10)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(2)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(11)<16;16,1> //16x16 to 16x4 - First 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(12)<16;16,1> (abs)wDIFF_TEMPORAL(13)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(14)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(3)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(15)<16;16,1> //Compute diff betn curr and prev. - Second 16 lines //13 lines. add (16) wDIFF_TEMPORAL(16)<1> ubCURR_UV(22,2)<16;16,1> -ubPREV_UV(8,0)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(17)<1> ubCURR_UV(23,2)<16;16,1> -ubPREV_UV(8,16)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(18)<1> ubCURR_UV(24,2)<16;16,1> -ubPREV_UV(8,32)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(19)<1> ubCURR_UV(25,2)<16;16,1> -ubPREV_UV(8,48)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(20)<1> ubCURR_UV(26,2)<16;16,1> -ubPREV_UV(8,64)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(21)<1> ubCURR_UV(27,2)<16;16,1> -ubPREV_UV(8,80)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(22)<1> ubCURR_UV(28,2)<16;16,1> -ubPREV_UV(8,96)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(23)<1> ubCURR_UV(29,2)<16;16,1> -ubPREV_UV(8,112)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(24)<1> ubCURR_UV(30,2)<16;16,1> -ubPREV_UV(8,128)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(25)<1> ubCURR_UV(31,2)<16;16,1> -ubPREV_UV(8,144)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(26)<1> ubCURR_UV(32,2)<16;16,1> -ubPREV_UV(8,160)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(27)<1> ubCURR_UV(33,2)<16;16,1> -ubPREV_UV(8,176)<16;16,1> //Diff UV interleaved add (16) wDIFF_TEMPORAL(28)<1> ubCURR_UV(34,2)<16;16,1> -ubPREV_UV(8,192)<16;16,1> //Diff UV interleaved //3 more lines add (16) wCURBE_TEMP(4)<1> ubCURR_UV(35,2)<16;16,1> -ubPREV_UV(8,208)<16;16,1> //Diff UV interleaved add (16) wCURBE_TEMP(5)<1> ubCURR_UV(36,2)<16;16,1> -ubPREV_UV(8,224)<16;16,1> //Diff UV interleaved add (16) wCURBE_TEMP(6)<1> ubCURR_UV(37,2)<16;16,1> -ubPREV_UV(8,240)<16;16,1> //Diff UV interleaved //16x4 to 8x4 - First 16 lines add (16) uwDIFF_TEMPORAL_SUM4x4(0)<1> uwDIFF_TEMPORAL_SUM4x4(0,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(0,2)<4;2,1> add (16) uwDIFF_TEMPORAL_SUM4x4(1)<1> uwDIFF_TEMPORAL_SUM4x4(2,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(2,2)<4;2,1> //8x4 to 4x4 - First 16 lines add (16) uwDIFF_TEMPORAL_SUM4x4_FINAL(0)<1> uwDIFF_TEMPORAL_SUM4x4(0,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(0,2)<4;2,1> { AccWrEn } //16x16 to 16x4 - Second 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(16)<16;16,1> (abs)wDIFF_TEMPORAL(17)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(18)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(0)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(19)<16;16,1> //16x16 to 16x4 - Second 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(20)<16;16,1> (abs)wDIFF_TEMPORAL(21)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(22)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(1)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(23)<16;16,1> //16x16 to 16x4 - Second 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(24)<16;16,1> (abs)wDIFF_TEMPORAL(25)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(26)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(2)<1> acc0.0<16;16,1>:uw (abs)wDIFF_TEMPORAL(27)<16;16,1> //16x16 to 16x4 - Second 16 lines add (16) acc0.0<1>:uw (abs)wDIFF_TEMPORAL(28)<16;16,1> (abs)wCURBE_TEMP(4)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wCURBE_TEMP(5)<16;16,1> add (16) uwDIFF_TEMPORAL_SUM4x4(3)<1> acc0.0<16;16,1>:uw (abs)wCURBE_TEMP(6)<16;16,1> //Find if block is motion block - First 16 lines cmp.g.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_FINAL(0)<16;16,1> r61.26<0;2,1>:ub //Move TEMPORAL_SUM4x4 for SIMD16 use later. mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,0)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,2)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,4)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,6)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,8)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,10)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,12)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(0,14)<0;2,1> //Pick Appropriate Weight History Based on motion. - First 16 lines (-f0.0) mov (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(2)<16;16,1> //Actual DN - First 16 lines cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(0)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(0)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(2,2)<8;8,1> -uwCURBE_TEMP(0,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(2,10)<8;8,1> -uwCURBE_TEMP(0,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(2,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,0)<8;8,1> uwCURBE_TEMP(0,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,8)<8;8,1> uwCURBE_TEMP(0,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(0)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(0)<1> ubCURR_UV(2,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(0)<1> wDIFF_TEMPORAL(0)<16;16,1> ubCURR_UV(2,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(1)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(1)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(3,2)<8;8,1> -uwCURBE_TEMP(0,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(3,10)<8;8,1> -uwCURBE_TEMP(0,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(3,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,16)<8;8,1> uwCURBE_TEMP(0,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,24)<8;8,1> uwCURBE_TEMP(0,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(1)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(1)<1> ubCURR_UV(3,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(1)<1> wDIFF_TEMPORAL(1)<16;16,1> ubCURR_UV(3,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(2)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(2)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(4,2)<8;8,1> -uwCURBE_TEMP(0,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(4,10)<8;8,1> -uwCURBE_TEMP(0,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(4,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,32)<8;8,1> uwCURBE_TEMP(0,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,40)<8;8,1> uwCURBE_TEMP(0,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(2)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(2)<1> ubCURR_UV(4,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(2)<1> wDIFF_TEMPORAL(2)<16;16,1> ubCURR_UV(4,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(3)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(3)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(5,2)<8;8,1> -uwCURBE_TEMP(0,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(5,10)<8;8,1> -uwCURBE_TEMP(0,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(5,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,48)<8;8,1> uwCURBE_TEMP(0,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,56)<8;8,1> uwCURBE_TEMP(0,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(3)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(3)<1> ubCURR_UV(5,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(3)<1> wDIFF_TEMPORAL(3)<16;16,1> ubCURR_UV(5,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(4)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(4)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(6,2)<8;8,1> -uwCURBE_TEMP(0,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(6,10)<8;8,1> -uwCURBE_TEMP(0,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(6,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,64)<8;8,1> uwCURBE_TEMP(0,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,72)<8;8,1> uwCURBE_TEMP(0,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(4)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(4)<1> ubCURR_UV(6,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(4)<1> wDIFF_TEMPORAL(4)<16;16,1> ubCURR_UV(6,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(5)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(5)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(7,2)<8;8,1> -uwCURBE_TEMP(0,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(7,10)<8;8,1> -uwCURBE_TEMP(0,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(7,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,80)<8;8,1> uwCURBE_TEMP(0,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,88)<8;8,1> uwCURBE_TEMP(0,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(5)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(5)<1> ubCURR_UV(7,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(5)<1> wDIFF_TEMPORAL(5)<16;16,1> ubCURR_UV(7,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(6)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(6)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(8,2)<8;8,1> -uwCURBE_TEMP(0,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(8,10)<8;8,1> -uwCURBE_TEMP(0,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(8,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,96)<8;8,1> uwCURBE_TEMP(0,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,104)<8;8,1> uwCURBE_TEMP(0,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(6)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(6)<1> ubCURR_UV(8,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(6)<1> wDIFF_TEMPORAL(6)<16;16,1> ubCURR_UV(8,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(7)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(7)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(9,2)<8;8,1> -uwCURBE_TEMP(0,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(9,10)<8;8,1> -uwCURBE_TEMP(0,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(9,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,112)<8;8,1> uwCURBE_TEMP(0,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,120)<8;8,1> uwCURBE_TEMP(0,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(7)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(7)<1> ubCURR_UV(9,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(7)<1> wDIFF_TEMPORAL(7)<16;16,1> ubCURR_UV(9,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(8)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(8)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(10,2)<8;8,1> -uwCURBE_TEMP(0,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(10,10)<8;8,1> -uwCURBE_TEMP(0,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(10,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,128)<8;8,1> uwCURBE_TEMP(0,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,136)<8;8,1> uwCURBE_TEMP(0,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(8)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(8)<1> ubCURR_UV(10,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(8)<1> wDIFF_TEMPORAL(8)<16;16,1> ubCURR_UV(10,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(9)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(9)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(11,2)<8;8,1> -uwCURBE_TEMP(0,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(11,10)<8;8,1> -uwCURBE_TEMP(0,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(11,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,144)<8;8,1> uwCURBE_TEMP(0,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,152)<8;8,1> uwCURBE_TEMP(0,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(9)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(9)<1> ubCURR_UV(11,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(9)<1> wDIFF_TEMPORAL(9)<16;16,1> ubCURR_UV(11,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(10)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(10)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(12,2)<8;8,1> -uwCURBE_TEMP(0,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(12,10)<8;8,1> -uwCURBE_TEMP(0,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(12,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,160)<8;8,1> uwCURBE_TEMP(0,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,168)<8;8,1> uwCURBE_TEMP(0,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(10)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(10)<1> ubCURR_UV(12,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(10)<1> wDIFF_TEMPORAL(10)<16;16,1> ubCURR_UV(12,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(11)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(11)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(13,2)<8;8,1> -uwCURBE_TEMP(0,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(13,10)<8;8,1> -uwCURBE_TEMP(0,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(13,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,176)<8;8,1> uwCURBE_TEMP(0,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,184)<8;8,1> uwCURBE_TEMP(0,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(11)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(11)<1> ubCURR_UV(13,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(11)<1> wDIFF_TEMPORAL(11)<16;16,1> ubCURR_UV(13,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(12)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(12)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(14,2)<8;8,1> -uwCURBE_TEMP(0,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(14,10)<8;8,1> -uwCURBE_TEMP(0,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(14,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,192)<8;8,1> uwCURBE_TEMP(0,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,200)<8;8,1> uwCURBE_TEMP(0,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(12)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(12)<1> ubCURR_UV(14,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(12)<1> wDIFF_TEMPORAL(12)<16;16,1> ubCURR_UV(14,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(13)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(13)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(15,2)<8;8,1> -uwCURBE_TEMP(0,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(15,10)<8;8,1> -uwCURBE_TEMP(0,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(15,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,208)<8;8,1> uwCURBE_TEMP(0,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,216)<8;8,1> uwCURBE_TEMP(0,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(13)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(13)<1> ubCURR_UV(15,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(13)<1> wDIFF_TEMPORAL(13)<16;16,1> ubCURR_UV(15,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(14)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(14)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(16,2)<8;8,1> -uwCURBE_TEMP(0,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(16,10)<8;8,1> -uwCURBE_TEMP(0,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(16,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,224)<8;8,1> uwCURBE_TEMP(0,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,232)<8;8,1> uwCURBE_TEMP(0,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(14)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(14)<1> ubCURR_UV(16,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(14)<1> wDIFF_TEMPORAL(14)<16;16,1> ubCURR_UV(16,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(15)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(15)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(17,2)<8;8,1> -uwCURBE_TEMP(0,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(17,10)<8;8,1> -uwCURBE_TEMP(0,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(17,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(0,240)<8;8,1> uwCURBE_TEMP(0,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(0,248)<8;8,1> uwCURBE_TEMP(0,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(15)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(15)<1> ubCURR_UV(17,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(15)<1> wDIFF_TEMPORAL(15)<16;16,1> ubCURR_UV(17,2)<16;16,1> //16x4 to 8x4 - Second 16 lines add (16) uwDIFF_TEMPORAL_SUM4x4(0)<1> uwDIFF_TEMPORAL_SUM4x4(0,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(0,2)<4;2,1> add (16) uwDIFF_TEMPORAL_SUM4x4(1)<1> uwDIFF_TEMPORAL_SUM4x4(2,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(2,2)<4;2,1> //8x4 to 4x4 - Second 16 lines add (16) uwDIFF_TEMPORAL_SUM4x4_FINAL(1)<1> uwDIFF_TEMPORAL_SUM4x4(0,0)<4;2,1> uwDIFF_TEMPORAL_SUM4x4(0,2)<4;2,1> { AccWrEn } //Find if block is motion block - Second 16 lines cmp.g.f1.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_FINAL(1)<16;16,1> r61.26<0;2,1>:ub //Move TEMPORAL_SUM4x4 for SIMD16 use later. mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,0)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,2)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,4)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,6)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,8)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,10)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0,0)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,12)<0;2,1> mov (8) uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0,8)<1> uwDIFF_TEMPORAL_SUM4x4_FINAL(1,14)<0;2,1> //Pick Appropriate Weight History Based on motion. - Second 16 lines (-f1.0) mov (16) uwCURBE_TEMP(1)<1> uwCURBE_TEMP(3)<16;16,1> //Actual DN - Second 16 lines cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(16)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(16)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(22,2)<8;8,1> -uwCURBE_TEMP(1,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(22,10)<8;8,1> -uwCURBE_TEMP(1,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(22,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,0)<8;8,1> uwCURBE_TEMP(1,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,8)<8;8,1> uwCURBE_TEMP(1,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(16)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(16)<1> ubCURR_UV(22,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(16)<1> wDIFF_TEMPORAL(16)<16;16,1> ubCURR_UV(22,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(17)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(17)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(23,2)<8;8,1> -uwCURBE_TEMP(1,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(23,10)<8;8,1> -uwCURBE_TEMP(1,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(23,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,16)<8;8,1> uwCURBE_TEMP(1,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,24)<8;8,1> uwCURBE_TEMP(1,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(17)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(17)<1> ubCURR_UV(23,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(17)<1> wDIFF_TEMPORAL(17)<16;16,1> ubCURR_UV(23,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(18)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(18)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(24,2)<8;8,1> -uwCURBE_TEMP(1,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(24,10)<8;8,1> -uwCURBE_TEMP(1,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(24,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,32)<8;8,1> uwCURBE_TEMP(1,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,40)<8;8,1> uwCURBE_TEMP(1,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(18)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(18)<1> ubCURR_UV(24,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(18)<1> wDIFF_TEMPORAL(18)<16;16,1> ubCURR_UV(24,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(19)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(19)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(25,2)<8;8,1> -uwCURBE_TEMP(1,0)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(25,10)<8;8,1> -uwCURBE_TEMP(1,2)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(25,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,48)<8;8,1> uwCURBE_TEMP(1,0)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,56)<8;8,1> uwCURBE_TEMP(1,2)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(19)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(19)<1> ubCURR_UV(25,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_0(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(19)<1> wDIFF_TEMPORAL(19)<16;16,1> ubCURR_UV(25,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(20)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(20)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(26,2)<8;8,1> -uwCURBE_TEMP(1,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(26,10)<8;8,1> -uwCURBE_TEMP(1,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(26,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,64)<8;8,1> uwCURBE_TEMP(1,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,72)<8;8,1> uwCURBE_TEMP(1,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(20)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(20)<1> ubCURR_UV(26,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(20)<1> wDIFF_TEMPORAL(20)<16;16,1> ubCURR_UV(26,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(21)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(21)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(27,2)<8;8,1> -uwCURBE_TEMP(1,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(27,10)<8;8,1> -uwCURBE_TEMP(1,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(27,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,80)<8;8,1> uwCURBE_TEMP(1,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,88)<8;8,1> uwCURBE_TEMP(1,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(21)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(21)<1> ubCURR_UV(27,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(21)<1> wDIFF_TEMPORAL(21)<16;16,1> ubCURR_UV(27,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(22)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(22)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(28,2)<8;8,1> -uwCURBE_TEMP(1,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(28,10)<8;8,1> -uwCURBE_TEMP(1,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(28,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,96)<8;8,1> uwCURBE_TEMP(1,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,104)<8;8,1> uwCURBE_TEMP(1,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(22)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(22)<1> ubCURR_UV(28,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(22)<1> wDIFF_TEMPORAL(22)<16;16,1> ubCURR_UV(28,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(23)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(23)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(29,2)<8;8,1> -uwCURBE_TEMP(1,4)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(29,10)<8;8,1> -uwCURBE_TEMP(1,6)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(29,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,112)<8;8,1> uwCURBE_TEMP(1,4)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,120)<8;8,1> uwCURBE_TEMP(1,6)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(23)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(23)<1> ubCURR_UV(29,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_1(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(23)<1> wDIFF_TEMPORAL(23)<16;16,1> ubCURR_UV(29,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(24)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(24)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(30,2)<8;8,1> -uwCURBE_TEMP(1,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(30,10)<8;8,1> -uwCURBE_TEMP(1,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(30,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,128)<8;8,1> uwCURBE_TEMP(1,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,136)<8;8,1> uwCURBE_TEMP(1,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(24)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(24)<1> ubCURR_UV(30,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(24)<1> wDIFF_TEMPORAL(24)<16;16,1> ubCURR_UV(30,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(25)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(25)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(31,2)<8;8,1> -uwCURBE_TEMP(1,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(31,10)<8;8,1> -uwCURBE_TEMP(1,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(31,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,144)<8;8,1> uwCURBE_TEMP(1,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,152)<8;8,1> uwCURBE_TEMP(1,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(25)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(25)<1> ubCURR_UV(31,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(25)<1> wDIFF_TEMPORAL(25)<16;16,1> ubCURR_UV(31,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(26)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(26)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(32,2)<8;8,1> -uwCURBE_TEMP(1,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(32,10)<8;8,1> -uwCURBE_TEMP(1,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(32,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,160)<8;8,1> uwCURBE_TEMP(1,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,168)<8;8,1> uwCURBE_TEMP(1,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(26)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(26)<1> ubCURR_UV(32,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(26)<1> wDIFF_TEMPORAL(26)<16;16,1> ubCURR_UV(32,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(27)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(27)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(33,2)<8;8,1> -uwCURBE_TEMP(1,8)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(33,10)<8;8,1> -uwCURBE_TEMP(1,10)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(33,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,176)<8;8,1> uwCURBE_TEMP(1,8)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,184)<8;8,1> uwCURBE_TEMP(1,10)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(27)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(27)<1> ubCURR_UV(33,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_2(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(27)<1> wDIFF_TEMPORAL(27)<16;16,1> ubCURR_UV(33,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(28)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wDIFF_TEMPORAL(28)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(34,2)<8;8,1> -uwCURBE_TEMP(1,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(34,10)<8;8,1> -uwCURBE_TEMP(1,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(34,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,192)<8;8,1> uwCURBE_TEMP(1,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,200)<8;8,1> uwCURBE_TEMP(1,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wDIFF_TEMPORAL(28)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wDIFF_TEMPORAL(28)<1> ubCURR_UV(34,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wDIFF_TEMPORAL(28)<1> wDIFF_TEMPORAL(28)<16;16,1> ubCURR_UV(34,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wCURBE_TEMP(4)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wCURBE_TEMP(4)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(35,2)<8;8,1> -uwCURBE_TEMP(1,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(35,10)<8;8,1> -uwCURBE_TEMP(1,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(35,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,208)<8;8,1> uwCURBE_TEMP(1,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,216)<8;8,1> uwCURBE_TEMP(1,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wCURBE_TEMP(4)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wCURBE_TEMP(4)<1> ubCURR_UV(35,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wCURBE_TEMP(4)<1> wCURBE_TEMP(4)<16;16,1> ubCURR_UV(35,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wCURBE_TEMP(5)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wCURBE_TEMP(5)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(36,2)<8;8,1> -uwCURBE_TEMP(1,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(36,10)<8;8,1> -uwCURBE_TEMP(1,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(36,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,224)<8;8,1> uwCURBE_TEMP(1,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,232)<8;8,1> uwCURBE_TEMP(1,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wCURBE_TEMP(5)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wCURBE_TEMP(5)<1> ubCURR_UV(36,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wCURBE_TEMP(5)<1> wCURBE_TEMP(5)<16;16,1> ubCURR_UV(36,2)<16;16,1> cmp.l.f0.0 (16) null<1>:w (abs)wCURBE_TEMP(6)<16;16,1> r61.28<0;2,1>:ub cmp.l.f1.0 (16) null<1>:w (abs)wCURBE_TEMP(6)<16;16,1> r61.30<0;2,1>:ub mul (8) acc0.0<1>:w ubCURR_UV(37,2)<8;8,1> -uwCURBE_TEMP(1,12)<0;2,1> mul (8) acc0.8<1>:w ubCURR_UV(37,10)<8;8,1> -uwCURBE_TEMP(1,14)<0;2,1> mac (16) acc0<1>:w ubCURR_UV(37,2)<16;16,1> 256:w mac (8) acc0.0<1>:w ubPREV_UV(8,240)<8;8,1> uwCURBE_TEMP(1,12)<0;2,1> mac (8) acc0.8<1>:w ubPREV_UV(8,248)<8;8,1> uwCURBE_TEMP(1,14)<0;2,1> add (16) acc0<1>:w acc0<16;16,1>:w 128:w (f0.0) shr (16) wCURBE_TEMP(6)<1> acc0<16;16,1>:w 8:w (-f0.0) mov (16) wCURBE_TEMP(6)<1> ubCURR_UV(37,2)<16;16,1> cmp.le.f0.0 (16) null<1>:w uwDIFF_TEMPORAL_SUM4x4_TEMP_3(0)<16;16,1> r61.26<0;2,1>:ub (-f0.0.allv) avg (16) wCURBE_TEMP(6)<1> wCURBE_TEMP(6)<16;16,1> ubCURR_UV(37,2)<16;16,1> //Pack Weight History WORD -> BYTE mov (16) ubCURBE_TEMP(3,0)<1> ubCURBE_TEMP(0)<32;16,2> mov (16) ubCURBE_TEMP(3,16)<1> ubCURBE_TEMP(1)<32;16,2> //Module Name : DN_UV_Compute_BNE_UV //Author : Tatiya, Rupesh //Description : Computes minimum SOAD for each 16x4 block. cmp.l.f0.0 (8) null:w uwSOAD_MIN_8x4(0,12)<16;4,1> uwSOAD_MIN_8x4(2,12)<16;4,1> (f0.0)sel (8) uwCURBE_TEMP(1,0)<1> uwSOAD_MIN_8x4(0,12)<16;4,1> uwSOAD_MIN_8x4(2,12)<16;4,1> mov (8) ubCURBE_TEMP(1)<1> ubCURBE_TEMP(1)<16;8,2> //File Name : DN_UV_PL3_Unpack_Denoised_UV.asm //Author : Tatiya, Rupesh //Description : Upack the interleaved UV data //First 16 lines. mov (8) ubMSGPAYLOAD_U(0,0)<1> ubDIFF_TEMPORAL(0,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(0,16)<1> ubDIFF_TEMPORAL(1,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(0,0)<1> ubDIFF_TEMPORAL(0,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(0,16)<1> ubDIFF_TEMPORAL(1,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(1,0)<1> ubDIFF_TEMPORAL(2,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(1,16)<1> ubDIFF_TEMPORAL(3,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(1,0)<1> ubDIFF_TEMPORAL(2,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(1,16)<1> ubDIFF_TEMPORAL(3,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(2,0)<1> ubDIFF_TEMPORAL(4,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(2,16)<1> ubDIFF_TEMPORAL(5,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(2,0)<1> ubDIFF_TEMPORAL(4,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(2,16)<1> ubDIFF_TEMPORAL(5,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(3,0)<1> ubDIFF_TEMPORAL(6,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(3,16)<1> ubDIFF_TEMPORAL(7,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(3,0)<1> ubDIFF_TEMPORAL(6,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(3,16)<1> ubDIFF_TEMPORAL(7,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(4,0)<1> ubDIFF_TEMPORAL(8,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(4,16)<1> ubDIFF_TEMPORAL(9,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(4,0)<1> ubDIFF_TEMPORAL(8,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(4,16)<1> ubDIFF_TEMPORAL(9,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(5,0)<1> ubDIFF_TEMPORAL(10,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(5,16)<1> ubDIFF_TEMPORAL(11,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(5,0)<1> ubDIFF_TEMPORAL(10,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(5,16)<1> ubDIFF_TEMPORAL(11,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(6,0)<1> ubDIFF_TEMPORAL(12,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(6,16)<1> ubDIFF_TEMPORAL(13,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(6,0)<1> ubDIFF_TEMPORAL(12,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(6,16)<1> ubDIFF_TEMPORAL(13,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(7,0)<1> ubDIFF_TEMPORAL(14,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(7,16)<1> ubDIFF_TEMPORAL(15,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(7,0)<1> ubDIFF_TEMPORAL(14,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(7,16)<1> ubDIFF_TEMPORAL(15,2)<32;8,4> //Second 16 lines. //12 lines first mov (8) ubMSGPAYLOAD_U(0,8)<1> ubDIFF_TEMPORAL(16,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(0,24)<1> ubDIFF_TEMPORAL(17,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(0,8)<1> ubDIFF_TEMPORAL(16,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(0,24)<1> ubDIFF_TEMPORAL(17,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(1,8)<1> ubDIFF_TEMPORAL(18,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(1,24)<1> ubDIFF_TEMPORAL(19,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(1,8)<1> ubDIFF_TEMPORAL(18,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(1,24)<1> ubDIFF_TEMPORAL(19,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(2,8)<1> ubDIFF_TEMPORAL(20,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(2,24)<1> ubDIFF_TEMPORAL(21,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(2,8)<1> ubDIFF_TEMPORAL(20,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(2,24)<1> ubDIFF_TEMPORAL(21,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(3,8)<1> ubDIFF_TEMPORAL(22,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(3,24)<1> ubDIFF_TEMPORAL(23,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(3,8)<1> ubDIFF_TEMPORAL(22,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(3,24)<1> ubDIFF_TEMPORAL(23,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(4,8)<1> ubDIFF_TEMPORAL(24,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(4,24)<1> ubDIFF_TEMPORAL(25,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(4,8)<1> ubDIFF_TEMPORAL(24,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(4,24)<1> ubDIFF_TEMPORAL(25,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(5,8)<1> ubDIFF_TEMPORAL(26,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(5,24)<1> ubDIFF_TEMPORAL(27,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(5,8)<1> ubDIFF_TEMPORAL(26,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(5,24)<1> ubDIFF_TEMPORAL(27,2)<32;8,4> //3 lines next mov (8) ubMSGPAYLOAD_U(6,8)<1> ubDIFF_TEMPORAL(28,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(6,24)<1> ubCURBE_TEMP(4,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(6,8)<1> ubDIFF_TEMPORAL(28,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(6,24)<1> ubCURBE_TEMP(4,2)<32;8,4> mov (8) ubMSGPAYLOAD_U(7,8)<1> ubCURBE_TEMP(5,0)<32;8,4> mov (8) ubMSGPAYLOAD_U(7,24)<1> ubCURBE_TEMP(6,0)<32;8,4> mov (8) ubMSGPAYLOAD_V(7,8)<1> ubCURBE_TEMP(5,2)<32;8,4> mov (8) ubMSGPAYLOAD_V(7,24)<1> ubCURBE_TEMP(6,2)<32;8,4> //Module Name : DN_UV_420_Save_Curr_Frame_Y //Author : Tatiya, Rupesh //Description : Save Curr Frame Y data for 420 Input //Module Name : DN_UV_Load_Curr_Frame_Y //Author : Tatiya, Rupesh //Description : Saves Y or YUY2 of Current frame. mov (8) acc0.0<1>:ud r0.0<8;8,1>:ud mov (2) acc0.0<1>:d r62.10<2;2,1>:w mov (1) acc0.2<1>:d 0xF000F:ud mov (8) r92.0<1>:ud acc0.0<8;8,1>:ud mov (8) r101.0<1>:ud acc0.0<8;8,1>:ud mov (8) r110.0<1>:ud acc0.0<8;8,1>:ud mov (8) r119.0<1>:ud acc0.0<8;8,1>:ud add (1) r101.1<1>:d acc0.1<0;1,0>:d 16:d add (1) r110.0<1>:d acc0.0<0;1,0>:d 16:d add (2) r119.0<1>:d acc0.0<2;2,1>:d 16:d send (8) null<1>:d r92 0x5 0x120A8018:ud send (8) null<1>:d r101 0x5 0x120A8018:ud send (8) null<1>:d r110 0x5 0x120A8018:ud send (8) null<1>:d r119 0x5 0x120A8018:ud //TODO - See if History saving can be combined with Curr Frame Save. - rT //Module Name : DN_UV_Save_Hist_UV //Author : Tatiya, Rupesh //Description : Saves DN history for UV data. mov (8) r3.0<1>:ud r0.0<8;8,1>:ud mov (2) r3.0<1>:d r62.12<2;2,1>:w mov (1) r3.2<1>:d 0x30007:ud send (8) null<1>:d r3 0x5 0x40A8021:ud //Module Name : DN_UV_Save_BNE_UV //Author : Tatiya, Rupesh //Description : Saves BNE values for 16x16 U and 16x16 V. mov (8) r1.0<1>:ud r0.0<8;8,1>:ud mov (2) r1.0<1>:d r63.12<2;2,1>:w mov (1) r1.2<1>:d 0x10003:ud send (8) null<1>:d r1 0x5 0x40A8023:ud //File Name : DN_UV_PL3_Save_Curr_Frame_UV.asm //Author : Tatiya, Rupesh //Description : Save U and V data for PL3 surface //Module name : DN_UV_Save_Curr_Frame_UV //Author : Tatiya, Rupesh //Description : Saves Current Frame (UV only). mov (8) r74<1>:ud r0.0<8;8,1>:ud mov (8) r83<1>:ud r0.0<8;8,1>:ud shr (2) r74.0<1>:d r62.10<2;2,1>:w 1:w mov (1) r74.2<1>:d 0xF000F:ud mov (8) r83.0<1>:ud r74.0<8;8,1>:ud send (8) null<1>:d r74 0x5 0x120A8019:ud send (8) null<1>:d r83 0x5 0x120A801A:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 //All sub-routines here // Module Name : Noise_Detection // Author : Tatiya, Rupesh // Description : Performs noise detection on 32 pixels of U (8x4) and 32 pixels of V (8x4). DN_UV_NOISE_DETECTION_UV: // Find Field Block Median // // Purpose : Find the median value of the nine pixels in the same field // which are centered at current pixel. // // Works on 9 pixels centered at the current pixel // NOTE: pixels are within same field. // v4 - current pixel // // v2 v1 v0 // * * * <--- Different field - not used // v5 v4 v3 // * * * <--- Different field - not used // v8 v7 v6 // Algorithm to find median modifies the data. // Copy the data needed to calculate median so the original source data stays intact. // //TODO - Change Interleaved implementation to separated one if - , does not work on predication. - rT //Delete Later - rT //mov (1) pCUR_UV:uw 52*32:uw // v0 mov (16) ubMEDIAN_TEMP(0,0)<1> r[a0.0,0]<16;16,1> // v0 mov (16) ubMEDIAN_TEMP(0,16)<1> r[a0.0,32]<16;16,1> // v1 mov (16) ubMEDIAN_TEMP(1,0)<1> r[a0.0,2]<16;16,1> // v1 mov (16) ubMEDIAN_TEMP(1,16)<1> r[a0.0,34]<16;16,1> // v2 mov (16) ubMEDIAN_TEMP(2,0)<1> r[a0.0,4]<16;16,1> // v2 mov (16) ubMEDIAN_TEMP(2,16)<1> r[a0.0,36]<16;16,1> // v3 mov (16) ubMEDIAN_TEMP(3,0)<1> r[a0.0,64]<16;16,1> // v3 mov (16) ubMEDIAN_TEMP(3,16)<1> r[a0.0,96]<16;16,1> // v4 mov (16) ubMEDIAN_TEMP(4,0)<1> r[a0.0,66]<16;16,1> // v4 mov (16) ubMEDIAN_TEMP(4,16)<1> r[a0.0,98]<16;16,1> // v5 mov (16) ubMEDIAN_TEMP(5,0)<1> r[a0.0,68]<16;16,1> // v5 mov (16) ubMEDIAN_TEMP(5,16)<1> r[a0.0,100]<16;16,1> // v6 mov (16) ubMEDIAN_TEMP(6,0)<1> r[a0.0,128]<16;16,1> // v6 mov (16) ubMEDIAN_TEMP(6,16)<1> r[a0.0,160]<16;16,1> // v7 mov (16) ubMEDIAN_TEMP(7,0)<1> r[a0.0,130]<16;16,1> // v7 mov (16) ubMEDIAN_TEMP(7,16)<1> r[a0.0,162]<16;16,1> // v8 mov (16) ubMEDIAN_TEMP(8,0)<1> r[a0.0,132]<16;16,1> // v8 mov (16) ubMEDIAN_TEMP(8,16)<1> r[a0.0,164]<16;16,1> //TODO - Optimize one instruction here. add (1) a0.0:uw a0.0<0;1,0>:uw 64:uw // v0 mov (16) ubMEDIAN_TEMP(9,0)<1> r[a0.0,0]<16;16,1> // v0 mov (16) ubMEDIAN_TEMP(9,16)<1> r[a0.0,32]<16;16,1> // v1 mov (16) ubMEDIAN_TEMP(10,0)<1> r[a0.0,2]<16;16,1> // v1 mov (16) ubMEDIAN_TEMP(10,16)<1> r[a0.0,34]<16;16,1> // v2 mov (16) ubMEDIAN_TEMP(11,0)<1> r[a0.0,4]<16;16,1> // v2 mov (16) ubMEDIAN_TEMP(11,16)<1> r[a0.0,36]<16;16,1> // v3 mov (16) ubMEDIAN_TEMP(12,0)<1> r[a0.0,64]<16;16,1> // v3 mov (16) ubMEDIAN_TEMP(12,16)<1> r[a0.0,96]<16;16,1> // v4 mov (16) ubMEDIAN_TEMP(13,0)<1> r[a0.0,66]<16;16,1> // v4 mov (16) ubMEDIAN_TEMP(13,16)<1> r[a0.0,98]<16;16,1> // v5 mov (16) ubMEDIAN_TEMP(14,0)<1> r[a0.0,68]<16;16,1> // v5 mov (16) ubMEDIAN_TEMP(14,16)<1> r[a0.0,100]<16;16,1> // v6 mov (16) ubMEDIAN_TEMP(15,0)<1> r[a0.0,128]<16;16,1> // v6 mov (16) ubMEDIAN_TEMP(15,16)<1> r[a0.0,160]<16;16,1> // v7 mov (16) ubMEDIAN_TEMP(16,0)<1> r[a0.0,130]<16;16,1> // v7 mov (16) ubMEDIAN_TEMP(16,16)<1> r[a0.0,162]<16;16,1> // v8 mov (16) ubMEDIAN_TEMP(17,0)<1> r[a0.0,132]<16;16,1> // v8 mov (16) ubMEDIAN_TEMP(17,16)<1> r[a0.0,164]<16;16,1> //TODO - Optimize one instruction here. add (1) a0.0:uw a0.0<0;1,0>:uw 64:uw // MedianSwap // // MedianSwap(inOutLeft, inOutRight) // { // if (inOutLeft > inOutRight) // { // temp = inOutLeft // inOutLeft = inOutRight // inOutRight = temp // } // } // MedianSwap(v1, v2) - U // MedianSwap(v4, v5) - U // MedianSwap(v1, v2) - V // MedianSwap(v4, v5) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(1,0)<32;16,2> ubMEDIAN_TEMP(2,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(5,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(1,1)<32;16,2> ubMEDIAN_TEMP(2,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(5,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(1,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(4,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(1,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(1,0)<2> ubMEDIAN_TEMP(2,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(5,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(1,1)<2> ubMEDIAN_TEMP(2,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(5,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(2,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(5,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(2,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(5,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v7, v8) - U // MedianSwap(v0, v1) - U // MedianSwap(v7, v8) - V // MedianSwap(v0, v1) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(7,0)<32;16,2> ubMEDIAN_TEMP(8,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(0,0)<32;16,2> ubMEDIAN_TEMP(1,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(7,1)<32;16,2> ubMEDIAN_TEMP(8,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(0,1)<32;16,2> ubMEDIAN_TEMP(1,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(7,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(0,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(7,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(0,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(7,0)<2> ubMEDIAN_TEMP(8,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(0,0)<2> ubMEDIAN_TEMP(1,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(7,1)<2> ubMEDIAN_TEMP(8,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(0,1)<2> ubMEDIAN_TEMP(1,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(8,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(1,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(8,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(1,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v3, v4) - U // MedianSwap(v6, v7) - U // MedianSwap(v3, v4) - V // MedianSwap(v6, v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(3,0)<32;16,2> ubMEDIAN_TEMP(4,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(6,0)<32;16,2> ubMEDIAN_TEMP(7,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(3,1)<32;16,2> ubMEDIAN_TEMP(4,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(6,1)<32;16,2> ubMEDIAN_TEMP(7,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(3,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(6,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(3,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(6,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(3,0)<2> ubMEDIAN_TEMP(4,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(6,0)<2> ubMEDIAN_TEMP(7,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(3,1)<2> ubMEDIAN_TEMP(4,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(6,1)<2> ubMEDIAN_TEMP(7,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(4,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(7,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(4,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(7,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v1, v2) - U // MedianSwap(v4, v5) - U // MedianSwap(v1, v2) - V // MedianSwap(v4, v5) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(1,0)<32;16,2> ubMEDIAN_TEMP(2,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(5,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(1,1)<32;16,2> ubMEDIAN_TEMP(2,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(5,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(1,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(4,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(1,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(1,0)<2> ubMEDIAN_TEMP(2,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(5,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(1,1)<2> ubMEDIAN_TEMP(2,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(5,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(2,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(5,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(2,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(5,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v7, v8) - U // MedianSwap(v0, v3) - U // MedianSwap(v7, v8) - V // MedianSwap(v0, v3) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(7,0)<32;16,2> ubMEDIAN_TEMP(8,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(0,0)<32;16,2> ubMEDIAN_TEMP(3,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(7,1)<32;16,2> ubMEDIAN_TEMP(8,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(0,1)<32;16,2> ubMEDIAN_TEMP(3,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(7,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(0,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(7,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(0,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(7,0)<2> ubMEDIAN_TEMP(8,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(0,0)<2> ubMEDIAN_TEMP(3,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(7,1)<2> ubMEDIAN_TEMP(8,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(0,1)<2> ubMEDIAN_TEMP(3,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(8,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(3,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(8,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(3,1)<2> ubTEMP1(1,16)<16;16,1> // NOTE: // Compare v0 to v6 to find the minimum. // Store the minimum for future use. //TODO - Find if MIN is needed. //cmp.l.f0.0 (16) null:w ubMEDIAN_TEMP(%1+0,0)<32;16,2> ubMEDIAN_TEMP(%1+6,0)<32;16,2> //cmp.l.f1.0 (16) null:w ubMEDIAN_TEMP(%1+0,1)<32;16,2> ubMEDIAN_TEMP(%1+6,1)<32;16,2> //(f0.0) mov (16) ubCURR_MIN(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+0,0)<32;16,2> //(f1.0) mov (16) ubCURR_MIN(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+0,1)<32;16,2> //(-f0.0) mov (16) ubCURR_MIN(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+6,0)<32;16,2> //(-f1.0) mov (16) ubCURR_MIN(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+6,1)<32;16,2> // MedianSwap(v5, v8) - U // MedianSwap(v4, v7) - U // MedianSwap(v5, v8) - V // MedianSwap(v4, v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(5,0)<32;16,2> ubMEDIAN_TEMP(8,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(7,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(5,1)<32;16,2> ubMEDIAN_TEMP(8,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(7,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(5,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(4,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(5,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(5,0)<2> ubMEDIAN_TEMP(8,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(7,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(5,1)<2> ubMEDIAN_TEMP(8,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(7,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(8,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(7,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(8,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(7,1)<2> ubTEMP1(1,16)<16;16,1> // NOTE: // Compare v2 to v8 to find the maximum. // Store the maximum for future use. //TODO - Find if MAX is needed. // cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(%1+2,0)<32;16,2> ubMEDIAN_TEMP(%1+8,0)<32;16,2> // cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(%1+2,1)<32;16,2> ubMEDIAN_TEMP(%1+8,1)<32;16,2> //(f0.0) mov (16) ubCURR_MAX(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+2,0)<32;16,2> //(f1.0) mov (16) ubCURR_MAX(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+2,1)<32;16,2> //(-f0.0) mov (16) ubCURR_MAX(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+8,0)<32;16,2> //(-f1.0) mov (16) ubCURR_MAX(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+8,1)<32;16,2> // MedianSwap(v3, v6) - U // MedianSwap(v1, v4) - U // MedianSwap(v3, v6) - V // MedianSwap(v1, v4) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(3,0)<32;16,2> ubMEDIAN_TEMP(6,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(1,0)<32;16,2> ubMEDIAN_TEMP(4,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(3,1)<32;16,2> ubMEDIAN_TEMP(6,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(1,1)<32;16,2> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(6,0)<2> ubMEDIAN_TEMP(3,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(1,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(6,1)<2> ubMEDIAN_TEMP(3,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(1,1)<32;16,2> // MedianSwap(v2,v5) - U // MedianSwap(v4,v7) - U // MedianSwap(v2,v5) - V // MedianSwap(v4,v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(2,0)<32;16,2> ubMEDIAN_TEMP(5,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(7,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(2,1)<32;16,2> ubMEDIAN_TEMP(5,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(7,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(2,0)<2> ubMEDIAN_TEMP(5,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(7,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(2,1)<2> ubMEDIAN_TEMP(5,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(7,1)<32;16,2> // MedianSwap(v4,v2) - U // MedianSwap(v4,v2) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(2,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(2,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(4,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(2,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(2,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(2,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(2,1)<2> ubTEMP1(0,16)<16;16,1> // MedianSwap(v6,v4) - U // MedianSwap(v6,v4) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(6,0)<32;16,2> ubMEDIAN_TEMP(4,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(6,1)<32;16,2> ubMEDIAN_TEMP(4,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(6,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(6,1)<32;16,2> // MedianSwap(v4,v2) - U // MedianSwap(v4,v2) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(4,0)<32;16,2> ubMEDIAN_TEMP(2,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(4,1)<32;16,2> ubMEDIAN_TEMP(2,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(4,0)<2> ubMEDIAN_TEMP(2,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(4,1)<2> ubMEDIAN_TEMP(2,1)<32;16,2> cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(10,0)<32;16,2> ubMEDIAN_TEMP(11,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(14,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(10,1)<32;16,2> ubMEDIAN_TEMP(11,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(14,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(10,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(13,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(10,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(10,0)<2> ubMEDIAN_TEMP(11,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(14,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(10,1)<2> ubMEDIAN_TEMP(11,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(14,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(11,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(14,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(11,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(14,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v7, v8) - U // MedianSwap(v0, v1) - U // MedianSwap(v7, v8) - V // MedianSwap(v0, v1) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(16,0)<32;16,2> ubMEDIAN_TEMP(17,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(9,0)<32;16,2> ubMEDIAN_TEMP(10,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(16,1)<32;16,2> ubMEDIAN_TEMP(17,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(9,1)<32;16,2> ubMEDIAN_TEMP(10,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(16,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(9,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(16,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(9,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(16,0)<2> ubMEDIAN_TEMP(17,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(9,0)<2> ubMEDIAN_TEMP(10,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(16,1)<2> ubMEDIAN_TEMP(17,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(9,1)<2> ubMEDIAN_TEMP(10,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(17,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(10,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(17,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(10,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v3, v4) - U // MedianSwap(v6, v7) - U // MedianSwap(v3, v4) - V // MedianSwap(v6, v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(12,0)<32;16,2> ubMEDIAN_TEMP(13,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(15,0)<32;16,2> ubMEDIAN_TEMP(16,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(12,1)<32;16,2> ubMEDIAN_TEMP(13,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(15,1)<32;16,2> ubMEDIAN_TEMP(16,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(12,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(15,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(12,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(15,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(12,0)<2> ubMEDIAN_TEMP(13,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(15,0)<2> ubMEDIAN_TEMP(16,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(12,1)<2> ubMEDIAN_TEMP(13,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(15,1)<2> ubMEDIAN_TEMP(16,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(13,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(16,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(13,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(16,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v1, v2) - U // MedianSwap(v4, v5) - U // MedianSwap(v1, v2) - V // MedianSwap(v4, v5) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(10,0)<32;16,2> ubMEDIAN_TEMP(11,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(14,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(10,1)<32;16,2> ubMEDIAN_TEMP(11,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(14,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(10,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(13,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(10,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(10,0)<2> ubMEDIAN_TEMP(11,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(14,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(10,1)<2> ubMEDIAN_TEMP(11,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(14,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(11,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(14,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(11,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(14,1)<2> ubTEMP1(1,16)<16;16,1> // MedianSwap(v7, v8) - U // MedianSwap(v0, v3) - U // MedianSwap(v7, v8) - V // MedianSwap(v0, v3) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(16,0)<32;16,2> ubMEDIAN_TEMP(17,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(9,0)<32;16,2> ubMEDIAN_TEMP(12,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(16,1)<32;16,2> ubMEDIAN_TEMP(17,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(9,1)<32;16,2> ubMEDIAN_TEMP(12,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(16,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(9,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(16,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(9,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(16,0)<2> ubMEDIAN_TEMP(17,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(9,0)<2> ubMEDIAN_TEMP(12,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(16,1)<2> ubMEDIAN_TEMP(17,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(9,1)<2> ubMEDIAN_TEMP(12,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(17,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(12,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(17,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(12,1)<2> ubTEMP1(1,16)<16;16,1> // NOTE: // Compare v0 to v6 to find the minimum. // Store the minimum for future use. //TODO - Find if MIN is needed. //cmp.l.f0.0 (16) null:w ubMEDIAN_TEMP(%1+0,0)<32;16,2> ubMEDIAN_TEMP(%1+6,0)<32;16,2> //cmp.l.f1.0 (16) null:w ubMEDIAN_TEMP(%1+0,1)<32;16,2> ubMEDIAN_TEMP(%1+6,1)<32;16,2> //(f0.0) mov (16) ubCURR_MIN(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+0,0)<32;16,2> //(f1.0) mov (16) ubCURR_MIN(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+0,1)<32;16,2> //(-f0.0) mov (16) ubCURR_MIN(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+6,0)<32;16,2> //(-f1.0) mov (16) ubCURR_MIN(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+6,1)<32;16,2> // MedianSwap(v5, v8) - U // MedianSwap(v4, v7) - U // MedianSwap(v5, v8) - V // MedianSwap(v4, v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(14,0)<32;16,2> ubMEDIAN_TEMP(17,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(16,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(14,1)<32;16,2> ubMEDIAN_TEMP(17,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(16,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(14,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(13,0)<32;16,2> mov (16) ubTEMP1(1,0)<1> ubMEDIAN_TEMP(14,1)<32;16,2> mov (16) ubTEMP1(1,16)<1> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(14,0)<2> ubMEDIAN_TEMP(17,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(16,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(14,1)<2> ubMEDIAN_TEMP(17,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(16,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(17,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(16,0)<2> ubTEMP1(0,16)<16;16,1> (f1.0) mov (16) ubMEDIAN_TEMP(17,1)<2> ubTEMP1(1,0)<16;16,1> (f1.1) mov (16) ubMEDIAN_TEMP(16,1)<2> ubTEMP1(1,16)<16;16,1> // NOTE: // Compare v2 to v8 to find the maximum. // Store the maximum for future use. //TODO - Find if MAX is needed. // cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(%1+2,0)<32;16,2> ubMEDIAN_TEMP(%1+8,0)<32;16,2> // cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(%1+2,1)<32;16,2> ubMEDIAN_TEMP(%1+8,1)<32;16,2> //(f0.0) mov (16) ubCURR_MAX(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+2,0)<32;16,2> //(f1.0) mov (16) ubCURR_MAX(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+2,1)<32;16,2> //(-f0.0) mov (16) ubCURR_MAX(0,%2*16+0)<1> ubMEDIAN_TEMP(%1+8,0)<32;16,2> //(-f1.0) mov (16) ubCURR_MAX(1,%2*16+0)<1> ubMEDIAN_TEMP(%1+8,1)<32;16,2> // MedianSwap(v3, v6) - U // MedianSwap(v1, v4) - U // MedianSwap(v3, v6) - V // MedianSwap(v1, v4) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(12,0)<32;16,2> ubMEDIAN_TEMP(15,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(10,0)<32;16,2> ubMEDIAN_TEMP(13,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(12,1)<32;16,2> ubMEDIAN_TEMP(15,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(10,1)<32;16,2> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(15,0)<2> ubMEDIAN_TEMP(12,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(10,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(15,1)<2> ubMEDIAN_TEMP(12,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(10,1)<32;16,2> // MedianSwap(v2,v5) - U // MedianSwap(v4,v7) - U // MedianSwap(v2,v5) - V // MedianSwap(v4,v7) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(11,0)<32;16,2> ubMEDIAN_TEMP(14,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(16,0)<32;16,2> cmp.g.f1.0 (16) null:w ubMEDIAN_TEMP(11,1)<32;16,2> ubMEDIAN_TEMP(14,1)<32;16,2> cmp.g.f1.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(16,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(11,0)<2> ubMEDIAN_TEMP(14,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(16,0)<32;16,2> (f1.0) mov (16) ubMEDIAN_TEMP(11,1)<2> ubMEDIAN_TEMP(14,1)<32;16,2> (f1.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(16,1)<32;16,2> // MedianSwap(v4,v2) - U // MedianSwap(v4,v2) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(11,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(11,1)<32;16,2> mov (16) ubTEMP1(0,0)<1> ubMEDIAN_TEMP(13,0)<32;16,2> mov (16) ubTEMP1(0,16)<1> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(11,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(11,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(11,0)<2> ubTEMP1(0,0)<16;16,1> (f0.1) mov (16) ubMEDIAN_TEMP(11,1)<2> ubTEMP1(0,16)<16;16,1> // MedianSwap(v6,v4) - U // MedianSwap(v6,v4) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(15,0)<32;16,2> ubMEDIAN_TEMP(13,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(15,1)<32;16,2> ubMEDIAN_TEMP(13,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(15,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(15,1)<32;16,2> // MedianSwap(v4,v2) - U // MedianSwap(v4,v2) - V cmp.g.f0.0 (16) null:w ubMEDIAN_TEMP(13,0)<32;16,2> ubMEDIAN_TEMP(11,0)<32;16,2> cmp.g.f0.1 (16) null:w ubMEDIAN_TEMP(13,1)<32;16,2> ubMEDIAN_TEMP(11,1)<32;16,2> (f0.0) mov (16) ubMEDIAN_TEMP(13,0)<2> ubMEDIAN_TEMP(11,0)<32;16,2> (f0.1) mov (16) ubMEDIAN_TEMP(13,1)<2> ubMEDIAN_TEMP(11,1)<32;16,2> // Sobel Value calculation for the current pixel v4 // v2 v1 v0 // * * * <--- Different field - not used // v5 v4 v3 // * * * <--- Different field - not used // v8 v7 v6 // // Gx = -v0 - 2*v3 - v6 + v2 + 2*v5 + v8 // Gy = v0 + 2*v1 + v2 - v6 - 2*v7 - v8 // // Sobel = (|Gx| + |Gy|) >> 3 //TODO - Change Later - rT add (1) a0.0:uw a0.0<0;1,0>:uw -128:uw // - 2 * v3 mul (16) acc0.0<1>:w r[a0.0,64]<16;16,1>:ub -2:w // + v8 mac (16) acc0.0<1>:w r[a0.0,132]<16;16,1>:ub 1:w // - v0 mac (16) acc0.0<1>:w r[a0.0,0]<16;16,1>:ub -1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,128]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,4]<16;16,1>:ub 1:w // + 2 * v5 mac (16) wSOBEL_X(0)<1> r[a0.0,68]<16;16,1>:ub 2:w // - 2 * v3 mul (16) acc0.0<1>:w r[a0.0,96]<16;16,1>:ub -2:w // + v8 mac (16) acc0.0<1>:w r[a0.0,164]<16;16,1>:ub 1:w // - v0 mac (16) acc0.0<1>:w r[a0.0,32]<16;16,1>:ub -1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,160]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,36]<16;16,1>:ub 1:w // + 2 * v5 mac (16) wSOBEL_X(1)<1> r[a0.0,100]<16;16,1>:ub 2:w // - 2 * v3 mul (16) acc0.0<1>:w r[a0.0,128]<16;16,1>:ub -2:w // + v8 mac (16) acc0.0<1>:w r[a0.0,196]<16;16,1>:ub 1:w // - v0 mac (16) acc0.0<1>:w r[a0.0,64]<16;16,1>:ub -1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,192]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,68]<16;16,1>:ub 1:w // + 2 * v5 mac (16) wSOBEL_X(2)<1> r[a0.0,132]<16;16,1>:ub 2:w // - 2 * v3 mul (16) acc0.0<1>:w r[a0.0,160]<16;16,1>:ub -2:w // + v8 mac (16) acc0.0<1>:w r[a0.0,228]<16;16,1>:ub 1:w // - v0 mac (16) acc0.0<1>:w r[a0.0,96]<16;16,1>:ub -1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,224]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,100]<16;16,1>:ub 1:w // + 2 * v5 mac (16) wSOBEL_X(3)<1> r[a0.0,164]<16;16,1>:ub 2:w // + 2 * v1 mul (16) acc0.0<1>:w r[a0.0,2]<16;16,1>:ub 2:w // + v0 mac (16) acc0.0<1>:w r[a0.0,0]<16;16,1>:ub 1:w // - v8 mac (16) acc0.0<1>:w r[a0.0,132]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,4]<16;16,1>:ub 1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,128]<16;16,1>:ub -1:w // - 2 * v7 mac (16) acc0.0<1>:w r[a0.0,130]<16;16,1>:ub -2:w add (16) acc0.0<1>:uw (abs)acc0.0<16;16,1>:w (abs)wSOBEL_X(0)<16;16,1> shr (16) uwSOBEL(0)<1> acc0.0<16;16,1>:uw 3:uw // + 2 * v1 mul (16) acc0.0<1>:w r[a0.0,34]<16;16,1>:ub 2:w // + v0 mac (16) acc0.0<1>:w r[a0.0,32]<16;16,1>:ub 1:w // - v8 mac (16) acc0.0<1>:w r[a0.0,164]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,36]<16;16,1>:ub 1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,160]<16;16,1>:ub -1:w // - 2 * v7 mac (16) acc0.0<1>:w r[a0.0,162]<16;16,1>:ub -2:w add (16) acc0.0<1>:uw (abs)acc0.0<16;16,1>:w (abs)wSOBEL_X(1)<16;16,1> shr (16) uwSOBEL(1)<1> acc0.0<16;16,1>:uw 3:uw // + 2 * v1 mul (16) acc0.0<1>:w r[a0.0,66]<16;16,1>:ub 2:w // + v0 mac (16) acc0.0<1>:w r[a0.0,64]<16;16,1>:ub 1:w // - v8 mac (16) acc0.0<1>:w r[a0.0,196]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,68]<16;16,1>:ub 1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,192]<16;16,1>:ub -1:w // - 2 * v7 mac (16) acc0.0<1>:w r[a0.0,194]<16;16,1>:ub -2:w add (16) acc0.0<1>:uw (abs)acc0.0<16;16,1>:w (abs)wSOBEL_X(2)<16;16,1> shr (16) uwSOBEL(2)<1> acc0.0<16;16,1>:uw 3:uw // + 2 * v1 mul (16) acc0.0<1>:w r[a0.0,98]<16;16,1>:ub 2:w // + v0 mac (16) acc0.0<1>:w r[a0.0,96]<16;16,1>:ub 1:w // - v8 mac (16) acc0.0<1>:w r[a0.0,228]<16;16,1>:ub -1:w // + v2 mac (16) acc0.0<1>:w r[a0.0,100]<16;16,1>:ub 1:w // - v6 mac (16) acc0.0<1>:w r[a0.0,224]<16;16,1>:ub -1:w // - 2 * v7 mac (16) acc0.0<1>:w r[a0.0,226]<16;16,1>:ub -2:w add (16) acc0.0<1>:uw (abs)acc0.0<16;16,1>:w (abs)wSOBEL_X(3)<16;16,1> shr (16) uwSOBEL(3)<1> acc0.0<16;16,1>:uw 3:uw //Mov Median in CURBE_TEMP to free up temp space. mov (16) ubMEDIAN(0,0)<1> ubMEDIAN_TEMP(4,0)<16;16,1> mov (16) ubMEDIAN(0,16)<1> ubMEDIAN_TEMP(4,16)<16;16,1> mov (16) ubMEDIAN(0,32)<1> ubMEDIAN_TEMP(13,0)<16;16,1> mov (16) ubMEDIAN(0,48)<1> ubMEDIAN_TEMP(13,16)<16;16,1> // Find: // absDiff = abs(ubCurY - ubMedian) // Find the difference between pixel and median value. //Median is interleaved. So difference is also interleaved. //------------------------------------------------------------------------------------------ //Process 16 U and 16 V pixels here and rest later. // first row - v0,v1,v2 add (16) wDIFF(0)<1> r[a0.0,0]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(1)<1> r[a0.0,2]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(2)<1> r[a0.0,4]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> // second row - v3,v4,v5 add (16) wDIFF(3)<1> r[a0.0,64]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(4)<1> r[a0.0,66]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(5)<1> r[a0.0,68]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> // third row - v6,v7,v8 add (16) wDIFF(6)<1> r[a0.0,128]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(7)<1> r[a0.0,130]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> add (16) wDIFF(8)<1> r[a0.0,132]<16;16,1>:ub -ubMEDIAN(0,0)<16;16,1> // first row - v0,v1,v2 add (16) wDIFF(9)<1> r[a0.0,32]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(10)<1> r[a0.0,34]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(11)<1> r[a0.0,36]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> // second row - v3,v4,v5 add (16) wDIFF(12)<1> r[a0.0,96]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(13)<1> r[a0.0,98]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(14)<1> r[a0.0,100]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> // third row - v6,v7,v8 add (16) wDIFF(15)<1> r[a0.0,160]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(16)<1> r[a0.0,162]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> add (16) wDIFF(17)<1> r[a0.0,164]<16;16,1>:ub -ubMEDIAN(0,16)<16;16,1> //TODO - Change Later - rT add (1) a0.0:uw a0.0<0;1,0>:uw 64:uw // Find sum of all absolute differences AND // maximum absolute difference for 16 U and 16 V here. //First 2 rows of 8x4 //Compare 0-1, 2-3, 4-5, 6-7 cmp.g.f0.0 (16) null:uw (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> cmp.g.f0.1 (16) null:uw (abs)wDIFF(2)<16;16,1> (abs)wDIFF(3)<16;16,1> cmp.g.f1.0 (16) null:uw (abs)wDIFF(4)<16;16,1> (abs)wDIFF(5)<16;16,1> cmp.g.f1.1 (16) null:uw (abs)wDIFF(6)<16;16,1> (abs)wDIFF(7)<16;16,1> //Calculate SAD add (16) acc0.0<1>:uw (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(2)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(3)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(4)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(5)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(6)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(7)<16;16,1> add (16) uwSOAD(0)<1> acc0.0<16;16,1>:uw (abs)wDIFF(8)<16;16,1> (f0.0) sel (16) uwCURBE_TEMP(0)<1> (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> (f0.1) sel (16) uwCURBE_TEMP(1)<1> (abs)wDIFF(2)<16;16,1> (abs)wDIFF(3)<16;16,1> (f1.0) sel (16) uwCURBE_TEMP(2)<1> (abs)wDIFF(4)<16;16,1> (abs)wDIFF(5)<16;16,1> (f1.1) sel (16) uwCURBE_TEMP(3)<1> (abs)wDIFF(6)<16;16,1> (abs)wDIFF(7)<16;16,1> //------------ //DIFF(0-7) is not needed here. Populate it. // first row - v0,v1,v2 add (16) wDIFF(0)<1> r[a0.0,0]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(1)<1> r[a0.0,2]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(2)<1> r[a0.0,4]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> // second row - v3,v4,v5 add (16) wDIFF(3)<1> r[a0.0,64]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(4)<1> r[a0.0,66]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(5)<1> r[a0.0,68]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> // third row - v6,v7 add (16) wDIFF(6)<1> r[a0.0,128]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> add (16) wDIFF(7)<1> r[a0.0,130]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> //------------ //Compare Max(0,1) - Max(2,3), Max(4,5) - Max(6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> cmp.g.f0.1 (16) null:uw uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> (f0.1)sel (16) uwCURBE_TEMP(2)<1> uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> //Compare Max(0,1,2,3) - Max(4,5,6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> //Compare Max(0,1,2,3,4,5,6,7) - 8 cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(8)<16;16,1> (f0.0)sel (16) uwMAX_ABS_DIFF(0)<1> uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(8)<16;16,1> //------------ //Load v8 - DIFF(8) add (16) wDIFF(8)<1> r[a0.0,132]<16;16,1>:ub -ubMEDIAN(1,0)<16;16,1> //------------ //Compare 0-1, 2-3, 4-5, 6-7 cmp.g.f0.0 (16) null:uw (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> cmp.g.f0.1 (16) null:uw (abs)wDIFF(11)<16;16,1> (abs)wDIFF(12)<16;16,1> cmp.g.f1.0 (16) null:uw (abs)wDIFF(13)<16;16,1> (abs)wDIFF(14)<16;16,1> cmp.g.f1.1 (16) null:uw (abs)wDIFF(15)<16;16,1> (abs)wDIFF(16)<16;16,1> //Calculate SAD add (16) acc0.0<1>:uw (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(11)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(12)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(13)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(14)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(15)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(16)<16;16,1> add (16) uwSOAD(1)<1> acc0.0<16;16,1>:uw (abs)wDIFF(17)<16;16,1> (f0.0) sel (16) uwCURBE_TEMP(0)<1> (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> (f0.1) sel (16) uwCURBE_TEMP(1)<1> (abs)wDIFF(11)<16;16,1> (abs)wDIFF(12)<16;16,1> (f1.0) sel (16) uwCURBE_TEMP(2)<1> (abs)wDIFF(13)<16;16,1> (abs)wDIFF(14)<16;16,1> (f1.1) sel (16) uwCURBE_TEMP(3)<1> (abs)wDIFF(15)<16;16,1> (abs)wDIFF(16)<16;16,1> //------------ //DIFF(0-7) is not needed here. Populate it. // first row - v0,v1,v2 add (16) wDIFF(9)<1> r[a0.0,32]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(10)<1> r[a0.0,34]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(11)<1> r[a0.0,36]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> // second row - v3,v4,v5 add (16) wDIFF(12)<1> r[a0.0,96]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(13)<1> r[a0.0,98]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(14)<1> r[a0.0,100]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> // third row - v6,v7 add (16) wDIFF(15)<1> r[a0.0,160]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> add (16) wDIFF(16)<1> r[a0.0,162]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> //------------ //Compare Max(0,1) - Max(2,3), Max(4,5) - Max(6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> cmp.g.f0.1 (16) null:uw uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> (f0.1)sel (16) uwCURBE_TEMP(2)<1> uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> //Compare Max(0,1,2,3) - Max(4,5,6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> //Compare Max(0,1,2,3,4,5,6,7) - 8 cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(17)<16;16,1> (f0.0)sel (16) uwMAX_ABS_DIFF(1)<1> uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(17)<16;16,1> //------------ //Load v8 - DIFF(8) add (16) wDIFF(17)<1> r[a0.0,164]<16;16,1>:ub -ubMEDIAN(1,16)<16;16,1> //------------ //if ((sobel_edge_measure < m_SobelEdgeThreshold) && ((block_max-block_min) < m_LocalDiffThreshold)) // if (sigma_mb_min > sigma) // sigma_mb_min = sigma; //NOTE: block_min is always zero as median is one of the value in 3x3 block. So no need o calculate it. // So just do - //if ((sobel_edge_measure < m_SobelEdgeThreshold) && ((block_max) < m_LocalDiffThreshold) && ( sigma < sigma_mb_min)) // sigma_mb_min = sigma; //We are processing 32 bytes of U and 32 bytes of V - each of size 8x4. //Compare first 8 bytes with max possible (255). //Start above condition from second 8 bytes. //TODO - Change Later - rT // mov (1) pCUR_MIN_SOAD_8x4:uw 1752:uw //r54.24:ub //First row of 8x4 cmp.l.f0.0 (16) null:uw uwSOBEL(0)<16;16,1> r55.30<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwMAX_ABS_DIFF(0)<16;16,1> r55.28<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwSOAD(0)<16;16,1> 255:uw (f0.0) sel (16) uwSOBEL(0)<1> uwSOAD(0)<16;16,1> 255:uw //Second row of 8x4 cmp.l.f0.0 (16) null:uw uwSOBEL(1)<16;16,1> r55.30<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwMAX_ABS_DIFF(1)<16;16,1> r55.28<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwSOAD(1)<16;16,1> uwSOBEL(0)<16;16,1> (f0.0) mov (16) uwSOBEL(0)<1> uwSOAD(1)<16;16,1> // Find sum of all absolute differences AND // maximum absolute difference for 16 U and 16 V here. //Second 2 rows of 8x4 //Compare 0-1, 2-3, 4-5, 6-7 cmp.g.f0.0 (16) null:uw (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> cmp.g.f0.1 (16) null:uw (abs)wDIFF(2)<16;16,1> (abs)wDIFF(3)<16;16,1> cmp.g.f1.0 (16) null:uw (abs)wDIFF(4)<16;16,1> (abs)wDIFF(5)<16;16,1> cmp.g.f1.1 (16) null:uw (abs)wDIFF(6)<16;16,1> (abs)wDIFF(7)<16;16,1> //Calculate SAD add (16) acc0.0<1>:uw (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(2)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(3)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(4)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(5)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(6)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(7)<16;16,1> add (16) uwSOAD(0)<1> acc0.0<16;16,1>:uw (abs)wDIFF(8)<16;16,1> (f0.0) sel (16) uwCURBE_TEMP(0)<1> (abs)wDIFF(0)<16;16,1> (abs)wDIFF(1)<16;16,1> (f0.1) sel (16) uwCURBE_TEMP(1)<1> (abs)wDIFF(2)<16;16,1> (abs)wDIFF(3)<16;16,1> (f1.0) sel (16) uwCURBE_TEMP(2)<1> (abs)wDIFF(4)<16;16,1> (abs)wDIFF(5)<16;16,1> (f1.1) sel (16) uwCURBE_TEMP(3)<1> (abs)wDIFF(6)<16;16,1> (abs)wDIFF(7)<16;16,1> //Compare Max(0,1) - Max(2,3), Max(4,5) - Max(6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> cmp.g.f0.1 (16) null:uw uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> (f0.1)sel (16) uwCURBE_TEMP(2)<1> uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> //Compare Max(0,1,2,3) - Max(4,5,6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> //Compare Max(0,1,2,3,4,5,6,7) - 8 cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(8)<16;16,1> (f0.0)sel (16) uwMAX_ABS_DIFF(0)<1> uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(8)<16;16,1> //Compare 0-1, 2-3, 4-5, 6-7 cmp.g.f0.0 (16) null:uw (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> cmp.g.f0.1 (16) null:uw (abs)wDIFF(11)<16;16,1> (abs)wDIFF(12)<16;16,1> cmp.g.f1.0 (16) null:uw (abs)wDIFF(13)<16;16,1> (abs)wDIFF(14)<16;16,1> cmp.g.f1.1 (16) null:uw (abs)wDIFF(15)<16;16,1> (abs)wDIFF(16)<16;16,1> //Calculate SAD add (16) acc0.0<1>:uw (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(11)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(12)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(13)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(14)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(15)<16;16,1> add (16) acc0.0<1>:uw acc0.0<16;16,1>:uw (abs)wDIFF(16)<16;16,1> add (16) uwSOAD(1)<1> acc0.0<16;16,1>:uw (abs)wDIFF(17)<16;16,1> (f0.0) sel (16) uwCURBE_TEMP(0)<1> (abs)wDIFF(9)<16;16,1> (abs)wDIFF(10)<16;16,1> (f0.1) sel (16) uwCURBE_TEMP(1)<1> (abs)wDIFF(11)<16;16,1> (abs)wDIFF(12)<16;16,1> (f1.0) sel (16) uwCURBE_TEMP(2)<1> (abs)wDIFF(13)<16;16,1> (abs)wDIFF(14)<16;16,1> (f1.1) sel (16) uwCURBE_TEMP(3)<1> (abs)wDIFF(15)<16;16,1> (abs)wDIFF(16)<16;16,1> //Compare Max(0,1) - Max(2,3), Max(4,5) - Max(6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> cmp.g.f0.1 (16) null:uw uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(1)<16;16,1> (f0.1)sel (16) uwCURBE_TEMP(2)<1> uwCURBE_TEMP(2)<16;16,1> uwCURBE_TEMP(3)<16;16,1> //Compare Max(0,1,2,3) - Max(4,5,6,7) cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> (f0.0)sel (16) uwCURBE_TEMP(0)<1> uwCURBE_TEMP(0)<16;16,1> uwCURBE_TEMP(2)<16;16,1> //Compare Max(0,1,2,3,4,5,6,7) - 8 cmp.g.f0.0 (16) null:uw uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(17)<16;16,1> (f0.0)sel (16) uwMAX_ABS_DIFF(1)<1> uwCURBE_TEMP(0)<16;16,1> (abs)wDIFF(17)<16;16,1> //Third row of 8x4 cmp.l.f0.0 (16) null:uw uwSOBEL(2)<16;16,1> r55.30<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwMAX_ABS_DIFF(0)<16;16,1> r55.28<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwSOAD(0)<16;16,1> uwSOBEL(0)<16;16,1> (f0.0) mov (16) uwSOBEL(0)<1> uwSOAD(0)<16;16,1> //Fourth row of 8x4 cmp.l.f0.0 (16) null:uw uwSOBEL(3)<16;16,1> r55.30<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwMAX_ABS_DIFF(1)<16;16,1> r55.28<0;2,1>:ub (f0.0) cmp.l.f0.0 (16) null:uw uwSOAD(1)<16;16,1> uwSOBEL(0)<16;16,1> (f0.0) mov (16) uwSOBEL(0)<1> uwSOAD(1)<16;16,1> cmp.l.f0.0 (8) null:uw uwSOBEL(0,0)<8;8,1> uwSOBEL(0,8)<8;8,1> (f0.0) sel (8) uwSOBEL(0)<1> uwSOBEL(0,0)<8;8,1> uwSOBEL(0,8)<8;8,1> cmp.l.f0.0 (4) null:uw uwSOBEL(0,0)<4;4,1> uwSOBEL(0,4)<4;4,1> (f0.0) sel (4) uwSOBEL(0)<1> uwSOBEL(0,0)<4;4,1> uwSOBEL(0,4)<4;4,1> cmp.l.f0.0 (2) null:uw uwSOBEL(0,0)<2;2,1> uwSOBEL(0,2)<2;2,1> (f0.0) sel (2) r[a0.1,0]<1>:uw uwSOBEL(0,0)<2;2,1> uwSOBEL(0,2)<2;2,1> // End of common.inc mov (1) ip:ud r7.7<0;1,0>:d .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PL3_DN_422CP.g4a000066400000000000000000000574731231401140700246170ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 117 // Total instruction count // 1 // Total kernel count .kernel PL3_DN_422CP .code // FileName: DN_PL_Core.asm // Author: Vivek Kumar // Description: Tasks for DN only case (16x8 block) for planar format // FileName: DN.asm // Author: Vivek Kumar // Description: Tasks for DN only case (16x8 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x45E8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(4,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DN_Hist_Save.asm // Author: Vivek Kumar // Description: Saves DN history data to statistics surface // Write denoise history to memory mov (8) r27<1>:ud r0.0<8;8,1>:ud // message header mov (2) mudMSGHDR_HIST(1)<1> udDNDI_RESP(4,0)<2;2,1> // Move denoise history to MRF (4x2) shr (2) r27.0<1>:ud r7.0<2;2,1>:w 2:w // X,Y origin / 4 add (1) r27.0<1>:ud r27.0<0;1,0>:ud r1.12<0;1,0>:uw { NoDDClr } // Add pitch to X origin mov (1) r27.2<1>:ud 0x10003:ud { NoDDChk } // block width and height mov (8) mudMSGHDR_HIST(0)<1> r27.0<8;8,1>:ud send (8) null<1>:d r22 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x50003:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | X | X | X | X | //---------------------------------------------------- //| X | SVCM | X | //---------------------------------------------------- //| SHCM | STAD | X | //---------------------------------------------------- //| X | X | //---------------------------------------------------- //| X | SVCM | X | //---------------------------------------------------- //| SHCM | STAD | X | //---------------------------------------------------- mov (1) mubMSGHDR_ENC_STATS(1,0)<1> ubDNDI_RESP(4,8)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (1) muwMSGHDR_ENC_STATS(1,3)<1> uwDNDI_RESP(4,11)<0;1,0> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) muwMSGHDR_ENC_STATS(1,4)<1> uwDNDI_RESP(4,12)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (1) muwMSGHDR_ENC_STATS(1,9)<1> uwDNDI_RESP(4,8)<0;1,0> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) muwMSGHDR_ENC_STATS(1,10)<1> uwDNDI_RESP(4,9)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DN_Load_UV_IMC3_16x8.asm // Author: Vivek Kumar // Description: Read UV for 16x8 block through DATAPORT // FileName: UVCopy_Load_16x8.asm // Author: Vivek Kumar // Description: Read UV for 16x8 block through DATAPORT //CHANGE : Read extra UV data to convert to 422. -rT //we are reading extra data in ALL cases irrespective of whether upsampling is reqd or not later on, to keep things simple. add (2) r27.0<1>:d r7.0<2;2,1>:w r4.4<2;2,1>:w // Source Y Block origin asr (2) r27.0<1>:d r27.0<2;2,1>:d 1:w { NoDDClr } // U/V block origin should be half of Y's mov (1) r27.2<1>:ud 0x40007:ud { NoDDChk } // U/V block width and height (8x5) mov (8) r36<1>:ud r27.0<8;8,1>:ud mov (8) r38<1>:ud r27.0<8;8,1>:ud send (8) udDNDI_UV_RESP(0)<1> r36 0x4 0x2290001:ud send (8) udDNDI_UV_RESP(2)<1> r38 0x4 0x2290002:ud //Update Header for Save mov (1) mudMSGHDR_UCOPY(0,2)<1> 0x30007:ud // U block width and height (8x4) mov (1) mudMSGHDR_VCOPY(0,2)<1> 0x30007:ud // V block width and height (8x4) // FileName: DN_Save_Y_16x8.asm // Author: Vivek Kumar // Description: Save one 16x8 blocks of Y channel of DN output for reference mov (8) mudDN_Y_OUT(0,0)<1> r0<8;8,1>:ud // message header mov (2) mudDN_Y_OUT(0,0)<1> r7.0<2;2,1>:w { NoDDClr } // X origin mov (1) mudDN_Y_OUT(0,2)<1> 0x7000F:ud { NoDDChk } // block width and height (16x8) //send out data through data port send (8) null<1>:d mudDN_Y_OUT 0x5 0xA0A8018:ud // FileName: DN_Save_UV_IMC3_16x8.asm // Author: Vivek Kumar // Description: Save UV for 16x8 block through DATAPORT // FileName: UVCopy_Save_16x8.asm // Author: Vivek Kumar // Description: Save UV for 16x8 block through DATAPORT //Reuse the header from Load component //Header is modified at the end of load - to be usable for save. mov (8) mudMSGHDR_UCOPY(1)<1> udDNDI_UV_RESP(0)<8;8,1> mov (8) mudMSGHDR_VCOPY(1)<1> udDNDI_UV_RESP(2)<8;8,1> send (4) null<1>:d r36 0x5 0x40A8019:ud send (4) null<1>:d r38 0x5 0x40A801A:ud // FileName: DN_Upsample_UV_IMC3_16x8.asm // Author: Tatiya, Rupesh // Description: Upconvert 420 UV to 422 // FileName: UVCopy_Upsample_UV_16x8.asm // Author: Tatiya, Rupesh // Description: Convert 42X UV to 422 - to be used for IECP. avg.sat (16) uwDNDI_UVCOPY_TEMP(0) ubDNDI_UV_RESP(0,0)<0;8,1> ubDNDI_UV_RESP(0,0)<8;8,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(4) ubDNDI_UV_RESP(2,0)<0;8,1> ubDNDI_UV_RESP(2,0)<8;8,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(1) ubDNDI_UV_RESP(0,8)<0;8,1> ubDNDI_UV_RESP(0,8)<8;8,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(5) ubDNDI_UV_RESP(2,8)<0;8,1> ubDNDI_UV_RESP(2,8)<8;8,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(2) ubDNDI_UV_RESP(0,16)<0;8,1> ubDNDI_UV_RESP(0,16)<8;8,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(6) ubDNDI_UV_RESP(2,16)<0;8,1> ubDNDI_UV_RESP(2,16)<8;8,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(3) ubDNDI_UV_RESP(0,24)<0;8,1> ubDNDI_UV_RESP(0,24)<8;8,1> avg.sat (16) uwDNDI_UVCOPY_TEMP(7) ubDNDI_UV_RESP(2,24)<0;8,1> ubDNDI_UV_RESP(2,24)<8;8,1> mov (16) ubDNDI_RESP(5, 1)<2> ubDNDI_UVCOPY_TEMP(0,0)<32;16,2> { NoDDClr } mov (16) ubDNDI_RESP(5, 0)<2> ubDNDI_UVCOPY_TEMP(4,0)<32;16,2> { NoDDChk } mov (16) ubDNDI_RESP(5, 33)<2> ubDNDI_UVCOPY_TEMP(1,0)<32;16,2> { NoDDClr } mov (16) ubDNDI_RESP(5, 32)<2> ubDNDI_UVCOPY_TEMP(5,0)<32;16,2> { NoDDChk } mov (16) ubDNDI_RESP(5, 65)<2> ubDNDI_UVCOPY_TEMP(2,0)<32;16,2> { NoDDClr } mov (16) ubDNDI_RESP(5, 64)<2> ubDNDI_UVCOPY_TEMP(6,0)<32;16,2> { NoDDChk } mov (16) ubDNDI_RESP(5, 97)<2> ubDNDI_UVCOPY_TEMP(3,0)<32;16,2> { NoDDClr } mov (16) ubDNDI_RESP(5, 96)<2> ubDNDI_UVCOPY_TEMP(7,0)<32;16,2> { NoDDChk } // FileName: DN_Save_422CP_16x8.asm // Author: Vivek Kumar // Description: Save one 16x8 blocks of DN output to the color pipe in 4-2-2 format .declare mubMSGHDR_DN_OUT_2 Base=r36.0 ElementSize=1 Type=ub mov (8) mudMSGHDR_DN_OUT(0)<1> r0<8;8,1>:ud // message header shl (1) mdMSGHDR_DN_OUT(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin * 2 (422 output) mov (1) mdMSGHDR_DN_OUT(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_DN_OUT(0,2)<1> 0x7000F:ud { NoDDClr, NoDDChk } // block width and height (16x8) //M0.3 - 0 - CP Enable, 1 - Area of Interest, 3:2 Message Format(TBD), 4:3 - Ignored, 31:5 CP state pointer //Compose area-of-interest bit + color pipe state pointer or (1) mudMSGHDR_DN_OUT(0,3)<1> r2.4<0;1,0>:ud r7.26<0;1,0>:b { NoDDChk } // First 8 x 8 Block mov (8) mubMSGHDR_DN_OUT(1)<2> ubDNDI_RESP(0,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(1,16)<2> ubDNDI_RESP(0,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(2)<2> ubDNDI_RESP(0,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(2,16)<2> ubDNDI_RESP(0,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(3)<2> ubDNDI_RESP(0,64)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(3,16)<2> ubDNDI_RESP(0,80)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(4)<2> ubDNDI_RESP(0,96)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT(4,16)<2> ubDNDI_RESP(0,112)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(1,1)<4> ubDNDI_RESP(5,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(1,17)<4> ubDNDI_RESP(5,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(1,3)<4> ubDNDI_RESP(5,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(1,19)<4> ubDNDI_RESP(5,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(2,1)<4> ubDNDI_RESP(5,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(2,17)<4> ubDNDI_RESP(5,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(2,3)<4> ubDNDI_RESP(5,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(2,19)<4> ubDNDI_RESP(5,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(3,1)<4> ubDNDI_RESP(5,65)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(3,17)<4> ubDNDI_RESP(5,81)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(3,3)<4> ubDNDI_RESP(5,64)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(3,19)<4> ubDNDI_RESP(5,80)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(4,1)<4> ubDNDI_RESP(5,97)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(4,17)<4> ubDNDI_RESP(5,113)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(4,3)<4> ubDNDI_RESP(5,96)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT(4,19)<4> ubDNDI_RESP(5,112)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Second 8 x 8 Block mov (8) r36.0<1>:ud r31.0<8;8,1>:ud add (1) r36.0<1>:ud r36.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DN_OUT_2(1)<2> ubDNDI_RESP(0,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(1,16)<2> ubDNDI_RESP(0,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(2)<2> ubDNDI_RESP(0,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(2,16)<2> ubDNDI_RESP(0,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(3)<2> ubDNDI_RESP(0,72)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(3,16)<2> ubDNDI_RESP(0,88)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(4)<2> ubDNDI_RESP(0,104)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DN_OUT_2(4,16)<2> ubDNDI_RESP(0,120)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(1,1)<4> ubDNDI_RESP(5,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(1,17)<4> ubDNDI_RESP(5,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(1,3)<4> ubDNDI_RESP(5,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(1,19)<4> ubDNDI_RESP(5,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(2,1)<4> ubDNDI_RESP(5,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(2,17)<4> ubDNDI_RESP(5,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(2,3)<4> ubDNDI_RESP(5,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(2,19)<4> ubDNDI_RESP(5,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(3,1)<4> ubDNDI_RESP(5,73)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(3,17)<4> ubDNDI_RESP(5,89)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(3,3)<4> ubDNDI_RESP(5,72)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(3,19)<4> ubDNDI_RESP(5,88)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(4,1)<4> ubDNDI_RESP(5,105)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(4,17)<4> ubDNDI_RESP(5,121)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(4,3)<4> ubDNDI_RESP(5,104)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DN_OUT_2(4,19)<4> ubDNDI_RESP(5,120)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization //send out data through data port send (8) null<1>:d r31.0 0x5 0xA0A801B:ud send (8) null<1>:d r36.0 0x5 0xA0A801B:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PL3_DN_PL3.g4a000066400000000000000000000351071231401140700244510ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 44 // Total instruction count // 1 // Total kernel count .kernel PL3_DN_PL3 .code // FileName: DN_PL_Core.asm // Author: Vivek Kumar // Description: Tasks for DN only case (16x8 block) for planar format // FileName: DN.asm // Author: Vivek Kumar // Description: Tasks for DN only case (16x8 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x45E8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(4,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DN_Hist_Save.asm // Author: Vivek Kumar // Description: Saves DN history data to statistics surface // Write denoise history to memory mov (8) r27<1>:ud r0.0<8;8,1>:ud // message header mov (2) mudMSGHDR_HIST(1)<1> udDNDI_RESP(4,0)<2;2,1> // Move denoise history to MRF (4x2) shr (2) r27.0<1>:ud r7.0<2;2,1>:w 2:w // X,Y origin / 4 add (1) r27.0<1>:ud r27.0<0;1,0>:ud r1.12<0;1,0>:uw { NoDDClr } // Add pitch to X origin mov (1) r27.2<1>:ud 0x10003:ud { NoDDChk } // block width and height mov (8) mudMSGHDR_HIST(0)<1> r27.0<8;8,1>:ud send (8) null<1>:d r22 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x50003:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | X | X | X | X | //---------------------------------------------------- //| X | SVCM | X | //---------------------------------------------------- //| SHCM | STAD | X | //---------------------------------------------------- //| X | X | //---------------------------------------------------- //| X | SVCM | X | //---------------------------------------------------- //| SHCM | STAD | X | //---------------------------------------------------- mov (1) mubMSGHDR_ENC_STATS(1,0)<1> ubDNDI_RESP(4,8)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (1) muwMSGHDR_ENC_STATS(1,3)<1> uwDNDI_RESP(4,11)<0;1,0> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) muwMSGHDR_ENC_STATS(1,4)<1> uwDNDI_RESP(4,12)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (1) muwMSGHDR_ENC_STATS(1,9)<1> uwDNDI_RESP(4,8)<0;1,0> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) muwMSGHDR_ENC_STATS(1,10)<1> uwDNDI_RESP(4,9)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DN_Load_UV_IMC3_16x8.asm // Author: Vivek Kumar // Description: Read UV for 16x8 block through DATAPORT // FileName: UVCopy_Load_16x8.asm // Author: Vivek Kumar // Description: Read UV for 16x8 block through DATAPORT //CHANGE : Read extra UV data to convert to 422. -rT //we are reading extra data in ALL cases irrespective of whether upsampling is reqd or not later on, to keep things simple. add (2) r27.0<1>:d r7.0<2;2,1>:w r4.4<2;2,1>:w // Source Y Block origin asr (2) r27.0<1>:d r27.0<2;2,1>:d 1:w { NoDDClr } // U/V block origin should be half of Y's mov (1) r27.2<1>:ud 0x40007:ud { NoDDChk } // U/V block width and height (8x5) mov (8) r36<1>:ud r27.0<8;8,1>:ud mov (8) r38<1>:ud r27.0<8;8,1>:ud send (8) udDNDI_UV_RESP(0)<1> r36 0x4 0x2290001:ud send (8) udDNDI_UV_RESP(2)<1> r38 0x4 0x2290002:ud //Update Header for Save mov (1) mudMSGHDR_UCOPY(0,2)<1> 0x30007:ud // U block width and height (8x4) mov (1) mudMSGHDR_VCOPY(0,2)<1> 0x30007:ud // V block width and height (8x4) // FileName: DN_Save_Y_16x8.asm // Author: Vivek Kumar // Description: Save one 16x8 blocks of Y channel of DN output for reference mov (8) mudDN_Y_OUT(0,0)<1> r0<8;8,1>:ud // message header mov (2) mudDN_Y_OUT(0,0)<1> r7.0<2;2,1>:w { NoDDClr } // X origin mov (1) mudDN_Y_OUT(0,2)<1> 0x7000F:ud { NoDDChk } // block width and height (16x8) //send out data through data port send (8) null<1>:d mudDN_Y_OUT 0x5 0xA0A8018:ud // FileName: DN_Save_UV_IMC3_16x8.asm // Author: Vivek Kumar // Description: Save UV for 16x8 block through DATAPORT // FileName: UVCopy_Save_16x8.asm // Author: Vivek Kumar // Description: Save UV for 16x8 block through DATAPORT //Reuse the header from Load component //Header is modified at the end of load - to be usable for save. mov (8) mudMSGHDR_UCOPY(1)<1> udDNDI_UV_RESP(0)<8;8,1> mov (8) mudMSGHDR_VCOPY(1)<1> udDNDI_UV_RESP(2)<8;8,1> send (4) null<1>:d r36 0x5 0x40A8019:ud send (4) null<1>:d r38 0x5 0x40A801A:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PL_DI_422CP.g4a000066400000000000000000000501311231401140700245070ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 87 // Total instruction count // 1 // Total kernel count .kernel PL_DI_422CP .code // FileName: DI.asm // Author: Vivek Kumar // Description: Tasks for DI only case (16x4 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x4AE8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(9,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DI_STMM_Save.asm // Author: Vivek Kumar // Description: Saves DI STMM Data to statistics surface in case of DI enabled (for 16x4 block) // Write STMM to memory mov (8) mudMSGHDR_STMM(0)<1> r0.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udDNDI_RESP(8,0) // Move STMM to MRF shr (1) mudMSGHDR_STMM(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin / 2 mov (1) mudMSGHDR_STMM(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_STMM(0,2)<1> 0x30007:ud { NoDDChk } // block width and height (8x4) send (8) null<1>:d r20 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x20007:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | MCNT | FCNT | TCNT | X | X | X | X | //---------------------------------------------------- //| DcTpT | SVCM | DcBpT | DcTpB | //---------------------------------------------------- //| SHCM | STAD | DcTcB | DcBpB | //---------------------------------------------------- mov (1) mudMSGHDR_ENC_STATS(1,0)<1> udDNDI_RESP(9,1)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,3)<2> udDNDI_RESP(9,3)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,2)<2> udDNDI_RESP(9,5)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DI_Save_422CP_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in 422 format to Color Pipe (IECP) .declare mubMSGHDR_DI_OUT1_1 Base=r18.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT1_2 Base=r21.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT2_1 Base=r24.0 ElementSize=1 Type=ub .declare mubMSGHDR_DI_OUT2_2 Base=r27.0 ElementSize=1 Type=ub mov (8) r27.0<1>:ud r0.0<8;8,1>:ud shl (1) r27.0<1>:ud r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be doubled mov (1) r27.1<1>:ud r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) r27.2<1>:ud 0x3000F:ud { NoDDClr, NoDDChk } // Block width and height (16x8) //M0.3 - 0 - CP Enable, 1 - Area of Interest, 3:2 Message Format(TBD), 4:3 - Ignored, 31:5 CP state pointer //Compose area-of-interest bit + color pipe state pointer or (1) r27.3<1>:ud r2.4<0;1,0>:ud r7.26<0;1,0>:b { NoDDChk } //prepare the message headers mov (8) r18.0<1>:ud r27<8;8,1>:ud mov (8) r24.0<1>:ud r27<8;8,1>:ud // Pack 2nd field Y; First 8x4 block mov (8) mubMSGHDR_DI_OUT1_1(1)<2> ubDNDI_RESP(0,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(1,16)<2> ubDNDI_RESP(0,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(2)<2> ubDNDI_RESP(0,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_1(2,16)<2> ubDNDI_RESP(0,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 2nd field U, V; First 8x4 block mov (4) mubMSGHDR_DI_OUT1_1(1,1)<4> ubDNDI_RESP(2,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,17)<4> ubDNDI_RESP(2,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,3)<4> ubDNDI_RESP(2,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(1,19)<4> ubDNDI_RESP(2,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,1)<4> ubDNDI_RESP(2,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,17)<4> ubDNDI_RESP(2,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,3)<4> ubDNDI_RESP(2,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_1(2,19)<4> ubDNDI_RESP(2,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Pack 2nd field Y; Second 8x4 block mov (8) r21.0<1>:ud r18.0<8;8,1>:ud add (1) r21.0<1>:ud r21.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DI_OUT1_2(1)<2> ubDNDI_RESP(0,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(1,16)<2> ubDNDI_RESP(0,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(2)<2> ubDNDI_RESP(0,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT1_2(2,16)<2> ubDNDI_RESP(0,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 2nd field U, V; Second 8x4 block mov (4) mubMSGHDR_DI_OUT1_2(1,1)<4> ubDNDI_RESP(2,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,17)<4> ubDNDI_RESP(2,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,3)<4> ubDNDI_RESP(2,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(1,19)<4> ubDNDI_RESP(2,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,1)<4> ubDNDI_RESP(2,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,17)<4> ubDNDI_RESP(2,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,3)<4> ubDNDI_RESP(2,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT1_2(2,19)<4> ubDNDI_RESP(2,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization send (8) null<1>:d r18.0 0x5 0x60A801B:ud send (8) null<1>:d r21.0 0x5 0x60A801B:ud // Pack 1st field Y; 1st 8x4 block mov (8) mubMSGHDR_DI_OUT2_1(1)<2> ubDNDI_RESP(4,0)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(1,16)<2> ubDNDI_RESP(4,16)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(2)<2> ubDNDI_RESP(4,32)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_1(2,16)<2> ubDNDI_RESP(4,48)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 1st field U,V; 1st 8x4 block mov (4) mubMSGHDR_DI_OUT2_1(1,1)<4> ubDNDI_RESP(6,1)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,17)<4> ubDNDI_RESP(6,17)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,3)<4> ubDNDI_RESP(6,0)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(1,19)<4> ubDNDI_RESP(6,16)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,1)<4> ubDNDI_RESP(6,33)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,17)<4> ubDNDI_RESP(6,49)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,3)<4> ubDNDI_RESP(6,32)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_1(2,19)<4> ubDNDI_RESP(6,48)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization // Pack 1st field Y; 2nd 8x4 block mov (8) r27.0<1>:ud r24.0<8;8,1>:ud add (1) r27.0<1>:ud r27.0<0;1,0>:w 0x10:w mov (8) mubMSGHDR_DI_OUT2_2(1)<2> ubDNDI_RESP(4,8)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(1,16)<2> ubDNDI_RESP(4,24)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(2)<2> ubDNDI_RESP(4,40)<8;8,1> { NoDDClr } // copy line of Y directly to memory as optimization mov (8) mubMSGHDR_DI_OUT2_2(2,16)<2> ubDNDI_RESP(4,56)<8;8,1> { NoDDClr, NoDDChk } // copy line of Y directly to memory as optimization // Pack 1st field U, V; 2nd 8x4 block mov (4) mubMSGHDR_DI_OUT2_2(1,1)<4> ubDNDI_RESP(6,9)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,17)<4> ubDNDI_RESP(6,25)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,3)<4> ubDNDI_RESP(6,8)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(1,19)<4> ubDNDI_RESP(6,24)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,1)<4> ubDNDI_RESP(6,41)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,17)<4> ubDNDI_RESP(6,57)<8;4,2> { NoDDClr, NoDDChk } // copy line of U directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,3)<4> ubDNDI_RESP(6,40)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization mov (4) mubMSGHDR_DI_OUT2_2(2,19)<4> ubDNDI_RESP(6,56)<8;4,2> { NoDDChk } // copy line of V directly to memory as optimization send (8) null<1>:d r24.0 0x5 0x60A801E:ud send (8) null<1>:d r27.0 0x5 0x60A801E:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/PL_DI_PA.g4a000066400000000000000000000354061231401140700242650ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 57 // Total instruction count // 1 // Total kernel count .kernel PL_DI_PA .code // FileName: DI.asm // Author: Vivek Kumar // Description: Tasks for DI only case (16x4 block) // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: DNDI.inc // Author: Vivek Kumar // Description: Include file for DN, DI and DNDI // Inputs: DI_ENABLE, DN_ENABLE, DN_PLANAR, DN_PACKED // End of common.inc //Interface: //Static Parameters: //r1 //====================== Binding table (Explicit To DNDI)========================================= .declare mudMSGHDR_DNDI Base=r18 ElementSize=4 Type=ud .declare mdMSGHDR_DNDI Base=r18 ElementSize=4 Type=d .declare mwMSGHDR_DNDI Base=r18 ElementSize=2 Type=w .declare mudMSGHDR_STMM Base=r20 ElementSize=4 Type=ud .declare mudMSGHDR_HIST Base=r22 ElementSize=4 Type=ud .declare mudMSGHDR_ENC_STATS Base=r24 ElementSize=4 Type=ud .declare muwMSGHDR_ENC_STATS Base=r24 ElementSize=2 Type=uw .declare mubMSGHDR_ENC_STATS Base=r24 ElementSize=1 Type=ub .declare mudMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=ud .declare mdMSGHDR_DN_OUT Base=r31.0 ElementSize=4 Type=d .declare mubMSGHDR_DN_OUT Base=r31.0 ElementSize=1 Type=ub .declare mudMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=ud .declare mdMSGHDR_UVCOPY Base=r36 ElementSize=4 Type=d .declare mudMSGHDR_UCOPY Base=r36 ElementSize=4 Type=ud .declare mudMSGHDR_VCOPY Base=r38 ElementSize=4 Type=ud .declare mudMSGHDR_DI_OUT1 Base=r18.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT1 Base=r18.0 ElementSize=1 Type=ub .declare mudMSGHDR_DI_OUT2 Base=r23.0 ElementSize=4 Type=ud .declare mubMSGHDR_DI_OUT2 Base=r23.0 ElementSize=1 Type=ub //r45 //Use r45 as message header, so no need to "mov" the data. .declare mudDN_Y_OUT Base=r45.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud // Message response (Denoised & DI-ed pixels & statistics); Use buffer 5 .declare udDNDI_RESP Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwDNDI_RESP Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubDNDI_RESP Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub // Message response (UV Copy); Use buffer 5 .declare udDNDI_UV_RESP Base=r58.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ubDNDI_UV_RESP Base=r58.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Temp GRFs: For 42X to 422 Conversion .declare uwDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //8 GRFs .declare ubDNDI_UVCOPY_TEMP Base=r10.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //8 GRFs //--------------------------------------------------------------------------- // Message descriptors //--------------------------------------------------------------------------- // Extended message descriptor // Message descriptor for sampler read // = 000 0010 (message len 2) 00000 (resp len - set later, 12 or 5 or 11) // 1 (header present 1) 0 11 (SIMD32/64 mode) // 1000 (message type) 0000 (DI state index) // 00000000 (binding table index - set later) // = 0x040b8000 // Attention: The Message Length is The Number of GRFs with Data Only, without the Header //--------------------------------------------------------------------------- // VDI Return Data format //--------------------------------------------------------------------------- // Defines for DI enabled // Defines for DI disabled // FileName: DNDI_Command.asm // Author: Vivek Kumar // Description: Sends a message to the VDI to process one DN (16x8) or DNDI (16x4) block // Prepare the DNDI send command mov (8) mudMSGHDR_DNDI(0)<1> r0.0<8;8,1>:ud // message header mov (1) mwMSGHDR_DNDI(1,4)<1> r7.0<0;1,0>:w { NoDDClr } // horizontal origin // Do we need to add offset here? -vK mov (1) mwMSGHDR_DNDI(1,12)<1> r7.1<0;1,0>:w { NoDDChk } // vertical origin // Can these 2 be combined? - vK send (8) udDNDI_RESP(0)<1> r18 0x2 0x4AE8003:ud // On Gen6, with VDI walker, use the XY pair returned rather than programmed above // VDI_RETURNED_XY is ordered XY in case of walker enables and the same as programmed in case of walker disabled mov (2) r7.0<1>:w uwDNDI_RESP(9,14)<2;2,1> // horizontal/Vertial origin in W.14 and W.15 // FileName: DI_STMM_Save.asm // Author: Vivek Kumar // Description: Saves DI STMM Data to statistics surface in case of DI enabled (for 16x4 block) // Write STMM to memory mov (8) mudMSGHDR_STMM(0)<1> r0.0<8;8,1>:ud // message header mov (8) mudMSGHDR_STMM(1)<1> udDNDI_RESP(8,0) // Move STMM to MRF shr (1) mudMSGHDR_STMM(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } // X origin / 2 mov (1) mudMSGHDR_STMM(0,1)<1> r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Y origin mov (1) mudMSGHDR_STMM(0,2)<1> 0x30007:ud { NoDDChk } // block width and height (8x4) send (8) null<1>:d r20 0x5 0x40A8021:ud // FileName: DNDI_Enc_Stats_Save.asm // Author: Vivek Kumar // Description: Saves Encoder Statistics data to statistics surface in case of DI enabled (for 16x4 block) // Write encoder statistics to memory //Currently enable this only on Gen6 validation mov (8) mudMSGHDR_ENC_STATS(1)<1> 0x0:ud // Init payload MRF mov (8) mudMSGHDR_ENC_STATS(0)<1> r0.0<8;8,1>:ud // message header shr (1) mudMSGHDR_ENC_STATS(0,0)<1> r7.0<0;1,0>:w 1:w { NoDDClr } //enable the flag after testing on si { NoDDClr } // X origin / 2 mul (1) acc0.1<1>:ud r7.1<0;1,0>:w 3:w // Y origin * 3 shr (1) mudMSGHDR_ENC_STATS(0,1)<1> acc0.1<0;1,0>:ud 2:w { NoDDClr, NoDDChk } //enable the flag after testing on si { NoDDClr, NoDDChk } // Y origin * 3/4 mov (1) mudMSGHDR_ENC_STATS(0,2)<1> 0x20007:ud { NoDDChk } //enable the flag after testing on si { NoDDChk } // block width and height (8x3) add (2) mudMSGHDR_ENC_STATS(0,0)<1> mudMSGHDR_ENC_STATS(0,0)<2;2,1> r1.12<2;2,1>:uw // Add pitch to X,Y origin //Data block for Encoder Statistics //---------------------------------------------------- //| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Bytes //---------------------------------------------------- //| BNE | MCNT | FCNT | TCNT | X | X | X | X | //---------------------------------------------------- //| DcTpT | SVCM | DcBpT | DcTpB | //---------------------------------------------------- //| SHCM | STAD | DcTcB | DcBpB | //---------------------------------------------------- mov (1) mudMSGHDR_ENC_STATS(1,0)<1> udDNDI_RESP(9,1)<0;1,0> { NoDDClr } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,3)<2> udDNDI_RESP(9,3)<2;2,1> { NoDDClr, NoDDChk } // Move encoder statistics to MRF mov (2) mudMSGHDR_ENC_STATS(1,2)<2> udDNDI_RESP(9,5)<2;2,1> { NoDDChk } // Move encoder statistics to MRF send (8) null<1>:d r24 0x5 0x40A8021:ud // FileName: DI_Save_PA_16x4.asm // Author: Vivek Kumar // Description: Save two 16x4 blocks of DI output in Packed format add (4) a0.4<1>:uw r2.28<4;4,1>:ub 608:w // Initial Y,U,V offset in YUV422 block; it starts at m20 mov (8) r27.0<1>:ud r0.0<8;8,1>:ud shl (1) r27.0<1>:d r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be doubled mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin mov (1) r27.2<1>:ud 0x3001F:ud { NoDDChk } // Block width and height (32x8) //prepare the message headers mov (8) r18.0<1>:ud r27<8;8,1>:ud mov (8) r23.0<1>:ud r27<8;8,1>:ud // Pack 2nd field Y mov (16) r[a0.4, 0]<2> ubDNDI_RESP(0,0) { NoDDClr } mov (16) r[a0.4, 32]<2> ubDNDI_RESP(0,16) { NoDDClr } mov (16) r[a0.4, 64]<2> ubDNDI_RESP(0,32) { NoDDClr } mov (16) r[a0.4, 96]<2> ubDNDI_RESP(0,48) { NoDDClr } // Pack 2nd field U mov (8) r[a0.5, 0]<4> ubDNDI_RESP(2,1)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 32]<4> ubDNDI_RESP(2,17)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 64]<4> ubDNDI_RESP(2,33)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 96]<4> ubDNDI_RESP(2,49)<16;8,2> { NoDDClr, NoDDChk } //U pixels // Pack 2nd field V mov (8) r[a0.6, 0]<4> ubDNDI_RESP(2,0)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 32]<4> ubDNDI_RESP(2,16)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 64]<4> ubDNDI_RESP(2,32)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 96]<4> ubDNDI_RESP(2,48)<16;8,2> { NoDDChk } //Vpixels // Pack 1st field Y mov (16) r[a0.4, 160]<2> ubDNDI_RESP(4,0) { NoDDClr } mov (16) r[a0.4, 192]<2> ubDNDI_RESP(4,16) { NoDDClr } mov (16) r[a0.4, 224]<2> ubDNDI_RESP(4,32) { NoDDClr } mov (16) r[a0.4, 256]<2> ubDNDI_RESP(4,48) { NoDDClr } // Pack 1st field U mov (8) r[a0.5, 160]<4> ubDNDI_RESP(6,1)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 192]<4> ubDNDI_RESP(6,17)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 224]<4> ubDNDI_RESP(6,33)<16;8,2> { NoDDClr, NoDDChk } //U pixels mov (8) r[a0.5, 256]<4> ubDNDI_RESP(6,49)<16;8,2> { NoDDClr, NoDDChk } //U pixels // Pack 1st field V mov (8) r[a0.6, 160]<4> ubDNDI_RESP(6,0)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 192]<4> ubDNDI_RESP(6,16)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 224]<4> ubDNDI_RESP(6,32)<16;8,2> { NoDDChk } //Vpixels mov (8) r[a0.6, 256]<4> ubDNDI_RESP(6,48)<16;8,2> { NoDDChk } //Vpixels //save the previous frame send (8) null<1>:d r18.0 0x5 0xA0A801B:ud //save the current frame send (8) null<1>:d r23.0 0x5 0xA0A801E:ud //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/RGB_to_YUV.g4a000066400000000000000000001051071231401140700246710ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * Authors: * Zhao Yakui */ // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: YUV_to_RGB.asm // // Convert YUV to RGB, handle it by 16x4 block // // Description: Includes all definitions explicit to Fast Composite. //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare bBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare bBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare bBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare bBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //Pointer to mask reg .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written //Unnecessary to use the MSGPayLoad, So it is temporiarily used for conversion of YUV->RGB .declare fBUFFER_R Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_G Base=r30.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_B Base=r32.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_Y Base=r36.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_U Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_V Base=r40.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare wTempY Base=r42.0 ElementSize=2 Type=w .declare wTempU Base=r44.0 ElementSize=2 Type=w .declare wTempV Base=r46.0 ElementSize=2 Type=w .declare ubTempY Base=r42.0 ElementSize=1 Type=ub .declare ubTempU Base=r44.0 ElementSize=1 Type=ub .declare ubTempV Base=r46.0 ElementSize=1 Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ // ITU-R conversion, Now we are using ITU-R conversion // Y = 0.299R + 0.587G + 0.114B // U = -0.169R - 0.331G + 0.499B + 128 // V = 0.499R - 0.418G - 0.0813B+ 128 // At the save module we have all 8 address sub-registers available. // So we will use PING-PONG type of scheme to save the data using // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help // reduce dependency. - rT //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4. //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5). //Offsets are zero for buffer 0 and buffer 4. //It always uses the YUVA layout. //for BUFFER_0 mov (4) a0.0<1>:uw r22.0<4;4,1>:uw mov (4) a0.4<1>:uw r22.0<4;4,1>:uw // YUV uses the a0.5,a0.6 and a0.4 as the indirect-register // Y = a0.5, U=a0.6, V=a0.4 // if channel swap? // This means that it should be BGRX(B is the LSB) or RGBX // 1 means that it is BGRX. and.nz.f0.0 null<1>:w r2.0<0;1,0>:uw 0x01:w // pointer swap (f0.0) mov (1) uwTemp0<1> a0.0:uw (f0.0) mov (1) a0.0:uw a0.1:uw (f0.0) mov (1) a0.1:uw uwTemp0<0;1,0> //the first line in the block 0 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 17]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 0]<1>:uw 0:uw mov (16) r[a0.6, 0]<1>:uw 0:uw mov (16) r[a0.4, 0]<1>:uw 0:uw mov (16) r[a0.5,1]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,1]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,1]<2>:ub ubTempV(0, 0)<32;8,4> //the second line in the block 0 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 49]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 32]<1>:uw 0:uw mov (16) r[a0.6, 32]<1>:uw 0:uw mov (16) r[a0.4, 32]<1>:uw 0:uw mov (16) r[a0.5,33]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,33]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,33]<2>:ub ubTempV(0, 0)<32;8,4> //the third line in the block 0 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 81]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 64]<1>:uw 0:uw mov (16) r[a0.6, 64]<1>:uw 0:uw mov (16) r[a0.4, 64]<1>:uw 0:uw mov (16) r[a0.5,65]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,65]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,65]<2>:ub ubTempV(0, 0)<32;8,4> //the fourth line in the block 0 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 113]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 96]<1>:uw 0:uw mov (16) r[a0.6, 96]<1>:uw 0:uw mov (16) r[a0.4, 96]<1>:uw 0:uw mov (16) r[a0.5,97]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,97]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,97]<2>:ub ubTempV(0, 0)<32;8,4> //for Buffer_1 add (8) a0.0<1>:uw a0.0<8;8,1>:uw 512:uw //the first line in the block 1 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 17]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 0]<1>:uw 0:uw mov (16) r[a0.6, 0]<1>:uw 0:uw mov (16) r[a0.4, 0]<1>:uw 0:uw mov (16) r[a0.5,1]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,1]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,1]<2>:ub ubTempV(0, 0)<32;8,4> //the second line in the block 1 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 49]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 32]<1>:uw 0:uw mov (16) r[a0.6, 32]<1>:uw 0:uw mov (16) r[a0.4, 32]<1>:uw 0:uw mov (16) r[a0.5,33]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,33]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,33]<2>:ub ubTempV(0, 0)<32;8,4> //the third line in the block 1 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 81]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 64]<1>:uw 0:uw mov (16) r[a0.6, 64]<1>:uw 0:uw mov (16) r[a0.4, 64]<1>:uw 0:uw mov (16) r[a0.5,65]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,65]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,65]<2>:ub ubTempV(0, 0)<32;8,4> //the fourth line in the block 1 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 113]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 96]<1>:uw 0:uw mov (16) r[a0.6, 96]<1>:uw 0:uw mov (16) r[a0.4, 96]<1>:uw 0:uw mov (16) r[a0.5,97]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,97]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,97]<2>:ub ubTempV(0, 0)<32;8,4> //for Buffer_2 add (8) a0.0<1>:uw a0.0<8;8,1>:uw 512:uw //the first line in the block 2 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 17]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 0]<1>:uw 0:uw mov (16) r[a0.6, 0]<1>:uw 0:uw mov (16) r[a0.4, 0]<1>:uw 0:uw mov (16) r[a0.5,1]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,1]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,1]<2>:ub ubTempV(0, 0)<32;8,4> //the second line in the block 2 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 49]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 32]<1>:uw 0:uw mov (16) r[a0.6, 32]<1>:uw 0:uw mov (16) r[a0.4, 32]<1>:uw 0:uw mov (16) r[a0.5,33]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,33]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,33]<2>:ub ubTempV(0, 0)<32;8,4> //the third line in the block 2 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 81]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 64]<1>:uw 0:uw mov (16) r[a0.6, 64]<1>:uw 0:uw mov (16) r[a0.4, 64]<1>:uw 0:uw mov (16) r[a0.5,65]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,65]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,65]<2>:ub ubTempV(0, 0)<32;8,4> //the fourth line in the block 2 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 113]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 96]<1>:uw 0:uw mov (16) r[a0.6, 96]<1>:uw 0:uw mov (16) r[a0.4, 96]<1>:uw 0:uw mov (16) r[a0.5,97]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,97]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,97]<2>:ub ubTempV(0, 0)<32;8,4> //for Buffer_3 add (8) a0.0<1>:uw a0.0<8;8,1>:uw 512:uw //the first line in the block 3 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 17]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 0]<1>:uw 0:uw mov (16) r[a0.6, 0]<1>:uw 0:uw mov (16) r[a0.4, 0]<1>:uw 0:uw mov (16) r[a0.5,1]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,1]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,1]<2>:ub ubTempV(0, 0)<32;8,4> //the second line in the block 3 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 49]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 32]<1>:uw 0:uw mov (16) r[a0.6, 32]<1>:uw 0:uw mov (16) r[a0.4, 32]<1>:uw 0:uw mov (16) r[a0.5,33]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,33]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,33]<2>:ub ubTempV(0, 0)<32;8,4> //the third line in the block 3 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 81]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 64]<1>:uw 0:uw mov (16) r[a0.6, 64]<1>:uw 0:uw mov (16) r[a0.4, 64]<1>:uw 0:uw mov (16) r[a0.5,65]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,65]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,65]<2>:ub ubTempV(0, 0)<32;8,4> //the fourth line in the block 3 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 113]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 96]<1>:uw 0:uw mov (16) r[a0.6, 96]<1>:uw 0:uw mov (16) r[a0.4, 96]<1>:uw 0:uw mov (16) r[a0.5,97]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,97]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,97]<2>:ub ubTempV(0, 0)<32;8,4> intel-driver-1.3.0/src/shaders/post_processing/gen7/Save_AVS_NV12.g4a000066400000000000000000000572721231401140700252000ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 131 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: Save_AVS_NV12.asm // // Save NV12 420 frame data block of size 16x16 // // To save 16x16 block (16x16 bytes of Y and 16x8 bytes of interleaved UV), we need 2 send instructions with of size 16x16 and 16x8 each. // --------------- // | 16x16 | // | YUYV | // --------------- // | 16x8 UV | // --------------- //----------------------------------------------------------------- //The layout of data is as follows: //mMSGHDR0 : Y data header (16x16) //mubMSGPAYLOAD0 : Y data payload (8 GRFs) //mMSGHDR1 : U data header (16x8) //mubMSGPAYLOAD1 : U data payload (4 GRFs) //------------------------------------------------------------------ // Module name: Save.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written .declare mudMSGPAYLOAD0 Base=r29.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD1 Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD2 Base=r47.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD3 Base=r56.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare muwMSGPAYLOAD0 Base=r29.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD1 Base=r38.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD2 Base=r47.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD3 Base=r56.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mubMSGPAYLOAD0 Base=r29.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD1 Base=r38.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD2 Base=r47.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD3 Base=r56.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD4 Base=r32.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD5 Base=r41.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD6 Base=r50.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD7 Base=r59.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ // At the save module we have all 8 address sub-registers available. // So we will use PING-PONG type of scheme to save the data using // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help // reduce dependency. - rT //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4. //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5). //Offsets are zero for buffer 0 and buffer 4. add (4) a0.0:uw r22.0<4;4,1>:w 0:uw add (4) a0.4:uw r22.0<4;4,1>:w 512:uw //Set up header for Y,U and V data mov (8) r28<1>:ud r27<8;8,1>:ud mov (8) r37<1>:ud r27<8;8,1>:ud mov (2) r28.0<1>:d r7.0<2;2,1>:w { NoDDClr } //ORI Y (LUMA) = ORI mov (1) r37.0<1>:d r7.0<0;1,0>:w { NoDDClr } //H ORI (CHROMA) = H ORI shr (1) r37.1<1>:d r7.1<0;1,0>:w 1:w { NoDDClr, NoDDChk } //V ORI (CHROMA) = V ORI/2 mov (1) r28.2<1>:ud 0xF000F:ud { NoDDChk } // Y Block width and height (16x16) mov (1) r37.2<1>:ud 0x7000F:ud { NoDDChk } // UV Block width and height(16x8) // Unscramble, and pack data directly to MRFs // Data 16x16 block is divided as - // --------- // | 0 | // --------- // | 1 | // --------- // | 2 | // --------- // | 3 | // --------- // All sub-blocks are of size 16x4 // 0: ubBUFFER_0 // 1: ubBUFFER_1, ubBUFFER_0+16 // 2: ubBUFFER_2 // 3: ubBUFFER_3, ubBUFFER_2+16 //Y Rounding 16x4 top part add.sat (16) r[a0.1,0]<1>:uw r[a0.1,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,32]<1>:uw r[a0.1,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,64]<1>:uw r[a0.1,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,96]<1>:uw r[a0.1,96]<16;16,1>:uw 0x0080:uw // U Averaging and Rounding, 8x2 top part shr (8) uwBUFFER_5(0,0)<2> r[a0.2,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(1,0)<2> r[a0.2,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(2,0)<2> r[a0.2,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(3,0)<2> r[a0.2,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(0,0)<2> uwBUFFER_5(0,0)<16;8,2> uwBUFFER_5(1,0)<16;8,2> add.sat (8) r[a0.2,0]<2>:uw uwBUFFER_5(0,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(2,0)<2> uwBUFFER_5(2,0)<16;8,2> uwBUFFER_5(3,0)<16;8,2> add.sat (8) r[a0.2,64]<2>:uw uwBUFFER_5(2,0)<16;8,2> 0x0080:uw // V Averaging and Rounding, 8x2 top part shr (8) uwBUFFER_5(4,0)<2> r[a0.0,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(5,0)<2> r[a0.0,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(6,0)<2> r[a0.0,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(7,0)<2> r[a0.0,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(4,0)<2> uwBUFFER_5(4,0)<16;8,2> uwBUFFER_5(5,0)<16;8,2> add.sat (8) r[a0.0,0]<2>:uw uwBUFFER_5(4,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(6,0)<2> uwBUFFER_5(6,0)<16;8,2> uwBUFFER_5(7,0)<16;8,2> add.sat (8) r[a0.0,64]<2>:uw uwBUFFER_5(6,0)<16;8,2> 0x0080:uw add (4) a0.0:uw r22.0<4;4,1>:w 1024:uw //Update Buffer 2 pointers //Y Rounding, 16x4 bottom part add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,64]<1>:uw r[a0.5,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,96]<1>:uw r[a0.5,96]<16;16,1>:uw 0x0080:uw // U Averaging and Rounding, 8x2 bottom part shr (8) uwBUFFER_5(0,0)<2> r[a0.6,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(1,0)<2> r[a0.6,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(2,0)<2> r[a0.6,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(3,0)<2> r[a0.6,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(0,0)<2> uwBUFFER_5(0,0)<16;8,2> uwBUFFER_5(1,0)<16;8,2> add.sat (8) r[a0.6,0]<2>:uw uwBUFFER_5(0,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(2,0)<2> uwBUFFER_5(2,0)<16;8,2> uwBUFFER_5(3,0)<16;8,2> add.sat (8) r[a0.6,64]<2>:uw uwBUFFER_5(2,0)<16;8,2> 0x0080:uw // V Averaging and Rounding, 8x2 bottom part shr (8) uwBUFFER_5(4,0)<2> r[a0.4,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(5,0)<2> r[a0.4,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(6,0)<2> r[a0.4,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(7,0)<2> r[a0.4,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(4,0)<2> uwBUFFER_5(4,0)<16;8,2> uwBUFFER_5(5,0)<16;8,2> add.sat (8) r[a0.4,0]<2>:uw uwBUFFER_5(4,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(6,0)<2> uwBUFFER_5(6,0)<16;8,2> uwBUFFER_5(7,0)<16;8,2> add.sat (8) r[a0.4,64]<2>:uw uwBUFFER_5(6,0)<16;8,2> 0x0080:uw add (4) a0.4:uw r22.0<4;4,1>:w 1536:uw //Update Buffer 3 pointers //Y Rounding 16x4 top part add.sat (16) r[a0.1,0]<1>:uw r[a0.1,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,32]<1>:uw r[a0.1,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,64]<1>:uw r[a0.1,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,96]<1>:uw r[a0.1,96]<16;16,1>:uw 0x0080:uw // U Averaging and Rounding, 8x2 top part shr (8) uwBUFFER_5(0,0)<2> r[a0.2,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(1,0)<2> r[a0.2,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(2,0)<2> r[a0.2,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(3,0)<2> r[a0.2,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(0,0)<2> uwBUFFER_5(0,0)<16;8,2> uwBUFFER_5(1,0)<16;8,2> add.sat (8) r[a0.2,0]<2>:uw uwBUFFER_5(0,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(2,0)<2> uwBUFFER_5(2,0)<16;8,2> uwBUFFER_5(3,0)<16;8,2> add.sat (8) r[a0.2,64]<2>:uw uwBUFFER_5(2,0)<16;8,2> 0x0080:uw // V Averaging and Rounding, 8x2 top part shr (8) uwBUFFER_5(4,0)<2> r[a0.0,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(5,0)<2> r[a0.0,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(6,0)<2> r[a0.0,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(7,0)<2> r[a0.0,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(4,0)<2> uwBUFFER_5(4,0)<16;8,2> uwBUFFER_5(5,0)<16;8,2> add.sat (8) r[a0.0,0]<2>:uw uwBUFFER_5(4,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(6,0)<2> uwBUFFER_5(6,0)<16;8,2> uwBUFFER_5(7,0)<16;8,2> add.sat (8) r[a0.0,64]<2>:uw uwBUFFER_5(6,0)<16;8,2> 0x0080:uw add (4) a0.0:uw r22.0<4;4,1>:w 1024:uw //Update Buffer 2 pointers //Y Rounding, 16x4 bottom part add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,64]<1>:uw r[a0.5,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,96]<1>:uw r[a0.5,96]<16;16,1>:uw 0x0080:uw // U Averaging and Rounding, 8x2 bottom part shr (8) uwBUFFER_5(0,0)<2> r[a0.6,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(1,0)<2> r[a0.6,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(2,0)<2> r[a0.6,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(3,0)<2> r[a0.6,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(0,0)<2> uwBUFFER_5(0,0)<16;8,2> uwBUFFER_5(1,0)<16;8,2> add.sat (8) r[a0.6,0]<2>:uw uwBUFFER_5(0,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(2,0)<2> uwBUFFER_5(2,0)<16;8,2> uwBUFFER_5(3,0)<16;8,2> add.sat (8) r[a0.6,64]<2>:uw uwBUFFER_5(2,0)<16;8,2> 0x0080:uw // V Averaging and Rounding, 8x2 bottom part shr (8) uwBUFFER_5(4,0)<2> r[a0.4,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(5,0)<2> r[a0.4,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(6,0)<2> r[a0.4,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(7,0)<2> r[a0.4,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(4,0)<2> uwBUFFER_5(4,0)<16;8,2> uwBUFFER_5(5,0)<16;8,2> add.sat (8) r[a0.4,0]<2>:uw uwBUFFER_5(4,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(6,0)<2> uwBUFFER_5(6,0)<16;8,2> uwBUFFER_5(7,0)<16;8,2> add.sat (8) r[a0.4,64]<2>:uw uwBUFFER_5(6,0)<16;8,2> 0x0080:uw add (4) a0.4:uw r22.0<4;4,1>:w 1536:uw //Update Buffer 3 pointers // restore pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4 registers add (4) a0.0:uw r22.0<4;4,1>:w 0:uw add (4) a0.4:uw r22.0<4;4,1>:w 512:uw //Buffer 0 //Move Y to msg payload mov (16) mubMSGPAYLOAD0(0,0)<1> r[a0.1, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(0,16)<1> r[a0.1, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(1,0)<1> r[a0.1, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(1,16)<1> r[a0.1, 97]<32;16,2>:ub { NoDDChk } //Move U to msg payload mov (8) mubMSGPAYLOAD1(0,0)<2> r[a0.2, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD1(0,16)<2> r[a0.2, 65]<32;8,4>:ub { NoDDClr, NoDDChk } //Move V to msg payload mov (8) mubMSGPAYLOAD1(0,1)<2> r[a0.0, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(0,17)<2> r[a0.0, 65]<32;8,4>:ub { NoDDChk } add (4) a0.0:uw r22.0<4;4,1>:w 1024:uw //Update Buffer 2 pointers //Buffer 1 mov (16) mubMSGPAYLOAD0(2,0)<1> r[a0.5, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(2,16)<1> r[a0.5, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(3,0)<1> r[a0.5, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(3,16)<1> r[a0.5, 97]<32;16,2>:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(1,0)<2> r[a0.6, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD1(1,16)<2> r[a0.6, 65]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(1,1)<2> r[a0.4, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(1,17)<2> r[a0.4, 65]<32;8,4>:ub { NoDDChk } add (4) a0.4:uw r22.0<4;4,1>:w 1536:uw //Update Buffer 3 pointers //Buffer 2 mov (16) mubMSGPAYLOAD0(4,0)<1> r[a0.1, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(4,16)<1> r[a0.1, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(5,0)<1> r[a0.1, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(5,16)<1> r[a0.1, 97]<32;16,2>:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(2,0)<2> r[a0.2, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD1(2,16)<2> r[a0.2, 65]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(2,1)<2> r[a0.0, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(2,17)<2> r[a0.0, 65]<32;8,4>:ub { NoDDChk } //Buffer 3 mov (16) mubMSGPAYLOAD0(6,0)<1> r[a0.5, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(6,16)<1> r[a0.5, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(7,0)<1> r[a0.5, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(7,16)<1> r[a0.5, 97]<32;16,2>:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(3,0)<2> r[a0.6, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD1(3,16)<2> r[a0.6, 65]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(3,1)<2> r[a0.4, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(3,17)<2> r[a0.4, 65]<32;8,4>:ub { NoDDChk } //=========================================================================== send (1) null<1>:d r28 0x5 0x120A8018:ud send (1) null<1>:d r37 0x5 0xA0A8019:ud intel-driver-1.3.0/src/shaders/post_processing/gen7/Save_AVS_PA.g4a000066400000000000000000000630001231401140700247740ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 174 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: Save_AVS_PA.asm // // Save PA 422 frame data block of size 16x16 // // To save 16x16 block (32x16 bytes of YUYV) we need 2 send instructions with of size 16x16 each. // ------------------------------- // | 16x16 | 16x16 | // | YUYV | YUYV | // ------------------------------- // these 2 sends are replaced by 8 32x2 sends to improve performance // Module name: Save.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written .declare mudMSGPAYLOAD0 Base=r29.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD1 Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD2 Base=r47.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD3 Base=r56.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare muwMSGPAYLOAD0 Base=r29.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD1 Base=r38.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD2 Base=r47.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD3 Base=r56.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mubMSGPAYLOAD0 Base=r29.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD1 Base=r38.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD2 Base=r47.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD3 Base=r56.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD4 Base=r32.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD5 Base=r41.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD6 Base=r50.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD7 Base=r59.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ //wBUFF_CHNL_PTR points to buffer 0. //Add appropriate offsets to get pointers for all buffers (1,2,3). //Offset is zero for buffer 0. add (4) a0.0:uw r22.0<4;4,1>:w 0:uw //Set DEST pointers according to output packing i.e. YUYV, YVYU, UYVY, VYUY add (4) a0.4<1>:w r2.28<4;4,1>:ub 928:uw shl (1) r27.0<1>:d r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be 2 times mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin (1st quadrant) mov (1) r27.2<1>:ud 0x1001F:ud { NoDDChk } // Block width and height (32x2) // Rounding // left add.sat (4) r[a0.0, 0]<2>:uw r[a0.0, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,32]<2>:uw r[a0.0, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,64]<2>:uw r[a0.0, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,96]<2>:uw r[a0.0, 96]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 0]<1>:uw r[a0.1, 0]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,32]<1>:uw r[a0.1, 32]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,64]<1>:uw r[a0.1, 64]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,96]<1>:uw r[a0.1, 96]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 0]<2>:uw r[a0.2, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,32]<2>:uw r[a0.2, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,64]<2>:uw r[a0.2, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,96]<2>:uw r[a0.2, 96]<8;4,2>:uw 0x0080:uw // right add.sat (4) r[a0.0,16]<2>:uw r[a0.0, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,48]<2>:uw r[a0.0, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,80]<2>:uw r[a0.0, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,112]<2>:uw r[a0.0, 112]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 16]<1>:uw r[a0.1, 16]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,48]<1>:uw r[a0.1, 48]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,80]<1>:uw r[a0.1, 80]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,112]<1>:uw r[a0.1, 112]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 16]<2>:uw r[a0.2, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,48]<2>:uw r[a0.2, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,80]<2>:uw r[a0.2, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,112]<2>:uw r[a0.2, 112]<8;4,2>:uw 0x0080:uw add (4) a0.0:uw r22.0<4;4,1>:w 512:uw // left add.sat (4) r[a0.0, 0]<2>:uw r[a0.0, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,32]<2>:uw r[a0.0, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,64]<2>:uw r[a0.0, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,96]<2>:uw r[a0.0, 96]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 0]<1>:uw r[a0.1, 0]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,32]<1>:uw r[a0.1, 32]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,64]<1>:uw r[a0.1, 64]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,96]<1>:uw r[a0.1, 96]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 0]<2>:uw r[a0.2, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,32]<2>:uw r[a0.2, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,64]<2>:uw r[a0.2, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,96]<2>:uw r[a0.2, 96]<8;4,2>:uw 0x0080:uw // right add.sat (4) r[a0.0,16]<2>:uw r[a0.0, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,48]<2>:uw r[a0.0, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,80]<2>:uw r[a0.0, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,112]<2>:uw r[a0.0, 112]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 16]<1>:uw r[a0.1, 16]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,48]<1>:uw r[a0.1, 48]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,80]<1>:uw r[a0.1, 80]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,112]<1>:uw r[a0.1, 112]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 16]<2>:uw r[a0.2, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,48]<2>:uw r[a0.2, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,80]<2>:uw r[a0.2, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,112]<2>:uw r[a0.2, 112]<8;4,2>:uw 0x0080:uw add (4) a0.0:uw r22.0<4;4,1>:w 1024:uw // left add.sat (4) r[a0.0, 0]<2>:uw r[a0.0, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,32]<2>:uw r[a0.0, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,64]<2>:uw r[a0.0, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,96]<2>:uw r[a0.0, 96]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 0]<1>:uw r[a0.1, 0]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,32]<1>:uw r[a0.1, 32]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,64]<1>:uw r[a0.1, 64]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,96]<1>:uw r[a0.1, 96]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 0]<2>:uw r[a0.2, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,32]<2>:uw r[a0.2, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,64]<2>:uw r[a0.2, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,96]<2>:uw r[a0.2, 96]<8;4,2>:uw 0x0080:uw // right add.sat (4) r[a0.0,16]<2>:uw r[a0.0, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,48]<2>:uw r[a0.0, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,80]<2>:uw r[a0.0, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,112]<2>:uw r[a0.0, 112]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 16]<1>:uw r[a0.1, 16]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,48]<1>:uw r[a0.1, 48]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,80]<1>:uw r[a0.1, 80]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,112]<1>:uw r[a0.1, 112]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 16]<2>:uw r[a0.2, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,48]<2>:uw r[a0.2, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,80]<2>:uw r[a0.2, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,112]<2>:uw r[a0.2, 112]<8;4,2>:uw 0x0080:uw add (4) a0.0:uw r22.0<4;4,1>:w 1536:uw // left add.sat (4) r[a0.0, 0]<2>:uw r[a0.0, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,32]<2>:uw r[a0.0, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,64]<2>:uw r[a0.0, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,96]<2>:uw r[a0.0, 96]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 0]<1>:uw r[a0.1, 0]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,32]<1>:uw r[a0.1, 32]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,64]<1>:uw r[a0.1, 64]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,96]<1>:uw r[a0.1, 96]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 0]<2>:uw r[a0.2, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,32]<2>:uw r[a0.2, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,64]<2>:uw r[a0.2, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,96]<2>:uw r[a0.2, 96]<8;4,2>:uw 0x0080:uw // right add.sat (4) r[a0.0,16]<2>:uw r[a0.0, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,48]<2>:uw r[a0.0, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,80]<2>:uw r[a0.0, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,112]<2>:uw r[a0.0, 112]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 16]<1>:uw r[a0.1, 16]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,48]<1>:uw r[a0.1, 48]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,80]<1>:uw r[a0.1, 80]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,112]<1>:uw r[a0.1, 112]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 16]<2>:uw r[a0.2, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,48]<2>:uw r[a0.2, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,80]<2>:uw r[a0.2, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,112]<2>:uw r[a0.2, 112]<8;4,2>:uw 0x0080:uw add (4) a0.0:uw r22.0<4;4,1>:w 2048:uw // restore pointer add (4) a0.0:uw r22.0<4;4,1>:w 0:uw mov (8) r28<1>:ud r27<8;8,1>:ud mov (8) r37<1>:ud r27<8;8,1>:ud add (1) r37.1<1>:d r27.1<0;1,0>:d 2:d // Point to 2nd part mov (8) r[a0.6, 0]<4>:ub r[a0.0, 1]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 32]<4>:ub r[a0.0,33]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4, 0]<2>:ub r[a0.1, 1]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4, 32]<2>:ub r[a0.1,33]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5, 0]<4>:ub r[a0.2, 1]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5, 32]<4>:ub r[a0.2,33]<32;8,4>:ub { NoDDChk } mov (8) r[a0.6, 288]<4>:ub r[a0.0,65]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 320]<4>:ub r[a0.0,97]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4,288]<2>:ub r[a0.1,65]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4,320]<2>:ub r[a0.1,97]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5,288]<4>:ub r[a0.2,65]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5,320]<4>:ub r[a0.2,97]<32;8,4>:ub { NoDDChk } send (1) null<1>:d r28 0x5 0x60A8018:ud send (1) null<1>:d r37 0x5 0x60A8018:ud // restore pointer add (4) a0.0:uw r22.0<4;4,1>:w 512:uw add (1) r28.1<1>:d r27.1<0;1,0>:d 4:d // Point to 2nd part add (1) r37.1<1>:d r27.1<0;1,0>:d 6:d // Point to 2nd part mov (8) r[a0.6, 0]<4>:ub r[a0.0, 1]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 32]<4>:ub r[a0.0,33]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4, 0]<2>:ub r[a0.1, 1]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4, 32]<2>:ub r[a0.1,33]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5, 0]<4>:ub r[a0.2, 1]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5, 32]<4>:ub r[a0.2,33]<32;8,4>:ub { NoDDChk } mov (8) r[a0.6, 288]<4>:ub r[a0.0,65]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 320]<4>:ub r[a0.0,97]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4,288]<2>:ub r[a0.1,65]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4,320]<2>:ub r[a0.1,97]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5,288]<4>:ub r[a0.2,65]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5,320]<4>:ub r[a0.2,97]<32;8,4>:ub { NoDDChk } send (1) null<1>:d r28 0x5 0x60A8018:ud send (1) null<1>:d r37 0x5 0x60A8018:ud // restore pointer add (4) a0.0:uw r22.0<4;4,1>:w 1024:uw add (1) r28.1<1>:d r27.1<0;1,0>:d 8:d // Point to 2nd part add (1) r37.1<1>:d r27.1<0;1,0>:d 10:d // Point to 2nd part mov (8) r[a0.6, 0]<4>:ub r[a0.0, 1]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 32]<4>:ub r[a0.0,33]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4, 0]<2>:ub r[a0.1, 1]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4, 32]<2>:ub r[a0.1,33]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5, 0]<4>:ub r[a0.2, 1]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5, 32]<4>:ub r[a0.2,33]<32;8,4>:ub { NoDDChk } mov (8) r[a0.6, 288]<4>:ub r[a0.0,65]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 320]<4>:ub r[a0.0,97]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4,288]<2>:ub r[a0.1,65]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4,320]<2>:ub r[a0.1,97]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5,288]<4>:ub r[a0.2,65]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5,320]<4>:ub r[a0.2,97]<32;8,4>:ub { NoDDChk } send (1) null<1>:d r28 0x5 0x60A8018:ud send (1) null<1>:d r37 0x5 0x60A8018:ud // restore pointer add (4) a0.0:uw r22.0<4;4,1>:w 1536:uw add (1) r28.1<1>:d r27.1<0;1,0>:d 12:d // Point to 2nd part add (1) r37.1<1>:d r27.1<0;1,0>:d 14:d // Point to 2nd part mov (8) r[a0.6, 0]<4>:ub r[a0.0, 1]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 32]<4>:ub r[a0.0,33]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4, 0]<2>:ub r[a0.1, 1]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4, 32]<2>:ub r[a0.1,33]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5, 0]<4>:ub r[a0.2, 1]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5, 32]<4>:ub r[a0.2,33]<32;8,4>:ub { NoDDChk } mov (8) r[a0.6, 288]<4>:ub r[a0.0,65]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 320]<4>:ub r[a0.0,97]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4,288]<2>:ub r[a0.1,65]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4,320]<2>:ub r[a0.1,97]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5,288]<4>:ub r[a0.2,65]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5,320]<4>:ub r[a0.2,97]<32;8,4>:ub { NoDDChk } send (1) null<1>:d r28 0x5 0x60A8018:ud send (1) null<1>:d r37 0x5 0x60A8018:ud intel-driver-1.3.0/src/shaders/post_processing/gen7/Save_AVS_PL3.g4a000066400000000000000000000503221231401140700250750ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 84 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: Save_AVS_PL3.asm // // Save PL3 420 frame data block of size 16x16 // // To save 16x16 block (16x16 byte of Y and 8x8 byte of U and V each) we need 3 send instructions with one of size 16x16 and two of size 8x8. // ----------------- // | 16x16 Y | // | | // ----------------- // | 8x8 U | // --------- // | 8x8 V | // --------- //----------------------------------------------------------------- //The layout of data is as follows: //mMSGHDR0 : Y data header (16x16) //mubMSGPAYLOAD0 : Y data payload (8 GRFs) //mMSGHDR1 : U data header (8x8) //mubMSGPAYLOAD1 : U data payload (2 GRFs) //mMSGHDR2 : V data header (8x8) //mubMSGPAYLOAD2 : V data payload (2 GRFs) //------------------------------------------------------------------ // Module name: Save.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written .declare mudMSGPAYLOAD0 Base=r29.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD1 Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD2 Base=r47.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD3 Base=r56.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare muwMSGPAYLOAD0 Base=r29.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD1 Base=r38.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD2 Base=r47.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD3 Base=r56.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mubMSGPAYLOAD0 Base=r29.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD1 Base=r38.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD2 Base=r47.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD3 Base=r56.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD4 Base=r32.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD5 Base=r41.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD6 Base=r50.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD7 Base=r59.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ // At the save module we have all 8 address sub-registers available. // So we will use PING-PONG type of scheme to save the data using // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help // reduce dependency. - rT //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4. //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5). //Offsets are zero for buffer 0 and buffer 4. add (4) a0.0:uw r22.0<4;4,1>:w 0:uw add (4) a0.4:uw r22.0<4;4,1>:w 512:uw //Set up header for Y,U and V data mov (8) r28<1>:ud r27<8;8,1>:ud mov (8) r37<1>:ud r27<8;8,1>:ud mov (8) r46<1>:ud r27<8;8,1>:ud mov (2) r28.0<1>:d r7.0<2;2,1>:w { NoDDClr } //ORI Y (LUMA) = ORI shr (2) r37.0<1>:d r7.0<2;2,1>:w 1:w { NoDDClr } //H/V ORI U = H/V ORI/2 shr (2) r46.0<1>:d r7.0<2;2,1>:w 1:w { NoDDClr } //H/V ORI V = H/V ORI/2 mov (1) r28.2<1>:ud 0xF000F:ud { NoDDChk } // Y Block width and height (16x16) mov (1)r37.2<1>:ud 0x70007:ud { NoDDChk } // U Block width and height (8x8) mov (1)r46.2<1>:ud 0x70007:ud { NoDDChk } // V Block width and height (8x8) // Unscramble, and pack data directly to MRFs // Data 16x16 block is divided as - // --------- // | 0 | // --------- // | 1 | // --------- // | 2 | // --------- // | 3 | // --------- // All sub-blocks are of size 16x4 // 0: ubBUFFER_0 // 1: ubBUFFER_1, ubBUFFER_0+16 // 2: ubBUFFER_2 // 3: ubBUFFER_3, ubBUFFER_2+16 //Y Rounding, first add.sat (16) r[a0.1,0]<1>:uw r[a0.1,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,32]<1>:uw r[a0.1,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,64]<1>:uw r[a0.1,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,96]<1>:uw r[a0.1,96]<16;16,1>:uw 0x0080:uw // U rounding add.sat (8) r[a0.2,0]<2>:uw r[a0.2,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.2,64]<2>:uw r[a0.2,64]<16;8,2>:uw 0x0080:uw // V rounding add.sat (8) r[a0.0,0]<2>:uw r[a0.0,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.0,64]<2>:uw r[a0.0,64]<16;8,2>:uw 0x0080:uw add (4) a0.0:uw r22.0<4;4,1>:w 1024:uw //Update Buffer 2 pointers //Y Rounding, second add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,64]<1>:uw r[a0.5,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,96]<1>:uw r[a0.5,96]<16;16,1>:uw 0x0080:uw // U rounding add.sat (8) r[a0.6,0]<2>:uw r[a0.6,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.6,64]<2>:uw r[a0.6,64]<16;8,2>:uw 0x0080:uw // V rounding add.sat (8) r[a0.4,0]<2>:uw r[a0.4,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.4,64]<2>:uw r[a0.4,64]<16;8,2>:uw 0x0080:uw add (4) a0.4:uw r22.0<4;4,1>:w 1536:uw //Update Buffer 3 pointers //Y Rounding, third add.sat (16) r[a0.1,0]<1>:uw r[a0.1,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,32]<1>:uw r[a0.1,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,64]<1>:uw r[a0.1,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,96]<1>:uw r[a0.1,96]<16;16,1>:uw 0x0080:uw // U rounding add.sat (8) r[a0.2,0]<2>:uw r[a0.2,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.2,64]<2>:uw r[a0.2,64]<16;8,2>:uw 0x0080:uw // V rounding add.sat (8) r[a0.0,0]<2>:uw r[a0.0,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.0,64]<2>:uw r[a0.0,64]<16;8,2>:uw 0x0080:uw //Y Rounding, fourth add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,64]<1>:uw r[a0.5,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,96]<1>:uw r[a0.5,96]<16;16,1>:uw 0x0080:uw // U rounding add.sat (8) r[a0.6,0]<2>:uw r[a0.6,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.6,64]<2>:uw r[a0.6,64]<16;8,2>:uw 0x0080:uw // V rounding add.sat (8) r[a0.4,0]<2>:uw r[a0.4,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.4,64]<2>:uw r[a0.4,64]<16;8,2>:uw 0x0080:uw // restore the TOP and BOT pointers add (4) a0.0:uw r22.0<4;4,1>:w 0:uw add (4) a0.4:uw r22.0<4;4,1>:w 512:uw //Buffer 0 //Move Y to msg payload mov (16) mubMSGPAYLOAD0(0,0)<1> r[a0.1, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(0,16)<1> r[a0.1, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(1,0)<1> r[a0.1, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(1,16)<1> r[a0.1, 97]<32;16,2>:ub { NoDDChk } //Move U to msg payload mov (8) mubMSGPAYLOAD1(0,0)<1> r[a0.2, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD1(0,8)<1> r[a0.2, 65]<32;8,4>:ub { NoDDClr, NoDDChk } //Move V to msg payload mov (8) mubMSGPAYLOAD2(0,0)<1> r[a0.0, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD2(0,8)<1> r[a0.0, 65]<32;8,4>:ub { NoDDClr, NoDDChk } add (4) a0.0:uw r22.0<4;4,1>:w 1024:uw //Update Buffer 2 pointers //Buffer 1 mov (16) mubMSGPAYLOAD0(2,0)<1> r[a0.5, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(2,16)<1> r[a0.5, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(3,0)<1> r[a0.5, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(3,16)<1> r[a0.5, 97]<32;16,2>:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(0,16)<1> r[a0.6, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(0,24)<1> r[a0.6, 65]<32;8,4>:ub { NoDDChk } mov (8) mubMSGPAYLOAD2(0,16)<1> r[a0.4, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(0,24)<1> r[a0.4, 65]<32;8,4>:ub { NoDDChk } add (4) a0.4:uw r22.0<4;4,1>:w 1536:uw //Update Buffer 3 pointers //Buffer 2 mov (16) mubMSGPAYLOAD0(4,0)<1> r[a0.1, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(4,16)<1> r[a0.1, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(5,0)<1> r[a0.1, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(5,16)<1> r[a0.1, 97]<32;16,2>:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(1,0)<1> r[a0.2, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD1(1,8)<1> r[a0.2, 65]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(1,0)<1> r[a0.0, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD2(1,8)<1> r[a0.0, 65]<32;8,4>:ub { NoDDClr, NoDDChk } //Buffer 3 mov (16) mubMSGPAYLOAD0(6,0)<1> r[a0.5, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(6,16)<1> r[a0.5, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(7,0)<1> r[a0.5, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(7,16)<1> r[a0.5, 97]<32;16,2>:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(1,16)<1> r[a0.6, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(1,24)<1> r[a0.6, 65]<32;8,4>:ub { NoDDChk } mov (8) mubMSGPAYLOAD2(1,16)<1> r[a0.4, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(1,24)<1> r[a0.4, 65]<32;8,4>:ub { NoDDChk } //=========================================================================== send (1) null<1>:d r28 0x5 0x120A8018:ud send (1) null<1>:d r37 0x5 0x60A8019:ud send (1) null<1>:d r46 0x5 0x60A801A:ud intel-driver-1.3.0/src/shaders/post_processing/gen7/Save_AVS_RGB.g4a000066400000000000000000000670061231401140700251200ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 198 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: Save_AVS_RGB.asm // // Save packed ARGB 444 frame data block of size 16x16 // // To save 16x16 block (64x16 byte layout for ARGB8888) we need 4 send instructions with 16x16 in each // ----------------- // | 0 | 1 | 2 | 3 | // ----------------- // the 4 16x16 block send has been replaced by 16 32x2 sends to get better performance // Module name: Save.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written .declare mudMSGPAYLOAD0 Base=r29.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD1 Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD2 Base=r47.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD3 Base=r56.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare muwMSGPAYLOAD0 Base=r29.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD1 Base=r38.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD2 Base=r47.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD3 Base=r56.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mubMSGPAYLOAD0 Base=r29.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD1 Base=r38.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD2 Base=r47.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD3 Base=r56.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD4 Base=r32.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD5 Base=r41.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD6 Base=r50.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD7 Base=r59.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ // At the save module we have all 8 address sub-registers available. // So we will use PING-PONG type of scheme to save the data using // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help // reduce dependency. - rT // channel switching based on bit 0 of uWRGB_BGR_CH_SWITCH // if channel swap? and.nz.f0.0 null<1>:w r2.3<0;1,0>:uw 0x01:w //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4. //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5). //Offsets are zero for buffer 0 and buffer 4. add (4) a0.0:uw r22.0<4;4,1>:w 0:uw // pointer swap (f0.0) mov (1) uwTemp0<1> a0.0:uw (f0.0) mov (1) a0.0:uw a0.2:uw (f0.0) mov (1) a0.2:uw uwTemp0<0;1,0> shl (1) r27.0<1>:d r7.0<0;1,0>:w 2:w { NoDDClr } // H. block origin need to be quadrupled mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin (1st quadrant) mov (1) r27.2<1>:ud 0x1001F:ud { NoDDChk } // Block width and height (32x2) add (4) a0.4:uw a0.0<4;4,1>:w r22.8<0;2,1>:w mov (8) r28<1>:ud r27<8;8,1>:ud mov (8) r37<1>:ud r27<8;8,1>:ud mov (8) r46<1>:ud r27<8;8,1>:ud mov (8) r55<1>:ud r27<8;8,1>:ud mov (8) r31<1>:ud r27<8;8,1>:ud mov (8) r40<1>:ud r27<8;8,1>:ud mov (8) r49<1>:ud r27<8;8,1>:ud mov (8) r58<1>:ud r27<8;8,1>:ud //for BUFFER 0 add (1) r37.1<1>:d r27.1<0;1,0>:d 2:d add (1) r46.0<1>:d r27.0<0;1,0>:d 32:d add (1) r55.0<1>:d r27.0<0;1,0>:d 32:d add (1) r55.1<1>:d r27.1<0;1,0>:d 2:d // for BUFFER 1 add (1) r31.1<1>:d r27.1<0;1,0>:d 4:d add (1) r40.1<1>:d r27.1<0;1,0>:d 6:d add (1) r49.0<1>:d r27.0<0;1,0>:d 32:d add (1) r49.1<1>:d r27.1<0;1,0>:d 4:d add (1) r58.0<1>:d r27.0<0;1,0>:d 32:d add (1) r58.1<1>:d r27.1<0;1,0>:d 6:d // write Buf_0 to 1st quarter of four horizontal output blocks // Please note the scattered order of NODDCLR, NODDCHK flags. Since the sub-registers // of destination reg are not updated at one place and hence even flags are scattered. -rT mov (8) mubMSGPAYLOAD0(0, 0)<4> r[a0.2, 1]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD0(0, 1)<4> r[a0.1, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD0(0, 2)<4> r[a0.0, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD0(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD0(1, 0)<4> r[a0.2, 33]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD0(1, 1)<4> r[a0.1, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD0(1, 2)<4> r[a0.0, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD0(1, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(0, 0)<4> r[a0.6, 1]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD1(0, 1)<4> r[a0.5, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(0, 2)<4> r[a0.4, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(1, 0)<4> r[a0.6, 33]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD1(1, 1)<4> r[a0.5, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(1, 2)<4> r[a0.4, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(1, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD2(0, 0)<4> r[a0.2, 17]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD2(0, 1)<4> r[a0.1, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(0, 2)<4> r[a0.0, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD2(1, 0)<4> r[a0.2, 49]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD2(1, 1)<4> r[a0.1, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(1, 2)<4> r[a0.0, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(1, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD3(0, 0)<4> r[a0.6, 17]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD3(0, 1)<4> r[a0.5, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD3(0, 2)<4> r[a0.4, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD3(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD3(1, 0)<4> r[a0.6, 49]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD3(1, 1)<4> r[a0.5, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD3(1, 2)<4> r[a0.4, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD3(1, 3)<4> r2.31:ub { NoDDChk } // write Buf_1 to 2nd quarter of four horizontal output blocks add (4) a0.0:uw r22.0<4;4,1>:w 512:uw // pointer swap (f0.0) mov (1) uwTemp0<1> a0.0:uw (f0.0) mov (1) a0.0:uw a0.2:uw (f0.0) mov (1) a0.2:uw uwTemp0<0;1,0> add (4) a0.4:uw a0.0<4;4,1>:w r22.8<0;2,1>:w mov (8) mubMSGPAYLOAD4(0, 0)<4> r[a0.2, 1]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD4(0, 1)<4> r[a0.1, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD4(0, 2)<4> r[a0.0, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD4(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD4(1, 0)<4> r[a0.2, 33]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD4(1, 1)<4> r[a0.1, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD4(1, 2)<4> r[a0.0, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD4(1, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD5(0, 0)<4> r[a0.6, 1]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD5(0, 1)<4> r[a0.5, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD5(0, 2)<4> r[a0.4, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD5(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD5(1, 0)<4> r[a0.6, 33]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD5(1, 1)<4> r[a0.5, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD5(1, 2)<4> r[a0.4, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD5(1, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD6(0, 0)<4> r[a0.2, 17]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD6(0, 1)<4> r[a0.1, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD6(0, 2)<4> r[a0.0, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD6(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD6(1, 0)<4> r[a0.2, 49]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD6(1, 1)<4> r[a0.1, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD6(1, 2)<4> r[a0.0, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD6(1, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD7(0, 0)<4> r[a0.6, 17]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD7(0, 1)<4> r[a0.5, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD7(0, 2)<4> r[a0.4, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD7(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD7(1, 0)<4> r[a0.6, 49]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD7(1, 1)<4> r[a0.5, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD7(1, 2)<4> r[a0.4, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD7(1, 3)<4> r2.31:ub { NoDDChk } // send buffer 0 and buffer 1 send (1) null<1>:d r28 0x5 0x60A8018:ud send (1) null<1>:d r37 0x5 0x60A8018:ud send (1) null<1>:d r46 0x5 0x60A8018:ud send (1) null<1>:d r55 0x5 0x60A8018:ud send (1) null<1>:d r31 0x5 0x60A8018:ud send (1) null<1>:d r40 0x5 0x60A8018:ud send (1) null<1>:d r49 0x5 0x60A8018:ud send (1) null<1>:d r58 0x5 0x60A8018:ud //========== //prepare headers //for BUFFER 2 add (1) r28.1<1>:d r27.1<0;1,0>:d 8:d add (1) r37.1<1>:d r27.1<0;1,0>:d 10:d add (1) r46.0<1>:d r27.0<0;1,0>:d 32:d add (1) r46.1<1>:d r27.1<0;1,0>:d 8:d add (1) r55.0<1>:d r27.0<0;1,0>:d 32:d add (1) r55.1<1>:d r27.1<0;1,0>:d 10:d // for BUFFER 3 add (1) r31.1<1>:d r27.1<0;1,0>:d 12:d add (1) r40.1<1>:d r27.1<0;1,0>:d 14:d add (1) r49.0<1>:d r27.0<0;1,0>:d 32:d add (1) r49.1<1>:d r27.1<0;1,0>:d 12:d add (1) r58.0<1>:d r27.0<0;1,0>:d 32:d add (1) r58.1<1>:d r27.1<0;1,0>:d 14:d //=========== // write Buf_2 to 3rd quarter of four horizontal output blocks add (4) a0.0:uw r22.0<4;4,1>:w 1024:uw // pointer swap (f0.0) mov (1) uwTemp0<1> a0.0:uw (f0.0) mov (1) a0.0:uw a0.2:uw (f0.0) mov (1) a0.2:uw uwTemp0<0;1,0> add (4) a0.4:uw a0.0<4;4,1>:w r22.8<0;2,1>:w mov (8) mubMSGPAYLOAD0(0, 0)<4> r[a0.2, 1]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD0(0, 1)<4> r[a0.1, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD0(0, 2)<4> r[a0.0, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD0(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD0(1, 0)<4> r[a0.2, 33]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD0(1, 1)<4> r[a0.1, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD0(1, 2)<4> r[a0.0, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD0(1, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(0, 0)<4> r[a0.6, 1]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD1(0, 1)<4> r[a0.5, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(0, 2)<4> r[a0.4, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(1, 0)<4> r[a0.6, 33]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD1(1, 1)<4> r[a0.5, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(1, 2)<4> r[a0.4, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(1, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD2(0, 0)<4> r[a0.2, 17]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD2(0, 1)<4> r[a0.1, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(0, 2)<4> r[a0.0, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD2(1, 0)<4> r[a0.2, 49]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD2(1, 1)<4> r[a0.1, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(1, 2)<4> r[a0.0, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(1, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD3(0, 0)<4> r[a0.6, 17]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD3(0, 1)<4> r[a0.5, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD3(0, 2)<4> r[a0.4, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD3(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD3(1, 0)<4> r[a0.6, 49]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD3(1, 1)<4> r[a0.5, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD3(1, 2)<4> r[a0.4, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD3(1, 3)<4> r2.31:ub { NoDDChk } // write Buf_3 to 4th quarter of four horizontal output blocks add (4) a0.0:uw r22.0<4;4,1>:w 1536:uw // pointer swap (f0.0) mov (1) uwTemp0<1> a0.0:uw (f0.0) mov (1) a0.0:uw a0.2:uw (f0.0) mov (1) a0.2:uw uwTemp0<0;1,0> add (4) a0.4:uw a0.0<4;4,1>:w r22.8<0;2,1>:w mov (8) mubMSGPAYLOAD4(0, 0)<4> r[a0.2, 1]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD4(0, 1)<4> r[a0.1, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD4(0, 2)<4> r[a0.0, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD4(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD4(1, 0)<4> r[a0.2, 33]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD4(1, 1)<4> r[a0.1, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD4(1, 2)<4> r[a0.0, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD4(1, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD5(0, 0)<4> r[a0.6, 1]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD5(0, 1)<4> r[a0.5, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD5(0, 2)<4> r[a0.4, 1]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD5(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD5(1, 0)<4> r[a0.6, 33]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD5(1, 1)<4> r[a0.5, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD5(1, 2)<4> r[a0.4, 33]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD5(1, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD6(0, 0)<4> r[a0.2, 17]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD6(0, 1)<4> r[a0.1, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD6(0, 2)<4> r[a0.0, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD6(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD6(1, 0)<4> r[a0.2, 49]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD6(1, 1)<4> r[a0.1, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD6(1, 2)<4> r[a0.0, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD6(1, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD7(0, 0)<4> r[a0.6, 17]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD7(0, 1)<4> r[a0.5, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD7(0, 2)<4> r[a0.4, 17]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD7(0, 3)<4> r2.31:ub { NoDDChk } mov (8) mubMSGPAYLOAD7(1, 0)<4> r[a0.6, 49]<16;8,2> { NoDDClr } mov (8) mubMSGPAYLOAD7(1, 1)<4> r[a0.5, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD7(1, 2)<4> r[a0.4, 49]<16;8,2> { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD7(1, 3)<4> r2.31:ub { NoDDChk } // send buffer 2 and buffer 3 send (1) null<1>:d r28 0x5 0x60A8018:ud send (1) null<1>:d r37 0x5 0x60A8018:ud send (1) null<1>:d r46 0x5 0x60A8018:ud send (1) null<1>:d r55 0x5 0x60A8018:ud send (1) null<1>:d r31 0x5 0x60A8018:ud send (1) null<1>:d r40 0x5 0x60A8018:ud send (1) null<1>:d r49 0x5 0x60A8018:ud send (1) null<1>:d r58 0x5 0x60A8018:ud intel-driver-1.3.0/src/shaders/post_processing/gen7/Save_AVS_RGBX.g4a000066400000000000000000000573461231401140700252560ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * Authors: * Zhao Yakui */ // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: Save_AVS_RGBX.asm // // Save packed ARGB 444 frame data block of size 16x16 // // To save 16x16 block (64x16 byte layout for ARGB8888) we need 4 send instructions with 32x8 in each // -------- // | 0 | 1 | // | 2 | 3 | // --------- // the 4 32x8 block send is used // Module name: Save.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written .declare mudMSGPAYLOAD0 Base=r29.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD1 Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD2 Base=r47.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD3 Base=r56.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare muwMSGPAYLOAD0 Base=r29.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD1 Base=r38.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD2 Base=r47.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD3 Base=r56.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mubMSGPAYLOAD0 Base=r29.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD1 Base=r38.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD2 Base=r47.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD3 Base=r56.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD4 Base=r32.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD5 Base=r41.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD6 Base=r50.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD7 Base=r59.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ // At the save module we have all 8 address sub-registers available. // So we will use PING-PONG type of scheme to save the data using // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help // reduce dependency. - rT //Internal LAYOUT:(RRGGBBAA) //Assign buffer channel order for Buffer 0123 in the order RGBA a0.3>A, a0.2>B, a0.1>G, a0.0>R // R = 0, G= 4, B = 8, A = 12. mov (4) acc0.0<1>:w 0x62EA:v add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw // if channel swap? // This means that it should be BGRA(B is the LSB) or RGBA // the internal format is always RGBA(MSB-A-B-G-R). and.nz.f0.0 null<1>:w r2.3<0;1,0>:uw 0x01:w //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4. //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5). //Offsets are zero for buffer 0 and buffer 4. add (4) a0.0:uw r22.0<4;4,1>:w 0:uw // pointer swap (f0.0) mov (1) uwTemp0<1> a0.0<0;1,0>:uw (f0.0) mov (1) a0.0<1>:uw a0.2<0;1,0>:uw (f0.0) mov (1) a0.2<1>:uw uwTemp0<0;1,0> shl (1) r27.0<1>:d r7.0<0;1,0>:w 2:w { NoDDClr } // H. block origin need to be quadrupled mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin (1st quadrant) mov (1) r27.2<1>:ud 0x3001F:ud { NoDDChk } // Block width and height (32x4) mov (4) a0.4<1>:uw a0.0<4;4,1>:uw mov (8) r28<1>:ud r27<8;8,1>:ud mov (8) r37<1>:ud r27<8;8,1>:ud mov (8) r46<1>:ud r27<8;8,1>:ud mov (8) r55<1>:ud r27<8;8,1>:ud mov (8) r31<1>:ud r27<8;8,1>:ud mov (8) r40<1>:ud r27<8;8,1>:ud mov (8) r49<1>:ud r27<8;8,1>:ud mov (8) r58<1>:ud r27<8;8,1>:ud //Buffer 0/1 are written by using 4 32x4. add (1) r37.0<1>:d r27.0<0;1,0>:d 32:d add (1) r46.1<1>:d r27.1<0;1,0>:d 4:d add (1) r55.1<1>:d r27.1<0;1,0>:d 4:d add (1) r55.0<1>:d r27.0<0;1,0>:d 32:d // write Buf_0 to 1st quarter of four horizontal output blocks // Please note the scattered order of NODDCLR, NODDCHK flags. Since the sub-registers // of destination reg are not updated at one place and hence even flags are scattered. -rT /* for block 0 the left part of buffer 0 and 1 */ mov (8) mubMSGPAYLOAD0(0, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(1, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(0, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(1, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(2, 0)<4> r[a0.0, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 1)<4> r[a0.1, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 2)<4> r[a0.2, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(3, 0)<4> r[a0.0, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 1)<4> r[a0.1, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 2)<4> r[a0.2, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(2, 0)<4> r[a0.0, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 1)<4> r[a0.1, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 2)<4> r[a0.2, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(3, 0)<4> r[a0.0, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 1)<4> r[a0.1, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 2)<4> r[a0.2, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 3)<4> r2.31:ub /* For Buffer 0 */ send (16) null<1>:d r28 0x5 0x0A0A8018:ud send (16) null<1>:d r37 0x5 0x0A0A8018:ud add (4) a0.0<1>:uw a0.4<4;4,1>:uw 512:uw mov (8) mubMSGPAYLOAD2(0, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(1, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(0, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(1, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(2, 0)<4> r[a0.0, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 1)<4> r[a0.1, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 2)<4> r[a0.2, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(3, 0)<4> r[a0.0, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 1)<4> r[a0.1, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 2)<4> r[a0.2, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(2, 0)<4> r[a0.0, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 1)<4> r[a0.1, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 2)<4> r[a0.2, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(3, 0)<4> r[a0.0, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 1)<4> r[a0.1, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 2)<4> r[a0.2, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 3)<4> r2.31:ub // send Buffer 1 send (16) null<1>:d r46 0x5 0x0A0A8018:ud send (16) null<1>:d r55 0x5 0x0A0A8018:ud /* for Buffer 2/3 */ mov (8) r28<1>:ud r27<8;8,1>:ud mov (8) r37<1>:ud r27<8;8,1>:ud mov (8) r46<1>:ud r27<8;8,1>:ud mov (8) r55<1>:ud r27<8;8,1>:ud add (1) r28.1<1>:d r27.1<0;1,0>:d 8:d add (1) r37.0<1>:d r27.0<0;1,0>:d 32:d add (1) r37.1<1>:d r27.1<0;1,0>:d 8:d add (1) r46.1<1>:d r27.1<0;1,0>:d 12:d add (1) r55.1<1>:d r27.1<0;1,0>:d 12:d add (1) r55.0<1>:d r27.0<0;1,0>:d 32:d add (4) a0.0<1>:uw a0.4<4;4,1>:uw 1024:uw mov (8) mubMSGPAYLOAD0(0, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(1, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(0, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(1, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(2, 0)<4> r[a0.0, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 1)<4> r[a0.1, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 2)<4> r[a0.2, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(3, 0)<4> r[a0.0, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 1)<4> r[a0.1, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 2)<4> r[a0.2, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(2, 0)<4> r[a0.0, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 1)<4> r[a0.1, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 2)<4> r[a0.2, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(3, 0)<4> r[a0.0, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 1)<4> r[a0.1, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 2)<4> r[a0.2, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 3)<4> r2.31:ub // Send Buffer 2 send (16) null<1>:d r28 0x5 0x0A0A8018:ud send (16) null<1>:d r37 0x5 0x0A0A8018:ud add (4) a0.0<1>:uw a0.4<4;4,1>:uw 1536:uw mov (8) mubMSGPAYLOAD2(0, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(1, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(0, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(1, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(2, 0)<4> r[a0.0, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 1)<4> r[a0.1, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 2)<4> r[a0.2, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(3, 0)<4> r[a0.0, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 1)<4> r[a0.1, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 2)<4> r[a0.2, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(2, 0)<4> r[a0.0, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 1)<4> r[a0.1, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 2)<4> r[a0.2, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(3, 0)<4> r[a0.0, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 1)<4> r[a0.1, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 2)<4> r[a0.2, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 3)<4> r2.31:ub // send buffer 3 send (16) null<1>:d r46 0x5 0x0A0A8018:ud send (16) null<1>:d r55 0x5 0x0A0A8018:ud intel-driver-1.3.0/src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a000066400000000000000000000274431231401140700263200ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 7 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Module Name: Set_AVS_Buf_0123_BGRA.asm //Module Name: Set_Buf_0123_BGRA // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //AVS LAYOUT:(UUYYVVAA) //AVS RGBX LAYOUT (RRGGBBAA) //Assign buffer channel order for Buffer 0123 in the order AUYV a0.3>A, a0.2>U, a0.1>Y, a0.0>V // V = 8, Y= 0, U = 4, A = 12. // And a0.x is used as indirect-register for RGBX. R=a0.1, G=a0.2, B=a0.0 // B = 8, R= 0, G = 4, A = 12 mov (4) acc0.0<1>:w 0x6EA2:v add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw //OPT: wAVS_SU_SHUFFLE_PTR_0 and udAVS_SU_SHUFFLE_OFF_0 are sub-regs of same GRF. -rT //SU LAYOUT:(VYUAVYUA) //V = 4, Y = 2, U = 0, A = 6 //B = 4, G = 2, R = 0, A = 6 mov (4) acc0.0<1>:w 0x6204:v add (4) acc0.0<1>:w acc0<4;4,1>:w 64:uw shl (4) r18.0<1>:w acc0<4;4,1>:w 5:uw { NoDDClr } //Convert to BYTE address. //OFFSET: mov (1) r18.4<1>:ud 0x1000100:ud { NoDDChk } intel-driver-1.3.0/src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a000066400000000000000000000270501231401140700261740ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 7 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Module Name: Set_AVS_Buf_0123_PL2.asm //Module Name: Set_Buf_0123_PL2 // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //AVS LAYOUT: (YYUUVVAA) //Assign buffer channel order for Buffer 0123 in the order AUYV a0.3>A, a0.2>U, a0.1>Y, a0.0>V //For PL2-AVS: V = 8, Y= 0, U = 4, A = 12. mov (4) acc0.0<1>:w 0x6EA2:v //Subtract 6 from 0,4,8,12 add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw //add 6 back shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw //Convert to BYTE address. //OPT: wAVS_SU_SHUFFLE_PTR_0 and udAVS_SU_SHUFFLE_OFF_0 are sub-regs of same GRF. -rT //SU LAYOUT:(YUVAYUVA) //V = 4, Y = 0, U = 2, A = 6 mov (4) acc0.0<1>:w 0x6204:v add (4) acc0.0<1>:w acc0<4;4,1>:w 64:uw shl (4) r18.0<1>:w acc0<4;4,1>:w 5:uw { NoDDClr } //Convert to BYTE address. //OFFSET: mov (1) r18.4<1>:ud 0x1000100:ud { NoDDChk } intel-driver-1.3.0/src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a000066400000000000000000000273571231401140700262070ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 7 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Module Name: Set_AVS_Buf_0123_PL3.asm //Module Name: Set_Buf_0123_PL3 // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //AVS LAYOUT: (YYUUVVAA) //Assign buffer channel order for Buffer 0123 in the order AUYV a0.3>A, a0.2>U, a0.1>Y, a0.0>V //For PL3-AVS: V = 8, Y= 0, U = 4, A = 12. mov (4) acc0.0<1>:w 0x6EA2:v //Subtract 6 from 0,4,8,12 add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw //add 6 back shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw //Convert to BYTE address. //OPT: wAVS_SU_SHUFFLE_PTR_0 and udAVS_SU_SHUFFLE_OFF_0 are sub-regs of same GRF. -rT //SU LAYOUT:(YUVAYUVA) //V = 4, Y = 0, U = 2, A = 6 mov (4) acc0.0<1>:w 0x6204:v add (4) acc0.0<1>:w acc0<4;4,1>:w 64:uw shl (4) r18.0<1>:w acc0<4;4,1>:w 5:uw { NoDDClr } //Convert to BYTE address. //OFFSET: mov (1) r18.4<1>:ud 0x1000100:ud { NoDDChk } intel-driver-1.3.0/src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a000066400000000000000000000271671231401140700263740ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 7 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Module Name: Set_AVS_Buf_0123_YUVA.asm // Module Name : Set_Buf_0123_VUYA // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //For AVS: We use surface state as R8G8B8A8_UNORM and hence set pointers to VUYA. //AVS LAYOUT:(VVUUYYAA) //Assign buffer channel order for Buffer 0123 in the order AUYV a0.3>A, a0.2>U, a0.1>Y, a0.0>V //V = 0, Y= 8, U = 4, A = 12. mov (4) acc0.0<1>:w 0x6E2A:v add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw //Used by Shuffle. //SU LAYOUT:(VUYAVUYA) //V = 0, Y = 4, U = 2, A = 6 mov (4) acc0.0<1>:w 0x6240:v add (4) acc0.0<1>:w acc0<4;4,1>:w 64:uw shl (4) r18.0<1>:w acc0<4;4,1>:w 5:uw { NoDDClr } //Convert to BYTE address. //OFFSET: mov (1) r18.4<1>:ud 0x1000100:ud { NoDDChk } intel-driver-1.3.0/src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a000066400000000000000000000273461231401140700263730ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 7 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Module Name: Set_AVS_Buf_0123_VYUA.asm //Module Name: Set_Buf_0123_VYUA // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //AVS LAYOUT:(VVYYUUAA) //Assign buffer channel order for Buffer 0123 in the order AUYV a0.3>A, a0.2>U, a0.1>Y, a0.0>V // V = 0, Y= 4, U = 8, A = 12. mov (4) acc0.0<1>:w 0x62EA:v //Subtract 6 from 0,4,8,12 add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw //add 6 back shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw //Convert to BYTE address. //OPT: wAVS_SU_SHUFFLE_PTR_0 and udAVS_SU_SHUFFLE_OFF_0 are sub-regs of same GRF. -rT //SU LAYOUT:(VYUAVYUA) //V = 0, Y = 2, U = 4, A = 6 mov (4) acc0.0<1>:w 0x6420:v add (4) acc0.0<1>:w acc0<4;4,1>:w 64:uw shl (4) r18.0<1>:w acc0<4;4,1>:w 5:uw { NoDDClr } //Convert to BYTE address. //OFFSET: mov (1) r18.4<1>:ud 0x1000100:ud { NoDDChk } intel-driver-1.3.0/src/shaders/post_processing/gen7/Set_Layer_0.g4a000066400000000000000000000363301231401140700251210ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 18 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Module name: Set_Layer_N.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Used to generate LABELS at compile time. //definitions for Expand Mask .declare uwMask_Temp1 Base=r17.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF .declare ubMask_Temp1 Base=r17.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // 1 GRF .declare udMask_Temp1 Base=r17.0 ElementSize=4 Type=ud // 1 GRF .declare uwMask_Temp2 Base=r16.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF .declare ubMask_Temp2 Base=r16.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // 1 GRF .declare udMask_Temp2 Base=r16.0 ElementSize=4 Type=ud // 1 GRF .declare uwMask_Temp3 Base=r15.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF .declare ubMask_Temp3 Base=r15.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // 1 GRF .declare udALPHA_MASK_REG Base=r21.0 ElementSize=4 Type=ud // 1 GRF .declare udALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=4 Type=ud // 1 GRF //Initialize mask reg to FFFF mov (16) uwALPHA_MASK_REG(0)<1> 0xFFFF:uw //Fast jump for - //LAYER0: we determine whether layer 0 is to be loaded and processed or not based // on block mask in module "Set_Layer_0" and store result in f0.1. // This flag is then directly used to while loading buf0-3 and colorfill. // (So flag f0.1 should not be changed from Set_Layer_0 till Colorfill) // //LAYER1-7: For all other layers, we compute whether layer is to be loaded and processed // based on block mask in module "Set_Layer_1-7" and store result in SKIP_LAYER // variable. // While Loading buf 4 and 5, we move SKIP_LAYER to f0.0 every time and use it // for Loading. // For processing though, we move SKIP_LAYER only once to f0.1 in module // "Set_Buf0_Buf4" and use f0.1 for deciding whether layer 1-7 (all 4 sub blocks) // is to be processed or not. // (So flag f0.1) should not be modififed from module "Set_Buf0_Buf4" till module // that processess sub-block 3). // //None of the above fast jumps, apply to CSC modules. We always perform CSC irrespective of mask. // //Example: (Without going into finer details) // Typical Combined kernel: // // (let var = decision whether to load/process that layer) // // Set_Layer_0 //f0.1 <- var // .. // Set_Layer_1 //f0.1 <- var, SKIP_LAYER <- var // .. // Load buf 0 //use f0.1 // Load buf 4 //f0.0 <- SKIP_LAYER // Load buf 1 //use f0.1 // Load buf 5 //f0.0 <- SKIP_LAYER // Load buf 2 //use f0.1 // Load buf 3 //use f0.1 // .. // .. // Colorfill // .. // Set_Buf0_Buf4 //f0.1 <- SKIP_LAYER // process0-4 //Use f0.1 // Load buf 4 // Set_Buf1_Buf5 // process1-5 // Load buf 5 // .. // Set_Layer_2 //f0.1 <-var, SKIP_LAYER <- var // .. // Set_Buf2_Buf4 // process2-4 // Load buf 4 // Set_Buf3_Buf5 // process3-5 // Load buf 5 // .. //For layer 0, use f0.1 directly cmp.ne.f0.1 (1) null<1>:d r7.2:uw 0:uw (f0.1)cmp.ne.f0.1 (1) null<1>:d r7.3:uw 0:uw (-f0.1) jmpi (1) SKIP_LAYER_L0 and (1) r24.2:ub r2.2<0;1,0>:uw 3:uw //Copy all AVS Payload data // Setup Message Payload Header for 1st block of Media Sampler 8x8 (16x4 for IVB+) mov (1) r25.6:f r7.5:f { NoDDClr } //NLAS dx mov (1) r25.4:f r3.0:f { NoDDClr, NoDDChk } //Step X mov (1) r25.5:f r4.0:f { NoDDClr, NoDDChk } //Step Y mov (1) r25.2:f r6.0<0;1,0>:f { NoDDClr, NoDDChk } //Orig X mov (1) r25.3:f r5.0<0;1,0>:f { NoDDChk } //Orig Y //NLAS calculations for 2nd half of blocks of Media Sampler 8x8: // X(i) = X0 + dx*i + ddx*i*(i-1)/2 ==> X(8) = X0 + dx*8 +ddx*28 // dx(i)= dx(0) + ddx*i ==> dx(8)= dx + ddx*8 //OPTIMIZATION: fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY - are sub registers of same GRF. Use NODDCLR NODDCHK. -rT // Calculating X(8) mov (1) acc0.2:f r6.0:f mac (1) acc0.2:f r3.0:f 8.0:f mac (1) r23.2:f r7.5:f 28.0:f { NoDDClr } // Calculating Y(4) mul (1) r23.1<1>:f r4.0:f 4.0:f { NoDDClr, NoDDChk } //dY*4 // Calculating dx(8) mov (1) acc0.4:f r3.0:f mac (1) r23.4:f r7.5:f 8.0:f { NoDDClr, NoDDChk } // Binding Index mov (1) r23.5:ud 0:ud { NoDDChk } SKIP_LAYER_L0: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/VP_Setup.g4a000066400000000000000000000761201231401140700245210ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 326 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: VP_Setup.asm // Author: Vivek Kumar // Description: Sets up all parameters for the Video Processing Kernel // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Setup pointer to the inline parameter // Copy MSG HDR mov (8) r27.0<1>:ud r0.0<8;8,1>:ud // Initialize message payload header with R0 //temp; remove it once unread msg warnings are resolved -vK mov (8) r25:ud r0.0<8;8,1>:ud mov (8) r26:ud r0.0<8;8,1>:ud // Calculate StepX for all layers and overwrite it on the ratio mul (8) r3.0<1>:f r3.0<8;8,1>:f r7.4<0;1,0>:f //StepX_ratio = StepX / VideoStepX //Normalised Ratio of Horizontal step size with main video for all layers now becomes //Normalised Horizontal step size for all layers // Calculate block origin for all layers and overwrite it on the frame origin mov (2) r8.5<1>:f r7.0<2;2,1>:w //Convert origin from word to float cmp.e.f0.0 (8) null<1>:d r2.26:ub 1:uw shr (1) r17.0<1>:uw r2.2<0;1,0>:uw 0:uw and (1) r17.0<1>:uw r17.0<0;1,0>:uw 3:uw cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 1:uw (f0.1) jmpi (1) ROTATE_90_L0 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 2:uw (f0.1) jmpi (1) ROTATE_180_L0 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 3:uw (f0.1) jmpi (1) ROTATE_270_L0 // rotate 0 degree ROTATE_0_L0: (-f0.0)mov (1) acc0.0:f r6.0<0;1,0>:f (-f0.0)mac (1) r6.0<1>:f r3.0<0;1,0>:f r8.5<0;1,0>:f mov (1) acc0.0:f r5.0<0;1,0>:f mac (1) r5.0<1>:f r4.0<0;1,0>:f r8.6<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L0 // rotate 90 degree ROTATE_90_L0: (-f0.0)mov (1) acc0.0:f r6.0<0;1,0>:f (-f0.0)mac (1) r6.0<1>:f r3.0<0;1,0>:f r8.6<0;1,0>:f mov (1) r16.0<1>:f r2.0<0;1,0>:uw add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.0:f r5.0<0;1,0>:f mac (1) r5.0<1>:f r4.0<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L0 // rotate 180 degree ROTATE_180_L0: (-f0.0)mov (1) r16.0<1>:f r2.0<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.0:f r6.0<0;1,0>:f (-f0.0)mac (1) r6.0<1>:f r3.0<0;1,0>:f r17.0<0;1,0>:f mov (1) r16.0<1>:f r2.1<0;1,0>:uw add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.0:f r5.0<0;1,0>:f mac (1) r5.0<1>:f r4.0<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L0 // rotate 270 degree ROTATE_270_L0: (-f0.0)mov (1) r16.0<1>:f r2.1<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.0:f r6.0<0;1,0>:f (-f0.0)mac (1) r6.0<1>:f r3.0<0;1,0>:f r17.0<0;1,0>:f mov (1) acc0.0:f r5.0<0;1,0>:f mac (1) r5.0<1>:f r4.0<0;1,0>:f r8.5<0;1,0>:f END_SRC_BLOCK_ORIG_COMP_L0: nop shr (1) r17.0<1>:uw r2.2<0;1,0>:uw 2:uw and (1) r17.0<1>:uw r17.0<0;1,0>:uw 3:uw cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 1:uw (f0.1) jmpi (1) ROTATE_90_L1 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 2:uw (f0.1) jmpi (1) ROTATE_180_L1 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 3:uw (f0.1) jmpi (1) ROTATE_270_L1 // rotate 0 degree ROTATE_0_L1: (-f0.0)mov (1) acc0.1:f r6.1<0;1,0>:f (-f0.0)mac (1) r6.1<1>:f r3.1<0;1,0>:f r8.5<0;1,0>:f mov (1) acc0.1:f r5.1<0;1,0>:f mac (1) r5.1<1>:f r4.1<0;1,0>:f r8.6<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L1 // rotate 90 degree ROTATE_90_L1: (-f0.0)mov (1) acc0.1:f r6.1<0;1,0>:f (-f0.0)mac (1) r6.1<1>:f r3.1<0;1,0>:f r8.6<0;1,0>:f mov (1) r16.0<1>:f r2.0<0;1,0>:uw add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.1:f r5.1<0;1,0>:f mac (1) r5.1<1>:f r4.1<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L1 // rotate 180 degree ROTATE_180_L1: (-f0.0)mov (1) r16.0<1>:f r2.0<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.1:f r6.1<0;1,0>:f (-f0.0)mac (1) r6.1<1>:f r3.1<0;1,0>:f r17.0<0;1,0>:f mov (1) r16.0<1>:f r2.1<0;1,0>:uw add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.1:f r5.1<0;1,0>:f mac (1) r5.1<1>:f r4.1<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L1 // rotate 270 degree ROTATE_270_L1: (-f0.0)mov (1) r16.0<1>:f r2.1<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.1:f r6.1<0;1,0>:f (-f0.0)mac (1) r6.1<1>:f r3.1<0;1,0>:f r17.0<0;1,0>:f mov (1) acc0.1:f r5.1<0;1,0>:f mac (1) r5.1<1>:f r4.1<0;1,0>:f r8.5<0;1,0>:f END_SRC_BLOCK_ORIG_COMP_L1: nop shr (1) r17.0<1>:uw r2.2<0;1,0>:uw 4:uw and (1) r17.0<1>:uw r17.0<0;1,0>:uw 3:uw cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 1:uw (f0.1) jmpi (1) ROTATE_90_L2 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 2:uw (f0.1) jmpi (1) ROTATE_180_L2 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 3:uw (f0.1) jmpi (1) ROTATE_270_L2 // rotate 0 degree ROTATE_0_L2: (-f0.0)mov (1) acc0.2:f r6.2<0;1,0>:f (-f0.0)mac (1) r6.2<1>:f r3.2<0;1,0>:f r8.5<0;1,0>:f mov (1) acc0.2:f r5.2<0;1,0>:f mac (1) r5.2<1>:f r4.2<0;1,0>:f r8.6<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L2 // rotate 90 degree ROTATE_90_L2: (-f0.0)mov (1) acc0.2:f r6.2<0;1,0>:f (-f0.0)mac (1) r6.2<1>:f r3.2<0;1,0>:f r8.6<0;1,0>:f mov (1) r16.0<1>:f r2.0<0;1,0>:uw add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.2:f r5.2<0;1,0>:f mac (1) r5.2<1>:f r4.2<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L2 // rotate 180 degree ROTATE_180_L2: (-f0.0)mov (1) r16.0<1>:f r2.0<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.2:f r6.2<0;1,0>:f (-f0.0)mac (1) r6.2<1>:f r3.2<0;1,0>:f r17.0<0;1,0>:f mov (1) r16.0<1>:f r2.1<0;1,0>:uw add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.2:f r5.2<0;1,0>:f mac (1) r5.2<1>:f r4.2<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L2 // rotate 270 degree ROTATE_270_L2: (-f0.0)mov (1) r16.0<1>:f r2.1<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.2:f r6.2<0;1,0>:f (-f0.0)mac (1) r6.2<1>:f r3.2<0;1,0>:f r17.0<0;1,0>:f mov (1) acc0.2:f r5.2<0;1,0>:f mac (1) r5.2<1>:f r4.2<0;1,0>:f r8.5<0;1,0>:f END_SRC_BLOCK_ORIG_COMP_L2: nop shr (1) r17.0<1>:uw r2.2<0;1,0>:uw 6:uw and (1) r17.0<1>:uw r17.0<0;1,0>:uw 3:uw cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 1:uw (f0.1) jmpi (1) ROTATE_90_L3 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 2:uw (f0.1) jmpi (1) ROTATE_180_L3 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 3:uw (f0.1) jmpi (1) ROTATE_270_L3 // rotate 0 degree ROTATE_0_L3: (-f0.0)mov (1) acc0.3:f r6.3<0;1,0>:f (-f0.0)mac (1) r6.3<1>:f r3.3<0;1,0>:f r8.5<0;1,0>:f mov (1) acc0.3:f r5.3<0;1,0>:f mac (1) r5.3<1>:f r4.3<0;1,0>:f r8.6<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L3 // rotate 90 degree ROTATE_90_L3: (-f0.0)mov (1) acc0.3:f r6.3<0;1,0>:f (-f0.0)mac (1) r6.3<1>:f r3.3<0;1,0>:f r8.6<0;1,0>:f mov (1) r16.0<1>:f r2.0<0;1,0>:uw add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.3:f r5.3<0;1,0>:f mac (1) r5.3<1>:f r4.3<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L3 // rotate 180 degree ROTATE_180_L3: (-f0.0)mov (1) r16.0<1>:f r2.0<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.3:f r6.3<0;1,0>:f (-f0.0)mac (1) r6.3<1>:f r3.3<0;1,0>:f r17.0<0;1,0>:f mov (1) r16.0<1>:f r2.1<0;1,0>:uw add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.3:f r5.3<0;1,0>:f mac (1) r5.3<1>:f r4.3<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L3 // rotate 270 degree ROTATE_270_L3: (-f0.0)mov (1) r16.0<1>:f r2.1<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.3:f r6.3<0;1,0>:f (-f0.0)mac (1) r6.3<1>:f r3.3<0;1,0>:f r17.0<0;1,0>:f mov (1) acc0.3:f r5.3<0;1,0>:f mac (1) r5.3<1>:f r4.3<0;1,0>:f r8.5<0;1,0>:f END_SRC_BLOCK_ORIG_COMP_L3: nop shr (1) r17.0<1>:uw r2.2<0;1,0>:uw 8:uw and (1) r17.0<1>:uw r17.0<0;1,0>:uw 3:uw cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 1:uw (f0.1) jmpi (1) ROTATE_90_L4 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 2:uw (f0.1) jmpi (1) ROTATE_180_L4 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 3:uw (f0.1) jmpi (1) ROTATE_270_L4 // rotate 0 degree ROTATE_0_L4: (-f0.0)mov (1) acc0.4:f r6.4<0;1,0>:f (-f0.0)mac (1) r6.4<1>:f r3.4<0;1,0>:f r8.5<0;1,0>:f mov (1) acc0.4:f r5.4<0;1,0>:f mac (1) r5.4<1>:f r4.4<0;1,0>:f r8.6<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L4 // rotate 90 degree ROTATE_90_L4: (-f0.0)mov (1) acc0.4:f r6.4<0;1,0>:f (-f0.0)mac (1) r6.4<1>:f r3.4<0;1,0>:f r8.6<0;1,0>:f mov (1) r16.0<1>:f r2.0<0;1,0>:uw add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.4:f r5.4<0;1,0>:f mac (1) r5.4<1>:f r4.4<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L4 // rotate 180 degree ROTATE_180_L4: (-f0.0)mov (1) r16.0<1>:f r2.0<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.4:f r6.4<0;1,0>:f (-f0.0)mac (1) r6.4<1>:f r3.4<0;1,0>:f r17.0<0;1,0>:f mov (1) r16.0<1>:f r2.1<0;1,0>:uw add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.4:f r5.4<0;1,0>:f mac (1) r5.4<1>:f r4.4<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L4 // rotate 270 degree ROTATE_270_L4: (-f0.0)mov (1) r16.0<1>:f r2.1<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.4:f r6.4<0;1,0>:f (-f0.0)mac (1) r6.4<1>:f r3.4<0;1,0>:f r17.0<0;1,0>:f mov (1) acc0.4:f r5.4<0;1,0>:f mac (1) r5.4<1>:f r4.4<0;1,0>:f r8.5<0;1,0>:f END_SRC_BLOCK_ORIG_COMP_L4: nop shr (1) r17.0<1>:uw r2.2<0;1,0>:uw 10:uw and (1) r17.0<1>:uw r17.0<0;1,0>:uw 3:uw cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 1:uw (f0.1) jmpi (1) ROTATE_90_L5 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 2:uw (f0.1) jmpi (1) ROTATE_180_L5 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 3:uw (f0.1) jmpi (1) ROTATE_270_L5 // rotate 0 degree ROTATE_0_L5: (-f0.0)mov (1) acc0.5:f r6.5<0;1,0>:f (-f0.0)mac (1) r6.5<1>:f r3.5<0;1,0>:f r8.5<0;1,0>:f mov (1) acc0.5:f r5.5<0;1,0>:f mac (1) r5.5<1>:f r4.5<0;1,0>:f r8.6<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L5 // rotate 90 degree ROTATE_90_L5: (-f0.0)mov (1) acc0.5:f r6.5<0;1,0>:f (-f0.0)mac (1) r6.5<1>:f r3.5<0;1,0>:f r8.6<0;1,0>:f mov (1) r16.0<1>:f r2.0<0;1,0>:uw add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.5:f r5.5<0;1,0>:f mac (1) r5.5<1>:f r4.5<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L5 // rotate 180 degree ROTATE_180_L5: (-f0.0)mov (1) r16.0<1>:f r2.0<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.5:f r6.5<0;1,0>:f (-f0.0)mac (1) r6.5<1>:f r3.5<0;1,0>:f r17.0<0;1,0>:f mov (1) r16.0<1>:f r2.1<0;1,0>:uw add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.5:f r5.5<0;1,0>:f mac (1) r5.5<1>:f r4.5<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L5 // rotate 270 degree ROTATE_270_L5: (-f0.0)mov (1) r16.0<1>:f r2.1<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.5:f r6.5<0;1,0>:f (-f0.0)mac (1) r6.5<1>:f r3.5<0;1,0>:f r17.0<0;1,0>:f mov (1) acc0.5:f r5.5<0;1,0>:f mac (1) r5.5<1>:f r4.5<0;1,0>:f r8.5<0;1,0>:f END_SRC_BLOCK_ORIG_COMP_L5: nop shr (1) r17.0<1>:uw r2.2<0;1,0>:uw 12:uw and (1) r17.0<1>:uw r17.0<0;1,0>:uw 3:uw cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 1:uw (f0.1) jmpi (1) ROTATE_90_L6 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 2:uw (f0.1) jmpi (1) ROTATE_180_L6 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 3:uw (f0.1) jmpi (1) ROTATE_270_L6 // rotate 0 degree ROTATE_0_L6: (-f0.0)mov (1) acc0.6:f r6.6<0;1,0>:f (-f0.0)mac (1) r6.6<1>:f r3.6<0;1,0>:f r8.5<0;1,0>:f mov (1) acc0.6:f r5.6<0;1,0>:f mac (1) r5.6<1>:f r4.6<0;1,0>:f r8.6<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L6 // rotate 90 degree ROTATE_90_L6: (-f0.0)mov (1) acc0.6:f r6.6<0;1,0>:f (-f0.0)mac (1) r6.6<1>:f r3.6<0;1,0>:f r8.6<0;1,0>:f mov (1) r16.0<1>:f r2.0<0;1,0>:uw add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.6:f r5.6<0;1,0>:f mac (1) r5.6<1>:f r4.6<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L6 // rotate 180 degree ROTATE_180_L6: (-f0.0)mov (1) r16.0<1>:f r2.0<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.6:f r6.6<0;1,0>:f (-f0.0)mac (1) r6.6<1>:f r3.6<0;1,0>:f r17.0<0;1,0>:f mov (1) r16.0<1>:f r2.1<0;1,0>:uw add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.6:f r5.6<0;1,0>:f mac (1) r5.6<1>:f r4.6<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L6 // rotate 270 degree ROTATE_270_L6: (-f0.0)mov (1) r16.0<1>:f r2.1<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.6:f r6.6<0;1,0>:f (-f0.0)mac (1) r6.6<1>:f r3.6<0;1,0>:f r17.0<0;1,0>:f mov (1) acc0.6:f r5.6<0;1,0>:f mac (1) r5.6<1>:f r4.6<0;1,0>:f r8.5<0;1,0>:f END_SRC_BLOCK_ORIG_COMP_L6: nop shr (1) r17.0<1>:uw r2.2<0;1,0>:uw 14:uw and (1) r17.0<1>:uw r17.0<0;1,0>:uw 3:uw cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 1:uw (f0.1) jmpi (1) ROTATE_90_L7 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 2:uw (f0.1) jmpi (1) ROTATE_180_L7 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 3:uw (f0.1) jmpi (1) ROTATE_270_L7 // rotate 0 degree ROTATE_0_L7: (-f0.0)mov (1) acc0.7:f r6.7<0;1,0>:f (-f0.0)mac (1) r6.7<1>:f r3.7<0;1,0>:f r8.5<0;1,0>:f mov (1) acc0.7:f r5.7<0;1,0>:f mac (1) r5.7<1>:f r4.7<0;1,0>:f r8.6<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L7 // rotate 90 degree ROTATE_90_L7: (-f0.0)mov (1) acc0.7:f r6.7<0;1,0>:f (-f0.0)mac (1) r6.7<1>:f r3.7<0;1,0>:f r8.6<0;1,0>:f mov (1) r16.0<1>:f r2.0<0;1,0>:uw add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.7:f r5.7<0;1,0>:f mac (1) r5.7<1>:f r4.7<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L7 // rotate 180 degree ROTATE_180_L7: (-f0.0)mov (1) r16.0<1>:f r2.0<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.7:f r6.7<0;1,0>:f (-f0.0)mac (1) r6.7<1>:f r3.7<0;1,0>:f r17.0<0;1,0>:f mov (1) r16.0<1>:f r2.1<0;1,0>:uw add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.7:f r5.7<0;1,0>:f mac (1) r5.7<1>:f r4.7<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L7 // rotate 270 degree ROTATE_270_L7: (-f0.0)mov (1) r16.0<1>:f r2.1<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.7:f r6.7<0;1,0>:f (-f0.0)mac (1) r6.7<1>:f r3.7<0;1,0>:f r17.0<0;1,0>:f mov (1) acc0.7:f r5.7<0;1,0>:f mac (1) r5.7<1>:f r4.7<0;1,0>:f r8.5<0;1,0>:f END_SRC_BLOCK_ORIG_COMP_L7: nop intel-driver-1.3.0/src/shaders/post_processing/gen7/YUV_to_RGB.g4a000066400000000000000000001124741231401140700246760ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * Authors: * Zhao Yakui */ // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: YUV_to_RGB.asm // // Convert YUV to RGB, handle it by 16x4 block // // Description: Includes all definitions explicit to Fast Composite. //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare bBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare bBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare bBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare bBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written //Unnecessary to use the MSGPayLoad, So it is temporiarily used for conversion of YUV->RGB .declare fBUFFER_R Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_G Base=r30.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_B Base=r32.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_Y Base=r36.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_U Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_V Base=r40.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare wTempR Base=r42.0 ElementSize=2 Type=w .declare wTempG Base=r44.0 ElementSize=2 Type=w .declare wTempB Base=r46.0 ElementSize=2 Type=w .declare ubTempR Base=r42.0 ElementSize=1 Type=ub .declare ubTempG Base=r44.0 ElementSize=1 Type=ub .declare ubTempB Base=r46.0 ElementSize=1 Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare wTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ // NTSC standard // R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255)) // G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255)) // B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255)) // ITU-R conversion, Now we are using ITU-R conversion // R = clip( Y + 1.402*(Cr-128)) // ITU-R // G = clip( Y - 0.344*(Cb-128) - 0.714*(Cr-128)) // B = clip( Y + 1.772*(Cb-128)) // At the save module we have all 8 address sub-registers available. // So we will use PING-PONG type of scheme to save the data using // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help // reduce dependency. - rT //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4. //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5). //Offsets are zero for buffer 0 and buffer 4. //Y/U/V is also stored as R/G/B for the internal purpose //for BUFFER_0 mov (4) a0.0<1>:uw r22.0<4;4,1>:uw //the first line in the block 0 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 17]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,1]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,1]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,1]<2>:ub ubTempB(0, 0)<32;8,4> //the second line in the block 0 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 49]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,33]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,33]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,33]<2>:ub ubTempB(0, 0)<32;8,4> //the third line in the block 0 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 81]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,65]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,65]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,65]<2>:ub ubTempB(0, 0)<32;8,4> //the fourth line in the block 0 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 113]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,97]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,97]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,97]<2>:ub ubTempB(0, 0)<32;8,4> //for BUFFER_1 add (4) a0.0<1>:uw r22.0<4;4,1>:uw 512:uw //the first line in the block 1 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 17]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,1]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,1]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,1]<2>:ub ubTempB(0, 0)<32;8,4> //the second line in the block 1 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 49]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,33]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,33]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,33]<2>:ub ubTempB(0, 0)<32;8,4> //the third line in the block 1 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 81]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,65]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,65]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,65]<2>:ub ubTempB(0, 0)<32;8,4> //the fourth line in the block 1 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 113]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,97]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,97]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,97]<2>:ub ubTempB(0, 0)<32;8,4> //for BUFFER_2 add (4) a0.0<1>:uw r22.0<4;4,1>:uw 1024:uw //the first line in the block 2 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 17]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,1]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,1]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,1]<2>:ub ubTempB(0, 0)<32;8,4> //the second line in the block 2 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 49]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,33]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,33]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,33]<2>:ub ubTempB(0, 0)<32;8,4> //the third line in the block 2 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 81]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,65]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,65]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,65]<2>:ub ubTempB(0, 0)<32;8,4> //the fourth line in the block 2 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 113]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,97]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,97]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,97]<2>:ub ubTempB(0, 0)<32;8,4> //for BUFFER_3 add (4) a0.0<1>:uw r22.0<4;4,1>:uw 1536:uw //the first line in the block 3 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 17]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,1]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,1]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,1]<2>:ub ubTempB(0, 0)<32;8,4> //the second line in the block 3 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 49]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,33]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,33]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,33]<2>:ub ubTempB(0, 0)<32;8,4> //the third line in the block 3 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 81]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,65]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,65]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,65]<2>:ub ubTempB(0, 0)<32;8,4> //the fourth line in the block 3 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 113]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,97]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,97]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,97]<2>:ub ubTempB(0, 0)<32;8,4> intel-driver-1.3.0/src/shaders/post_processing/gen7/avs.asm000066400000000000000000000005241231401140700237050ustar00rootroot00000000000000// Module name: AVS .kernel AVS .code #include "VP_Setup.g4a" #include "Set_Layer_0.g4a" #include "Set_AVS_Buf_0123_PL2.g4a" #include "PL2_AVS_Buf_0.g4a" #include "PL2_AVS_Buf_1.g4a" #include "PL2_AVS_Buf_2.g4a" #include "PL2_AVS_Buf_3.g4a" #include "Save_AVS_NV12.g4a" #include "EOT.g4a" .end_code .end_kernel // end of DNDI intel-driver-1.3.0/src/shaders/post_processing/gen7/avs.g75b000066400000000000000000001062021231401140700236710ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000000d0 }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000290 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00000401, 0x24a001a5, 0x000000e0, 0x00000000 }, { 0x00000c08, 0x24a43da5, 0x000000e2, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x0007000f }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x44c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x44d00231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x44c10231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x44d10231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x44e00231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x44f00231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x44e10231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x44f10231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x45000231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x45100231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x45010231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x45110231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x45200231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x45300231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x45210231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x45310231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/avs.g7b000066400000000000000000001062021231401140700236040ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000001a }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000052 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00000401, 0x24a001a5, 0x000000e0, 0x00000000 }, { 0x00000c08, 0x24a43da5, 0x000000e2, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x0007000f }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x44c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x44d00231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x44c10231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x44d10231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x44e00231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x44f00231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x44e10231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x44f10231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x45000231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x45100231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x45010231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x45110231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x45200231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x45300231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x45210231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x45310231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/dndi.asm000066400000000000000000000001571231401140700240340ustar00rootroot00000000000000// Module name: DNDI .kernel DNDI .code #include "NV12_DI_NV12.g4a" .end_code .end_kernel // end of DNDI intel-driver-1.3.0/src/shaders/post_processing/gen7/dndi.g75b000066400000000000000000000047421231401140700240240ustar00rootroot00000000000000 { 0x00600001, 0x22400021, 0x008d0000, 0x00000000 }, { 0x00000401, 0x226801ad, 0x000000e0, 0x00000000 }, { 0x00000801, 0x227801ad, 0x000000e2, 0x00000000 }, { 0x02600031, 0x25c00e21, 0x00000240, 0x04ae8003 }, { 0x00200001, 0x20e0012d, 0x004506fc, 0x00000000 }, { 0x00600001, 0x22800021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x22a00021, 0x008d06c0, 0x00000000 }, { 0x00000408, 0x22803da1, 0x000000e0, 0x00010001 }, { 0x00000c01, 0x228401a1, 0x000000e2, 0x00000000 }, { 0x00000801, 0x22880061, 0x00000000, 0x00030007 }, { 0x05600031, 0x20000e24, 0x00000280, 0x040a8021 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000021, 0x008d0000, 0x00000000 }, { 0x00000408, 0x23003da1, 0x000000e0, 0x00010001 }, { 0x00000041, 0x24043da0, 0x000000e2, 0x00030003 }, { 0x00000c08, 0x23043c01, 0x00000404, 0x00020002 }, { 0x00000801, 0x23080061, 0x00000000, 0x00020007 }, { 0x00200040, 0x23002421, 0x00450300, 0x00450038 }, { 0x00000401, 0x23200021, 0x000006e4, 0x00000000 }, { 0x00200c01, 0x432c0021, 0x004506ec, 0x00000000 }, { 0x00200801, 0x43280021, 0x004506f4, 0x00000000 }, { 0x05600031, 0x20000e24, 0x00000300, 0x040a8021 }, { 0x00600001, 0x23800021, 0x008d0000, 0x00000000 }, { 0x00000401, 0x238001a5, 0x000000e0, 0x00000000 }, { 0x00000c01, 0x238401a5, 0x000000e2, 0x00000000 }, { 0x00000801, 0x23880061, 0x00000000, 0x0003000f }, { 0x00600001, 0x22400021, 0x008d0380, 0x00000000 }, { 0x00600001, 0x22e00021, 0x008d0380, 0x00000000 }, { 0x00600001, 0x22600021, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x22800021, 0x008d05e0, 0x00000000 }, { 0x00600001, 0x23000021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0660, 0x00000000 }, { 0x0000040c, 0x23843ca5, 0x00000384, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x0001000f }, { 0x00800401, 0x42c00231, 0x00ce0601, 0x00000000 }, { 0x00800801, 0x42c10231, 0x00ce0600, 0x00000000 }, { 0x00800401, 0x43600231, 0x00ce0681, 0x00000000 }, { 0x00800801, 0x43610231, 0x00ce0680, 0x00000000 }, { 0x00600001, 0x22a00021, 0x008d0380, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0380, 0x00000000 }, { 0x05600031, 0x20000e24, 0x00000240, 0x060a801b }, { 0x05600031, 0x20000e24, 0x000002e0, 0x060a801e }, { 0x05600031, 0x20000e24, 0x000002a0, 0x040a801c }, { 0x05600031, 0x20000e24, 0x00000340, 0x040a801f }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/dndi.g7b000066400000000000000000000047421231401140700237370ustar00rootroot00000000000000 { 0x00600001, 0x22400021, 0x008d0000, 0x00000000 }, { 0x00000401, 0x226801ad, 0x000000e0, 0x00000000 }, { 0x00000801, 0x227801ad, 0x000000e2, 0x00000000 }, { 0x02600031, 0x25c00e21, 0x00000240, 0x04ae8003 }, { 0x00200001, 0x20e0012d, 0x004506fc, 0x00000000 }, { 0x00600001, 0x22800021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x22a00021, 0x008d06c0, 0x00000000 }, { 0x00000408, 0x22803da1, 0x000000e0, 0x00010001 }, { 0x00000c01, 0x228401a1, 0x000000e2, 0x00000000 }, { 0x00000801, 0x22880061, 0x00000000, 0x00030007 }, { 0x05600031, 0x20000e24, 0x00000280, 0x040a8021 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000021, 0x008d0000, 0x00000000 }, { 0x00000408, 0x23003da1, 0x000000e0, 0x00010001 }, { 0x00000041, 0x24043da0, 0x000000e2, 0x00030003 }, { 0x00000c08, 0x23043c01, 0x00000404, 0x00020002 }, { 0x00000801, 0x23080061, 0x00000000, 0x00020007 }, { 0x00200040, 0x23002421, 0x00450300, 0x00450038 }, { 0x00000401, 0x23200021, 0x000006e4, 0x00000000 }, { 0x00200c01, 0x432c0021, 0x004506ec, 0x00000000 }, { 0x00200801, 0x43280021, 0x004506f4, 0x00000000 }, { 0x05600031, 0x20000e24, 0x00000300, 0x040a8021 }, { 0x00600001, 0x23800021, 0x008d0000, 0x00000000 }, { 0x00000401, 0x238001a5, 0x000000e0, 0x00000000 }, { 0x00000c01, 0x238401a5, 0x000000e2, 0x00000000 }, { 0x00000801, 0x23880061, 0x00000000, 0x0003000f }, { 0x00600001, 0x22400021, 0x008d0380, 0x00000000 }, { 0x00600001, 0x22e00021, 0x008d0380, 0x00000000 }, { 0x00600001, 0x22600021, 0x008d05c0, 0x00000000 }, { 0x00600001, 0x22800021, 0x008d05e0, 0x00000000 }, { 0x00600001, 0x23000021, 0x008d0640, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0660, 0x00000000 }, { 0x0000040c, 0x23843ca5, 0x00000384, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x0001000f }, { 0x00800401, 0x42c00231, 0x00ce0601, 0x00000000 }, { 0x00800801, 0x42c10231, 0x00ce0600, 0x00000000 }, { 0x00800401, 0x43600231, 0x00ce0681, 0x00000000 }, { 0x00800801, 0x43610231, 0x00ce0680, 0x00000000 }, { 0x00600001, 0x22a00021, 0x008d0380, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0380, 0x00000000 }, { 0x05600031, 0x20000e24, 0x00000240, 0x060a801b }, { 0x05600031, 0x20000e24, 0x000002e0, 0x060a801e }, { 0x05600031, 0x20000e24, 0x000002a0, 0x040a801c }, { 0x05600031, 0x20000e24, 0x00000340, 0x040a801f }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/nv12_dn_nv12.asm000066400000000000000000000001001231401140700252170ustar00rootroot00000000000000// Module name: DN #include "NV12_DN_NV12.g4a" // end of DNDI intel-driver-1.3.0/src/shaders/post_processing/gen7/nv12_dn_nv12.g75b000066400000000000000000000042301231401140700252130ustar00rootroot00000000000000 { 0x00600001, 0x22400021, 0x008d0000, 0x00000000 }, { 0x00000401, 0x226801ad, 0x000000e0, 0x00000000 }, { 0x00000801, 0x227801ad, 0x000000e2, 0x00000000 }, { 0x02600031, 0x25c00e21, 0x00000240, 0x045e8003 }, { 0x00200001, 0x20e0012d, 0x0045065c, 0x00000000 }, { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00200001, 0x22e00021, 0x00450640, 0x00000000 }, { 0x00200008, 0x23603da1, 0x004500e0, 0x00020002 }, { 0x00000440, 0x23602421, 0x00000360, 0x00000038 }, { 0x00000801, 0x23680061, 0x00000000, 0x00010003 }, { 0x00600001, 0x22c00021, 0x008d0360, 0x00000000 }, { 0x05600031, 0x20000e24, 0x000002c0, 0x040a8021 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000021, 0x008d0000, 0x00000000 }, { 0x00000408, 0x23003da1, 0x000000e0, 0x00010001 }, { 0x00000041, 0x24043da0, 0x000000e2, 0x00030003 }, { 0x00000c08, 0x23043c01, 0x00000404, 0x00020002 }, { 0x00000801, 0x23080061, 0x00000000, 0x00050003 }, { 0x00200040, 0x23002421, 0x00450300, 0x00450038 }, { 0x00000401, 0x23200231, 0x00000648, 0x00000000 }, { 0x00000c01, 0x23260129, 0x00000656, 0x00000000 }, { 0x00200c01, 0x23280129, 0x00450658, 0x00000000 }, { 0x00000c01, 0x23320129, 0x00000650, 0x00000000 }, { 0x00200801, 0x23340129, 0x00450652, 0x00000000 }, { 0x05600031, 0x20000e24, 0x00000300, 0x040a8021 }, { 0x00200040, 0x236035a5, 0x004500e0, 0x00450088 }, { 0x0000040c, 0x23643ca5, 0x00000364, 0x00010001 }, { 0x00000801, 0x23680061, 0x00000000, 0x0004000f }, { 0x00600001, 0x24800021, 0x008d0360, 0x00000000 }, { 0x04600031, 0x27400e21, 0x00000480, 0x02390001 }, { 0x00000001, 0x24880061, 0x00000000, 0x0003000f }, { 0x00600001, 0x25a00021, 0x008d0000, 0x00000000 }, { 0x00200401, 0x25a001a1, 0x004500e0, 0x00000000 }, { 0x00000801, 0x25a80061, 0x00000000, 0x0007000f }, { 0x05600031, 0x20000e24, 0x000005a0, 0x0a0a8018 }, { 0x00600001, 0x24a00021, 0x008d0740, 0x00000000 }, { 0x00600001, 0x24c00021, 0x008d0760, 0x00000000 }, { 0x05600031, 0x20000e24, 0x00000480, 0x060a8019 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/nv12_dn_nv12.g7b000066400000000000000000000042301231401140700251260ustar00rootroot00000000000000 { 0x00600001, 0x22400021, 0x008d0000, 0x00000000 }, { 0x00000401, 0x226801ad, 0x000000e0, 0x00000000 }, { 0x00000801, 0x227801ad, 0x000000e2, 0x00000000 }, { 0x02600031, 0x25c00e21, 0x00000240, 0x045e8003 }, { 0x00200001, 0x20e0012d, 0x0045065c, 0x00000000 }, { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00200001, 0x22e00021, 0x00450640, 0x00000000 }, { 0x00200008, 0x23603da1, 0x004500e0, 0x00020002 }, { 0x00000440, 0x23602421, 0x00000360, 0x00000038 }, { 0x00000801, 0x23680061, 0x00000000, 0x00010003 }, { 0x00600001, 0x22c00021, 0x008d0360, 0x00000000 }, { 0x05600031, 0x20000e24, 0x000002c0, 0x040a8021 }, { 0x00600001, 0x23200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x23000021, 0x008d0000, 0x00000000 }, { 0x00000408, 0x23003da1, 0x000000e0, 0x00010001 }, { 0x00000041, 0x24043da0, 0x000000e2, 0x00030003 }, { 0x00000c08, 0x23043c01, 0x00000404, 0x00020002 }, { 0x00000801, 0x23080061, 0x00000000, 0x00050003 }, { 0x00200040, 0x23002421, 0x00450300, 0x00450038 }, { 0x00000401, 0x23200231, 0x00000648, 0x00000000 }, { 0x00000c01, 0x23260129, 0x00000656, 0x00000000 }, { 0x00200c01, 0x23280129, 0x00450658, 0x00000000 }, { 0x00000c01, 0x23320129, 0x00000650, 0x00000000 }, { 0x00200801, 0x23340129, 0x00450652, 0x00000000 }, { 0x05600031, 0x20000e24, 0x00000300, 0x040a8021 }, { 0x00200040, 0x236035a5, 0x004500e0, 0x00450088 }, { 0x0000040c, 0x23643ca5, 0x00000364, 0x00010001 }, { 0x00000801, 0x23680061, 0x00000000, 0x0004000f }, { 0x00600001, 0x24800021, 0x008d0360, 0x00000000 }, { 0x04600031, 0x27400e21, 0x00000480, 0x02390001 }, { 0x00000001, 0x24880061, 0x00000000, 0x0003000f }, { 0x00600001, 0x25a00021, 0x008d0000, 0x00000000 }, { 0x00200401, 0x25a001a1, 0x004500e0, 0x00000000 }, { 0x00000801, 0x25a80061, 0x00000000, 0x0007000f }, { 0x05600031, 0x20000e24, 0x000005a0, 0x0a0a8018 }, { 0x00600001, 0x24a00021, 0x008d0740, 0x00000000 }, { 0x00600001, 0x24c00021, 0x008d0760, 0x00000000 }, { 0x05600031, 0x20000e24, 0x00000480, 0x060a8019 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pa_to_pa.asm000066400000000000000000000004731231401140700247010ustar00rootroot00000000000000// Module name: AVS .kernel PA_TO_PL3 .code #include "VP_Setup.g4a" #include "Set_Layer_0.g4a" #include "Set_AVS_Buf_0123_VYUA.g4a" #include "PA_AVS_Buf_0.g4a" #include "PA_AVS_Buf_1.g4a" #include "PA_AVS_Buf_2.g4a" #include "PA_AVS_Buf_3.g4a" #include "Save_AVS_PA.g4a" #include "EOT.g4a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/pa_to_pa.g75b000066400000000000000000001105631231401140700246670ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000000d0 }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x000062ea }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006420 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000240 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000230 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000230 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000230 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082e2c, 0x0069005c, 0x03a003a0 }, { 0x00000409, 0x23603da5, 0x000000e0, 0x00010001 }, { 0x00000c01, 0x236401a5, 0x000000e2, 0x00000000 }, { 0x00000801, 0x23680061, 0x00000000, 0x0001001f }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x02000200 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x06000600 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x08000800 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000002 }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x02000200 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000004 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000006 }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000008 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x0000000a }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x06000600 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x0000000c }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x0000000e }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pa_to_pa.g7b000066400000000000000000001105631231401140700246020ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000001a }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x000062ea }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006420 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000048 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000046 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000046 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000046 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082e2c, 0x0069005c, 0x03a003a0 }, { 0x00000409, 0x23603da5, 0x000000e0, 0x00010001 }, { 0x00000c01, 0x236401a5, 0x000000e2, 0x00000000 }, { 0x00000801, 0x23680061, 0x00000000, 0x0001001f }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x02000200 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x06000600 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x08000800 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000002 }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x02000200 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000004 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000006 }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000008 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x0000000a }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x06000600 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x0000000c }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x0000000e }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pa_to_pl2.asm000066400000000000000000000005071231401140700247740ustar00rootroot00000000000000// Module name: AVS .kernel PA_TO_pl2 .code #include "VP_Setup.g4a" #include "Set_Layer_0.g4a" #include "Set_AVS_Buf_0123_VYUA.g4a" #include "PA_AVS_Buf_0.g4a" #include "PA_AVS_Buf_1.g4a" #include "PA_AVS_Buf_2.g4a" #include "PA_AVS_Buf_3.g4a" #include "Save_AVS_NV12.g4a" #include "EOT.g4a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/pa_to_pl2.g75b000066400000000000000000001040661231401140700247650ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000000d0 }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x000062ea }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006420 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000240 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000230 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000230 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000230 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00000401, 0x24a001a5, 0x000000e0, 0x00000000 }, { 0x00000c08, 0x24a43da5, 0x000000e2, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x0007000f }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x44c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x44d00231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x44c10231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x44d10231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x44e00231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x44f00231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x44e10231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x44f10231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x45000231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x45100231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x45010231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x45110231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x45200231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x45300231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x45210231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x45310231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pa_to_pl2.g7b000066400000000000000000001040661231401140700247000ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000001a }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x000062ea }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006420 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000048 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000046 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000046 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000046 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00000401, 0x24a001a5, 0x000000e0, 0x00000000 }, { 0x00000c08, 0x24a43da5, 0x000000e2, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x0007000f }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x44c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x44d00231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x44c10231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x44d10231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x44e00231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x44f00231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x44e10231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x44f10231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x45000231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x45100231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x45010231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x45110231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x45200231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x45300231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x45210231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x45310231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pa_to_pl3.asm000066400000000000000000000005061231401140700247740ustar00rootroot00000000000000// Module name: AVS .kernel PA_TO_PL3 .code #include "VP_Setup.g4a" #include "Set_Layer_0.g4a" #include "Set_AVS_Buf_0123_VYUA.g4a" #include "PA_AVS_Buf_0.g4a" #include "PA_AVS_Buf_1.g4a" #include "PA_AVS_Buf_2.g4a" #include "PA_AVS_Buf_3.g4a" #include "Save_AVS_PL3.g4a" #include "EOT.g4a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/pa_to_pl3.g75b000066400000000000000000000770351231401140700247730ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000000d0 }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x000062ea }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006420 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000240 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000230 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000230 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000230 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00200408, 0x24a03da5, 0x004500e0, 0x00010001 }, { 0x00200408, 0x25c03da5, 0x004500e0, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x00070007 }, { 0x00000801, 0x25c80061, 0x00000000, 0x00070007 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x80600040, 0xc8002d29, 0x00ae8800, 0x00800080 }, { 0x80600040, 0xc8402d29, 0x00ae8840, 0x00800080 }, { 0x80600040, 0xc0002d29, 0x00ae8000, 0x00800080 }, { 0x80600040, 0xc0402d29, 0x00ae8040, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x80600040, 0xd8002d29, 0x00ae9800, 0x00800080 }, { 0x80600040, 0xd8402d29, 0x00ae9840, 0x00800080 }, { 0x80600040, 0xd0002d29, 0x00ae9000, 0x00800080 }, { 0x80600040, 0xd0402d29, 0x00ae9040, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x80600040, 0xc8002d29, 0x00ae8800, 0x00800080 }, { 0x80600040, 0xc8402d29, 0x00ae8840, 0x00800080 }, { 0x80600040, 0xc0002d29, 0x00ae8000, 0x00800080 }, { 0x80600040, 0xc0402d29, 0x00ae8040, 0x00800080 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x80600040, 0xd8002d29, 0x00ae9800, 0x00800080 }, { 0x80600040, 0xd8402d29, 0x00ae9840, 0x00800080 }, { 0x80600040, 0xd0002d29, 0x00ae9000, 0x00800080 }, { 0x80600040, 0xd0402d29, 0x00ae9040, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x24c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x24c80231, 0x00cf8841, 0x00000000 }, { 0x00600401, 0x25e00231, 0x00cf8001, 0x00000000 }, { 0x00600c01, 0x25e80231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600c01, 0x24d00231, 0x00cf9801, 0x00000000 }, { 0x00600801, 0x24d80231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x25f00231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x25f80231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x24e00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x24e80231, 0x00cf8841, 0x00000000 }, { 0x00600401, 0x26000231, 0x00cf8001, 0x00000000 }, { 0x00600c01, 0x26080231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600c01, 0x24f00231, 0x00cf9801, 0x00000000 }, { 0x00600801, 0x24f80231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x26100231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x26180231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8019 }, { 0x05000031, 0x20000e24, 0x000005c0, 0x060a801a }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pa_to_pl3.g7b000066400000000000000000000770351231401140700247060ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000001a }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x000062ea }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006420 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000048 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000046 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000046 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000046 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00200408, 0x24a03da5, 0x004500e0, 0x00010001 }, { 0x00200408, 0x25c03da5, 0x004500e0, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x00070007 }, { 0x00000801, 0x25c80061, 0x00000000, 0x00070007 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x80600040, 0xc8002d29, 0x00ae8800, 0x00800080 }, { 0x80600040, 0xc8402d29, 0x00ae8840, 0x00800080 }, { 0x80600040, 0xc0002d29, 0x00ae8000, 0x00800080 }, { 0x80600040, 0xc0402d29, 0x00ae8040, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x80600040, 0xd8002d29, 0x00ae9800, 0x00800080 }, { 0x80600040, 0xd8402d29, 0x00ae9840, 0x00800080 }, { 0x80600040, 0xd0002d29, 0x00ae9000, 0x00800080 }, { 0x80600040, 0xd0402d29, 0x00ae9040, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x80600040, 0xc8002d29, 0x00ae8800, 0x00800080 }, { 0x80600040, 0xc8402d29, 0x00ae8840, 0x00800080 }, { 0x80600040, 0xc0002d29, 0x00ae8000, 0x00800080 }, { 0x80600040, 0xc0402d29, 0x00ae8040, 0x00800080 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x80600040, 0xd8002d29, 0x00ae9800, 0x00800080 }, { 0x80600040, 0xd8402d29, 0x00ae9840, 0x00800080 }, { 0x80600040, 0xd0002d29, 0x00ae9000, 0x00800080 }, { 0x80600040, 0xd0402d29, 0x00ae9040, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x24c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x24c80231, 0x00cf8841, 0x00000000 }, { 0x00600401, 0x25e00231, 0x00cf8001, 0x00000000 }, { 0x00600c01, 0x25e80231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600c01, 0x24d00231, 0x00cf9801, 0x00000000 }, { 0x00600801, 0x24d80231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x25f00231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x25f80231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x24e00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x24e80231, 0x00cf8841, 0x00000000 }, { 0x00600401, 0x26000231, 0x00cf8001, 0x00000000 }, { 0x00600c01, 0x26080231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600c01, 0x24f00231, 0x00cf9801, 0x00000000 }, { 0x00600801, 0x24f80231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x26100231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x26180231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8019 }, { 0x05000031, 0x20000e24, 0x000005c0, 0x060a801a }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl2_to_pa.asm000066400000000000000000000005101231401140700247660ustar00rootroot00000000000000// Module name: AVS .kernel PL2_TO_PA .code #include "VP_Setup.g4a" #include "Set_Layer_0.g4a" #include "Set_AVS_Buf_0123_PL2.g4a" #include "PL2_AVS_Buf_0.g4a" #include "PL2_AVS_Buf_1.g4a" #include "PL2_AVS_Buf_2.g4a" #include "PL2_AVS_Buf_3.g4a" #include "Save_AVS_PA.g4a" #include "EOT.g4a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/pl2_to_pa.g75b000066400000000000000000001126771231401140700247740ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000000d0 }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000290 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082e2c, 0x0069005c, 0x03a003a0 }, { 0x00000409, 0x23603da5, 0x000000e0, 0x00010001 }, { 0x00000c01, 0x236401a5, 0x000000e2, 0x00000000 }, { 0x00000801, 0x23680061, 0x00000000, 0x0001001f }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x02000200 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x06000600 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x08000800 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000002 }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x02000200 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000004 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000006 }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000008 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x0000000a }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x06000600 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x0000000c }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x0000000e }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl2_to_pa.g7b000066400000000000000000001126771231401140700247070ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000001a }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000052 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082e2c, 0x0069005c, 0x03a003a0 }, { 0x00000409, 0x23603da5, 0x000000e0, 0x00010001 }, { 0x00000c01, 0x236401a5, 0x000000e2, 0x00000000 }, { 0x00000801, 0x23680061, 0x00000000, 0x0001001f }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x02000200 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x06000600 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x08000800 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000002 }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x02000200 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000004 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000006 }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000008 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x0000000a }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x06000600 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x0000000c }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x0000000e }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl2_to_pl2.asm000066400000000000000000000005131231401140700250660ustar00rootroot00000000000000// Module name: AVS .kernel PL2_TO_PL2 .code #include "VP_Setup.g4a" #include "Set_Layer_0.g4a" #include "Set_AVS_Buf_0123_PL2.g4a" #include "PL2_AVS_Buf_0.g4a" #include "PL2_AVS_Buf_1.g4a" #include "PL2_AVS_Buf_2.g4a" #include "PL2_AVS_Buf_3.g4a" #include "Save_AVS_NV12.g4a" #include "EOT.g4a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/pl2_to_pl2.g75b000066400000000000000000001062021231401140700250540ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000000d0 }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000290 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00000401, 0x24a001a5, 0x000000e0, 0x00000000 }, { 0x00000c08, 0x24a43da5, 0x000000e2, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x0007000f }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x44c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x44d00231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x44c10231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x44d10231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x44e00231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x44f00231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x44e10231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x44f10231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x45000231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x45100231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x45010231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x45110231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x45200231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x45300231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x45210231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x45310231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl2_to_pl2.g7b000066400000000000000000001062021231401140700247670ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000001a }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000052 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00000401, 0x24a001a5, 0x000000e0, 0x00000000 }, { 0x00000c08, 0x24a43da5, 0x000000e2, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x0007000f }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x44c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x44d00231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x44c10231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x44d10231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x44e00231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x44f00231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x44e10231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x44f10231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x45000231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x45100231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x45010231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x45110231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x45200231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x45300231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x45210231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x45310231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl2_to_pl3.asm000066400000000000000000000005121231401140700250660ustar00rootroot00000000000000// Module name: AVS .kernel PL2_TO_PL3 .code #include "VP_Setup.g4a" #include "Set_Layer_0.g4a" #include "Set_AVS_Buf_0123_PL2.g4a" #include "PL2_AVS_Buf_0.g4a" #include "PL2_AVS_Buf_1.g4a" #include "PL2_AVS_Buf_2.g4a" #include "PL2_AVS_Buf_3.g4a" #include "Save_AVS_PL3.g4a" #include "EOT.g4a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/pl2_to_pl3.g75b000066400000000000000000001011511231401140700250530ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000000d0 }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000290 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00200408, 0x24a03da5, 0x004500e0, 0x00010001 }, { 0x00200408, 0x25c03da5, 0x004500e0, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x00070007 }, { 0x00000801, 0x25c80061, 0x00000000, 0x00070007 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x80600040, 0xc8002d29, 0x00ae8800, 0x00800080 }, { 0x80600040, 0xc8402d29, 0x00ae8840, 0x00800080 }, { 0x80600040, 0xc0002d29, 0x00ae8000, 0x00800080 }, { 0x80600040, 0xc0402d29, 0x00ae8040, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x80600040, 0xd8002d29, 0x00ae9800, 0x00800080 }, { 0x80600040, 0xd8402d29, 0x00ae9840, 0x00800080 }, { 0x80600040, 0xd0002d29, 0x00ae9000, 0x00800080 }, { 0x80600040, 0xd0402d29, 0x00ae9040, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x80600040, 0xc8002d29, 0x00ae8800, 0x00800080 }, { 0x80600040, 0xc8402d29, 0x00ae8840, 0x00800080 }, { 0x80600040, 0xc0002d29, 0x00ae8000, 0x00800080 }, { 0x80600040, 0xc0402d29, 0x00ae8040, 0x00800080 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x80600040, 0xd8002d29, 0x00ae9800, 0x00800080 }, { 0x80600040, 0xd8402d29, 0x00ae9840, 0x00800080 }, { 0x80600040, 0xd0002d29, 0x00ae9000, 0x00800080 }, { 0x80600040, 0xd0402d29, 0x00ae9040, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x24c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x24c80231, 0x00cf8841, 0x00000000 }, { 0x00600401, 0x25e00231, 0x00cf8001, 0x00000000 }, { 0x00600c01, 0x25e80231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600c01, 0x24d00231, 0x00cf9801, 0x00000000 }, { 0x00600801, 0x24d80231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x25f00231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x25f80231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x24e00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x24e80231, 0x00cf8841, 0x00000000 }, { 0x00600401, 0x26000231, 0x00cf8001, 0x00000000 }, { 0x00600c01, 0x26080231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600c01, 0x24f00231, 0x00cf9801, 0x00000000 }, { 0x00600801, 0x24f80231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x26100231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x26180231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8019 }, { 0x05000031, 0x20000e24, 0x000005c0, 0x060a801a }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl2_to_pl3.g7b000066400000000000000000001011511231401140700247660ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000001a }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000052 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00200408, 0x24a03da5, 0x004500e0, 0x00010001 }, { 0x00200408, 0x25c03da5, 0x004500e0, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x00070007 }, { 0x00000801, 0x25c80061, 0x00000000, 0x00070007 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x80600040, 0xc8002d29, 0x00ae8800, 0x00800080 }, { 0x80600040, 0xc8402d29, 0x00ae8840, 0x00800080 }, { 0x80600040, 0xc0002d29, 0x00ae8000, 0x00800080 }, { 0x80600040, 0xc0402d29, 0x00ae8040, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x80600040, 0xd8002d29, 0x00ae9800, 0x00800080 }, { 0x80600040, 0xd8402d29, 0x00ae9840, 0x00800080 }, { 0x80600040, 0xd0002d29, 0x00ae9000, 0x00800080 }, { 0x80600040, 0xd0402d29, 0x00ae9040, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x80600040, 0xc8002d29, 0x00ae8800, 0x00800080 }, { 0x80600040, 0xc8402d29, 0x00ae8840, 0x00800080 }, { 0x80600040, 0xc0002d29, 0x00ae8000, 0x00800080 }, { 0x80600040, 0xc0402d29, 0x00ae8040, 0x00800080 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x80600040, 0xd8002d29, 0x00ae9800, 0x00800080 }, { 0x80600040, 0xd8402d29, 0x00ae9840, 0x00800080 }, { 0x80600040, 0xd0002d29, 0x00ae9000, 0x00800080 }, { 0x80600040, 0xd0402d29, 0x00ae9040, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x24c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x24c80231, 0x00cf8841, 0x00000000 }, { 0x00600401, 0x25e00231, 0x00cf8001, 0x00000000 }, { 0x00600c01, 0x25e80231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600c01, 0x24d00231, 0x00cf9801, 0x00000000 }, { 0x00600801, 0x24d80231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x25f00231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x25f80231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x24e00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x24e80231, 0x00cf8841, 0x00000000 }, { 0x00600401, 0x26000231, 0x00cf8001, 0x00000000 }, { 0x00600c01, 0x26080231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600c01, 0x24f00231, 0x00cf9801, 0x00000000 }, { 0x00600801, 0x24f80231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x26100231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x26180231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8019 }, { 0x05000031, 0x20000e24, 0x000005c0, 0x060a801a }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl2_to_rgbx.asm000066400000000000000000000005441231401140700253370ustar00rootroot00000000000000// Module name: AVS .kernel PL2_TO_PA .code #include "VP_Setup.g4a" #include "Set_Layer_0.g4a" #include "Set_AVS_Buf_0123_PL2.g4a" #include "PL2_AVS_Buf_0.g4a" #include "PL2_AVS_Buf_1.g4a" #include "PL2_AVS_Buf_2.g4a" #include "PL2_AVS_Buf_3.g4a" #include "YUV_to_RGB.g4a" #include "Save_AVS_RGBX.g4a" #include "EOT.g4a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/pl2_to_rgbx.g75b000066400000000000000000001714641231401140700253350ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000000d0 }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000290 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000280 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x22000128, 0x006902c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8011, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8031, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8051, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8071, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0610231, 0x00cf05c0, 0x00000000 }, { 0x00400040, 0x22002d28, 0x006902c0, 0x02000200 }, { 0x00600001, 0x2480023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8011, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8031, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8051, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8071, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0610231, 0x00cf05c0, 0x00000000 }, { 0x00400040, 0x22002d28, 0x006902c0, 0x04000400 }, { 0x00600001, 0x2480023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8011, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8031, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8051, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8071, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0610231, 0x00cf05c0, 0x00000000 }, { 0x00400040, 0x22002d28, 0x006902c0, 0x06000600 }, { 0x00600001, 0x2480023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8011, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8031, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8051, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8071, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0610231, 0x00cf05c0, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x000062ea }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x02800005, 0x20003d2c, 0x00000046, 0x00010001 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00010001, 0x22200109, 0x00000200, 0x00000000 }, { 0x00010001, 0x22000108, 0x00000204, 0x00000000 }, { 0x00010001, 0x22040128, 0x00000220, 0x00000000 }, { 0x00000409, 0x23603da5, 0x000000e0, 0x00020002 }, { 0x00000c01, 0x236401a5, 0x000000e2, 0x00000000 }, { 0x00000801, 0x23680061, 0x00000000, 0x0003001f }, { 0x00400001, 0x22080108, 0x00690200, 0x00000000 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x26e00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x23e00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25000021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x26200021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x27400021, 0x008d0360, 0x00000000 }, { 0x00000040, 0x24a01ca5, 0x00000360, 0x00000020 }, { 0x00000040, 0x25c41ca5, 0x00000364, 0x00000004 }, { 0x00000040, 0x26e41ca5, 0x00000364, 0x00000004 }, { 0x00000040, 0x26e01ca5, 0x00000360, 0x00000020 }, { 0x00600001, 0x63a00231, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x63a10231, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x63a20231, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x63a30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x63c00231, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x63c10231, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x63c20231, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x63c30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64c00231, 0x00ae8011, 0x00000000 }, { 0x00600001, 0x64c10231, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x64c20231, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x64c30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64e00231, 0x00ae8031, 0x00000000 }, { 0x00600001, 0x64e10231, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x64e20231, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x64e30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x63e00231, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x63e10231, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x63e20231, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x63e30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64000231, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x64010231, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x64020231, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x64030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x65000231, 0x00ae8051, 0x00000000 }, { 0x00600001, 0x65010231, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x65020231, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x65030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x65200231, 0x00ae8071, 0x00000000 }, { 0x00600001, 0x65210231, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x65220231, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x65230231, 0x0000005f, 0x00000000 }, { 0x05800031, 0x20000e24, 0x00000380, 0x0a0a8018 }, { 0x05800031, 0x20000e24, 0x000004a0, 0x0a0a8018 }, { 0x00400040, 0x22002d08, 0x00690208, 0x02000200 }, { 0x00600001, 0x65e00231, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x65e10231, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x65e20231, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x65e30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66000231, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x66010231, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x66020231, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x66030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67000231, 0x00ae8011, 0x00000000 }, { 0x00600001, 0x67010231, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x67020231, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x67030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67200231, 0x00ae8031, 0x00000000 }, { 0x00600001, 0x67210231, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x67220231, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x67230231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66200231, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x66210231, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x66220231, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x66230231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66400231, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x66410231, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x66420231, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x66430231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67400231, 0x00ae8051, 0x00000000 }, { 0x00600001, 0x67410231, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x67420231, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x67430231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67600231, 0x00ae8071, 0x00000000 }, { 0x00600001, 0x67610231, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x67620231, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x67630231, 0x0000005f, 0x00000000 }, { 0x05800031, 0x20000e24, 0x000005c0, 0x0a0a8018 }, { 0x05800031, 0x20000e24, 0x000006e0, 0x0a0a8018 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x26e00021, 0x008d0360, 0x00000000 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000008 }, { 0x00000040, 0x24a01ca5, 0x00000360, 0x00000020 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000008 }, { 0x00000040, 0x25c41ca5, 0x00000364, 0x0000000c }, { 0x00000040, 0x26e41ca5, 0x00000364, 0x0000000c }, { 0x00000040, 0x26e01ca5, 0x00000360, 0x00000020 }, { 0x00400040, 0x22002d08, 0x00690208, 0x04000400 }, { 0x00600001, 0x63a00231, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x63a10231, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x63a20231, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x63a30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x63c00231, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x63c10231, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x63c20231, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x63c30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64c00231, 0x00ae8011, 0x00000000 }, { 0x00600001, 0x64c10231, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x64c20231, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x64c30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64e00231, 0x00ae8031, 0x00000000 }, { 0x00600001, 0x64e10231, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x64e20231, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x64e30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x63e00231, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x63e10231, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x63e20231, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x63e30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64000231, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x64010231, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x64020231, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x64030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x65000231, 0x00ae8051, 0x00000000 }, { 0x00600001, 0x65010231, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x65020231, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x65030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x65200231, 0x00ae8071, 0x00000000 }, { 0x00600001, 0x65210231, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x65220231, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x65230231, 0x0000005f, 0x00000000 }, { 0x05800031, 0x20000e24, 0x00000380, 0x0a0a8018 }, { 0x05800031, 0x20000e24, 0x000004a0, 0x0a0a8018 }, { 0x00400040, 0x22002d08, 0x00690208, 0x06000600 }, { 0x00600001, 0x65e00231, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x65e10231, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x65e20231, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x65e30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66000231, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x66010231, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x66020231, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x66030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67000231, 0x00ae8011, 0x00000000 }, { 0x00600001, 0x67010231, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x67020231, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x67030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67200231, 0x00ae8031, 0x00000000 }, { 0x00600001, 0x67210231, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x67220231, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x67230231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66200231, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x66210231, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x66220231, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x66230231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66400231, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x66410231, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x66420231, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x66430231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67400231, 0x00ae8051, 0x00000000 }, { 0x00600001, 0x67410231, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x67420231, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x67430231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67600231, 0x00ae8071, 0x00000000 }, { 0x00600001, 0x67610231, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x67620231, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x67630231, 0x0000005f, 0x00000000 }, { 0x05800031, 0x20000e24, 0x000005c0, 0x0a0a8018 }, { 0x05800031, 0x20000e24, 0x000006e0, 0x0a0a8018 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl2_to_rgbx.g7b000066400000000000000000001714641231401140700252500ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000001a }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000052 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x048eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x22000128, 0x006902c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8011, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8031, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8051, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8071, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0610231, 0x00cf05c0, 0x00000000 }, { 0x00400040, 0x22002d28, 0x006902c0, 0x02000200 }, { 0x00600001, 0x2480023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8011, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8031, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8051, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8071, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0610231, 0x00cf05c0, 0x00000000 }, { 0x00400040, 0x22002d28, 0x006902c0, 0x04000400 }, { 0x00600001, 0x2480023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8011, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8031, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8051, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8071, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0610231, 0x00cf05c0, 0x00000000 }, { 0x00400040, 0x22002d28, 0x006902c0, 0x06000600 }, { 0x00600001, 0x2480023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8011, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8031, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8051, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2480023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x24a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x24c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x24e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2500023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2520023d, 0x00ae8071, 0x00000000 }, { 0x00800040, 0x24c07fbd, 0x008d04c0, 0xc3000000 }, { 0x00800040, 0x25007fbd, 0x008d0500, 0xc3000000 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23807fbd, 0x008d0500, 0x3fb374bc }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbc, 0x008d04c0, 0xbeb020c5 }, { 0x00800048, 0x23c07fbd, 0x008d0500, 0xbf36c8b4 }, { 0x00800001, 0x240003bc, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24007fbd, 0x008d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24807fbd, 0x008d0380, 0x3b8080c4 }, { 0x80800041, 0x24c07fbd, 0x008d03c0, 0x3b8080c4 }, { 0x80800041, 0x25007fbd, 0x008d0400, 0x3b8080c4 }, { 0x00800041, 0x23807fbd, 0x008d0480, 0x437f0000 }, { 0x00800041, 0x23c07fbd, 0x008d04c0, 0x437f0000 }, { 0x00800041, 0x24007fbd, 0x008d0500, 0x437f0000 }, { 0x00800001, 0x454003ad, 0x008d0380, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0610231, 0x00cf05c0, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x000062ea }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x02800005, 0x20003d2c, 0x00000046, 0x00010001 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00010001, 0x22200109, 0x00000200, 0x00000000 }, { 0x00010001, 0x22000108, 0x00000204, 0x00000000 }, { 0x00010001, 0x22040128, 0x00000220, 0x00000000 }, { 0x00000409, 0x23603da5, 0x000000e0, 0x00020002 }, { 0x00000c01, 0x236401a5, 0x000000e2, 0x00000000 }, { 0x00000801, 0x23680061, 0x00000000, 0x0003001f }, { 0x00400001, 0x22080108, 0x00690200, 0x00000000 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x26e00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x23e00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25000021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x26200021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x27400021, 0x008d0360, 0x00000000 }, { 0x00000040, 0x24a01ca5, 0x00000360, 0x00000020 }, { 0x00000040, 0x25c41ca5, 0x00000364, 0x00000004 }, { 0x00000040, 0x26e41ca5, 0x00000364, 0x00000004 }, { 0x00000040, 0x26e01ca5, 0x00000360, 0x00000020 }, { 0x00600001, 0x63a00231, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x63a10231, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x63a20231, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x63a30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x63c00231, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x63c10231, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x63c20231, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x63c30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64c00231, 0x00ae8011, 0x00000000 }, { 0x00600001, 0x64c10231, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x64c20231, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x64c30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64e00231, 0x00ae8031, 0x00000000 }, { 0x00600001, 0x64e10231, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x64e20231, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x64e30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x63e00231, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x63e10231, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x63e20231, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x63e30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64000231, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x64010231, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x64020231, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x64030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x65000231, 0x00ae8051, 0x00000000 }, { 0x00600001, 0x65010231, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x65020231, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x65030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x65200231, 0x00ae8071, 0x00000000 }, { 0x00600001, 0x65210231, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x65220231, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x65230231, 0x0000005f, 0x00000000 }, { 0x05800031, 0x20000e24, 0x00000380, 0x0a0a8018 }, { 0x05800031, 0x20000e24, 0x000004a0, 0x0a0a8018 }, { 0x00400040, 0x22002d08, 0x00690208, 0x02000200 }, { 0x00600001, 0x65e00231, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x65e10231, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x65e20231, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x65e30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66000231, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x66010231, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x66020231, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x66030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67000231, 0x00ae8011, 0x00000000 }, { 0x00600001, 0x67010231, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x67020231, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x67030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67200231, 0x00ae8031, 0x00000000 }, { 0x00600001, 0x67210231, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x67220231, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x67230231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66200231, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x66210231, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x66220231, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x66230231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66400231, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x66410231, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x66420231, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x66430231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67400231, 0x00ae8051, 0x00000000 }, { 0x00600001, 0x67410231, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x67420231, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x67430231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67600231, 0x00ae8071, 0x00000000 }, { 0x00600001, 0x67610231, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x67620231, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x67630231, 0x0000005f, 0x00000000 }, { 0x05800031, 0x20000e24, 0x000005c0, 0x0a0a8018 }, { 0x05800031, 0x20000e24, 0x000006e0, 0x0a0a8018 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x26e00021, 0x008d0360, 0x00000000 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000008 }, { 0x00000040, 0x24a01ca5, 0x00000360, 0x00000020 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000008 }, { 0x00000040, 0x25c41ca5, 0x00000364, 0x0000000c }, { 0x00000040, 0x26e41ca5, 0x00000364, 0x0000000c }, { 0x00000040, 0x26e01ca5, 0x00000360, 0x00000020 }, { 0x00400040, 0x22002d08, 0x00690208, 0x04000400 }, { 0x00600001, 0x63a00231, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x63a10231, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x63a20231, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x63a30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x63c00231, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x63c10231, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x63c20231, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x63c30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64c00231, 0x00ae8011, 0x00000000 }, { 0x00600001, 0x64c10231, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x64c20231, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x64c30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64e00231, 0x00ae8031, 0x00000000 }, { 0x00600001, 0x64e10231, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x64e20231, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x64e30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x63e00231, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x63e10231, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x63e20231, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x63e30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64000231, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x64010231, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x64020231, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x64030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x65000231, 0x00ae8051, 0x00000000 }, { 0x00600001, 0x65010231, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x65020231, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x65030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x65200231, 0x00ae8071, 0x00000000 }, { 0x00600001, 0x65210231, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x65220231, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x65230231, 0x0000005f, 0x00000000 }, { 0x05800031, 0x20000e24, 0x00000380, 0x0a0a8018 }, { 0x05800031, 0x20000e24, 0x000004a0, 0x0a0a8018 }, { 0x00400040, 0x22002d08, 0x00690208, 0x06000600 }, { 0x00600001, 0x65e00231, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x65e10231, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x65e20231, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x65e30231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66000231, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x66010231, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x66020231, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x66030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67000231, 0x00ae8011, 0x00000000 }, { 0x00600001, 0x67010231, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x67020231, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x67030231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67200231, 0x00ae8031, 0x00000000 }, { 0x00600001, 0x67210231, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x67220231, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x67230231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66200231, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x66210231, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x66220231, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x66230231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66400231, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x66410231, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x66420231, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x66430231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67400231, 0x00ae8051, 0x00000000 }, { 0x00600001, 0x67410231, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x67420231, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x67430231, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67600231, 0x00ae8071, 0x00000000 }, { 0x00600001, 0x67610231, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x67620231, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x67630231, 0x0000005f, 0x00000000 }, { 0x05800031, 0x20000e24, 0x000005c0, 0x0a0a8018 }, { 0x05800031, 0x20000e24, 0x000006e0, 0x0a0a8018 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl3_to_pa.asm000066400000000000000000000005101231401140700247670ustar00rootroot00000000000000// Module name: AVS .kernel PL3_TO_PA .code #include "VP_Setup.g4a" #include "Set_Layer_0.g4a" #include "Set_AVS_Buf_0123_PL3.g4a" #include "PL3_AVS_Buf_0.g4a" #include "PL3_AVS_Buf_1.g4a" #include "PL3_AVS_Buf_2.g4a" #include "PL3_AVS_Buf_3.g4a" #include "Save_AVS_PA.g4a" #include "EOT.g4a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/pl3_to_pa.g75b000066400000000000000000001141231231401140700247610ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000000d0 }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000002c0 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x29000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000002b0 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2b000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000002b0 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2d000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000002b0 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2f000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082e2c, 0x0069005c, 0x03a003a0 }, { 0x00000409, 0x23603da5, 0x000000e0, 0x00010001 }, { 0x00000c01, 0x236401a5, 0x000000e2, 0x00000000 }, { 0x00000801, 0x23680061, 0x00000000, 0x0001001f }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x02000200 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x06000600 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x08000800 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000002 }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x02000200 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000004 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000006 }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000008 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x0000000a }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x06000600 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x0000000c }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x0000000e }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl3_to_pa.g7b000066400000000000000000001141231231401140700246740ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000001a }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000058 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x29000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000056 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2b000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000056 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2d000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000056 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2f000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082e2c, 0x0069005c, 0x03a003a0 }, { 0x00000409, 0x23603da5, 0x000000e0, 0x00010001 }, { 0x00000c01, 0x236401a5, 0x000000e2, 0x00000000 }, { 0x00000801, 0x23680061, 0x00000000, 0x0001001f }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x02000200 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x06000600 }, { 0x80400040, 0xc0002d29, 0x008a8000, 0x00800080 }, { 0x80400040, 0xc0202d29, 0x008a8020, 0x00800080 }, { 0x80400040, 0xc0402d29, 0x008a8040, 0x00800080 }, { 0x80400040, 0xc0602d29, 0x008a8060, 0x00800080 }, { 0x80600040, 0xa4002d29, 0x008d8400, 0x00800080 }, { 0x80600040, 0xa4202d29, 0x008d8420, 0x00800080 }, { 0x80600040, 0xa4402d29, 0x008d8440, 0x00800080 }, { 0x80600040, 0xa4602d29, 0x008d8460, 0x00800080 }, { 0x80400040, 0xc8002d29, 0x008a8800, 0x00800080 }, { 0x80400040, 0xc8202d29, 0x008a8820, 0x00800080 }, { 0x80400040, 0xc8402d29, 0x008a8840, 0x00800080 }, { 0x80400040, 0xc8602d29, 0x008a8860, 0x00800080 }, { 0x80400040, 0xc0102d29, 0x008a8010, 0x00800080 }, { 0x80400040, 0xc0302d29, 0x008a8030, 0x00800080 }, { 0x80400040, 0xc0502d29, 0x008a8050, 0x00800080 }, { 0x80400040, 0xc0702d29, 0x008a8070, 0x00800080 }, { 0x80600040, 0xa4102d29, 0x008d8410, 0x00800080 }, { 0x80600040, 0xa4302d29, 0x008d8430, 0x00800080 }, { 0x80600040, 0xa4502d29, 0x008d8450, 0x00800080 }, { 0x80600040, 0xa4702d29, 0x008d8470, 0x00800080 }, { 0x80400040, 0xc8102d29, 0x008a8810, 0x00800080 }, { 0x80400040, 0xc8302d29, 0x008a8830, 0x00800080 }, { 0x80400040, 0xc8502d29, 0x008a8850, 0x00800080 }, { 0x80400040, 0xc8702d29, 0x008a8870, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x08000800 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000002 }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x02000200 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000004 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x00000006 }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x00000008 }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x0000000a }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x06000600 }, { 0x00000040, 0x23841ca5, 0x00000364, 0x0000000c }, { 0x00000040, 0x24a41ca5, 0x00000364, 0x0000000e }, { 0x00600401, 0xf8000231, 0x00cf8001, 0x00000000 }, { 0x00600401, 0xf8200231, 0x00cf8021, 0x00000000 }, { 0x00800c01, 0xd0000231, 0x00d28401, 0x00000000 }, { 0x00800c01, 0xd0200231, 0x00d28421, 0x00000000 }, { 0x00600801, 0xf4000231, 0x00cf8801, 0x00000000 }, { 0x00600801, 0xf4200231, 0x00cf8821, 0x00000000 }, { 0x00600401, 0xf9200231, 0x00cf8041, 0x00000000 }, { 0x00600401, 0xf9400231, 0x00cf8061, 0x00000000 }, { 0x00800c01, 0xd1200231, 0x00d28441, 0x00000000 }, { 0x00800c01, 0xd1400231, 0x00d28461, 0x00000000 }, { 0x00600801, 0xf5200231, 0x00cf8841, 0x00000000 }, { 0x00600801, 0xf5400231, 0x00cf8861, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x060a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8018 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl3_to_pl2.asm000066400000000000000000000005131231401140700250670ustar00rootroot00000000000000// Module name: AVS .kernel PL3_TO_PL2 .code #include "VP_Setup.g4a" #include "Set_Layer_0.g4a" #include "Set_AVS_Buf_0123_PL3.g4a" #include "PL3_AVS_Buf_0.g4a" #include "PL3_AVS_Buf_1.g4a" #include "PL3_AVS_Buf_2.g4a" #include "PL3_AVS_Buf_3.g4a" #include "Save_AVS_NV12.g4a" #include "EOT.g4a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/pl3_to_pl2.g75b000066400000000000000000001074261231401140700250660ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000000d0 }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000002c0 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x29000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000002b0 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2b000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000002b0 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2d000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000002b0 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2f000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00000401, 0x24a001a5, 0x000000e0, 0x00000000 }, { 0x00000c08, 0x24a43da5, 0x000000e2, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x0007000f }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x44c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x44d00231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x44c10231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x44d10231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x44e00231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x44f00231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x44e10231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x44f10231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x45000231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x45100231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x45010231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x45110231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x45200231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x45300231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x45210231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x45310231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl3_to_pl2.g7b000066400000000000000000001074261231401140700250010ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000001a }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000058 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x29000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000056 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2b000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000056 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2d000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000056 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2f000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00000401, 0x24a001a5, 0x000000e0, 0x00000000 }, { 0x00000c08, 0x24a43da5, 0x000000e2, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x0007000f }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x44c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x44d00231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x44c10231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x44d10231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x44e00231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x44f00231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x44e10231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x44f10231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x45000231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x45100231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x45010231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x45110231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x45200231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x45300231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x45210231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x45310231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl3_to_pl3.asm000066400000000000000000000005121231401140700250670ustar00rootroot00000000000000// Module name: AVS .kernel PL3_TO_PL3 .code #include "VP_Setup.g4a" #include "Set_Layer_0.g4a" #include "Set_AVS_Buf_0123_PL3.g4a" #include "PL3_AVS_Buf_0.g4a" #include "PL3_AVS_Buf_1.g4a" #include "PL3_AVS_Buf_2.g4a" #include "PL3_AVS_Buf_3.g4a" #include "Save_AVS_PL3.g4a" #include "EOT.g4a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/pl3_to_pl3.g75b000066400000000000000000001023751231401140700250650ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000000d0 }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000002c0 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x29000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000002b0 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2b000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000002b0 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2d000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000002b0 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2f000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00200408, 0x24a03da5, 0x004500e0, 0x00010001 }, { 0x00200408, 0x25c03da5, 0x004500e0, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x00070007 }, { 0x00000801, 0x25c80061, 0x00000000, 0x00070007 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x80600040, 0xc8002d29, 0x00ae8800, 0x00800080 }, { 0x80600040, 0xc8402d29, 0x00ae8840, 0x00800080 }, { 0x80600040, 0xc0002d29, 0x00ae8000, 0x00800080 }, { 0x80600040, 0xc0402d29, 0x00ae8040, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x80600040, 0xd8002d29, 0x00ae9800, 0x00800080 }, { 0x80600040, 0xd8402d29, 0x00ae9840, 0x00800080 }, { 0x80600040, 0xd0002d29, 0x00ae9000, 0x00800080 }, { 0x80600040, 0xd0402d29, 0x00ae9040, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x80600040, 0xc8002d29, 0x00ae8800, 0x00800080 }, { 0x80600040, 0xc8402d29, 0x00ae8840, 0x00800080 }, { 0x80600040, 0xc0002d29, 0x00ae8000, 0x00800080 }, { 0x80600040, 0xc0402d29, 0x00ae8040, 0x00800080 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x80600040, 0xd8002d29, 0x00ae9800, 0x00800080 }, { 0x80600040, 0xd8402d29, 0x00ae9840, 0x00800080 }, { 0x80600040, 0xd0002d29, 0x00ae9000, 0x00800080 }, { 0x80600040, 0xd0402d29, 0x00ae9040, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x24c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x24c80231, 0x00cf8841, 0x00000000 }, { 0x00600401, 0x25e00231, 0x00cf8001, 0x00000000 }, { 0x00600c01, 0x25e80231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600c01, 0x24d00231, 0x00cf9801, 0x00000000 }, { 0x00600801, 0x24d80231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x25f00231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x25f80231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x24e00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x24e80231, 0x00cf8841, 0x00000000 }, { 0x00600401, 0x26000231, 0x00cf8001, 0x00000000 }, { 0x00600c01, 0x26080231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600c01, 0x24f00231, 0x00cf9801, 0x00000000 }, { 0x00600801, 0x24f80231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x26100231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x26180231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8019 }, { 0x05000031, 0x20000e24, 0x000005c0, 0x060a801a }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/pl3_to_pl3.g7b000066400000000000000000001023751231401140700250000ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000001a }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000058 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x28800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x29000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000056 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2a800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2b000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000056 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2c800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2d000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000056 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000d000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x00000001, 0x21d403bd, 0x00000228, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x00000001, 0x222803bd, 0x000001d4, 0x00000000 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044eb801 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2e800229, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x044ebc02 }, { 0x00000001, 0x22080061, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2f000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00200408, 0x24a03da5, 0x004500e0, 0x00010001 }, { 0x00200408, 0x25c03da5, 0x004500e0, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x00070007 }, { 0x00000801, 0x25c80061, 0x00000000, 0x00070007 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x80600040, 0xc8002d29, 0x00ae8800, 0x00800080 }, { 0x80600040, 0xc8402d29, 0x00ae8840, 0x00800080 }, { 0x80600040, 0xc0002d29, 0x00ae8000, 0x00800080 }, { 0x80600040, 0xc0402d29, 0x00ae8040, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x80600040, 0xd8002d29, 0x00ae9800, 0x00800080 }, { 0x80600040, 0xd8402d29, 0x00ae9840, 0x00800080 }, { 0x80600040, 0xd0002d29, 0x00ae9000, 0x00800080 }, { 0x80600040, 0xd0402d29, 0x00ae9040, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x80600040, 0xc8002d29, 0x00ae8800, 0x00800080 }, { 0x80600040, 0xc8402d29, 0x00ae8840, 0x00800080 }, { 0x80600040, 0xc0002d29, 0x00ae8000, 0x00800080 }, { 0x80600040, 0xc0402d29, 0x00ae8040, 0x00800080 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x80600040, 0xd8002d29, 0x00ae9800, 0x00800080 }, { 0x80600040, 0xd8402d29, 0x00ae9840, 0x00800080 }, { 0x80600040, 0xd0002d29, 0x00ae9000, 0x00800080 }, { 0x80600040, 0xd0402d29, 0x00ae9040, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x24c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x24c80231, 0x00cf8841, 0x00000000 }, { 0x00600401, 0x25e00231, 0x00cf8001, 0x00000000 }, { 0x00600c01, 0x25e80231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600c01, 0x24d00231, 0x00cf9801, 0x00000000 }, { 0x00600801, 0x24d80231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x25f00231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x25f80231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x24e00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x24e80231, 0x00cf8841, 0x00000000 }, { 0x00600401, 0x26000231, 0x00cf8001, 0x00000000 }, { 0x00600c01, 0x26080231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600c01, 0x24f00231, 0x00cf9801, 0x00000000 }, { 0x00600801, 0x24f80231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x26100231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x26180231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x060a8019 }, { 0x05000031, 0x20000e24, 0x000005c0, 0x060a801a }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/rgbx_to_nv12.asm000066400000000000000000000005441231401140700254300ustar00rootroot00000000000000// Module name: AVS .kernel RGBX_TO_NV12 .code #include "VP_Setup.g4a" #include "Set_Layer_0.g4a" #include "Set_AVS_Buf_0123_BGRA.g4a" #include "PA_AVS_Buf_0.g4a" #include "PA_AVS_Buf_1.g4a" #include "PA_AVS_Buf_2.g4a" #include "PA_AVS_Buf_3.g4a" #include "RGB_to_YUV.g4a" #include "Save_AVS_NV12.g4a" #include "EOT.g4a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen7/rgbx_to_nv12.g75b000066400000000000000000001616051231401140700254220ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000090 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000000f0 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000180 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x000000d0 }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000240 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000230 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000230 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000230 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x000001a0 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x22000128, 0x006902c0, 0x00000000 }, { 0x00400001, 0x22080128, 0x006902c0, 0x00000000 }, { 0x02800005, 0x20003d2c, 0x00000040, 0x00010001 }, { 0x00010001, 0x22200109, 0x00000200, 0x00000000 }, { 0x00010001, 0x22000108, 0x00000202, 0x00000000 }, { 0x00010001, 0x22020128, 0x00000220, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8011, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8031, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8051, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8071, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0610231, 0x00cf05c0, 0x00000000 }, { 0x00600040, 0x22002d08, 0x008d0200, 0x02000200 }, { 0x00600001, 0x2380023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8011, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8031, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8051, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8071, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0610231, 0x00cf05c0, 0x00000000 }, { 0x00600040, 0x22002d08, 0x008d0200, 0x02000200 }, { 0x00600001, 0x2380023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8011, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8031, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8051, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8071, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0610231, 0x00cf05c0, 0x00000000 }, { 0x00600040, 0x22002d08, 0x008d0200, 0x02000200 }, { 0x00600001, 0x2380023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8011, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8031, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8051, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8071, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0610231, 0x00cf05c0, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00000401, 0x24a001a5, 0x000000e0, 0x00000000 }, { 0x00000c08, 0x24a43da5, 0x000000e2, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x0007000f }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x44c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x44d00231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x44c10231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x44d10231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x44e00231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x44f00231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x44e10231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x44f10231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x45000231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x45100231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x45010231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x45110231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x45200231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x45300231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x45210231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x45310231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen7/rgbx_to_nv12.g7b000066400000000000000000001616051231401140700253350ustar00rootroot00000000000000 { 0x00600001, 0x23600021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200021, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400021, 0x008d0000, 0x00000000 }, { 0x00600041, 0x206077bd, 0x008d0060, 0x000000f0 }, { 0x00200001, 0x211401bd, 0x004500e0, 0x00000000 }, { 0x01600010, 0x20002e24, 0x0000005a, 0x00010001 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00000000 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000114 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240003bc, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c077bd, 0x00000060, 0x00000220 }, { 0x00000001, 0x240003bc, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a077bd, 0x00000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00020002 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000114 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240403bc, 0x000000c4, 0x00000000 }, { 0x00110048, 0x20c477bd, 0x00000064, 0x00000220 }, { 0x00000001, 0x240403bc, 0x000000a4, 0x00000000 }, { 0x00000048, 0x20a477bd, 0x00000084, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00040004 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000114 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240803bc, 0x000000c8, 0x00000000 }, { 0x00110048, 0x20c877bd, 0x00000068, 0x00000220 }, { 0x00000001, 0x240803bc, 0x000000a8, 0x00000000 }, { 0x00000048, 0x20a877bd, 0x00000088, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00060006 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000114 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x240c03bc, 0x000000cc, 0x00000000 }, { 0x00110048, 0x20cc77bd, 0x0000006c, 0x00000220 }, { 0x00000001, 0x240c03bc, 0x000000ac, 0x00000000 }, { 0x00000048, 0x20ac77bd, 0x0000008c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x00080008 }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000114 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241003bc, 0x000000d0, 0x00000000 }, { 0x00110048, 0x20d077bd, 0x00000070, 0x00000220 }, { 0x00000001, 0x241003bc, 0x000000b0, 0x00000000 }, { 0x00000048, 0x20b077bd, 0x00000090, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000a000a }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000114 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241403bc, 0x000000d4, 0x00000000 }, { 0x00110048, 0x20d477bd, 0x00000074, 0x00000220 }, { 0x00000001, 0x241403bc, 0x000000b4, 0x00000000 }, { 0x00000048, 0x20b477bd, 0x00000094, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000c000c }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000114 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241803bc, 0x000000d8, 0x00000000 }, { 0x00110048, 0x20d877bd, 0x00000078, 0x00000220 }, { 0x00000001, 0x241803bc, 0x000000b8, 0x00000000 }, { 0x00000048, 0x20b877bd, 0x00000098, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000008, 0x22202d29, 0x00000044, 0x000e000e }, { 0x00000005, 0x22202d29, 0x00000220, 0x00030003 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00010001 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000012 }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00020002 }, { 0x00010220, 0x34001c00, 0x02001400, 0x0000001e }, { 0x01000010, 0x20002d2c, 0x02000220, 0x00030003 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000030 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000114 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000118 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000118 }, { 0x00000001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000024 }, { 0x00110001, 0x2200013d, 0x00000040, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004114, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00000040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00000040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000220 }, { 0x00000220, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00110001, 0x2200013d, 0x00000042, 0x00000000 }, { 0x00110040, 0x222077bd, 0x00004118, 0x00000200 }, { 0x00110040, 0x22207fbd, 0x00000220, 0xc1800000 }, { 0x00110001, 0x241c03bc, 0x000000dc, 0x00000000 }, { 0x00110048, 0x20dc77bd, 0x0000007c, 0x00000220 }, { 0x00000001, 0x241c03bc, 0x000000bc, 0x00000000 }, { 0x00000048, 0x20bc77bd, 0x0000009c, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a00169, 0x00000000, 0xffffffff }, { 0x02000010, 0x20002d24, 0x020000e4, 0x00000000 }, { 0x02010010, 0x20002d24, 0x020000e6, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x0000001a }, { 0x00000005, 0x23022d31, 0x00000044, 0x00030003 }, { 0x00000401, 0x233803bd, 0x000000f4, 0x00000000 }, { 0x00000c01, 0x233003bd, 0x00000060, 0x00000000 }, { 0x00000c01, 0x233403bd, 0x00000080, 0x00000000 }, { 0x00000c01, 0x232803bd, 0x000000c0, 0x00000000 }, { 0x00000801, 0x232c03bd, 0x000000a0, 0x00000000 }, { 0x00000001, 0x240803bc, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24087fbc, 0x00000060, 0x41000000 }, { 0x00000448, 0x22e87fbd, 0x000000f4, 0x41e00000 }, { 0x00000c41, 0x22e47fbd, 0x00000080, 0x40800000 }, { 0x00000001, 0x241003bc, 0x00000060, 0x00000000 }, { 0x00000c48, 0x22f07fbd, 0x000000f4, 0x41000000 }, { 0x00000801, 0x22f40061, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006ea2 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00460046 }, { 0x00400009, 0x22c02d8d, 0x00690400, 0x00050005 }, { 0x00400001, 0x2400036c, 0x00000000, 0x00006204 }, { 0x00400040, 0x24002d8c, 0x00690400, 0x00400040 }, { 0x00400409, 0x22402d8d, 0x00690400, 0x00050005 }, { 0x00000801, 0x22500061, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00061, 0x00000000, 0x00400040 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000048 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000401, 0x233c0021, 0x000000fc, 0x00000000 }, { 0x00000801, 0x23240121, 0x000000f8, 0x00000000 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x28000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000046 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000001 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2a000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000046 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000002 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2c000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00110220, 0x34001c00, 0x02001400, 0x00000046 }, { 0x00000040, 0x22000c20, 0x000002f4, 0x050eb400 }, { 0x00000001, 0x22080061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23240d21, 0x000000f8, 0x00000003 }, { 0x00600001, 0x22200021, 0x008d0320, 0x00000000 }, { 0x00000001, 0x21d00109, 0x00000600, 0x00000000 }, { 0x02000005, 0x20002d28, 0x00000046, 0x00020002 }, { 0x00110220, 0x34001c00, 0x00001400, 0x00000034 }, { 0x02600005, 0x20002d28, 0x00000046, 0x00040004 }, { 0x00610001, 0x240003bc, 0x00000228, 0x00000000 }, { 0x00610048, 0x24007fbc, 0x00000230, 0xc0000000 }, { 0x00610048, 0x24007fbc, 0x00000238, 0x40400000 }, { 0x00010001, 0x21c8039d, 0x00210400, 0x00000000 }, { 0x00110001, 0x21c803bd, 0x00000228, 0x00000000 }, { 0x00000005, 0x21c42d21, 0x00000046, 0xfff8fff8 }, { 0x0000000c, 0x21c41c21, 0x000001c4, 0x00000003 }, { 0x00000001, 0x21c4003d, 0x000001c4, 0x00000000 }, { 0x00000041, 0x21c077bd, 0x000001c8, 0x000001c4 }, { 0x00000040, 0x21c87fbd, 0x000001c0, 0x3ca00000 }, { 0x00000040, 0x21cc7fbd, 0x000001c0, 0x3f7f0000 }, { 0x05000010, 0x20007fbc, 0x000001c0, 0x00000000 }, { 0x00000001, 0x21c003a5, 0x000001c0, 0x00000000 }, { 0x00010040, 0x21c01ca5, 0x000001c0, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001c8, 0x00000000 }, { 0x00000001, 0x21c803a5, 0x000001c8, 0x00000000 }, { 0x00010040, 0x21c81ca5, 0x000001c8, 0xffffffff }, { 0x05000010, 0x20007fbc, 0x000001cc, 0x00000000 }, { 0x00000001, 0x21cc03a5, 0x000001cc, 0x00000000 }, { 0x00010040, 0x21cc1ca5, 0x000001cc, 0xffffffff }, { 0x00000001, 0x26000168, 0x00000000, 0x00000000 }, { 0x03000010, 0x200014a4, 0x040001c8, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x04000228, 0x0000404c }, { 0x01110010, 0x200014a4, 0x000001cc, 0x000001c0 }, { 0x00010040, 0x222877bd, 0x00000228, 0x00000048 }, { 0x00000001, 0x26000128, 0x000001d0, 0x00000000 }, { 0x02000031, 0x2e000229, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x22000128, 0x006902c0, 0x00000000 }, { 0x00400001, 0x22080128, 0x006902c0, 0x00000000 }, { 0x02800005, 0x20003d2c, 0x00000040, 0x00010001 }, { 0x00010001, 0x22200109, 0x00000200, 0x00000000 }, { 0x00010001, 0x22000108, 0x00000202, 0x00000000 }, { 0x00010001, 0x22020128, 0x00000220, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8011, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8031, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8051, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8071, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0610231, 0x00cf05c0, 0x00000000 }, { 0x00600040, 0x22002d08, 0x008d0200, 0x02000200 }, { 0x00600001, 0x2380023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8011, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8031, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8051, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8071, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0610231, 0x00cf05c0, 0x00000000 }, { 0x00600040, 0x22002d08, 0x008d0200, 0x02000200 }, { 0x00600001, 0x2380023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8011, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8031, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8051, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8071, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0610231, 0x00cf05c0, 0x00000000 }, { 0x00600040, 0x22002d08, 0x008d0200, 0x02000200 }, { 0x00600001, 0x2380023d, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8801, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8811, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8011, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0000169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4010231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8010231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0010231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8821, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8831, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8031, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0200169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4210231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8210231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0210231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8841, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8851, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8051, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0400169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4410231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8410231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0410231, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x2380023d, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x23a0023d, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x23c0023d, 0x00ae8861, 0x00000000 }, { 0x00600001, 0x23e0023d, 0x00ae8871, 0x00000000 }, { 0x00600001, 0x2400023d, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x2420023d, 0x00ae8071, 0x00000000 }, { 0x00800041, 0x24007fbc, 0x008d0380, 0x3e991687 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0x3f1645a2 }, { 0x00800048, 0x24807fbd, 0x008d0400, 0x3de978d5 }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0xbe2d0e56 }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbea978d5 }, { 0x00800048, 0x24c07fbd, 0x008d0400, 0x3eff7cee }, { 0x00800001, 0x240003fc, 0x00000000, 0x43000000 }, { 0x00800048, 0x24007fbc, 0x008d0380, 0x3eff7cee }, { 0x00800048, 0x24007fbc, 0x008d03c0, 0xbed60419 }, { 0x00800048, 0x25007fbd, 0x008d0400, 0xbda6809d }, { 0x00800001, 0x454003ad, 0x008d0480, 0x00000000 }, { 0x00800001, 0x458003ad, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c003ad, 0x008d0500, 0x00000000 }, { 0x00800001, 0xb4600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb8600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xb0600169, 0x00000000, 0x00000000 }, { 0x00800001, 0xd4610231, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xd8610231, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xd0610231, 0x00cf05c0, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00600001, 0x23800021, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d0360, 0x00000000 }, { 0x00200401, 0x238001a5, 0x004500e0, 0x00000000 }, { 0x00000401, 0x24a001a5, 0x000000e0, 0x00000000 }, { 0x00000c08, 0x24a43da5, 0x000000e2, 0x00010001 }, { 0x00000801, 0x23880061, 0x00000000, 0x000f000f }, { 0x00000801, 0x24a80061, 0x00000000, 0x0007000f }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x80800040, 0xa4002d29, 0x00b18400, 0x00800080 }, { 0x80800040, 0xa4202d29, 0x00b18420, 0x00800080 }, { 0x80800040, 0xa4402d29, 0x00b18440, 0x00800080 }, { 0x80800040, 0xa4602d29, 0x00b18460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae8800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae8820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae8840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae8860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xc8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae8000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae8020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae8040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae8060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xc0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x80800040, 0xb4002d29, 0x00b19400, 0x00800080 }, { 0x80800040, 0xb4202d29, 0x00b19420, 0x00800080 }, { 0x80800040, 0xb4402d29, 0x00b19440, 0x00800080 }, { 0x80800040, 0xb4602d29, 0x00b19460, 0x00800080 }, { 0x00600008, 0x45c03d29, 0x00ae9800, 0x00010001 }, { 0x00600008, 0x45e03d29, 0x00ae9820, 0x00010001 }, { 0x00600008, 0x46003d29, 0x00ae9840, 0x00010001 }, { 0x00600008, 0x46203d29, 0x00ae9860, 0x00010001 }, { 0x00600040, 0x45c02529, 0x00ae05c0, 0x00ae05e0 }, { 0x80600040, 0xd8002d29, 0x00ae05c0, 0x00800080 }, { 0x00600040, 0x46002529, 0x00ae0600, 0x00ae0620 }, { 0x80600040, 0xd8402d29, 0x00ae0600, 0x00800080 }, { 0x00600008, 0x46403d29, 0x00ae9000, 0x00010001 }, { 0x00600008, 0x46603d29, 0x00ae9020, 0x00010001 }, { 0x00600008, 0x46803d29, 0x00ae9040, 0x00010001 }, { 0x00600008, 0x46a03d29, 0x00ae9060, 0x00010001 }, { 0x00600040, 0x46402529, 0x00ae0640, 0x00ae0660 }, { 0x80600040, 0xd0002d29, 0x00ae0640, 0x00800080 }, { 0x00600040, 0x46802529, 0x00ae0680, 0x00ae06a0 }, { 0x80600040, 0xd0402d29, 0x00ae0680, 0x00800080 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x02000200 }, { 0x00800401, 0x23a00231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x23b00231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x23c00231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x23d00231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x44c00231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x44d00231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x44c10231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x44d10231, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22002da8, 0x006902c0, 0x04000400 }, { 0x00800401, 0x23e00231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x23f00231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24000231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24100231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x44e00231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x44f00231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x44e10231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x44f10231, 0x00cf9041, 0x00000000 }, { 0x00400040, 0x22082da8, 0x006902c0, 0x06000600 }, { 0x00800401, 0x24200231, 0x00d28401, 0x00000000 }, { 0x00800801, 0x24300231, 0x00d28421, 0x00000000 }, { 0x00800401, 0x24400231, 0x00d28441, 0x00000000 }, { 0x00800801, 0x24500231, 0x00d28461, 0x00000000 }, { 0x00600401, 0x45000231, 0x00cf8801, 0x00000000 }, { 0x00600c01, 0x45100231, 0x00cf8841, 0x00000000 }, { 0x00600c01, 0x45010231, 0x00cf8001, 0x00000000 }, { 0x00600801, 0x45110231, 0x00cf8041, 0x00000000 }, { 0x00800401, 0x24600231, 0x00d29401, 0x00000000 }, { 0x00800801, 0x24700231, 0x00d29421, 0x00000000 }, { 0x00800401, 0x24800231, 0x00d29441, 0x00000000 }, { 0x00800801, 0x24900231, 0x00d29461, 0x00000000 }, { 0x00600401, 0x45200231, 0x00cf9801, 0x00000000 }, { 0x00600c01, 0x45300231, 0x00cf9841, 0x00000000 }, { 0x00600c01, 0x45210231, 0x00cf9001, 0x00000000 }, { 0x00600801, 0x45310231, 0x00cf9041, 0x00000000 }, { 0x05000031, 0x20000e24, 0x00000380, 0x120a8018 }, { 0x05000031, 0x20000e24, 0x000004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20001e24, 0x00000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen75/000077500000000000000000000000001231401140700224765ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/post_processing/gen75/Makefile.am000066400000000000000000000003541231401140700245340ustar00rootroot00000000000000INTEL_PP_PRE_G75B = \ sharpening_h_blur.g75b \ sharpening_unmask.g75b \ sharpening_v_blur.g75b EXTRA_DIST = $(INTEL_PP_PRE_G75B) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/post_processing/gen75/sharpening_h_blur.g75b000066400000000000000000002616561231401140700266750ustar00rootroot00000000000000{ 0x00000001, 0x23400161, 0x00000000, 0x00000000 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000001, 0x23440161, 0x00000000, 0x00020002 }, { 0x00000001, 0x20480061, 0x00000000, 0x000f0007 }, { 0x00000001, 0x20400161, 0x00000000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000340, 0x02490000 }, { 0x00000001, 0x204403bd, 0x00000028, 0x00000000 }, { 0x00000001, 0x202c0161, 0x00000000, 0x00040004 }, { 0x0c600031, 0x204003a1, 0x00000040, 0x00000200 }, { 0x00000040, 0x20243c21, 0x00000020, 0xfffcfffc }, { 0x06000010, 0x20002c20, 0x02000024, 0x00040004 }, { 0x00200001, 0x232803bd, 0x004500b0, 0x00000000 }, { 0x00200001, 0x230803bd, 0x004500a0, 0x00000000 }, { 0x00200001, 0x22e803bd, 0x00450090, 0x00000000 }, { 0x00200001, 0x22c803bd, 0x00450080, 0x00000000 }, { 0x00200001, 0x22a803bd, 0x00450070, 0x00000000 }, { 0x00200001, 0x228803bd, 0x00450060, 0x00000000 }, { 0x00200001, 0x226803bd, 0x00450050, 0x00000000 }, { 0x00200001, 0x224803bd, 0x00450040, 0x00000000 }, { 0x00200001, 0x233803bd, 0x004500b8, 0x00000000 }, { 0x00200001, 0x231803bd, 0x004500a8, 0x00000000 }, { 0x00200001, 0x22f803bd, 0x00450098, 0x00000000 }, { 0x00200001, 0x22d803bd, 0x00450088, 0x00000000 }, { 0x00200001, 0x22b803bd, 0x00450078, 0x00000000 }, { 0x00200001, 0x229803bd, 0x00450068, 0x00000000 }, { 0x00200001, 0x227803bd, 0x00450058, 0x00000000 }, { 0x00200001, 0x225803bd, 0x00450048, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x000067d0 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000340, 0x02490000 }, { 0x00200001, 0x226003bd, 0x00450268, 0x00000000 }, { 0x00200001, 0x224003bd, 0x00450248, 0x00000000 }, { 0x00200001, 0x228003bd, 0x00450288, 0x00000000 }, { 0x00200001, 0x22c003bd, 0x004502c8, 0x00000000 }, { 0x00200001, 0x22a003bd, 0x004502a8, 0x00000000 }, { 0x00200001, 0x232003bd, 0x00450328, 0x00000000 }, { 0x00000001, 0x20480061, 0x00000000, 0x000f0007 }, { 0x00200001, 0x230003bd, 0x00450308, 0x00000000 }, { 0x00200001, 0x22e003bd, 0x004502e8, 0x00000000 }, { 0x00000040, 0x20402c21, 0x0000002c, 0x00040004 }, { 0x00000001, 0x204403bd, 0x00000028, 0x00000000 }, { 0x0c600031, 0x204003a1, 0x00000040, 0x00000200 }, { 0x00200001, 0x227003bd, 0x00450278, 0x00000000 }, { 0x00200001, 0x225003bd, 0x00450258, 0x00000000 }, { 0x00200001, 0x226803bd, 0x00450050, 0x00000000 }, { 0x00200001, 0x224803bd, 0x00450040, 0x00000000 }, { 0x00200001, 0x227803bd, 0x00450058, 0x00000000 }, { 0x00200001, 0x225803bd, 0x00450048, 0x00000000 }, { 0x00000001, 0x2040023d, 0x00000240, 0x00000000 }, { 0x00200001, 0x229003bd, 0x00450298, 0x00000000 }, { 0x00000001, 0x2044023d, 0x00000250, 0x00000000 }, { 0x00000001, 0x2048023d, 0x00000260, 0x00000000 }, { 0x00200001, 0x228803bd, 0x00450060, 0x00000000 }, { 0x00200001, 0x22d003bd, 0x004502d8, 0x00000000 }, { 0x00200001, 0x22b003bd, 0x004502b8, 0x00000000 }, { 0x00200001, 0x229803bd, 0x00450068, 0x00000000 }, { 0x00000001, 0x204c023d, 0x00000270, 0x00000000 }, { 0x00200001, 0x22c803bd, 0x00450080, 0x00000000 }, { 0x00200001, 0x22a803bd, 0x00450070, 0x00000000 }, { 0x00000001, 0x2050023d, 0x00000280, 0x00000000 }, { 0x00200001, 0x22d803bd, 0x00450088, 0x00000000 }, { 0x00200001, 0x22b803bd, 0x00450078, 0x00000000 }, { 0x00200001, 0x233003bd, 0x00450338, 0x00000000 }, { 0x00200001, 0x231003bd, 0x00450318, 0x00000000 }, { 0x00200001, 0x22f003bd, 0x004502f8, 0x00000000 }, { 0x00000001, 0x2054023d, 0x00000290, 0x00000000 }, { 0x00200001, 0x22e803bd, 0x00450090, 0x00000000 }, { 0x00200001, 0x230803bd, 0x004500a0, 0x00000000 }, { 0x00200001, 0x232803bd, 0x004500b0, 0x00000000 }, { 0x00000001, 0x2058023d, 0x000002a0, 0x00000000 }, { 0x00000001, 0x2060023d, 0x000002c0, 0x00000000 }, { 0x00000001, 0x2064023d, 0x000002d0, 0x00000000 }, { 0x00000001, 0x205c023d, 0x000002b0, 0x00000000 }, { 0x00200001, 0x233803bd, 0x004500b8, 0x00000000 }, { 0x00200001, 0x231803bd, 0x004500a8, 0x00000000 }, { 0x00200001, 0x22f803bd, 0x00450098, 0x00000000 }, { 0x00000001, 0x2068023d, 0x000002e0, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c1, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000241, 0x00000000 }, { 0x00000001, 0x203003fd, 0x00000000, 0x332bcc77 }, { 0x00000001, 0x214003fd, 0x00000000, 0x3c1d98ad }, { 0x00000001, 0x206c023d, 0x000002f0, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d1, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000251, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000261, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e1, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f1, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000271, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000281, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000301, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000311, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000291, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a1, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000321, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000331, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b1, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00000001, 0x2080023d, 0x00000242, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c2, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000252, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000262, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000272, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000282, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000292, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a2, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x00000001, 0x209c023d, 0x000002b2, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d2, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x2080023d, 0x00000243, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e2, 0x00000000 }, { 0x00000001, 0x2070023d, 0x00000300, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f2, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000253, 0x00000000 }, { 0x00000001, 0x2074023d, 0x00000310, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000263, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000302, 0x00000000 }, { 0x00000001, 0x2078023d, 0x00000320, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000312, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000273, 0x00000000 }, { 0x00000001, 0x207c023d, 0x00000330, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000283, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000322, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x20bc023d, 0x00000332, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000293, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a3, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x209c023d, 0x000002b3, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c3, 0x00000000 }, { 0x00000001, 0x215003fd, 0x00000000, 0x3e525448 }, { 0x00000001, 0x216003fd, 0x00000000, 0x3f11e168 }, { 0x00000001, 0x20a4023d, 0x000002d3, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e3, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f3, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000303, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20b4023d, 0x00000313, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000323, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000244, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000254, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000333, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x2088023d, 0x00000264, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000274, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c4, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d4, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000284, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000294, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e4, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f4, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a4, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b4, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000304, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000314, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x2080023d, 0x00000245, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000324, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000334, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000255, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000265, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x20a0023d, 0x000002c5, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000275, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000285, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d5, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e5, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000295, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a5, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f5, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000305, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b5, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20b4023d, 0x00000315, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000325, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000246, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000256, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000335, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x2088023d, 0x00000266, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000276, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c6, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000286, 0x00000000 }, { 0x00000001, 0x217003fd, 0x00000000, 0x3875735f }, { 0x00000001, 0x20a4023d, 0x000002d6, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e6, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f6, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000306, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000296, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000316, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000326, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a6, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b6, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000336, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x2080023d, 0x00000247, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c7, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d7, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000257, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000267, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e7, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f7, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000277, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000287, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000307, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000317, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000297, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a7, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000327, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000337, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b7, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x20a0023d, 0x000002c8, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000248, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000258, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d8, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e8, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000268, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000278, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f8, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000308, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000288, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000298, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000318, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000328, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a8, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b8, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000338, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x218003a5, 0x00000100, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000104, 0x00000000 }, { 0x00000001, 0x61a000b1, 0x00000180, 0x00000000 }, { 0x00000001, 0x2060023d, 0x000002c1, 0x00000000 }, { 0x00000001, 0x2040023d, 0x00000241, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000242, 0x00000000 }, { 0x00000001, 0x61a800b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000108, 0x00000000 }, { 0x00000001, 0x61b000b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000010c, 0x00000000 }, { 0x00000001, 0x61b800b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000110, 0x00000000 }, { 0x00000001, 0x61c000b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000114, 0x00000000 }, { 0x00000001, 0x61c800b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000118, 0x00000000 }, { 0x00000001, 0x61d000b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000011c, 0x00000000 }, { 0x00000001, 0x61d800b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000120, 0x00000000 }, { 0x00000001, 0x61e000b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000124, 0x00000000 }, { 0x00000001, 0x61e800b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000128, 0x00000000 }, { 0x00000001, 0x61f000b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000012c, 0x00000000 }, { 0x00000001, 0x61f800b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000130, 0x00000000 }, { 0x00000001, 0x2064023d, 0x000002d1, 0x00000000 }, { 0x00000001, 0x2044023d, 0x00000251, 0x00000000 }, { 0x00000001, 0x620000b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000134, 0x00000000 }, { 0x00000001, 0x2048023d, 0x00000261, 0x00000000 }, { 0x00000001, 0x2068023d, 0x000002e1, 0x00000000 }, { 0x00000001, 0x206c023d, 0x000002f1, 0x00000000 }, { 0x00000001, 0x204c023d, 0x00000271, 0x00000000 }, { 0x00000001, 0x620800b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000138, 0x00000000 }, { 0x00000001, 0x2050023d, 0x00000281, 0x00000000 }, { 0x00000001, 0x2070023d, 0x00000301, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000252, 0x00000000 }, { 0x00000001, 0x2074023d, 0x00000311, 0x00000000 }, { 0x00000001, 0x2054023d, 0x00000291, 0x00000000 }, { 0x00000001, 0x621000b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000262, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000013c, 0x00000000 }, { 0x00000001, 0x2058023d, 0x000002a1, 0x00000000 }, { 0x00000001, 0x2078023d, 0x00000321, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000272, 0x00000000 }, { 0x00000001, 0x207c023d, 0x00000331, 0x00000000 }, { 0x00000001, 0x205c023d, 0x000002b1, 0x00000000 }, { 0x00000001, 0x621800b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000282, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c2, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000292, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d2, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e2, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f2, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000302, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000312, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a2, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000322, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000332, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b2, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00000001, 0x2080023d, 0x00000243, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c3, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x2084023d, 0x00000253, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d3, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000263, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000273, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e3, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f3, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000283, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000293, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000303, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000313, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a3, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b3, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000323, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000333, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x2080023d, 0x00000244, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a0023d, 0x000002c4, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000254, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000264, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d4, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e4, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000274, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000284, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f4, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000304, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000294, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a4, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000314, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000324, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b4, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20bc023d, 0x00000334, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x2080023d, 0x00000245, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000255, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c5, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000265, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d5, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000275, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e5, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f5, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000285, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000295, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000305, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000315, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a5, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b5, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000325, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000335, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x2080023d, 0x00000246, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x20a0023d, 0x000002c6, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000256, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000266, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d6, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e6, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000276, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000286, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f6, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000306, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000296, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a6, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000316, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000326, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b6, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20bc023d, 0x00000336, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x2080023d, 0x00000247, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000257, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c7, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d7, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000267, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000277, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e7, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f7, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000287, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000297, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000307, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000317, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a7, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b7, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000327, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000337, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x2080023d, 0x00000248, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c8, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000258, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000268, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000278, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000288, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000298, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a8, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x2080023d, 0x00000249, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000259, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000269, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000279, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000289, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000299, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a9, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d8, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b9, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x20a8023d, 0x000002e8, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f8, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000100, 0x00000000 }, { 0x00000001, 0x61a100b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000308, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000318, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000104, 0x00000000 }, { 0x00000001, 0x61a900b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000328, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000338, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000108, 0x00000000 }, { 0x00000001, 0x61b100b1, 0x00000220, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x20a0023d, 0x000002c9, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000010c, 0x00000000 }, { 0x00000001, 0x61b900b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d9, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e9, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000110, 0x00000000 }, { 0x00000001, 0x61c100b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f9, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000309, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000114, 0x00000000 }, { 0x00000001, 0x61c900b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000319, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000329, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000118, 0x00000000 }, { 0x00000001, 0x61d100b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000339, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x222003a5, 0x0000011c, 0x00000000 }, { 0x00000001, 0x61d900b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000120, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c3, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000243, 0x00000000 }, { 0x00000001, 0x2060023d, 0x000002c2, 0x00000000 }, { 0x00000001, 0x2040023d, 0x00000242, 0x00000000 }, { 0x00000001, 0x61e100b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000124, 0x00000000 }, { 0x00000001, 0x61e900b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000128, 0x00000000 }, { 0x00000001, 0x61f100b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000012c, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d3, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000253, 0x00000000 }, { 0x00000001, 0x61f900b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2064023d, 0x000002d2, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e3, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000263, 0x00000000 }, { 0x00000001, 0x2044023d, 0x00000252, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000130, 0x00000000 }, { 0x00000001, 0x620100b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2048023d, 0x00000262, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000273, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f3, 0x00000000 }, { 0x00000001, 0x2068023d, 0x000002e2, 0x00000000 }, { 0x00000001, 0x206c023d, 0x000002f2, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000303, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000283, 0x00000000 }, { 0x00000001, 0x204c023d, 0x00000272, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000134, 0x00000000 }, { 0x00000001, 0x620900b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2050023d, 0x00000282, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000293, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000313, 0x00000000 }, { 0x00000001, 0x2070023d, 0x00000302, 0x00000000 }, { 0x00000001, 0x2074023d, 0x00000312, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000323, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a3, 0x00000000 }, { 0x00000001, 0x2054023d, 0x00000292, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000138, 0x00000000 }, { 0x00000001, 0x621100b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2058023d, 0x000002a2, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b3, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000333, 0x00000000 }, { 0x00000001, 0x2078023d, 0x00000322, 0x00000000 }, { 0x00000001, 0x207c023d, 0x00000332, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00000001, 0x205c023d, 0x000002b2, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000013c, 0x00000000 }, { 0x00000001, 0x621900b1, 0x00000220, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x2080023d, 0x00000244, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c4, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000254, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d4, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000264, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e4, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f4, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000274, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000284, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000304, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000314, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000294, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a4, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000324, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000334, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b4, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a0023d, 0x000002c5, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000245, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000255, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d5, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e5, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000265, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000275, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f5, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000305, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000285, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000295, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000315, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000325, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a5, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b5, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000335, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x2080023d, 0x00000246, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c6, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d6, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000256, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000266, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e6, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f6, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000276, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000286, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000306, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000316, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000296, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a6, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000326, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000336, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b6, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x2080023d, 0x00000247, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x2084023d, 0x00000257, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c7, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000267, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000277, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d7, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e7, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000287, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000297, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f7, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000307, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a7, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b7, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000317, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000327, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x2080023d, 0x00000248, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000337, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x2084023d, 0x00000258, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000268, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c8, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d8, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000278, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000288, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e8, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f8, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000298, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a8, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000308, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000318, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x20b8023d, 0x00000328, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000338, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000249, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000259, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a0023d, 0x000002c9, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000269, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000279, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d9, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e9, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000289, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000299, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f9, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000309, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a9, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b9, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000319, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000329, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x20bc023d, 0x00000339, 0x00000000 }, { 0x00000001, 0x2080023d, 0x0000024a, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x20a0023d, 0x000002ca, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025a, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026a, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002da, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ea, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027a, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028a, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fa, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030a, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029a, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002aa, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031a, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032a, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002ba, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x20bc023d, 0x0000033a, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x222003a5, 0x00000100, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000104, 0x00000000 }, { 0x00000001, 0x41a20231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000108, 0x00000000 }, { 0x00000001, 0x41aa0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000010c, 0x00000000 }, { 0x00000001, 0x41b20231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000110, 0x00000000 }, { 0x00000001, 0x41ba0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000114, 0x00000000 }, { 0x00000001, 0x41c20231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000118, 0x00000000 }, { 0x00000001, 0x41ca0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000011c, 0x00000000 }, { 0x00000001, 0x41d20231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000120, 0x00000000 }, { 0x00000001, 0x41da0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000124, 0x00000000 }, { 0x00000001, 0x41e20231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x41ea0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000128, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c4, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000244, 0x00000000 }, { 0x00000001, 0x2040023d, 0x00000243, 0x00000000 }, { 0x00000001, 0x2060023d, 0x000002c3, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000012c, 0x00000000 }, { 0x00000001, 0x41f20231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d4, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000254, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000130, 0x00000000 }, { 0x00000001, 0x41fa0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x2044023d, 0x00000253, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e4, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000264, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2048023d, 0x00000263, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f4, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000274, 0x00000000 }, { 0x00000001, 0x2064023d, 0x000002d3, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000134, 0x00000000 }, { 0x00000001, 0x42020231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2068023d, 0x000002e3, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000284, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000304, 0x00000000 }, { 0x00000001, 0x204c023d, 0x00000273, 0x00000000 }, { 0x00000001, 0x2050023d, 0x00000283, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000314, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000294, 0x00000000 }, { 0x00000001, 0x206c023d, 0x000002f3, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000138, 0x00000000 }, { 0x00000001, 0x420a0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2070023d, 0x00000303, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a4, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000324, 0x00000000 }, { 0x00000001, 0x2054023d, 0x00000293, 0x00000000 }, { 0x00000001, 0x2058023d, 0x000002a3, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000334, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b4, 0x00000000 }, { 0x00000001, 0x2074023d, 0x00000313, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000013c, 0x00000000 }, { 0x00000001, 0x42120231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2078023d, 0x00000323, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00000001, 0x205c023d, 0x000002b3, 0x00000000 }, { 0x00000001, 0x207c023d, 0x00000333, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x00000001, 0x421a0231, 0x00000024, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x2080023d, 0x00000245, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c5, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000255, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d5, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000265, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000275, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e5, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f5, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000285, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000295, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000305, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000315, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a5, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b5, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000325, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000335, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x2080023d, 0x00000246, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a0023d, 0x000002c6, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000256, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000266, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d6, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e6, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000276, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000286, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f6, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000306, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000296, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a6, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000316, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000326, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b6, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20bc023d, 0x00000336, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x2080023d, 0x00000247, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000257, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c7, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d7, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000267, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000277, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e7, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f7, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000287, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000297, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000307, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000317, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a7, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b7, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000327, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000337, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x2080023d, 0x00000248, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000258, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000268, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c8, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000278, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000288, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d8, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e8, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000298, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a8, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f8, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000308, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20b4023d, 0x00000318, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000328, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000249, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000259, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000338, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x2088023d, 0x00000269, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000279, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c9, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d9, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000289, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000299, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e9, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f9, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a9, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b9, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000309, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000319, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x2080023d, 0x0000024a, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000329, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000339, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025a, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026a, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a0023d, 0x000002ca, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027a, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028a, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002da, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ea, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029a, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002aa, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fa, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030a, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002ba, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031a, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032a, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x20bc023d, 0x0000033a, 0x00000000 }, { 0x00000001, 0x2080023d, 0x0000024b, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x20a0023d, 0x000002cb, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025b, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026b, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002db, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002eb, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027b, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028b, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fb, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030b, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029b, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002ab, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031b, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032b, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002bb, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x20bc023d, 0x0000033b, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x222003a5, 0x00000100, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000104, 0x00000000 }, { 0x00000001, 0x41a30231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000108, 0x00000000 }, { 0x00000001, 0x41ab0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000010c, 0x00000000 }, { 0x00000001, 0x41b30231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000110, 0x00000000 }, { 0x00000001, 0x41bb0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000114, 0x00000000 }, { 0x00000001, 0x41c30231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000118, 0x00000000 }, { 0x00000001, 0x41cb0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000011c, 0x00000000 }, { 0x00000001, 0x41d30231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000120, 0x00000000 }, { 0x00000001, 0x41db0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000124, 0x00000000 }, { 0x00000001, 0x41e30231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x41eb0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000128, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c5, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000245, 0x00000000 }, { 0x00000001, 0x2060023d, 0x000002c4, 0x00000000 }, { 0x00000001, 0x2040023d, 0x00000244, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000012c, 0x00000000 }, { 0x00000001, 0x41f30231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000130, 0x00000000 }, { 0x00000001, 0x41fb0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d5, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000255, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e5, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000265, 0x00000000 }, { 0x00000001, 0x2064023d, 0x000002d4, 0x00000000 }, { 0x00000001, 0x2044023d, 0x00000254, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000134, 0x00000000 }, { 0x00000001, 0x42030231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2048023d, 0x00000264, 0x00000000 }, { 0x00000001, 0x2068023d, 0x000002e4, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000275, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f5, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000305, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000285, 0x00000000 }, { 0x00000001, 0x206c023d, 0x000002f4, 0x00000000 }, { 0x00000001, 0x204c023d, 0x00000274, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000138, 0x00000000 }, { 0x00000001, 0x420b0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2050023d, 0x00000284, 0x00000000 }, { 0x00000001, 0x2070023d, 0x00000304, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000295, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000315, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000325, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a5, 0x00000000 }, { 0x00000001, 0x2074023d, 0x00000314, 0x00000000 }, { 0x00000001, 0x2054023d, 0x00000294, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000013c, 0x00000000 }, { 0x00000001, 0x42130231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2058023d, 0x000002a4, 0x00000000 }, { 0x00000001, 0x2078023d, 0x00000324, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b5, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000335, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00000001, 0x207c023d, 0x00000334, 0x00000000 }, { 0x00000001, 0x205c023d, 0x000002b4, 0x00000000 }, { 0x00000001, 0x421b0231, 0x00000024, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x00000001, 0x2080023d, 0x00000246, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c6, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x2084023d, 0x00000256, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000266, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d6, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000276, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000286, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e6, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f6, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000296, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a6, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000306, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000316, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b6, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x20b8023d, 0x00000326, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000336, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000247, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000257, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a0023d, 0x000002c7, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000267, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000277, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d7, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e7, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000287, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000297, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f7, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000307, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a7, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b7, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000317, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000327, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x2080023d, 0x00000248, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000337, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x2084023d, 0x00000258, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000268, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c8, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d8, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000278, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000288, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e8, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f8, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000298, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a8, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000308, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000318, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b8, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000328, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x20bc023d, 0x00000338, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000249, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000259, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000269, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x208c023d, 0x00000279, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000289, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c9, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d9, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000299, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a9, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e9, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f9, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b9, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20b0023d, 0x00000309, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000319, 0x00000000 }, { 0x00000001, 0x2080023d, 0x0000024a, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025a, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000329, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000339, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026a, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027a, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x20a0023d, 0x000002ca, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028a, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029a, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002da, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ea, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002aa, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002ba, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fa, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030a, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x2080023d, 0x0000024b, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031a, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032a, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025b, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026b, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033a, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x208c023d, 0x0000027b, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028b, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002cb, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002db, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029b, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002ab, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002eb, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fb, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002bb, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030b, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x20b4023d, 0x0000031b, 0x00000000 }, { 0x00000001, 0x2080023d, 0x0000024c, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025c, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026c, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027c, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028c, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029c, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002ac, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002bc, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x222003a5, 0x00000100, 0x00000000 }, { 0x00000001, 0x61a400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000104, 0x00000000 }, { 0x00000001, 0x61ac00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032b, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000108, 0x00000000 }, { 0x00000001, 0x61b400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033b, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x222003a5, 0x0000010c, 0x00000000 }, { 0x00000001, 0x61bc00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002cc, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002dc, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000110, 0x00000000 }, { 0x00000001, 0x61c400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ec, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fc, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000114, 0x00000000 }, { 0x00000001, 0x61cc00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030c, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031c, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000118, 0x00000000 }, { 0x00000001, 0x61d400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032c, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033c, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000011c, 0x00000000 }, { 0x00000001, 0x61dc00b1, 0x00000220, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x222003a5, 0x00000120, 0x00000000 }, { 0x00000001, 0x61e400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000124, 0x00000000 }, { 0x00000001, 0x61ec00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000128, 0x00000000 }, { 0x00000001, 0x61f400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000012c, 0x00000000 }, { 0x00000001, 0x61fc00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000130, 0x00000000 }, { 0x00000001, 0x620400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000134, 0x00000000 }, { 0x00000001, 0x620c00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000138, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c6, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000246, 0x00000000 }, { 0x00000001, 0x2060023d, 0x000002c5, 0x00000000 }, { 0x00000001, 0x2040023d, 0x00000245, 0x00000000 }, { 0x00000001, 0x621400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d6, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000256, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000266, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e6, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f6, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000276, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000286, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000306, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000316, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000296, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a6, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000326, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000336, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b6, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00000001, 0x2064023d, 0x000002d5, 0x00000000 }, { 0x00000001, 0x2044023d, 0x00000255, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000247, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c7, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000257, 0x00000000 }, { 0x00000001, 0x2048023d, 0x00000265, 0x00000000 }, { 0x00000001, 0x2068023d, 0x000002e5, 0x00000000 }, { 0x00000001, 0x206c023d, 0x000002f5, 0x00000000 }, { 0x00000001, 0x204c023d, 0x00000275, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000267, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000277, 0x00000000 }, { 0x00000001, 0x2050023d, 0x00000285, 0x00000000 }, { 0x00000001, 0x2070023d, 0x00000305, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d7, 0x00000000 }, { 0x00000001, 0x2074023d, 0x00000315, 0x00000000 }, { 0x00000001, 0x2054023d, 0x00000295, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000287, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e7, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000297, 0x00000000 }, { 0x00000001, 0x2058023d, 0x000002a5, 0x00000000 }, { 0x00000001, 0x2078023d, 0x00000325, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f7, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000013c, 0x00000000 }, { 0x00000001, 0x207c023d, 0x00000335, 0x00000000 }, { 0x00000001, 0x205c023d, 0x000002b5, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a7, 0x00000000 }, { 0x00000001, 0x621c00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000307, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b7, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x20b4023d, 0x00000317, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x20b8023d, 0x00000327, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000248, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000258, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000268, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000337, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000278, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000288, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a0023d, 0x000002c8, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000298, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a8, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d8, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e8, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20ac023d, 0x000002f8, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000308, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000249, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000259, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000318, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000328, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000269, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000279, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000338, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x2090023d, 0x00000289, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000299, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c9, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d9, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a9, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b9, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e9, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f9, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x2080023d, 0x0000024a, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000309, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000319, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025a, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026a, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000329, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000339, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027a, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028a, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x20a0023d, 0x000002ca, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029a, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002aa, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002da, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ea, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002ba, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fa, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20b0023d, 0x0000030a, 0x00000000 }, { 0x00000001, 0x2080023d, 0x0000024b, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025b, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026b, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031a, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027b, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028b, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032a, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033a, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029b, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002ab, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x20a0023d, 0x000002cb, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002bb, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x20a4023d, 0x000002db, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002eb, 0x00000000 }, { 0x00000001, 0x2080023d, 0x0000024c, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025c, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fb, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030b, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026c, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027c, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031b, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032b, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028c, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029c, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033b, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x2098023d, 0x000002ac, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002bc, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002cc, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002dc, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x2080023d, 0x0000024d, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ec, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fc, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025d, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026d, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030c, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031c, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027d, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028d, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032c, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033c, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029d, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002ad, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x20a0023d, 0x000002cd, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002bd, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002dd, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x20a8023d, 0x000002ed, 0x00000000 }, { 0x00000001, 0x2040023d, 0x00000246, 0x00000000 }, { 0x00000001, 0x2060023d, 0x000002c6, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000100, 0x00000000 }, { 0x00000001, 0x61a500b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000104, 0x00000000 }, { 0x00000001, 0x61ad00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000108, 0x00000000 }, { 0x00000001, 0x61b500b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000010c, 0x00000000 }, { 0x00000001, 0x61bd00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000110, 0x00000000 }, { 0x00000001, 0x61c500b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fd, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000114, 0x00000000 }, { 0x00000001, 0x61cd00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030d, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031d, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000118, 0x00000000 }, { 0x00000001, 0x61d500b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032d, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033d, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000011c, 0x00000000 }, { 0x00000001, 0x61dd00b1, 0x00000220, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x222003a5, 0x00000120, 0x00000000 }, { 0x00000001, 0x61e500b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000124, 0x00000000 }, { 0x00000001, 0x61ed00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000128, 0x00000000 }, { 0x00000001, 0x61f500b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000012c, 0x00000000 }, { 0x00000001, 0x61fd00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000130, 0x00000000 }, { 0x00000001, 0x2044023d, 0x00000256, 0x00000000 }, { 0x00000001, 0x620500b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000134, 0x00000000 }, { 0x00000001, 0x2048023d, 0x00000266, 0x00000000 }, { 0x00000001, 0x204c023d, 0x00000276, 0x00000000 }, { 0x00000001, 0x620d00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000138, 0x00000000 }, { 0x00000001, 0x2050023d, 0x00000286, 0x00000000 }, { 0x00000001, 0x2054023d, 0x00000296, 0x00000000 }, { 0x00000001, 0x621500b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2064023d, 0x000002d6, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000013c, 0x00000000 }, { 0x00000001, 0x2058023d, 0x000002a6, 0x00000000 }, { 0x00000001, 0x2068023d, 0x000002e6, 0x00000000 }, { 0x00000001, 0x205c023d, 0x000002b6, 0x00000000 }, { 0x00000001, 0x621d00b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x206c023d, 0x000002f6, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c7, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000247, 0x00000000 }, { 0x00000001, 0x2070023d, 0x00000306, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d7, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000257, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000267, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e7, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f7, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000277, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000287, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000307, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000317, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000297, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a7, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000327, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000337, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b7, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00000001, 0x2080023d, 0x00000248, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x00000001, 0x2084023d, 0x00000258, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000268, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000278, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000288, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000298, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a8, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d8, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b8, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x2080023d, 0x00000249, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f8, 0x00000000 }, { 0x00000001, 0x2074023d, 0x00000316, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000308, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000259, 0x00000000 }, { 0x00000001, 0x2078023d, 0x00000326, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000269, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000318, 0x00000000 }, { 0x00000001, 0x207c023d, 0x00000336, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000328, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000279, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x2090023d, 0x00000289, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000338, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x2094023d, 0x00000299, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a9, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c9, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d9, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b9, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e9, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20ac023d, 0x000002f9, 0x00000000 }, { 0x00000001, 0x2080023d, 0x0000024a, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025a, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026a, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000309, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027a, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028a, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000319, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000329, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029a, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002aa, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000339, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x209c023d, 0x000002ba, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x20a0023d, 0x000002ca, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002da, 0x00000000 }, { 0x00000001, 0x2080023d, 0x0000024b, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025b, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ea, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fa, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026b, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027b, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030a, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031a, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028b, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029b, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032a, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033a, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002ab, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002bb, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x20a0023d, 0x000002cb, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x2080023d, 0x0000024c, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002db, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002eb, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025c, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026c, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fb, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030b, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027c, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028c, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031b, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032b, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029c, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002ac, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033b, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x209c023d, 0x000002bc, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002cc, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002dc, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x20a8023d, 0x000002ec, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fc, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030c, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031c, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032c, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033c, 0x00000000 }, { 0x00000001, 0x2080023d, 0x0000024d, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a0023d, 0x000002cd, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025d, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026d, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002dd, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ed, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027d, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028d, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fd, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030d, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029d, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002ad, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031d, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032d, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002bd, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x20bc023d, 0x0000033d, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x2080023d, 0x0000024e, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025e, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002ce, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002de, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026e, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027e, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ee, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fe, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028e, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029e, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030e, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031e, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002ae, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002be, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032e, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033e, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x222003a5, 0x00000100, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000104, 0x00000000 }, { 0x00000001, 0x41a60231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x41ae0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000108, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2040023d, 0x00000247, 0x00000000 }, { 0x00000001, 0x2060023d, 0x000002c7, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000010c, 0x00000000 }, { 0x00000001, 0x41b60231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000110, 0x00000000 }, { 0x00000001, 0x41be0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000114, 0x00000000 }, { 0x00000001, 0x41c60231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000118, 0x00000000 }, { 0x00000001, 0x41ce0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000011c, 0x00000000 }, { 0x00000001, 0x41d60231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000120, 0x00000000 }, { 0x00000001, 0x41de0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000124, 0x00000000 }, { 0x00000001, 0x41e60231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000128, 0x00000000 }, { 0x00000001, 0x41ee0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000012c, 0x00000000 }, { 0x00000001, 0x41f60231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000130, 0x00000000 }, { 0x00000001, 0x41fe0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2044023d, 0x00000257, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000134, 0x00000000 }, { 0x00000001, 0x42060231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2048023d, 0x00000267, 0x00000000 }, { 0x00000001, 0x204c023d, 0x00000277, 0x00000000 }, { 0x00000001, 0x222003a5, 0x00000138, 0x00000000 }, { 0x00000001, 0x420e0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2050023d, 0x00000287, 0x00000000 }, { 0x00000001, 0x2054023d, 0x00000297, 0x00000000 }, { 0x00000001, 0x222003a5, 0x0000013c, 0x00000000 }, { 0x00000001, 0x42160231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000220, 0x00000000 }, { 0x00000001, 0x2058023d, 0x000002a7, 0x00000000 }, { 0x00000001, 0x2064023d, 0x000002d7, 0x00000000 }, { 0x00000001, 0x205c023d, 0x000002b7, 0x00000000 }, { 0x00000001, 0x421e0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x2068023d, 0x000002e7, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c8, 0x00000000 }, { 0x00000001, 0x2080023d, 0x00000248, 0x00000000 }, { 0x00000001, 0x206c023d, 0x000002f7, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d8, 0x00000000 }, { 0x00000001, 0x2084023d, 0x00000258, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000268, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e8, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f8, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000278, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000288, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000308, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000318, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000298, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a8, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000328, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x00000338, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b8, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00000001, 0x2080023d, 0x00000249, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002c9, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x00000001, 0x2084023d, 0x00000259, 0x00000000 }, { 0x00000001, 0x2088023d, 0x00000269, 0x00000000 }, { 0x00000001, 0x208c023d, 0x00000279, 0x00000000 }, { 0x00000001, 0x2090023d, 0x00000289, 0x00000000 }, { 0x00000001, 0x2094023d, 0x00000299, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002a9, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002b9, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002d9, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x2080023d, 0x0000024a, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002e9, 0x00000000 }, { 0x00000001, 0x2070023d, 0x00000307, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002f9, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025a, 0x00000000 }, { 0x00000001, 0x2074023d, 0x00000317, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026a, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x00000309, 0x00000000 }, { 0x00000001, 0x2078023d, 0x00000327, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x00000319, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027a, 0x00000000 }, { 0x00000001, 0x207c023d, 0x00000337, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028a, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x00000329, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x20bc023d, 0x00000339, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029a, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002aa, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a0023d, 0x000002ca, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002ba, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002da, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20a8023d, 0x000002ea, 0x00000000 }, { 0x00000001, 0x2080023d, 0x0000024b, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fa, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025b, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026b, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030a, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031a, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027b, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028b, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032a, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033a, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029b, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002ab, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x20a0023d, 0x000002cb, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002bb, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x20a4023d, 0x000002db, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002eb, 0x00000000 }, { 0x00000001, 0x2080023d, 0x0000024c, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025c, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fb, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030b, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026c, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027c, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031b, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032b, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028c, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029c, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033b, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x2098023d, 0x000002ac, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002bc, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002cc, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002dc, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x2080023d, 0x0000024d, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ec, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fc, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025d, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026d, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030c, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031c, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027d, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028d, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032c, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033c, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029d, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002ad, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x209c023d, 0x000002bd, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002cd, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x20a4023d, 0x000002dd, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ed, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fd, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030d, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031d, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032d, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033d, 0x00000000 }, { 0x00000001, 0x2080023d, 0x0000024e, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a0023d, 0x000002ce, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025e, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026e, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002de, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ee, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027e, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028e, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002fe, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030e, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029e, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002ae, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031e, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032e, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002be, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x20bc023d, 0x0000033e, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x2080023d, 0x0000024f, 0x00000000 }, { 0x00000001, 0x2084023d, 0x0000025f, 0x00000000 }, { 0x00000001, 0x20a0023d, 0x000002cf, 0x00000000 }, { 0x00000001, 0x20a4023d, 0x000002df, 0x00000000 }, { 0x00000001, 0x2088023d, 0x0000026f, 0x00000000 }, { 0x00000001, 0x208c023d, 0x0000027f, 0x00000000 }, { 0x00000001, 0x20a8023d, 0x000002ef, 0x00000000 }, { 0x00000001, 0x20ac023d, 0x000002ff, 0x00000000 }, { 0x00000001, 0x2090023d, 0x0000028f, 0x00000000 }, { 0x00000001, 0x2094023d, 0x0000029f, 0x00000000 }, { 0x00000001, 0x20b0023d, 0x0000030f, 0x00000000 }, { 0x00000001, 0x20b4023d, 0x0000031f, 0x00000000 }, { 0x00000001, 0x2098023d, 0x000002af, 0x00000000 }, { 0x00000001, 0x209c023d, 0x000002bf, 0x00000000 }, { 0x00000001, 0x20b8023d, 0x0000032f, 0x00000000 }, { 0x00000001, 0x20bc023d, 0x0000033f, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x204003a5, 0x00000100, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x00000104, 0x00000000 }, { 0x00000001, 0x41a70231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x41af0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x204003a5, 0x00000108, 0x00000000 }, { 0x00600001, 0x218003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000344, 0x0a0a8000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x0000010c, 0x00000000 }, { 0x00000001, 0x41b70231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x00000110, 0x00000000 }, { 0x00000001, 0x41bf0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x00000114, 0x00000000 }, { 0x00000001, 0x41c70231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x00000118, 0x00000000 }, { 0x00000001, 0x41cf0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x0000011c, 0x00000000 }, { 0x00000001, 0x41d70231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x00000120, 0x00000000 }, { 0x00000001, 0x41df0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x00000124, 0x00000000 }, { 0x00000001, 0x41e70231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x00000128, 0x00000000 }, { 0x00000001, 0x41ef0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x0000012c, 0x00000000 }, { 0x00000001, 0x41f70231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x00000130, 0x00000000 }, { 0x00000001, 0x41ff0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x00000134, 0x00000000 }, { 0x00000001, 0x42070231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x00000138, 0x00000000 }, { 0x00000001, 0x420f0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x204003a5, 0x0000013c, 0x00000000 }, { 0x00000001, 0x42170231, 0x00000024, 0x00000000 }, { 0x00000001, 0x21880061, 0x00000000, 0x000f0007 }, { 0x00000001, 0x602400b1, 0x00000040, 0x00000000 }, { 0x00000001, 0x218003bd, 0x0000002c, 0x00000000 }, { 0x00000001, 0x421f0231, 0x00000024, 0x00000000 }, { 0x00000001, 0x218403bd, 0x00000028, 0x00000000 }, { 0x0c600031, 0x200003a0, 0x00000180, 0x00000200 }, { 0x00000040, 0x202c2c21, 0x0000002c, 0x00080008 }, { 0x00000040, 0x20243c21, 0x00000020, 0xfffcfffc }, { 0x05000010, 0x20000420, 0x0000002c, 0x00000024 }, { 0x00010220, 0x34001c00, 0x00001400, 0xffff9830 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000340, 0x02290000 }, { 0x00000001, 0x20480061, 0x00000000, 0x000f0003 }, { 0x00000001, 0x20400161, 0x00000000, 0x00000000 }, { 0x00000001, 0x204403bd, 0x00000028, 0x00000000 }, { 0x0c600031, 0x204003a1, 0x00000040, 0x00000200 }, { 0x00800001, 0x206003bd, 0x008d0040, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000344, 0x060a8000 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000001, 0x20480061, 0x00000000, 0x000f0003 }, { 0x00000001, 0x20400161, 0x00000000, 0x00000000 }, { 0x00000001, 0x204403bd, 0x00000028, 0x00000000 }, { 0x0c600031, 0x200003a0, 0x00000040, 0x00000200 }, { 0x00000040, 0x20243c21, 0x00000020, 0xfffcfffc }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000340, 0x02290000 }, { 0x00000001, 0x20480061, 0x00000000, 0x000f0003 }, { 0x00000001, 0x204003bd, 0x00000024, 0x00000000 }, { 0x00000001, 0x204403bd, 0x00000028, 0x00000000 }, { 0x0c600031, 0x204003a1, 0x00000040, 0x00000200 }, { 0x00800001, 0x206003bd, 0x008d0040, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000344, 0x060a8000 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000001, 0x20480061, 0x00000000, 0x000f0003 }, { 0x00000001, 0x204003bd, 0x00000024, 0x00000000 }, { 0x00000001, 0x204403bd, 0x00000028, 0x00000000 }, { 0x0c600031, 0x200003a0, 0x00000040, 0x00000200 }, { 0x00600001, 0x2e0003bd, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20000fa0, 0x00000e00, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen75/sharpening_unmask.g75b000066400000000000000000000214621231401140700267050ustar00rootroot00000000000000{ 0x00000001, 0x21280161, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c0161, 0x00000000, 0x00000000 }, { 0x00000001, 0x21480161, 0x00000000, 0x00050005 }, { 0x00000001, 0x21680161, 0x00000000, 0x00040004 }, { 0x00000001, 0x21880161, 0x00000000, 0x00020002 }, { 0x00000001, 0x21080161, 0x00000000, 0x00010001 }, { 0x06000010, 0x20002c20, 0x04000020, 0x00000000 }, { 0x00010220, 0x34001c00, 0x04001400, 0x00000530 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000128, 0x02190000 }, { 0x06000010, 0x20002c20, 0x02000030, 0x00000000 }, { 0x00000001, 0x20480061, 0x00000000, 0x00030003 }, { 0x00000001, 0x204003bd, 0x0000002c, 0x00000000 }, { 0x00000001, 0x204403bd, 0x00000028, 0x00000000 }, { 0x0c600031, 0x206003a1, 0x00000040, 0x00000200 }, { 0x00000040, 0x22000c20, 0x00000188, 0x02190000 }, { 0x00400001, 0x21a003bd, 0x00690060, 0x00000000 }, { 0x0c600031, 0x204003a1, 0x00000040, 0x00000200 }, { 0x00400001, 0x21c003bd, 0x00690040, 0x00000000 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00000150 }, { 0x00000001, 0x218201ed, 0x00000000, 0x00800080 }, { 0x00400001, 0x217003bd, 0x006901a0, 0x00000000 }, { 0x00400001, 0x215003bd, 0x006901c0, 0x00000000 }, { 0x0020002c, 0x21601c01, 0x00490000, 0x00000460 }, { 0x00000001, 0x210c01ed, 0x00000000, 0x00800080 }, { 0x00400001, 0x217003bd, 0x006901a0, 0x00000000 }, { 0x00400001, 0x215003bd, 0x00690150, 0x00000000 }, { 0x0020002c, 0x21201c01, 0x00490000, 0x00000500 }, { 0x00400001, 0x217003bd, 0x00690150, 0x00000000 }, { 0x00000001, 0x218001ed, 0x00000000, 0x00800080 }, { 0x00400001, 0x215003bd, 0x00690150, 0x00000000 }, { 0x0020002c, 0x21001c01, 0x00490000, 0x00000570 }, { 0x00000001, 0x218001ed, 0x00000000, 0x00800080 }, { 0x0020002c, 0x21001c01, 0x00490000, 0x00000550 }, { 0x00000001, 0x4180002d, 0x00000030, 0x00000000 }, { 0x00400001, 0x217003bd, 0x00690150, 0x00000000 }, { 0x00000001, 0x202401ad, 0x00000180, 0x00000000 }, { 0x00400001, 0x215003bd, 0x006901a0, 0x00000000 }, { 0x0020002c, 0x21001c01, 0x00490000, 0x00000500 }, { 0x00400001, 0x219003bd, 0x00690150, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00400001, 0x219003bd, 0x006901a0, 0x00000000 }, { 0x01000010, 0x20002c20, 0x00000034, 0x00000000 }, { 0x00010220, 0x34001c00, 0x00001400, 0x00000160 }, { 0x00000001, 0x210e01ed, 0x00000000, 0x00800080 }, { 0x00400001, 0x217003bd, 0x006901a0, 0x00000000 }, { 0x00400001, 0x215003bd, 0x006901c0, 0x00000000 }, { 0x0020002c, 0x21801c01, 0x00490000, 0x000005e0 }, { 0x00000001, 0x210c01ed, 0x00000000, 0x00800080 }, { 0x00400001, 0x217003bd, 0x006901a0, 0x00000000 }, { 0x00400001, 0x215003bd, 0x00690150, 0x00000000 }, { 0x0020002c, 0x21201c01, 0x00490000, 0x00000380 }, { 0x00600040, 0x41503e31, 0x00ae4150, 0x00ff00ff }, { 0x00000001, 0x211001ed, 0x00000000, 0x00800080 }, { 0x00600040, 0x41513e31, 0x00ae4151, 0x00ff00ff }, { 0x00400001, 0x217003bd, 0x00690150, 0x00000000 }, { 0x0020002c, 0x21401c01, 0x00490000, 0x00000630 }, { 0x00000001, 0x211001ed, 0x00000000, 0x00800080 }, { 0x0020002c, 0x21401c01, 0x00490000, 0x00000610 }, { 0x00000001, 0x4110002d, 0x00000034, 0x00000000 }, { 0x00400001, 0x217003bd, 0x00690150, 0x00000000 }, { 0x00000001, 0x202401ad, 0x00000110, 0x00000000 }, { 0x00400001, 0x215003bd, 0x00690190, 0x00000000 }, { 0x0020002c, 0x21401c01, 0x00490000, 0x000005c0 }, { 0x00400001, 0x21e003bd, 0x00690150, 0x00000000 }, { 0x00000220, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00400001, 0x21e003bd, 0x00690190, 0x00000000 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000168, 0x040a8000 }, { 0x00400001, 0x206003bd, 0x006901e0, 0x00000000 }, { 0x00000001, 0x20480061, 0x00000000, 0x00030003 }, { 0x00000001, 0x204003bd, 0x0000002c, 0x00000000 }, { 0x00000001, 0x204403bd, 0x00000028, 0x00000000 }, { 0x0c600031, 0x200003a0, 0x00000040, 0x00000200 }, { 0x0000000c, 0x20242c21, 0x00000028, 0x00010001 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000108, 0x02190000 }, { 0x00000001, 0x20480061, 0x00000000, 0x00010003 }, { 0x00000001, 0x204003bd, 0x0000002c, 0x00000000 }, { 0x00000001, 0x204403bd, 0x00000024, 0x00000000 }, { 0x0c600031, 0x204003a1, 0x00000040, 0x00000200 }, { 0x00200001, 0x206003bd, 0x00450040, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000148, 0x040a8000 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000001, 0x20480061, 0x00000000, 0x00010003 }, { 0x00000001, 0x204003bd, 0x0000002c, 0x00000000 }, { 0x00000001, 0x204403bd, 0x00000024, 0x00000000 }, { 0x0c600031, 0x200003a0, 0x00000040, 0x00000200 }, { 0x00000040, 0x202c2c21, 0x0000002c, 0x00040004 }, { 0x05000010, 0x20000420, 0x0600002c, 0x00000020 }, { 0x00010220, 0x34001c00, 0x06001400, 0xfffffad0 }, { 0x00600001, 0x2e0003bd, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20000fa0, 0x00000e00, 0x82000010 }, { 0x00000040, 0x20243da5, 0x00004182, 0x00800080 }, { 0x00600041, 0x20c03625, 0x008d0178, 0x00000182 }, { 0x00600041, 0x20803625, 0x008d0170, 0x00000182 }, { 0x05600010, 0x2000462c, 0x00ae0170, 0x00ae0150 }, { 0x00600041, 0x206044a5, 0x00000024, 0x008d0158 }, { 0x00600041, 0x204044a5, 0x00000024, 0x008d0150 }, { 0x00600040, 0x20a014a5, 0x008d00c0, 0x008d0060 }, { 0x00600040, 0x208014a5, 0x008d0080, 0x008d0040 }, { 0x0080000c, 0x40403cad, 0x008d0080, 0x00070007 }, { 0x05601010, 0x2000462c, 0x00ae0171, 0x00ae0151 }, { 0x00800001, 0x204001ad, 0x00ae0040, 0x00000000 }, { 0x00610001, 0x415001b1, 0x00ae0040, 0x00000000 }, { 0x00611001, 0x415101b1, 0x00ae0042, 0x00000000 }, { 0x0020002d, 0x20000024, 0x00450160, 0x00000000 }, { 0x00800040, 0x2040462d, 0x00b10150, 0x00b14170 }, { 0x00000040, 0x20243da5, 0x0000410c, 0x00800080 }, { 0x05800010, 0x20003dac, 0x04b10040, 0x00000000 }, { 0x00810001, 0x204001ad, 0x04b14040, 0x00000000 }, { 0x00600041, 0x208044a5, 0x00000024, 0x008d0158 }, { 0x00600041, 0x206044a5, 0x00000024, 0x008d0150 }, { 0x00800041, 0x20a035a5, 0x008d0040, 0x0000010c }, { 0x00800040, 0x204014a5, 0x008d00a0, 0x008d0060 }, { 0x0080000c, 0x60403cb1, 0x008d0040, 0x00070007 }, { 0x00800001, 0x21500231, 0x00cf0040, 0x00000000 }, { 0x0020002d, 0x20000024, 0x00450120, 0x00000000 }, { 0x00600040, 0x20803e25, 0x008d4170, 0x00ff00ff }, { 0x00600040, 0x20403e25, 0x008d4150, 0x00ff00ff }, { 0x00600040, 0x20a03e25, 0x008d4178, 0x00ff00ff }, { 0x00600040, 0x20603e25, 0x008d4158, 0x00ff00ff }, { 0x00000040, 0x20243da5, 0x00004180, 0x00800080 }, { 0x10600041, 0x240014a4, 0x008d0040, 0x008d0080 }, { 0x10600049, 0x200014a4, 0x008d0040, 0x008d0080 }, { 0x00600001, 0x20c00085, 0x008d0400, 0x00000000 }, { 0x10600041, 0x240014a4, 0x008d0060, 0x008d00a0 }, { 0x10600049, 0x200014a4, 0x008d0060, 0x008d00a0 }, { 0x00600001, 0x20e00085, 0x008d0400, 0x00000000 }, { 0x00000001, 0x204001e5, 0x00000000, 0x00ff00ff }, { 0x0c600038, 0x208014a5, 0x008d00e0, 0x00000040 }, { 0x0c600038, 0x206014a5, 0x008d00c0, 0x00000040 }, { 0x00800040, 0x40403cad, 0x008d4060, 0x00ff00ff }, { 0x00800001, 0x204001ad, 0x00ae0040, 0x00000000 }, { 0x00600041, 0x208044a5, 0x00000024, 0x008d0158 }, { 0x00800041, 0x20a035a5, 0x008d0040, 0x00000180 }, { 0x00600041, 0x206044a5, 0x00000024, 0x008d0150 }, { 0x00800040, 0x204014a5, 0x008d00a0, 0x008d0060 }, { 0x0080000c, 0x60403cb1, 0x008d0040, 0x00070007 }, { 0x00800001, 0x21500231, 0x00cf0040, 0x00000000 }, { 0x0020002d, 0x20000024, 0x00450100, 0x00000000 }, { 0x00000040, 0x20243da5, 0x0000410e, 0x00800080 }, { 0x00600041, 0x20c03625, 0x008d0178, 0x0000010e }, { 0x00600041, 0x20803625, 0x008d0170, 0x0000010e }, { 0x03600010, 0x2000462c, 0x02ae0170, 0x00ae0150 }, { 0x00600041, 0x206044a5, 0x00000024, 0x008d0158 }, { 0x00600041, 0x204044a5, 0x00000024, 0x008d0150 }, { 0x00600040, 0x20a014a5, 0x008d00c0, 0x008d0060 }, { 0x00600040, 0x208014a5, 0x008d0080, 0x008d0040 }, { 0x0080000c, 0x40403cad, 0x008d0080, 0x00070007 }, { 0x03601010, 0x2000462c, 0x02ae0171, 0x00ae0151 }, { 0x00800001, 0x204001ad, 0x00ae0040, 0x00000000 }, { 0x00610001, 0x415001b1, 0x02ae0040, 0x00000000 }, { 0x00611001, 0x415101b1, 0x02ae0042, 0x00000000 }, { 0x0020002d, 0x20000024, 0x00450180, 0x00000000 }, { 0x00000001, 0x208001e5, 0x00000000, 0x00ff00ff }, { 0x00600041, 0x20604625, 0x008d0178, 0x008d0158 }, { 0x00600041, 0x20404625, 0x008d0170, 0x008d0150 }, { 0x00000040, 0x20243da5, 0x00004110, 0x00800080 }, { 0x0c600038, 0x20c014a5, 0x008d0060, 0x00000080 }, { 0x0c600038, 0x20a014a5, 0x008d0040, 0x00000080 }, { 0x00800001, 0x404000ad, 0x008d00a0, 0x00000000 }, { 0x00800001, 0x204001ad, 0x00ae0040, 0x00000000 }, { 0x00600041, 0x208044a5, 0x00000024, 0x008d0158 }, { 0x00800041, 0x20a035a5, 0x008d0040, 0x00000110 }, { 0x00600041, 0x206044a5, 0x00000024, 0x008d0150 }, { 0x00800040, 0x204014a5, 0x008d00a0, 0x008d0060 }, { 0x0080000c, 0x60403cb1, 0x008d0040, 0x00070007 }, { 0x00800001, 0x21500231, 0x00cf0040, 0x00000000 }, { 0x0020002d, 0x20000024, 0x00450140, 0x00000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen75/sharpening_v_blur.g75b000066400000000000000000000460601231401140700267010ustar00rootroot00000000000000{ 0x00000001, 0x23600161, 0x00000000, 0x00000000 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000001, 0x23640161, 0x00000000, 0x00020002 }, { 0x00000001, 0x20480061, 0x00000000, 0x0007000f }, { 0x00000001, 0x204003bd, 0x0000002c, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000360, 0x02490000 }, { 0x00000001, 0x20440161, 0x00000000, 0x00000000 }, { 0x00000001, 0x20280161, 0x00000000, 0x00040004 }, { 0x0c600031, 0x22e003a1, 0x00000040, 0x00000200 }, { 0x00000040, 0x20203c21, 0x00000024, 0xfffcfffc }, { 0x06000010, 0x20002c20, 0x02000020, 0x00040004 }, { 0x00010220, 0x34001c00, 0x02001400, 0x00001470 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000360, 0x02490000 }, { 0x00800001, 0x22a003bd, 0x008d0320, 0x00000000 }, { 0x00800001, 0x226003bd, 0x008d02e0, 0x00000000 }, { 0x00000001, 0x20480061, 0x00000000, 0x0007000f }, { 0x00000001, 0x204003bd, 0x0000002c, 0x00000000 }, { 0x00000040, 0x20442c21, 0x00000028, 0x00040004 }, { 0x00600001, 0x20a0023d, 0x008d0278, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d0270, 0x00000000 }, { 0x00600001, 0x2060023d, 0x008d0268, 0x00000000 }, { 0x0c600031, 0x22e003a1, 0x00000040, 0x00000200 }, { 0x00000001, 0x202003fd, 0x00000000, 0x332bcc77 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00600001, 0x2040023d, 0x008d0260, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x00600001, 0x20a0023d, 0x008d0288, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d0280, 0x00000000 }, { 0x00000001, 0x214003fd, 0x00000000, 0x3e525448 }, { 0x00000001, 0x216003fd, 0x00000000, 0x3875735f }, { 0x00600001, 0x2040023d, 0x008d0270, 0x00000000 }, { 0x00000001, 0x203003fd, 0x00000000, 0x3c1d98ad }, { 0x00600001, 0x2060023d, 0x008d0278, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00600001, 0x20a0023d, 0x008d0298, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d0290, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00600001, 0x20a0023d, 0x008d02a8, 0x00000000 }, { 0x00000001, 0x215003fd, 0x00000000, 0x3f11e168 }, { 0x00600001, 0x2080023d, 0x008d02a0, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00600001, 0x20a0023d, 0x008d02b8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02b0, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00600001, 0x20a0023d, 0x008d02c8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02c0, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00600001, 0x20a0023d, 0x008d02d8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02d0, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00600001, 0x20a0023d, 0x008d02e8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02e0, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x00600001, 0x20a0023d, 0x008d0288, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d0280, 0x00000000 }, { 0x00800001, 0x218003a5, 0x008d0100, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00800001, 0x618000b1, 0x008d0180, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0298, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d0290, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00600001, 0x2080023d, 0x008d02a0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02a8, 0x00000000 }, { 0x00800001, 0x21a00231, 0x00cf0180, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00600001, 0x2080023d, 0x008d02b0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02b8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00600001, 0x2060023d, 0x008d0288, 0x00000000 }, { 0x00600001, 0x2040023d, 0x008d0280, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00600001, 0x2080023d, 0x008d02c0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02c8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00600001, 0x2080023d, 0x008d02d0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02d8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00600001, 0x2080023d, 0x008d02e0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02e8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00600001, 0x2080023d, 0x008d02f0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02f8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x00600001, 0x2080023d, 0x008d0290, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0298, 0x00000000 }, { 0x00800001, 0x222003a5, 0x008d0100, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00800001, 0x622000b1, 0x008d0220, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02a8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02a0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00600001, 0x2080023d, 0x008d02b0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02b8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00600001, 0x2080023d, 0x008d02c0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02c8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00600001, 0x2080023d, 0x008d02d0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02d8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00600001, 0x2080023d, 0x008d02e0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02e8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x21b00231, 0x00cf0220, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02f0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02f8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00600001, 0x2080023d, 0x008d0300, 0x00000000 }, { 0x00600001, 0x2060023d, 0x008d0298, 0x00000000 }, { 0x00600001, 0x2040023d, 0x008d0290, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0308, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x00600001, 0x20a0023d, 0x008d02a8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02a0, 0x00000000 }, { 0x00800001, 0x222003a5, 0x008d0100, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00800001, 0x622000b1, 0x008d0220, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02b8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02b0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00600001, 0x2040023d, 0x008d02a0, 0x00000000 }, { 0x00600001, 0x2060023d, 0x008d02a8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02c0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02c8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00600001, 0x2080023d, 0x008d02d0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02d8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00600001, 0x2080023d, 0x008d02e0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02e8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00600001, 0x2080023d, 0x008d02f0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02f8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00600001, 0x2080023d, 0x008d0300, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0308, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00600001, 0x2080023d, 0x008d0310, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0318, 0x00000000 }, { 0x00800001, 0x21c00231, 0x00cf0220, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x00600001, 0x2080023d, 0x008d02b0, 0x00000000 }, { 0x00800001, 0x222003a5, 0x008d0100, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02b8, 0x00000000 }, { 0x00800001, 0x622000b1, 0x008d0220, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00800001, 0x21d00231, 0x00cf0220, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x00600001, 0x20a0023d, 0x008d02c8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02c0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x00600001, 0x2040023d, 0x008d02b0, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00600001, 0x2060023d, 0x008d02b8, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02d8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02d0, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00600001, 0x20a0023d, 0x008d02e8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02e0, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00600001, 0x20a0023d, 0x008d02f8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02f0, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00600001, 0x20a0023d, 0x008d0308, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d0300, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00600001, 0x20a0023d, 0x008d0318, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d0310, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00600001, 0x20a0023d, 0x008d0328, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d0320, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x00600001, 0x20a0023d, 0x008d02c8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02c0, 0x00000000 }, { 0x00800001, 0x222003a5, 0x008d0100, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00800001, 0x622000b1, 0x008d0220, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02d8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02d0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00600001, 0x2080023d, 0x008d02e0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02e8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00600001, 0x2080023d, 0x008d02f0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02f8, 0x00000000 }, { 0x00800001, 0x21e00231, 0x00cf0220, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00600001, 0x2080023d, 0x008d0300, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0308, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00600001, 0x2060023d, 0x008d02c8, 0x00000000 }, { 0x00600001, 0x2040023d, 0x008d02c0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00600001, 0x2080023d, 0x008d0310, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0318, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00600001, 0x2080023d, 0x008d0320, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0328, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00600001, 0x2080023d, 0x008d0330, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0338, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x00600001, 0x2080023d, 0x008d02d0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02d8, 0x00000000 }, { 0x00800001, 0x222003a5, 0x008d0100, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00800001, 0x622000b1, 0x008d0220, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02e8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02e0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00600001, 0x2080023d, 0x008d02f0, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02f8, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00600001, 0x2080023d, 0x008d0300, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0308, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00600001, 0x2080023d, 0x008d0310, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0318, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00600001, 0x2080023d, 0x008d0320, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0328, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00600001, 0x2080023d, 0x008d0330, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0338, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00800001, 0x21f00231, 0x00cf0220, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d0340, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0348, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x00600001, 0x2080023d, 0x008d02e0, 0x00000000 }, { 0x00600001, 0x2060023d, 0x008d02d8, 0x00000000 }, { 0x00600001, 0x2040023d, 0x008d02d0, 0x00000000 }, { 0x00600001, 0x218003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000364, 0x0a0a8000 }, { 0x00600001, 0x20a0023d, 0x008d02e8, 0x00000000 }, { 0x00800001, 0x222003a5, 0x008d0100, 0x00000000 }, { 0x00800041, 0x20c07fbd, 0x008d0080, 0x3875735f }, { 0x00800001, 0x622000b1, 0x008d0220, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d02f8, 0x00000000 }, { 0x00600001, 0x2080023d, 0x008d02f0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00600001, 0x2080023d, 0x008d0300, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0308, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00600001, 0x2080023d, 0x008d0310, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0318, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00600001, 0x2080023d, 0x008d0320, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0328, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00600001, 0x2080023d, 0x008d0330, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0338, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00600001, 0x2080023d, 0x008d0340, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0348, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00600001, 0x2080023d, 0x008d0350, 0x00000000 }, { 0x00600001, 0x20a0023d, 0x008d0358, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x00000001, 0x21880061, 0x00000000, 0x0007000f }, { 0x00800001, 0x204003a5, 0x008d0100, 0x00000000 }, { 0x00000001, 0x218003bd, 0x0000002c, 0x00000000 }, { 0x00800001, 0x22000231, 0x00cf0220, 0x00000000 }, { 0x00800001, 0x604000b1, 0x008d0040, 0x00000000 }, { 0x00800001, 0x22100231, 0x00cf0040, 0x00000000 }, { 0x00000001, 0x218403bd, 0x00000028, 0x00000000 }, { 0x00000040, 0x20282c21, 0x00000028, 0x00080008 }, { 0x0c600031, 0x200003a0, 0x00000180, 0x00000200 }, { 0x00000040, 0x20203c21, 0x00000024, 0xfffcfffc }, { 0x05000010, 0x20000420, 0x00000028, 0x00000020 }, { 0x00010220, 0x34001c00, 0x00001400, 0xffffeb90 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000360, 0x02290000 }, { 0x00000001, 0x20480061, 0x00000000, 0x0003000f }, { 0x00000001, 0x204003bd, 0x0000002c, 0x00000000 }, { 0x00000001, 0x20440161, 0x00000000, 0x00000000 }, { 0x0c600031, 0x226003a1, 0x00000040, 0x00000200 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000364, 0x060a8000 }, { 0x00800001, 0x206003bd, 0x008d0260, 0x00000000 }, { 0x00000001, 0x20480061, 0x00000000, 0x0003000f }, { 0x00000001, 0x204003bd, 0x0000002c, 0x00000000 }, { 0x00000001, 0x20440161, 0x00000000, 0x00000000 }, { 0x00000040, 0x20203c21, 0x00000024, 0xfffcfffc }, { 0x0c600031, 0x200003a0, 0x00000040, 0x00000200 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000360, 0x02290000 }, { 0x00000001, 0x20480061, 0x00000000, 0x0003000f }, { 0x00000001, 0x204003bd, 0x0000002c, 0x00000000 }, { 0x00000001, 0x204403bd, 0x00000020, 0x00000000 }, { 0x0c600031, 0x226003a1, 0x00000040, 0x00000200 }, { 0x00600001, 0x204003bd, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000c20, 0x00000364, 0x060a8000 }, { 0x00800001, 0x206003bd, 0x008d0260, 0x00000000 }, { 0x00000001, 0x20480061, 0x00000000, 0x0003000f }, { 0x00000001, 0x204003bd, 0x0000002c, 0x00000000 }, { 0x00000001, 0x204403bd, 0x00000020, 0x00000000 }, { 0x0c600031, 0x200003a0, 0x00000040, 0x00000200 }, { 0x00600001, 0x2e0003bd, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20000fa0, 0x00000e00, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/000077500000000000000000000000001231401140700224125ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/post_processing/gen8/EOT.g8a000066400000000000000000000111121231401140700234360ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 2 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //End of Thread message mov (8) r127<1>:ud r0.0<8;8,1>:ud send (1) null<1>:d r127 0x27 0x02000010 intel-driver-1.3.0/src/shaders/post_processing/gen8/Makefile.am000066400000000000000000000027741231401140700244600ustar00rootroot00000000000000INTEL_PP_G8B = \ pl2_to_pl2.g8b \ pl2_to_pl3.g8b \ pl3_to_pl2.g8b \ pl3_to_pl3.g8b \ pl2_to_rgbx.g8b \ rgbx_to_nv12.g8b \ pl2_to_pa.g8b \ pl3_to_pa.g8b \ pa_to_pl2.g8b \ pa_to_pl3.g8b \ pa_to_pa.g8b \ $(NULL) INTEL_PP_PRE_G8B = \ sharpening_h_blur.g8b \ sharpening_unmask.g8b \ sharpening_v_blur.g8b INTEL_PP_G8A = \ EOT.g8a \ PL2_AVS_Buf_0.g8a \ PL2_AVS_Buf_1.g8a \ PL2_AVS_Buf_2.g8a \ PL2_AVS_Buf_3.g8a \ PL3_AVS_Buf_0.g8a \ PL3_AVS_Buf_1.g8a \ PL3_AVS_Buf_2.g8a \ PL3_AVS_Buf_3.g8a \ PA_AVS_Buf_0.g8a \ PA_AVS_Buf_1.g8a \ PA_AVS_Buf_2.g8a \ PA_AVS_Buf_3.g8a \ Save_AVS_NV12.g8a \ Save_AVS_PL3.g8a \ Save_AVS_RGBX.g8a \ Save_AVS_PA.g8a \ Set_AVS_Buf_0123_PL2.g8a \ Set_AVS_Buf_0123_PL3.g8a \ Set_AVS_Buf_0123_BGRA.g8a \ Set_AVS_Buf_0123_VYUA.g8a \ YUV_to_RGB.g8a \ RGB_to_YUV.g8a \ Set_Layer_0.g8a \ VP_Setup.g8a \ $(NULL) INTEL_PP_ASM = $(INTEL_PP_G8B:%.g8b=%.asm) INTEL_PP_GEN8_ASM = $(INTEL_PP_G8B:%.g8b=%.g8s) TARGETS = if HAVE_GEN4ASM TARGETS += $(INTEL_PP_G8B) endif all-local: $(TARGETS) SUFFIXES = .g8b .g8s .asm $(INTEL_PP_GEN8_ASM): $(INTEL_PP_ASM) $(INTEL_PP_G8A) .asm.g8s: $(AM_V_GEN)cpp $< > _pp0.$@; \ ../../gpp.py _pp0.$@ $@; \ rm _pp0.$@ .g8s.g8b: $(AM_V_GEN)intel-gen4asm -a -o $@ -g 8 $< CLEANFILES = $(INTEL_PP_GEN7_ASM) EXTRA_DIST = \ $(INTEL_PP_ASM) \ $(INTEL_PP_G8A) \ $(INTEL_PP_G8B) \ $(INTEL_PP_PRE_G8B) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/post_processing/gen8/PA_AVS_Buf_0.g8a000066400000000000000000000357531231401140700250540ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 44 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_0.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. mov (1) r22.4<1>:ud 0x400040:ud mov (1) r16.3<1>:ud r0.3<0;1,0>:ud //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x50EB000:ud //msg desc mov (1) r16.2<1>:ud 0x00000000:ud // Enable ARGB channels // set the vertical block number mov (1) r25.1<1>:ud 0:ud mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs send (1) uwBUFFER_0(0)<1> r16 0x2 a0.0:ud // Returns RGBA data in 16 GRFs in scrambled order SKIP_AVS_LOAD_L0_0_: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/PA_AVS_Buf_1.g8a000066400000000000000000000357531231401140700250550ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 44 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_0.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. mov (1) r22.4<1>:ud 0x400040:ud mov (1) r16.3<1>:ud r0.3<0;1,0>:ud //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x50EB000:ud //msg desc mov (1) r16.2<1>:ud 0x00000000:ud // Enable ARGB channels // set the vertical block number mov (1) r25.1<1>:ud 1:ud mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs send (1) uwBUFFER_1(0)<1> r16 0x2 a0.0:ud // Returns RGBA data in 16 GRFs in scrambled order SKIP_AVS_LOAD_L0_0_: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/PA_AVS_Buf_2.g8a000066400000000000000000000357531231401140700250560ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 44 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_0.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. mov (1) r22.4<1>:ud 0x400040:ud mov (1) r16.3<1>:ud r0.3<0;1,0>:ud //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x50EB000:ud //msg desc mov (1) r16.2<1>:ud 0x00000000:ud // Enable ARGB channels // set the vertical block number mov (1) r25.1<1>:ud 2:ud mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs send (1) uwBUFFER_2(0)<1> r16 0x2 a0.0:ud // Returns RGBA data in 16 GRFs in scrambled order SKIP_AVS_LOAD_L0_0_: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/PA_AVS_Buf_3.g8a000066400000000000000000000357531231401140700250570ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 44 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_0.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. mov (1) r22.4<1>:ud 0x400040:ud mov (1) r16.3<1>:ud r0.3<0;1,0>:ud //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x50EB000:ud //msg desc mov (1) r16.2<1>:ud 0x00000000:ud // Enable ARGB channels // set the vertical block number mov (1) r25.1<1>:ud 3:ud mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs send (1) uwBUFFER_3(0)<1> r16 0x2 a0.0:ud // Returns RGBA data in 16 GRFs in scrambled order SKIP_AVS_LOAD_L0_0_: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/PL2_AVS_Buf_0.g8a000066400000000000000000000364771231401140700251550ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 44 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_0.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. mov (1) r22.4<1>:ud 0x400040:ud mov (1) r16.3<1>:ud r0.3<0;1,0>:ud //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB000:ud //msg desc mov (1) r16.2<1>:ud 0x0000D000:ud // Enable Red channel // set the vertical block number mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs send (1) uwBUFFER_0(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x48EB001:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2<1>:ud 0x0000A000:ud // Enable Red+Blue channel send (1) uwBUFFER_0(4)<1> r16 0x2 a0.0:ud // Returns UV data in 8 GRFs in scrambled order SKIP_AVS_LOAD_L0_0_: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/PL2_AVS_Buf_1.g8a000066400000000000000000000362021231401140700251400ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 42 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_1.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 1 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ mov (1) r16.3<1>:ud r0.3<0;1,0>:ud //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB000:ud //msg desc mov (1) r16.2<1>:ud 0x0000D000:ud // Enable Red channel // set the vertical block number mov (1) r25.1<1>:ud 1:ud mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs send (1) uwBUFFER_1(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x48EB001:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2<1>:ud 0x0000A000:ud // Enable Red+Blue channel send (1) uwBUFFER_1(4)<1> r16 0x2 a0.0:ud // Returns UV data in 8 GRFs in scrambled order SKIP_AVS_LOAD_L0_1_: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/PL2_AVS_Buf_2.g8a000066400000000000000000000361751231401140700251520ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 42 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_2.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 2 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ mov (1) r16.3<1>:ud r0.3<0;1,0>:ud //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB000:ud //msg desc mov (1) r16.2<1>:ud 0x0000D000:ud // Enable Red channel // set the vertical block number mov (1) r25.1<1>:ud 2:ud mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs send (1) uwBUFFER_2(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x48EB001:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2<1>:ud 0x0000A000:ud // Enable Red+Blue channel send (1) uwBUFFER_2(4)<1> r16 0x2 a0.0:ud // Returns UV data in 8 GRFs in scrambled order SKIP_AVS_LOAD_L0_2_: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/PL2_AVS_Buf_3.g8a000066400000000000000000000362041231401140700251440ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 42 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_3.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ mov (1) r16.3<1>:ud r0.3<0;1,0>:ud //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB000:ud //msg desc mov (1) r16.2<1>:ud 0x0000D000:ud // Enable Red channel // set the vertical block number mov (1) r25.1<1>:ud 3:ud mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs send (1) uwBUFFER_3(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x48EB001:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2<1>:ud 0x0000A000:ud // Enable Red+Blue channel send (1) uwBUFFER_3(4)<1> r16 0x2 a0.0:ud // Returns UV data in 8 GRFs in scrambled order SKIP_AVS_LOAD_L0_3_: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/PL3_AVS_Buf_0.g8a000066400000000000000000000372111231401140700251410ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 44 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_0.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. mov (1) r22.4<1>:ud 0x400040:ud mov (1) r16.3<1>:ud r0.3<0;1,0>:ud //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB000:ud //msg desc mov (1) r16.2<1>:ud 0x0000D000:ud // Enable Red channel // set the vertical block number mov (1) r25.1<1>:ud 0:ud mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs send (1) uwBUFFER_0(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB001:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2<1>:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_0(4)<1> r16 0x2 a0.0:ud // Returns U data in 4 GRFs in scrambled order add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB002:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2<1>:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_0(8)<1> r16 0x2 a0.0:ud // Returns V data in 4 GRFs in scrambled order SKIP_AVS_LOAD_L0_0_: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/PL3_AVS_Buf_1.g8a000066400000000000000000000372111231401140700251420ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 44 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_0.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. mov (1) r22.4<1>:ud 0x400040:ud mov (1) r16.3<1>:ud r0.3<0;1,0>:ud //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB000:ud //msg desc mov (1) r16.2<1>:ud 0x0000D000:ud // Enable Red channel // set the vertical block number mov (1) r25.1<1>:ud 1:ud mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs send (1) uwBUFFER_1(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB001:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2<1>:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_1(4)<1> r16 0x2 a0.0:ud // Returns U data in 4 GRFs in scrambled order add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB002:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2<1>:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_1(8)<1> r16 0x2 a0.0:ud // Returns V data in 4 GRFs in scrambled order SKIP_AVS_LOAD_L0_0_: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/PL3_AVS_Buf_2.g8a000066400000000000000000000372041231401140700251450ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 44 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_0.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. mov (1) r22.4<1>:ud 0x400040:ud mov (1) r16.3<1>:ud r0.3<0;1,0>:ud //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB000:ud //msg desc mov (1) r16.2<1>:ud 0x0000D000:ud // Enable Red channel // set the vertical block number mov (1) r25.1<1>:ud 2:ud mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs send (1) uwBUFFER_2(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB001:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2<1>:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_2(4)<1> r16 0x2 a0.0:ud // Returns U data in 4 GRFs in scrambled order add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB002:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2<1>:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_2(8)<1> r16 0x2 a0.0:ud // Returns V data in 4 GRFs in scrambled order SKIP_AVS_LOAD_L0_0_: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/PL3_AVS_Buf_3.g8a000066400000000000000000000372041231401140700251460ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 44 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: PL2_AVS_Buf_0.asm // Author: Tatiya, Rupesh // Description: Loads 8x8 AVS/IEF PL2 data into Buffer 0 // FileName : PL2_AVS_Buf.asm // Author : Tatiya, Rupesh // Description : Loads 8x8 AVS/IEF PL2 data into Buffer N // Module name: Scaling.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. // Message Header // m0.7 31:0 Debug // m0.6 31:0 Debug // m0.5 31:0 Ignored // m0.4 31:0 Ignored // m0.3 31:0 Ignored // m0.2 31:16 Ignored // 15 Alpha Write Channel Mask enable=0, disable=1 // 14 Blue Write Channel Mask (U) // 13 Green Write Channel Mask (Y) // 12 Red Write Channel Mask (V) // 11:0 Ignored // m0.1 Ignored // m0.0 Ignored // AVS payload // m1.7 Group ID Number // m1.6 U 2nd Derivative ---> NLAS dx // m1.5 Delta V ---> Step Y // m1.4 Delta U ---> Step X // m1.3 Pixel 0 V Address ---> ORIY (Y0) // m1.2 Pixel 0 U Address ---> ORIX (X0) // m1.1 Vertical Block Number // m1.0 Reserved // Sampler Message Descriptor // 31:29 Reserved 000 // 28:25 Message length 0010 // 24:20 Response length xxxxx ---> 4GRFs for each enabled channel (AVS), 2GRFs for each enabled channel (sample unorm) // 19 Header Present 1 // 18:17 SIMD Mode 11 ---> SIMD32/64 // 16:12 Message Type xxxxx ---> 01011 sample_8x8, 01100 (sample_unorm), 01010 (sample_unorm+killpix) // 11:8 Sampler Index xxxx // 7:0 Binding Table Index xxxxxxxx // Msg Header M0.2 // 15:15 Alpha Write Channel Mask, 0: written back, 1: not written back // 14:14 Blue Write Channel Mask // 13:13 Green Write Channel Mask // 12:12 Red Write Channel Mask //By design, Buffer 0,1,2,3 always have Layer 0 and Buffer 4,5 always have L1-L7 //used to generate LABELS at compile time. // 18:17 SIMD Mode 10 ---> SIMD16 // 16:12 Message Type xxxxx ---> 00000 (SIMD16) //r10-17 - 8 GRFs to load SIMD16 data (upto 4 channels) //r18-19 - 2 GRFs to store sampler ramp. .declare mfSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare muwSCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare mudCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare mubCALING_0X_34X_PAYLOAD Base=r14.0 ElementSize=1 SrcRegion=<32;32,1> DstRegion=<1> Type=ub .declare fSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udSCALING_0X_34X_TEMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare ub4SCALING_0X_34X_TEMP Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<1> Type=ub .declare uwSCALING_0X_34X_TEMP Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw // Sampler ramp is used for Scaling 0X_0.34X .declare fSAMPLER_RAMP Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> Type=f // 1 GRFs, 8 elements //#define rMSGDSC_UV r23.0 //End of _SCALING_ //NOTE: We need offsets for second halfof LAYER 0 - even if we do not load it. //Update the channel offset in the buffers for the lower 8x4 data for BUFFER_0. mov (1) r22.4<1>:ud 0x400040:ud mov (1) r16.3<1>:ud r0.3<0;1,0>:ud //AVS_PAYLOAD already has all the data loaded at this point add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB000:ud //msg desc mov (1) r16.2<1>:ud 0x0000D000:ud // Enable Red channel // set the vertical block number mov (1) r25.1<1>:ud 3:ud mov (8) r17.0<1>:ud r25.0<8;8,1>:ud // Copy msg payload mirrors to MRFs send (1) uwBUFFER_3(0)<1> r16 0x2 a0.0:ud // Returns Y data in 4 GRFs in scrambled order add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB001:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2<1>:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_3(4)<1> r16 0x2 a0.0:ud // Returns U data in 4 GRFs in scrambled order add (1) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EB002:ud // msg desc; 1 is added to change BI to UV mov (1) r16.2<1>:ud 0x0000E000:ud // Enable Red channel send (1) uwBUFFER_3(8)<1> r16 0x2 a0.0:ud // Returns V data in 4 GRFs in scrambled order SKIP_AVS_LOAD_L0_0_: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/RGB_to_YUV.g8a000066400000000000000000001051071231401140700246760ustar00rootroot00000000000000/* * Copyright 2000-2013 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * Authors: * Zhao Yakui */ // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: YUV_to_RGB.asm // // Convert YUV to RGB, handle it by 16x4 block // // Description: Includes all definitions explicit to Fast Composite. //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare bBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare bBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare bBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare bBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw //Pointer to mask reg .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written //Unnecessary to use the MSGPayLoad, So it is temporiarily used for conversion of YUV->RGB .declare fBUFFER_R Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_G Base=r30.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_B Base=r32.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_Y Base=r36.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_U Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_V Base=r40.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare wTempY Base=r42.0 ElementSize=2 Type=w .declare wTempU Base=r44.0 ElementSize=2 Type=w .declare wTempV Base=r46.0 ElementSize=2 Type=w .declare ubTempY Base=r42.0 ElementSize=1 Type=ub .declare ubTempU Base=r44.0 ElementSize=1 Type=ub .declare ubTempV Base=r46.0 ElementSize=1 Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ // ITU-R conversion, Now we are using ITU-R conversion // Y = 0.299R + 0.587G + 0.114B // U = -0.169R - 0.331G + 0.499B + 128 // V = 0.499R - 0.418G - 0.0813B+ 128 // At the save module we have all 8 address sub-registers available. // So we will use PING-PONG type of scheme to save the data using // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help // reduce dependency. - rT //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4. //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5). //Offsets are zero for buffer 0 and buffer 4. //It always uses the YUVA layout. //for BUFFER_0 mov (4) a0.0<1>:uw r22.0<4;4,1>:uw mov (4) a0.4<1>:uw r22.0<4;4,1>:uw // YUV uses the a0.5,a0.6 and a0.4 as the indirect-register // Y = a0.5, U=a0.6, V=a0.4 // if channel swap? // This means that it should be BGRX(B is the LSB) or RGBX // 1 means that it is BGRX. and.nz.f0.0 null<1>:w r2.0<0;1,0>:uw 0x01:w // pointer swap (f0.0) mov (1) uwTemp0<1> a0.0:uw (f0.0) mov (1) a0.0:uw a0.1:uw (f0.0) mov (1) a0.1:uw uwTemp0<0;1,0> //the first line in the block 0 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 17]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 0]<1>:uw 0:uw mov (16) r[a0.6, 0]<1>:uw 0:uw mov (16) r[a0.4, 0]<1>:uw 0:uw mov (16) r[a0.5,1]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,1]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,1]<2>:ub ubTempV(0, 0)<32;8,4> //the second line in the block 0 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 49]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 32]<1>:uw 0:uw mov (16) r[a0.6, 32]<1>:uw 0:uw mov (16) r[a0.4, 32]<1>:uw 0:uw mov (16) r[a0.5,33]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,33]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,33]<2>:ub ubTempV(0, 0)<32;8,4> //the third line in the block 0 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 81]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 64]<1>:uw 0:uw mov (16) r[a0.6, 64]<1>:uw 0:uw mov (16) r[a0.4, 64]<1>:uw 0:uw mov (16) r[a0.5,65]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,65]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,65]<2>:ub ubTempV(0, 0)<32;8,4> //the fourth line in the block 0 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 113]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 96]<1>:uw 0:uw mov (16) r[a0.6, 96]<1>:uw 0:uw mov (16) r[a0.4, 96]<1>:uw 0:uw mov (16) r[a0.5,97]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,97]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,97]<2>:ub ubTempV(0, 0)<32;8,4> //for Buffer_1 add (8) a0.0<1>:uw a0.0<8;8,1>:uw 512:uw //the first line in the block 1 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 17]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 0]<1>:uw 0:uw mov (16) r[a0.6, 0]<1>:uw 0:uw mov (16) r[a0.4, 0]<1>:uw 0:uw mov (16) r[a0.5,1]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,1]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,1]<2>:ub ubTempV(0, 0)<32;8,4> //the second line in the block 1 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 49]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 32]<1>:uw 0:uw mov (16) r[a0.6, 32]<1>:uw 0:uw mov (16) r[a0.4, 32]<1>:uw 0:uw mov (16) r[a0.5,33]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,33]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,33]<2>:ub ubTempV(0, 0)<32;8,4> //the third line in the block 1 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 81]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 64]<1>:uw 0:uw mov (16) r[a0.6, 64]<1>:uw 0:uw mov (16) r[a0.4, 64]<1>:uw 0:uw mov (16) r[a0.5,65]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,65]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,65]<2>:ub ubTempV(0, 0)<32;8,4> //the fourth line in the block 1 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 113]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 96]<1>:uw 0:uw mov (16) r[a0.6, 96]<1>:uw 0:uw mov (16) r[a0.4, 96]<1>:uw 0:uw mov (16) r[a0.5,97]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,97]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,97]<2>:ub ubTempV(0, 0)<32;8,4> //for Buffer_2 add (8) a0.0<1>:uw a0.0<8;8,1>:uw 512:uw //the first line in the block 2 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 17]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 0]<1>:uw 0:uw mov (16) r[a0.6, 0]<1>:uw 0:uw mov (16) r[a0.4, 0]<1>:uw 0:uw mov (16) r[a0.5,1]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,1]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,1]<2>:ub ubTempV(0, 0)<32;8,4> //the second line in the block 2 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 49]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 32]<1>:uw 0:uw mov (16) r[a0.6, 32]<1>:uw 0:uw mov (16) r[a0.4, 32]<1>:uw 0:uw mov (16) r[a0.5,33]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,33]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,33]<2>:ub ubTempV(0, 0)<32;8,4> //the third line in the block 2 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 81]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 64]<1>:uw 0:uw mov (16) r[a0.6, 64]<1>:uw 0:uw mov (16) r[a0.4, 64]<1>:uw 0:uw mov (16) r[a0.5,65]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,65]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,65]<2>:ub ubTempV(0, 0)<32;8,4> //the fourth line in the block 2 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 113]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 96]<1>:uw 0:uw mov (16) r[a0.6, 96]<1>:uw 0:uw mov (16) r[a0.4, 96]<1>:uw 0:uw mov (16) r[a0.5,97]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,97]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,97]<2>:ub ubTempV(0, 0)<32;8,4> //for Buffer_3 add (8) a0.0<1>:uw a0.0<8;8,1>:uw 512:uw //the first line in the block 3 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 17]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 0]<1>:uw 0:uw mov (16) r[a0.6, 0]<1>:uw 0:uw mov (16) r[a0.4, 0]<1>:uw 0:uw mov (16) r[a0.5,1]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,1]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,1]<2>:ub ubTempV(0, 0)<32;8,4> //the second line in the block 3 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 49]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 32]<1>:uw 0:uw mov (16) r[a0.6, 32]<1>:uw 0:uw mov (16) r[a0.4, 32]<1>:uw 0:uw mov (16) r[a0.5,33]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,33]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,33]<2>:ub ubTempV(0, 0)<32;8,4> //the third line in the block 3 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 81]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 64]<1>:uw 0:uw mov (16) r[a0.6, 64]<1>:uw 0:uw mov (16) r[a0.4, 64]<1>:uw 0:uw mov (16) r[a0.5,65]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,65]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,65]<2>:ub ubTempV(0, 0)<32;8,4> //the fourth line in the block 3 mov (8) fBUFFER_R(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_R(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_G(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_G(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_B(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_B(1, 0)<1> r[a0.0, 113]<16;8,2>:ub mul (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.299f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> 0.587f mac (16) fBUFFER_Y(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.114f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> -0.169f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.331f mac (16) fBUFFER_U(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.499f mov (16) acc0.0<1>:f 128.0f mac (16) acc0.0<1>:f fBUFFER_R(0, 0)<8;8,1> 0.499f mac (16) acc0.0<1>:f fBUFFER_G(0, 0)<8;8,1> -0.418f mac (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> -0.0813f mov (16) wTempY(0,0)<2> fBUFFER_Y(0, 0)<8;8,1> mov (16) wTempU(0,0)<2> fBUFFER_U(0, 0)<8;8,1> mov (16) wTempV(0,0)<2> fBUFFER_V(0, 0)<8;8,1> mov (16) r[a0.5, 96]<1>:uw 0:uw mov (16) r[a0.6, 96]<1>:uw 0:uw mov (16) r[a0.4, 96]<1>:uw 0:uw mov (16) r[a0.5,97]<2>:ub ubTempY(0, 0)<32;8,4> mov (16) r[a0.6,97]<2>:ub ubTempU(0, 0)<32;8,4> mov (16) r[a0.4,97]<2>:ub ubTempV(0, 0)<32;8,4> intel-driver-1.3.0/src/shaders/post_processing/gen8/Save_AVS_NV12.g8a000066400000000000000000000561721231401140700252030ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 131 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: Save_AVS_NV12.asm // // Save NV12 420 frame data block of size 16x16 // // To save 16x16 block (16x16 bytes of Y and 16x8 bytes of interleaved UV), we need 2 send instructions with of size 16x16 and 16x8 each. // --------------- // | 16x16 | // | YUYV | // --------------- // | 16x8 UV | // --------------- //----------------------------------------------------------------- //The layout of data is as follows: //mMSGHDR0 : Y data header (16x16) //mubMSGPAYLOAD0 : Y data payload (8 GRFs) //mMSGHDR1 : U data header (16x8) //mubMSGPAYLOAD1 : U data payload (4 GRFs) //------------------------------------------------------------------ // Module name: Save.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written .declare mudMSGPAYLOAD0 Base=r29.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD1 Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD2 Base=r47.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD3 Base=r56.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare muwMSGPAYLOAD0 Base=r29.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD1 Base=r38.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD2 Base=r47.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD3 Base=r56.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mubMSGPAYLOAD0 Base=r29.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD1 Base=r38.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD2 Base=r47.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD3 Base=r56.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD4 Base=r32.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD5 Base=r41.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD6 Base=r50.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD7 Base=r59.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ // At the save module we have all 8 address sub-registers available. // So we will use PING-PONG type of scheme to save the data using // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help // reduce dependency. - rT //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4. //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5). //Offsets are zero for buffer 0 and buffer 4. add (4) a0.0<1>:uw r22.0<4;4,1>:w 0:uw add (4) a0.4<1>:uw r22.0<4;4,1>:w 512:uw //Set up header for Y,U and V data mov (8) r28<1>:ud r27<8;8,1>:ud mov (8) r37<1>:ud r27<8;8,1>:ud mov (2) r28.0<1>:d r7.0<2;2,1>:w { NoDDClr } //ORI Y (LUMA) = ORI mov (1) r37.0<1>:d r7.0<0;1,0>:w { NoDDClr } //H ORI (CHROMA) = H ORI shr (1) r37.1<1>:d r7.1<0;1,0>:w 1:w { NoDDClr, NoDDChk } //V ORI (CHROMA) = V ORI/2 mov (1) r28.2<1>:ud 0xF000F:ud { NoDDChk } // Y Block width and height (16x16) mov (1) r37.2<1>:ud 0x7000F:ud { NoDDChk } // UV Block width and height(16x8) // Unscramble, and pack data directly to MRFs // Data 16x16 block is divided as - // --------- // | 0 | // --------- // | 1 | // --------- // | 2 | // --------- // | 3 | // --------- // All sub-blocks are of size 16x4 // 0: ubBUFFER_0 // 1: ubBUFFER_1, ubBUFFER_0+16 // 2: ubBUFFER_2 // 3: ubBUFFER_3, ubBUFFER_2+16 //Y Rounding 16x4 top part add.sat (16) r[a0.1,0]<1>:uw r[a0.1,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,32]<1>:uw r[a0.1,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,64]<1>:uw r[a0.1,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,96]<1>:uw r[a0.1,96]<16;16,1>:uw 0x0080:uw // U Averaging and Rounding, 8x2 top part shr (8) uwBUFFER_5(0,0)<2> r[a0.2,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(1,0)<2> r[a0.2,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(2,0)<2> r[a0.2,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(3,0)<2> r[a0.2,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(0,0)<2> uwBUFFER_5(0,0)<16;8,2> uwBUFFER_5(1,0)<16;8,2> add.sat (8) r[a0.2,0]<2>:uw uwBUFFER_5(0,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(2,0)<2> uwBUFFER_5(2,0)<16;8,2> uwBUFFER_5(3,0)<16;8,2> add.sat (8) r[a0.2,64]<2>:uw uwBUFFER_5(2,0)<16;8,2> 0x0080:uw // V Averaging and Rounding, 8x2 top part shr (8) uwBUFFER_5(4,0)<2> r[a0.0,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(5,0)<2> r[a0.0,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(6,0)<2> r[a0.0,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(7,0)<2> r[a0.0,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(4,0)<2> uwBUFFER_5(4,0)<16;8,2> uwBUFFER_5(5,0)<16;8,2> add.sat (8) r[a0.0,0]<2>:uw uwBUFFER_5(4,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(6,0)<2> uwBUFFER_5(6,0)<16;8,2> uwBUFFER_5(7,0)<16;8,2> add.sat (8) r[a0.0,64]<2>:uw uwBUFFER_5(6,0)<16;8,2> 0x0080:uw add (4) a0.0<1>:uw r22.0<4;4,1>:w 1024:uw //Update Buffer 2 pointers //Y Rounding, 16x4 bottom part add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,64]<1>:uw r[a0.5,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,96]<1>:uw r[a0.5,96]<16;16,1>:uw 0x0080:uw // U Averaging and Rounding, 8x2 bottom part shr (8) uwBUFFER_5(0,0)<2> r[a0.6,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(1,0)<2> r[a0.6,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(2,0)<2> r[a0.6,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(3,0)<2> r[a0.6,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(0,0)<2> uwBUFFER_5(0,0)<16;8,2> uwBUFFER_5(1,0)<16;8,2> add.sat (8) r[a0.6,0]<2>:uw uwBUFFER_5(0,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(2,0)<2> uwBUFFER_5(2,0)<16;8,2> uwBUFFER_5(3,0)<16;8,2> add.sat (8) r[a0.6,64]<2>:uw uwBUFFER_5(2,0)<16;8,2> 0x0080:uw // V Averaging and Rounding, 8x2 bottom part shr (8) uwBUFFER_5(4,0)<2> r[a0.4,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(5,0)<2> r[a0.4,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(6,0)<2> r[a0.4,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(7,0)<2> r[a0.4,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(4,0)<2> uwBUFFER_5(4,0)<16;8,2> uwBUFFER_5(5,0)<16;8,2> add.sat (8) r[a0.4,0]<2>:uw uwBUFFER_5(4,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(6,0)<2> uwBUFFER_5(6,0)<16;8,2> uwBUFFER_5(7,0)<16;8,2> add.sat (8) r[a0.4,64]<2>:uw uwBUFFER_5(6,0)<16;8,2> 0x0080:uw add (4) a0.4<1>:uw r22.0<4;4,1>:w 1536:uw //Update Buffer 3 pointers //Y Rounding 16x4 top part add.sat (16) r[a0.1,0]<1>:uw r[a0.1,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,32]<1>:uw r[a0.1,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,64]<1>:uw r[a0.1,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,96]<1>:uw r[a0.1,96]<16;16,1>:uw 0x0080:uw // U Averaging and Rounding, 8x2 top part shr (8) uwBUFFER_5(0,0)<2> r[a0.2,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(1,0)<2> r[a0.2,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(2,0)<2> r[a0.2,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(3,0)<2> r[a0.2,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(0,0)<2> uwBUFFER_5(0,0)<16;8,2> uwBUFFER_5(1,0)<16;8,2> add.sat (8) r[a0.2,0]<2>:uw uwBUFFER_5(0,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(2,0)<2> uwBUFFER_5(2,0)<16;8,2> uwBUFFER_5(3,0)<16;8,2> add.sat (8) r[a0.2,64]<2>:uw uwBUFFER_5(2,0)<16;8,2> 0x0080:uw // V Averaging and Rounding, 8x2 top part shr (8) uwBUFFER_5(4,0)<2> r[a0.0,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(5,0)<2> r[a0.0,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(6,0)<2> r[a0.0,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(7,0)<2> r[a0.0,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(4,0)<2> uwBUFFER_5(4,0)<16;8,2> uwBUFFER_5(5,0)<16;8,2> add.sat (8) r[a0.0,0]<2>:uw uwBUFFER_5(4,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(6,0)<2> uwBUFFER_5(6,0)<16;8,2> uwBUFFER_5(7,0)<16;8,2> add.sat (8) r[a0.0,64]<2>:uw uwBUFFER_5(6,0)<16;8,2> 0x0080:uw add (4) a0.0<1>:uw r22.0<4;4,1>:w 1024:uw //Update Buffer 2 pointers //Y Rounding, 16x4 bottom part add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,64]<1>:uw r[a0.5,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,96]<1>:uw r[a0.5,96]<16;16,1>:uw 0x0080:uw // U Averaging and Rounding, 8x2 bottom part shr (8) uwBUFFER_5(0,0)<2> r[a0.6,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(1,0)<2> r[a0.6,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(2,0)<2> r[a0.6,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(3,0)<2> r[a0.6,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(0,0)<2> uwBUFFER_5(0,0)<16;8,2> uwBUFFER_5(1,0)<16;8,2> add.sat (8) r[a0.6,0]<2>:uw uwBUFFER_5(0,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(2,0)<2> uwBUFFER_5(2,0)<16;8,2> uwBUFFER_5(3,0)<16;8,2> add.sat (8) r[a0.6,64]<2>:uw uwBUFFER_5(2,0)<16;8,2> 0x0080:uw // V Averaging and Rounding, 8x2 bottom part shr (8) uwBUFFER_5(4,0)<2> r[a0.4,0]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(5,0)<2> r[a0.4,32]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(6,0)<2> r[a0.4,64]<16;8,2>:uw 1:w shr (8) uwBUFFER_5(7,0)<2> r[a0.4,96]<16;8,2>:uw 1:w add (8) uwBUFFER_5(4,0)<2> uwBUFFER_5(4,0)<16;8,2> uwBUFFER_5(5,0)<16;8,2> add.sat (8) r[a0.4,0]<2>:uw uwBUFFER_5(4,0)<16;8,2> 0x0080:uw add (8) uwBUFFER_5(6,0)<2> uwBUFFER_5(6,0)<16;8,2> uwBUFFER_5(7,0)<16;8,2> add.sat (8) r[a0.4,64]<2>:uw uwBUFFER_5(6,0)<16;8,2> 0x0080:uw add (4) a0.4<1>:uw r22.0<4;4,1>:w 1536:uw //Update Buffer 3 pointers // restore pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4 registers add (4) a0.0<1>:uw r22.0<4;4,1>:w 0:uw add (4) a0.4<1>:uw r22.0<4;4,1>:w 512:uw //Buffer 0 //Move Y to msg payload mov (16) mubMSGPAYLOAD0(0,0)<1> r[a0.1, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(0,16)<1> r[a0.1, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(1,0)<1> r[a0.1, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(1,16)<1> r[a0.1, 97]<32;16,2>:ub { NoDDChk } //Move U to msg payload mov (8) mubMSGPAYLOAD1(0,0)<2> r[a0.2, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD1(0,16)<2> r[a0.2, 65]<32;8,4>:ub { NoDDClr, NoDDChk } //Move V to msg payload mov (8) mubMSGPAYLOAD1(0,1)<2> r[a0.0, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(0,17)<2> r[a0.0, 65]<32;8,4>:ub { NoDDChk } add (4) a0.0<1>:uw r22.0<4;4,1>:w 1024:uw //Update Buffer 2 pointers //Buffer 1 mov (16) mubMSGPAYLOAD0(2,0)<1> r[a0.5, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(2,16)<1> r[a0.5, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(3,0)<1> r[a0.5, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(3,16)<1> r[a0.5, 97]<32;16,2>:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(1,0)<2> r[a0.6, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD1(1,16)<2> r[a0.6, 65]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(1,1)<2> r[a0.4, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(1,17)<2> r[a0.4, 65]<32;8,4>:ub { NoDDChk } add (4) a0.4<1>:uw r22.0<4;4,1>:w 1536:uw //Update Buffer 3 pointers //Buffer 2 mov (16) mubMSGPAYLOAD0(4,0)<1> r[a0.1, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(4,16)<1> r[a0.1, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(5,0)<1> r[a0.1, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(5,16)<1> r[a0.1, 97]<32;16,2>:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(2,0)<2> r[a0.2, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD1(2,16)<2> r[a0.2, 65]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(2,1)<2> r[a0.0, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(2,17)<2> r[a0.0, 65]<32;8,4>:ub { NoDDChk } //Buffer 3 mov (16) mubMSGPAYLOAD0(6,0)<1> r[a0.5, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(6,16)<1> r[a0.5, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(7,0)<1> r[a0.5, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(7,16)<1> r[a0.5, 97]<32;16,2>:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(3,0)<2> r[a0.6, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD1(3,16)<2> r[a0.6, 65]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(3,1)<2> r[a0.4, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(3,17)<2> r[a0.4, 65]<32;8,4>:ub { NoDDChk } //=========================================================================== send (1) null<1>:d r28 0xc 0x120A8018:ud send (1) null<1>:d r37 0xc 0xA0A8019:ud intel-driver-1.3.0/src/shaders/post_processing/gen8/Save_AVS_PA.g8a000066400000000000000000000621011231401140700250020ustar00rootroot00000000000000/* * Copyright 2000-2013 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * Authors: Zhao Yakui */ // 174 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: Save_AVS_PA.asm // // Save PA 422 frame data block of size 16x16 // // To save 16x16 block (32x16 bytes of YUYV) we need 2 send instructions with of size 16x16 each. // ------------------------------- // | 16x16 | 16x16 | // | YUYV | YUYV | // ------------------------------- // these 2 sends are replaced by 8 32x2 sends to improve performance // Module name: Save.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written .declare mudMSGPAYLOAD0 Base=r29.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD1 Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD2 Base=r47.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD3 Base=r56.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare muwMSGPAYLOAD0 Base=r29.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD1 Base=r38.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD2 Base=r47.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD3 Base=r56.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mubMSGPAYLOAD0 Base=r29.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD1 Base=r38.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD2 Base=r47.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD3 Base=r56.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD4 Base=r32.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD5 Base=r41.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD6 Base=r50.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD7 Base=r59.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ //wBUFF_CHNL_PTR points to buffer 0. //Add appropriate offsets to get pointers for all buffers (1,2,3). //Offset is zero for buffer 0. add (4) a0.0<1>:uw r22.0<4;4,1>:w 0:uw //Set DEST pointers according to output packing i.e. YUYV, YVYU, UYVY, VYUY add (4) a0.4<1>:w r2.28<4;4,1>:ub 928:uw /* X block origin. YUY2 or UYUV */ shl (1) r27.0<1>:d r7.0<0;1,0>:w 1:w { NoDDClr } // H. block origin need to be 2 times mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin (1st quadrant) mov (1) r27.2<1>:ud 0x1001F:ud { NoDDChk } // Block width and height (32x2) // Rounding // left add.sat (4) r[a0.0, 0]<2>:uw r[a0.0, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,32]<2>:uw r[a0.0, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,64]<2>:uw r[a0.0, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,96]<2>:uw r[a0.0, 96]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 0]<1>:uw r[a0.1, 0]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,32]<1>:uw r[a0.1, 32]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,64]<1>:uw r[a0.1, 64]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,96]<1>:uw r[a0.1, 96]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 0]<2>:uw r[a0.2, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,32]<2>:uw r[a0.2, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,64]<2>:uw r[a0.2, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,96]<2>:uw r[a0.2, 96]<8;4,2>:uw 0x0080:uw // right add.sat (4) r[a0.0,16]<2>:uw r[a0.0, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,48]<2>:uw r[a0.0, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,80]<2>:uw r[a0.0, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,112]<2>:uw r[a0.0, 112]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 16]<1>:uw r[a0.1, 16]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,48]<1>:uw r[a0.1, 48]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,80]<1>:uw r[a0.1, 80]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,112]<1>:uw r[a0.1, 112]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 16]<2>:uw r[a0.2, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,48]<2>:uw r[a0.2, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,80]<2>:uw r[a0.2, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,112]<2>:uw r[a0.2, 112]<8;4,2>:uw 0x0080:uw add (4) a0.0<1>:uw r22.0<4;4,1>:w 512:uw // left add.sat (4) r[a0.0, 0]<2>:uw r[a0.0, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,32]<2>:uw r[a0.0, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,64]<2>:uw r[a0.0, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,96]<2>:uw r[a0.0, 96]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 0]<1>:uw r[a0.1, 0]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,32]<1>:uw r[a0.1, 32]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,64]<1>:uw r[a0.1, 64]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,96]<1>:uw r[a0.1, 96]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 0]<2>:uw r[a0.2, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,32]<2>:uw r[a0.2, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,64]<2>:uw r[a0.2, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,96]<2>:uw r[a0.2, 96]<8;4,2>:uw 0x0080:uw // right add.sat (4) r[a0.0,16]<2>:uw r[a0.0, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,48]<2>:uw r[a0.0, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,80]<2>:uw r[a0.0, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,112]<2>:uw r[a0.0, 112]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 16]<1>:uw r[a0.1, 16]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,48]<1>:uw r[a0.1, 48]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,80]<1>:uw r[a0.1, 80]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,112]<1>:uw r[a0.1, 112]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 16]<2>:uw r[a0.2, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,48]<2>:uw r[a0.2, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,80]<2>:uw r[a0.2, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,112]<2>:uw r[a0.2, 112]<8;4,2>:uw 0x0080:uw add (4) a0.0<1>:uw r22.0<4;4,1>:w 1024:uw // left add.sat (4) r[a0.0, 0]<2>:uw r[a0.0, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,32]<2>:uw r[a0.0, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,64]<2>:uw r[a0.0, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,96]<2>:uw r[a0.0, 96]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 0]<1>:uw r[a0.1, 0]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,32]<1>:uw r[a0.1, 32]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,64]<1>:uw r[a0.1, 64]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,96]<1>:uw r[a0.1, 96]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 0]<2>:uw r[a0.2, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,32]<2>:uw r[a0.2, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,64]<2>:uw r[a0.2, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,96]<2>:uw r[a0.2, 96]<8;4,2>:uw 0x0080:uw // right add.sat (4) r[a0.0,16]<2>:uw r[a0.0, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,48]<2>:uw r[a0.0, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,80]<2>:uw r[a0.0, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,112]<2>:uw r[a0.0, 112]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 16]<1>:uw r[a0.1, 16]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,48]<1>:uw r[a0.1, 48]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,80]<1>:uw r[a0.1, 80]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,112]<1>:uw r[a0.1, 112]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 16]<2>:uw r[a0.2, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,48]<2>:uw r[a0.2, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,80]<2>:uw r[a0.2, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,112]<2>:uw r[a0.2, 112]<8;4,2>:uw 0x0080:uw add (4) a0.0<1>:uw r22.0<4;4,1>:w 1536:uw // left add.sat (4) r[a0.0, 0]<2>:uw r[a0.0, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,32]<2>:uw r[a0.0, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,64]<2>:uw r[a0.0, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,96]<2>:uw r[a0.0, 96]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 0]<1>:uw r[a0.1, 0]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,32]<1>:uw r[a0.1, 32]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,64]<1>:uw r[a0.1, 64]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,96]<1>:uw r[a0.1, 96]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 0]<2>:uw r[a0.2, 0]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,32]<2>:uw r[a0.2, 32]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,64]<2>:uw r[a0.2, 64]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,96]<2>:uw r[a0.2, 96]<8;4,2>:uw 0x0080:uw // right add.sat (4) r[a0.0,16]<2>:uw r[a0.0, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,48]<2>:uw r[a0.0, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,80]<2>:uw r[a0.0, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.0,112]<2>:uw r[a0.0, 112]<8;4,2>:uw 0x0080:uw add.sat (8) r[a0.1, 16]<1>:uw r[a0.1, 16]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,48]<1>:uw r[a0.1, 48]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,80]<1>:uw r[a0.1, 80]<8;8,1>:uw 0x0080:uw add.sat (8) r[a0.1,112]<1>:uw r[a0.1, 112]<8;8,1>:uw 0x0080:uw add.sat (4) r[a0.2, 16]<2>:uw r[a0.2, 16]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,48]<2>:uw r[a0.2, 48]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,80]<2>:uw r[a0.2, 80]<8;4,2>:uw 0x0080:uw add.sat (4) r[a0.2,112]<2>:uw r[a0.2, 112]<8;4,2>:uw 0x0080:uw add (4) a0.0<1>:uw r22.0<4;4,1>:w 2048:uw // restore pointer add (4) a0.0<1>:uw r22.0<4;4,1>:w 0:uw mov (8) r28<1>:ud r27<8;8,1>:ud mov (8) r37<1>:ud r27<8;8,1>:ud add (1) r37.1<1>:d r27.1<0;1,0>:d 2:d // Point to 2nd part /* a0.2 U, a0.1 Y, a0.0 V */ mov (8) r[a0.6, 0]<4>:ub r[a0.0, 1]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 32]<4>:ub r[a0.0,33]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4, 0]<2>:ub r[a0.1, 1]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4, 32]<2>:ub r[a0.1,33]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5, 0]<4>:ub r[a0.2, 1]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5, 32]<4>:ub r[a0.2,33]<32;8,4>:ub { NoDDChk } /* a0.4 + 288 = r38 */ mov (8) r[a0.6, 288]<4>:ub r[a0.0,65]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 320]<4>:ub r[a0.0,97]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4,288]<2>:ub r[a0.1,65]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4,320]<2>:ub r[a0.1,97]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5,288]<4>:ub r[a0.2,65]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5,320]<4>:ub r[a0.2,97]<32;8,4>:ub { NoDDChk } send (1) null<1>:d r28 0xc 0x60A8018:ud send (1) null<1>:d r37 0xc 0x60A8018:ud // restore pointer add (4) a0.0<1>:uw r22.0<4;4,1>:w 512:uw add (1) r28.1<1>:d r27.1<0;1,0>:d 4:d // Point to 2nd part add (1) r37.1<1>:d r27.1<0;1,0>:d 6:d // Point to 2nd part mov (8) r[a0.6, 0]<4>:ub r[a0.0, 1]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 32]<4>:ub r[a0.0,33]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4, 0]<2>:ub r[a0.1, 1]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4, 32]<2>:ub r[a0.1,33]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5, 0]<4>:ub r[a0.2, 1]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5, 32]<4>:ub r[a0.2,33]<32;8,4>:ub { NoDDChk } mov (8) r[a0.6, 288]<4>:ub r[a0.0,65]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 320]<4>:ub r[a0.0,97]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4,288]<2>:ub r[a0.1,65]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4,320]<2>:ub r[a0.1,97]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5,288]<4>:ub r[a0.2,65]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5,320]<4>:ub r[a0.2,97]<32;8,4>:ub { NoDDChk } send (1) null<1>:d r28 0xc 0x60A8018:ud send (1) null<1>:d r37 0xc 0x60A8018:ud // restore pointer add (4) a0.0<1>:uw r22.0<4;4,1>:w 1024:uw add (1) r28.1<1>:d r27.1<0;1,0>:d 8:d // Point to 2nd part add (1) r37.1<1>:d r27.1<0;1,0>:d 10:d // Point to 2nd part mov (8) r[a0.6, 0]<4>:ub r[a0.0, 1]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 32]<4>:ub r[a0.0,33]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4, 0]<2>:ub r[a0.1, 1]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4, 32]<2>:ub r[a0.1,33]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5, 0]<4>:ub r[a0.2, 1]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5, 32]<4>:ub r[a0.2,33]<32;8,4>:ub { NoDDChk } mov (8) r[a0.6, 288]<4>:ub r[a0.0,65]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 320]<4>:ub r[a0.0,97]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4,288]<2>:ub r[a0.1,65]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4,320]<2>:ub r[a0.1,97]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5,288]<4>:ub r[a0.2,65]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5,320]<4>:ub r[a0.2,97]<32;8,4>:ub { NoDDChk } send (1) null<1>:d r28 0xc 0x60A8018:ud send (1) null<1>:d r37 0xc 0x60A8018:ud // restore pointer add (4) a0.0<1>:uw r22.0<4;4,1>:w 1536:uw add (1) r28.1<1>:d r27.1<0;1,0>:d 12:d // Point to 2nd part add (1) r37.1<1>:d r27.1<0;1,0>:d 14:d // Point to 2nd part mov (8) r[a0.6, 0]<4>:ub r[a0.0, 1]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 32]<4>:ub r[a0.0,33]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4, 0]<2>:ub r[a0.1, 1]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4, 32]<2>:ub r[a0.1,33]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5, 0]<4>:ub r[a0.2, 1]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5, 32]<4>:ub r[a0.2,33]<32;8,4>:ub { NoDDChk } mov (8) r[a0.6, 288]<4>:ub r[a0.0,65]<32;8,4>:ub { NoDDClr } mov (8) r[a0.6, 320]<4>:ub r[a0.0,97]<32;8,4>:ub { NoDDClr } mov (16) r[a0.4,288]<2>:ub r[a0.1,65]<32;16,2>:ub { NoDDClr, NoDDChk } mov (16) r[a0.4,320]<2>:ub r[a0.1,97]<32;16,2>:ub { NoDDClr, NoDDChk } mov (8) r[a0.5,288]<4>:ub r[a0.2,65]<32;8,4>:ub { NoDDChk } mov (8) r[a0.5,320]<4>:ub r[a0.2,97]<32;8,4>:ub { NoDDChk } send (1) null<1>:d r28 0xc 0x60A8018:ud send (1) null<1>:d r37 0xc 0x60A8018:ud intel-driver-1.3.0/src/shaders/post_processing/gen8/Save_AVS_PL3.g8a000066400000000000000000000473651231401140700251170ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * Author: Zhao Yakui * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 84 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: Save_AVS_PL3.asm // // Save PL3 420 frame data block of size 16x16 // // To save 16x16 block (16x16 byte of Y and 8x8 byte of U and V each) we need 3 send instructions with one of size 16x16 and two of size 8x8. // ----------------- // | 16x16 Y | // | | // ----------------- // | 8x8 U | // --------- // | 8x8 V | // --------- //----------------------------------------------------------------- //The layout of data is as follows: //mMSGHDR0 : Y data header (16x16) //mubMSGPAYLOAD0 : Y data payload (8 GRFs) //mMSGHDR1 : U data header (8x8) //mubMSGPAYLOAD1 : U data payload (2 GRFs) //mMSGHDR2 : V data header (8x8) //mubMSGPAYLOAD2 : V data payload (2 GRFs) //------------------------------------------------------------------ // Module name: Save.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written .declare mudMSGPAYLOAD0 Base=r29.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD1 Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD2 Base=r47.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD3 Base=r56.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare muwMSGPAYLOAD0 Base=r29.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD1 Base=r38.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD2 Base=r47.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD3 Base=r56.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mubMSGPAYLOAD0 Base=r29.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD1 Base=r38.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD2 Base=r47.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD3 Base=r56.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD4 Base=r32.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD5 Base=r41.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD6 Base=r50.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD7 Base=r59.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ // At the save module we have all 8 address sub-registers available. // So we will use PING-PONG type of scheme to save the data using // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help // reduce dependency. - rT //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4. //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5). //Offsets are zero for buffer 0 and buffer 4. add (4) a0.0<1>:uw r22.0<4;4,1>:w 0:uw add (4) a0.4<1>:uw r22.0<4;4,1>:w 512:uw //Set up header for Y,U and V data mov (8) r28<1>:ud r27<8;8,1>:ud mov (8) r37<1>:ud r27<8;8,1>:ud mov (8) r46<1>:ud r27<8;8,1>:ud mov (2) r28.0<1>:d r7.0<2;2,1>:w { NoDDClr } //ORI Y (LUMA) = ORI shr (2) r37.0<1>:d r7.0<2;2,1>:w 1:w { NoDDClr } //H/V ORI U = H/V ORI/2 shr (2) r46.0<1>:d r7.0<2;2,1>:w 1:w { NoDDClr } //H/V ORI V = H/V ORI/2 mov (1) r28.2<1>:ud 0xF000F:ud { NoDDChk } // Y Block width and height (16x16) mov (1) r37.2<1>:ud 0x70007:ud { NoDDChk } // U Block width and height (8x8) mov (1) r46.2<1>:ud 0x70007:ud { NoDDChk } // V Block width and height (8x8) // Unscramble, and pack data directly to MRFs // Data 16x16 block is divided as - // --------- // | 0 | // --------- // | 1 | // --------- // | 2 | // --------- // | 3 | // --------- // All sub-blocks are of size 16x4 // 0: ubBUFFER_0 // 1: ubBUFFER_1, ubBUFFER_0+16 // 2: ubBUFFER_2 // 3: ubBUFFER_3, ubBUFFER_2+16 //Y Rounding, first add.sat (16) r[a0.1,0]<1>:uw r[a0.1,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,32]<1>:uw r[a0.1,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,64]<1>:uw r[a0.1,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,96]<1>:uw r[a0.1,96]<16;16,1>:uw 0x0080:uw // U rounding add.sat (8) r[a0.2,0]<2>:uw r[a0.2,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.2,64]<2>:uw r[a0.2,64]<16;8,2>:uw 0x0080:uw // V rounding add.sat (8) r[a0.0,0]<2>:uw r[a0.0,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.0,64]<2>:uw r[a0.0,64]<16;8,2>:uw 0x0080:uw add (4) a0.0<1>:uw r22.0<4;4,1>:w 1024:uw //Update Buffer 2 pointers //Y Rounding, second add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,64]<1>:uw r[a0.5,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,96]<1>:uw r[a0.5,96]<16;16,1>:uw 0x0080:uw // U rounding add.sat (8) r[a0.6,0]<2>:uw r[a0.6,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.6,64]<2>:uw r[a0.6,64]<16;8,2>:uw 0x0080:uw // V rounding add.sat (8) r[a0.4,0]<2>:uw r[a0.4,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.4,64]<2>:uw r[a0.4,64]<16;8,2>:uw 0x0080:uw add (4) a0.4<1>:uw r22.0<4;4,1>:w 1536:uw //Update Buffer 3 pointers //Y Rounding, third add.sat (16) r[a0.1,0]<1>:uw r[a0.1,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,32]<1>:uw r[a0.1,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,64]<1>:uw r[a0.1,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.1,96]<1>:uw r[a0.1,96]<16;16,1>:uw 0x0080:uw // U rounding add.sat (8) r[a0.2,0]<2>:uw r[a0.2,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.2,64]<2>:uw r[a0.2,64]<16;8,2>:uw 0x0080:uw // V rounding add.sat (8) r[a0.0,0]<2>:uw r[a0.0,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.0,64]<2>:uw r[a0.0,64]<16;8,2>:uw 0x0080:uw //Y Rounding, fourth add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,64]<1>:uw r[a0.5,64]<16;16,1>:uw 0x0080:uw add.sat (16) r[a0.5,96]<1>:uw r[a0.5,96]<16;16,1>:uw 0x0080:uw // U rounding add.sat (8) r[a0.6,0]<2>:uw r[a0.6,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.6,64]<2>:uw r[a0.6,64]<16;8,2>:uw 0x0080:uw // V rounding add.sat (8) r[a0.4,0]<2>:uw r[a0.4,0]<16;8,2>:uw 0x0080:uw add.sat (8) r[a0.4,64]<2>:uw r[a0.4,64]<16;8,2>:uw 0x0080:uw // restore the TOP and BOT pointers add (4) a0.0<1>:uw r22.0<4;4,1>:w 0:uw add (4) a0.4<1>:uw r22.0<4;4,1>:w 512:uw //Buffer 0 //Move Y to msg payload mov (16) mubMSGPAYLOAD0(0,0)<1> r[a0.1, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(0,16)<1> r[a0.1, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(1,0)<1> r[a0.1, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(1,16)<1> r[a0.1, 97]<32;16,2>:ub { NoDDChk } //Move U to msg payload mov (8) mubMSGPAYLOAD1(0,0)<1> r[a0.2, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD1(0,8)<1> r[a0.2, 65]<32;8,4>:ub { NoDDClr, NoDDChk } //Move V to msg payload mov (8) mubMSGPAYLOAD2(0,0)<1> r[a0.0, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD2(0,8)<1> r[a0.0, 65]<32;8,4>:ub { NoDDClr, NoDDChk } add (4) a0.0<1>:uw r22.0<4;4,1>:w 1024:uw //Update Buffer 2 pointers //Buffer 1 mov (16) mubMSGPAYLOAD0(2,0)<1> r[a0.5, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(2,16)<1> r[a0.5, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(3,0)<1> r[a0.5, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(3,16)<1> r[a0.5, 97]<32;16,2>:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(0,16)<1> r[a0.6, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(0,24)<1> r[a0.6, 65]<32;8,4>:ub { NoDDChk } mov (8) mubMSGPAYLOAD2(0,16)<1> r[a0.4, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(0,24)<1> r[a0.4, 65]<32;8,4>:ub { NoDDChk } add (4) a0.4<1>:uw r22.0<4;4,1>:w 1536:uw //Update Buffer 3 pointers //Buffer 2 mov (16) mubMSGPAYLOAD0(4,0)<1> r[a0.1, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(4,16)<1> r[a0.1, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(5,0)<1> r[a0.1, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(5,16)<1> r[a0.1, 97]<32;16,2>:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(1,0)<1> r[a0.2, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD1(1,8)<1> r[a0.2, 65]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(1,0)<1> r[a0.0, 1]<32;8,4>:ub { NoDDClr } mov (8) mubMSGPAYLOAD2(1,8)<1> r[a0.0, 65]<32;8,4>:ub { NoDDClr, NoDDChk } //Buffer 3 mov (16) mubMSGPAYLOAD0(6,0)<1> r[a0.5, 1]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(6,16)<1> r[a0.5, 33]<32;16,2>:ub { NoDDChk } mov (16) mubMSGPAYLOAD0(7,0)<1> r[a0.5, 65]<32;16,2>:ub { NoDDClr } mov (16) mubMSGPAYLOAD0(7,16)<1> r[a0.5, 97]<32;16,2>:ub { NoDDChk } mov (8) mubMSGPAYLOAD1(1,16)<1> r[a0.6, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD1(1,24)<1> r[a0.6, 65]<32;8,4>:ub { NoDDChk } mov (8) mubMSGPAYLOAD2(1,16)<1> r[a0.4, 1]<32;8,4>:ub { NoDDClr, NoDDChk } mov (8) mubMSGPAYLOAD2(1,24)<1> r[a0.4, 65]<32;8,4>:ub { NoDDChk } //=========================================================================== send (1) null<1>:d r28 0xc 0x120A8018:ud send (1) null<1>:d r37 0xc 0x60A8019:ud send (1) null<1>:d r46 0xc 0x60A801A:ud intel-driver-1.3.0/src/shaders/post_processing/gen8/Save_AVS_RGBX.g8a000066400000000000000000000574051231401140700252570ustar00rootroot00000000000000/* * Copyright 2000-2013 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * Authors: * Zhao Yakui */ // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: Save_AVS_RGBX.asm // // Save packed ARGB 444 frame data block of size 16x16 // // To save 16x16 block (64x16 byte layout for ARGB8888) we need 8 send instructions with 32x4 in each // -------- // | 0 | 1 | // | 2 | 3 | // | 4 | 5 | // | 6 | 7 | // --------- // the 8 32x4 block send is used // Module name: Save.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written .declare mudMSGPAYLOAD0 Base=r29.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD1 Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD2 Base=r47.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mudMSGPAYLOAD3 Base=r56.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare muwMSGPAYLOAD0 Base=r29.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD1 Base=r38.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD2 Base=r47.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare muwMSGPAYLOAD3 Base=r56.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mubMSGPAYLOAD0 Base=r29.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD1 Base=r38.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD2 Base=r47.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD3 Base=r56.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD4 Base=r32.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD5 Base=r41.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD6 Base=r50.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare mubMSGPAYLOAD7 Base=r59.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ // At the save module we have all 8 address sub-registers available. // So we will use PING-PONG type of scheme to save the data using // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help // reduce dependency. - rT //Internal LAYOUT:(RRGGBBAA) //Assign buffer channel order for Buffer 0123 in the order RGBA a0.3>A, a0.2>B, a0.1>G, a0.0>R // R = 0, G= 4, B = 8, A = 12. mov (4) acc0.0<1>:w 0x62EA:v add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw // if channel swap? // This means that it should be BGRA(B is the LSB) or RGBA // the internal format is always RGBA(MSB-A-B-G-R). and.nz.f0.0 null<1>:w r2.3<0;1,0>:uw 0x01:w //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4. //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5). //Offsets are zero for buffer 0 and buffer 4. add (4) a0.0<1>:uw r22.0<4;4,1>:w 0:uw // pointer swap (f0.0) mov (1) uwTemp0<1> a0.0<0;1,0>:uw (f0.0) mov (1) a0.0<1>:uw a0.2<0;1,0>:uw (f0.0) mov (1) a0.2<1>:uw uwTemp0<0;1,0> shl (1) r27.0<1>:d r7.0<0;1,0>:w 2:w { NoDDClr } // H. block origin need to be quadrupled mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin (1st quadrant) mov (1) r27.2<1>:ud 0x3001F:ud { NoDDChk } // Block width and height (32x4) mov (4) a0.4<1>:uw a0.0<4;4,1>:uw mov (8) r28<1>:ud r27<8;8,1>:ud mov (8) r37<1>:ud r27<8;8,1>:ud mov (8) r46<1>:ud r27<8;8,1>:ud mov (8) r55<1>:ud r27<8;8,1>:ud mov (8) r31<1>:ud r27<8;8,1>:ud mov (8) r40<1>:ud r27<8;8,1>:ud mov (8) r49<1>:ud r27<8;8,1>:ud mov (8) r58<1>:ud r27<8;8,1>:ud //Buffer 0/1 are written by using 4 32x4. add (1) r37.0<1>:d r27.0<0;1,0>:d 32:d add (1) r46.1<1>:d r27.1<0;1,0>:d 4:d add (1) r55.1<1>:d r27.1<0;1,0>:d 4:d add (1) r55.0<1>:d r27.0<0;1,0>:d 32:d // write Buf_0 to 1st quarter of four horizontal output blocks // Please note the scattered order of NODDCLR, NODDCHK flags. Since the sub-registers // of destination reg are not updated at one place and hence even flags are scattered. -rT /* for block 0 the left part of buffer 0 and 1 */ mov (8) mubMSGPAYLOAD0(0, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(1, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(0, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(1, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(2, 0)<4> r[a0.0, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 1)<4> r[a0.1, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 2)<4> r[a0.2, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(3, 0)<4> r[a0.0, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 1)<4> r[a0.1, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 2)<4> r[a0.2, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(2, 0)<4> r[a0.0, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 1)<4> r[a0.1, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 2)<4> r[a0.2, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(3, 0)<4> r[a0.0, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 1)<4> r[a0.1, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 2)<4> r[a0.2, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 3)<4> r2.31:ub /* For Buffer 0 */ send (16) null<1>:d r28 0xc 0x0A0A8018:ud send (16) null<1>:d r37 0xc 0x0A0A8018:ud add (4) a0.0<1>:uw a0.4<4;4,1>:uw 512:uw mov (8) mubMSGPAYLOAD2(0, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(1, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(0, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(1, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(2, 0)<4> r[a0.0, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 1)<4> r[a0.1, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 2)<4> r[a0.2, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(3, 0)<4> r[a0.0, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 1)<4> r[a0.1, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 2)<4> r[a0.2, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(2, 0)<4> r[a0.0, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 1)<4> r[a0.1, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 2)<4> r[a0.2, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(3, 0)<4> r[a0.0, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 1)<4> r[a0.1, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 2)<4> r[a0.2, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 3)<4> r2.31:ub // send Buffer 1 send (16) null<1>:d r46 0xc 0x0A0A8018:ud send (16) null<1>:d r55 0xc 0x0A0A8018:ud /* for Buffer 2/3 */ mov (8) r28<1>:ud r27<8;8,1>:ud mov (8) r37<1>:ud r27<8;8,1>:ud mov (8) r46<1>:ud r27<8;8,1>:ud mov (8) r55<1>:ud r27<8;8,1>:ud add (1) r28.1<1>:d r27.1<0;1,0>:d 8:d add (1) r37.0<1>:d r27.0<0;1,0>:d 32:d add (1) r37.1<1>:d r27.1<0;1,0>:d 8:d add (1) r46.1<1>:d r27.1<0;1,0>:d 12:d add (1) r55.1<1>:d r27.1<0;1,0>:d 12:d add (1) r55.0<1>:d r27.0<0;1,0>:d 32:d add (4) a0.0<1>:uw a0.4<4;4,1>:uw 1024:uw mov (8) mubMSGPAYLOAD0(0, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(1, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(0, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(1, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(2, 0)<4> r[a0.0, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 1)<4> r[a0.1, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 2)<4> r[a0.2, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD0(3, 0)<4> r[a0.0, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 1)<4> r[a0.1, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 2)<4> r[a0.2, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD0(3, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(2, 0)<4> r[a0.0, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 1)<4> r[a0.1, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 2)<4> r[a0.2, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD1(3, 0)<4> r[a0.0, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 1)<4> r[a0.1, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 2)<4> r[a0.2, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD1(3, 3)<4> r2.31:ub // Send Buffer 2 send (16) null<1>:d r28 0xc 0x0A0A8018:ud send (16) null<1>:d r37 0xc 0x0A0A8018:ud add (4) a0.0<1>:uw a0.4<4;4,1>:uw 1536:uw mov (8) mubMSGPAYLOAD2(0, 0)<4> r[a0.0, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 1)<4> r[a0.1, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 2)<4> r[a0.2, 1]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(1, 0)<4> r[a0.0, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 1)<4> r[a0.1, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 2)<4> r[a0.2, 33]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(0, 0)<4> r[a0.0, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 1)<4> r[a0.1, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 2)<4> r[a0.2, 17]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(0, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(1, 0)<4> r[a0.0, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 1)<4> r[a0.1, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 2)<4> r[a0.2, 49]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(1, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(2, 0)<4> r[a0.0, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 1)<4> r[a0.1, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 2)<4> r[a0.2, 65]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD2(3, 0)<4> r[a0.0, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 1)<4> r[a0.1, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 2)<4> r[a0.2, 97]<16;8,2>:ub mov (8) mubMSGPAYLOAD2(3, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(2, 0)<4> r[a0.0, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 1)<4> r[a0.1, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 2)<4> r[a0.2, 81]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(2, 3)<4> r2.31:ub mov (8) mubMSGPAYLOAD3(3, 0)<4> r[a0.0, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 1)<4> r[a0.1, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 2)<4> r[a0.2, 113]<16;8,2>:ub mov (8) mubMSGPAYLOAD3(3, 3)<4> r2.31:ub // send buffer 3 send (16) null<1>:d r46 0xc 0x0A0A8018:ud send (16) null<1>:d r55 0xc 0x0A0A8018:ud intel-driver-1.3.0/src/shaders/post_processing/gen8/Set_AVS_Buf_0123_BGRA.g8a000066400000000000000000000267711231401140700263300ustar00rootroot00000000000000/* * Copyright 2000-2013 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * Authors: Zhao Yakui */ // 7 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Module Name: Set_AVS_Buf_0123_BGRA.asm //Module Name: Set_Buf_0123_BGRA // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //AVS LAYOUT:(UUYYVVAA) //AVS RGBX LAYOUT (RRGGBBAA) //Assign buffer channel order for Buffer 0123 in the order AUYV a0.3>A, a0.2>U, a0.1>Y, a0.0>V // V = 8, Y= 0, U = 4, A = 12. // And a0.x is used as indirect-register for RGBX. R=a0.1, G=a0.2, B=a0.0 // B = 8, R= 0, G = 4, A = 12 mov (4) acc0.0<1>:w 0x6EA2:v add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw //OPT: wAVS_SU_SHUFFLE_PTR_0 and udAVS_SU_SHUFFLE_OFF_0 are sub-regs of same GRF. -rT //SU LAYOUT:(VYUAVYUA) //V = 4, Y = 2, U = 0, A = 6 //B = 4, G = 2, R = 0, A = 6 mov (4) acc0.0<1>:w 0x6204:v add (4) acc0.0<1>:w acc0<4;4,1>:w 64:uw shl (4) r18.0<1>:w acc0<4;4,1>:w 5:uw { NoDDClr } //Convert to BYTE address. //OFFSET: mov (1) r18.4<1>:ud 0x1000100:ud { NoDDChk } intel-driver-1.3.0/src/shaders/post_processing/gen8/Set_AVS_Buf_0123_PL2.g8a000066400000000000000000000263161231401140700262050ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 7 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Module Name: Set_AVS_Buf_0123_PL2.asm //Module Name: Set_Buf_0123_PL2 // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //AVS LAYOUT: (YYUUVVAA) //Assign buffer channel order for Buffer 0123 in the order AUYV a0.3>A, a0.2>U, a0.1>Y, a0.0>V //For PL2-AVS: V = 8, Y= 0, U = 4, A = 12. mov (4) acc0.0<1>:w 0x6EA2:v //Subtract 6 from 0,4,8,12 add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw //add 6 back shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw //Convert to BYTE address. //OPT: wAVS_SU_SHUFFLE_PTR_0 and udAVS_SU_SHUFFLE_OFF_0 are sub-regs of same GRF. -rT //SU LAYOUT:(YUVAYUVA) //V = 4, Y = 0, U = 2, A = 6 mov (4) acc0.0<1>:w 0x6204:v add (4) acc0.0<1>:w acc0<4;4,1>:w 64:uw shl (4) r18.0<1>:w acc0<4;4,1>:w 5:uw { NoDDClr } //Convert to BYTE address. //OFFSET: mov (1) r18.4<1>:ud 0x1000100:ud { NoDDChk } intel-driver-1.3.0/src/shaders/post_processing/gen8/Set_AVS_Buf_0123_PL3.g8a000066400000000000000000000266231231401140700262070ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 7 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Module Name: Set_AVS_Buf_0123_PL3.asm //Module Name: Set_Buf_0123_PL3 // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //AVS LAYOUT: (YYUUVVAA) //Assign buffer channel order for Buffer 0123 in the order AUYV a0.3>A, a0.2>U, a0.1>Y, a0.0>V //For PL3-AVS: V = 8, Y= 0, U = 4, A = 12. mov (4) acc0.0<1>:w 0x6EA2:v //Subtract 6 from 0,4,8,12 add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw //add 6 back shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw //Convert to BYTE address. //OPT: wAVS_SU_SHUFFLE_PTR_0 and udAVS_SU_SHUFFLE_OFF_0 are sub-regs of same GRF. -rT //SU LAYOUT:(YUVAYUVA) //V = 4, Y = 0, U = 2, A = 6 mov (4) acc0.0<1>:w 0x6204:v add (4) acc0.0<1>:w acc0<4;4,1>:w 64:uw shl (4) r18.0<1>:w acc0<4;4,1>:w 5:uw { NoDDClr } //Convert to BYTE address. //OFFSET: mov (1) r18.4<1>:ud 0x1000100:ud { NoDDChk } intel-driver-1.3.0/src/shaders/post_processing/gen8/Set_AVS_Buf_0123_VYUA.g8a000066400000000000000000000270431231401140700263720ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 7 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Module Name: Set_AVS_Buf_0123_VYUA.asm //Module Name: Set_Buf_0123_VYUA // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //AVS LAYOUT:(VVYYUUAA) //Assign buffer channel order for Buffer 0123 in the order AUYV a0.3>A, a0.2>U, a0.1>Y, a0.0>V // V = 0, Y= 4, U = 8, A = 12. //YCrCb or YCrCb_Swap returns the following data: //Cr is returned on R-channel. 0 //Y is returned on G channel. 4 //Cb is returned on B channel. 8 mov (4) acc0.0<1>:w 0x62EA:v //Subtract 6 from 0,4,8,12 add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw //add 6 back shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw //Convert to BYTE address. //OPT: wAVS_SU_SHUFFLE_PTR_0 and udAVS_SU_SHUFFLE_OFF_0 are sub-regs of same GRF. -rT //SU LAYOUT:(VYUAVYUA) //V = 0, Y = 2, U = 4, A = 6 mov (4) acc0.0<1>:w 0x6420:v add (4) acc0.0<1>:w acc0<4;4,1>:w 64:uw shl (4) r18.0<1>:w acc0<4;4,1>:w 5:uw { NoDDClr } //Convert to BYTE address. //OFFSET: mov (1) r18.4<1>:ud 0x1000100:ud { NoDDChk } intel-driver-1.3.0/src/shaders/post_processing/gen8/Set_Layer_0.g8a000066400000000000000000000366031231401140700251310ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // 18 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 #define MSG_AVS_SAMPLE 0x00000000 #define MSG_CONVOLE_SAMPLE 0x10000000 #define MSG_MINMAX_SAMPLE 0x20000000 #define MSG_MINMAXF_SAMPLE 0x30000000 #define MSG_ERODE_SAMPLE 0x40000000 #define MSG_DILATE_SAMPLE 0x50000000 #define MSG_BOOLCENT_SAMPLE 0x60000000 #define MSG_CENTROID_SAMPLE 0x70000000 #define MSG_IEF_BYPASS 0x08000000 #define MSG_IEF_ENABLE 0x00000000 //16x4 or 8x4 or 16x8 or 4x4 #define MSG_AVS_164 0x00000000 #define MSG_AVS_84 0x02000000 #define MSG_AVS_168 0x04000000 #define MSG_AVS_44 0x06000000 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc //Module name: Set_Layer_N.inc // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Used to generate LABELS at compile time. //definitions for Expand Mask .declare uwMask_Temp1 Base=r17.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF .declare ubMask_Temp1 Base=r17.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // 1 GRF .declare udMask_Temp1 Base=r17.0 ElementSize=4 Type=ud // 1 GRF .declare uwMask_Temp2 Base=r16.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF .declare ubMask_Temp2 Base=r16.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // 1 GRF .declare udMask_Temp2 Base=r16.0 ElementSize=4 Type=ud // 1 GRF .declare uwMask_Temp3 Base=r15.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF .declare ubMask_Temp3 Base=r15.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub // 1 GRF .declare udALPHA_MASK_REG Base=r21.0 ElementSize=4 Type=ud // 1 GRF .declare udALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=4 Type=ud // 1 GRF //Initialize mask reg to FFFF mov (16) uwALPHA_MASK_REG(0)<1> 0xFFFF:uw //Fast jump for - //LAYER0: we determine whether layer 0 is to be loaded and processed or not based // on block mask in module "Set_Layer_0" and store result in f0.1. // This flag is then directly used to while loading buf0-3 and colorfill. // (So flag f0.1 should not be changed from Set_Layer_0 till Colorfill) // //LAYER1-7: For all other layers, we compute whether layer is to be loaded and processed // based on block mask in module "Set_Layer_1-7" and store result in SKIP_LAYER // variable. // While Loading buf 4 and 5, we move SKIP_LAYER to f0.0 every time and use it // for Loading. // For processing though, we move SKIP_LAYER only once to f0.1 in module // "Set_Buf0_Buf4" and use f0.1 for deciding whether layer 1-7 (all 4 sub blocks) // is to be processed or not. // (So flag f0.1) should not be modififed from module "Set_Buf0_Buf4" till module // that processess sub-block 3). // //None of the above fast jumps, apply to CSC modules. We always perform CSC irrespective of mask. // //Example: (Without going into finer details) // Typical Combined kernel: // // (let var = decision whether to load/process that layer) // // Set_Layer_0 //f0.1 <- var // .. // Set_Layer_1 //f0.1 <- var, SKIP_LAYER <- var // .. // Load buf 0 //use f0.1 // Load buf 4 //f0.0 <- SKIP_LAYER // Load buf 1 //use f0.1 // Load buf 5 //f0.0 <- SKIP_LAYER // Load buf 2 //use f0.1 // Load buf 3 //use f0.1 // .. // .. // Colorfill // .. // Set_Buf0_Buf4 //f0.1 <- SKIP_LAYER // process0-4 //Use f0.1 // Load buf 4 // Set_Buf1_Buf5 // process1-5 // Load buf 5 // .. // Set_Layer_2 //f0.1 <-var, SKIP_LAYER <- var // .. // Set_Buf2_Buf4 // process2-4 // Load buf 4 // Set_Buf3_Buf5 // process3-5 // Load buf 5 // .. and (1) r24.2<1>:ub r2.2<0;1,0>:uw 3:uw //Copy all AVS Payload data // Setup Message Payload Header for 1st block of Media Sampler 8x8 (16x4 for IVB+) //currently the dx & dy is passed by Constant buffer (zero) mov (1) r25.0<1>:f r7.6<0;1,0>:f //NLAS dy mov (1) r25.6<1>:f r7.5<0;1,0>:f //NLAS dx mov (1) r25.4<1>:f r3.0<0;1,0>:f //Step X mov (1) r25.5<1>:f r4.0<0;1,0>:f //Step Y mov (1) r25.2<1>:f r6.0<0;1,0>:f //Orig X mov (1) r25.3<1>:f r5.0<0;1,0>:f //Orig Y mov (1) r25.7<1>:ud 0:ud add (1) r25.7<1>:ud r25.7<0;1,0>:ud MSG_AVS_SAMPLE + MSG_AVS_164 + MSG_IEF_BYPASS:ud //NLAS calculations for 2nd half of blocks of Media Sampler 8x8: // X(i) = X0 + dx*i + ddx*i*(i-1)/2 ==> X(8) = X0 + dx*8 +ddx*28 // dx(i)= dx(0) + ddx*i ==> dx(8)= dx + ddx*8 //OPTIMIZATION: fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY - are sub registers of same GRF. Use NODDCLR NODDCHK. -rT // Calculating X(8) mov (1) acc0.2<1>:f r6.0<0;1,0>:f mac (1) acc0.2<1>:f r3.0<0;1,0>:f 8.0:f mac (1) r23.2<1>:f r7.5<0;1,0>:f 28.0:f { NoDDClr } // Calculating Y(4) mul (1) r23.1<1>:f r4.0<0;1,0>:f 4.0:f { NoDDClr, NoDDChk } //dY*4 // Calculating dx(8) mov (1) acc0.4<1>:f r3.0<0;1,0>:f mac (1) r23.4<1>:f r7.5<0;1,0>:f 8.0:f { NoDDClr, NoDDChk } // Binding Index mov (1) r23.5<1>:ud 0:ud { NoDDChk } SKIP_LAYER_L0: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/VP_Setup.g8a000066400000000000000000000344371231401140700245330ustar00rootroot00000000000000/* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* * Copyright 2000-2011 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * Authors: Zhao Yakui */ // 326 // Total instruction count // 1 // Total kernel count // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // FileName: VP_Setup.asm // Author: Vivek Kumar // Description: Sets up all parameters for the Video Processing Kernel // Description: Includes all definitions explicit to Fast Composite. // End of common.inc //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Setup pointer to the inline parameter // Copy MSG HDR mov (8) r27.0<1>:ud r0.0<8;8,1>:ud // Initialize message payload header with R0 // Only one layer is enough //temp; remove it once unread msg warnings are resolved -vK mov (8) r25<1>:ud r0.0<8;8,1>:ud mov (8) r26<1>:ud r0.0<8;8,1>:ud // Calculate StepX for all layers and overwrite it on the ratio mul (8) r3.0<1>:f r3.0<8;8,1>:f r7.4<0;1,0>:f //StepX_ratio = StepX / VideoStepX //Normalised Ratio of Horizontal step size with main video for all layers now becomes //Normalised Horizontal step size for all layers // Calculate block origin for all layers and overwrite it on the frame origin mov (2) r8.5<1>:f r7.0<2;2,1>:w //Convert origin from word to float cmp.e.f0.0 (1) null<1>:d r2.26<0;1,0>:ub 1:uw shr (1) r17.0<1>:uw r2.2<0;1,0>:uw 0:uw and (1) r17.0<1>:uw r17.0<0;1,0>:uw 3:uw cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 1:uw (f0.1) jmpi (1) ROTATE_90_L0 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 2:uw (f0.1) jmpi (1) ROTATE_180_L0 cmp.e.f0.1 (1) null<1>:w r17.0<0;1,0>:uw 3:uw (f0.1) jmpi (1) ROTATE_270_L0 // rotate 0 degree ROTATE_0_L0: (-f0.0)mov (1) acc0.0<1>:f r6.0<0;1,0>:f (-f0.0)mac (1) r6.0<1>:f r3.0<0;1,0>:f r8.5<0;1,0>:f mov (1) acc0.0<1>:f r5.0<0;1,0>:f mac (1) r5.0<1>:f r4.0<0;1,0>:f r8.6<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L0 // rotate 90 degree ROTATE_90_L0: (-f0.0)mov (1) acc0.0<1>:f r6.0<0;1,0>:f (-f0.0)mac (1) r6.0<1>:f r3.0<0;1,0>:f r8.6<0;1,0>:f mov (1) r16.0<1>:f r2.0<0;1,0>:uw add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.0<1>:f r5.0<0;1,0>:f mac (1) r5.0<1>:f r4.0<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L0 // rotate 180 degree ROTATE_180_L0: (-f0.0)mov (1) r16.0<1>:f r2.0<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.5<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.0<1>:f r6.0<0;1,0>:f (-f0.0)mac (1) r6.0<1>:f r3.0<0;1,0>:f r17.0<0;1,0>:f mov (1) r16.0<1>:f r2.1<0;1,0>:uw add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f mov (1) acc0.0<1>:f r5.0<0;1,0>:f mac (1) r5.0<1>:f r4.0<0;1,0>:f r17.0<0;1,0>:f jmpi (1) END_SRC_BLOCK_ORIG_COMP_L0 // rotate 270 degree ROTATE_270_L0: (-f0.0)mov (1) r16.0<1>:f r2.1<0;1,0>:uw (-f0.0)add (1) r17.0<1>:f -r8.6<0;1,0>:f r16.0<0;1,0>:f (-f0.0)add (1) r17.0<1>:f r17.0<0;1,0>:f -16.0:f (-f0.0)mov (1) acc0.0<1>:f r6.0<0;1,0>:f (-f0.0)mac (1) r6.0<1>:f r3.0<0;1,0>:f r17.0<0;1,0>:f mov (1) acc0.0<1>:f r5.0<0;1,0>:f mac (1) r5.0<1>:f r4.0<0;1,0>:f r8.5<0;1,0>:f END_SRC_BLOCK_ORIG_COMP_L0: nop intel-driver-1.3.0/src/shaders/post_processing/gen8/YUV_to_RGB.g8a000066400000000000000000001142741231401140700247030ustar00rootroot00000000000000/* * Copyright 2000-2013 Intel Corporation All Rights Reserved * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * Authors: * Zhao Yakui */ // Module name: common.inc // // Common header file for all Video-Processing kernels // .default_execution_size (16) .default_register_type :ub .reg_count_total 128 .reg_count_payload 7 //========== Common constants ========== //========== Macros ========== //Fast Jump, For more details see "Set_Layer_N.asm" //========== Defines ==================== //========== Static Parameters (Common To All) ========== //r1 //r2 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //Color Pipe (IECP) parameters //ByteCopy //r4 // e.g. byte0 byte1 byte2 // YUYV 0 1 3 // YVYU 0 3 1 //========== Inline parameters (Common To All) =========== //============== Binding Index Table=========== //Common between DNDI and DNUV //================= Common Message Descriptor ===== // Message descriptor for thread spawning // Message Descriptors // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later) // 0000,0000,0000 // 0001(Spawn a root thread),0001 (Root thread spawn thread) // = 0x02000011 // Thread Spawner Message Descriptor // Message descriptor for atomic operation add // Message Descriptors // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later) // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add) // 0000,0000 (Binding table index, added later) // = 0x02000011 // Atomic Operation Add Message Descriptor // Message descriptor for dataport media write // Message Descriptors // = 000 0001 (min message len 1 - add later) 00000 (resp len 0) // 1 (header present 1) 0 1010 (media block write) 000000 // 00000000 (binding table index - set later) // = 0x020A8000 // Message Length defines // Response Length defines // Block Width and Height Size defines // Extended Message Descriptors // Common message descriptors: //===================== Math Function Control =================================== //============ Message Registers =============== // buf4 starts from r28 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f //=================== End of thread instruction =========================== //=====================Pointers Used===================================== //======================================================================= //r9-r17 // Define temp space for any usages // Common Buffers // temp space for rotation .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub // End of common.inc // Module name: YUV_to_RGB.asm // // Convert YUV to RGB, handle it by 16x4 block // // Description: Includes all definitions explicit to Fast Composite. //========== GRF partition ========== // r0 header : r0 (1 GRF) // Static parameters : r1 - r6 (6 GRFS) // Inline parameters : r7 - r8 (2 GRFs) // MSGSRC : r27 (1 GRF) //=================================== //Interface: //========== Static Parameters (Explicit To Fast Composite) ========== //r1 //CSC Set 0 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud //Constant alpha //r2 // Gen7 AVS WA // WiDi Definitions //Colorfill // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise. .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub //r3 //Normalised Ratio of Horizontal step size with main video for all layers //Normalised Ratio of Horizontal step size with main video for all layers becomes //Normalised Horizontal step size for all layers in VP_Setup.asm //r4 //Normalised Vertical step size for all layers //r5 //Normalised Vertical Frame Origin for all layers //r6 //Normalised Horizontal Frame Origin for all layers //========== Inline Parameters (Explicit To Fast Composite) ========== //Main video Step X //====================== Binding table (Explicit To Fast Composite)========================================= //Used by Interlaced Scaling Kernels //========== Sampler State Table Index (Explicit To Fast Composite)========== //Sampler Index for AVS/IEF messages //Sampler Index for SIMD16 sampler messages //============================================================================= .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f .declare bBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare bBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare bBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub .declare bBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub //Pointer to mask reg //r18 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF //r19 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF //r20 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r21 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF //r22 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use // NODDCLR, NODDCHK flags. -rT //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT //r23 //Lumakey //r24 //r25 //r26 //defines to generate LABELS during compile time. //Msg payload buffers; upto 4 full-size messages can be written //Unnecessary to use the MSGPayLoad, So it is temporiarily used for conversion of YUV->RGB .declare fBUFFER_R Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_G Base=r30.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_B Base=r32.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_Y Base=r36.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_U Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare fBUFFER_V Base=r40.0 ElementSize=4 SrcRegion=<8;8,1> Type=f .declare wTempR Base=r42.0 ElementSize=2 Type=w .declare wTempG Base=r44.0 ElementSize=2 Type=w .declare wTempB Base=r46.0 ElementSize=2 Type=w .declare ubTempR Base=r42.0 ElementSize=1 Type=ub .declare ubTempG Base=r44.0 ElementSize=1 Type=ub .declare ubTempB Base=r46.0 ElementSize=1 Type=ub // the r17 register (nTEMP0) is originally defined from "Common.inc" // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming .declare wTemp0 Base=r17.0 ElementSize=2 Type=uw //_SAVE_INC_ // NTSC standard // R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255)) // G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255)) // B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255)) // ITU-R conversion, Now we are using ITU-R conversion // R = clip( Y + 1.402*(Cr-128)) // ITU-R // G = clip( Y - 0.344*(Cb-128) - 0.714*(Cr-128)) // B = clip( Y + 1.772*(Cb-128)) // At the save module we have all 8 address sub-registers available. // So we will use PING-PONG type of scheme to save the data using // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help // reduce dependency. - rT //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4. //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5). //Offsets are zero for buffer 0 and buffer 4. //Y/U/V is also stored as R/G/B for the internal purpose //for BUFFER_0 mov (4) a0.0<1>:uw r22.0<4;4,1>:uw //the first line in the block 0 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 17]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,1]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,1]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,1]<2>:ub ubTempB(0, 0)<32;8,4> //the second line in the block 0 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 49]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,33]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,33]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,33]<2>:ub ubTempB(0, 0)<32;8,4> //the third line in the block 0 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 81]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,65]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,65]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,65]<2>:ub ubTempB(0, 0)<32;8,4> //the fourth line in the block 0 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 113]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,97]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,97]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,97]<2>:ub ubTempB(0, 0)<32;8,4> //for BUFFER_1 add (4) a0.0<1>:uw r22.0<4;4,1>:uw 512:uw //the first line in the block 1 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 17]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,1]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,1]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,1]<2>:ub ubTempB(0, 0)<32;8,4> //the second line in the block 1 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 49]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,33]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,33]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,33]<2>:ub ubTempB(0, 0)<32;8,4> //the third line in the block 1 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 81]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,65]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,65]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,65]<2>:ub ubTempB(0, 0)<32;8,4> //the fourth line in the block 1 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 113]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,97]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,97]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,97]<2>:ub ubTempB(0, 0)<32;8,4> //for BUFFER_2 add (4) a0.0<1>:uw r22.0<4;4,1>:uw 1024:uw //the first line in the block 2 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 17]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,1]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,1]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,1]<2>:ub ubTempB(0, 0)<32;8,4> //the second line in the block 2 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 49]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,33]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,33]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,33]<2>:ub ubTempB(0, 0)<32;8,4> //the third line in the block 2 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 81]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,65]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,65]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,65]<2>:ub ubTempB(0, 0)<32;8,4> //the fourth line in the block 2 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 113]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,97]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,97]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,97]<2>:ub ubTempB(0, 0)<32;8,4> //for BUFFER_3 add (4) a0.0<1>:uw r22.0<4;4,1>:uw 1536:uw //the first line in the block 3 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 1]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 17]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 1]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 17]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 1]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 17]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,1]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,1]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,1]<2>:ub ubTempB(0, 0)<32;8,4> //the second line in the block 3 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 33]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 49]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 33]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 49]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 33]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 49]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,33]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,33]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,33]<2>:ub ubTempB(0, 0)<32;8,4> //the third line in the block 3 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 65]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 81]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 65]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 81]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 65]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 81]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,65]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,65]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,65]<2>:ub ubTempB(0, 0)<32;8,4> //the fourth line in the block 3 mov (8) fBUFFER_Y(0, 0)<1> r[a0.1, 97]<16;8,2>:ub mov (8) fBUFFER_Y(1, 0)<1> r[a0.1, 113]<16;8,2>:ub mov (8) fBUFFER_U(0, 0)<1> r[a0.2, 97]<16;8,2>:ub mov (8) fBUFFER_U(1, 0)<1> r[a0.2, 113]<16;8,2>:ub mov (8) fBUFFER_V(0, 0)<1> r[a0.0, 97]<16;8,2>:ub mov (8) fBUFFER_V(1, 0)<1> r[a0.0, 113]<16;8,2>:ub add (16) fBUFFER_U(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> -128.0f add (16) fBUFFER_V(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -128.0f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_R(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 1.402f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (8) acc0.0<1>:f fBUFFER_U(0, 0)<8;8,1> -0.344f mac (8) acc1.0<1>:f fBUFFER_U(1, 0)<8;8,1> -0.344f mac (16) fBUFFER_G(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> -0.714f mov (16) acc0.0<1>:f fBUFFER_Y(0, 0)<8;8,1> mac (16) fBUFFER_B(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 1.772f mul.sat (16) fBUFFER_Y(0, 0)<1> fBUFFER_R(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_U(0, 0)<1> fBUFFER_G(0, 0)<8;8,1> 0.0039216f mul.sat (16) fBUFFER_V(0, 0)<1> fBUFFER_B(0, 0)<8;8,1> 0.0039216f mul (16) fBUFFER_R(0, 0)<1> fBUFFER_Y(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_G(0, 0)<1> fBUFFER_U(0, 0)<8;8,1> 255.0f mul (16) fBUFFER_B(0, 0)<1> fBUFFER_V(0, 0)<8;8,1> 255.0f mov (16) wTempR(0, 0)<2> fBUFFER_R(0, 0)<8;8,1> mov (16) wTempG(0, 0)<2> fBUFFER_G(0, 0)<8;8,1> mov (16) wTempB(0, 0)<2> fBUFFER_B(0, 0)<8;8,1> mov (16) r[a0.1,97]<2>:ub ubTempR(0, 0)<32;8,4> mov (16) r[a0.2,97]<2>:ub ubTempG(0, 0)<32;8,4> mov (16) r[a0.0,97]<2>:ub ubTempB(0, 0)<32;8,4> intel-driver-1.3.0/src/shaders/post_processing/gen8/pa_to_pa.asm000066400000000000000000000004761231401140700247050ustar00rootroot00000000000000// Module name: AVS .kernel YUY2_TO_NV12 .code #include "VP_Setup.g8a" #include "Set_Layer_0.g8a" #include "Set_AVS_Buf_0123_VYUA.g8a" #include "PA_AVS_Buf_0.g8a" #include "PA_AVS_Buf_1.g8a" #include "PA_AVS_Buf_2.g8a" #include "PA_AVS_Buf_3.g8a" #include "Save_AVS_PA.g8a" #include "EOT.g8a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen8/pa_to_pa.g8b000066400000000000000000000357611231401140700246120ustar00rootroot00000000000000 { 0x00600001, 0x23600208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400208, 0x008d0000, 0x00000000 }, { 0x00600041, 0x20603ae8, 0x3a8d0060, 0x000000f0 }, { 0x00200001, 0x21141ae8, 0x004500e0, 0x00000000 }, { 0x01000010, 0x20002220, 0x1600005a, 0x00010001 }, { 0x00000008, 0x22201248, 0x16000044, 0x00000000 }, { 0x00000005, 0x22201248, 0x16000220, 0x00030003 }, { 0x01000010, 0x20001261, 0x16000220, 0x00010001 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000090 }, { 0x01000010, 0x20001261, 0x16000220, 0x00020002 }, { 0x00010020, 0x34000005, 0x0e001400, 0x000000f0 }, { 0x01000010, 0x20001261, 0x16000220, 0x00030003 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000180 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000114 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000118 }, { 0x00000020, 0x34000004, 0x0e001400, 0x000001a0 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000118 }, { 0x00000001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000120 }, { 0x00110001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000070 }, { 0x00110001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a01648, 0x10000000, 0xffffffff }, { 0x00000005, 0x23021288, 0x16000044, 0x00030003 }, { 0x00000001, 0x23203ae8, 0x000000f8, 0x00000000 }, { 0x00000001, 0x23383ae8, 0x000000f4, 0x00000000 }, { 0x00000001, 0x23303ae8, 0x00000060, 0x00000000 }, { 0x00000001, 0x23343ae8, 0x00000080, 0x00000000 }, { 0x00000001, 0x23283ae8, 0x000000c0, 0x00000000 }, { 0x00000001, 0x232c3ae8, 0x000000a0, 0x00000000 }, { 0x00000001, 0x233c0608, 0x00000000, 0x00000000 }, { 0x00000040, 0x233c0208, 0x0600033c, 0x08000000 }, { 0x00000001, 0x24083ae0, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24083ae0, 0x3e000060, 0x41000000 }, { 0x00000248, 0x22e83ae8, 0x3e0000f4, 0x41e00000 }, { 0x00000641, 0x22e43ae8, 0x3e000080, 0x40800000 }, { 0x00000001, 0x24103ae0, 0x00000060, 0x00000000 }, { 0x00000648, 0x22f03ae8, 0x3e0000f4, 0x41000000 }, { 0x00000401, 0x22f40608, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x24003660, 0x30000000, 0x000062ea }, { 0x00400040, 0x24001860, 0x16690400, 0x00460046 }, { 0x00400009, 0x22c01868, 0x16690400, 0x00050005 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006420 }, { 0x00400040, 0x24001860, 0x16690400, 0x00400040 }, { 0x00400209, 0x22401868, 0x16690400, 0x00050005 }, { 0x00000401, 0x22500608, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x28002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000001 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2a002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000002 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2c002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000003 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2e002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22082260, 0x1669005c, 0x03a003a0 }, { 0x00000209, 0x23601a28, 0x1e0000e0, 0x00010001 }, { 0x00000601, 0x23641a28, 0x000000e2, 0x00000000 }, { 0x00000401, 0x23680608, 0x00000000, 0x0001001f }, { 0x80400040, 0xc0001248, 0x168a8000, 0x00800080 }, { 0x80400040, 0xc0201248, 0x168a8020, 0x00800080 }, { 0x80400040, 0xc0401248, 0x168a8040, 0x00800080 }, { 0x80400040, 0xc0601248, 0x168a8060, 0x00800080 }, { 0x80600040, 0xa2001248, 0x168d8200, 0x00800080 }, { 0x80600040, 0xa2201248, 0x168d8220, 0x00800080 }, { 0x80600040, 0xa2401248, 0x168d8240, 0x00800080 }, { 0x80600040, 0xa2601248, 0x168d8260, 0x00800080 }, { 0x80400040, 0xc4001248, 0x168a8400, 0x00800080 }, { 0x80400040, 0xc4201248, 0x168a8420, 0x00800080 }, { 0x80400040, 0xc4401248, 0x168a8440, 0x00800080 }, { 0x80400040, 0xc4601248, 0x168a8460, 0x00800080 }, { 0x80400040, 0xc0101248, 0x168a8010, 0x00800080 }, { 0x80400040, 0xc0301248, 0x168a8030, 0x00800080 }, { 0x80400040, 0xc0501248, 0x168a8050, 0x00800080 }, { 0x80400040, 0xc0701248, 0x168a8070, 0x00800080 }, { 0x80600040, 0xa2101248, 0x168d8210, 0x00800080 }, { 0x80600040, 0xa2301248, 0x168d8230, 0x00800080 }, { 0x80600040, 0xa2501248, 0x168d8250, 0x00800080 }, { 0x80600040, 0xa2701248, 0x168d8270, 0x00800080 }, { 0x80400040, 0xc4101248, 0x168a8410, 0x00800080 }, { 0x80400040, 0xc4301248, 0x168a8430, 0x00800080 }, { 0x80400040, 0xc4501248, 0x168a8450, 0x00800080 }, { 0x80400040, 0xc4701248, 0x168a8470, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x02000200 }, { 0x80400040, 0xc0001248, 0x168a8000, 0x00800080 }, { 0x80400040, 0xc0201248, 0x168a8020, 0x00800080 }, { 0x80400040, 0xc0401248, 0x168a8040, 0x00800080 }, { 0x80400040, 0xc0601248, 0x168a8060, 0x00800080 }, { 0x80600040, 0xa2001248, 0x168d8200, 0x00800080 }, { 0x80600040, 0xa2201248, 0x168d8220, 0x00800080 }, { 0x80600040, 0xa2401248, 0x168d8240, 0x00800080 }, { 0x80600040, 0xa2601248, 0x168d8260, 0x00800080 }, { 0x80400040, 0xc4001248, 0x168a8400, 0x00800080 }, { 0x80400040, 0xc4201248, 0x168a8420, 0x00800080 }, { 0x80400040, 0xc4401248, 0x168a8440, 0x00800080 }, { 0x80400040, 0xc4601248, 0x168a8460, 0x00800080 }, { 0x80400040, 0xc0101248, 0x168a8010, 0x00800080 }, { 0x80400040, 0xc0301248, 0x168a8030, 0x00800080 }, { 0x80400040, 0xc0501248, 0x168a8050, 0x00800080 }, { 0x80400040, 0xc0701248, 0x168a8070, 0x00800080 }, { 0x80600040, 0xa2101248, 0x168d8210, 0x00800080 }, { 0x80600040, 0xa2301248, 0x168d8230, 0x00800080 }, { 0x80600040, 0xa2501248, 0x168d8250, 0x00800080 }, { 0x80600040, 0xa2701248, 0x168d8270, 0x00800080 }, { 0x80400040, 0xc4101248, 0x168a8410, 0x00800080 }, { 0x80400040, 0xc4301248, 0x168a8430, 0x00800080 }, { 0x80400040, 0xc4501248, 0x168a8450, 0x00800080 }, { 0x80400040, 0xc4701248, 0x168a8470, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80400040, 0xc0001248, 0x168a8000, 0x00800080 }, { 0x80400040, 0xc0201248, 0x168a8020, 0x00800080 }, { 0x80400040, 0xc0401248, 0x168a8040, 0x00800080 }, { 0x80400040, 0xc0601248, 0x168a8060, 0x00800080 }, { 0x80600040, 0xa2001248, 0x168d8200, 0x00800080 }, { 0x80600040, 0xa2201248, 0x168d8220, 0x00800080 }, { 0x80600040, 0xa2401248, 0x168d8240, 0x00800080 }, { 0x80600040, 0xa2601248, 0x168d8260, 0x00800080 }, { 0x80400040, 0xc4001248, 0x168a8400, 0x00800080 }, { 0x80400040, 0xc4201248, 0x168a8420, 0x00800080 }, { 0x80400040, 0xc4401248, 0x168a8440, 0x00800080 }, { 0x80400040, 0xc4601248, 0x168a8460, 0x00800080 }, { 0x80400040, 0xc0101248, 0x168a8010, 0x00800080 }, { 0x80400040, 0xc0301248, 0x168a8030, 0x00800080 }, { 0x80400040, 0xc0501248, 0x168a8050, 0x00800080 }, { 0x80400040, 0xc0701248, 0x168a8070, 0x00800080 }, { 0x80600040, 0xa2101248, 0x168d8210, 0x00800080 }, { 0x80600040, 0xa2301248, 0x168d8230, 0x00800080 }, { 0x80600040, 0xa2501248, 0x168d8250, 0x00800080 }, { 0x80600040, 0xa2701248, 0x168d8270, 0x00800080 }, { 0x80400040, 0xc4101248, 0x168a8410, 0x00800080 }, { 0x80400040, 0xc4301248, 0x168a8430, 0x00800080 }, { 0x80400040, 0xc4501248, 0x168a8450, 0x00800080 }, { 0x80400040, 0xc4701248, 0x168a8470, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x06000600 }, { 0x80400040, 0xc0001248, 0x168a8000, 0x00800080 }, { 0x80400040, 0xc0201248, 0x168a8020, 0x00800080 }, { 0x80400040, 0xc0401248, 0x168a8040, 0x00800080 }, { 0x80400040, 0xc0601248, 0x168a8060, 0x00800080 }, { 0x80600040, 0xa2001248, 0x168d8200, 0x00800080 }, { 0x80600040, 0xa2201248, 0x168d8220, 0x00800080 }, { 0x80600040, 0xa2401248, 0x168d8240, 0x00800080 }, { 0x80600040, 0xa2601248, 0x168d8260, 0x00800080 }, { 0x80400040, 0xc4001248, 0x168a8400, 0x00800080 }, { 0x80400040, 0xc4201248, 0x168a8420, 0x00800080 }, { 0x80400040, 0xc4401248, 0x168a8440, 0x00800080 }, { 0x80400040, 0xc4601248, 0x168a8460, 0x00800080 }, { 0x80400040, 0xc0101248, 0x168a8010, 0x00800080 }, { 0x80400040, 0xc0301248, 0x168a8030, 0x00800080 }, { 0x80400040, 0xc0501248, 0x168a8050, 0x00800080 }, { 0x80400040, 0xc0701248, 0x168a8070, 0x00800080 }, { 0x80600040, 0xa2101248, 0x168d8210, 0x00800080 }, { 0x80600040, 0xa2301248, 0x168d8230, 0x00800080 }, { 0x80600040, 0xa2501248, 0x168d8250, 0x00800080 }, { 0x80600040, 0xa2701248, 0x168d8270, 0x00800080 }, { 0x80400040, 0xc4101248, 0x168a8410, 0x00800080 }, { 0x80400040, 0xc4301248, 0x168a8430, 0x00800080 }, { 0x80400040, 0xc4501248, 0x168a8450, 0x00800080 }, { 0x80400040, 0xc4701248, 0x168a8470, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x08000800 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00600001, 0x23800208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00208, 0x008d0360, 0x00000000 }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x00000002 }, { 0x00600201, 0xec002288, 0x00cf8001, 0x00000000 }, { 0x00600201, 0xec202288, 0x00cf8021, 0x00000000 }, { 0x00800601, 0xc8002288, 0x00d28201, 0x00000000 }, { 0x00800601, 0xc8202288, 0x00d28221, 0x00000000 }, { 0x00600401, 0xea002288, 0x00cf8401, 0x00000000 }, { 0x00600401, 0xea202288, 0x00cf8421, 0x00000000 }, { 0x00600201, 0xed202288, 0x00cf8041, 0x00000000 }, { 0x00600201, 0xed402288, 0x00cf8061, 0x00000000 }, { 0x00800601, 0xc9202288, 0x00d28241, 0x00000000 }, { 0x00800601, 0xc9402288, 0x00d28261, 0x00000000 }, { 0x00600401, 0xeb202288, 0x00cf8441, 0x00000000 }, { 0x00600401, 0xeb402288, 0x00cf8461, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x060a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8018 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x02000200 }, { 0x00000040, 0x23840a28, 0x0e000364, 0x00000004 }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x00000006 }, { 0x00600201, 0xec002288, 0x00cf8001, 0x00000000 }, { 0x00600201, 0xec202288, 0x00cf8021, 0x00000000 }, { 0x00800601, 0xc8002288, 0x00d28201, 0x00000000 }, { 0x00800601, 0xc8202288, 0x00d28221, 0x00000000 }, { 0x00600401, 0xea002288, 0x00cf8401, 0x00000000 }, { 0x00600401, 0xea202288, 0x00cf8421, 0x00000000 }, { 0x00600201, 0xed202288, 0x00cf8041, 0x00000000 }, { 0x00600201, 0xed402288, 0x00cf8061, 0x00000000 }, { 0x00800601, 0xc9202288, 0x00d28241, 0x00000000 }, { 0x00800601, 0xc9402288, 0x00d28261, 0x00000000 }, { 0x00600401, 0xeb202288, 0x00cf8441, 0x00000000 }, { 0x00600401, 0xeb402288, 0x00cf8461, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x060a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8018 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x00000040, 0x23840a28, 0x0e000364, 0x00000008 }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x0000000a }, { 0x00600201, 0xec002288, 0x00cf8001, 0x00000000 }, { 0x00600201, 0xec202288, 0x00cf8021, 0x00000000 }, { 0x00800601, 0xc8002288, 0x00d28201, 0x00000000 }, { 0x00800601, 0xc8202288, 0x00d28221, 0x00000000 }, { 0x00600401, 0xea002288, 0x00cf8401, 0x00000000 }, { 0x00600401, 0xea202288, 0x00cf8421, 0x00000000 }, { 0x00600201, 0xed202288, 0x00cf8041, 0x00000000 }, { 0x00600201, 0xed402288, 0x00cf8061, 0x00000000 }, { 0x00800601, 0xc9202288, 0x00d28241, 0x00000000 }, { 0x00800601, 0xc9402288, 0x00d28261, 0x00000000 }, { 0x00600401, 0xeb202288, 0x00cf8441, 0x00000000 }, { 0x00600401, 0xeb402288, 0x00cf8461, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x060a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8018 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x06000600 }, { 0x00000040, 0x23840a28, 0x0e000364, 0x0000000c }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x0000000e }, { 0x00600201, 0xec002288, 0x00cf8001, 0x00000000 }, { 0x00600201, 0xec202288, 0x00cf8021, 0x00000000 }, { 0x00800601, 0xc8002288, 0x00d28201, 0x00000000 }, { 0x00800601, 0xc8202288, 0x00d28221, 0x00000000 }, { 0x00600401, 0xea002288, 0x00cf8401, 0x00000000 }, { 0x00600401, 0xea202288, 0x00cf8421, 0x00000000 }, { 0x00600201, 0xed202288, 0x00cf8041, 0x00000000 }, { 0x00600201, 0xed402288, 0x00cf8061, 0x00000000 }, { 0x00800601, 0xc9202288, 0x00d28241, 0x00000000 }, { 0x00800601, 0xc9402288, 0x00d28261, 0x00000000 }, { 0x00600401, 0xeb202288, 0x00cf8441, 0x00000000 }, { 0x00600401, 0xeb402288, 0x00cf8461, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x060a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8018 }, { 0x00600001, 0x2fe00208, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20002220, 0x0e000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/pa_to_pl2.asm000066400000000000000000000005121231401140700247710ustar00rootroot00000000000000// Module name: AVS .kernel YUY2_TO_NV12 .code #include "VP_Setup.g8a" #include "Set_Layer_0.g8a" #include "Set_AVS_Buf_0123_VYUA.g8a" #include "PA_AVS_Buf_0.g8a" #include "PA_AVS_Buf_1.g8a" #include "PA_AVS_Buf_2.g8a" #include "PA_AVS_Buf_3.g8a" #include "Save_AVS_NV12.g8a" #include "EOT.g8a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen8/pa_to_pl2.g8b000066400000000000000000000312641231401140700247010ustar00rootroot00000000000000 { 0x00600001, 0x23600208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400208, 0x008d0000, 0x00000000 }, { 0x00600041, 0x20603ae8, 0x3a8d0060, 0x000000f0 }, { 0x00200001, 0x21141ae8, 0x004500e0, 0x00000000 }, { 0x01000010, 0x20002220, 0x1600005a, 0x00010001 }, { 0x00000008, 0x22201248, 0x16000044, 0x00000000 }, { 0x00000005, 0x22201248, 0x16000220, 0x00030003 }, { 0x01000010, 0x20001261, 0x16000220, 0x00010001 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000090 }, { 0x01000010, 0x20001261, 0x16000220, 0x00020002 }, { 0x00010020, 0x34000005, 0x0e001400, 0x000000f0 }, { 0x01000010, 0x20001261, 0x16000220, 0x00030003 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000180 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000114 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000118 }, { 0x00000020, 0x34000004, 0x0e001400, 0x000001a0 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000118 }, { 0x00000001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000120 }, { 0x00110001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000070 }, { 0x00110001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a01648, 0x10000000, 0xffffffff }, { 0x00000005, 0x23021288, 0x16000044, 0x00030003 }, { 0x00000001, 0x23203ae8, 0x000000f8, 0x00000000 }, { 0x00000001, 0x23383ae8, 0x000000f4, 0x00000000 }, { 0x00000001, 0x23303ae8, 0x00000060, 0x00000000 }, { 0x00000001, 0x23343ae8, 0x00000080, 0x00000000 }, { 0x00000001, 0x23283ae8, 0x000000c0, 0x00000000 }, { 0x00000001, 0x232c3ae8, 0x000000a0, 0x00000000 }, { 0x00000001, 0x233c0608, 0x00000000, 0x00000000 }, { 0x00000040, 0x233c0208, 0x0600033c, 0x08000000 }, { 0x00000001, 0x24083ae0, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24083ae0, 0x3e000060, 0x41000000 }, { 0x00000248, 0x22e83ae8, 0x3e0000f4, 0x41e00000 }, { 0x00000641, 0x22e43ae8, 0x3e000080, 0x40800000 }, { 0x00000001, 0x24103ae0, 0x00000060, 0x00000000 }, { 0x00000648, 0x22f03ae8, 0x3e0000f4, 0x41000000 }, { 0x00000401, 0x22f40608, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x24003660, 0x30000000, 0x000062ea }, { 0x00400040, 0x24001860, 0x16690400, 0x00460046 }, { 0x00400009, 0x22c01868, 0x16690400, 0x00050005 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006420 }, { 0x00400040, 0x24001860, 0x16690400, 0x00400040 }, { 0x00400209, 0x22401868, 0x16690400, 0x00050005 }, { 0x00000401, 0x22500608, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x28002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000001 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2a002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000002 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2c002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000003 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2e002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00600001, 0x23800208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00208, 0x008d0360, 0x00000000 }, { 0x00200201, 0x23801a28, 0x004500e0, 0x00000000 }, { 0x00000201, 0x24a01a28, 0x000000e0, 0x00000000 }, { 0x00000608, 0x24a41a28, 0x1e0000e2, 0x00010001 }, { 0x00000401, 0x23880608, 0x00000000, 0x000f000f }, { 0x00000401, 0x24a80608, 0x00000000, 0x0007000f }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8400, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8420, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8440, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8460, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc4001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xc4401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8000, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8020, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8040, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8060, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc0001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8c00, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8c20, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8c40, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8c60, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xcc001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xcc401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8800, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8820, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8840, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8860, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc8001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc8401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8400, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8420, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8440, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8460, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc4001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xc4401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8000, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8020, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8040, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8060, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc0001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8c00, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8c20, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8c40, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8c60, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xcc001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xcc401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8800, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8820, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8840, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8860, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc8001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc8401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00800201, 0x23a02288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x23b02288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x23c02288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x23d02288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x44c02288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x44d02288, 0x00cf8441, 0x00000000 }, { 0x00600601, 0x44c12288, 0x00cf8001, 0x00000000 }, { 0x00600401, 0x44d12288, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x00800201, 0x23e02288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x23f02288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24002288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24102288, 0x00d28a61, 0x00000000 }, { 0x00600201, 0x44e02288, 0x00cf8c01, 0x00000000 }, { 0x00600601, 0x44f02288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x44e12288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x44f12288, 0x00cf8841, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x00800201, 0x24202288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x24302288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x24402288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x24502288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x45002288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x45102288, 0x00cf8441, 0x00000000 }, { 0x00600601, 0x45012288, 0x00cf8001, 0x00000000 }, { 0x00600401, 0x45112288, 0x00cf8041, 0x00000000 }, { 0x00800201, 0x24602288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x24702288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24802288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24902288, 0x00d28a61, 0x00000000 }, { 0x00600201, 0x45202288, 0x00cf8c01, 0x00000000 }, { 0x00600601, 0x45302288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x45212288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x45312288, 0x00cf8841, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x120a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00208, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20002220, 0x0e000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/pa_to_pl3.asm000066400000000000000000000005111231401140700247710ustar00rootroot00000000000000// Module name: AVS .kernel YUY2_TO_NV12 .code #include "VP_Setup.g8a" #include "Set_Layer_0.g8a" #include "Set_AVS_Buf_0123_VYUA.g8a" #include "PA_AVS_Buf_0.g8a" #include "PA_AVS_Buf_1.g8a" #include "PA_AVS_Buf_2.g8a" #include "PA_AVS_Buf_3.g8a" #include "Save_AVS_PL3.g8a" #include "EOT.g8a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen8/pa_to_pl3.g8b000066400000000000000000000242331231401140700247000ustar00rootroot00000000000000 { 0x00600001, 0x23600208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400208, 0x008d0000, 0x00000000 }, { 0x00600041, 0x20603ae8, 0x3a8d0060, 0x000000f0 }, { 0x00200001, 0x21141ae8, 0x004500e0, 0x00000000 }, { 0x01000010, 0x20002220, 0x1600005a, 0x00010001 }, { 0x00000008, 0x22201248, 0x16000044, 0x00000000 }, { 0x00000005, 0x22201248, 0x16000220, 0x00030003 }, { 0x01000010, 0x20001261, 0x16000220, 0x00010001 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000090 }, { 0x01000010, 0x20001261, 0x16000220, 0x00020002 }, { 0x00010020, 0x34000005, 0x0e001400, 0x000000f0 }, { 0x01000010, 0x20001261, 0x16000220, 0x00030003 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000180 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000114 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000118 }, { 0x00000020, 0x34000004, 0x0e001400, 0x000001a0 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000118 }, { 0x00000001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000120 }, { 0x00110001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000070 }, { 0x00110001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a01648, 0x10000000, 0xffffffff }, { 0x00000005, 0x23021288, 0x16000044, 0x00030003 }, { 0x00000001, 0x23203ae8, 0x000000f8, 0x00000000 }, { 0x00000001, 0x23383ae8, 0x000000f4, 0x00000000 }, { 0x00000001, 0x23303ae8, 0x00000060, 0x00000000 }, { 0x00000001, 0x23343ae8, 0x00000080, 0x00000000 }, { 0x00000001, 0x23283ae8, 0x000000c0, 0x00000000 }, { 0x00000001, 0x232c3ae8, 0x000000a0, 0x00000000 }, { 0x00000001, 0x233c0608, 0x00000000, 0x00000000 }, { 0x00000040, 0x233c0208, 0x0600033c, 0x08000000 }, { 0x00000001, 0x24083ae0, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24083ae0, 0x3e000060, 0x41000000 }, { 0x00000248, 0x22e83ae8, 0x3e0000f4, 0x41e00000 }, { 0x00000641, 0x22e43ae8, 0x3e000080, 0x40800000 }, { 0x00000001, 0x24103ae0, 0x00000060, 0x00000000 }, { 0x00000648, 0x22f03ae8, 0x3e0000f4, 0x41000000 }, { 0x00000401, 0x22f40608, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x24003660, 0x30000000, 0x000062ea }, { 0x00400040, 0x24001860, 0x16690400, 0x00460046 }, { 0x00400009, 0x22c01868, 0x16690400, 0x00050005 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006420 }, { 0x00400040, 0x24001860, 0x16690400, 0x00400040 }, { 0x00400209, 0x22401868, 0x16690400, 0x00050005 }, { 0x00000401, 0x22500608, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x28002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000001 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2a002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000002 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2c002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000003 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2e002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00600001, 0x23800208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00208, 0x008d0360, 0x00000000 }, { 0x00200201, 0x23801a28, 0x004500e0, 0x00000000 }, { 0x00200208, 0x24a01a28, 0x1e4500e0, 0x00010001 }, { 0x00200208, 0x25c01a28, 0x1e4500e0, 0x00010001 }, { 0x00000401, 0x23880608, 0x00000000, 0x000f000f }, { 0x00000401, 0x24a80608, 0x00000000, 0x00070007 }, { 0x00000401, 0x25c80608, 0x00000000, 0x00070007 }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x80600040, 0xc4001248, 0x16ae8400, 0x00800080 }, { 0x80600040, 0xc4401248, 0x16ae8440, 0x00800080 }, { 0x80600040, 0xc0001248, 0x16ae8000, 0x00800080 }, { 0x80600040, 0xc0401248, 0x16ae8040, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x80600040, 0xcc001248, 0x16ae8c00, 0x00800080 }, { 0x80600040, 0xcc401248, 0x16ae8c40, 0x00800080 }, { 0x80600040, 0xc8001248, 0x16ae8800, 0x00800080 }, { 0x80600040, 0xc8401248, 0x16ae8840, 0x00800080 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x80600040, 0xc4001248, 0x16ae8400, 0x00800080 }, { 0x80600040, 0xc4401248, 0x16ae8440, 0x00800080 }, { 0x80600040, 0xc0001248, 0x16ae8000, 0x00800080 }, { 0x80600040, 0xc0401248, 0x16ae8040, 0x00800080 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x80600040, 0xcc001248, 0x16ae8c00, 0x00800080 }, { 0x80600040, 0xcc401248, 0x16ae8c40, 0x00800080 }, { 0x80600040, 0xc8001248, 0x16ae8800, 0x00800080 }, { 0x80600040, 0xc8401248, 0x16ae8840, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00800201, 0x23a02288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x23b02288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x23c02288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x23d02288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x24c02288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x24c82288, 0x00cf8441, 0x00000000 }, { 0x00600201, 0x25e02288, 0x00cf8001, 0x00000000 }, { 0x00600601, 0x25e82288, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x00800201, 0x23e02288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x23f02288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24002288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24102288, 0x00d28a61, 0x00000000 }, { 0x00600601, 0x24d02288, 0x00cf8c01, 0x00000000 }, { 0x00600401, 0x24d82288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x25f02288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x25f82288, 0x00cf8841, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x00800201, 0x24202288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x24302288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x24402288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x24502288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x24e02288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x24e82288, 0x00cf8441, 0x00000000 }, { 0x00600201, 0x26002288, 0x00cf8001, 0x00000000 }, { 0x00600601, 0x26082288, 0x00cf8041, 0x00000000 }, { 0x00800201, 0x24602288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x24702288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24802288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24902288, 0x00d28a61, 0x00000000 }, { 0x00600601, 0x24f02288, 0x00cf8c01, 0x00000000 }, { 0x00600401, 0x24f82288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x26102288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x26182288, 0x00cf8841, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x120a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8019 }, { 0x0c000031, 0x20002220, 0x060005c0, 0x060a801a }, { 0x00600001, 0x2fe00208, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20002220, 0x0e000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/pl2_to_pa.asm000066400000000000000000000005101231401140700247670ustar00rootroot00000000000000// Module name: AVS .kernel PL2_TO_PA .code #include "VP_Setup.g8a" #include "Set_Layer_0.g8a" #include "Set_AVS_Buf_0123_PL2.g8a" #include "PL2_AVS_Buf_0.g8a" #include "PL2_AVS_Buf_1.g8a" #include "PL2_AVS_Buf_2.g8a" #include "PL2_AVS_Buf_3.g8a" #include "Save_AVS_PA.g8a" #include "EOT.g8a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen8/pl2_to_pa.g8b000066400000000000000000000366511231401140700247060ustar00rootroot00000000000000 { 0x00600001, 0x23600208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400208, 0x008d0000, 0x00000000 }, { 0x00600041, 0x20603ae8, 0x3a8d0060, 0x000000f0 }, { 0x00200001, 0x21141ae8, 0x004500e0, 0x00000000 }, { 0x01000010, 0x20002220, 0x1600005a, 0x00010001 }, { 0x00000008, 0x22201248, 0x16000044, 0x00000000 }, { 0x00000005, 0x22201248, 0x16000220, 0x00030003 }, { 0x01000010, 0x20001261, 0x16000220, 0x00010001 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000090 }, { 0x01000010, 0x20001261, 0x16000220, 0x00020002 }, { 0x00010020, 0x34000005, 0x0e001400, 0x000000f0 }, { 0x01000010, 0x20001261, 0x16000220, 0x00030003 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000180 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000114 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000118 }, { 0x00000020, 0x34000004, 0x0e001400, 0x000001a0 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000118 }, { 0x00000001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000120 }, { 0x00110001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000070 }, { 0x00110001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a01648, 0x10000000, 0xffffffff }, { 0x00000005, 0x23021288, 0x16000044, 0x00030003 }, { 0x00000001, 0x23203ae8, 0x000000f8, 0x00000000 }, { 0x00000001, 0x23383ae8, 0x000000f4, 0x00000000 }, { 0x00000001, 0x23303ae8, 0x00000060, 0x00000000 }, { 0x00000001, 0x23343ae8, 0x00000080, 0x00000000 }, { 0x00000001, 0x23283ae8, 0x000000c0, 0x00000000 }, { 0x00000001, 0x232c3ae8, 0x000000a0, 0x00000000 }, { 0x00000001, 0x233c0608, 0x00000000, 0x00000000 }, { 0x00000040, 0x233c0208, 0x0600033c, 0x08000000 }, { 0x00000001, 0x24083ae0, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24083ae0, 0x3e000060, 0x41000000 }, { 0x00000248, 0x22e83ae8, 0x3e0000f4, 0x41e00000 }, { 0x00000641, 0x22e43ae8, 0x3e000080, 0x40800000 }, { 0x00000001, 0x24103ae0, 0x00000060, 0x00000000 }, { 0x00000648, 0x22f03ae8, 0x3e0000f4, 0x41000000 }, { 0x00000401, 0x22f40608, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006ea2 }, { 0x00400040, 0x24001860, 0x16690400, 0x00460046 }, { 0x00400009, 0x22c01868, 0x16690400, 0x00050005 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006204 }, { 0x00400040, 0x24001860, 0x16690400, 0x00400040 }, { 0x00400209, 0x22401868, 0x16690400, 0x00050005 }, { 0x00000401, 0x22500608, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x28002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000001 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2a002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000002 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2c002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000003 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2e002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22082260, 0x1669005c, 0x03a003a0 }, { 0x00000209, 0x23601a28, 0x1e0000e0, 0x00010001 }, { 0x00000601, 0x23641a28, 0x000000e2, 0x00000000 }, { 0x00000401, 0x23680608, 0x00000000, 0x0001001f }, { 0x80400040, 0xc0001248, 0x168a8000, 0x00800080 }, { 0x80400040, 0xc0201248, 0x168a8020, 0x00800080 }, { 0x80400040, 0xc0401248, 0x168a8040, 0x00800080 }, { 0x80400040, 0xc0601248, 0x168a8060, 0x00800080 }, { 0x80600040, 0xa2001248, 0x168d8200, 0x00800080 }, { 0x80600040, 0xa2201248, 0x168d8220, 0x00800080 }, { 0x80600040, 0xa2401248, 0x168d8240, 0x00800080 }, { 0x80600040, 0xa2601248, 0x168d8260, 0x00800080 }, { 0x80400040, 0xc4001248, 0x168a8400, 0x00800080 }, { 0x80400040, 0xc4201248, 0x168a8420, 0x00800080 }, { 0x80400040, 0xc4401248, 0x168a8440, 0x00800080 }, { 0x80400040, 0xc4601248, 0x168a8460, 0x00800080 }, { 0x80400040, 0xc0101248, 0x168a8010, 0x00800080 }, { 0x80400040, 0xc0301248, 0x168a8030, 0x00800080 }, { 0x80400040, 0xc0501248, 0x168a8050, 0x00800080 }, { 0x80400040, 0xc0701248, 0x168a8070, 0x00800080 }, { 0x80600040, 0xa2101248, 0x168d8210, 0x00800080 }, { 0x80600040, 0xa2301248, 0x168d8230, 0x00800080 }, { 0x80600040, 0xa2501248, 0x168d8250, 0x00800080 }, { 0x80600040, 0xa2701248, 0x168d8270, 0x00800080 }, { 0x80400040, 0xc4101248, 0x168a8410, 0x00800080 }, { 0x80400040, 0xc4301248, 0x168a8430, 0x00800080 }, { 0x80400040, 0xc4501248, 0x168a8450, 0x00800080 }, { 0x80400040, 0xc4701248, 0x168a8470, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x02000200 }, { 0x80400040, 0xc0001248, 0x168a8000, 0x00800080 }, { 0x80400040, 0xc0201248, 0x168a8020, 0x00800080 }, { 0x80400040, 0xc0401248, 0x168a8040, 0x00800080 }, { 0x80400040, 0xc0601248, 0x168a8060, 0x00800080 }, { 0x80600040, 0xa2001248, 0x168d8200, 0x00800080 }, { 0x80600040, 0xa2201248, 0x168d8220, 0x00800080 }, { 0x80600040, 0xa2401248, 0x168d8240, 0x00800080 }, { 0x80600040, 0xa2601248, 0x168d8260, 0x00800080 }, { 0x80400040, 0xc4001248, 0x168a8400, 0x00800080 }, { 0x80400040, 0xc4201248, 0x168a8420, 0x00800080 }, { 0x80400040, 0xc4401248, 0x168a8440, 0x00800080 }, { 0x80400040, 0xc4601248, 0x168a8460, 0x00800080 }, { 0x80400040, 0xc0101248, 0x168a8010, 0x00800080 }, { 0x80400040, 0xc0301248, 0x168a8030, 0x00800080 }, { 0x80400040, 0xc0501248, 0x168a8050, 0x00800080 }, { 0x80400040, 0xc0701248, 0x168a8070, 0x00800080 }, { 0x80600040, 0xa2101248, 0x168d8210, 0x00800080 }, { 0x80600040, 0xa2301248, 0x168d8230, 0x00800080 }, { 0x80600040, 0xa2501248, 0x168d8250, 0x00800080 }, { 0x80600040, 0xa2701248, 0x168d8270, 0x00800080 }, { 0x80400040, 0xc4101248, 0x168a8410, 0x00800080 }, { 0x80400040, 0xc4301248, 0x168a8430, 0x00800080 }, { 0x80400040, 0xc4501248, 0x168a8450, 0x00800080 }, { 0x80400040, 0xc4701248, 0x168a8470, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80400040, 0xc0001248, 0x168a8000, 0x00800080 }, { 0x80400040, 0xc0201248, 0x168a8020, 0x00800080 }, { 0x80400040, 0xc0401248, 0x168a8040, 0x00800080 }, { 0x80400040, 0xc0601248, 0x168a8060, 0x00800080 }, { 0x80600040, 0xa2001248, 0x168d8200, 0x00800080 }, { 0x80600040, 0xa2201248, 0x168d8220, 0x00800080 }, { 0x80600040, 0xa2401248, 0x168d8240, 0x00800080 }, { 0x80600040, 0xa2601248, 0x168d8260, 0x00800080 }, { 0x80400040, 0xc4001248, 0x168a8400, 0x00800080 }, { 0x80400040, 0xc4201248, 0x168a8420, 0x00800080 }, { 0x80400040, 0xc4401248, 0x168a8440, 0x00800080 }, { 0x80400040, 0xc4601248, 0x168a8460, 0x00800080 }, { 0x80400040, 0xc0101248, 0x168a8010, 0x00800080 }, { 0x80400040, 0xc0301248, 0x168a8030, 0x00800080 }, { 0x80400040, 0xc0501248, 0x168a8050, 0x00800080 }, { 0x80400040, 0xc0701248, 0x168a8070, 0x00800080 }, { 0x80600040, 0xa2101248, 0x168d8210, 0x00800080 }, { 0x80600040, 0xa2301248, 0x168d8230, 0x00800080 }, { 0x80600040, 0xa2501248, 0x168d8250, 0x00800080 }, { 0x80600040, 0xa2701248, 0x168d8270, 0x00800080 }, { 0x80400040, 0xc4101248, 0x168a8410, 0x00800080 }, { 0x80400040, 0xc4301248, 0x168a8430, 0x00800080 }, { 0x80400040, 0xc4501248, 0x168a8450, 0x00800080 }, { 0x80400040, 0xc4701248, 0x168a8470, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x06000600 }, { 0x80400040, 0xc0001248, 0x168a8000, 0x00800080 }, { 0x80400040, 0xc0201248, 0x168a8020, 0x00800080 }, { 0x80400040, 0xc0401248, 0x168a8040, 0x00800080 }, { 0x80400040, 0xc0601248, 0x168a8060, 0x00800080 }, { 0x80600040, 0xa2001248, 0x168d8200, 0x00800080 }, { 0x80600040, 0xa2201248, 0x168d8220, 0x00800080 }, { 0x80600040, 0xa2401248, 0x168d8240, 0x00800080 }, { 0x80600040, 0xa2601248, 0x168d8260, 0x00800080 }, { 0x80400040, 0xc4001248, 0x168a8400, 0x00800080 }, { 0x80400040, 0xc4201248, 0x168a8420, 0x00800080 }, { 0x80400040, 0xc4401248, 0x168a8440, 0x00800080 }, { 0x80400040, 0xc4601248, 0x168a8460, 0x00800080 }, { 0x80400040, 0xc0101248, 0x168a8010, 0x00800080 }, { 0x80400040, 0xc0301248, 0x168a8030, 0x00800080 }, { 0x80400040, 0xc0501248, 0x168a8050, 0x00800080 }, { 0x80400040, 0xc0701248, 0x168a8070, 0x00800080 }, { 0x80600040, 0xa2101248, 0x168d8210, 0x00800080 }, { 0x80600040, 0xa2301248, 0x168d8230, 0x00800080 }, { 0x80600040, 0xa2501248, 0x168d8250, 0x00800080 }, { 0x80600040, 0xa2701248, 0x168d8270, 0x00800080 }, { 0x80400040, 0xc4101248, 0x168a8410, 0x00800080 }, { 0x80400040, 0xc4301248, 0x168a8430, 0x00800080 }, { 0x80400040, 0xc4501248, 0x168a8450, 0x00800080 }, { 0x80400040, 0xc4701248, 0x168a8470, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x08000800 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00600001, 0x23800208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00208, 0x008d0360, 0x00000000 }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x00000002 }, { 0x00600201, 0xec002288, 0x00cf8001, 0x00000000 }, { 0x00600201, 0xec202288, 0x00cf8021, 0x00000000 }, { 0x00800601, 0xc8002288, 0x00d28201, 0x00000000 }, { 0x00800601, 0xc8202288, 0x00d28221, 0x00000000 }, { 0x00600401, 0xea002288, 0x00cf8401, 0x00000000 }, { 0x00600401, 0xea202288, 0x00cf8421, 0x00000000 }, { 0x00600201, 0xed202288, 0x00cf8041, 0x00000000 }, { 0x00600201, 0xed402288, 0x00cf8061, 0x00000000 }, { 0x00800601, 0xc9202288, 0x00d28241, 0x00000000 }, { 0x00800601, 0xc9402288, 0x00d28261, 0x00000000 }, { 0x00600401, 0xeb202288, 0x00cf8441, 0x00000000 }, { 0x00600401, 0xeb402288, 0x00cf8461, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x060a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8018 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x02000200 }, { 0x00000040, 0x23840a28, 0x0e000364, 0x00000004 }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x00000006 }, { 0x00600201, 0xec002288, 0x00cf8001, 0x00000000 }, { 0x00600201, 0xec202288, 0x00cf8021, 0x00000000 }, { 0x00800601, 0xc8002288, 0x00d28201, 0x00000000 }, { 0x00800601, 0xc8202288, 0x00d28221, 0x00000000 }, { 0x00600401, 0xea002288, 0x00cf8401, 0x00000000 }, { 0x00600401, 0xea202288, 0x00cf8421, 0x00000000 }, { 0x00600201, 0xed202288, 0x00cf8041, 0x00000000 }, { 0x00600201, 0xed402288, 0x00cf8061, 0x00000000 }, { 0x00800601, 0xc9202288, 0x00d28241, 0x00000000 }, { 0x00800601, 0xc9402288, 0x00d28261, 0x00000000 }, { 0x00600401, 0xeb202288, 0x00cf8441, 0x00000000 }, { 0x00600401, 0xeb402288, 0x00cf8461, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x060a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8018 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x00000040, 0x23840a28, 0x0e000364, 0x00000008 }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x0000000a }, { 0x00600201, 0xec002288, 0x00cf8001, 0x00000000 }, { 0x00600201, 0xec202288, 0x00cf8021, 0x00000000 }, { 0x00800601, 0xc8002288, 0x00d28201, 0x00000000 }, { 0x00800601, 0xc8202288, 0x00d28221, 0x00000000 }, { 0x00600401, 0xea002288, 0x00cf8401, 0x00000000 }, { 0x00600401, 0xea202288, 0x00cf8421, 0x00000000 }, { 0x00600201, 0xed202288, 0x00cf8041, 0x00000000 }, { 0x00600201, 0xed402288, 0x00cf8061, 0x00000000 }, { 0x00800601, 0xc9202288, 0x00d28241, 0x00000000 }, { 0x00800601, 0xc9402288, 0x00d28261, 0x00000000 }, { 0x00600401, 0xeb202288, 0x00cf8441, 0x00000000 }, { 0x00600401, 0xeb402288, 0x00cf8461, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x060a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8018 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x06000600 }, { 0x00000040, 0x23840a28, 0x0e000364, 0x0000000c }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x0000000e }, { 0x00600201, 0xec002288, 0x00cf8001, 0x00000000 }, { 0x00600201, 0xec202288, 0x00cf8021, 0x00000000 }, { 0x00800601, 0xc8002288, 0x00d28201, 0x00000000 }, { 0x00800601, 0xc8202288, 0x00d28221, 0x00000000 }, { 0x00600401, 0xea002288, 0x00cf8401, 0x00000000 }, { 0x00600401, 0xea202288, 0x00cf8421, 0x00000000 }, { 0x00600201, 0xed202288, 0x00cf8041, 0x00000000 }, { 0x00600201, 0xed402288, 0x00cf8061, 0x00000000 }, { 0x00800601, 0xc9202288, 0x00d28241, 0x00000000 }, { 0x00800601, 0xc9402288, 0x00d28261, 0x00000000 }, { 0x00600401, 0xeb202288, 0x00cf8441, 0x00000000 }, { 0x00600401, 0xeb402288, 0x00cf8461, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x060a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8018 }, { 0x00600001, 0x2fe00208, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20002220, 0x0e000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/pl2_to_pl2.asm000066400000000000000000000005131231401140700250670ustar00rootroot00000000000000// Module name: AVS .kernel PL2_TO_PL2 .code #include "VP_Setup.g8a" #include "Set_Layer_0.g8a" #include "Set_AVS_Buf_0123_PL2.g8a" #include "PL2_AVS_Buf_0.g8a" #include "PL2_AVS_Buf_1.g8a" #include "PL2_AVS_Buf_2.g8a" #include "PL2_AVS_Buf_3.g8a" #include "Save_AVS_NV12.g8a" #include "EOT.g8a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen8/pl2_to_pl2.g8b000066400000000000000000000321541231401140700247750ustar00rootroot00000000000000 { 0x00600001, 0x23600208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400208, 0x008d0000, 0x00000000 }, { 0x00600041, 0x20603ae8, 0x3a8d0060, 0x000000f0 }, { 0x00200001, 0x21141ae8, 0x004500e0, 0x00000000 }, { 0x01000010, 0x20002220, 0x1600005a, 0x00010001 }, { 0x00000008, 0x22201248, 0x16000044, 0x00000000 }, { 0x00000005, 0x22201248, 0x16000220, 0x00030003 }, { 0x01000010, 0x20001261, 0x16000220, 0x00010001 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000090 }, { 0x01000010, 0x20001261, 0x16000220, 0x00020002 }, { 0x00010020, 0x34000005, 0x0e001400, 0x000000f0 }, { 0x01000010, 0x20001261, 0x16000220, 0x00030003 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000180 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000114 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000118 }, { 0x00000020, 0x34000004, 0x0e001400, 0x000001a0 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000118 }, { 0x00000001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000120 }, { 0x00110001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000070 }, { 0x00110001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a01648, 0x10000000, 0xffffffff }, { 0x00000005, 0x23021288, 0x16000044, 0x00030003 }, { 0x00000001, 0x23203ae8, 0x000000f8, 0x00000000 }, { 0x00000001, 0x23383ae8, 0x000000f4, 0x00000000 }, { 0x00000001, 0x23303ae8, 0x00000060, 0x00000000 }, { 0x00000001, 0x23343ae8, 0x00000080, 0x00000000 }, { 0x00000001, 0x23283ae8, 0x000000c0, 0x00000000 }, { 0x00000001, 0x232c3ae8, 0x000000a0, 0x00000000 }, { 0x00000001, 0x233c0608, 0x00000000, 0x00000000 }, { 0x00000040, 0x233c0208, 0x0600033c, 0x08000000 }, { 0x00000001, 0x24083ae0, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24083ae0, 0x3e000060, 0x41000000 }, { 0x00000248, 0x22e83ae8, 0x3e0000f4, 0x41e00000 }, { 0x00000641, 0x22e43ae8, 0x3e000080, 0x40800000 }, { 0x00000001, 0x24103ae0, 0x00000060, 0x00000000 }, { 0x00000648, 0x22f03ae8, 0x3e0000f4, 0x41000000 }, { 0x00000401, 0x22f40608, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006ea2 }, { 0x00400040, 0x24001860, 0x16690400, 0x00460046 }, { 0x00400009, 0x22c01868, 0x16690400, 0x00050005 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006204 }, { 0x00400040, 0x24001860, 0x16690400, 0x00400040 }, { 0x00400209, 0x22401868, 0x16690400, 0x00050005 }, { 0x00000401, 0x22500608, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x28002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000001 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2a002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000002 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2c002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000003 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2e002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00600001, 0x23800208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00208, 0x008d0360, 0x00000000 }, { 0x00200201, 0x23801a28, 0x004500e0, 0x00000000 }, { 0x00000201, 0x24a01a28, 0x000000e0, 0x00000000 }, { 0x00000608, 0x24a41a28, 0x1e0000e2, 0x00010001 }, { 0x00000401, 0x23880608, 0x00000000, 0x000f000f }, { 0x00000401, 0x24a80608, 0x00000000, 0x0007000f }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8400, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8420, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8440, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8460, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc4001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xc4401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8000, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8020, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8040, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8060, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc0001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8c00, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8c20, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8c40, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8c60, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xcc001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xcc401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8800, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8820, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8840, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8860, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc8001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc8401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8400, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8420, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8440, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8460, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc4001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xc4401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8000, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8020, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8040, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8060, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc0001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8c00, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8c20, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8c40, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8c60, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xcc001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xcc401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8800, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8820, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8840, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8860, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc8001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc8401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00800201, 0x23a02288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x23b02288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x23c02288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x23d02288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x44c02288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x44d02288, 0x00cf8441, 0x00000000 }, { 0x00600601, 0x44c12288, 0x00cf8001, 0x00000000 }, { 0x00600401, 0x44d12288, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x00800201, 0x23e02288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x23f02288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24002288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24102288, 0x00d28a61, 0x00000000 }, { 0x00600201, 0x44e02288, 0x00cf8c01, 0x00000000 }, { 0x00600601, 0x44f02288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x44e12288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x44f12288, 0x00cf8841, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x00800201, 0x24202288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x24302288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x24402288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x24502288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x45002288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x45102288, 0x00cf8441, 0x00000000 }, { 0x00600601, 0x45012288, 0x00cf8001, 0x00000000 }, { 0x00600401, 0x45112288, 0x00cf8041, 0x00000000 }, { 0x00800201, 0x24602288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x24702288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24802288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24902288, 0x00d28a61, 0x00000000 }, { 0x00600201, 0x45202288, 0x00cf8c01, 0x00000000 }, { 0x00600601, 0x45302288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x45212288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x45312288, 0x00cf8841, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x120a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00208, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20002220, 0x0e000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/pl2_to_pl3.asm000066400000000000000000000005121231401140700250670ustar00rootroot00000000000000// Module name: AVS .kernel PL2_TO_PL3 .code #include "VP_Setup.g8a" #include "Set_Layer_0.g8a" #include "Set_AVS_Buf_0123_PL2.g8a" #include "PL2_AVS_Buf_0.g8a" #include "PL2_AVS_Buf_1.g8a" #include "PL2_AVS_Buf_2.g8a" #include "PL2_AVS_Buf_3.g8a" #include "Save_AVS_PL3.g8a" #include "EOT.g8a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen8/pl2_to_pl3.g8b000066400000000000000000000251231231401140700247740ustar00rootroot00000000000000 { 0x00600001, 0x23600208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400208, 0x008d0000, 0x00000000 }, { 0x00600041, 0x20603ae8, 0x3a8d0060, 0x000000f0 }, { 0x00200001, 0x21141ae8, 0x004500e0, 0x00000000 }, { 0x01000010, 0x20002220, 0x1600005a, 0x00010001 }, { 0x00000008, 0x22201248, 0x16000044, 0x00000000 }, { 0x00000005, 0x22201248, 0x16000220, 0x00030003 }, { 0x01000010, 0x20001261, 0x16000220, 0x00010001 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000090 }, { 0x01000010, 0x20001261, 0x16000220, 0x00020002 }, { 0x00010020, 0x34000005, 0x0e001400, 0x000000f0 }, { 0x01000010, 0x20001261, 0x16000220, 0x00030003 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000180 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000114 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000118 }, { 0x00000020, 0x34000004, 0x0e001400, 0x000001a0 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000118 }, { 0x00000001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000120 }, { 0x00110001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000070 }, { 0x00110001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a01648, 0x10000000, 0xffffffff }, { 0x00000005, 0x23021288, 0x16000044, 0x00030003 }, { 0x00000001, 0x23203ae8, 0x000000f8, 0x00000000 }, { 0x00000001, 0x23383ae8, 0x000000f4, 0x00000000 }, { 0x00000001, 0x23303ae8, 0x00000060, 0x00000000 }, { 0x00000001, 0x23343ae8, 0x00000080, 0x00000000 }, { 0x00000001, 0x23283ae8, 0x000000c0, 0x00000000 }, { 0x00000001, 0x232c3ae8, 0x000000a0, 0x00000000 }, { 0x00000001, 0x233c0608, 0x00000000, 0x00000000 }, { 0x00000040, 0x233c0208, 0x0600033c, 0x08000000 }, { 0x00000001, 0x24083ae0, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24083ae0, 0x3e000060, 0x41000000 }, { 0x00000248, 0x22e83ae8, 0x3e0000f4, 0x41e00000 }, { 0x00000641, 0x22e43ae8, 0x3e000080, 0x40800000 }, { 0x00000001, 0x24103ae0, 0x00000060, 0x00000000 }, { 0x00000648, 0x22f03ae8, 0x3e0000f4, 0x41000000 }, { 0x00000401, 0x22f40608, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006ea2 }, { 0x00400040, 0x24001860, 0x16690400, 0x00460046 }, { 0x00400009, 0x22c01868, 0x16690400, 0x00050005 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006204 }, { 0x00400040, 0x24001860, 0x16690400, 0x00400040 }, { 0x00400209, 0x22401868, 0x16690400, 0x00050005 }, { 0x00000401, 0x22500608, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x28002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000001 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2a002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000002 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2c002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000003 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2e002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00600001, 0x23800208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00208, 0x008d0360, 0x00000000 }, { 0x00200201, 0x23801a28, 0x004500e0, 0x00000000 }, { 0x00200208, 0x24a01a28, 0x1e4500e0, 0x00010001 }, { 0x00200208, 0x25c01a28, 0x1e4500e0, 0x00010001 }, { 0x00000401, 0x23880608, 0x00000000, 0x000f000f }, { 0x00000401, 0x24a80608, 0x00000000, 0x00070007 }, { 0x00000401, 0x25c80608, 0x00000000, 0x00070007 }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x80600040, 0xc4001248, 0x16ae8400, 0x00800080 }, { 0x80600040, 0xc4401248, 0x16ae8440, 0x00800080 }, { 0x80600040, 0xc0001248, 0x16ae8000, 0x00800080 }, { 0x80600040, 0xc0401248, 0x16ae8040, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x80600040, 0xcc001248, 0x16ae8c00, 0x00800080 }, { 0x80600040, 0xcc401248, 0x16ae8c40, 0x00800080 }, { 0x80600040, 0xc8001248, 0x16ae8800, 0x00800080 }, { 0x80600040, 0xc8401248, 0x16ae8840, 0x00800080 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x80600040, 0xc4001248, 0x16ae8400, 0x00800080 }, { 0x80600040, 0xc4401248, 0x16ae8440, 0x00800080 }, { 0x80600040, 0xc0001248, 0x16ae8000, 0x00800080 }, { 0x80600040, 0xc0401248, 0x16ae8040, 0x00800080 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x80600040, 0xcc001248, 0x16ae8c00, 0x00800080 }, { 0x80600040, 0xcc401248, 0x16ae8c40, 0x00800080 }, { 0x80600040, 0xc8001248, 0x16ae8800, 0x00800080 }, { 0x80600040, 0xc8401248, 0x16ae8840, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00800201, 0x23a02288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x23b02288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x23c02288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x23d02288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x24c02288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x24c82288, 0x00cf8441, 0x00000000 }, { 0x00600201, 0x25e02288, 0x00cf8001, 0x00000000 }, { 0x00600601, 0x25e82288, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x00800201, 0x23e02288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x23f02288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24002288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24102288, 0x00d28a61, 0x00000000 }, { 0x00600601, 0x24d02288, 0x00cf8c01, 0x00000000 }, { 0x00600401, 0x24d82288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x25f02288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x25f82288, 0x00cf8841, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x00800201, 0x24202288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x24302288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x24402288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x24502288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x24e02288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x24e82288, 0x00cf8441, 0x00000000 }, { 0x00600201, 0x26002288, 0x00cf8001, 0x00000000 }, { 0x00600601, 0x26082288, 0x00cf8041, 0x00000000 }, { 0x00800201, 0x24602288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x24702288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24802288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24902288, 0x00d28a61, 0x00000000 }, { 0x00600601, 0x24f02288, 0x00cf8c01, 0x00000000 }, { 0x00600401, 0x24f82288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x26102288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x26182288, 0x00cf8841, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x120a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8019 }, { 0x0c000031, 0x20002220, 0x060005c0, 0x060a801a }, { 0x00600001, 0x2fe00208, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20002220, 0x0e000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/pl2_to_rgbx.asm000066400000000000000000000005451231401140700253410ustar00rootroot00000000000000// Module name: AVS .kernel PL2_TO_PL2 .code #include "VP_Setup.g8a" #include "Set_Layer_0.g8a" #include "Set_AVS_Buf_0123_PL2.g8a" #include "PL2_AVS_Buf_0.g8a" #include "PL2_AVS_Buf_1.g8a" #include "PL2_AVS_Buf_2.g8a" #include "PL2_AVS_Buf_3.g8a" #include "YUV_to_RGB.g8a" #include "Save_AVS_RGBX.g8a" #include "EOT.g8a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen8/pl2_to_rgbx.g8b000066400000000000000000001172161231401140700252450ustar00rootroot00000000000000 { 0x00600001, 0x23600208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400208, 0x008d0000, 0x00000000 }, { 0x00600041, 0x20603ae8, 0x3a8d0060, 0x000000f0 }, { 0x00200001, 0x21141ae8, 0x004500e0, 0x00000000 }, { 0x01000010, 0x20002220, 0x1600005a, 0x00010001 }, { 0x00000008, 0x22201248, 0x16000044, 0x00000000 }, { 0x00000005, 0x22201248, 0x16000220, 0x00030003 }, { 0x01000010, 0x20001261, 0x16000220, 0x00010001 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000090 }, { 0x01000010, 0x20001261, 0x16000220, 0x00020002 }, { 0x00010020, 0x34000005, 0x0e001400, 0x000000f0 }, { 0x01000010, 0x20001261, 0x16000220, 0x00030003 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000180 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000114 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000118 }, { 0x00000020, 0x34000004, 0x0e001400, 0x000001a0 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000118 }, { 0x00000001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000120 }, { 0x00110001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000070 }, { 0x00110001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a01648, 0x10000000, 0xffffffff }, { 0x00000005, 0x23021288, 0x16000044, 0x00030003 }, { 0x00000001, 0x23203ae8, 0x000000f8, 0x00000000 }, { 0x00000001, 0x23383ae8, 0x000000f4, 0x00000000 }, { 0x00000001, 0x23303ae8, 0x00000060, 0x00000000 }, { 0x00000001, 0x23343ae8, 0x00000080, 0x00000000 }, { 0x00000001, 0x23283ae8, 0x000000c0, 0x00000000 }, { 0x00000001, 0x232c3ae8, 0x000000a0, 0x00000000 }, { 0x00000001, 0x233c0608, 0x00000000, 0x00000000 }, { 0x00000040, 0x233c0208, 0x0600033c, 0x08000000 }, { 0x00000001, 0x24083ae0, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24083ae0, 0x3e000060, 0x41000000 }, { 0x00000248, 0x22e83ae8, 0x3e0000f4, 0x41e00000 }, { 0x00000641, 0x22e43ae8, 0x3e000080, 0x40800000 }, { 0x00000001, 0x24103ae0, 0x00000060, 0x00000000 }, { 0x00000648, 0x22f03ae8, 0x3e0000f4, 0x41000000 }, { 0x00000401, 0x22f40608, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006ea2 }, { 0x00400040, 0x24001860, 0x16690400, 0x00460046 }, { 0x00400009, 0x22c01868, 0x16690400, 0x00050005 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006204 }, { 0x00400040, 0x24001860, 0x16690400, 0x00400040 }, { 0x00400209, 0x22401868, 0x16690400, 0x00050005 }, { 0x00000401, 0x22500608, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x28002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x28802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000001 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2a002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2a802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000002 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2c002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2c802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000003 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2e002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x048eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000a000 }, { 0x02000031, 0x2e802248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x22001240, 0x006902c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8201, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8211, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8011, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2012288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4012288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0012288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8221, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8231, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8031, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2212288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4212288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0212288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8241, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8251, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8051, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2412288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4412288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0412288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8261, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8271, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8071, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2612288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4612288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0612288, 0x00cf05c0, 0x00000000 }, { 0x00400040, 0x22001240, 0x166902c0, 0x02000200 }, { 0x00600001, 0x248022e8, 0x00ae8201, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8211, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8011, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2012288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4012288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0012288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8221, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8231, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8031, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2212288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4212288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0212288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8241, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8251, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8051, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2412288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4412288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0412288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8261, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8271, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8071, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2612288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4612288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0612288, 0x00cf05c0, 0x00000000 }, { 0x00400040, 0x22001240, 0x166902c0, 0x04000400 }, { 0x00600001, 0x248022e8, 0x00ae8201, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8211, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8011, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2012288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4012288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0012288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8221, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8231, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8031, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2212288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4212288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0212288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8241, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8251, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8051, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2412288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4412288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0412288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8261, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8271, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8071, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2612288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4612288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0612288, 0x00cf05c0, 0x00000000 }, { 0x00400040, 0x22001240, 0x166902c0, 0x06000600 }, { 0x00600001, 0x248022e8, 0x00ae8201, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8211, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8011, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2012288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4012288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0012288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8221, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8231, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8031, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2212288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4212288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0212288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8241, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8251, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8051, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2412288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4412288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0412288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x248022e8, 0x00ae8261, 0x00000000 }, { 0x00600001, 0x24a022e8, 0x00ae8271, 0x00000000 }, { 0x00600001, 0x24c022e8, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x24e022e8, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x250022e8, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x252022e8, 0x00ae8071, 0x00000000 }, { 0x00800040, 0x24c03ae8, 0x3e8d04c0, 0xc3000000 }, { 0x00800040, 0x25003ae8, 0x3e8d0500, 0xc3000000 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x23803ae8, 0x3e8d0500, 0x3fb374bc }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00600048, 0x24003ae0, 0x3e8d04c0, 0xbeb020c5 }, { 0x00600048, 0x24203ae0, 0x3e8d04e0, 0xbeb020c5 }, { 0x00800048, 0x23c03ae8, 0x3e8d0500, 0xbf36c8b4 }, { 0x00800001, 0x24003ae0, 0x008d0480, 0x00000000 }, { 0x00800048, 0x24003ae8, 0x3e8d04c0, 0x3fe2d0e5 }, { 0x80800041, 0x24803ae8, 0x3e8d0380, 0x3b8080c4 }, { 0x80800041, 0x24c03ae8, 0x3e8d03c0, 0x3b8080c4 }, { 0x80800041, 0x25003ae8, 0x3e8d0400, 0x3b8080c4 }, { 0x00800041, 0x23803ae8, 0x3e8d0480, 0x437f0000 }, { 0x00800041, 0x23c03ae8, 0x3e8d04c0, 0x437f0000 }, { 0x00800041, 0x24003ae8, 0x3e8d0500, 0x437f0000 }, { 0x00800001, 0x45403a68, 0x008d0380, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d03c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0400, 0x00000000 }, { 0x00800001, 0xc2612288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xc4612288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc0612288, 0x00cf05c0, 0x00000000 }, { 0x00400001, 0x24003660, 0x30000000, 0x000062ea }, { 0x00400040, 0x24001860, 0x16690400, 0x00460046 }, { 0x00400009, 0x22c01868, 0x16690400, 0x00050005 }, { 0x02800005, 0x20001260, 0x1e000046, 0x00010001 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00010001, 0x22201048, 0x00000200, 0x00000000 }, { 0x00010001, 0x22001040, 0x00000204, 0x00000000 }, { 0x00010001, 0x22041240, 0x00000220, 0x00000000 }, { 0x00000209, 0x23601a28, 0x1e0000e0, 0x00020002 }, { 0x00000601, 0x23641a28, 0x000000e2, 0x00000000 }, { 0x00000401, 0x23680608, 0x00000000, 0x0003001f }, { 0x00400001, 0x22081040, 0x00690200, 0x00000000 }, { 0x00600001, 0x23800208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x26e00208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x23e00208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25000208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x26200208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x27400208, 0x008d0360, 0x00000000 }, { 0x00000040, 0x24a00a28, 0x0e000360, 0x00000020 }, { 0x00000040, 0x25c40a28, 0x0e000364, 0x00000004 }, { 0x00000040, 0x26e40a28, 0x0e000364, 0x00000004 }, { 0x00000040, 0x26e00a28, 0x0e000360, 0x00000020 }, { 0x00600001, 0x63a02288, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x63a12288, 0x00ae8201, 0x00000000 }, { 0x00600001, 0x63a22288, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x63a32288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x63c02288, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x63c12288, 0x00ae8221, 0x00000000 }, { 0x00600001, 0x63c22288, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x63c32288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64c02288, 0x00ae8011, 0x00000000 }, { 0x00600001, 0x64c12288, 0x00ae8211, 0x00000000 }, { 0x00600001, 0x64c22288, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x64c32288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64e02288, 0x00ae8031, 0x00000000 }, { 0x00600001, 0x64e12288, 0x00ae8231, 0x00000000 }, { 0x00600001, 0x64e22288, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x64e32288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x63e02288, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x63e12288, 0x00ae8241, 0x00000000 }, { 0x00600001, 0x63e22288, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x63e32288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64002288, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x64012288, 0x00ae8261, 0x00000000 }, { 0x00600001, 0x64022288, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x64032288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x65002288, 0x00ae8051, 0x00000000 }, { 0x00600001, 0x65012288, 0x00ae8251, 0x00000000 }, { 0x00600001, 0x65022288, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x65032288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x65202288, 0x00ae8071, 0x00000000 }, { 0x00600001, 0x65212288, 0x00ae8271, 0x00000000 }, { 0x00600001, 0x65222288, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x65232288, 0x0000005f, 0x00000000 }, { 0x0c800031, 0x20002220, 0x06000380, 0x0a0a8018 }, { 0x0c800031, 0x20002220, 0x060004a0, 0x0a0a8018 }, { 0x00400040, 0x22001040, 0x16690208, 0x02000200 }, { 0x00600001, 0x65e02288, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x65e12288, 0x00ae8201, 0x00000000 }, { 0x00600001, 0x65e22288, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x65e32288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66002288, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x66012288, 0x00ae8221, 0x00000000 }, { 0x00600001, 0x66022288, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x66032288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67002288, 0x00ae8011, 0x00000000 }, { 0x00600001, 0x67012288, 0x00ae8211, 0x00000000 }, { 0x00600001, 0x67022288, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x67032288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67202288, 0x00ae8031, 0x00000000 }, { 0x00600001, 0x67212288, 0x00ae8231, 0x00000000 }, { 0x00600001, 0x67222288, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x67232288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66202288, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x66212288, 0x00ae8241, 0x00000000 }, { 0x00600001, 0x66222288, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x66232288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66402288, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x66412288, 0x00ae8261, 0x00000000 }, { 0x00600001, 0x66422288, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x66432288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67402288, 0x00ae8051, 0x00000000 }, { 0x00600001, 0x67412288, 0x00ae8251, 0x00000000 }, { 0x00600001, 0x67422288, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x67432288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67602288, 0x00ae8071, 0x00000000 }, { 0x00600001, 0x67612288, 0x00ae8271, 0x00000000 }, { 0x00600001, 0x67622288, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x67632288, 0x0000005f, 0x00000000 }, { 0x0c800031, 0x20002220, 0x060005c0, 0x0a0a8018 }, { 0x0c800031, 0x20002220, 0x060006e0, 0x0a0a8018 }, { 0x00600001, 0x23800208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x26e00208, 0x008d0360, 0x00000000 }, { 0x00000040, 0x23840a28, 0x0e000364, 0x00000008 }, { 0x00000040, 0x24a00a28, 0x0e000360, 0x00000020 }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x00000008 }, { 0x00000040, 0x25c40a28, 0x0e000364, 0x0000000c }, { 0x00000040, 0x26e40a28, 0x0e000364, 0x0000000c }, { 0x00000040, 0x26e00a28, 0x0e000360, 0x00000020 }, { 0x00400040, 0x22001040, 0x16690208, 0x04000400 }, { 0x00600001, 0x63a02288, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x63a12288, 0x00ae8201, 0x00000000 }, { 0x00600001, 0x63a22288, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x63a32288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x63c02288, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x63c12288, 0x00ae8221, 0x00000000 }, { 0x00600001, 0x63c22288, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x63c32288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64c02288, 0x00ae8011, 0x00000000 }, { 0x00600001, 0x64c12288, 0x00ae8211, 0x00000000 }, { 0x00600001, 0x64c22288, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x64c32288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64e02288, 0x00ae8031, 0x00000000 }, { 0x00600001, 0x64e12288, 0x00ae8231, 0x00000000 }, { 0x00600001, 0x64e22288, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x64e32288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x63e02288, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x63e12288, 0x00ae8241, 0x00000000 }, { 0x00600001, 0x63e22288, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x63e32288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x64002288, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x64012288, 0x00ae8261, 0x00000000 }, { 0x00600001, 0x64022288, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x64032288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x65002288, 0x00ae8051, 0x00000000 }, { 0x00600001, 0x65012288, 0x00ae8251, 0x00000000 }, { 0x00600001, 0x65022288, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x65032288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x65202288, 0x00ae8071, 0x00000000 }, { 0x00600001, 0x65212288, 0x00ae8271, 0x00000000 }, { 0x00600001, 0x65222288, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x65232288, 0x0000005f, 0x00000000 }, { 0x0c800031, 0x20002220, 0x06000380, 0x0a0a8018 }, { 0x0c800031, 0x20002220, 0x060004a0, 0x0a0a8018 }, { 0x00400040, 0x22001040, 0x16690208, 0x06000600 }, { 0x00600001, 0x65e02288, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x65e12288, 0x00ae8201, 0x00000000 }, { 0x00600001, 0x65e22288, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x65e32288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66002288, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x66012288, 0x00ae8221, 0x00000000 }, { 0x00600001, 0x66022288, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x66032288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67002288, 0x00ae8011, 0x00000000 }, { 0x00600001, 0x67012288, 0x00ae8211, 0x00000000 }, { 0x00600001, 0x67022288, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x67032288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67202288, 0x00ae8031, 0x00000000 }, { 0x00600001, 0x67212288, 0x00ae8231, 0x00000000 }, { 0x00600001, 0x67222288, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x67232288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66202288, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x66212288, 0x00ae8241, 0x00000000 }, { 0x00600001, 0x66222288, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x66232288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x66402288, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x66412288, 0x00ae8261, 0x00000000 }, { 0x00600001, 0x66422288, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x66432288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67402288, 0x00ae8051, 0x00000000 }, { 0x00600001, 0x67412288, 0x00ae8251, 0x00000000 }, { 0x00600001, 0x67422288, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x67432288, 0x0000005f, 0x00000000 }, { 0x00600001, 0x67602288, 0x00ae8071, 0x00000000 }, { 0x00600001, 0x67612288, 0x00ae8271, 0x00000000 }, { 0x00600001, 0x67622288, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x67632288, 0x0000005f, 0x00000000 }, { 0x0c800031, 0x20002220, 0x060005c0, 0x0a0a8018 }, { 0x0c800031, 0x20002220, 0x060006e0, 0x0a0a8018 }, { 0x00600001, 0x2fe00208, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20002220, 0x0e000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/pl3_to_pa.asm000066400000000000000000000005111231401140700247710ustar00rootroot00000000000000// Module name: AVS .kernel PL3_TO_PL3 .code #include "VP_Setup.g8a" #include "Set_Layer_0.g8a" #include "Set_AVS_Buf_0123_PL3.g8a" #include "PL3_AVS_Buf_0.g8a" #include "PL3_AVS_Buf_1.g8a" #include "PL3_AVS_Buf_2.g8a" #include "PL3_AVS_Buf_3.g8a" #include "Save_AVS_PA.g8a" #include "EOT.g8a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen8/pl3_to_pa.g8b000066400000000000000000000404311231401140700246760ustar00rootroot00000000000000 { 0x00600001, 0x23600208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400208, 0x008d0000, 0x00000000 }, { 0x00600041, 0x20603ae8, 0x3a8d0060, 0x000000f0 }, { 0x00200001, 0x21141ae8, 0x004500e0, 0x00000000 }, { 0x01000010, 0x20002220, 0x1600005a, 0x00010001 }, { 0x00000008, 0x22201248, 0x16000044, 0x00000000 }, { 0x00000005, 0x22201248, 0x16000220, 0x00030003 }, { 0x01000010, 0x20001261, 0x16000220, 0x00010001 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000090 }, { 0x01000010, 0x20001261, 0x16000220, 0x00020002 }, { 0x00010020, 0x34000005, 0x0e001400, 0x000000f0 }, { 0x01000010, 0x20001261, 0x16000220, 0x00030003 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000180 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000114 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000118 }, { 0x00000020, 0x34000004, 0x0e001400, 0x000001a0 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000118 }, { 0x00000001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000120 }, { 0x00110001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000070 }, { 0x00110001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a01648, 0x10000000, 0xffffffff }, { 0x00000005, 0x23021288, 0x16000044, 0x00030003 }, { 0x00000001, 0x23203ae8, 0x000000f8, 0x00000000 }, { 0x00000001, 0x23383ae8, 0x000000f4, 0x00000000 }, { 0x00000001, 0x23303ae8, 0x00000060, 0x00000000 }, { 0x00000001, 0x23343ae8, 0x00000080, 0x00000000 }, { 0x00000001, 0x23283ae8, 0x000000c0, 0x00000000 }, { 0x00000001, 0x232c3ae8, 0x000000a0, 0x00000000 }, { 0x00000001, 0x233c0608, 0x00000000, 0x00000000 }, { 0x00000040, 0x233c0208, 0x0600033c, 0x08000000 }, { 0x00000001, 0x24083ae0, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24083ae0, 0x3e000060, 0x41000000 }, { 0x00000248, 0x22e83ae8, 0x3e0000f4, 0x41e00000 }, { 0x00000641, 0x22e43ae8, 0x3e000080, 0x40800000 }, { 0x00000001, 0x24103ae0, 0x00000060, 0x00000000 }, { 0x00000648, 0x22f03ae8, 0x3e0000f4, 0x41000000 }, { 0x00000401, 0x22f40608, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006ea2 }, { 0x00400040, 0x24001860, 0x16690400, 0x00460046 }, { 0x00400009, 0x22c01868, 0x16690400, 0x00050005 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006204 }, { 0x00400040, 0x24001860, 0x16690400, 0x00400040 }, { 0x00400209, 0x22401868, 0x16690400, 0x00050005 }, { 0x00000401, 0x22500608, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x28002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x28802248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb002 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x29002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000001 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2a002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2a802248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb002 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2b002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000002 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2c002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2c802248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb002 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2d002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000003 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2e002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2e802248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb002 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2f002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22082260, 0x1669005c, 0x03a003a0 }, { 0x00000209, 0x23601a28, 0x1e0000e0, 0x00010001 }, { 0x00000601, 0x23641a28, 0x000000e2, 0x00000000 }, { 0x00000401, 0x23680608, 0x00000000, 0x0001001f }, { 0x80400040, 0xc0001248, 0x168a8000, 0x00800080 }, { 0x80400040, 0xc0201248, 0x168a8020, 0x00800080 }, { 0x80400040, 0xc0401248, 0x168a8040, 0x00800080 }, { 0x80400040, 0xc0601248, 0x168a8060, 0x00800080 }, { 0x80600040, 0xa2001248, 0x168d8200, 0x00800080 }, { 0x80600040, 0xa2201248, 0x168d8220, 0x00800080 }, { 0x80600040, 0xa2401248, 0x168d8240, 0x00800080 }, { 0x80600040, 0xa2601248, 0x168d8260, 0x00800080 }, { 0x80400040, 0xc4001248, 0x168a8400, 0x00800080 }, { 0x80400040, 0xc4201248, 0x168a8420, 0x00800080 }, { 0x80400040, 0xc4401248, 0x168a8440, 0x00800080 }, { 0x80400040, 0xc4601248, 0x168a8460, 0x00800080 }, { 0x80400040, 0xc0101248, 0x168a8010, 0x00800080 }, { 0x80400040, 0xc0301248, 0x168a8030, 0x00800080 }, { 0x80400040, 0xc0501248, 0x168a8050, 0x00800080 }, { 0x80400040, 0xc0701248, 0x168a8070, 0x00800080 }, { 0x80600040, 0xa2101248, 0x168d8210, 0x00800080 }, { 0x80600040, 0xa2301248, 0x168d8230, 0x00800080 }, { 0x80600040, 0xa2501248, 0x168d8250, 0x00800080 }, { 0x80600040, 0xa2701248, 0x168d8270, 0x00800080 }, { 0x80400040, 0xc4101248, 0x168a8410, 0x00800080 }, { 0x80400040, 0xc4301248, 0x168a8430, 0x00800080 }, { 0x80400040, 0xc4501248, 0x168a8450, 0x00800080 }, { 0x80400040, 0xc4701248, 0x168a8470, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x02000200 }, { 0x80400040, 0xc0001248, 0x168a8000, 0x00800080 }, { 0x80400040, 0xc0201248, 0x168a8020, 0x00800080 }, { 0x80400040, 0xc0401248, 0x168a8040, 0x00800080 }, { 0x80400040, 0xc0601248, 0x168a8060, 0x00800080 }, { 0x80600040, 0xa2001248, 0x168d8200, 0x00800080 }, { 0x80600040, 0xa2201248, 0x168d8220, 0x00800080 }, { 0x80600040, 0xa2401248, 0x168d8240, 0x00800080 }, { 0x80600040, 0xa2601248, 0x168d8260, 0x00800080 }, { 0x80400040, 0xc4001248, 0x168a8400, 0x00800080 }, { 0x80400040, 0xc4201248, 0x168a8420, 0x00800080 }, { 0x80400040, 0xc4401248, 0x168a8440, 0x00800080 }, { 0x80400040, 0xc4601248, 0x168a8460, 0x00800080 }, { 0x80400040, 0xc0101248, 0x168a8010, 0x00800080 }, { 0x80400040, 0xc0301248, 0x168a8030, 0x00800080 }, { 0x80400040, 0xc0501248, 0x168a8050, 0x00800080 }, { 0x80400040, 0xc0701248, 0x168a8070, 0x00800080 }, { 0x80600040, 0xa2101248, 0x168d8210, 0x00800080 }, { 0x80600040, 0xa2301248, 0x168d8230, 0x00800080 }, { 0x80600040, 0xa2501248, 0x168d8250, 0x00800080 }, { 0x80600040, 0xa2701248, 0x168d8270, 0x00800080 }, { 0x80400040, 0xc4101248, 0x168a8410, 0x00800080 }, { 0x80400040, 0xc4301248, 0x168a8430, 0x00800080 }, { 0x80400040, 0xc4501248, 0x168a8450, 0x00800080 }, { 0x80400040, 0xc4701248, 0x168a8470, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80400040, 0xc0001248, 0x168a8000, 0x00800080 }, { 0x80400040, 0xc0201248, 0x168a8020, 0x00800080 }, { 0x80400040, 0xc0401248, 0x168a8040, 0x00800080 }, { 0x80400040, 0xc0601248, 0x168a8060, 0x00800080 }, { 0x80600040, 0xa2001248, 0x168d8200, 0x00800080 }, { 0x80600040, 0xa2201248, 0x168d8220, 0x00800080 }, { 0x80600040, 0xa2401248, 0x168d8240, 0x00800080 }, { 0x80600040, 0xa2601248, 0x168d8260, 0x00800080 }, { 0x80400040, 0xc4001248, 0x168a8400, 0x00800080 }, { 0x80400040, 0xc4201248, 0x168a8420, 0x00800080 }, { 0x80400040, 0xc4401248, 0x168a8440, 0x00800080 }, { 0x80400040, 0xc4601248, 0x168a8460, 0x00800080 }, { 0x80400040, 0xc0101248, 0x168a8010, 0x00800080 }, { 0x80400040, 0xc0301248, 0x168a8030, 0x00800080 }, { 0x80400040, 0xc0501248, 0x168a8050, 0x00800080 }, { 0x80400040, 0xc0701248, 0x168a8070, 0x00800080 }, { 0x80600040, 0xa2101248, 0x168d8210, 0x00800080 }, { 0x80600040, 0xa2301248, 0x168d8230, 0x00800080 }, { 0x80600040, 0xa2501248, 0x168d8250, 0x00800080 }, { 0x80600040, 0xa2701248, 0x168d8270, 0x00800080 }, { 0x80400040, 0xc4101248, 0x168a8410, 0x00800080 }, { 0x80400040, 0xc4301248, 0x168a8430, 0x00800080 }, { 0x80400040, 0xc4501248, 0x168a8450, 0x00800080 }, { 0x80400040, 0xc4701248, 0x168a8470, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x06000600 }, { 0x80400040, 0xc0001248, 0x168a8000, 0x00800080 }, { 0x80400040, 0xc0201248, 0x168a8020, 0x00800080 }, { 0x80400040, 0xc0401248, 0x168a8040, 0x00800080 }, { 0x80400040, 0xc0601248, 0x168a8060, 0x00800080 }, { 0x80600040, 0xa2001248, 0x168d8200, 0x00800080 }, { 0x80600040, 0xa2201248, 0x168d8220, 0x00800080 }, { 0x80600040, 0xa2401248, 0x168d8240, 0x00800080 }, { 0x80600040, 0xa2601248, 0x168d8260, 0x00800080 }, { 0x80400040, 0xc4001248, 0x168a8400, 0x00800080 }, { 0x80400040, 0xc4201248, 0x168a8420, 0x00800080 }, { 0x80400040, 0xc4401248, 0x168a8440, 0x00800080 }, { 0x80400040, 0xc4601248, 0x168a8460, 0x00800080 }, { 0x80400040, 0xc0101248, 0x168a8010, 0x00800080 }, { 0x80400040, 0xc0301248, 0x168a8030, 0x00800080 }, { 0x80400040, 0xc0501248, 0x168a8050, 0x00800080 }, { 0x80400040, 0xc0701248, 0x168a8070, 0x00800080 }, { 0x80600040, 0xa2101248, 0x168d8210, 0x00800080 }, { 0x80600040, 0xa2301248, 0x168d8230, 0x00800080 }, { 0x80600040, 0xa2501248, 0x168d8250, 0x00800080 }, { 0x80600040, 0xa2701248, 0x168d8270, 0x00800080 }, { 0x80400040, 0xc4101248, 0x168a8410, 0x00800080 }, { 0x80400040, 0xc4301248, 0x168a8430, 0x00800080 }, { 0x80400040, 0xc4501248, 0x168a8450, 0x00800080 }, { 0x80400040, 0xc4701248, 0x168a8470, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x08000800 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00600001, 0x23800208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00208, 0x008d0360, 0x00000000 }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x00000002 }, { 0x00600201, 0xec002288, 0x00cf8001, 0x00000000 }, { 0x00600201, 0xec202288, 0x00cf8021, 0x00000000 }, { 0x00800601, 0xc8002288, 0x00d28201, 0x00000000 }, { 0x00800601, 0xc8202288, 0x00d28221, 0x00000000 }, { 0x00600401, 0xea002288, 0x00cf8401, 0x00000000 }, { 0x00600401, 0xea202288, 0x00cf8421, 0x00000000 }, { 0x00600201, 0xed202288, 0x00cf8041, 0x00000000 }, { 0x00600201, 0xed402288, 0x00cf8061, 0x00000000 }, { 0x00800601, 0xc9202288, 0x00d28241, 0x00000000 }, { 0x00800601, 0xc9402288, 0x00d28261, 0x00000000 }, { 0x00600401, 0xeb202288, 0x00cf8441, 0x00000000 }, { 0x00600401, 0xeb402288, 0x00cf8461, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x060a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8018 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x02000200 }, { 0x00000040, 0x23840a28, 0x0e000364, 0x00000004 }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x00000006 }, { 0x00600201, 0xec002288, 0x00cf8001, 0x00000000 }, { 0x00600201, 0xec202288, 0x00cf8021, 0x00000000 }, { 0x00800601, 0xc8002288, 0x00d28201, 0x00000000 }, { 0x00800601, 0xc8202288, 0x00d28221, 0x00000000 }, { 0x00600401, 0xea002288, 0x00cf8401, 0x00000000 }, { 0x00600401, 0xea202288, 0x00cf8421, 0x00000000 }, { 0x00600201, 0xed202288, 0x00cf8041, 0x00000000 }, { 0x00600201, 0xed402288, 0x00cf8061, 0x00000000 }, { 0x00800601, 0xc9202288, 0x00d28241, 0x00000000 }, { 0x00800601, 0xc9402288, 0x00d28261, 0x00000000 }, { 0x00600401, 0xeb202288, 0x00cf8441, 0x00000000 }, { 0x00600401, 0xeb402288, 0x00cf8461, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x060a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8018 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x00000040, 0x23840a28, 0x0e000364, 0x00000008 }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x0000000a }, { 0x00600201, 0xec002288, 0x00cf8001, 0x00000000 }, { 0x00600201, 0xec202288, 0x00cf8021, 0x00000000 }, { 0x00800601, 0xc8002288, 0x00d28201, 0x00000000 }, { 0x00800601, 0xc8202288, 0x00d28221, 0x00000000 }, { 0x00600401, 0xea002288, 0x00cf8401, 0x00000000 }, { 0x00600401, 0xea202288, 0x00cf8421, 0x00000000 }, { 0x00600201, 0xed202288, 0x00cf8041, 0x00000000 }, { 0x00600201, 0xed402288, 0x00cf8061, 0x00000000 }, { 0x00800601, 0xc9202288, 0x00d28241, 0x00000000 }, { 0x00800601, 0xc9402288, 0x00d28261, 0x00000000 }, { 0x00600401, 0xeb202288, 0x00cf8441, 0x00000000 }, { 0x00600401, 0xeb402288, 0x00cf8461, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x060a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8018 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x06000600 }, { 0x00000040, 0x23840a28, 0x0e000364, 0x0000000c }, { 0x00000040, 0x24a40a28, 0x0e000364, 0x0000000e }, { 0x00600201, 0xec002288, 0x00cf8001, 0x00000000 }, { 0x00600201, 0xec202288, 0x00cf8021, 0x00000000 }, { 0x00800601, 0xc8002288, 0x00d28201, 0x00000000 }, { 0x00800601, 0xc8202288, 0x00d28221, 0x00000000 }, { 0x00600401, 0xea002288, 0x00cf8401, 0x00000000 }, { 0x00600401, 0xea202288, 0x00cf8421, 0x00000000 }, { 0x00600201, 0xed202288, 0x00cf8041, 0x00000000 }, { 0x00600201, 0xed402288, 0x00cf8061, 0x00000000 }, { 0x00800601, 0xc9202288, 0x00d28241, 0x00000000 }, { 0x00800601, 0xc9402288, 0x00d28261, 0x00000000 }, { 0x00600401, 0xeb202288, 0x00cf8441, 0x00000000 }, { 0x00600401, 0xeb402288, 0x00cf8461, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x060a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8018 }, { 0x00600001, 0x2fe00208, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20002220, 0x0e000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/pl3_to_pl2.asm000066400000000000000000000005131231401140700250700ustar00rootroot00000000000000// Module name: AVS .kernel PL3_TO_PL2 .code #include "VP_Setup.g8a" #include "Set_Layer_0.g8a" #include "Set_AVS_Buf_0123_PL3.g8a" #include "PL3_AVS_Buf_0.g8a" #include "PL3_AVS_Buf_1.g8a" #include "PL3_AVS_Buf_2.g8a" #include "PL3_AVS_Buf_3.g8a" #include "Save_AVS_NV12.g8a" #include "EOT.g8a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen8/pl3_to_pl2.g8b000066400000000000000000000337341231401140700250030ustar00rootroot00000000000000 { 0x00600001, 0x23600208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400208, 0x008d0000, 0x00000000 }, { 0x00600041, 0x20603ae8, 0x3a8d0060, 0x000000f0 }, { 0x00200001, 0x21141ae8, 0x004500e0, 0x00000000 }, { 0x01000010, 0x20002220, 0x1600005a, 0x00010001 }, { 0x00000008, 0x22201248, 0x16000044, 0x00000000 }, { 0x00000005, 0x22201248, 0x16000220, 0x00030003 }, { 0x01000010, 0x20001261, 0x16000220, 0x00010001 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000090 }, { 0x01000010, 0x20001261, 0x16000220, 0x00020002 }, { 0x00010020, 0x34000005, 0x0e001400, 0x000000f0 }, { 0x01000010, 0x20001261, 0x16000220, 0x00030003 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000180 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000114 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000118 }, { 0x00000020, 0x34000004, 0x0e001400, 0x000001a0 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000118 }, { 0x00000001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000120 }, { 0x00110001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000070 }, { 0x00110001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a01648, 0x10000000, 0xffffffff }, { 0x00000005, 0x23021288, 0x16000044, 0x00030003 }, { 0x00000001, 0x23203ae8, 0x000000f8, 0x00000000 }, { 0x00000001, 0x23383ae8, 0x000000f4, 0x00000000 }, { 0x00000001, 0x23303ae8, 0x00000060, 0x00000000 }, { 0x00000001, 0x23343ae8, 0x00000080, 0x00000000 }, { 0x00000001, 0x23283ae8, 0x000000c0, 0x00000000 }, { 0x00000001, 0x232c3ae8, 0x000000a0, 0x00000000 }, { 0x00000001, 0x233c0608, 0x00000000, 0x00000000 }, { 0x00000040, 0x233c0208, 0x0600033c, 0x08000000 }, { 0x00000001, 0x24083ae0, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24083ae0, 0x3e000060, 0x41000000 }, { 0x00000248, 0x22e83ae8, 0x3e0000f4, 0x41e00000 }, { 0x00000641, 0x22e43ae8, 0x3e000080, 0x40800000 }, { 0x00000001, 0x24103ae0, 0x00000060, 0x00000000 }, { 0x00000648, 0x22f03ae8, 0x3e0000f4, 0x41000000 }, { 0x00000401, 0x22f40608, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006ea2 }, { 0x00400040, 0x24001860, 0x16690400, 0x00460046 }, { 0x00400009, 0x22c01868, 0x16690400, 0x00050005 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006204 }, { 0x00400040, 0x24001860, 0x16690400, 0x00400040 }, { 0x00400209, 0x22401868, 0x16690400, 0x00050005 }, { 0x00000401, 0x22500608, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x28002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x28802248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb002 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x29002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000001 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2a002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2a802248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb002 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2b002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000002 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2c002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2c802248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb002 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2d002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000003 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2e002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2e802248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb002 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2f002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00600001, 0x23800208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00208, 0x008d0360, 0x00000000 }, { 0x00200201, 0x23801a28, 0x004500e0, 0x00000000 }, { 0x00000201, 0x24a01a28, 0x000000e0, 0x00000000 }, { 0x00000608, 0x24a41a28, 0x1e0000e2, 0x00010001 }, { 0x00000401, 0x23880608, 0x00000000, 0x000f000f }, { 0x00000401, 0x24a80608, 0x00000000, 0x0007000f }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8400, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8420, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8440, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8460, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc4001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xc4401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8000, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8020, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8040, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8060, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc0001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8c00, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8c20, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8c40, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8c60, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xcc001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xcc401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8800, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8820, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8840, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8860, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc8001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc8401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8400, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8420, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8440, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8460, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc4001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xc4401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8000, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8020, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8040, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8060, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc0001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8c00, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8c20, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8c40, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8c60, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xcc001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xcc401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8800, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8820, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8840, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8860, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc8001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc8401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00800201, 0x23a02288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x23b02288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x23c02288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x23d02288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x44c02288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x44d02288, 0x00cf8441, 0x00000000 }, { 0x00600601, 0x44c12288, 0x00cf8001, 0x00000000 }, { 0x00600401, 0x44d12288, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x00800201, 0x23e02288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x23f02288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24002288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24102288, 0x00d28a61, 0x00000000 }, { 0x00600201, 0x44e02288, 0x00cf8c01, 0x00000000 }, { 0x00600601, 0x44f02288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x44e12288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x44f12288, 0x00cf8841, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x00800201, 0x24202288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x24302288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x24402288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x24502288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x45002288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x45102288, 0x00cf8441, 0x00000000 }, { 0x00600601, 0x45012288, 0x00cf8001, 0x00000000 }, { 0x00600401, 0x45112288, 0x00cf8041, 0x00000000 }, { 0x00800201, 0x24602288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x24702288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24802288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24902288, 0x00d28a61, 0x00000000 }, { 0x00600201, 0x45202288, 0x00cf8c01, 0x00000000 }, { 0x00600601, 0x45302288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x45212288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x45312288, 0x00cf8841, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x120a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00208, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20002220, 0x0e000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/pl3_to_pl3.asm000066400000000000000000000005121231401140700250700ustar00rootroot00000000000000// Module name: AVS .kernel PL3_TO_PL3 .code #include "VP_Setup.g8a" #include "Set_Layer_0.g8a" #include "Set_AVS_Buf_0123_PL3.g8a" #include "PL3_AVS_Buf_0.g8a" #include "PL3_AVS_Buf_1.g8a" #include "PL3_AVS_Buf_2.g8a" #include "PL3_AVS_Buf_3.g8a" #include "Save_AVS_PL3.g8a" #include "EOT.g8a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen8/pl3_to_pl3.g8b000066400000000000000000000267031231401140700250020ustar00rootroot00000000000000 { 0x00600001, 0x23600208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400208, 0x008d0000, 0x00000000 }, { 0x00600041, 0x20603ae8, 0x3a8d0060, 0x000000f0 }, { 0x00200001, 0x21141ae8, 0x004500e0, 0x00000000 }, { 0x01000010, 0x20002220, 0x1600005a, 0x00010001 }, { 0x00000008, 0x22201248, 0x16000044, 0x00000000 }, { 0x00000005, 0x22201248, 0x16000220, 0x00030003 }, { 0x01000010, 0x20001261, 0x16000220, 0x00010001 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000090 }, { 0x01000010, 0x20001261, 0x16000220, 0x00020002 }, { 0x00010020, 0x34000005, 0x0e001400, 0x000000f0 }, { 0x01000010, 0x20001261, 0x16000220, 0x00030003 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000180 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000114 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000118 }, { 0x00000020, 0x34000004, 0x0e001400, 0x000001a0 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000118 }, { 0x00000001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000120 }, { 0x00110001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000070 }, { 0x00110001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a01648, 0x10000000, 0xffffffff }, { 0x00000005, 0x23021288, 0x16000044, 0x00030003 }, { 0x00000001, 0x23203ae8, 0x000000f8, 0x00000000 }, { 0x00000001, 0x23383ae8, 0x000000f4, 0x00000000 }, { 0x00000001, 0x23303ae8, 0x00000060, 0x00000000 }, { 0x00000001, 0x23343ae8, 0x00000080, 0x00000000 }, { 0x00000001, 0x23283ae8, 0x000000c0, 0x00000000 }, { 0x00000001, 0x232c3ae8, 0x000000a0, 0x00000000 }, { 0x00000001, 0x233c0608, 0x00000000, 0x00000000 }, { 0x00000040, 0x233c0208, 0x0600033c, 0x08000000 }, { 0x00000001, 0x24083ae0, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24083ae0, 0x3e000060, 0x41000000 }, { 0x00000248, 0x22e83ae8, 0x3e0000f4, 0x41e00000 }, { 0x00000641, 0x22e43ae8, 0x3e000080, 0x40800000 }, { 0x00000001, 0x24103ae0, 0x00000060, 0x00000000 }, { 0x00000648, 0x22f03ae8, 0x3e0000f4, 0x41000000 }, { 0x00000401, 0x22f40608, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006ea2 }, { 0x00400040, 0x24001860, 0x16690400, 0x00460046 }, { 0x00400009, 0x22c01868, 0x16690400, 0x00050005 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006204 }, { 0x00400040, 0x24001860, 0x16690400, 0x00400040 }, { 0x00400209, 0x22401868, 0x16690400, 0x00050005 }, { 0x00000401, 0x22500608, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x28002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x28802248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb002 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x29002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000001 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2a002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2a802248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb002 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2b002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000002 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2c002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2c802248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb002 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2d002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000d000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000003 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2e002248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb001 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2e802248, 0x00000200, 0x00000200 }, { 0x00000040, 0x22000200, 0x060002f4, 0x044eb002 }, { 0x00000001, 0x22080608, 0x00000000, 0x0000e000 }, { 0x02000031, 0x2f002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00600001, 0x23800208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x25c00208, 0x008d0360, 0x00000000 }, { 0x00200201, 0x23801a28, 0x004500e0, 0x00000000 }, { 0x00200208, 0x24a01a28, 0x1e4500e0, 0x00010001 }, { 0x00200208, 0x25c01a28, 0x1e4500e0, 0x00010001 }, { 0x00000401, 0x23880608, 0x00000000, 0x000f000f }, { 0x00000401, 0x24a80608, 0x00000000, 0x00070007 }, { 0x00000401, 0x25c80608, 0x00000000, 0x00070007 }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x80600040, 0xc4001248, 0x16ae8400, 0x00800080 }, { 0x80600040, 0xc4401248, 0x16ae8440, 0x00800080 }, { 0x80600040, 0xc0001248, 0x16ae8000, 0x00800080 }, { 0x80600040, 0xc0401248, 0x16ae8040, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x80600040, 0xcc001248, 0x16ae8c00, 0x00800080 }, { 0x80600040, 0xcc401248, 0x16ae8c40, 0x00800080 }, { 0x80600040, 0xc8001248, 0x16ae8800, 0x00800080 }, { 0x80600040, 0xc8401248, 0x16ae8840, 0x00800080 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x80600040, 0xc4001248, 0x16ae8400, 0x00800080 }, { 0x80600040, 0xc4401248, 0x16ae8440, 0x00800080 }, { 0x80600040, 0xc0001248, 0x16ae8000, 0x00800080 }, { 0x80600040, 0xc0401248, 0x16ae8040, 0x00800080 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x80600040, 0xcc001248, 0x16ae8c00, 0x00800080 }, { 0x80600040, 0xcc401248, 0x16ae8c40, 0x00800080 }, { 0x80600040, 0xc8001248, 0x16ae8800, 0x00800080 }, { 0x80600040, 0xc8401248, 0x16ae8840, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00800201, 0x23a02288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x23b02288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x23c02288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x23d02288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x24c02288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x24c82288, 0x00cf8441, 0x00000000 }, { 0x00600201, 0x25e02288, 0x00cf8001, 0x00000000 }, { 0x00600601, 0x25e82288, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x00800201, 0x23e02288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x23f02288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24002288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24102288, 0x00d28a61, 0x00000000 }, { 0x00600601, 0x24d02288, 0x00cf8c01, 0x00000000 }, { 0x00600401, 0x24d82288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x25f02288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x25f82288, 0x00cf8841, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x00800201, 0x24202288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x24302288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x24402288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x24502288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x24e02288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x24e82288, 0x00cf8441, 0x00000000 }, { 0x00600201, 0x26002288, 0x00cf8001, 0x00000000 }, { 0x00600601, 0x26082288, 0x00cf8041, 0x00000000 }, { 0x00800201, 0x24602288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x24702288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24802288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24902288, 0x00d28a61, 0x00000000 }, { 0x00600601, 0x24f02288, 0x00cf8c01, 0x00000000 }, { 0x00600401, 0x24f82288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x26102288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x26182288, 0x00cf8841, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x120a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x060a8019 }, { 0x0c000031, 0x20002220, 0x060005c0, 0x060a801a }, { 0x00600001, 0x2fe00208, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20002220, 0x0e000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/rgbx_to_nv12.asm000066400000000000000000000005441231401140700254310ustar00rootroot00000000000000// Module name: AVS .kernel RGBX_TO_NV12 .code #include "VP_Setup.g8a" #include "Set_Layer_0.g8a" #include "Set_AVS_Buf_0123_BGRA.g8a" #include "PA_AVS_Buf_0.g8a" #include "PA_AVS_Buf_1.g8a" #include "PA_AVS_Buf_2.g8a" #include "PA_AVS_Buf_3.g8a" #include "RGB_to_YUV.g8a" #include "Save_AVS_NV12.g8a" #include "EOT.g8a" .end_code .end_kernel intel-driver-1.3.0/src/shaders/post_processing/gen8/rgbx_to_nv12.g8b000066400000000000000000001070031231401140700253270ustar00rootroot00000000000000 { 0x00600001, 0x23600208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23200208, 0x008d0000, 0x00000000 }, { 0x00600001, 0x23400208, 0x008d0000, 0x00000000 }, { 0x00600041, 0x20603ae8, 0x3a8d0060, 0x000000f0 }, { 0x00200001, 0x21141ae8, 0x004500e0, 0x00000000 }, { 0x01000010, 0x20002220, 0x1600005a, 0x00010001 }, { 0x00000008, 0x22201248, 0x16000044, 0x00000000 }, { 0x00000005, 0x22201248, 0x16000220, 0x00030003 }, { 0x01000010, 0x20001261, 0x16000220, 0x00010001 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000090 }, { 0x01000010, 0x20001261, 0x16000220, 0x00020002 }, { 0x00010020, 0x34000005, 0x0e001400, 0x000000f0 }, { 0x01000010, 0x20001261, 0x16000220, 0x00030003 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000180 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000114 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000118 }, { 0x00000020, 0x34000004, 0x0e001400, 0x000001a0 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000118 }, { 0x00000001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000120 }, { 0x00110001, 0x220012e8, 0x00000040, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004114, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00000040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00000040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000220 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000070 }, { 0x00110001, 0x220012e8, 0x00000042, 0x00000000 }, { 0x00110040, 0x22203ae8, 0x3a004118, 0x00000200 }, { 0x00110040, 0x22203ae8, 0x3e000220, 0xc1800000 }, { 0x00110001, 0x24003ae0, 0x000000c0, 0x00000000 }, { 0x00110048, 0x20c03ae8, 0x3a000060, 0x00000220 }, { 0x00000001, 0x24003ae0, 0x000000a0, 0x00000000 }, { 0x00000048, 0x20a03ae8, 0x3a000080, 0x00000114 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00800001, 0x22a01648, 0x10000000, 0xffffffff }, { 0x00000005, 0x23021288, 0x16000044, 0x00030003 }, { 0x00000001, 0x23203ae8, 0x000000f8, 0x00000000 }, { 0x00000001, 0x23383ae8, 0x000000f4, 0x00000000 }, { 0x00000001, 0x23303ae8, 0x00000060, 0x00000000 }, { 0x00000001, 0x23343ae8, 0x00000080, 0x00000000 }, { 0x00000001, 0x23283ae8, 0x000000c0, 0x00000000 }, { 0x00000001, 0x232c3ae8, 0x000000a0, 0x00000000 }, { 0x00000001, 0x233c0608, 0x00000000, 0x00000000 }, { 0x00000040, 0x233c0208, 0x0600033c, 0x08000000 }, { 0x00000001, 0x24083ae0, 0x000000c0, 0x00000000 }, { 0x00000048, 0x24083ae0, 0x3e000060, 0x41000000 }, { 0x00000248, 0x22e83ae8, 0x3e0000f4, 0x41e00000 }, { 0x00000641, 0x22e43ae8, 0x3e000080, 0x40800000 }, { 0x00000001, 0x24103ae0, 0x00000060, 0x00000000 }, { 0x00000648, 0x22f03ae8, 0x3e0000f4, 0x41000000 }, { 0x00000401, 0x22f40608, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006ea2 }, { 0x00400040, 0x24001860, 0x16690400, 0x00460046 }, { 0x00400009, 0x22c01868, 0x16690400, 0x00050005 }, { 0x00400001, 0x24003660, 0x30000000, 0x00006204 }, { 0x00400040, 0x24001860, 0x16690400, 0x00400040 }, { 0x00400209, 0x22401868, 0x16690400, 0x00050005 }, { 0x00000401, 0x22500608, 0x00000000, 0x01000100 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000000 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x28002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000001 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2a002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000002 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2c002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000001, 0x22d00608, 0x00000000, 0x00400040 }, { 0x00000001, 0x220c0208, 0x0000000c, 0x00000000 }, { 0x00000040, 0x22000200, 0x060002f4, 0x050eb000 }, { 0x00000001, 0x22080608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23240608, 0x00000000, 0x00000003 }, { 0x00600001, 0x22200208, 0x008d0320, 0x00000000 }, { 0x02000031, 0x2e002248, 0x00000200, 0x00000200 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00400001, 0x22001240, 0x006902c0, 0x00000000 }, { 0x00400001, 0x22081240, 0x006902c0, 0x00000000 }, { 0x02800005, 0x20001260, 0x1e000040, 0x00010001 }, { 0x00010001, 0x22201048, 0x00000200, 0x00000000 }, { 0x00010001, 0x22001040, 0x00000202, 0x00000000 }, { 0x00010001, 0x22021240, 0x00000220, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8201, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8211, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8011, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa001648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac001648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8001648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca012288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc012288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8012288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8221, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8231, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8031, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa201648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac201648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8201648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca212288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc212288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8212288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8241, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8251, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8051, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa401648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac401648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8401648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca412288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc412288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8412288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8261, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8271, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8071, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa601648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac601648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8601648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca612288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc612288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8612288, 0x00cf05c0, 0x00000000 }, { 0x00600040, 0x22001040, 0x168d0200, 0x02000200 }, { 0x00600001, 0x238022e8, 0x00ae8201, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8211, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8011, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa001648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac001648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8001648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca012288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc012288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8012288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8221, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8231, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8031, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa201648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac201648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8201648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca212288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc212288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8212288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8241, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8251, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8051, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa401648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac401648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8401648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca412288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc412288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8412288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8261, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8271, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8071, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa601648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac601648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8601648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca612288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc612288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8612288, 0x00cf05c0, 0x00000000 }, { 0x00600040, 0x22001040, 0x168d0200, 0x02000200 }, { 0x00600001, 0x238022e8, 0x00ae8201, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8211, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8011, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa001648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac001648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8001648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca012288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc012288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8012288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8221, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8231, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8031, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa201648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac201648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8201648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca212288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc212288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8212288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8241, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8251, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8051, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa401648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac401648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8401648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca412288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc412288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8412288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8261, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8271, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8071, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa601648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac601648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8601648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca612288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc612288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8612288, 0x00cf05c0, 0x00000000 }, { 0x00600040, 0x22001040, 0x168d0200, 0x02000200 }, { 0x00600001, 0x238022e8, 0x00ae8201, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8211, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8401, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8411, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8001, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8011, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa001648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac001648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8001648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca012288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc012288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8012288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8221, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8231, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8421, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8431, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8021, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8031, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa201648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac201648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8201648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca212288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc212288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8212288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8241, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8251, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8441, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8451, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8041, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8051, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa401648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac401648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8401648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca412288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc412288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8412288, 0x00cf05c0, 0x00000000 }, { 0x00600001, 0x238022e8, 0x00ae8261, 0x00000000 }, { 0x00600001, 0x23a022e8, 0x00ae8271, 0x00000000 }, { 0x00600001, 0x23c022e8, 0x00ae8461, 0x00000000 }, { 0x00600001, 0x23e022e8, 0x00ae8471, 0x00000000 }, { 0x00600001, 0x240022e8, 0x00ae8061, 0x00000000 }, { 0x00600001, 0x242022e8, 0x00ae8071, 0x00000000 }, { 0x00800041, 0x24003ae0, 0x3e8d0380, 0x3e991687 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0x3f1645a2 }, { 0x00800048, 0x24803ae8, 0x3e8d0400, 0x3de978d5 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0xbe2d0e56 }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbea978d5 }, { 0x00800048, 0x24c03ae8, 0x3e8d0400, 0x3eff7cee }, { 0x00800001, 0x24003ee0, 0x38000000, 0x43000000 }, { 0x00800048, 0x24003ae0, 0x3e8d0380, 0x3eff7cee }, { 0x00800048, 0x24003ae0, 0x3e8d03c0, 0xbed60419 }, { 0x00800048, 0x25003ae8, 0x3e8d0400, 0xbda6809d }, { 0x00800001, 0x45403a68, 0x008d0480, 0x00000000 }, { 0x00800001, 0x45803a68, 0x008d04c0, 0x00000000 }, { 0x00800001, 0x45c03a68, 0x008d0500, 0x00000000 }, { 0x00800001, 0xaa601648, 0x10000000, 0x00000000 }, { 0x00800001, 0xac601648, 0x10000000, 0x00000000 }, { 0x00800001, 0xa8601648, 0x10000000, 0x00000000 }, { 0x00800001, 0xca612288, 0x00cf0540, 0x00000000 }, { 0x00800001, 0xcc612288, 0x00cf0580, 0x00000000 }, { 0x00800001, 0xc8612288, 0x00cf05c0, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00600001, 0x23800208, 0x008d0360, 0x00000000 }, { 0x00600001, 0x24a00208, 0x008d0360, 0x00000000 }, { 0x00200201, 0x23801a28, 0x004500e0, 0x00000000 }, { 0x00000201, 0x24a01a28, 0x000000e0, 0x00000000 }, { 0x00000608, 0x24a41a28, 0x1e0000e2, 0x00010001 }, { 0x00000401, 0x23880608, 0x00000000, 0x000f000f }, { 0x00000401, 0x24a80608, 0x00000000, 0x0007000f }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8400, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8420, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8440, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8460, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc4001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xc4401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8000, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8020, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8040, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8060, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc0001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8c00, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8c20, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8c40, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8c60, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xcc001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xcc401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8800, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8820, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8840, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8860, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc8001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc8401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x80800040, 0xa2001248, 0x16b18200, 0x00800080 }, { 0x80800040, 0xa2201248, 0x16b18220, 0x00800080 }, { 0x80800040, 0xa2401248, 0x16b18240, 0x00800080 }, { 0x80800040, 0xa2601248, 0x16b18260, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8400, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8420, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8440, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8460, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xc4001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xc4401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8000, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8020, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8040, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8060, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc0001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc0401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x80800040, 0xaa001248, 0x16b18a00, 0x00800080 }, { 0x80800040, 0xaa201248, 0x16b18a20, 0x00800080 }, { 0x80800040, 0xaa401248, 0x16b18a40, 0x00800080 }, { 0x80800040, 0xaa601248, 0x16b18a60, 0x00800080 }, { 0x00600008, 0x45c01248, 0x1eae8c00, 0x00010001 }, { 0x00600008, 0x45e01248, 0x1eae8c20, 0x00010001 }, { 0x00600008, 0x46001248, 0x1eae8c40, 0x00010001 }, { 0x00600008, 0x46201248, 0x1eae8c60, 0x00010001 }, { 0x00600040, 0x45c01248, 0x12ae05c0, 0x00ae05e0 }, { 0x80600040, 0xcc001248, 0x16ae05c0, 0x00800080 }, { 0x00600040, 0x46001248, 0x12ae0600, 0x00ae0620 }, { 0x80600040, 0xcc401248, 0x16ae0600, 0x00800080 }, { 0x00600008, 0x46401248, 0x1eae8800, 0x00010001 }, { 0x00600008, 0x46601248, 0x1eae8820, 0x00010001 }, { 0x00600008, 0x46801248, 0x1eae8840, 0x00010001 }, { 0x00600008, 0x46a01248, 0x1eae8860, 0x00010001 }, { 0x00600040, 0x46401248, 0x12ae0640, 0x00ae0660 }, { 0x80600040, 0xc8001248, 0x16ae0640, 0x00800080 }, { 0x00600040, 0x46801248, 0x12ae0680, 0x00ae06a0 }, { 0x80600040, 0xc8401248, 0x16ae0680, 0x00800080 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x02000200 }, { 0x00800201, 0x23a02288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x23b02288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x23c02288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x23d02288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x44c02288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x44d02288, 0x00cf8441, 0x00000000 }, { 0x00600601, 0x44c12288, 0x00cf8001, 0x00000000 }, { 0x00600401, 0x44d12288, 0x00cf8041, 0x00000000 }, { 0x00400040, 0x22001a40, 0x166902c0, 0x04000400 }, { 0x00800201, 0x23e02288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x23f02288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24002288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24102288, 0x00d28a61, 0x00000000 }, { 0x00600201, 0x44e02288, 0x00cf8c01, 0x00000000 }, { 0x00600601, 0x44f02288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x44e12288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x44f12288, 0x00cf8841, 0x00000000 }, { 0x00400040, 0x22081a40, 0x166902c0, 0x06000600 }, { 0x00800201, 0x24202288, 0x00d28201, 0x00000000 }, { 0x00800401, 0x24302288, 0x00d28221, 0x00000000 }, { 0x00800201, 0x24402288, 0x00d28241, 0x00000000 }, { 0x00800401, 0x24502288, 0x00d28261, 0x00000000 }, { 0x00600201, 0x45002288, 0x00cf8401, 0x00000000 }, { 0x00600601, 0x45102288, 0x00cf8441, 0x00000000 }, { 0x00600601, 0x45012288, 0x00cf8001, 0x00000000 }, { 0x00600401, 0x45112288, 0x00cf8041, 0x00000000 }, { 0x00800201, 0x24602288, 0x00d28a01, 0x00000000 }, { 0x00800401, 0x24702288, 0x00d28a21, 0x00000000 }, { 0x00800201, 0x24802288, 0x00d28a41, 0x00000000 }, { 0x00800401, 0x24902288, 0x00d28a61, 0x00000000 }, { 0x00600201, 0x45202288, 0x00cf8c01, 0x00000000 }, { 0x00600601, 0x45302288, 0x00cf8c41, 0x00000000 }, { 0x00600601, 0x45212288, 0x00cf8801, 0x00000000 }, { 0x00600401, 0x45312288, 0x00cf8841, 0x00000000 }, { 0x0c000031, 0x20002220, 0x06000380, 0x120a8018 }, { 0x0c000031, 0x20002220, 0x060004a0, 0x0a0a8019 }, { 0x00600001, 0x2fe00208, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20002220, 0x0e000fe0, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/sharpening_h_blur.g8b000066400000000000000000002563701231401140700265220ustar00rootroot00000000000000{ 0x00000001, 0x23401608, 0x00000000, 0x00000000 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000001, 0x23441608, 0x00000000, 0x00020002 }, { 0x00000001, 0x20480608, 0x00000000, 0x000f0007 }, { 0x00000001, 0x20401608, 0x00000000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000340, 0x02490000 }, { 0x00000001, 0x20443ae8, 0x00000028, 0x00000000 }, { 0x00000001, 0x202c1608, 0x00000000, 0x00040004 }, { 0x0c600031, 0x20403a08, 0x00000040, 0x00000200 }, { 0x00000040, 0x20240208, 0x1e000020, 0xfffcfffc }, { 0x06000010, 0x20000201, 0x16000024, 0x00040004 }, { 0x00200001, 0x23283ae8, 0x004500b0, 0x00000000 }, { 0x00200001, 0x23083ae8, 0x004500a0, 0x00000000 }, { 0x00200001, 0x22e83ae8, 0x00450090, 0x00000000 }, { 0x00200001, 0x22c83ae8, 0x00450080, 0x00000000 }, { 0x00200001, 0x22a83ae8, 0x00450070, 0x00000000 }, { 0x00200001, 0x22883ae8, 0x00450060, 0x00000000 }, { 0x00200001, 0x22683ae8, 0x00450050, 0x00000000 }, { 0x00200001, 0x22483ae8, 0x00450040, 0x00000000 }, { 0x00200001, 0x23383ae8, 0x004500b8, 0x00000000 }, { 0x00200001, 0x23183ae8, 0x004500a8, 0x00000000 }, { 0x00200001, 0x22f83ae8, 0x00450098, 0x00000000 }, { 0x00200001, 0x22d83ae8, 0x00450088, 0x00000000 }, { 0x00200001, 0x22b83ae8, 0x00450078, 0x00000000 }, { 0x00200001, 0x22983ae8, 0x00450068, 0x00000000 }, { 0x00200001, 0x22783ae8, 0x00450058, 0x00000000 }, { 0x00200001, 0x22583ae8, 0x00450048, 0x00000000 }, { 0x00010020, 0x34000005, 0x0e001400, 0x000067d0 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000340, 0x02490000 }, { 0x00200001, 0x22603ae8, 0x00450268, 0x00000000 }, { 0x00200001, 0x22403ae8, 0x00450248, 0x00000000 }, { 0x00200001, 0x22803ae8, 0x00450288, 0x00000000 }, { 0x00200001, 0x22c03ae8, 0x004502c8, 0x00000000 }, { 0x00200001, 0x22a03ae8, 0x004502a8, 0x00000000 }, { 0x00200001, 0x23203ae8, 0x00450328, 0x00000000 }, { 0x00000001, 0x20480608, 0x00000000, 0x000f0007 }, { 0x00200001, 0x23003ae8, 0x00450308, 0x00000000 }, { 0x00200001, 0x22e03ae8, 0x004502e8, 0x00000000 }, { 0x00000040, 0x20400208, 0x1600002c, 0x00040004 }, { 0x00000001, 0x20443ae8, 0x00000028, 0x00000000 }, { 0x0c600031, 0x20403a08, 0x00000040, 0x00000200 }, { 0x00200001, 0x22703ae8, 0x00450278, 0x00000000 }, { 0x00200001, 0x22503ae8, 0x00450258, 0x00000000 }, { 0x00200001, 0x22683ae8, 0x00450050, 0x00000000 }, { 0x00200001, 0x22483ae8, 0x00450040, 0x00000000 }, { 0x00200001, 0x22783ae8, 0x00450058, 0x00000000 }, { 0x00200001, 0x22583ae8, 0x00450048, 0x00000000 }, { 0x00000001, 0x204022e8, 0x00000240, 0x00000000 }, { 0x00200001, 0x22903ae8, 0x00450298, 0x00000000 }, { 0x00000001, 0x204422e8, 0x00000250, 0x00000000 }, { 0x00000001, 0x204822e8, 0x00000260, 0x00000000 }, { 0x00200001, 0x22883ae8, 0x00450060, 0x00000000 }, { 0x00200001, 0x22d03ae8, 0x004502d8, 0x00000000 }, { 0x00200001, 0x22b03ae8, 0x004502b8, 0x00000000 }, { 0x00200001, 0x22983ae8, 0x00450068, 0x00000000 }, { 0x00000001, 0x204c22e8, 0x00000270, 0x00000000 }, { 0x00200001, 0x22c83ae8, 0x00450080, 0x00000000 }, { 0x00200001, 0x22a83ae8, 0x00450070, 0x00000000 }, { 0x00000001, 0x205022e8, 0x00000280, 0x00000000 }, { 0x00200001, 0x22d83ae8, 0x00450088, 0x00000000 }, { 0x00200001, 0x22b83ae8, 0x00450078, 0x00000000 }, { 0x00200001, 0x23303ae8, 0x00450338, 0x00000000 }, { 0x00200001, 0x23103ae8, 0x00450318, 0x00000000 }, { 0x00200001, 0x22f03ae8, 0x004502f8, 0x00000000 }, { 0x00000001, 0x205422e8, 0x00000290, 0x00000000 }, { 0x00200001, 0x22e83ae8, 0x00450090, 0x00000000 }, { 0x00200001, 0x23083ae8, 0x004500a0, 0x00000000 }, { 0x00200001, 0x23283ae8, 0x004500b0, 0x00000000 }, { 0x00000001, 0x205822e8, 0x000002a0, 0x00000000 }, { 0x00000001, 0x206022e8, 0x000002c0, 0x00000000 }, { 0x00000001, 0x206422e8, 0x000002d0, 0x00000000 }, { 0x00000001, 0x205c22e8, 0x000002b0, 0x00000000 }, { 0x00200001, 0x23383ae8, 0x004500b8, 0x00000000 }, { 0x00200001, 0x23183ae8, 0x004500a8, 0x00000000 }, { 0x00200001, 0x22f83ae8, 0x00450098, 0x00000000 }, { 0x00000001, 0x206822e8, 0x000002e0, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c1, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000241, 0x00000000 }, { 0x00000001, 0x20303ee8, 0x00000000, 0x332bcc77 }, { 0x00000001, 0x21403ee8, 0x00000000, 0x3c1d98ad }, { 0x00000001, 0x206c22e8, 0x000002f0, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d1, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000251, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000261, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e1, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f1, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000271, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000281, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000301, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000311, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000291, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a1, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000321, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000331, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b1, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00000001, 0x208022e8, 0x00000242, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c2, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000252, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000262, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000272, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000282, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000292, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a2, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x00000001, 0x209c22e8, 0x000002b2, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d2, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x208022e8, 0x00000243, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e2, 0x00000000 }, { 0x00000001, 0x207022e8, 0x00000300, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f2, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000253, 0x00000000 }, { 0x00000001, 0x207422e8, 0x00000310, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000263, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000302, 0x00000000 }, { 0x00000001, 0x207822e8, 0x00000320, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000312, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000273, 0x00000000 }, { 0x00000001, 0x207c22e8, 0x00000330, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000283, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000322, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x20bc22e8, 0x00000332, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000293, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a3, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x209c22e8, 0x000002b3, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c3, 0x00000000 }, { 0x00000001, 0x21503ee8, 0x00000000, 0x3e525448 }, { 0x00000001, 0x21603ee8, 0x00000000, 0x3f11e168 }, { 0x00000001, 0x20a422e8, 0x000002d3, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e3, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f3, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000303, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20b422e8, 0x00000313, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000323, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000244, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000254, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000333, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x208822e8, 0x00000264, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000274, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c4, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d4, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000284, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000294, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e4, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f4, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a4, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b4, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000304, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000314, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x208022e8, 0x00000245, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000324, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000334, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000255, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000265, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x20a022e8, 0x000002c5, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000275, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000285, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d5, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e5, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000295, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a5, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f5, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000305, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b5, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20b422e8, 0x00000315, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000325, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000246, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000256, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000335, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x208822e8, 0x00000266, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000276, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c6, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000286, 0x00000000 }, { 0x00000001, 0x21703ee8, 0x00000000, 0x3875735f }, { 0x00000001, 0x20a422e8, 0x000002d6, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e6, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f6, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000306, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000296, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000316, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000326, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a6, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b6, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000336, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x208022e8, 0x00000247, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c7, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d7, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000257, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000267, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e7, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f7, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000277, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000287, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000307, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000317, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000297, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a7, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000327, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000337, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b7, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x20a022e8, 0x000002c8, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000248, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000258, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d8, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e8, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000268, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000278, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f8, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000308, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000288, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000298, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000318, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000328, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a8, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b8, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000338, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x21803a28, 0x00000100, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000104, 0x00000000 }, { 0x00000001, 0x61a00a88, 0x00000180, 0x00000000 }, { 0x00000001, 0x206022e8, 0x000002c1, 0x00000000 }, { 0x00000001, 0x204022e8, 0x00000241, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000242, 0x00000000 }, { 0x00000001, 0x61a80a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000108, 0x00000000 }, { 0x00000001, 0x61b00a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000010c, 0x00000000 }, { 0x00000001, 0x61b80a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000110, 0x00000000 }, { 0x00000001, 0x61c00a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000114, 0x00000000 }, { 0x00000001, 0x61c80a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000118, 0x00000000 }, { 0x00000001, 0x61d00a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000011c, 0x00000000 }, { 0x00000001, 0x61d80a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000120, 0x00000000 }, { 0x00000001, 0x61e00a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000124, 0x00000000 }, { 0x00000001, 0x61e80a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000128, 0x00000000 }, { 0x00000001, 0x61f00a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000012c, 0x00000000 }, { 0x00000001, 0x61f80a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000130, 0x00000000 }, { 0x00000001, 0x206422e8, 0x000002d1, 0x00000000 }, { 0x00000001, 0x204422e8, 0x00000251, 0x00000000 }, { 0x00000001, 0x62000a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000134, 0x00000000 }, { 0x00000001, 0x204822e8, 0x00000261, 0x00000000 }, { 0x00000001, 0x206822e8, 0x000002e1, 0x00000000 }, { 0x00000001, 0x206c22e8, 0x000002f1, 0x00000000 }, { 0x00000001, 0x204c22e8, 0x00000271, 0x00000000 }, { 0x00000001, 0x62080a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000138, 0x00000000 }, { 0x00000001, 0x205022e8, 0x00000281, 0x00000000 }, { 0x00000001, 0x207022e8, 0x00000301, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000252, 0x00000000 }, { 0x00000001, 0x207422e8, 0x00000311, 0x00000000 }, { 0x00000001, 0x205422e8, 0x00000291, 0x00000000 }, { 0x00000001, 0x62100a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000262, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000013c, 0x00000000 }, { 0x00000001, 0x205822e8, 0x000002a1, 0x00000000 }, { 0x00000001, 0x207822e8, 0x00000321, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000272, 0x00000000 }, { 0x00000001, 0x207c22e8, 0x00000331, 0x00000000 }, { 0x00000001, 0x205c22e8, 0x000002b1, 0x00000000 }, { 0x00000001, 0x62180a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000282, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c2, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000292, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d2, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e2, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f2, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000302, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000312, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a2, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000322, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000332, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b2, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00000001, 0x208022e8, 0x00000243, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c3, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x208422e8, 0x00000253, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d3, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000263, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000273, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e3, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f3, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000283, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000293, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000303, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000313, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a3, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b3, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000323, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000333, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x208022e8, 0x00000244, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a022e8, 0x000002c4, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000254, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000264, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d4, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e4, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000274, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000284, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f4, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000304, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000294, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a4, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000314, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000324, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b4, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20bc22e8, 0x00000334, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x208022e8, 0x00000245, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000255, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c5, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000265, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d5, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000275, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e5, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f5, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000285, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000295, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000305, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000315, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a5, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b5, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000325, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000335, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x208022e8, 0x00000246, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x20a022e8, 0x000002c6, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000256, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000266, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d6, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e6, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000276, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000286, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f6, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000306, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000296, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a6, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000316, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000326, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b6, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20bc22e8, 0x00000336, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x208022e8, 0x00000247, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000257, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c7, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d7, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000267, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000277, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e7, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f7, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000287, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000297, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000307, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000317, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a7, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b7, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000327, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000337, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x208022e8, 0x00000248, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c8, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000258, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000268, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000278, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000288, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000298, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a8, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x208022e8, 0x00000249, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000259, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000269, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000279, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000289, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000299, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a9, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d8, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b9, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x20a822e8, 0x000002e8, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f8, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000100, 0x00000000 }, { 0x00000001, 0x61a10a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000308, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000318, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000104, 0x00000000 }, { 0x00000001, 0x61a90a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000328, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000338, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000108, 0x00000000 }, { 0x00000001, 0x61b10a88, 0x00000220, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x20a022e8, 0x000002c9, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000010c, 0x00000000 }, { 0x00000001, 0x61b90a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d9, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e9, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000110, 0x00000000 }, { 0x00000001, 0x61c10a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f9, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000309, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000114, 0x00000000 }, { 0x00000001, 0x61c90a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000319, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000329, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000118, 0x00000000 }, { 0x00000001, 0x61d10a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000339, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x22203a28, 0x0000011c, 0x00000000 }, { 0x00000001, 0x61d90a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000120, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c3, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000243, 0x00000000 }, { 0x00000001, 0x206022e8, 0x000002c2, 0x00000000 }, { 0x00000001, 0x204022e8, 0x00000242, 0x00000000 }, { 0x00000001, 0x61e10a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000124, 0x00000000 }, { 0x00000001, 0x61e90a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000128, 0x00000000 }, { 0x00000001, 0x61f10a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000012c, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d3, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000253, 0x00000000 }, { 0x00000001, 0x61f90a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x206422e8, 0x000002d2, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e3, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000263, 0x00000000 }, { 0x00000001, 0x204422e8, 0x00000252, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000130, 0x00000000 }, { 0x00000001, 0x62010a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x204822e8, 0x00000262, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000273, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f3, 0x00000000 }, { 0x00000001, 0x206822e8, 0x000002e2, 0x00000000 }, { 0x00000001, 0x206c22e8, 0x000002f2, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000303, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000283, 0x00000000 }, { 0x00000001, 0x204c22e8, 0x00000272, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000134, 0x00000000 }, { 0x00000001, 0x62090a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x205022e8, 0x00000282, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000293, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000313, 0x00000000 }, { 0x00000001, 0x207022e8, 0x00000302, 0x00000000 }, { 0x00000001, 0x207422e8, 0x00000312, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000323, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a3, 0x00000000 }, { 0x00000001, 0x205422e8, 0x00000292, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000138, 0x00000000 }, { 0x00000001, 0x62110a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x205822e8, 0x000002a2, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b3, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000333, 0x00000000 }, { 0x00000001, 0x207822e8, 0x00000322, 0x00000000 }, { 0x00000001, 0x207c22e8, 0x00000332, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00000001, 0x205c22e8, 0x000002b2, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000013c, 0x00000000 }, { 0x00000001, 0x62190a88, 0x00000220, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x208022e8, 0x00000244, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c4, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000254, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d4, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000264, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e4, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f4, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000274, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000284, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000304, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000314, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000294, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a4, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000324, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000334, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b4, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a022e8, 0x000002c5, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000245, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000255, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d5, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e5, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000265, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000275, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f5, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000305, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000285, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000295, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000315, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000325, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a5, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b5, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000335, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x208022e8, 0x00000246, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c6, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d6, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000256, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000266, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e6, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f6, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000276, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000286, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000306, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000316, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000296, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a6, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000326, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000336, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b6, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x208022e8, 0x00000247, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x208422e8, 0x00000257, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c7, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000267, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000277, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d7, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e7, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000287, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000297, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f7, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000307, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a7, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b7, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000317, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000327, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x208022e8, 0x00000248, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000337, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x208422e8, 0x00000258, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000268, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c8, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d8, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000278, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000288, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e8, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f8, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000298, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a8, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000308, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000318, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x20b822e8, 0x00000328, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000338, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000249, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000259, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a022e8, 0x000002c9, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000269, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000279, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d9, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e9, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000289, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000299, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f9, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000309, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a9, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b9, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000319, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000329, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x20bc22e8, 0x00000339, 0x00000000 }, { 0x00000001, 0x208022e8, 0x0000024a, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x20a022e8, 0x000002ca, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025a, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026a, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002da, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ea, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027a, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028a, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fa, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030a, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029a, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002aa, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031a, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032a, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002ba, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x20bc22e8, 0x0000033a, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x22203a28, 0x00000100, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000104, 0x00000000 }, { 0x00000001, 0x41a22288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000108, 0x00000000 }, { 0x00000001, 0x41aa2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000010c, 0x00000000 }, { 0x00000001, 0x41b22288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000110, 0x00000000 }, { 0x00000001, 0x41ba2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000114, 0x00000000 }, { 0x00000001, 0x41c22288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000118, 0x00000000 }, { 0x00000001, 0x41ca2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000011c, 0x00000000 }, { 0x00000001, 0x41d22288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000120, 0x00000000 }, { 0x00000001, 0x41da2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000124, 0x00000000 }, { 0x00000001, 0x41e22288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x41ea2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000128, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c4, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000244, 0x00000000 }, { 0x00000001, 0x204022e8, 0x00000243, 0x00000000 }, { 0x00000001, 0x206022e8, 0x000002c3, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000012c, 0x00000000 }, { 0x00000001, 0x41f22288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d4, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000254, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000130, 0x00000000 }, { 0x00000001, 0x41fa2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x204422e8, 0x00000253, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e4, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000264, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x204822e8, 0x00000263, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f4, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000274, 0x00000000 }, { 0x00000001, 0x206422e8, 0x000002d3, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000134, 0x00000000 }, { 0x00000001, 0x42022288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x206822e8, 0x000002e3, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000284, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000304, 0x00000000 }, { 0x00000001, 0x204c22e8, 0x00000273, 0x00000000 }, { 0x00000001, 0x205022e8, 0x00000283, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000314, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000294, 0x00000000 }, { 0x00000001, 0x206c22e8, 0x000002f3, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000138, 0x00000000 }, { 0x00000001, 0x420a2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x207022e8, 0x00000303, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a4, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000324, 0x00000000 }, { 0x00000001, 0x205422e8, 0x00000293, 0x00000000 }, { 0x00000001, 0x205822e8, 0x000002a3, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000334, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b4, 0x00000000 }, { 0x00000001, 0x207422e8, 0x00000313, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000013c, 0x00000000 }, { 0x00000001, 0x42122288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x207822e8, 0x00000323, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00000001, 0x205c22e8, 0x000002b3, 0x00000000 }, { 0x00000001, 0x207c22e8, 0x00000333, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x00000001, 0x421a2288, 0x00000024, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x208022e8, 0x00000245, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c5, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000255, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d5, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000265, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000275, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e5, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f5, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000285, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000295, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000305, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000315, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a5, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b5, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000325, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000335, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x208022e8, 0x00000246, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a022e8, 0x000002c6, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000256, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000266, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d6, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e6, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000276, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000286, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f6, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000306, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000296, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a6, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000316, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000326, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b6, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20bc22e8, 0x00000336, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x208022e8, 0x00000247, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000257, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c7, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d7, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000267, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000277, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e7, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f7, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000287, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000297, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000307, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000317, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a7, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b7, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000327, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000337, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x208022e8, 0x00000248, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000258, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000268, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c8, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000278, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000288, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d8, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e8, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000298, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a8, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f8, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000308, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20b422e8, 0x00000318, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000328, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000249, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000259, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000338, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x208822e8, 0x00000269, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000279, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c9, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d9, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000289, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000299, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e9, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f9, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a9, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b9, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000309, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000319, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x208022e8, 0x0000024a, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000329, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000339, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025a, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026a, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a022e8, 0x000002ca, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027a, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028a, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002da, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ea, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029a, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002aa, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fa, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030a, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002ba, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031a, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032a, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x20bc22e8, 0x0000033a, 0x00000000 }, { 0x00000001, 0x208022e8, 0x0000024b, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x20a022e8, 0x000002cb, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025b, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026b, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002db, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002eb, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027b, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028b, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fb, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030b, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029b, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002ab, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031b, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032b, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002bb, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x20bc22e8, 0x0000033b, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x22203a28, 0x00000100, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000104, 0x00000000 }, { 0x00000001, 0x41a32288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000108, 0x00000000 }, { 0x00000001, 0x41ab2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000010c, 0x00000000 }, { 0x00000001, 0x41b32288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000110, 0x00000000 }, { 0x00000001, 0x41bb2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000114, 0x00000000 }, { 0x00000001, 0x41c32288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000118, 0x00000000 }, { 0x00000001, 0x41cb2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000011c, 0x00000000 }, { 0x00000001, 0x41d32288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000120, 0x00000000 }, { 0x00000001, 0x41db2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000124, 0x00000000 }, { 0x00000001, 0x41e32288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x41eb2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000128, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c5, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000245, 0x00000000 }, { 0x00000001, 0x206022e8, 0x000002c4, 0x00000000 }, { 0x00000001, 0x204022e8, 0x00000244, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000012c, 0x00000000 }, { 0x00000001, 0x41f32288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000130, 0x00000000 }, { 0x00000001, 0x41fb2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d5, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000255, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e5, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000265, 0x00000000 }, { 0x00000001, 0x206422e8, 0x000002d4, 0x00000000 }, { 0x00000001, 0x204422e8, 0x00000254, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000134, 0x00000000 }, { 0x00000001, 0x42032288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x204822e8, 0x00000264, 0x00000000 }, { 0x00000001, 0x206822e8, 0x000002e4, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000275, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f5, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000305, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000285, 0x00000000 }, { 0x00000001, 0x206c22e8, 0x000002f4, 0x00000000 }, { 0x00000001, 0x204c22e8, 0x00000274, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000138, 0x00000000 }, { 0x00000001, 0x420b2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x205022e8, 0x00000284, 0x00000000 }, { 0x00000001, 0x207022e8, 0x00000304, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000295, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000315, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000325, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a5, 0x00000000 }, { 0x00000001, 0x207422e8, 0x00000314, 0x00000000 }, { 0x00000001, 0x205422e8, 0x00000294, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000013c, 0x00000000 }, { 0x00000001, 0x42132288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x205822e8, 0x000002a4, 0x00000000 }, { 0x00000001, 0x207822e8, 0x00000324, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b5, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000335, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00000001, 0x207c22e8, 0x00000334, 0x00000000 }, { 0x00000001, 0x205c22e8, 0x000002b4, 0x00000000 }, { 0x00000001, 0x421b2288, 0x00000024, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x00000001, 0x208022e8, 0x00000246, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c6, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x208422e8, 0x00000256, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000266, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d6, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000276, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000286, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e6, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f6, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000296, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a6, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000306, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000316, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b6, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x20b822e8, 0x00000326, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000336, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000247, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000257, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a022e8, 0x000002c7, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000267, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000277, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d7, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e7, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000287, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000297, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f7, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000307, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a7, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b7, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000317, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000327, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x208022e8, 0x00000248, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000337, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x208422e8, 0x00000258, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000268, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c8, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d8, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000278, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000288, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e8, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f8, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000298, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a8, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000308, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000318, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b8, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000328, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x20bc22e8, 0x00000338, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000249, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000259, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000269, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x208c22e8, 0x00000279, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000289, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c9, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d9, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000299, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a9, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e9, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f9, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b9, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20b022e8, 0x00000309, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000319, 0x00000000 }, { 0x00000001, 0x208022e8, 0x0000024a, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025a, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000329, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000339, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026a, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027a, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x20a022e8, 0x000002ca, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028a, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029a, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002da, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ea, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002aa, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002ba, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fa, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030a, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x208022e8, 0x0000024b, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031a, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032a, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025b, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026b, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033a, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x208c22e8, 0x0000027b, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028b, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002cb, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002db, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029b, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002ab, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002eb, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fb, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002bb, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030b, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x20b422e8, 0x0000031b, 0x00000000 }, { 0x00000001, 0x208022e8, 0x0000024c, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025c, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026c, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027c, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028c, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029c, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002ac, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002bc, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x22203a28, 0x00000100, 0x00000000 }, { 0x00000001, 0x61a40a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000104, 0x00000000 }, { 0x00000001, 0x61ac0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032b, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000108, 0x00000000 }, { 0x00000001, 0x61b40a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033b, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x22203a28, 0x0000010c, 0x00000000 }, { 0x00000001, 0x61bc0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002cc, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002dc, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000110, 0x00000000 }, { 0x00000001, 0x61c40a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ec, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fc, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000114, 0x00000000 }, { 0x00000001, 0x61cc0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030c, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031c, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000118, 0x00000000 }, { 0x00000001, 0x61d40a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032c, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033c, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000011c, 0x00000000 }, { 0x00000001, 0x61dc0a88, 0x00000220, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x22203a28, 0x00000120, 0x00000000 }, { 0x00000001, 0x61e40a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000124, 0x00000000 }, { 0x00000001, 0x61ec0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000128, 0x00000000 }, { 0x00000001, 0x61f40a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000012c, 0x00000000 }, { 0x00000001, 0x61fc0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000130, 0x00000000 }, { 0x00000001, 0x62040a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000134, 0x00000000 }, { 0x00000001, 0x620c0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000138, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c6, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000246, 0x00000000 }, { 0x00000001, 0x206022e8, 0x000002c5, 0x00000000 }, { 0x00000001, 0x204022e8, 0x00000245, 0x00000000 }, { 0x00000001, 0x62140a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d6, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000256, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000266, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e6, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f6, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000276, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000286, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000306, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000316, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000296, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a6, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000326, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000336, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b6, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00000001, 0x206422e8, 0x000002d5, 0x00000000 }, { 0x00000001, 0x204422e8, 0x00000255, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000247, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c7, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000257, 0x00000000 }, { 0x00000001, 0x204822e8, 0x00000265, 0x00000000 }, { 0x00000001, 0x206822e8, 0x000002e5, 0x00000000 }, { 0x00000001, 0x206c22e8, 0x000002f5, 0x00000000 }, { 0x00000001, 0x204c22e8, 0x00000275, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000267, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000277, 0x00000000 }, { 0x00000001, 0x205022e8, 0x00000285, 0x00000000 }, { 0x00000001, 0x207022e8, 0x00000305, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d7, 0x00000000 }, { 0x00000001, 0x207422e8, 0x00000315, 0x00000000 }, { 0x00000001, 0x205422e8, 0x00000295, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000287, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e7, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000297, 0x00000000 }, { 0x00000001, 0x205822e8, 0x000002a5, 0x00000000 }, { 0x00000001, 0x207822e8, 0x00000325, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f7, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000013c, 0x00000000 }, { 0x00000001, 0x207c22e8, 0x00000335, 0x00000000 }, { 0x00000001, 0x205c22e8, 0x000002b5, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a7, 0x00000000 }, { 0x00000001, 0x621c0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000307, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b7, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x20b422e8, 0x00000317, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x20b822e8, 0x00000327, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000248, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000258, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000268, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000337, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000278, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000288, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a022e8, 0x000002c8, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000298, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a8, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d8, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e8, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20ac22e8, 0x000002f8, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000308, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000249, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000259, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000318, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000328, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000269, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000279, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000338, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x209022e8, 0x00000289, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000299, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c9, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d9, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a9, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b9, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e9, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f9, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x208022e8, 0x0000024a, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000309, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000319, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025a, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026a, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000329, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000339, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027a, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028a, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x20a022e8, 0x000002ca, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029a, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002aa, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002da, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ea, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002ba, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fa, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20b022e8, 0x0000030a, 0x00000000 }, { 0x00000001, 0x208022e8, 0x0000024b, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025b, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026b, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031a, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027b, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028b, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032a, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033a, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029b, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002ab, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x20a022e8, 0x000002cb, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002bb, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x20a422e8, 0x000002db, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002eb, 0x00000000 }, { 0x00000001, 0x208022e8, 0x0000024c, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025c, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fb, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030b, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026c, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027c, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031b, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032b, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028c, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029c, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033b, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x209822e8, 0x000002ac, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002bc, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002cc, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002dc, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x208022e8, 0x0000024d, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ec, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fc, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025d, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026d, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030c, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031c, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027d, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028d, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032c, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033c, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029d, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002ad, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x20a022e8, 0x000002cd, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002bd, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002dd, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x20a822e8, 0x000002ed, 0x00000000 }, { 0x00000001, 0x204022e8, 0x00000246, 0x00000000 }, { 0x00000001, 0x206022e8, 0x000002c6, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000100, 0x00000000 }, { 0x00000001, 0x61a50a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000104, 0x00000000 }, { 0x00000001, 0x61ad0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000108, 0x00000000 }, { 0x00000001, 0x61b50a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000010c, 0x00000000 }, { 0x00000001, 0x61bd0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000110, 0x00000000 }, { 0x00000001, 0x61c50a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fd, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000114, 0x00000000 }, { 0x00000001, 0x61cd0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030d, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031d, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000118, 0x00000000 }, { 0x00000001, 0x61d50a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032d, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033d, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000011c, 0x00000000 }, { 0x00000001, 0x61dd0a88, 0x00000220, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x22203a28, 0x00000120, 0x00000000 }, { 0x00000001, 0x61e50a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000124, 0x00000000 }, { 0x00000001, 0x61ed0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000128, 0x00000000 }, { 0x00000001, 0x61f50a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000012c, 0x00000000 }, { 0x00000001, 0x61fd0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000130, 0x00000000 }, { 0x00000001, 0x204422e8, 0x00000256, 0x00000000 }, { 0x00000001, 0x62050a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000134, 0x00000000 }, { 0x00000001, 0x204822e8, 0x00000266, 0x00000000 }, { 0x00000001, 0x204c22e8, 0x00000276, 0x00000000 }, { 0x00000001, 0x620d0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000138, 0x00000000 }, { 0x00000001, 0x205022e8, 0x00000286, 0x00000000 }, { 0x00000001, 0x205422e8, 0x00000296, 0x00000000 }, { 0x00000001, 0x62150a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x206422e8, 0x000002d6, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000013c, 0x00000000 }, { 0x00000001, 0x205822e8, 0x000002a6, 0x00000000 }, { 0x00000001, 0x206822e8, 0x000002e6, 0x00000000 }, { 0x00000001, 0x205c22e8, 0x000002b6, 0x00000000 }, { 0x00000001, 0x621d0a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x206c22e8, 0x000002f6, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c7, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000247, 0x00000000 }, { 0x00000001, 0x207022e8, 0x00000306, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d7, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000257, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000267, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e7, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f7, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000277, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000287, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000307, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000317, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000297, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a7, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000327, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000337, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b7, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00000001, 0x208022e8, 0x00000248, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x00000001, 0x208422e8, 0x00000258, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000268, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000278, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000288, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000298, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a8, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d8, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b8, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e8, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x208022e8, 0x00000249, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f8, 0x00000000 }, { 0x00000001, 0x207422e8, 0x00000316, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000308, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000259, 0x00000000 }, { 0x00000001, 0x207822e8, 0x00000326, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000269, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000318, 0x00000000 }, { 0x00000001, 0x207c22e8, 0x00000336, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000328, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000279, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x209022e8, 0x00000289, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000338, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x209422e8, 0x00000299, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a9, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c9, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d9, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b9, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e9, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20ac22e8, 0x000002f9, 0x00000000 }, { 0x00000001, 0x208022e8, 0x0000024a, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025a, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026a, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000309, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027a, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028a, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000319, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000329, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029a, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002aa, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000339, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x209c22e8, 0x000002ba, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x20a022e8, 0x000002ca, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002da, 0x00000000 }, { 0x00000001, 0x208022e8, 0x0000024b, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025b, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ea, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fa, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026b, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027b, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030a, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031a, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028b, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029b, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032a, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033a, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002ab, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002bb, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x20a022e8, 0x000002cb, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x208022e8, 0x0000024c, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002db, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002eb, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025c, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026c, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fb, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030b, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027c, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028c, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031b, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032b, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029c, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002ac, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033b, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x209c22e8, 0x000002bc, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002cc, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002dc, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x20a822e8, 0x000002ec, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fc, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030c, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031c, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032c, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033c, 0x00000000 }, { 0x00000001, 0x208022e8, 0x0000024d, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a022e8, 0x000002cd, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025d, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026d, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002dd, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ed, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027d, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028d, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fd, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030d, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029d, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002ad, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031d, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032d, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002bd, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x20bc22e8, 0x0000033d, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x208022e8, 0x0000024e, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025e, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002ce, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002de, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026e, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027e, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ee, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fe, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028e, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029e, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030e, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031e, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002ae, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002be, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032e, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033e, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x22203a28, 0x00000100, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000104, 0x00000000 }, { 0x00000001, 0x41a62288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x41ae2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000108, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x204022e8, 0x00000247, 0x00000000 }, { 0x00000001, 0x206022e8, 0x000002c7, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000010c, 0x00000000 }, { 0x00000001, 0x41b62288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000110, 0x00000000 }, { 0x00000001, 0x41be2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000114, 0x00000000 }, { 0x00000001, 0x41c62288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000118, 0x00000000 }, { 0x00000001, 0x41ce2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000011c, 0x00000000 }, { 0x00000001, 0x41d62288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000120, 0x00000000 }, { 0x00000001, 0x41de2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000124, 0x00000000 }, { 0x00000001, 0x41e62288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000128, 0x00000000 }, { 0x00000001, 0x41ee2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000012c, 0x00000000 }, { 0x00000001, 0x41f62288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000130, 0x00000000 }, { 0x00000001, 0x41fe2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x204422e8, 0x00000257, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000134, 0x00000000 }, { 0x00000001, 0x42062288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x204822e8, 0x00000267, 0x00000000 }, { 0x00000001, 0x204c22e8, 0x00000277, 0x00000000 }, { 0x00000001, 0x22203a28, 0x00000138, 0x00000000 }, { 0x00000001, 0x420e2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x205022e8, 0x00000287, 0x00000000 }, { 0x00000001, 0x205422e8, 0x00000297, 0x00000000 }, { 0x00000001, 0x22203a28, 0x0000013c, 0x00000000 }, { 0x00000001, 0x42162288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000220, 0x00000000 }, { 0x00000001, 0x205822e8, 0x000002a7, 0x00000000 }, { 0x00000001, 0x206422e8, 0x000002d7, 0x00000000 }, { 0x00000001, 0x205c22e8, 0x000002b7, 0x00000000 }, { 0x00000001, 0x421e2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x206822e8, 0x000002e7, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c8, 0x00000000 }, { 0x00000001, 0x208022e8, 0x00000248, 0x00000000 }, { 0x00000001, 0x206c22e8, 0x000002f7, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d8, 0x00000000 }, { 0x00000001, 0x208422e8, 0x00000258, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000268, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e8, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f8, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000278, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000288, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000308, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000318, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000298, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a8, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000328, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x00000338, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b8, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00000001, 0x208022e8, 0x00000249, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002c9, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872003 }, { 0x00000001, 0x208422e8, 0x00000259, 0x00000000 }, { 0x00000001, 0x208822e8, 0x00000269, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x00000279, 0x00000000 }, { 0x00000001, 0x209022e8, 0x00000289, 0x00000000 }, { 0x00000001, 0x209422e8, 0x00000299, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002a9, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002b9, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002d9, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x208022e8, 0x0000024a, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002e9, 0x00000000 }, { 0x00000001, 0x207022e8, 0x00000307, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002f9, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025a, 0x00000000 }, { 0x00000001, 0x207422e8, 0x00000317, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026a, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x00000309, 0x00000000 }, { 0x00000001, 0x207822e8, 0x00000327, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x00000319, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027a, 0x00000000 }, { 0x00000001, 0x207c22e8, 0x00000337, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028a, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x00000329, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72003 }, { 0x00000001, 0x20bc22e8, 0x00000339, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029a, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002aa, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a022e8, 0x000002ca, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002ba, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002da, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x20a822e8, 0x000002ea, 0x00000000 }, { 0x00000001, 0x208022e8, 0x0000024b, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fa, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025b, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026b, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030a, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031a, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027b, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028b, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032a, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033a, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029b, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002ab, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x20a022e8, 0x000002cb, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002bb, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00000001, 0x20a422e8, 0x000002db, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002eb, 0x00000000 }, { 0x00000001, 0x208022e8, 0x0000024c, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025c, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fb, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030b, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026c, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027c, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031b, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032b, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028c, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029c, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033b, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00000001, 0x209822e8, 0x000002ac, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002bc, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002cc, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002dc, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00000001, 0x208022e8, 0x0000024d, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ec, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fc, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025d, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026d, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030c, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031c, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027d, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028d, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032c, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033c, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029d, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002ad, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x00000001, 0x209c22e8, 0x000002bd, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002cd, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x20a422e8, 0x000002dd, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ed, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fd, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030d, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031d, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032d, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033d, 0x00000000 }, { 0x00000001, 0x208022e8, 0x0000024e, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00000001, 0x20a022e8, 0x000002ce, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025e, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026e, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002de, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ee, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027e, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028e, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002fe, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030e, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029e, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002ae, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031e, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032e, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002be, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072017 }, { 0x00000001, 0x20bc22e8, 0x0000033e, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472017 }, { 0x00000001, 0x208022e8, 0x0000024f, 0x00000000 }, { 0x00000001, 0x208422e8, 0x0000025f, 0x00000000 }, { 0x00000001, 0x20a022e8, 0x000002cf, 0x00000000 }, { 0x00000001, 0x20a422e8, 0x000002df, 0x00000000 }, { 0x00000001, 0x208822e8, 0x0000026f, 0x00000000 }, { 0x00000001, 0x208c22e8, 0x0000027f, 0x00000000 }, { 0x00000001, 0x20a822e8, 0x000002ef, 0x00000000 }, { 0x00000001, 0x20ac22e8, 0x000002ff, 0x00000000 }, { 0x00000001, 0x209022e8, 0x0000028f, 0x00000000 }, { 0x00000001, 0x209422e8, 0x0000029f, 0x00000000 }, { 0x00000001, 0x20b022e8, 0x0000030f, 0x00000000 }, { 0x00000001, 0x20b422e8, 0x0000031f, 0x00000000 }, { 0x00000001, 0x209822e8, 0x000002af, 0x00000000 }, { 0x00000001, 0x209c22e8, 0x000002bf, 0x00000000 }, { 0x00000001, 0x20b822e8, 0x0000032f, 0x00000000 }, { 0x00000001, 0x20bc22e8, 0x0000033f, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00000001, 0x20403a28, 0x00000100, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x00000104, 0x00000000 }, { 0x00000001, 0x41a72288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x41af2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x20403a28, 0x00000108, 0x00000000 }, { 0x00600001, 0x21803ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000344, 0x0a0a8000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x0000010c, 0x00000000 }, { 0x00000001, 0x41b72288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x00000110, 0x00000000 }, { 0x00000001, 0x41bf2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x00000114, 0x00000000 }, { 0x00000001, 0x41c72288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x00000118, 0x00000000 }, { 0x00000001, 0x41cf2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x0000011c, 0x00000000 }, { 0x00000001, 0x41d72288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x00000120, 0x00000000 }, { 0x00000001, 0x41df2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x00000124, 0x00000000 }, { 0x00000001, 0x41e72288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x00000128, 0x00000000 }, { 0x00000001, 0x41ef2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x0000012c, 0x00000000 }, { 0x00000001, 0x41f72288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x00000130, 0x00000000 }, { 0x00000001, 0x41ff2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x00000134, 0x00000000 }, { 0x00000001, 0x42072288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x00000138, 0x00000000 }, { 0x00000001, 0x420f2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x20403a28, 0x0000013c, 0x00000000 }, { 0x00000001, 0x42172288, 0x00000024, 0x00000000 }, { 0x00000001, 0x21880608, 0x00000000, 0x000f0007 }, { 0x00000001, 0x60240a88, 0x00000040, 0x00000000 }, { 0x00000001, 0x21803ae8, 0x0000002c, 0x00000000 }, { 0x00000001, 0x421f2288, 0x00000024, 0x00000000 }, { 0x00000001, 0x21843ae8, 0x00000028, 0x00000000 }, { 0x0c600031, 0x20003a00, 0x00000180, 0x00000200 }, { 0x00000040, 0x202c0208, 0x1600002c, 0x00080008 }, { 0x00000040, 0x20240208, 0x1e000020, 0xfffcfffc }, { 0x05000010, 0x20000200, 0x0200002c, 0x00000024 }, { 0x00010020, 0x34000004, 0x0e001400, 0xffff9830 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000340, 0x02290000 }, { 0x00000001, 0x20480608, 0x00000000, 0x000f0003 }, { 0x00000001, 0x20401608, 0x00000000, 0x00000000 }, { 0x00000001, 0x20443ae8, 0x00000028, 0x00000000 }, { 0x0c600031, 0x20403a08, 0x00000040, 0x00000200 }, { 0x00800001, 0x20603ae8, 0x008d0040, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000344, 0x060a8000 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000001, 0x20480608, 0x00000000, 0x000f0003 }, { 0x00000001, 0x20401608, 0x00000000, 0x00000000 }, { 0x00000001, 0x20443ae8, 0x00000028, 0x00000000 }, { 0x0c600031, 0x20003a00, 0x00000040, 0x00000200 }, { 0x00000040, 0x20240208, 0x1e000020, 0xfffcfffc }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000340, 0x02290000 }, { 0x00000001, 0x20480608, 0x00000000, 0x000f0003 }, { 0x00000001, 0x20403ae8, 0x00000024, 0x00000000 }, { 0x00000001, 0x20443ae8, 0x00000028, 0x00000000 }, { 0x0c600031, 0x20403a08, 0x00000040, 0x00000200 }, { 0x00800001, 0x20603ae8, 0x008d0040, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000344, 0x060a8000 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000001, 0x20480608, 0x00000000, 0x000f0003 }, { 0x00000001, 0x20403ae8, 0x00000024, 0x00000000 }, { 0x00000001, 0x20443ae8, 0x00000028, 0x00000000 }, { 0x0c600031, 0x20003a00, 0x00000040, 0x00000200 }, { 0x00600001, 0x2e003ae8, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20003a00, 0x06000e00, 0x82000010 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/sharpening_unmask.g8b000066400000000000000000000201141231401140700265260ustar00rootroot00000000000000{ 0x00000001, 0x21281608, 0x00000000, 0x00000000 }, { 0x00000001, 0x202c1608, 0x00000000, 0x00000000 }, { 0x00000001, 0x21481608, 0x00000000, 0x00050005 }, { 0x00000001, 0x21681608, 0x00000000, 0x00040004 }, { 0x00000001, 0x21881608, 0x00000000, 0x00020002 }, { 0x00000001, 0x21081608, 0x00000000, 0x00010001 }, { 0x06000010, 0x20000202, 0x16000020, 0x00000000 }, { 0x00010020, 0x34000006, 0x0e001400, 0x00000530 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000128, 0x02190000 }, { 0x06000010, 0x20000201, 0x16000030, 0x00000000 }, { 0x00000001, 0x20480608, 0x00000000, 0x00030003 }, { 0x00000001, 0x20403ae8, 0x0000002c, 0x00000000 }, { 0x00000001, 0x20443ae8, 0x00000028, 0x00000000 }, { 0x0c600031, 0x20603a08, 0x00000040, 0x00000200 }, { 0x00000040, 0x22000200, 0x06000188, 0x02190000 }, { 0x00400001, 0x21a03ae8, 0x00690060, 0x00000000 }, { 0x0c600031, 0x20403a08, 0x00000040, 0x00000200 }, { 0x00400001, 0x21c03ae8, 0x00690040, 0x00000000 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000150 }, { 0x00000001, 0x21821e68, 0x00000000, 0x00800080 }, { 0x00400001, 0x21703ae8, 0x006901a0, 0x00000000 }, { 0x00400001, 0x21503ae8, 0x006901c0, 0x00000000 }, { 0x0080802c, 0x21600008, 0x0e490000, 0x00000460 }, { 0x00000001, 0x210c1e68, 0x00000000, 0x00800080 }, { 0x00400001, 0x21703ae8, 0x006901a0, 0x00000000 }, { 0x00400001, 0x21503ae8, 0x00690150, 0x00000000 }, { 0x0080802c, 0x21200008, 0x0e490000, 0x000004e0 }, { 0x00400001, 0x21703ae8, 0x00690150, 0x00000000 }, { 0x00000001, 0x21801e68, 0x00000000, 0x00800080 }, { 0x00400001, 0x21503ae8, 0x00690150, 0x00000000 }, { 0x0080802c, 0x21000008, 0x0e490000, 0x00000550 }, { 0x00000001, 0x21801e68, 0x00000000, 0x00800080 }, { 0x0080802c, 0x21000008, 0x0e490000, 0x00000530 }, { 0x00000001, 0x41800268, 0x00000030, 0x00000000 }, { 0x00400001, 0x21703ae8, 0x00690150, 0x00000000 }, { 0x00000001, 0x20241a68, 0x00000180, 0x00000000 }, { 0x00400001, 0x21503ae8, 0x006901a0, 0x00000000 }, { 0x0080802c, 0x21000008, 0x0e490000, 0x000004e0 }, { 0x00400001, 0x21903ae8, 0x00690150, 0x00000000 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000010 }, { 0x00400001, 0x21903ae8, 0x006901a0, 0x00000000 }, { 0x01000010, 0x20000200, 0x16000034, 0x00000000 }, { 0x00010020, 0x34000004, 0x0e001400, 0x00000160 }, { 0x00000001, 0x21121e68, 0x00000000, 0x00800080 }, { 0x00400001, 0x21703ae8, 0x006901a0, 0x00000000 }, { 0x00400001, 0x21503ae8, 0x006901c0, 0x00000000 }, { 0x0080802c, 0x21800008, 0x0e490000, 0x00000560 }, { 0x00000001, 0x210c1e68, 0x00000000, 0x00800080 }, { 0x00400001, 0x21703ae8, 0x006901a0, 0x00000000 }, { 0x00400001, 0x21503ae8, 0x00690150, 0x00000000 }, { 0x0080802c, 0x21200008, 0x0e490000, 0x00000360 }, { 0x00600040, 0x41502288, 0x1eae4150, 0x00ff00ff }, { 0x00000001, 0x21101e68, 0x00000000, 0x00800080 }, { 0x00600040, 0x41512288, 0x1eae4151, 0x00ff00ff }, { 0x00400001, 0x21703ae8, 0x00690150, 0x00000000 }, { 0x0080802c, 0x21400008, 0x0e490000, 0x00000590 }, { 0x00000001, 0x21101e68, 0x00000000, 0x00800080 }, { 0x0080802c, 0x21400008, 0x0e490000, 0x00000570 }, { 0x00000001, 0x41100268, 0x00000034, 0x00000000 }, { 0x00400001, 0x21703ae8, 0x00690150, 0x00000000 }, { 0x00000001, 0x20241a68, 0x00000110, 0x00000000 }, { 0x00400001, 0x21503ae8, 0x00690190, 0x00000000 }, { 0x0080802c, 0x21400008, 0x0e490000, 0x00000520 }, { 0x00400001, 0x21e03ae8, 0x00690150, 0x00000000 }, { 0x00000020, 0x34000004, 0x0e001400, 0x00000010 }, { 0x00400001, 0x21e03ae8, 0x00690190, 0x00000000 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000168, 0x040a8000 }, { 0x00400001, 0x20603ae8, 0x006901e0, 0x00000000 }, { 0x00000001, 0x20480608, 0x00000000, 0x00030003 }, { 0x00000001, 0x20403ae8, 0x0000002c, 0x00000000 }, { 0x00000001, 0x20443ae8, 0x00000028, 0x00000000 }, { 0x0c600031, 0x20003a00, 0x00000040, 0x00000200 }, { 0x0000000c, 0x20240208, 0x16000028, 0x00010001 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000108, 0x02190000 }, { 0x00000001, 0x20480608, 0x00000000, 0x00010003 }, { 0x00000001, 0x20403ae8, 0x0000002c, 0x00000000 }, { 0x00000001, 0x20443ae8, 0x00000024, 0x00000000 }, { 0x0c600031, 0x20403a08, 0x00000040, 0x00000200 }, { 0x00200001, 0x20603ae8, 0x00450040, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000148, 0x040a8000 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000001, 0x20480608, 0x00000000, 0x00010003 }, { 0x00000001, 0x20403ae8, 0x0000002c, 0x00000000 }, { 0x00000001, 0x20443ae8, 0x00000024, 0x00000000 }, { 0x0c600031, 0x20003a00, 0x00000040, 0x00000200 }, { 0x00000040, 0x202c0208, 0x1600002c, 0x00040004 }, { 0x05000010, 0x20000203, 0x0200002c, 0x00000020 }, { 0x00010020, 0x34000007, 0x0e001400, 0xfffffad0 }, { 0x00600001, 0x2e003ae8, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20003a00, 0x06000e00, 0x82000010 }, { 0x00000040, 0x20241a28, 0x1e004182, 0x00800080 }, { 0x00800041, 0x20802228, 0x1ab10170, 0x00000182 }, { 0x05600010, 0x20002260, 0x22ae0170, 0x00ae0150 }, { 0x00600041, 0x20600a28, 0x22000024, 0x008d0158 }, { 0x00600041, 0x20400a28, 0x22000024, 0x008d0150 }, { 0x00800040, 0x20400a28, 0x0a8d0080, 0x008d0040 }, { 0x0080000c, 0x40400a68, 0x1e8d0040, 0x00070007 }, { 0x05601010, 0x20002260, 0x22ae0171, 0x00ae0151 }, { 0x00800001, 0x20401a68, 0x00ae0040, 0x00000000 }, { 0x00610001, 0x41501a88, 0x00ae0040, 0x00000000 }, { 0x00611001, 0x41511a88, 0x00ae0042, 0x00000000 }, { 0x0080002d, 0x20000220, 0x00450160, 0x00000000 }, { 0x00800040, 0x20402268, 0x22b10150, 0x00b14170 }, { 0x00000040, 0x20241a28, 0x1e00410c, 0x00800080 }, { 0x05800010, 0x20001a62, 0x1eb10040, 0x00000000 }, { 0x00810001, 0x20401a6a, 0x00b14040, 0x00000000 }, { 0x00600041, 0x20800a28, 0x22000024, 0x008d0158 }, { 0x00600041, 0x20600a28, 0x22000024, 0x008d0150 }, { 0x00800041, 0x20a01a28, 0x1a8d0040, 0x0000010c }, { 0x00800040, 0x20400a28, 0x0a8d00a0, 0x008d0060 }, { 0x0080000c, 0x60400a88, 0x1e8d0040, 0x00070007 }, { 0x00800001, 0x21502288, 0x00cf0040, 0x00000000 }, { 0x0080002d, 0x20000220, 0x00450120, 0x00000000 }, { 0x00800040, 0x20802228, 0x1eb14170, 0x00ff00ff }, { 0x00800040, 0x20402228, 0x1eb14150, 0x00ff00ff }, { 0x00000040, 0x20241a28, 0x1e004180, 0x00800080 }, { 0x00600041, 0x20c00a28, 0x0a8d0040, 0x008d0080 }, { 0x00600041, 0x20e00a28, 0x0a8d0060, 0x008d00a0 }, { 0x00000001, 0x20401e28, 0x00000000, 0x00ff00ff }, { 0x0c600038, 0x20800a28, 0x0a8d00e0, 0x00000040 }, { 0x0c600038, 0x20600a28, 0x0a8d00c0, 0x00000040 }, { 0x00800040, 0x40400a68, 0x1e8d4060, 0x00ff00ff }, { 0x00800001, 0x20401a68, 0x00ae0040, 0x00000000 }, { 0x00600041, 0x20800a28, 0x22000024, 0x008d0158 }, { 0x00800041, 0x20a01a28, 0x1a8d0040, 0x00000180 }, { 0x00600041, 0x20600a28, 0x22000024, 0x008d0150 }, { 0x00800040, 0x20400a28, 0x0a8d00a0, 0x008d0060 }, { 0x0080000c, 0x60400a88, 0x1e8d0040, 0x00070007 }, { 0x00800001, 0x21502288, 0x00cf0040, 0x00000000 }, { 0x0080002d, 0x20000220, 0x00450100, 0x00000000 }, { 0x00000040, 0x20241a28, 0x1e004112, 0x00800080 }, { 0x00800041, 0x20802228, 0x1ab10170, 0x00000112 }, { 0x03600010, 0x20002261, 0x22ae0170, 0x00ae0150 }, { 0x00600041, 0x20600a28, 0x22000024, 0x008d0158 }, { 0x00600041, 0x20400a28, 0x22000024, 0x008d0150 }, { 0x00800040, 0x20400a28, 0x0a8d0080, 0x008d0040 }, { 0x0080000c, 0x40400a68, 0x1e8d0040, 0x00070007 }, { 0x03601010, 0x20002261, 0x22ae0171, 0x00ae0151 }, { 0x00800001, 0x20401a68, 0x00ae0040, 0x00000000 }, { 0x00610001, 0x41501a89, 0x00ae0040, 0x00000000 }, { 0x00611001, 0x41511a89, 0x00ae0042, 0x00000000 }, { 0x0080002d, 0x20000220, 0x00450180, 0x00000000 }, { 0x00000001, 0x20801e28, 0x00000000, 0x00ff00ff }, { 0x00800041, 0x20402228, 0x22b10170, 0x00b10150 }, { 0x00000040, 0x20241a28, 0x1e004110, 0x00800080 }, { 0x0c600038, 0x20c00a28, 0x0a8d0060, 0x00000080 }, { 0x0c600038, 0x20a00a28, 0x0a8d0040, 0x00000080 }, { 0x00800001, 0x40400a68, 0x008d00a0, 0x00000000 }, { 0x00800001, 0x20401a68, 0x00ae0040, 0x00000000 }, { 0x00600041, 0x20800a28, 0x22000024, 0x008d0158 }, { 0x00800041, 0x20a01a28, 0x1a8d0040, 0x00000110 }, { 0x00600041, 0x20600a28, 0x22000024, 0x008d0150 }, { 0x00800040, 0x20400a28, 0x0a8d00a0, 0x008d0060 }, { 0x0080000c, 0x60400a88, 0x1e8d0040, 0x00070007 }, { 0x00800001, 0x21502288, 0x00cf0040, 0x00000000 }, { 0x0080002d, 0x20000220, 0x00450140, 0x00000000 }, intel-driver-1.3.0/src/shaders/post_processing/gen8/sharpening_v_blur.g8b000066400000000000000000000360401231401140700265260ustar00rootroot00000000000000{ 0x00000001, 0x23601608, 0x00000000, 0x00000000 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000001, 0x23641608, 0x00000000, 0x00020002 }, { 0x00000001, 0x20480608, 0x00000000, 0x0007000f }, { 0x00000001, 0x20403ae8, 0x0000002c, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000360, 0x02490000 }, { 0x00000001, 0x20441608, 0x00000000, 0x00000000 }, { 0x00000001, 0x20281608, 0x00000000, 0x00040004 }, { 0x0c600031, 0x22e03a08, 0x00000040, 0x00000200 }, { 0x00000040, 0x20200208, 0x1e000024, 0xfffcfffc }, { 0x06000010, 0x20000201, 0x16000020, 0x00040004 }, { 0x00010020, 0x34000005, 0x0e001400, 0x00000ff0 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000360, 0x02490000 }, { 0x00800001, 0x22a03ae8, 0x008d0320, 0x00000000 }, { 0x00800001, 0x22603ae8, 0x008d02e0, 0x00000000 }, { 0x00000001, 0x21403ee8, 0x00000000, 0x3e525448 }, { 0x00000001, 0x21603ee8, 0x00000000, 0x3875735f }, { 0x00000001, 0x20480608, 0x00000000, 0x0007000f }, { 0x00000001, 0x20403ae8, 0x0000002c, 0x00000000 }, { 0x00000040, 0x20440208, 0x16000028, 0x00040004 }, { 0x00800001, 0x208022e8, 0x00b10270, 0x00000000 }, { 0x0c600031, 0x22e03a08, 0x00000040, 0x00000200 }, { 0x00000001, 0x20203ee8, 0x00000000, 0x332bcc77 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00800001, 0x208022e8, 0x00b10280, 0x00000000 }, { 0x00800001, 0x204022e8, 0x00b10260, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x00000001, 0x20303ee8, 0x00000000, 0x3c1d98ad }, { 0x00800001, 0x204022e8, 0x00b10270, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b10290, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00000001, 0x21503ee8, 0x00000000, 0x3f11e168 }, { 0x00800001, 0x208022e8, 0x00b102a0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00800001, 0x208022e8, 0x00b102b0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b102c0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b102d0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00800001, 0x208022e8, 0x00b102e0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x00800001, 0x208022e8, 0x00b10280, 0x00000000 }, { 0x00800001, 0x21803a28, 0x008d0100, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00800001, 0x61800a88, 0x008d0180, 0x00000000 }, { 0x00800001, 0x21a02288, 0x00cf0180, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x00800001, 0x208022e8, 0x00b10290, 0x00000000 }, { 0x00800001, 0x204022e8, 0x00b10280, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b102a0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b102b0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00800001, 0x208022e8, 0x00b102c0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b102d0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b102e0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00800001, 0x208022e8, 0x00b102f0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x00800001, 0x208022e8, 0x00b10290, 0x00000000 }, { 0x00800001, 0x22203a28, 0x008d0100, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00800001, 0x62200a88, 0x008d0220, 0x00000000 }, { 0x00800001, 0x208022e8, 0x00b102a0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b102b0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b102c0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00800001, 0x208022e8, 0x00b102d0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b102e0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b102f0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00800001, 0x208022e8, 0x00b10300, 0x00000000 }, { 0x00800001, 0x21b02288, 0x00cf0220, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x00800001, 0x22203a28, 0x008d0100, 0x00000000 }, { 0x00800001, 0x62200a88, 0x008d0220, 0x00000000 }, { 0x00800001, 0x208022e8, 0x00b102a0, 0x00000000 }, { 0x00800001, 0x204022e8, 0x00b10290, 0x00000000 }, { 0x00800001, 0x21c02288, 0x00cf0220, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00800001, 0x208022e8, 0x00b102b0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x204022e8, 0x00b102a0, 0x00000000 }, { 0x00800001, 0x208022e8, 0x00b102c0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b102d0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00800001, 0x208022e8, 0x00b102e0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b102f0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b10300, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00800001, 0x208022e8, 0x00b10310, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x00800001, 0x208022e8, 0x00b102b0, 0x00000000 }, { 0x00800001, 0x22203a28, 0x008d0100, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00800001, 0x62200a88, 0x008d0220, 0x00000000 }, { 0x00800001, 0x208022e8, 0x00b102c0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b102d0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b102e0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00800001, 0x208022e8, 0x00b102f0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b10300, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x21d02288, 0x00cf0220, 0x00000000 }, { 0x00800001, 0x208022e8, 0x00b10310, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x00800001, 0x204022e8, 0x00b102b0, 0x00000000 }, { 0x00800001, 0x208022e8, 0x00b10320, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x00800001, 0x208022e8, 0x00b102c0, 0x00000000 }, { 0x00800001, 0x22203a28, 0x008d0100, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00800001, 0x62200a88, 0x008d0220, 0x00000000 }, { 0x00800001, 0x208022e8, 0x00b102d0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x204022e8, 0x00b102c0, 0x00000000 }, { 0x00800001, 0x208022e8, 0x00b102e0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b102f0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00800001, 0x208022e8, 0x00b10300, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b10310, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b10320, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00800001, 0x208022e8, 0x00b10330, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x00800001, 0x21e02288, 0x00cf0220, 0x00000000 }, { 0x00800001, 0x208022e8, 0x00b102d0, 0x00000000 }, { 0x00800001, 0x22203a28, 0x008d0100, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00800001, 0x62200a88, 0x008d0220, 0x00000000 }, { 0x00800001, 0x208022e8, 0x00b102e0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b102f0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b10300, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00800001, 0x21f02288, 0x00cf0220, 0x00000000 }, { 0x00800001, 0x208022e8, 0x00b10310, 0x00000000 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x00800001, 0x204022e8, 0x00b102d0, 0x00000000 }, { 0x00600001, 0x21803ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000364, 0x0a0a8000 }, { 0x00800001, 0x208022e8, 0x00b10320, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b10330, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00800001, 0x208022e8, 0x00b10340, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x00800001, 0x208022e8, 0x00b102e0, 0x00000000 }, { 0x00800001, 0x22203a28, 0x008d0100, 0x00000000 }, { 0x00800041, 0x20c03ae8, 0x3e8d0080, 0x3875735f }, { 0x00800001, 0x62200a88, 0x008d0220, 0x00000000 }, { 0x00800001, 0x208022e8, 0x00b102f0, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392071c8, 0x00c72002 }, { 0x0060015b, 0x081e0000, 0x392061c8, 0x00872002 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b10300, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b10310, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472015 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072015 }, { 0x00800001, 0x208022e8, 0x00b10320, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472014 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072014 }, { 0x00800001, 0x208022e8, 0x00b10330, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472003 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072003 }, { 0x00800001, 0x208022e8, 0x00b10340, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472016 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072016 }, { 0x00800001, 0x208022e8, 0x00b10350, 0x00000000 }, { 0x0060015b, 0x091e0000, 0x392091c8, 0x01472002 }, { 0x0060015b, 0x081e0000, 0x392081c8, 0x01072002 }, { 0x00000001, 0x21880608, 0x00000000, 0x0007000f }, { 0x00800001, 0x20403a28, 0x008d0100, 0x00000000 }, { 0x00000001, 0x21803ae8, 0x0000002c, 0x00000000 }, { 0x00800001, 0x22002288, 0x00cf0220, 0x00000000 }, { 0x00800001, 0x60400a88, 0x008d0040, 0x00000000 }, { 0x00800001, 0x22102288, 0x00cf0040, 0x00000000 }, { 0x00000001, 0x21843ae8, 0x00000028, 0x00000000 }, { 0x00000040, 0x20280208, 0x16000028, 0x00080008 }, { 0x0c600031, 0x20003a00, 0x00000180, 0x00000200 }, { 0x00000040, 0x20200208, 0x1e000024, 0xfffcfffc }, { 0x05000010, 0x20000200, 0x02000028, 0x00000020 }, { 0x00010020, 0x34000004, 0x0e001400, 0xfffff010 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000360, 0x02290000 }, { 0x00000001, 0x20480608, 0x00000000, 0x0003000f }, { 0x00000001, 0x20403ae8, 0x0000002c, 0x00000000 }, { 0x00000001, 0x20441608, 0x00000000, 0x00000000 }, { 0x0c600031, 0x22603a08, 0x00000040, 0x00000200 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000364, 0x060a8000 }, { 0x00800001, 0x20603ae8, 0x008d0260, 0x00000000 }, { 0x00000001, 0x20480608, 0x00000000, 0x0003000f }, { 0x00000001, 0x20403ae8, 0x0000002c, 0x00000000 }, { 0x00000001, 0x20441608, 0x00000000, 0x00000000 }, { 0x00000040, 0x20200208, 0x1e000024, 0xfffcfffc }, { 0x0c600031, 0x20003a00, 0x00000040, 0x00000200 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000360, 0x02290000 }, { 0x00000001, 0x20480608, 0x00000000, 0x0003000f }, { 0x00000001, 0x20403ae8, 0x0000002c, 0x00000000 }, { 0x00000001, 0x20443ae8, 0x00000020, 0x00000000 }, { 0x0c600031, 0x22603a08, 0x00000040, 0x00000200 }, { 0x00600001, 0x20403ae8, 0x008d0000, 0x00000000 }, { 0x00000040, 0x22000200, 0x06000364, 0x060a8000 }, { 0x00800001, 0x20603ae8, 0x008d0260, 0x00000000 }, { 0x00000001, 0x20480608, 0x00000000, 0x0003000f }, { 0x00000001, 0x20403ae8, 0x0000002c, 0x00000000 }, { 0x00000001, 0x20443ae8, 0x00000020, 0x00000000 }, { 0x0c600031, 0x20003a00, 0x00000040, 0x00000200 }, { 0x00600001, 0x2e003ae8, 0x008d0000, 0x00000000 }, { 0x07000031, 0x20003a00, 0x06000e00, 0x82000010 }, intel-driver-1.3.0/src/shaders/render/000077500000000000000000000000001231401140700176075ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/render/Makefile.am000066400000000000000000000071101231401140700216420ustar00rootroot00000000000000 INTEL_G4I = \ exa_wm.g4i \ exa_wm_affine.g4i \ exa_wm_yuv_color_balance.gxa \ exa_yuv_rgb.gxa \ exa_yuv_gen4.g4i \ exa_yuv_gen6.g4i INTEL_G4A = \ exa_sf.g4a \ exa_wm_xy.g4a \ exa_wm_src_affine.g4a \ exa_wm_src_sample_argb.g4a \ exa_wm_src_sample_planar.g4a \ exa_wm_yuv_color_balance.g4a \ exa_wm_yuv_rgb.g4a \ exa_wm_write.g4a INTEL_G4S = $(INTEL_G4A:%.g4a=%.g4s) INTEL_G4B = \ exa_sf.g4b \ exa_wm_xy.g4b \ exa_wm_src_affine.g4b \ exa_wm_src_sample_argb.g4b \ exa_wm_src_sample_planar.g4b \ exa_wm_yuv_color_balance.g4b \ exa_wm_yuv_rgb.g4b \ exa_wm_write.g4b INTEL_G4B_GEN5 = \ exa_sf.g4b.gen5 \ exa_wm_xy.g4b.gen5 \ exa_wm_src_affine.g4b.gen5 \ exa_wm_src_sample_argb.g4b.gen5 \ exa_wm_src_sample_planar.g4b.gen5 \ exa_wm_yuv_color_balance.g4b.gen5 \ exa_wm_yuv_rgb.g4b.gen5 \ exa_wm_write.g4b.gen5 INTEL_G6I = $(INTEL_G4I) INTEL_G6A = \ exa_wm_src_affine.g6a \ exa_wm_src_sample_argb.g6a \ exa_wm_src_sample_planar.g6a \ exa_wm_write.g6a \ exa_wm_yuv_color_balance.g6a \ exa_wm_yuv_rgb.g6a INTEL_G6S = $(INTEL_G6A:%.g6a=%.g6s) INTEL_G6B = \ exa_wm_src_affine.g6b \ exa_wm_src_sample_argb.g6b \ exa_wm_src_sample_planar.g6b \ exa_wm_write.g6b \ exa_wm_yuv_color_balance.g6b \ exa_wm_yuv_rgb.g6b INTEL_G7I = $(INTEL_G4I) INTEL_G7A = \ exa_wm_src_affine.g7a \ exa_wm_src_sample_argb.g7a \ exa_wm_src_sample_planar.g7a \ exa_wm_write.g7a \ exa_wm_yuv_color_balance.g7a \ exa_wm_yuv_rgb.g7a INTEL_G7S = $(INTEL_G7A:%.g7a=%.g7s) INTEL_G7B = \ exa_wm_src_affine.g7b \ exa_wm_src_sample_argb.g7b \ exa_wm_src_sample_planar.g7b \ exa_wm_write.g7b \ exa_wm_yuv_color_balance.g7b \ exa_wm_yuv_rgb.g7b # XXX: only regenerate binary for EU code containing JMPI instructions INTEL_G7B_HASWELL = \ exa_wm_src_sample_planar.g7b.haswell \ exa_wm_yuv_color_balance.g7b.haswell \ $(NULL) INTEL_G8A = \ exa_wm_src_affine.g8a \ exa_wm_src_sample_planar.g8a \ exa_wm_src_sample_argb.g8a \ exa_wm_yuv_color_balance.g8a \ exa_wm_write.g8a \ exa_wm_yuv_rgb.g8a INTEL_G8S = $(INTEL_G8A:%.g8a=%.g8s) INTEL_G8B = \ exa_wm_src_affine.g8b \ exa_wm_src_sample_planar.g8b \ exa_wm_src_sample_argb.g8b \ exa_wm_yuv_color_balance.g8b \ exa_wm_yuv_rgb.g8b \ exa_wm_write.g8b TARGETS = if HAVE_GEN4ASM TARGETS += $(INTEL_G4B) TARGETS += $(INTEL_G4B_GEN5) TARGETS += $(INTEL_G6B) TARGETS += $(INTEL_G7B) TARGETS += $(INTEL_G7B_HASWELL) TARGETS += $(INTEL_G8B) endif all-local: $(TARGETS) SUFFIXES = .g4a .g4s .g4b .g4b.gen5 .g6a .g6s .g6b .g7a .g7s .g7b .g7b.haswell .g8a .g8b .g8s if HAVE_GEN4ASM $(INTEL_G4S): $(INTEL_G4A) $(INTEL_G4I) .g4a.g4s: $(AM_V_GEN)m4 $< > $@ .g4s.g4b: $(AM_V_GEN)$(GEN4ASM) -o $@ $< .g4s.g4b.gen5: $(AM_V_GEN)$(GEN4ASM) -g 5 -o $@ $< $(INTEL_G6S): $(INTEL_G6A) $(INTEL_G6I) .g6a.g6s: $(AM_V_GEN)m4 $< > $@ .g6s.g6b: $(AM_V_GEN)$(GEN4ASM) -g 6 -o $@ $< $(INTEL_G7S): $(INTEL_G7A) $(INTEL_G7I) .g7a.g7s: $(AM_V_GEN)m4 $< > $@ .g7s.g7b: $(AM_V_GEN)$(GEN4ASM) -g 7 -o $@ $< .g7s.g7b.haswell: $(AM_V_GEN)$(GEN4ASM) -g 7.5 -o $@ $< $(INTEL_G8S): $(INTEL_G8A) $(INTEL_G8I) .g8a.g8s: $(AM_V_GEN)m4 $< > $@ .g8s.g8b: $(AM_V_GEN)$(GEN4ASM) -g 8 -o $@ $< endif CLEANFILES = \ $(INTEL_G4S) \ $(INTEL_G6S) \ $(INTEL_G7S) \ $(INTEL_G8S) \ $(NULL) EXTRA_DIST = \ $(INTEL_G4A) \ $(INTEL_G4B) \ $(INTEL_G4B_GEN5) \ $(INTEL_G4I) \ $(INTEL_G6A) \ $(INTEL_G6B) \ $(INTEL_G7A) \ $(INTEL_G7B) \ $(INTEL_G7B_HASWELL) \ $(INTEL_G8A) \ $(INTEL_G8B) \ $(NULL) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/render/exa_sf.g4a000066400000000000000000000057321231401140700214600ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Keith Packard * Eric Anholt * */ /* * Inputs (note all sub-register addresses are bytes, not float indices) * * Note that the vertices will have been reordered: * * V0 is topmost (leftmost among topmost) (upper left) * V1 is next clockwise (lower right) * V2 is remaining (lower left) * * V0 ...................... XX * | . * | . * | . * V2------------------------V1 * * G0 thread state -- just pass along * * G1 and G2 are fixed by SF spec * * G1.0 reserved * G1.4 Provoking vertex * G1.8 Determinant * G1.12 X1 - X0 * G1.16 X2 - X0 * G1.20 Y1 - Y0 * G1.24 Y2 - Y0 * G1.30 reserved * * G2.0 Z0 * G2.4 1/W0 * G2.8 Z1 * G2.12 1/W1 * G2.16 Z2 * G2.20 1/W2 * G2.24 reserved * G2.30 reserved * * G3 is V0 Vertex Attribute Data from URB (upper left) * * G3.0 u0 * G3.4 v0 * * G4 is V1 Vertex Attribute Data from URB (lower right) * * G4.0 u1 * G4.4 v1 * * G5 is V2 Vertex Attribute Data from URB (lower left) * */ /* Compute inverses of the input deltas */ send (4) 0 g6<1>F g1.12<4,4,1>F math inv mlen 1 rlen 1 { align1 }; /* texture location at V0 */ mov (4) m3<1>F g3<4,4,1>F { align1 }; /* compute V1 - V2 (motion in X) for texture coordinates */ add (4) g7<1>F g4<4,4,1>F -g5<4,4,1>F { align1 }; /* multiply by 1/dx */ mul (4) m1<1>F g7<4,4,1>F g6.0<0,1,0>F { align1 }; /* Compute V2 - V0 (motion in Y) for texture coordinates */ add (4) g7<1>F g5<4,4,1>F -g3<4,4,1>F { align1 }; /* multiply by 1/dy */ mul (4) m2<1>F g7<4,4,1>F g6.8<0,1,0>F {align1 }; /* and we're done */ send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT }; nop; nop; nop; nop; nop; nop; nop; nop; intel-driver-1.3.0/src/shaders/render/exa_sf.g4b000066400000000000000000000014711231401140700214550ustar00rootroot00000000000000 { 0x00400031, 0x20c01fbd, 0x0069002c, 0x01110001 }, { 0x00400001, 0x206003be, 0x00690060, 0x00000000 }, { 0x00400040, 0x20e077bd, 0x00690080, 0x006940a0 }, { 0x00400041, 0x202077be, 0x006900e0, 0x000000c0 }, { 0x00400040, 0x20e077bd, 0x006900a0, 0x00694060 }, { 0x00400041, 0x204077be, 0x006900e0, 0x000000c8 }, { 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/render/exa_sf.g4b.gen5000066400000000000000000000014711231401140700223120ustar00rootroot00000000000000 { 0x00400031, 0x20c01fbd, 0x1069002c, 0x02100001 }, { 0x00400001, 0x206003be, 0x00690060, 0x00000000 }, { 0x00400040, 0x20e077bd, 0x00690080, 0x006940a0 }, { 0x00400041, 0x202077be, 0x006900e0, 0x000000c0 }, { 0x00400040, 0x20e077bd, 0x006900a0, 0x00694060 }, { 0x00400041, 0x204077be, 0x006900e0, 0x000000c8 }, { 0x00600031, 0x20001fbc, 0x648d0000, 0x8808c800 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/render/exa_wm.g4i000066400000000000000000000123441231401140700215000ustar00rootroot00000000000000/* * Copyright © 2006-2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard */ /* * Input parameters */ /* Destination X/Y */ define(`dst_x_uw', `g1.8<2,4,0>UW') define(`dst_y_uw', `g1.10<2,4,0>UW') define(`screen_x0', `g1.0<0,1,0>F') define(`screen_y0', `g1.4<0,1,0>F') /* UV flag */ define(`interleaved_uv', `g2.0<0,1,0>UW') /* Source transformation parameters */ define(`src_du_dx', `g6.0<0,1,0>F') define(`src_du_dy', `g6.4<0,1,0>F') define(`src_uo', `g6.12<0,1,0>F') define(`src_dv_dx', `g6.16<0,1,0>F') define(`src_dv_dy', `g6.20<0,1,0>F') define(`src_vo', `g6.28<0,1,0>F') define(`src_dw_dx', `g7.0<0,1,0>F') define(`src_dw_dy', `g7.4<0,1,0>F') define(`src_wo', `g7.12<0,1,0>F') define(`mask_du_dx', `g8.0<0,1,0>F') define(`mask_du_dy', `g8.4<0,1,0>F') define(`mask_uo', `g8.12<0,1,0>F') define(`mask_dv_dx', `g8.16<0,1,0>F') define(`mask_dv_dy', `g8.20<0,1,0>F') define(`mask_vo', `g8.28<0,1,0>F') define(`mask_dw_dx', `g9.0<0,1,0>F') define(`mask_dw_dy', `g9.4<0,1,0>F') define(`mask_wo', `g9.12<0,1,0>F') /* Attribute for snb+ */ define(`a0_a_x',`g10.0<0,1,0>F') define(`a0_a_y',`g10.16<0,1,0>F') /* * Local variables. Pairs must be aligned on even reg boundry */ /* this holds the X dest coordinates */ define(`dst_x', `g42') define(`dst_x_0', `dst_x') define(`dst_x_1', `g43') /* this holds the Y dest coordinates */ define(`dst_y', `g44') define(`dst_y_0', `dst_y') define(`dst_y_1', `g45') /* When computing x * dn/dx, use this */ define(`temp_x', `g30') define(`temp_x_0', `temp_x') define(`temp_x_1', `g31') /* When computing y * dn/dy, use this */ define(`temp_y', `g28') define(`temp_y_0', temp_y) define(`temp_y_1', `g29') /* when loading x/y, use these to hold them in UW format */ define(`temp_x_uw', temp_x) define(`temp_y_uw', temp_y) /* compute source and mask u/v to this pair to send to sampler */ define(`src_msg', `m1') define(`src_msg_ind',`1') define(`src_u', `m2') define(`src_v', `m4') define(`src_w', `g12') define(`src_w_0', `src_w') define(`src_w_1', `g13') define(`mask_msg', `m7') define(`mask_msg_ind',`7') define(`mask_u', `m8') define(`mask_v', `m10') define(`mask_w', `src_w') define(`mask_w_0', `src_w_0') define(`mask_w_1', `src_w_1') /* sample src to these registers */ define(`src_sample_base', `g14') define(`src_sample_r', `g14') define(`src_sample_r_01', `g14') define(`src_sample_r_23', `g15') define(`src_sample_g', `g16') define(`src_sample_g_01', `g16') define(`src_sample_g_23', `g17') define(`src_sample_b', `g18') define(`src_sample_b_01', `g18') define(`src_sample_b_23', `g19') define(`src_sample_a', `g20') define(`src_sample_a_01', `g20') define(`src_sample_a_23', `g21') /* sample mask to these registers */ define(`mask_sample_base', `g22') define(`mask_sample_r', `g22') define(`mask_sample_r_01', `g22') define(`mask_sample_r_23', `g23') define(`mask_sample_g', `g24') define(`mask_sample_g_01', `g24') define(`mask_sample_g_23', `g25') define(`mask_sample_b', `g26') define(`mask_sample_b_01', `g26') define(`mask_sample_b_23', `g27') define(`mask_sample_a', `g28') define(`mask_sample_a_01', `g28') define(`mask_sample_a_23', `g29') /* Color Balance to these registers */ define(`color_balance_base', `g32') define(`color_balance_r', `g32') define(`color_balance_r_01', `g32') define(`color_balance_r_23', `g33') define(`color_balance_g', `g34') define(`color_balance_g_01', `g34') define(`color_balance_g_23', `g35') define(`color_balance_b', `g36') define(`color_balance_b_01', `g37') define(`color_balance_b_23', `g37') define(`color_balance_a', `g38') define(`color_balance_a_01', `g39') define(`color_balance_a_23', `g39') /* data port SIMD16 send registers */ define(`data_port_msg_0', `m0') define(`data_port_msg_0_ind', `0') define(`data_port_msg_1', `m1') define(`data_port_r_01', `m2') define(`data_port_g_01', `m3') define(`data_port_b_01', `m4') define(`data_port_a_01', `m5') define(`data_port_r_23', `m6') define(`data_port_g_23', `m7') define(`data_port_b_23', `m8') define(`data_port_a_23', `m9') intel-driver-1.3.0/src/shaders/render/exa_wm_affine.g4i000066400000000000000000000035331231401140700230100ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard */ /* * Fragment to compute src u/v values under an affine transform */ /********** Compute u *************/ mul (16) temp_x<1>F dst_x<8,8,1>F du_dx { compr align1 }; mul (16) temp_y<1>F dst_y<8,8,1>F du_dy { compr align1 }; add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 }; add (16) u<1>F temp_x<8,8,1>F uo { compr align1 }; /********** Compute v *************/ mul (16) temp_x<1>F dst_x<8,8,1>F dv_dx { compr align1 }; mul (16) temp_y<1>F dst_y<8,8,1>F dv_dy { compr align1 }; add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 }; add (16) v<1>F temp_x<8,8,1>F vo { compr align1 }; intel-driver-1.3.0/src/shaders/render/exa_wm_src_affine.g4a000066400000000000000000000030631231401140700236450ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard */ /* * Fragment to compute src u/v values under an affine transform */ include(`exa_wm.g4i') define(`du_dx', `src_du_dx') define(`du_dy', `src_du_dy') define(`uo', `src_uo') define(`dv_dx', `src_dv_dx') define(`dv_dy', `src_dv_dy') define(`vo', `src_vo') define(`u', `src_u') define(`v', `src_v') include(`exa_wm_affine.g4i') intel-driver-1.3.0/src/shaders/render/exa_wm_src_affine.g4b000066400000000000000000000006701231401140700236470ustar00rootroot00000000000000 { 0x00802041, 0x23c077bd, 0x008d0540, 0x000000c0 }, { 0x00802041, 0x238077bd, 0x008d0580, 0x000000c4 }, { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, { 0x00802040, 0x204077be, 0x008d03c0, 0x000000cc }, { 0x00802041, 0x23c077bd, 0x008d0540, 0x000000d0 }, { 0x00802041, 0x238077bd, 0x008d0580, 0x000000d4 }, { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, { 0x00802040, 0x208077be, 0x008d03c0, 0x000000dc }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_affine.g4b.gen5000066400000000000000000000006701231401140700245040ustar00rootroot00000000000000 { 0x00802041, 0x23c077bd, 0x008d0540, 0x000000c0 }, { 0x00802041, 0x238077bd, 0x008d0580, 0x000000c4 }, { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, { 0x00802040, 0x204077be, 0x008d03c0, 0x000000cc }, { 0x00802041, 0x23c077bd, 0x008d0540, 0x000000d0 }, { 0x00802041, 0x238077bd, 0x008d0580, 0x000000d4 }, { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, { 0x00802040, 0x208077be, 0x008d03c0, 0x000000dc }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_affine.g6a000066400000000000000000000031231231401140700236440ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * */ /* * Fragment to compute src u/v values */ include(`exa_wm.g4i') define(`ul', `src_u') define(`uh', `m3') define(`vl', `src_v') define(`vh', `m5') define(`bl', `g2.0<8,8,1>F') define(`bh', `g4.0<8,8,1>F') /* U */ pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ /* V */ pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ intel-driver-1.3.0/src/shaders/render/exa_wm_src_affine.g6b000066400000000000000000000003341231401140700236460ustar00rootroot00000000000000 { 0x0060005a, 0x204077be, 0x00000140, 0x008d0040 }, { 0x0060005a, 0x206077be, 0x00000140, 0x008d0080 }, { 0x0060005a, 0x208077be, 0x00000150, 0x008d0040 }, { 0x0060005a, 0x20a077be, 0x00000150, 0x008d0080 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_affine.g7a000066400000000000000000000031221231401140700236440ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * */ /* * Fragment to compute src u/v values */ include(`exa_wm.g4i') define(`ul', `g66') define(`uh', `g67') define(`vl', `g68') define(`vh', `g69') define(`bl', `g2.0<8,8,1>F') define(`bh', `g4.0<8,8,1>F') /* U */ pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ /* V */ pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ intel-driver-1.3.0/src/shaders/render/exa_wm_src_affine.g7b000066400000000000000000000003341231401140700236470ustar00rootroot00000000000000 { 0x0060005a, 0x284077bd, 0x00000140, 0x008d0040 }, { 0x0060005a, 0x286077bd, 0x00000140, 0x008d0080 }, { 0x0060005a, 0x288077bd, 0x00000150, 0x008d0040 }, { 0x0060005a, 0x28a077bd, 0x00000150, 0x008d0080 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_affine.g8a000066400000000000000000000031221231401140700236450ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * */ /* * Fragment to compute src u/v values */ include(`exa_wm.g4i') define(`ul', `g66') define(`uh', `g67') define(`vl', `g68') define(`vh', `g69') define(`bl', `g2.0<8,8,1>F') define(`bh', `g4.0<8,8,1>F') /* U */ pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ /* V */ pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ intel-driver-1.3.0/src/shaders/render/exa_wm_src_affine.g8b000066400000000000000000000003341231401140700236500ustar00rootroot00000000000000 { 0x0060005a, 0x28403ae8, 0x3a000140, 0x008d0040 }, { 0x0060005a, 0x28603ae8, 0x3a000140, 0x008d0080 }, { 0x0060005a, 0x28803ae8, 0x3a000150, 0x008d0040 }, { 0x0060005a, 0x28a03ae8, 0x3a000150, 0x008d0080 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_argb.g4a000066400000000000000000000042601231401140700246710ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard */ /* Sample the src surface */ include(`exa_wm.g4i') define(`global_alpha', `r2.0<0,1,0>f') /* prepare sampler read back gX register, which would be written back to output */ /* use simd16 sampler, param 0 is u, param 1 is v. */ /* 'payload' loading, assuming tex coord start from g4 */ /* load argb */ mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; /* src_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ send (16) src_msg_ind /* msg reg index */ src_sample_base<1>UW /* readback */ g0<8,8,1>UW /* copy to msg start reg*/ sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */ mul (8) src_sample_a_01<1>f src_sample_a_01<8,8,1>f global_alpha { align1 }; mul (8) src_sample_a_23<1>f src_sample_a_23<8,8,1>f global_alpha { align1 }; intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_argb.g4b000066400000000000000000000003341231401140700246700ustar00rootroot00000000000000 { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, { 0x01800031, 0x21c01d29, 0x008d0000, 0x02580001 }, { 0x00600041, 0x228077bd, 0x008d0280, 0x00000040 }, { 0x00600041, 0x22a077bd, 0x008d02a0, 0x00000040 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_argb.g4b.gen5000066400000000000000000000003341231401140700255250ustar00rootroot00000000000000 { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, { 0x01800031, 0x21c01d29, 0x208d0000, 0x0a8a0001 }, { 0x00600041, 0x228077bd, 0x008d0280, 0x00000040 }, { 0x00600041, 0x22a077bd, 0x008d02a0, 0x00000040 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_argb.g6a000066400000000000000000000043421231401140700246740ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard */ /* Sample the src surface */ include(`exa_wm.g4i') /* subpicture global alpha */ define(`global_alpha', `r6.0<0,1,0>f') /* prepare sampler read back gX register, which would be written back to output */ /* use simd16 sampler, param 0 is u, param 1 is v. */ /* 'payload' loading, assuming tex coord start from g4 */ /* load argb */ mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; mov (8) src_msg<1>UD g0<8,8,1>UD { align1 mask_disable }; /* src_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ send (16) src_msg_ind /* msg reg index */ src_sample_base<1>UW /* readback */ null sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */ mul (8) src_sample_a_01<1>f src_sample_a_01<8,8,1>f global_alpha { align1 }; mul (8) src_sample_a_23<1>f src_sample_a_23<1>f global_alpha { align1 }; intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_argb.g6b000066400000000000000000000004231231401140700246710ustar00rootroot00000000000000 { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, { 0x00600201, 0x20200022, 0x008d0000, 0x00000000 }, { 0x02800031, 0x21c01cc9, 0x00000020, 0x0a8a0001 }, { 0x00600041, 0x228077bd, 0x008d0280, 0x000000c0 }, { 0x00600041, 0x22a077bd, 0x002002a0, 0x000000c0 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_argb.g7a000066400000000000000000000046141231401140700246770ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard */ /* Sample the src surface */ include(`exa_wm.g4i') /* Ivybridge uses GRFs in SEND instruction */ define(`src_msg_gen7', `g65') define(`src_msg_ind_gen7',`65') /* subpicture global alpha */ define(`global_alpha', `r6.0<0,1,0>f') /* prepare sampler read back gX register, which would be written back to output */ /* use simd16 sampler, param 0 is u, param 1 is v. */ /* 'payload' loading, assuming tex coord start from g4 */ /* load argb */ mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; mov (8) src_msg_gen7<1>UD g0<8,8,1>UD { align1 mask_disable }; /* src_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ send (16) src_msg_ind_gen7 /* msg reg index */ src_sample_base<1>UW /* readback */ null sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */ mul (8) src_sample_a_01<1>f src_sample_a_01<8,8,1>f global_alpha { align1 mask_disable }; mul (8) src_sample_a_23<1>f src_sample_a_23<8,8,1>f global_alpha { align1 mask_disable }; intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_argb.g7b000066400000000000000000000004231231401140700246720ustar00rootroot00000000000000 { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, { 0x00600201, 0x28200021, 0x008d0000, 0x00000000 }, { 0x02800031, 0x21c01ca9, 0x00000820, 0x0a8c0001 }, { 0x00600241, 0x228077bd, 0x008d0280, 0x000000c0 }, { 0x00600241, 0x22a077bd, 0x008d02a0, 0x000000c0 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_argb.g8a000066400000000000000000000046141231401140700247000ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard */ /* Sample the src surface */ include(`exa_wm.g4i') /* Ivybridge uses GRFs in SEND instruction */ define(`src_msg_gen8', `g65') define(`src_msg_ind_gen8',`65') /* subpicture global alpha */ define(`global_alpha', `r6.0<0,1,0>f') /* prepare sampler read back gX register, which would be written back to output */ /* use simd16 sampler, param 0 is u, param 1 is v. */ /* 'payload' loading, assuming tex coord start from g4 */ /* load argb */ mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; /* src_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ send (16) src_msg_ind_gen8 /* msg reg index */ src_sample_base<1>UW /* readback */ null sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */ mul (8) src_sample_a_01<1>f src_sample_a_01<8,8,1>f global_alpha { align1 mask_disable }; mul (8) src_sample_a_23<1>f src_sample_a_23<8,8,1>f global_alpha { align1 mask_disable }; intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_argb.g8b000066400000000000000000000004231231401140700246730ustar00rootroot00000000000000 { 0x00000001, 0x2008060c, 0x00000000, 0x00000000 }, { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, { 0x02800031, 0x21c00a48, 0x0e000820, 0x0a8c0001 }, { 0x00600041, 0x22803aec, 0x3a8d0280, 0x000000c0 }, { 0x00600041, 0x22a03aec, 0x3a8d02a0, 0x000000c0 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_planar.g4a000066400000000000000000000065401231401140700252360ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard */ /* Sample the src surface in planar format */ include(`exa_wm.g4i') /* prepare sampler read back gX register, which would be written back to output */ /* use simd16 sampler, param 0 is u, param 1 is v. */ /* 'payload' loading, assuming tex coord start from g4 */ and.nz (1) null interleaved_uv 0x01UW {align1}; (f0) jmpi INTERLEAVED_UV; /* load r */ mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; /* src_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ /* sample U (Cr) */ send (16) src_msg_ind /* msg reg index */ src_sample_g<1>UW /* readback */ g0<8,8,1>UW /* copy to msg start reg*/ sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ /* sample V (Cb) */ send (16) src_msg_ind /* msg reg index */ src_sample_b<1>UW /* readback */ g0<8,8,1>UW /* copy to msg start reg*/ sampler (5,4,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ jmpi SAMPLE_Y; INTERLEAVED_UV: /* load r */ mov (1) g0.8<1>UD 0x0000c000UD { align1 mask_disable }; /* sample UV (CrCb) */ send (16) src_msg_ind /* msg reg index */ src_sample_g<1>UW /* readback */ g0<8,8,1>UW /* copy to msg start reg*/ sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 4 { align1 }; /* required message len 5, readback len 8 */ /* load r */ mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; SAMPLE_Y: /* sample Y */ send (16) src_msg_ind /* msg reg index */ src_sample_r<1>UW /* readback */ g0<8,8,1>UW /* copy to msg start reg*/ sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_planar.g4b000066400000000000000000000010461231401140700252330ustar00rootroot00000000000000 { 0x02000005, 0x20002d3c, 0x00000040, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000004 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x01800031, 0x22001d29, 0x008d0000, 0x02520203 }, { 0x01800031, 0x22401d29, 0x008d0000, 0x02520405 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000003 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000c000 }, { 0x01800031, 0x22001d29, 0x008d0000, 0x02540203 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x01800031, 0x21c01d29, 0x008d0000, 0x02520001 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_planar.g4b.gen5000066400000000000000000000010461231401140700260700ustar00rootroot00000000000000 { 0x02000005, 0x20002d3c, 0x00000040, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x01800031, 0x22001d29, 0x208d0000, 0x0a2a0203 }, { 0x01800031, 0x22401d29, 0x208d0000, 0x0a2a0405 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000c000 }, { 0x01800031, 0x22001d29, 0x208d0000, 0x0a4a0203 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x01800031, 0x21c01d29, 0x208d0000, 0x0a2a0001 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_planar.g6a000066400000000000000000000073251231401140700252420ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard */ /* Sample the src surface in planar format */ include(`exa_wm.g4i') /* UV flag */ define(`nv12', `g6.0<0,1,0>UW') /* prepare sampler read back gX register, which would be written back to output */ /* use simd16 sampler, param 0 is u, param 1 is v. */ /* 'payload' loading, assuming tex coord start from g4 */ cmp.g.f0.0 (1) null nv12 0x0UW {align1}; (f0.0) jmpi INTERLEAVED_UV; /* load r */ mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; mov (8) src_msg<1>UD g0<8,8,1>UD { align1 mask_disable }; /* src_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ /* sample U (Cr) */ send (16) src_msg_ind /* msg reg index */ src_sample_g<1>UW /* readback */ null sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ /* sample V (Cb) */ mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; mov (8) src_msg<1>UD g0<8,8,1>UD { align1 mask_disable }; send (16) src_msg_ind /* msg reg index */ src_sample_b<1>UW /* readback */ null sampler (5,4,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ jmpi SAMPLE_Y; INTERLEAVED_UV: mov (1) g0.8<1>UD 0x0000c000UD { align1 mask_disable }; mov (8) src_msg<1>UD g0<8,8,1>UD { align1 mask_disable }; /* sample UV (CrCb) */ send (16) src_msg_ind /* msg reg index */ src_sample_g<1>UW /* readback */ null sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 4 { align1 }; /* required message len 5, readback len 8 */ SAMPLE_Y: mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; mov (8) src_msg<1>UD g0<8,8,1>UD { align1 mask_disable }; /* sample Y */ send (16) src_msg_ind /* msg reg index */ src_sample_r<1>UW /* readback */ null sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_planar.g6b000066400000000000000000000014711231401140700252370ustar00rootroot00000000000000 { 0x03000010, 0x20002d3c, 0x000000c0, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x00600201, 0x20200022, 0x008d0000, 0x00000000 }, { 0x02800031, 0x22001cc9, 0x00000020, 0x0a2a0203 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x00600201, 0x20200022, 0x008d0000, 0x00000000 }, { 0x02800031, 0x22401cc9, 0x00000020, 0x0a2a0405 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000c000 }, { 0x00600201, 0x20200022, 0x008d0000, 0x00000000 }, { 0x02800031, 0x22001cc9, 0x00000020, 0x0a4a0203 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x00600201, 0x20200022, 0x008d0000, 0x00000000 }, { 0x02800031, 0x21c01cc9, 0x00000020, 0x0a2a0001 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_planar.g7a000066400000000000000000000101041231401140700252300ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard */ /* Sample the src surface in planar format */ include(`exa_wm.g4i') /* Ivybridge uses GRFs in SEND instruction */ define(`src_msg_gen7', `g65') define(`src_msg_ind_gen7',`65') /* UV flag */ define(`uv_flag', `g6.0<0,1,0>UW') /* prepare sampler read back gX register, which would be written back to output */ /* use simd16 sampler, param 0 is u, param 1 is v. */ /* 'payload' loading, assuming tex coord start from g4 */ cmp.e.f0.0 (1) null uv_flag 0x1UW {align1}; (f0.0) jmpi INTERLEAVED_UV; cmp.e.f0.0 (1) null uv_flag 0x2UW {align1}; (f0.0) jmpi CONSTANT_UV; /* load r */ mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; mov (8) src_msg_gen7<1>UD g0<8,8,1>UD { align1 mask_disable }; /* emit sampler 'send' cmd */ /* sample U (Cr) */ send (16) src_msg_ind_gen7 /* msg reg index */ src_sample_g<1>UW /* readback */ null sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ /* sample V (Cb) */ mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; mov (8) src_msg_gen7<1>UD g0<8,8,1>UD { align1 mask_disable }; send (16) src_msg_ind_gen7 /* msg reg index */ src_sample_b<1>UW /* readback */ null sampler (5,4,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ jmpi SAMPLE_Y; CONSTANT_UV: mov (16) src_sample_g<1>f 0.5f { compr align1 mask_disable }; mov (16) src_sample_b<1>f 0.5f { compr align1 mask_disable }; jmpi SAMPLE_Y; INTERLEAVED_UV: mov (1) g0.8<1>UD 0x0000c000UD { align1 mask_disable }; mov (8) src_msg_gen7<1>UD g0<8,8,1>UD { align1 mask_disable }; /* sample UV (CrCb) */ send (16) src_msg_ind_gen7 /* msg reg index */ src_sample_g<1>UW /* readback */ null sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 4 { align1 }; /* required message len 5, readback len 8 */ SAMPLE_Y: mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; mov (8) src_msg_gen7<1>UD g0<8,8,1>UD { align1 mask_disable }; /* sample Y */ send (16) src_msg_ind_gen7 /* msg reg index */ src_sample_r<1>UW /* readback */ null sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_planar.g7b000066400000000000000000000021141231401140700252330ustar00rootroot00000000000000 { 0x01000010, 0x20002d3c, 0x000000c0, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x01000010, 0x20002d3c, 0x000000c0, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x00600201, 0x28200021, 0x008d0000, 0x00000000 }, { 0x02800031, 0x22001ca9, 0x00000820, 0x0a2c0203 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x00600201, 0x28200021, 0x008d0000, 0x00000000 }, { 0x02800031, 0x22401ca9, 0x00000820, 0x0a2c0405 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x00800201, 0x220003fd, 0x00000000, 0x3f000000 }, { 0x00800201, 0x224003fd, 0x00000000, 0x3f000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000c000 }, { 0x00600201, 0x28200021, 0x008d0000, 0x00000000 }, { 0x02800031, 0x22001ca9, 0x00000820, 0x0a4c0203 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x00600201, 0x28200021, 0x008d0000, 0x00000000 }, { 0x02800031, 0x21c01ca9, 0x00000820, 0x0a2c0001 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_planar.g7b.haswell000066400000000000000000000021141231401140700266710ustar00rootroot00000000000000 { 0x01000010, 0x20002d3c, 0x000000c0, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000c0 }, { 0x01000010, 0x20002d3c, 0x000000c0, 0x00020002 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x00600201, 0x28200021, 0x008d0000, 0x00000000 }, { 0x02800031, 0x22001ca9, 0x00000820, 0x0a2c0203 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x00600201, 0x28200021, 0x008d0000, 0x00000000 }, { 0x02800031, 0x22401ca9, 0x00000820, 0x0a2c0405 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000060 }, { 0x00800201, 0x220003fd, 0x00000000, 0x3f000000 }, { 0x00800201, 0x224003fd, 0x00000000, 0x3f000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000c000 }, { 0x00600201, 0x28200021, 0x008d0000, 0x00000000 }, { 0x02800031, 0x22001ca9, 0x00000820, 0x0a4c0203 }, { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, { 0x00600201, 0x28200021, 0x008d0000, 0x00000000 }, { 0x02800031, 0x21c01ca9, 0x00000820, 0x0a2c0001 }, intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_planar.g8a000066400000000000000000000101541231401140700252360ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard * Zhao Yakui */ /* Sample the src surface in planar format */ include(`exa_wm.g4i') /* Ivybridge uses GRFs in SEND instruction */ define(`src_msg_gen8', `g65') define(`src_msg_ind_gen8',`65') /* UV flag */ define(`uv_flag', `g6.0<0,1,0>UW') /* prepare sampler read back gX register, which would be written back to output */ /* use simd16 sampler, param 0 is u, param 1 is v. */ /* 'payload' loading, assuming tex coord start from g4 */ cmp.e.f0.0 (1) null uv_flag 0x1UW {align1}; (f0.0) jmpi INTERLEAVED_UV; cmp.e.f0.0 (1) null uv_flag 0x2UW {align1}; (f0.0) jmpi CONSTANT_UV; /* load r */ mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; /* emit sampler 'send' cmd */ /* sample U (Cr) */ send (16) src_msg_ind_gen8 /* msg reg index */ src_sample_g<1>UW /* readback */ null sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ /* sample V (Cb) */ mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; send (16) src_msg_ind_gen8 /* msg reg index */ src_sample_b<1>UW /* readback */ null sampler (5,4,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ jmpi SAMPLE_Y; CONSTANT_UV: mov (16) src_sample_g<1>f 0.5f { compr align1 mask_disable }; mov (16) src_sample_b<1>f 0.5f { compr align1 mask_disable }; jmpi SAMPLE_Y; INTERLEAVED_UV: mov (1) g0.8<1>UD 0x0000c000UD { align1 mask_disable }; mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; /* sample UV (CrCb) */ send (16) src_msg_ind_gen8 /* msg reg index */ src_sample_g<1>UW /* readback */ null sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 4 { align1 }; /* required message len 5, readback len 8 */ SAMPLE_Y: mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; /* sample Y */ send (16) src_msg_ind_gen8 /* msg reg index */ src_sample_r<1>UW /* readback */ null sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ intel-driver-1.3.0/src/shaders/render/exa_wm_src_sample_planar.g8b000066400000000000000000000021141231401140700252340ustar00rootroot00000000000000 { 0x01000010, 0x200012e0, 0x160000c0, 0x00010001 }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000c0 }, { 0x01000010, 0x200012e0, 0x160000c0, 0x00020002 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000070 }, { 0x00000001, 0x2008060c, 0x00000000, 0x0000e000 }, { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, { 0x02800031, 0x22000a48, 0x0e000820, 0x0a2c0203 }, { 0x00000001, 0x2008060c, 0x00000000, 0x0000e000 }, { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, { 0x02800031, 0x22400a48, 0x0e000820, 0x0a2c0405 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000060 }, { 0x00800001, 0x22003eec, 0x38000000, 0x3f000000 }, { 0x00800001, 0x22403eec, 0x38000000, 0x3f000000 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000030 }, { 0x00000001, 0x2008060c, 0x00000000, 0x0000c000 }, { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, { 0x02800031, 0x22000a48, 0x0e000820, 0x0a4c0203 }, { 0x00000001, 0x2008060c, 0x00000000, 0x0000e000 }, { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, { 0x02800031, 0x21c00a48, 0x0e000820, 0x0a2c0001 }, intel-driver-1.3.0/src/shaders/render/exa_wm_write.g4a000066400000000000000000000057741231401140700227130ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard */ include(`exa_wm.g4i') /* * Prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2), * * Note that the SIMD16 write message takes data for the first * two sub-spans followed by the data for the second two sub-spans * instead of having the two sub-spans interleaved by channel. Weird. */ mov (8) data_port_r_01<1>F g14<8,8,1>F { align1 }; mov (8) data_port_g_01<1>F g16<8,8,1>F { align1 }; mov (8) data_port_b_01<1>F g18<8,8,1>F { align1 }; mov (8) data_port_a_01<1>F src_sample_a_01<8,8,1>F { align1 }; mov (8) data_port_r_23<1>F src_sample_r_23<8,8,1>F { sechalf align1 }; mov (8) data_port_g_23<1>F src_sample_g_23<8,8,1>F { sechalf align1 }; mov (8) data_port_b_23<1>F src_sample_b_23<8,8,1>F { sechalf align1 }; mov (8) data_port_a_23<1>F src_sample_a_23<8,8,1>F { sechalf align1 }; mov (8) data_port_r_01<1>F src_sample_r_01<8,8,1>F { align1 }; mov (8) data_port_g_01<1>F src_sample_g_01<8,8,1>F { align1 }; mov (8) data_port_b_01<1>F src_sample_b_01<8,8,1>F { align1 }; mov (8) data_port_a_01<1>F src_sample_a_01<8,8,1>F { align1 }; mov (8) data_port_r_23<1>F src_sample_r_23<8,8,1>F { sechalf align1 }; mov (8) data_port_g_23<1>F src_sample_g_23<8,8,1>F { sechalf align1 }; mov (8) data_port_b_23<1>F src_sample_b_23<8,8,1>F { sechalf align1 }; mov (8) data_port_a_23<1>F src_sample_a_23<8,8,1>F { sechalf align1 }; /* m0, m1 are all direct passed by PS thread payload */ mov (8) data_port_msg_1<1>UD g1<8,8,1>UD { mask_disable align1 }; /* write */ send (16) data_port_msg_0_ind acc0<1>UW g0<8,8,1>UW write ( 0, /* binding_table */ 8, /* pixel scordboard clear, msg type simd16 single source */ 4, /* render target write */ 0 /* no write commit message */ ) mlen 10 rlen 0 { align1 EOT }; nop; nop; nop; nop; nop; nop; nop; nop; intel-driver-1.3.0/src/shaders/render/exa_wm_write.g4b000066400000000000000000000026261231401140700227050ustar00rootroot00000000000000 { 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x206003be, 0x008d0200, 0x00000000 }, { 0x00600001, 0x208003be, 0x008d0240, 0x00000000 }, { 0x00600001, 0x20a003be, 0x008d0280, 0x00000000 }, { 0x00601001, 0x20c003be, 0x008d01e0, 0x00000000 }, { 0x00601001, 0x20e003be, 0x008d0220, 0x00000000 }, { 0x00601001, 0x210003be, 0x008d0260, 0x00000000 }, { 0x00601001, 0x212003be, 0x008d02a0, 0x00000000 }, { 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x206003be, 0x008d0200, 0x00000000 }, { 0x00600001, 0x208003be, 0x008d0240, 0x00000000 }, { 0x00600001, 0x20a003be, 0x008d0280, 0x00000000 }, { 0x00601001, 0x20c003be, 0x008d01e0, 0x00000000 }, { 0x00601001, 0x20e003be, 0x008d0220, 0x00000000 }, { 0x00601001, 0x210003be, 0x008d0260, 0x00000000 }, { 0x00601001, 0x212003be, 0x008d02a0, 0x00000000 }, { 0x00600201, 0x20200022, 0x008d0020, 0x00000000 }, { 0x00800031, 0x24001d28, 0x008d0000, 0x85a04800 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/render/exa_wm_write.g4b.gen5000066400000000000000000000026261231401140700235420ustar00rootroot00000000000000 { 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x206003be, 0x008d0200, 0x00000000 }, { 0x00600001, 0x208003be, 0x008d0240, 0x00000000 }, { 0x00600001, 0x20a003be, 0x008d0280, 0x00000000 }, { 0x00601001, 0x20c003be, 0x008d01e0, 0x00000000 }, { 0x00601001, 0x20e003be, 0x008d0220, 0x00000000 }, { 0x00601001, 0x210003be, 0x008d0260, 0x00000000 }, { 0x00601001, 0x212003be, 0x008d02a0, 0x00000000 }, { 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x206003be, 0x008d0200, 0x00000000 }, { 0x00600001, 0x208003be, 0x008d0240, 0x00000000 }, { 0x00600001, 0x20a003be, 0x008d0280, 0x00000000 }, { 0x00601001, 0x20c003be, 0x008d01e0, 0x00000000 }, { 0x00601001, 0x20e003be, 0x008d0220, 0x00000000 }, { 0x00601001, 0x210003be, 0x008d0260, 0x00000000 }, { 0x00601001, 0x212003be, 0x008d02a0, 0x00000000 }, { 0x00600201, 0x20200022, 0x008d0020, 0x00000000 }, { 0x00800031, 0x24001d28, 0x548d0000, 0x94084800 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/render/exa_wm_write.g6a000066400000000000000000000046411231401140700227050ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * */ include(`exa_wm.g4i') /* * Prepare data in m2-m3 for Red channel, m4-m5 for Green channel, * m6-m7 for Blue and m8-m9 for Alpha channel */ define(`slot_r_00', `m2') define(`slot_r_01', `m3') define(`slot_g_00', `m4') define(`slot_g_01', `m5') define(`slot_b_00', `m6') define(`slot_b_01', `m7') define(`slot_a_00', `m8') define(`slot_a_01', `m9') define(`data_port_msg_2_ind', `2') mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 }; mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 }; mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 }; mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 }; mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 }; mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 }; mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 }; mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 }; /* write */ send (16) data_port_msg_2_ind acc0<1>UW null write ( 0, /* binding_table */ 16, /* pixel scordboard clear, msg type simd16 single source */ 12, /* render target write */ 0, /* no write commit message */ 0 /* headerless render target write */ ) mlen 8 rlen 0 { align1 EOT }; nop; nop; nop; nop; nop; nop; nop; nop; intel-driver-1.3.0/src/shaders/render/exa_wm_write.g6b000066400000000000000000000016471231401140700227110ustar00rootroot00000000000000 { 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x206003be, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x208003be, 0x008d0200, 0x00000000 }, { 0x00600001, 0x20a003be, 0x008d0220, 0x00000000 }, { 0x00600001, 0x20c003be, 0x008d0240, 0x00000000 }, { 0x00600001, 0x20e003be, 0x008d0260, 0x00000000 }, { 0x00600001, 0x210003be, 0x008d0280, 0x00000000 }, { 0x00600001, 0x212003be, 0x008d02a0, 0x00000000 }, { 0x05800031, 0x24001cc8, 0x00000040, 0x90019000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/render/exa_wm_write.g7a000066400000000000000000000053751231401140700227130ustar00rootroot00000000000000/* * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * */ include(`exa_wm.g4i') /* header */ define(`data_port_msg_2_0', `g64') define(`data_port_msg_2_1', `g65') define(`data_port_msg_2_ind', `64') mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable}; mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable}; /* * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel, * g70-g71 for Blue and g72-g73 for Alpha channel */ define(`slot_r_00', `g66') define(`slot_r_01', `g67') define(`slot_g_00', `g68') define(`slot_g_01', `g69') define(`slot_b_00', `g70') define(`slot_b_01', `g71') define(`slot_a_00', `g72') define(`slot_a_01', `g73') mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 mask_disable }; mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 mask_disable }; mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 mask_disable }; mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 mask_disable }; mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 mask_disable }; mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 mask_disable }; mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 mask_disable }; mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 mask_disable }; send (16) data_port_msg_2_ind null<1>UW null write ( 0, /* binding table index */ 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */ 12, /* render target write */ 0, /* ignore for Ivybridge */ 1 /* header present */ ) mlen 10 rlen 0 { align1 EOT }; nop; nop; nop; nop; nop; nop; nop; nop; intel-driver-1.3.0/src/shaders/render/exa_wm_write.g7b000066400000000000000000000020251231401140700227010ustar00rootroot00000000000000 { 0x00600201, 0x28000021, 0x008d0000, 0x00000000 }, { 0x00600201, 0x28200021, 0x008d0020, 0x00000000 }, { 0x00600201, 0x284003bd, 0x008d01c0, 0x00000000 }, { 0x00600201, 0x286003bd, 0x008d01e0, 0x00000000 }, { 0x00600201, 0x288003bd, 0x008d0200, 0x00000000 }, { 0x00600201, 0x28a003bd, 0x008d0220, 0x00000000 }, { 0x00600201, 0x28c003bd, 0x008d0240, 0x00000000 }, { 0x00600201, 0x28e003bd, 0x008d0260, 0x00000000 }, { 0x00600201, 0x290003bd, 0x008d0280, 0x00000000 }, { 0x00600201, 0x292003bd, 0x008d02a0, 0x00000000 }, { 0x05800031, 0x20001ca8, 0x00000800, 0x940b1000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/render/exa_wm_write.g8a000066400000000000000000000053751231401140700227140ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * */ include(`exa_wm.g4i') /* header */ define(`data_port_msg_2_0', `g64') define(`data_port_msg_2_1', `g65') define(`data_port_msg_2_ind', `64') mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable}; mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable}; /* * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel, * g70-g71 for Blue and g72-g73 for Alpha channel */ define(`slot_r_00', `g66') define(`slot_r_01', `g67') define(`slot_g_00', `g68') define(`slot_g_01', `g69') define(`slot_b_00', `g70') define(`slot_b_01', `g71') define(`slot_a_00', `g72') define(`slot_a_01', `g73') mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 mask_disable }; mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 mask_disable }; mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 mask_disable }; mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 mask_disable }; mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 mask_disable }; mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 mask_disable }; mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 mask_disable }; mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 mask_disable }; send (16) data_port_msg_2_ind null<1>UW null write ( 0, /* binding table index */ 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */ 12, /* render target write */ 0, /* ignore for Ivybridge */ 1 /* header present */ ) mlen 10 rlen 0 { align1 EOT }; nop; nop; nop; nop; nop; nop; nop; nop; intel-driver-1.3.0/src/shaders/render/exa_wm_write.g8b000066400000000000000000000020251231401140700227020ustar00rootroot00000000000000 { 0x00600001, 0x2800020c, 0x008d0000, 0x00000000 }, { 0x00600001, 0x2820020c, 0x008d0020, 0x00000000 }, { 0x00600001, 0x28403aec, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28603aec, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28803aec, 0x008d0200, 0x00000000 }, { 0x00600001, 0x28a03aec, 0x008d0220, 0x00000000 }, { 0x00600001, 0x28c03aec, 0x008d0240, 0x00000000 }, { 0x00600001, 0x28e03aec, 0x008d0260, 0x00000000 }, { 0x00600001, 0x29003aec, 0x008d0280, 0x00000000 }, { 0x00600001, 0x29203aec, 0x008d02a0, 0x00000000 }, { 0x05800031, 0x20000a40, 0x0e000800, 0x940b1000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/render/exa_wm_xy.g4a000066400000000000000000000035371231401140700222140ustar00rootroot00000000000000/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Wang Zhenyu * Keith Packard */ /* * Register assignments: * * x g6/g7 * y g8/g9 * * temp x g10/g11 * temp y g12/g13 * * src w g14/g15 * src u m1/m2 * src v m3/m4 */ /* Fragment to compute per-pixel XY values */ include(`exa_wm.g4i') /* Load X and Y coordinates and compute per-pixel coordinates */ add (16) temp_x_uw<1>UW dst_x_uw 0x10101010V { align1 }; add (16) temp_y_uw<1>UW dst_y_uw 0x11001100V { align1 }; /* subtract screen-space origin of vertex 0 */ add (16) dst_x<1>F temp_x_uw<8,8,1>UW -screen_x0 { compr align1 }; add (16) dst_y<1>F temp_y_uw<8,8,1>UW -screen_y0 { compr align1 }; intel-driver-1.3.0/src/shaders/render/exa_wm_xy.g4b000066400000000000000000000003341231401140700222050ustar00rootroot00000000000000 { 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 }, { 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 }, { 0x00802040, 0x2540753d, 0x008d03c0, 0x00004020 }, { 0x00802040, 0x2580753d, 0x008d0380, 0x00004024 }, intel-driver-1.3.0/src/shaders/render/exa_wm_xy.g4b.gen5000066400000000000000000000003341231401140700230420ustar00rootroot00000000000000 { 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 }, { 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 }, { 0x00802040, 0x2540753d, 0x008d03c0, 0x00004020 }, { 0x00802040, 0x2580753d, 0x008d0380, 0x00004024 }, intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_color_balance.g4a000066400000000000000000000031001231401140700252240ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Haihao Xiang * */ include(`exa_wm.g4i') /* Color Balance parameters */ define(`skip_color_balance', `g2.2<0,1,0>uw') define(`contrast', `g2.16<0,1,0>f') define(`brightness', `g2.20<0,1,0>f') define(`cos_c_s', `g2.24<0,1,0>f') define(`sin_c_s', `g2.28<0,1,0>f') define(`sin_c_s_t', `g2.28') include(`exa_wm_yuv_color_balance.gxa') intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_color_balance.g4b000066400000000000000000000014711231401140700252360ustar00rootroot00000000000000 { 0x01000010, 0x20002d3c, 0x00000042, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000d }, { 0x00802040, 0x24007fbd, 0x008d01c0, 0xbd808081 }, { 0x00802041, 0x240077bd, 0x008d0400, 0x00000050 }, { 0x00802040, 0x240077bd, 0x008d0400, 0x00000054 }, { 0x00802040, 0x21c07fbd, 0x008d0400, 0x3d808081 }, { 0x00802040, 0x24807fbd, 0x008d0200, 0xbf008084 }, { 0x00802040, 0x24407fbd, 0x008d0240, 0xbf008084 }, { 0x00802001, 0x240003fc, 0x00000000, 0x3f008084 }, { 0x00802048, 0x240077bc, 0x008d0440, 0x0000005c }, { 0x00802048, 0x220077bd, 0x008d0480, 0x00000058 }, { 0x00000041, 0x205c7fbd, 0x0000005c, 0xbf800000 }, { 0x00802001, 0x240003fc, 0x00000000, 0x3f008084 }, { 0x00802048, 0x240077bc, 0x008d0480, 0x0000005c }, { 0x00802048, 0x224077bd, 0x008d0440, 0x00000058 }, intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_color_balance.g4b.gen5000066400000000000000000000014711231401140700260730ustar00rootroot00000000000000 { 0x01000010, 0x20002d3c, 0x00000042, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00802040, 0x24007fbd, 0x008d01c0, 0xbd808081 }, { 0x00802041, 0x240077bd, 0x008d0400, 0x00000050 }, { 0x00802040, 0x240077bd, 0x008d0400, 0x00000054 }, { 0x00802040, 0x21c07fbd, 0x008d0400, 0x3d808081 }, { 0x00802040, 0x24807fbd, 0x008d0200, 0xbf008084 }, { 0x00802040, 0x24407fbd, 0x008d0240, 0xbf008084 }, { 0x00802001, 0x240003fc, 0x00000000, 0x3f008084 }, { 0x00802048, 0x240077bc, 0x008d0440, 0x0000005c }, { 0x00802048, 0x220077bd, 0x008d0480, 0x00000058 }, { 0x00000041, 0x205c7fbd, 0x0000005c, 0xbf800000 }, { 0x00802001, 0x240003fc, 0x00000000, 0x3f008084 }, { 0x00802048, 0x240077bc, 0x008d0480, 0x0000005c }, { 0x00802048, 0x224077bd, 0x008d0440, 0x00000058 }, intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_color_balance.g6a000066400000000000000000000031001231401140700252260ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Haihao Xiang * */ include(`exa_wm.g4i') /* Color Balance parameters */ define(`skip_color_balance', `g6.2<0,1,0>uw') define(`contrast', `g6.16<0,1,0>f') define(`brightness', `g6.20<0,1,0>f') define(`cos_c_s', `g6.24<0,1,0>f') define(`sin_c_s', `g6.28<0,1,0>f') define(`sin_c_s_t', `g6.28') include(`exa_wm_yuv_color_balance.gxa') intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_color_balance.g6b000066400000000000000000000014711231401140700252400ustar00rootroot00000000000000 { 0x01000010, 0x20002d3c, 0x000000c2, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00800040, 0x24007fbd, 0x008d01c0, 0xbd808081 }, { 0x00800041, 0x240077bd, 0x008d0400, 0x000000d0 }, { 0x00800040, 0x240077bd, 0x008d0400, 0x000000d4 }, { 0x00800040, 0x21c07fbd, 0x008d0400, 0x3d808081 }, { 0x00800040, 0x24807fbd, 0x008d0200, 0xbf008084 }, { 0x00800040, 0x24407fbd, 0x008d0240, 0xbf008084 }, { 0x00800001, 0x240003fc, 0x00000000, 0x3f008084 }, { 0x00800048, 0x240077bc, 0x008d0440, 0x000000dc }, { 0x00800048, 0x220077bd, 0x008d0480, 0x000000d8 }, { 0x00000041, 0x20dc7fbd, 0x000000dc, 0xbf800000 }, { 0x00800001, 0x240003fc, 0x00000000, 0x3f008084 }, { 0x00800048, 0x240077bc, 0x008d0480, 0x000000dc }, { 0x00800048, 0x224077bd, 0x008d0440, 0x000000d8 }, intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_color_balance.g7a000066400000000000000000000031001231401140700252270ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Haihao Xiang * */ include(`exa_wm.g4i') /* Color Balance parameters */ define(`skip_color_balance', `g6.2<0,1,0>uw') define(`contrast', `g6.16<0,1,0>f') define(`brightness', `g6.20<0,1,0>f') define(`cos_c_s', `g6.24<0,1,0>f') define(`sin_c_s', `g6.28<0,1,0>f') define(`sin_c_s_t', `g6.28') include(`exa_wm_yuv_color_balance.gxa') intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_color_balance.g7b000066400000000000000000000014711231401140700252410ustar00rootroot00000000000000 { 0x01000010, 0x20002d3c, 0x000000c2, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00800040, 0x24007fbd, 0x008d01c0, 0xbd808081 }, { 0x00800041, 0x240077bd, 0x008d0400, 0x000000d0 }, { 0x00800040, 0x240077bd, 0x008d0400, 0x000000d4 }, { 0x00800040, 0x21c07fbd, 0x008d0400, 0x3d808081 }, { 0x00800040, 0x24807fbd, 0x008d0200, 0xbf008084 }, { 0x00800040, 0x24407fbd, 0x008d0240, 0xbf008084 }, { 0x00800001, 0x240003fc, 0x00000000, 0x3f008084 }, { 0x00800048, 0x240077bc, 0x008d0440, 0x000000dc }, { 0x00800048, 0x220077bd, 0x008d0480, 0x000000d8 }, { 0x00000041, 0x20dc7fbd, 0x000000dc, 0xbf800000 }, { 0x00800001, 0x240003fc, 0x00000000, 0x3f008084 }, { 0x00800048, 0x240077bc, 0x008d0480, 0x000000dc }, { 0x00800048, 0x224077bd, 0x008d0440, 0x000000d8 }, intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_color_balance.g7b.haswell000066400000000000000000000014711231401140700266770ustar00rootroot00000000000000 { 0x01000010, 0x20002d3c, 0x000000c2, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000d0 }, { 0x00800040, 0x24007fbd, 0x008d01c0, 0xbd808081 }, { 0x00800041, 0x240077bd, 0x008d0400, 0x000000d0 }, { 0x00800040, 0x240077bd, 0x008d0400, 0x000000d4 }, { 0x00800040, 0x21c07fbd, 0x008d0400, 0x3d808081 }, { 0x00800040, 0x24807fbd, 0x008d0200, 0xbf008084 }, { 0x00800040, 0x24407fbd, 0x008d0240, 0xbf008084 }, { 0x00800001, 0x240003fc, 0x00000000, 0x3f008084 }, { 0x00800048, 0x240077bc, 0x008d0440, 0x000000dc }, { 0x00800048, 0x220077bd, 0x008d0480, 0x000000d8 }, { 0x00000041, 0x20dc7fbd, 0x000000dc, 0xbf800000 }, { 0x00800001, 0x240003fc, 0x00000000, 0x3f008084 }, { 0x00800048, 0x240077bc, 0x008d0480, 0x000000dc }, { 0x00800048, 0x224077bd, 0x008d0440, 0x000000d8 }, intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_color_balance.g8a000066400000000000000000000031511231401140700252360ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Haihao Xiang * Zhao Yakui * */ include(`exa_wm.g4i') /* Color Balance parameters */ define(`skip_color_balance', `g6.2<0,1,0>uw') define(`contrast', `g6.16<0,1,0>f') define(`brightness', `g6.20<0,1,0>f') define(`cos_c_s', `g6.24<0,1,0>f') define(`sin_c_s', `g6.28<0,1,0>f') define(`sin_c_s_t', `g6.28') include(`exa_wm_yuv_color_balance.gxa') intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_color_balance.g8b000066400000000000000000000014711231401140700252420ustar00rootroot00000000000000 { 0x01000010, 0x200012e0, 0x160000c2, 0x00010001 }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000d0 }, { 0x00800040, 0x24003ae8, 0x3e8d01c0, 0xbd808081 }, { 0x00800041, 0x24003ae8, 0x3a8d0400, 0x000000d0 }, { 0x00800040, 0x24003ae8, 0x3a8d0400, 0x000000d4 }, { 0x00800040, 0x21c03ae8, 0x3e8d0400, 0x3d808081 }, { 0x00800040, 0x24803ae8, 0x3e8d0200, 0xbf008084 }, { 0x00800040, 0x24403ae8, 0x3e8d0240, 0xbf008084 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x3f008084 }, { 0x00800048, 0x24003ae0, 0x3a8d0440, 0x000000dc }, { 0x00800048, 0x22003ae8, 0x3a8d0480, 0x000000d8 }, { 0x00000041, 0x20dc3ae8, 0x3e0000dc, 0xbf800000 }, { 0x00800001, 0x24003ee0, 0x38000000, 0x3f008084 }, { 0x00800048, 0x24003ae0, 0x3a8d0480, 0x000000dc }, { 0x00800048, 0x22403ae8, 0x3a8d0440, 0x000000d8 }, intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_color_balance.gxa000066400000000000000000000065741231401140700253520ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Haihao Xiang * */ define(`Cr', `src_sample_b') define(`Cr_01', `src_sample_b_01') define(`Cr_23', `src_sample_b_23') define(`Y', `src_sample_r') define(`Y_01', `src_sample_r_01') define(`Y_23', `src_sample_r_23') define(`Cb', `src_sample_g') define(`Cb_01', `src_sample_g_01') define(`Cb_23', `src_sample_g_23') define(`Crn', `color_balance_g') define(`Crn_01', `color_balance_g_01') define(`Crn_23', `color_balance_g_23') define(`Yn', `color_balance_r') define(`Yn_01', `color_balance_r_01') define(`Yn_23', `color_balance_r_23') define(`Cbn', `color_balance_b') define(`Cbn_01', `color_balance_b_01') define(`Cbn_23', `color_balance_b_23') cmp.e.f0.0 (1) null skip_color_balance 0x1uw {align1}; (f0.0) jmpi _DONE_COLOR_BALANCE; /* Yout = (Yin - 16 / 255) * contrast + brightness + 16 / 255 */ add (16) Yn<1>F Y<8,8,1>F -0.0627451F { compr align1 }; mul (16) Yn<1>F Yn<8,8,1>F contrast { compr align1 }; add (16) Yn<1>F Yn<8,8,1>F brightness { compr align1 }; add (16) Y<1>F Yn<8,8,1>F 0.0627451F { compr align1 }; /* Uout = (Uin - 128 / 255) * cos_c_s + (Vin - 128 / 255) * sin_c_s + 128 / 255 */ /* Vout = (Vin - 128 / 255) * cos_c_s - (Uin - 128 / 255) * sin_c_s + 128 / 255 */ add (16) Cbn<1>F Cb<8,8,1>F -0.501961F { compr align1 }; add (16) Crn<1>F Cr<8,8,1>F -0.501961F { compr align1 }; mov (16) acc0<1>F 0.501961F { compr align1 }; mac (16) acc0<1>F Crn<8,8,1>F sin_c_s { compr align1 }; mac (16) Cb<1>F Cbn<8,8,1>F cos_c_s { compr align1 }; mul (1) sin_c_s_t<1>F sin_c_s -1.0F { align1}; mov (16) acc0<1>F 0.501961F { compr align1 }; mac (16) acc0<1>F Cbn<8,8,1>F sin_c_s { compr align1 }; mac (16) Cr<1>F Crn<8,8,1>F cos_c_s { compr align1 }; _DONE_COLOR_BALANCE: intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_rgb.g4a000066400000000000000000000024661231401140700232310ustar00rootroot00000000000000/* * Copyright © 2006-2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Keith Packard * Eric Anholt * */ include(`exa_wm.g4i') include(`exa_yuv_gen4.g4i') include(`exa_yuv_rgb.gxa') intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_rgb.g4b000066400000000000000000000013131231401140700232200ustar00rootroot00000000000000 { 0x00802040, 0x22c077bd, 0x008d01c0, 0x0000006c }, { 0x00802040, 0x230077bd, 0x008d0200, 0x0000007c }, { 0x00802040, 0x234077bd, 0x008d0240, 0x0000008c }, { 0x00802041, 0x240077bc, 0x008d02c0, 0x00000060 }, { 0x00802048, 0x240077bc, 0x008d0300, 0x00000064 }, { 0x80802048, 0x21c077bd, 0x008d0340, 0x00000068 }, { 0x00802041, 0x240077bc, 0x008d02c0, 0x00000070 }, { 0x00802048, 0x240077bc, 0x008d0300, 0x00000074 }, { 0x80802048, 0x220077bd, 0x008d0340, 0x00000078 }, { 0x00802041, 0x240077bc, 0x008d02c0, 0x00000080 }, { 0x00802048, 0x240077bc, 0x008d0300, 0x00000084 }, { 0x80802048, 0x224077bd, 0x008d0340, 0x00000088 }, { 0x00802001, 0x228003fd, 0x00000000, 0x3f800000 }, intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_rgb.g4b.gen5000066400000000000000000000013131231401140700240550ustar00rootroot00000000000000 { 0x00802040, 0x22c077bd, 0x008d01c0, 0x0000006c }, { 0x00802040, 0x230077bd, 0x008d0200, 0x0000007c }, { 0x00802040, 0x234077bd, 0x008d0240, 0x0000008c }, { 0x00802041, 0x240077bc, 0x008d02c0, 0x00000060 }, { 0x00802048, 0x240077bc, 0x008d0300, 0x00000064 }, { 0x80802048, 0x21c077bd, 0x008d0340, 0x00000068 }, { 0x00802041, 0x240077bc, 0x008d02c0, 0x00000070 }, { 0x00802048, 0x240077bc, 0x008d0300, 0x00000074 }, { 0x80802048, 0x220077bd, 0x008d0340, 0x00000078 }, { 0x00802041, 0x240077bc, 0x008d02c0, 0x00000080 }, { 0x00802048, 0x240077bc, 0x008d0300, 0x00000084 }, { 0x80802048, 0x224077bd, 0x008d0340, 0x00000088 }, { 0x00802001, 0x228003fd, 0x00000000, 0x3f800000 }, intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_rgb.g6a000066400000000000000000000024651231401140700232320ustar00rootroot00000000000000/* * Copyright © 2006-2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Keith Packard * Eric Anholt * */ include(`exa_wm.g4i') include(`exa_yuv_gen6.g4i') include(`exa_yuv_rgb.gxa') intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_rgb.g6b000066400000000000000000000013131231401140700232220ustar00rootroot00000000000000 { 0x00800040, 0x22c077bd, 0x008d01c0, 0x000000ec }, { 0x00800040, 0x230077bd, 0x008d0200, 0x000000fc }, { 0x00800040, 0x234077bd, 0x008d0240, 0x0000010c }, { 0x00800041, 0x240077bc, 0x008d02c0, 0x000000e0 }, { 0x00800048, 0x240077bc, 0x008d0300, 0x000000e4 }, { 0x80800048, 0x21c077bd, 0x008d0340, 0x000000e8 }, { 0x00800041, 0x240077bc, 0x008d02c0, 0x000000f0 }, { 0x00800048, 0x240077bc, 0x008d0300, 0x000000f4 }, { 0x80800048, 0x220077bd, 0x008d0340, 0x000000f8 }, { 0x00800041, 0x240077bc, 0x008d02c0, 0x00000100 }, { 0x00800048, 0x240077bc, 0x008d0300, 0x00000104 }, { 0x80800048, 0x224077bd, 0x008d0340, 0x00000108 }, { 0x00800001, 0x228003fd, 0x00000000, 0x3f800000 }, intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_rgb.g7a000066400000000000000000000024651231401140700232330ustar00rootroot00000000000000/* * Copyright © 2006-2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Keith Packard * Eric Anholt * */ include(`exa_wm.g4i') include(`exa_yuv_gen6.g4i') include(`exa_yuv_rgb.gxa') intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_rgb.g7b000066400000000000000000000013131231401140700232230ustar00rootroot00000000000000 { 0x00800040, 0x22c077bd, 0x008d01c0, 0x000000ec }, { 0x00800040, 0x230077bd, 0x008d0200, 0x000000fc }, { 0x00800040, 0x234077bd, 0x008d0240, 0x0000010c }, { 0x00800041, 0x240077bc, 0x008d02c0, 0x000000e0 }, { 0x00800048, 0x240077bc, 0x008d0300, 0x000000e4 }, { 0x80800048, 0x21c077bd, 0x008d0340, 0x000000e8 }, { 0x00800041, 0x240077bc, 0x008d02c0, 0x000000f0 }, { 0x00800048, 0x240077bc, 0x008d0300, 0x000000f4 }, { 0x80800048, 0x220077bd, 0x008d0340, 0x000000f8 }, { 0x00800041, 0x240077bc, 0x008d02c0, 0x00000100 }, { 0x00800048, 0x240077bc, 0x008d0300, 0x00000104 }, { 0x80800048, 0x224077bd, 0x008d0340, 0x00000108 }, { 0x00800001, 0x228003fd, 0x00000000, 0x3f800000 }, intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_rgb.g8a000066400000000000000000000025301231401140700232250ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Keith Packard * Eric Anholt * Zhao Yakui * */ include(`exa_wm.g4i') include(`exa_yuv_gen6.g4i') include(`exa_yuv_rgb.gxa') intel-driver-1.3.0/src/shaders/render/exa_wm_yuv_rgb.g8b000066400000000000000000000013131231401140700232240ustar00rootroot00000000000000 { 0x00800040, 0x22c03ae8, 0x3a8d01c0, 0x000000ec }, { 0x00800040, 0x23003ae8, 0x3a8d0200, 0x000000fc }, { 0x00800040, 0x23403ae8, 0x3a8d0240, 0x0000010c }, { 0x00800041, 0x24003ae0, 0x3a8d02c0, 0x000000e0 }, { 0x00800048, 0x24003ae0, 0x3a8d0300, 0x000000e4 }, { 0x80800048, 0x21c03ae8, 0x3a8d0340, 0x000000e8 }, { 0x00800041, 0x24003ae0, 0x3a8d02c0, 0x000000f0 }, { 0x00800048, 0x24003ae0, 0x3a8d0300, 0x000000f4 }, { 0x80800048, 0x22003ae8, 0x3a8d0340, 0x000000f8 }, { 0x00800041, 0x24003ae0, 0x3a8d02c0, 0x00000100 }, { 0x00800048, 0x24003ae0, 0x3a8d0300, 0x00000104 }, { 0x80800048, 0x22403ae8, 0x3a8d0340, 0x00000108 }, { 0x00800001, 0x22803ee8, 0x38000000, 0x3f800000 }, intel-driver-1.3.0/src/shaders/render/exa_yuv_gen4.g4i000066400000000000000000000031731231401140700226150ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Zhao Yakui */ /* YUV to RGB matrix coeff */ define(`coef_ry', `g3.0<0,1,0>F') define(`coef_ru', `g3.4<0,1,0>F') define(`coef_rv', `g3.8<0,1,0>F') define(`coef_yd', `g3.12<0,1,0>F') define(`coef_gy', `g3.16<0,1,0>F') define(`coef_gu', `g3.20<0,1,0>F') define(`coef_gv', `g3.24<0,1,0>F') define(`coef_ud', `g3.28<0,1,0>F') define(`coef_by', `g4.0<0,1,0>F') define(`coef_bu', `g4.4<0,1,0>F') define(`coef_bv', `g4.8<0,1,0>F') define(`coef_vd', `g4.12<0,1,0>F') intel-driver-1.3.0/src/shaders/render/exa_yuv_gen6.g4i000066400000000000000000000031731231401140700226170ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Zhao Yakui */ /* YUV to RGB matrix coeff */ define(`coef_ry', `g7.0<0,1,0>F') define(`coef_ru', `g7.4<0,1,0>F') define(`coef_rv', `g7.8<0,1,0>F') define(`coef_yd', `g7.12<0,1,0>F') define(`coef_gy', `g7.16<0,1,0>F') define(`coef_gu', `g7.20<0,1,0>F') define(`coef_gv', `g7.24<0,1,0>F') define(`coef_ud', `g7.28<0,1,0>F') define(`coef_by', `g8.0<0,1,0>F') define(`coef_bu', `g8.4<0,1,0>F') define(`coef_bv', `g8.8<0,1,0>F') define(`coef_vd', `g8.12<0,1,0>F') intel-driver-1.3.0/src/shaders/render/exa_yuv_rgb.gxa000066400000000000000000000053151231401140700226260ustar00rootroot00000000000000/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Zhao Yakui */ define(`YCbCr_base', `src_sample_base') define(`Cr', `src_sample_b') define(`Cr_01', `src_sample_b_01') define(`Cr_23', `src_sample_b_23') define(`Y', `src_sample_r') define(`Y_01', `src_sample_r_01') define(`Y_23', `src_sample_r_23') define(`Cb', `src_sample_g') define(`Cb_01', `src_sample_g_01') define(`Cb_23', `src_sample_g_23') define(`Crn', `mask_sample_b') define(`Crn_01', `mask_sample_b_01') define(`Crn_23', `mask_sample_b_23') define(`Yn', `mask_sample_r') define(`Yn_01', `mask_sample_r_01') define(`Yn_23', `mask_sample_r_23') define(`Cbn', `mask_sample_g') define(`Cbn_01', `mask_sample_g_01') define(`Cbn_23', `mask_sample_g_23') add (16) Yn<1>F Y<8,8,1>F coef_yd { compr align1 }; add (16) Cbn<1>F Cb<8,8,1>F coef_ud { compr align1 }; add (16) Crn<1>F Cr<8,8,1>F coef_vd { compr align1 }; mul (16) acc0<1>F Yn<8,8,1>F coef_ry { compr align1 }; mac (16) acc0<1>F Cbn<8,8,1>F coef_ru { compr align1 }; mac.sat (16) src_sample_r<1>F Crn<8,8,1>F coef_rv { compr align1 }; mul (16) acc0<1>F Yn<8,8,1>F coef_gy { compr align1 }; mac (16) acc0<1>F Cbn<8,8,1>F coef_gu { compr align1 }; mac.sat(16) src_sample_g<1>F Crn<8,8,1>F coef_gv { compr align1 }; mul (16) acc0<1>F Yn<8,8,1>F coef_by { compr align1 }; mac (16) acc0<1>F Cbn<8,8,1>F coef_bu { compr align1 }; mac.sat(16) src_sample_b<1>F Crn<8,8,1>F coef_bv { compr align1 }; /* * A = 1.0 */ mov (16) src_sample_a<1>F 1.0F { compr align1 }; intel-driver-1.3.0/src/shaders/utils/000077500000000000000000000000001231401140700174705ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/utils/Makefile.am000066400000000000000000000041341231401140700215260ustar00rootroot00000000000000MFC_CORE = \ end_thread.asm \ mfc_batchbuffer_head.asm \ mfc_batchbuffer_tail.asm MFC_CORE_AVC = \ mfc_batchbuffer_avc_intra.asm \ mfc_batchbuffer_avc_inter.asm MFC_CORE_HSW = \ mfc_batchbuffer_hsw.asm INTEL_G6B = mfc_batchbuffer_avc_intra.g6b mfc_batchbuffer_avc_inter.g6b INTEL_G6A = mfc_batchbuffer_avc_intra.g6a mfc_batchbuffer_avc_inter.g6a INTEL_GEN6_INC = mfc_batchbuffer.inc INTEL_GEN6_ASM = $(INTEL_G6A:%.g6a=%.gen6.asm) INTEL_G7B = mfc_batchbuffer_avc_intra.g7b mfc_batchbuffer_avc_inter.g7b INTEL_G7A = mfc_batchbuffer_avc_intra.g7a mfc_batchbuffer_avc_inter.g7a INTEL_GEN7_INC = mfc_batchbuffer.inc INTEL_GEN7_ASM = $(INTEL_G7A:%.g7a=%.gen7.asm) INTEL_G75B = mfc_batchbuffer_hsw.g75b INTEL_G75A = mfc_batchbuffer_hsw.g75a INTEL_GEN75_INC = mfc_batchbuffer_hsw.inc INTEL_GEN75_ASM = $(INTEL_G75A:%.g75a=%.gen75.asm) TARGETS = if HAVE_GEN4ASM TARGETS += $(INTEL_G6B) TARGETS += $(INTEL_G7B) TARGETS += $(INTEL_G75B) endif all-local: $(TARGETS) SUFFIXES = .g6a .g6b .g7a .g7b .gen6.asm .gen7.asm .g75a .g75b .gen75.asm if HAVE_GEN4ASM $(INTEL_GEN6_ASM): $(MFC_CORE) $(MFC_CORE_AVC) $(INTEL_GEN6_INC) .g6a.gen6.asm: $(AM_V_GEN)cpp -P -DDEV_SNB $< > _mfc0.$@ && \ m4 _mfc0.$@ > $@ && \ rm _mfc0.$@ .gen6.asm.g6b: $(AM_V_GEN)$(GEN4ASM) -g 6 -o $@ $< $(INTEL_GEN7_ASM): $(MFC_CORE) $(MFC_CORE_AVC) $(INTEL_GEN7_INC) .g7a.gen7.asm: $(AM_V_GEN)cpp -P -DDEV_IVB $< > _mfc0.$@ && \ m4 _mfc0.$@ > $@ && \ rm _mfc0.$@ .gen7.asm.g7b: $(AM_V_GEN)$(GEN4ASM) -g 7 -o $@ $< $(INTEL_GEN75_ASM): $(MFC_CORE_HSW) $(INTEL_GEN75_INC) .g75a.gen75.asm: $(AM_V_GEN)cpp -P $< > _mfc0.$@ && \ m4 _mfc0.$@ > $@ && \ rm _mfc0.$@ .gen75.asm.g75b: $(AM_V_GEN)$(GEN4ASM) -g 7.5 -o $@ $< endif CLEANFILES = $(INTEL_GEN6_ASM) $(INTEL_GEN7_ASM) $(INTEL_GEN75_ASM) EXTRA_DIST = \ $(INTEL_G6A) \ $(INTEL_G6B) \ $(INTEL_G7A) \ $(INTEL_G7B) \ $(INTEL_G75A) \ $(INTEL_G75B) \ $(INTEL_GEN6_INC) \ $(INTEL_GEN7_INC) \ $(INTEL_GEN75_INC) \ $(MFC_CORE) \ $(MFC_CORE_AVC) \ $(MFC_CORE_HSW) \ $(NULL) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/utils/end_thread.asm000066400000000000000000000026241231401140700222730ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ __EXIT: mov (8) msg_reg0<1>:ud r0<8,8,1>:ud {align1} ; send (16) msg_ind acc0<1>ud null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT} ; intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer.inc000066400000000000000000000226051231401140700232700ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ define(`BIND_IDX_VME_OUTPUT', `0') define(`BIND_IDX_MFC_SLICE_HEADER', `1') define(`BIND_IDX_MFC_BATCHBUFFER', `2') define(`INTRAMBFLAG_MASK', `0x00002000') #ifdef DEV_SNB define(`OB_CACHE_TYPE', `5') #else define(`OB_CACHE_TYPE', `10') #endif define(`OB_READ', `0') define(`OB_WRITE', `8') define(`OB_CONTROL_0', `0') /* 1 OWord, low 128 bits */ define(`OB_CONTROL_1', `1') /* 1 OWord, high 128 bits */ define(`OB_CONTROL_2', `2') /* 2 OWords */ define(`OB_CONTROL_3', `3') /* 4 OWords */ define(`OB_CONTROL_4', `4') /* 8 OWords */ #ifdef DEV_SNB define(`OB_WRITE_COMMIT_CATEGORY', `1') /* write commit on Sandybrige */ #else define(`OB_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ #endif define(`OB_HEADER_PRESENT', `1') define(`INTER_VME_OUTPUT_IN_BYTES', `160') define(`INTER_VME_OUTPUT_IN_OWS', `10') define(`INTER_VME_OUTPUT_MV_IN_OWS', `8') define(`MFC_AVC_PAK_OBJECT_INTRA_DW0', `0x71490009:UD') define(`MFC_AVC_PAK_OBJECT_INTRA_DW3', `0x000e0000:UD') /* CbpDC (1 << 19 | 1 << 18 | 1 << 17) */ define(`MFC_AVC_PAK_OBJECT_INTRA_DW4', `0xFFFF0000:UD') /* CBP for Y */ define(`MFC_AVC_PAK_OBJECT_INTRA_DW5', `0x000F000F:UD') define(`MFC_AVC_PAK_OBJECT_INTRA_DW6', `0x04000000:UD') /* the flag of the last macroblock */ define(`MFC_AVC_PAK_OBJECT_INTER_DW0', `MFC_AVC_PAK_OBJECT_INTRA_DW0') define(`MFC_AVC_PAK_OBJECT_INTER_DW1', `0x20:UD') /* 32 MVs */ define(`MFC_AVC_PAK_OBJECT_INTER_DW2', `INTER_VME_OUTPUT_IN_BYTES:UD') /* offset, in bytes */ define(`MFC_AVC_PAK_OBJECT_INTER_DW3', `0x014e0000:UD') /* * (1 << 24) | PackedMvNum, Debug * (4 << 20) | 8 MV, SNB don't use it * (1 << 19) | CbpDcY * (1 << 18) | CbpDcU * (1 << 17) | CbpDcV * (0 << 15) | Transform8x8Flag = 0 * (0 << 14) | Frame based * (0 << 13) | Inter MB * (1 << 8) | MbType = P_L0_16x16 * (0 << 7) | MBZ for frame * (0 << 6) | MBZ * (2 << 4) | MBZ for inter * (0 << 3) | MBZ * (0 << 2) | SkipMbFlag * (0 << 0) InterMbMode */ define(`MFC_AVC_PAK_OBJECT_INTER_DW4', `MFC_AVC_PAK_OBJECT_INTRA_DW4') define(`MFC_AVC_PAK_OBJECT_INTER_DW5', `MFC_AVC_PAK_OBJECT_INTRA_DW5') define(`MFC_AVC_PAK_OBJECT_INTER_DW6', `MFC_AVC_PAK_OBJECT_INTRA_DW6') define(`MI_BATCH_BUFFER_END', `0x05000000:UD') /* GRF registers * r0 header * r1~r4 constant buffer (reserved) * r5 inline data * r6~r7 reserved * r8~r15 temporary registers * r16 write back of Oword Block Write */ /* * GRF 0 -- header */ define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ /* * GRF 1~4 -- Constant Buffer (reserved) */ define(`FLAG_MASK_LAST_SLICE', `0x0001:uw') define(`FLAG_MASK_LAST_OBJECT', `0x0002:uw') define(`FLAG_MASK_FIRST_OBJECT', `0x0004:uw') /* * GRF 5 -- inline data */ define(`inline_reg0', `r5') define(`head_offset', `inline_reg0.0') /* :ud, in units of Owords */ define(`batchbuffer_offset', `inline_reg0.4') /* :ud, in units of Owords */ define(`tail_size', `inline_reg0.8') /* :w, in units of Owords */ define(`head_size', `inline_reg0.10') /* :w, in units of Owords */ define(`flags', `inline_reg0.12') /* :uw, * bit0 the flag of the last slice * bit1 the flag of the last object in a slice * bit2 the flag of the first object in a slice */ define(`total_mbs', `inline_reg0.14') /* :w, the number of macroblock commands * being processed by the kernel */ define(`mb_x', `inline_reg0.16') /* :ub, */ define(`mb_y', `inline_reg0.17') /* :ub, */ define(`mb_xy', `inline_reg0.16') /* :uw, */ define(`width_in_mb', `inline_reg0.20') /* :uw, the picture width in macroblocks */ define(`qp', `inline_reg0.22') /* :ub, */ define(`ref_idx0', `inline_reg0.24') /* :ud */ define(`ref_idx1', `inline_reg0.28') /* :ud */ /* * GRF 8~15 -- temporary registers */ define(`tmp_reg0', `r8') define(`tmp_reg1', `r9') define(`tmp_reg2', `r10') define(`tmp_reg3', `r11') define(`tmp_reg4', `r12') define(`tmp_reg5', `r13') define(`tmp_reg6', `r14') define(`tmp_reg7', `r15') define(`tmp_vme_output', `tmp_reg0') define(`tmp_slice_header', `tmp_reg1') define(`tmp_mfc_batchbuffer', `tmp_reg2') define(`tmp_offset', `tmp_reg7') /* * GRF 16~23 write back for Oword Block Read message */ define(`ob_read_wb', `r16<1>:uw') define(`ob_read_wb0', `r16') define(`ob_read_wb1', `r17') define(`ob_read_wb2', `r18') define(`ob_read_wb3', `r19') define(`ob_read_wb4', `r20') define(`ob_read_wb5', `r21') define(`ob_read_wb6', `r22') define(`ob_read_wb7', `r23') define(`ob_read_wb_len_slice_header', `1') define(`ob_read_wb_len_vme_intra', `1') define(`ob_read_wb_len_vme_inter', `1') #ifdef DEV_SNB /* * GRF 24~25 write back for Oword Block Write message */ define(`ob_write_wb', `r24') define(`ob_write_wb_length', `1') #else /* * GRF 24~25 -- reserved */ define(`ob_write_wb', `null<1>:W') define(`ob_write_wb_length', `0') #endif /* * GRF 26~27 */ define(`pak_object_ud', `r26.0') define(`pak_object0_ud', `r26.0') define(`pak_object1_ud', `r26.4') define(`pak_object2_ud', `r26.8') define(`pak_object3_ud', `r26.12') define(`pak_object4_ud', `r26.16') define(`pak_object5_ud', `r26.20') define(`pak_object6_ud', `r26.24') define(`pak_object7_ud', `r26.28') define(`pak_object8_ud', `r27.0') define(`pak_object9_ud', `r27.4') define(`pak_object10_ud', `r27.8') define(`pak_object11_ud', `r27.12') #ifdef DEV_SNB /* * Message Payload registers */ define(`msg_ind', `0') define(`msg_reg0', `m0') define(`msg_reg1', `m1') define(`msg_reg2', `m2') define(`msg_reg3', `m3') define(`msg_reg4', `m4') define(`msg_reg5', `m5') define(`msg_reg6', `m6') define(`msg_reg7', `m7') define(`msg_reg8', `m8') #else /* * Message Payload registers */ define(`msg_ind', `64') define(`msg_reg0', `g64') define(`msg_reg1', `g65') define(`msg_reg2', `g66') define(`msg_reg3', `g67') define(`msg_reg4', `g68') define(`msg_reg5', `g69') define(`msg_reg6', `g70') define(`msg_reg7', `g71') define(`msg_reg8', `g72') #endif intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_avc_inter.asm000066400000000000000000000206571231401140700253360ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ __PAK_OBJECT: mul (1) tmp_offset.0<1>:ud width_in_mb<0,1,0>:uw mb_y<0,1,0>:ub {align1}; add (1) tmp_offset.0<1>:ud tmp_offset.0<0,1,0>:ud mb_x<0,1,0>:ub {align1}; /* * The layout of VME output * ++++++++++++++++++++++++++++++++++++++++++++++ * | MV(128bytes) | other info (32bytes) | * ++++++++++++++++++++++++++++++++++++++++++++++ */ mul (1) tmp_vme_output.8<1>:ud tmp_offset.0<0,1,0>:ud INTER_VME_OUTPUT_IN_OWS:ud {align1} ; /* point to output buffer */ add (1) tmp_vme_output.8<1>:ud tmp_vme_output.8<0,1,0>:ud INTER_VME_OUTPUT_MV_IN_OWS:uw {align1}; /* point to other info */ __PAK_OBJECT_LOOP: /* * Read other info */ mov (8) msg_reg0.0<1>:ud tmp_vme_output<8,8,1>:ud {align1} ; send (16) msg_ind ob_read_wb null data_port( OB_CACHE_TYPE, OB_READ, OB_CONTROL_2, BIND_IDX_VME_OUTPUT, OB_WRITE_COMMIT_CATEGORY, OB_HEADER_PRESENT ) mlen 1 rlen ob_read_wb_len_vme_inter {align1}; /* * Fill the command */ mov (16) pak_object_ud<1>:ud 0x0:ud {align1} ; and.z.f0.1 (1) null<1>:uw flags<0,1,0>:uw FLAG_MASK_LAST_OBJECT {align1}; and.z.f0.0 (1) null<1>:ud ob_read_wb0.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0)jmpi (1) __FILL_INTRA_PAK_COMMAND ; __FILL_INTER_PAK_COMMAND: /* DW0 */ mov (1) pak_object0_ud<1>:ud MFC_AVC_PAK_OBJECT_INTER_DW0 ; /* DW2 */ mul (1) pak_object2_ud<1>:ud tmp_offset.0<0,1,0>:ud INTER_VME_OUTPUT_IN_BYTES:ud {align1} ; /* DW5 */ mov (1) pak_object5_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW5 ; /* DW1 must be 32 for 8 MVs and 128 for 32 MVs !!! */ mov (1) pak_object1_ud<1>:ud ob_read_wb0.8<0,1,0>:ud {align1} ; /* DW3 */ mov (1) pak_object3_ud<1>:ud ob_read_wb0.0<0,1,0>:ud {align1} ; /* DW4 */ add (1) pak_object4_ud<1>:ud mb_xy<0,1,0>:uw MFC_AVC_PAK_OBJECT_INTER_DW4 {align1} ; add (1) mb_x<1>:ub mb_x<0,1,0>:ub 1:uw {align1}; cmp.e.f0.0 (1) null<1>:uw width_in_mb<0,1,0>:uw mb_x<0,1,0>:ub {align1}; (f0.0)mov (1) mb_x<1>:ub 0:uw {align1} ; (f0.0)add (1) mb_y<1>:ub mb_y<0,1,0>:ub 1:uw {align1} ; /* DW6 */ mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ; (-f0.1)mov (1) pak_object6_ud<1>:ud MFC_AVC_PAK_OBJECT_INTER_DW6 {align1} ; cmp.e.f0.0 (1) null<1>:uw total_mbs<0,1,0>:uw 1:uw {align1}; (-f0.0)mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ; add (1) pak_object6_ud<1>:ud pak_object6_ud<0,1,0>:ud qp<0,1,0>:ub {align1} ; /* DW7 */ mov (1) pak_object7_ud<1>:ud ob_read_wb0.4<0,1,0>:ud {align1} ; /* DW8 */ mov (1) pak_object8_ud<1>:ud ref_idx0<0,1,0>:ud {align1} ; /* DW9 */ mov (1) pak_object9_ud<1>:ud ref_idx1<0,1,0>:ud {align1} ; jmpi (1) __OUTPUT_PAK_COMMAND ; __FILL_INTRA_PAK_COMMAND: /* DW0 */ mov (1) pak_object0_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW0 ; /* DW5 */ mov (1) pak_object5_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW5 ; /* DW4 */ add (1) pak_object4_ud<1>:ud mb_xy<0,1,0>:uw MFC_AVC_PAK_OBJECT_INTRA_DW4 {align1} ; add (1) mb_x<1>:ub mb_x<0,1,0>:ub 1:uw {align1}; cmp.e.f0.0 (1) null<1>:uw width_in_mb<0,1,0>:uw mb_x<0,1,0>:ub {align1}; (f0.0)mov (1) mb_x<1>:ub 0:uw {align1} ; (f0.0)add (1) mb_y<1>:ub mb_y<0,1,0>:ub 1:uw {align1} ; /* DW6 */ mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ; (-f0.1)mov (1) pak_object6_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW6 {align1} ; cmp.e.f0.0 (1) null<1>:uw total_mbs<0,1,0>:uw 1:uw {align1}; (-f0.0)mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ; add (1) pak_object6_ud<1>:ud pak_object6_ud<0,1,0>:ud qp<0,1,0>:ub {align1} ; /* DW3 */ and (1) pak_object3_ud<1>:ud ob_read_wb0.0<0,1,0>:ud 0xFFFF {align1} ; add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud MFC_AVC_PAK_OBJECT_INTRA_DW3 {align1} ; /* DW7 */ mov (1) pak_object7_ud<1>:ud ob_read_wb0.4<0,1,0>:ud {align1} ; /* DW8 */ mov (1) pak_object8_ud<1>:ud ob_read_wb0.8<0,1,0>:ud {align1} ; /* DW9 */ and (1) pak_object9_ud<1>:ud ob_read_wb0.12<0,1,0>:ud 0xFC:ud {align1} ; __OUTPUT_PAK_COMMAND: mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ; mov (8) msg_reg1.0<1>:ud pak_object_ud<8,8,1>:ud {align1} ; mov (8) msg_reg2.0<1>:ud pak_object8_ud<8,8,1>:ud {align1} ; /* point to the next other info block */ add (1) tmp_vme_output.8<1>:ud tmp_vme_output.8<0,1,0>:ud INTER_VME_OUTPUT_IN_OWS:ud {align1} ; send (16) msg_ind ob_write_wb null data_port( OB_CACHE_TYPE, OB_WRITE, OB_CONTROL_3, BIND_IDX_MFC_BATCHBUFFER, OB_WRITE_COMMIT_CATEGORY, OB_HEADER_PRESENT ) mlen 3 rlen ob_write_wb_length {align1}; /* the new offset */ add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 4:ud {align1} ; add (1) tmp_offset.0<1>:ud tmp_offset.0<0,1,0>:ud 1:ud {align1}; add.z.f0.0 (1) total_mbs<1>:w total_mbs<0,1,0>:w -1:w {align1}; (-f0.0)jmpi (1) __PAK_OBJECT_LOOP ; intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_avc_inter.g6a000066400000000000000000000025531231401140700252260ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ #include "mfc_batchbuffer.inc" #include "mfc_batchbuffer_head.asm" #include "mfc_batchbuffer_avc_inter.asm" #include "mfc_batchbuffer_tail.asm" #include "end_thread.asm" intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_avc_inter.g6b000066400000000000000000000115261231401140700252270ustar00rootroot00000000000000 { 0x00800001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x21340231, 0x00000014, 0x00000000 }, { 0x00000001, 0x21280021, 0x000000a0, 0x00000000 }, { 0x00000001, 0x21540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x21480021, 0x000000a4, 0x00000000 }, { 0x01000005, 0x20002d28, 0x000000ac, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 }, { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0001 }, { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 }, { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 }, { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, { 0x01000040, 0x20aa3dad, 0x000000aa, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, { 0x00000041, 0x21e04521, 0x000000b4, 0x000000b1 }, { 0x00000040, 0x21e04421, 0x000001e0, 0x000000b0 }, { 0x00000041, 0x21080c21, 0x000001e0, 0x0000000a }, { 0x00000040, 0x21082c21, 0x00000108, 0x00080008 }, { 0x00600001, 0x20000022, 0x008d0100, 0x00000000 }, { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0200 }, { 0x00800001, 0x23400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 }, { 0x01000005, 0x20000c20, 0x00000200, 0x00002000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x23400061, 0x00000000, 0x71490009 }, { 0x00000041, 0x23480c21, 0x000001e0, 0x000000a0 }, { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, { 0x00000001, 0x23440021, 0x00000208, 0x00000000 }, { 0x00000001, 0x234c0021, 0x00000200, 0x00000000 }, { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 }, { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 }, { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 }, { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 }, { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 }, { 0x00000001, 0x23580061, 0x00000000, 0x00000000 }, { 0x00110001, 0x23580061, 0x02000000, 0x04000000 }, { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 }, { 0x00110001, 0x23580061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 }, { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 }, { 0x00000001, 0x23600021, 0x000000b8, 0x00000000 }, { 0x00000001, 0x23640021, 0x000000bc, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00000001, 0x23400061, 0x00000000, 0x71490009 }, { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 }, { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 }, { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 }, { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 }, { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 }, { 0x00000001, 0x23580061, 0x00000000, 0x00000000 }, { 0x00110001, 0x23580061, 0x02000000, 0x04000000 }, { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 }, { 0x00110001, 0x23580061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 }, { 0x00000005, 0x234c1c21, 0x00000200, 0x0000ffff }, { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e0000 }, { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 }, { 0x00000001, 0x23600021, 0x00000208, 0x00000000 }, { 0x00000005, 0x23640c21, 0x0000020c, 0x000000fc }, { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0340, 0x00000000 }, { 0x00600001, 0x20400022, 0x008d0360, 0x00000000 }, { 0x00000040, 0x21080c21, 0x00000108, 0x0000000a }, { 0x05800031, 0x23001cdd, 0x00000000, 0x061b0302 }, { 0x00000040, 0x21480c21, 0x00000148, 0x00000004 }, { 0x00000040, 0x21e00c21, 0x000001e0, 0x00000001 }, { 0x01000040, 0x20ae3dad, 0x000000ae, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffff9a }, { 0x00010020, 0x34001c00, 0x02001400, 0x0000001e }, { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 }, { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0001 }, { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 }, { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 }, { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, { 0x01000040, 0x20a83dad, 0x000000a8, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, { 0x01000005, 0x20002d28, 0x000000ac, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, { 0x00400001, 0x20200062, 0x00000000, 0x00000000 }, { 0x00000001, 0x20240062, 0x00000000, 0x05000000 }, { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 }, { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001cc0, 0x00000000, 0x82000010 }, intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_avc_inter.g7a000066400000000000000000000025531231401140700252270ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ #include "mfc_batchbuffer.inc" #include "mfc_batchbuffer_head.asm" #include "mfc_batchbuffer_avc_inter.asm" #include "mfc_batchbuffer_tail.asm" #include "end_thread.asm" intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_avc_inter.g7b000066400000000000000000000115261231401140700252300ustar00rootroot00000000000000 { 0x00800001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x21340231, 0x00000014, 0x00000000 }, { 0x00000001, 0x21280021, 0x000000a0, 0x00000000 }, { 0x00000001, 0x21540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x21480021, 0x000000a4, 0x00000000 }, { 0x01000005, 0x20002d28, 0x000000ac, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00600001, 0x28000021, 0x008d0120, 0x00000000 }, { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180001 }, { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, { 0x01000040, 0x20aa3dad, 0x000000aa, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, { 0x00000041, 0x21e04521, 0x000000b4, 0x000000b1 }, { 0x00000040, 0x21e04421, 0x000001e0, 0x000000b0 }, { 0x00000041, 0x21080c21, 0x000001e0, 0x0000000a }, { 0x00000040, 0x21082c21, 0x00000108, 0x00080008 }, { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 }, { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180200 }, { 0x00800001, 0x23400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 }, { 0x01000005, 0x20000c20, 0x00000200, 0x00002000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x23400061, 0x00000000, 0x71490009 }, { 0x00000041, 0x23480c21, 0x000001e0, 0x000000a0 }, { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, { 0x00000001, 0x23440021, 0x00000208, 0x00000000 }, { 0x00000001, 0x234c0021, 0x00000200, 0x00000000 }, { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 }, { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 }, { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 }, { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 }, { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 }, { 0x00000001, 0x23580061, 0x00000000, 0x00000000 }, { 0x00110001, 0x23580061, 0x02000000, 0x04000000 }, { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 }, { 0x00110001, 0x23580061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 }, { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 }, { 0x00000001, 0x23600021, 0x000000b8, 0x00000000 }, { 0x00000001, 0x23640021, 0x000000bc, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00000001, 0x23400061, 0x00000000, 0x71490009 }, { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 }, { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 }, { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 }, { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 }, { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 }, { 0x00000001, 0x23580061, 0x00000000, 0x00000000 }, { 0x00110001, 0x23580061, 0x02000000, 0x04000000 }, { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 }, { 0x00110001, 0x23580061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 }, { 0x00000005, 0x234c1c21, 0x00000200, 0x0000ffff }, { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e0000 }, { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 }, { 0x00000001, 0x23600021, 0x00000208, 0x00000000 }, { 0x00000005, 0x23640c21, 0x0000020c, 0x000000fc }, { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0340, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0360, 0x00000000 }, { 0x00000040, 0x21080c21, 0x00000108, 0x0000000a }, { 0x0a800031, 0x20001cac, 0x00000800, 0x060a0302 }, { 0x00000040, 0x21480c21, 0x00000148, 0x00000004 }, { 0x00000040, 0x21e00c21, 0x000001e0, 0x00000001 }, { 0x01000040, 0x20ae3dad, 0x000000ae, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffff9a }, { 0x00010020, 0x34001c00, 0x02001400, 0x0000001e }, { 0x00600001, 0x28000021, 0x008d0120, 0x00000000 }, { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180001 }, { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, { 0x01000040, 0x20a83dad, 0x000000a8, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, { 0x01000005, 0x20002d28, 0x000000ac, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, { 0x00400001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00000001, 0x28240061, 0x00000000, 0x05000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca0, 0x00000800, 0x82000010 }, intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_avc_intra.asm000066400000000000000000000122101231401140700253140ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ __PAK_OBJECT: mul (1) tmp_vme_output.8<1>:ud width_in_mb<0,1,0>:uw mb_y<0,1,0>:ub {align1}; add (1) tmp_vme_output.8<1>:ud tmp_vme_output.8<0,1,0>:ud mb_x<0,1,0>:ub {align1}; mov (16) pak_object_ud<1>:ud 0x0:ud {align1} ; mov (1) pak_object0_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW0 ; mov (1) pak_object5_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW5 ; and.z.f0.1 (1) null<1>:uw flags<0,1,0>:uw FLAG_MASK_LAST_OBJECT {align1}; __PAK_OBJECT_LOOP: mov (8) msg_reg0.0<1>:ud tmp_vme_output<8,8,1>:ud {align1} ; send (16) msg_ind ob_read_wb null data_port( OB_CACHE_TYPE, OB_READ, OB_CONTROL_0, BIND_IDX_VME_OUTPUT, OB_WRITE_COMMIT_CATEGORY, OB_HEADER_PRESENT ) mlen 1 rlen ob_read_wb_len_vme_intra {align1}; /* DW4 */ add (1) pak_object4_ud<1>:ud mb_xy<0,1,0>:uw MFC_AVC_PAK_OBJECT_INTRA_DW4 {align1} ; add (1) mb_x<1>:ub mb_x<0,1,0>:ub 1:uw {align1}; cmp.e.f0.0 (1) null<1>:uw width_in_mb<0,1,0>:uw mb_x<0,1,0>:ub {align1}; (f0.0)mov (1) mb_x<1>:ub 0:uw {align1} ; (f0.0)add (1) mb_y<1>:ub mb_y<0,1,0>:ub 1:uw {align1} ; /* DW6 */ mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ; (-f0.1)mov (1) pak_object6_ud<1>:ud MFC_AVC_PAK_OBJECT_INTRA_DW6 {align1} ; cmp.e.f0.0 (1) null<1>:uw total_mbs<0,1,0>:uw 1:uw {align1}; (-f0.0)mov (1) pak_object6_ud<1>:ud 0x0:ud {align1} ; add (1) pak_object6_ud<1>:ud pak_object6_ud<0,1,0>:ud qp<0,1,0>:ub {align1} ; /* DW3 */ and (1) pak_object3_ud<1>:ud ob_read_wb0.0<0,1,0>:ud 0xFFFF {align1} ; add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud MFC_AVC_PAK_OBJECT_INTRA_DW3 {align1} ; /* DW7 */ mov (1) pak_object7_ud<1>:ud ob_read_wb0.4<0,1,0>:ud {align1} ; /* DW8 */ mov (1) pak_object8_ud<1>:ud ob_read_wb0.8<0,1,0>:ud {align1} ; /* DW9 */ and (1) pak_object9_ud<1>:ud ob_read_wb0.12<0,1,0>:ud 0xFC:ud {align1} ; mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ; mov (8) msg_reg1.0<1>:ud pak_object_ud<8,8,1>:ud {align1} ; mov (8) msg_reg2.0<1>:ud pak_object8_ud<8,8,1>:ud {align1} ; /* the new offset */ add (1) tmp_vme_output.8<1>:ud tmp_vme_output.8<0,1,0>:ud 1:ud {align1} ; send (16) msg_ind ob_write_wb null data_port( OB_CACHE_TYPE, OB_WRITE, OB_CONTROL_3, BIND_IDX_MFC_BATCHBUFFER, OB_WRITE_COMMIT_CATEGORY, OB_HEADER_PRESENT ) mlen 3 rlen ob_write_wb_length {align1}; /* the new offset */ add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 4:ud {align1} ; add.z.f0.0 (1) total_mbs<1>:w total_mbs<0,1,0>:w -1:w {align1}; (-f0.0)jmpi (1) __PAK_OBJECT_LOOP ; intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_avc_intra.g6a000066400000000000000000000025531231401140700252220ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ #include "mfc_batchbuffer.inc" #include "mfc_batchbuffer_head.asm" #include "mfc_batchbuffer_avc_intra.asm" #include "mfc_batchbuffer_tail.asm" #include "end_thread.asm" intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_avc_intra.g6b000066400000000000000000000070561231401140700252260ustar00rootroot00000000000000 { 0x00800001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x21340231, 0x00000014, 0x00000000 }, { 0x00000001, 0x21280021, 0x000000a0, 0x00000000 }, { 0x00000001, 0x21540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x21480021, 0x000000a4, 0x00000000 }, { 0x01000005, 0x20002d28, 0x000000ac, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 }, { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0001 }, { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 }, { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 }, { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, { 0x01000040, 0x20aa3dad, 0x000000aa, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, { 0x00000041, 0x21084521, 0x000000b4, 0x000000b1 }, { 0x00000040, 0x21084421, 0x00000108, 0x000000b0 }, { 0x00800001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x23400061, 0x00000000, 0x71490009 }, { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 }, { 0x00600001, 0x20000022, 0x008d0100, 0x00000000 }, { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0000 }, { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 }, { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 }, { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 }, { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 }, { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 }, { 0x00000001, 0x23580061, 0x00000000, 0x00000000 }, { 0x00110001, 0x23580061, 0x02000000, 0x04000000 }, { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 }, { 0x00110001, 0x23580061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 }, { 0x00000005, 0x234c1c21, 0x00000200, 0x0000ffff }, { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e0000 }, { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 }, { 0x00000001, 0x23600021, 0x00000208, 0x00000000 }, { 0x00000005, 0x23640c21, 0x0000020c, 0x000000fc }, { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0340, 0x00000000 }, { 0x00600001, 0x20400022, 0x008d0360, 0x00000000 }, { 0x00000040, 0x21080c21, 0x00000108, 0x00000001 }, { 0x05800031, 0x23001cdd, 0x00000000, 0x061b0302 }, { 0x00000040, 0x21480c21, 0x00000148, 0x00000004 }, { 0x01000040, 0x20ae3dad, 0x000000ae, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffffce }, { 0x00010020, 0x34001c00, 0x02001400, 0x0000001e }, { 0x00600001, 0x20000022, 0x008d0120, 0x00000000 }, { 0x05800031, 0x22001cc9, 0x00000000, 0x021a0001 }, { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 }, { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 }, { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, { 0x01000040, 0x20a83dad, 0x000000a8, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, { 0x01000005, 0x20002d28, 0x000000ac, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00600001, 0x20000022, 0x008d0140, 0x00000000 }, { 0x00400001, 0x20200062, 0x00000000, 0x00000000 }, { 0x00000001, 0x20240062, 0x00000000, 0x05000000 }, { 0x05800031, 0x23001cdd, 0x00000000, 0x041b0002 }, { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001cc0, 0x00000000, 0x82000010 }, intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_avc_intra.g7a000066400000000000000000000025531231401140700252230ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ #include "mfc_batchbuffer.inc" #include "mfc_batchbuffer_head.asm" #include "mfc_batchbuffer_avc_intra.asm" #include "mfc_batchbuffer_tail.asm" #include "end_thread.asm" intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_avc_intra.g7b000066400000000000000000000070561231401140700252270ustar00rootroot00000000000000 { 0x00800001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x21340231, 0x00000014, 0x00000000 }, { 0x00000001, 0x21280021, 0x000000a0, 0x00000000 }, { 0x00000001, 0x21540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x21480021, 0x000000a4, 0x00000000 }, { 0x01000005, 0x20002d28, 0x000000ac, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00600001, 0x28000021, 0x008d0120, 0x00000000 }, { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180001 }, { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, { 0x01000040, 0x20aa3dad, 0x000000aa, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, { 0x00000041, 0x21084521, 0x000000b4, 0x000000b1 }, { 0x00000040, 0x21084421, 0x00000108, 0x000000b0 }, { 0x00800001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x23400061, 0x00000000, 0x71490009 }, { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, { 0x01000005, 0x20002d28, 0x020000ac, 0x00020002 }, { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 }, { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180000 }, { 0x00000040, 0x23500d21, 0x000000b0, 0xffff0000 }, { 0x00000040, 0x20b02e31, 0x000000b0, 0x00010001 }, { 0x01000010, 0x20004528, 0x000000b4, 0x000000b0 }, { 0x00010001, 0x20b00171, 0x00000000, 0x00000000 }, { 0x00010040, 0x20b12e31, 0x000000b1, 0x00010001 }, { 0x00000001, 0x23580061, 0x00000000, 0x00000000 }, { 0x00110001, 0x23580061, 0x02000000, 0x04000000 }, { 0x01000010, 0x20002d28, 0x000000ae, 0x00010001 }, { 0x00110001, 0x23580061, 0x00000000, 0x00000000 }, { 0x00000040, 0x23584421, 0x00000358, 0x000000b6 }, { 0x00000005, 0x234c1c21, 0x00000200, 0x0000ffff }, { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e0000 }, { 0x00000001, 0x235c0021, 0x00000204, 0x00000000 }, { 0x00000001, 0x23600021, 0x00000208, 0x00000000 }, { 0x00000005, 0x23640c21, 0x0000020c, 0x000000fc }, { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0340, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0360, 0x00000000 }, { 0x00000040, 0x21080c21, 0x00000108, 0x00000001 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x060a0302 }, { 0x00000040, 0x21480c21, 0x00000148, 0x00000004 }, { 0x01000040, 0x20ae3dad, 0x000000ae, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffffce }, { 0x00010020, 0x34001c00, 0x02001400, 0x0000001e }, { 0x00600001, 0x28000021, 0x008d0120, 0x00000000 }, { 0x0a800031, 0x22001ca9, 0x00000800, 0x02180001 }, { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, { 0x00000040, 0x21280c21, 0x00000128, 0x00000001 }, { 0x00000040, 0x21480c21, 0x00000148, 0x00000001 }, { 0x01000040, 0x20a83dad, 0x000000a8, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffffee }, { 0x01000005, 0x20002d28, 0x000000ac, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00600001, 0x28000021, 0x008d0140, 0x00000000 }, { 0x00400001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00000001, 0x28240061, 0x00000000, 0x05000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca0, 0x00000800, 0x82000010 }, intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_head.asm000066400000000000000000000066721231401140700242660ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ /* * __START */ __START: mov (16) tmp_reg0<1>:ud 0x0:ud {align1} ; mov (16) tmp_reg2<1>:ud 0x0:ud {align1} ; mov (1) tmp_slice_header.20<1>:ub thread_id_ub {align1}; /* dispatch id */ mov (1) tmp_slice_header.8<1>:ud head_offset<0,1,0>:ud {align1}; mov (1) tmp_mfc_batchbuffer.20<1>:ub thread_id_ub {align1}; /* dispatch id */ mov (1) tmp_mfc_batchbuffer.8<1>:ud batchbuffer_offset<0,1,0>:ud {align1}; __HEAD: and.z.f0.0 (1) null<1>:uw flags<0,1,0>:uw FLAG_MASK_FIRST_OBJECT {align1}; (f0.0)jmpi (1) __PAK_OBJECT ; __HEAD_LOOP: mov (8) msg_reg0.0<1>:ud tmp_slice_header<8,8,1>:ud {align1} ; send (16) msg_ind ob_read_wb null data_port( OB_CACHE_TYPE, OB_READ, OB_CONTROL_0, BIND_IDX_MFC_SLICE_HEADER, OB_WRITE_COMMIT_CATEGORY, OB_HEADER_PRESENT ) mlen 1 rlen ob_read_wb_len_slice_header {align1}; mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ; mov (8) msg_reg1.0<1>:ud ob_read_wb0<8,8,1>:ud {align1} ; send (16) msg_ind ob_write_wb null data_port( OB_CACHE_TYPE, OB_WRITE, OB_CONTROL_0, BIND_IDX_MFC_BATCHBUFFER, OB_WRITE_COMMIT_CATEGORY, OB_HEADER_PRESENT ) mlen 2 rlen ob_write_wb_length {align1}; /* the new offset */ add (1) tmp_slice_header.8<1>:ud tmp_slice_header.8<0,1,0>:ud 1:ud {align1} ; add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 1:ud {align1} ; add.z.f0.0 (1) head_size<1>:w head_size<0,1,0>:w -1:w {align1}; (-f0.0)jmpi (1) __HEAD_LOOP ; intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_hsw.asm000066400000000000000000000254161231401140700241630ustar00rootroot00000000000000/* * Copyright © 2010-2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Zhao Yakui */ START: mov (16) pak_object_reg0.0<1>:ud 0x0:ud {align1}; mov (8) obw_m0.0<1>:ud 0x0:ud {align1}; mov (8) mb_cur_msg.0<1>:ud 0x0:ud {align1}; mov (16) mb_temp.0<1>:ud 0x0:ud {align1}; mov (1) cur_mb_x<1>:uw mb_x<0,1,0>:ub {align1}; mov (1) cur_mb_y<1>:uw mb_y<0,1,0>:ub {align1}; mov (1) end_mb_x<1>:uw slice_end_x<0,1,0>:ub {align1}; mov (1) end_mb_y<1>:uw slice_end_y<0,1,0>:ub {align1}; mov (1) end_loop_count<1>:uw total_mbs<0,1,0>:uw {align1}; mov (1) vme_len<1>:ud 2:ud {align1}; and.z.f0.0 (1) null:uw mb_flag<0,1,0>:ub INTRA_SLICE:uw {align1}; (f0.0) mov (1) vme_len<1>:ud 24:ud {align1}; mov (1) obw_m0.8<1>:UD buffer_offset<0,1,0>:ud {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) mb_cur_msg.8<1>:UD width_in_mbs<0,1,0>:UW cur_mb_y<0,1,0>:UW {align1}; add (1) mb_cur_msg.8<1>:UD mb_cur_msg.8<0,1,0>:UD cur_mb_x<0,1,0>:uw {align1}; mul (1) mb_cur_msg.8<1>:UD mb_cur_msg.8<0,1,0>:UD vme_len<0,1,0>:UD {align1}; mov (1) mb_cur_msg.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) pak_object0_ud<1>:ud MFC_AVC_PAK_OBJECT_DW0:ud {align1}; mov (1) pak_object5_ud<1>:ud MFC_AVC_PAK_OBJECT_DW5:ud {align1}; mov (1) pak_object10_ud<1>:ud MFC_AVC_PAK_OBJECT_DW10:ud {align1}; mov (1) pak_object6_ud<1>:ub qp_flag<0,1,0>:ub {align1}; pak_object_loop: mov (8) mb_msg0.0<1>:ud mb_cur_msg.0<8,8,1>:ud {align1}; mov (1) pak_object4_ud<1>:ud MFC_AVC_PAK_OBJECT_DW4:ud {align1}; mov (1) tmp_reg0.0<1>:ub cur_mb_x<0,1,0>:ub {align1}; mov (1) tmp_reg0.1<1>:ub cur_mb_y<0,1,0>:ub {align1}; mov (1) pak_object4_ud<1>:uw tmp_reg0.0<0,1,0>:uw {align1}; /* pak_object6_ud */ mov (1) pak_object_reg0.26<1>:uw 0x0:uw {align1}; cmp.e.f0.0 (1) null:uw cur_mb_x<0,1,0>:uw end_mb_x<0,1,0>:uw {align1}; (-f0.0) jmpi (1) start_mb_flag; cmp.e.f0.0 (1) null:uw cur_mb_y<0,1,0>:uw end_mb_y<0,1,0>:uw {align1}; (f0.0) mov (1) pak_object_reg0.26<1>:uw MFC_AVC_PAK_LAST_MB:uw {align1}; start_mb_flag: and.z.f0.0 (1) null:uw mb_flag<0,1,0>:ub INTRA_SLICE:uw {align1}; (f0.0) jmpi (1) inter_frame_start; /* bind index 0, read 2 oword (32bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud null data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, MV_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; jmpi (1) intra_pak_command; nop; nop; inter_frame_start: /* bind index 0, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud null data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, MV_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) jmpi (1) intra_pak_command; /* MV len and MV mode */ and (1) pak_object3_ud<1>:ud mb_inter_wb.0<0,1,0>:ud MFC_AVC_INTER_MASK_DW3:ud {align1}; add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud MFC_AVC_PAK_CBP:ud {align1}; and (1) tmp_reg0.0<1>:uw mb_inter_wb.0<0,1,0>:uw INTER_MASK:uw {align1}; mov (1) pak_object1_ud<1>:ud 32:ud {align1}; cmp.e.f0.0 (1) null:uw tmp_reg0.0<0,1,0>:uw INTER_8X8MODE:uw {align1}; (-f0.0) add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud INTER_MV8:ud {align1}; (-f0.0) jmpi (1) inter_mv_check; and.nz.f0.0 (1) null:ud mb_inter_wb.4<0,1,0>:uw SUBSHAPE_MASK:uw {align1}; (f0.0) mov (1) pak_object1_ud<1>:ud 128:ud {align1}; (f0.0) add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud INTER_MV32:ud {align1}; (f0.0) jmpi (1) mv_check_end; add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud INTER_MV8:ud {align1}; inter_mv_check: and (1) tmp_reg0.0<1>:uw mb_inter_wb.0<0,1,0>:uw INTER_MASK:uw {align1}; cmp.e.f0.0 (1) null:uw tmp_reg0.0<0,1,0>:uw INTER_16X16MODE:uw {align1}; (f0.0) jmpi (1) mv_check_end; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB A */ /* bind index 0, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud null data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, MV_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ mov (2) mb_mv0.8<1>:ud mb_mv1.0<2,2,1>:ud {align1}; mov (2) mb_mv0.16<1>:ud mb_mv2.0<2,2,1>:ud {align1}; mov (2) mb_mv0.24<1>:ud mb_mv3.0<2,2,1>:ud {align1}; mov (8) msg_reg0.0<1>:ud mb_msg0.0<8,8,1>:ud {align1} ; mov (8) msg_reg1.0<1>:ud mb_mv0.0<8,8,1>:ud {align1} ; /* Write MV for MB A */ /* bind index 0, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, MV_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; mv_check_end: /* ref list */ mov (1) pak_object8_ud<1>:ud fwd_ref<0,1,0>:ud {align1}; mov (1) pak_object9_ud<1>:ud bwd_ref<0,1,0>:ud {align1}; /* inter_mode. pak_object7_ud */ mov (1) pak_object7_ud<1>:ud 0x0:ud {align1}; mov (1) pak_object_reg0.28<1>:ub mb_inter_wb.5<0,1,0>:ub {align1}; mov (1) pak_object_reg0.29<1>:ub mb_inter_wb.6<0,1,0>:ub {align1}; /* mv start address */ add (1) tmp_reg0.4<1>:ud mb_cur_msg.8<0,1,0>:ud 3:ud {align1}; mul (1) pak_object2_ud<1>:ud tmp_reg0.4<0,1,0>:ud 16:ud {align1}; jmpi (1) write_pak_command; intra_pak_command: /* object 1/2 is set to zero */ mov (2) pak_object1_ud<1>:ud 0x0:ud {align1}; /* object 7/8 intra mode */ mov (1) pak_object7_ud<1>:ud mb_intra_wb.4<0,1,0>:ud {align1}; mov (1) pak_object8_ud<1>:ud mb_intra_wb.8<0,1,0>:ud {align1}; /* object 9 Intra structure */ mov (1) pak_object9_ud<1>:ud 0x0:ud {align1}; mov (1) pak_object9_ud<1>:ub mb_intra_wb.12<0,1,0>:ub {align1}; and (1) pak_object3_ud<1>:ud mb_intra_wb.0<0,1,0>:ud MFC_AVC_INTRA_MASK_DW3:ud {align1}; add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud MFC_AVC_INTRA_FLAG + MFC_AVC_PAK_CBP:ud {align1}; mov (1) tmp_reg0.0<1>:ud 0:ud {align1}; mov (1) tmp_reg0.1<1>:ub mb_intra_wb.2<0,1,0>:ub {align1}; and (1) tmp_reg0.0<1>:uw tmp_reg0.0<0,1,0>:uw AVC_INTRA_MASK:uw {align1}; add (1) pak_object3_ud<1>:ud pak_object3_ud<0,1,0>:ud tmp_reg0.0<0,1,0>:ud {align1}; /* Write the pak command into the batchbuffer */ write_pak_command: mov (8) msg_reg0.0<1>:ud obw_m0.0<8,8,1>:ud {align1} ; mov (8) msg_reg1.0<1>:ud pak_object_reg0.0<8,8,1>:ud {align1} ; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, MFC_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; add (1) msg_reg0.8<1>:ud msg_reg0.8<0,1,0>:ud 2:ud {align1}; mov (8) msg_reg1.0<1>:ud pak_object_reg1.0<8,8,1>:ud {align1}; /* bind index 3, write 1 oword (16bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_0, MFC_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Check the next mb */ add (1) cur_loop_count<1>:uw cur_loop_count<0,1,0>:uw 1:uw {align1}; cmp.e.f0.0 (1) null:uw cur_loop_count<0,1,0>:uw end_loop_count<0,1,0>:uw {align1}; (f0.0) jmpi (1) pak_loop_end; /* the buffer offset for next block */ add (1) obw_m0.8<1>:ud obw_m0.8<0,1,0>:ud 3:uw {align1}; add (1) mb_cur_msg.8<1>:ud mb_cur_msg.8<0,1,0>:ud vme_len<0,1,0>:ud {align1}; add (1) cur_mb_x<1>:uw cur_mb_x<0,1,0>:uw 1:uw {align1}; /* Check whether it is already equal to width in mbs */ cmp.e.f0.0 (1) null:uw cur_mb_x<0,1,0>:uw width_in_mbs<0,1,0>:uw {align1}; (f0.0) add (1) cur_mb_y<1>:uw cur_mb_y<0,1,0>:uw 1:uw {align1}; (f0.0) mov (1) cur_mb_x<1>:uw 0:uw {align1}; /* continue the pak command for next mb */ jmpi (1) pak_object_loop; nop; nop; pak_loop_end: /* Issue message fence so that the previous write message is committed */ send (16) msg_ind mb_wb.0<1>:ud null data_port( OBR_CACHE_TYPE, OBR_MESSAGE_FENCE, OBR_MF_COMMIT, MFC_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (1) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; nop; intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_hsw.g75a000066400000000000000000000024101231401140700241330ustar00rootroot00000000000000/* * Copyright © 2010-2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Zhao Yakui */ #include "mfc_batchbuffer_hsw.inc" #include "mfc_batchbuffer_hsw.asm" intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_hsw.g75b000066400000000000000000000132171231401140700241430ustar00rootroot00000000000000 { 0x00800001, 0x23400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x21e00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00000001, 0x2ac00229, 0x000000a8, 0x00000000 }, { 0x00000001, 0x2ac20229, 0x000000a9, 0x00000000 }, { 0x00000001, 0x2ae00229, 0x000000b0, 0x00000000 }, { 0x00000001, 0x2ae20229, 0x000000b1, 0x00000000 }, { 0x00000001, 0x2ae40129, 0x000000ac, 0x00000000 }, { 0x00000001, 0x2ae80061, 0x00000000, 0x00000002 }, { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, { 0x00010001, 0x2ae80061, 0x00000000, 0x00000018 }, { 0x00000001, 0x21e80021, 0x000000a0, 0x00000000 }, { 0x00000001, 0x21f40231, 0x00000014, 0x00000000 }, { 0x00000041, 0x2b082521, 0x000000aa, 0x00000ac2 }, { 0x00000040, 0x2b082421, 0x00000b08, 0x00000ac0 }, { 0x00000041, 0x2b080421, 0x00000b08, 0x00000ae8 }, { 0x00000001, 0x2b140231, 0x00000014, 0x00000000 }, { 0x00000001, 0x23400061, 0x00000000, 0x7149000a }, { 0x00000001, 0x23540061, 0x00000000, 0x000f000f }, { 0x00000001, 0x23680061, 0x00000000, 0x00000000 }, { 0x00000001, 0x23580231, 0x000000a6, 0x00000000 }, { 0x00600001, 0x2b400021, 0x008d0b00, 0x00000000 }, { 0x00000001, 0x23500061, 0x00000000, 0xffff0000 }, { 0x00000001, 0x21000231, 0x00000ac0, 0x00000000 }, { 0x00000001, 0x21010231, 0x00000ac2, 0x00000000 }, { 0x00000001, 0x23500129, 0x00000100, 0x00000000 }, { 0x00000001, 0x235a0169, 0x00000000, 0x00000000 }, { 0x01000010, 0x20002528, 0x00000ac0, 0x00000ae0 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x01000010, 0x20002528, 0x00000ac2, 0x00000ae2 }, { 0x00010001, 0x235a0169, 0x00000000, 0x04000400 }, { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02180200 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000240 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280300 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000001f0 }, { 0x00000005, 0x234c0c21, 0x00000b80, 0x1f00ffff }, { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e0000 }, { 0x00000005, 0x21002d29, 0x00000b80, 0x00030003 }, { 0x00000001, 0x23440061, 0x00000000, 0x00000020 }, { 0x01000010, 0x20002d28, 0x00000100, 0x00030003 }, { 0x00110040, 0x234c0c21, 0x0000034c, 0x00400000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000050 }, { 0x02000005, 0x20002d20, 0x00000b84, 0xff00ff00 }, { 0x00010001, 0x23440061, 0x00000000, 0x00000080 }, { 0x00010040, 0x234c0c21, 0x0000034c, 0x00600000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000c0 }, { 0x00000040, 0x234c0c21, 0x0000034c, 0x00400000 }, { 0x00000005, 0x21002d29, 0x00000b80, 0x00030003 }, { 0x01000010, 0x20002d28, 0x00000100, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480400 }, { 0x00200001, 0x2ba80021, 0x00450bc0, 0x00000000 }, { 0x00200001, 0x2bb00021, 0x00450be0, 0x00000000 }, { 0x00200001, 0x2bb80021, 0x00450c00, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0b40, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0ba0, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0200 }, { 0x00000001, 0x23600021, 0x000000b4, 0x00000000 }, { 0x00000001, 0x23640021, 0x000000b8, 0x00000000 }, { 0x00000001, 0x235c0061, 0x00000000, 0x00000000 }, { 0x00000001, 0x235c0231, 0x00000b85, 0x00000000 }, { 0x00000001, 0x235d0231, 0x00000b86, 0x00000000 }, { 0x00000040, 0x21040c21, 0x00000b08, 0x00000003 }, { 0x00000041, 0x23480c21, 0x00000104, 0x00000010 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000b0 }, { 0x00200001, 0x23440061, 0x00000000, 0x00000000 }, { 0x00000001, 0x235c0021, 0x00000b64, 0x00000000 }, { 0x00000001, 0x23600021, 0x00000b68, 0x00000000 }, { 0x00000001, 0x23640061, 0x00000000, 0x00000000 }, { 0x00000001, 0x23640231, 0x00000b6c, 0x00000000 }, { 0x00000005, 0x234c0c21, 0x00000b60, 0x0000c0ff }, { 0x00000040, 0x234c0c21, 0x0000034c, 0x000e2000 }, { 0x00000001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00000001, 0x21010231, 0x00000b62, 0x00000000 }, { 0x00000005, 0x21002d29, 0x00000100, 0x1f001f00 }, { 0x00000040, 0x234c0421, 0x0000034c, 0x00000100 }, { 0x00600001, 0x28000021, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0340, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0202 }, { 0x00000040, 0x28080c21, 0x00000808, 0x00000002 }, { 0x00600001, 0x28200021, 0x008d0360, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0002 }, { 0x00000040, 0x2ac42d29, 0x00000ac4, 0x00010001 }, { 0x01000010, 0x20002528, 0x00000ac4, 0x00000ae4 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000090 }, { 0x00000040, 0x21e82c21, 0x000001e8, 0x00030003 }, { 0x00000040, 0x2b080421, 0x00000b08, 0x00000ae8 }, { 0x00000040, 0x2ac02d29, 0x00000ac0, 0x00010001 }, { 0x01000010, 0x20002528, 0x00000ac0, 0x000000aa }, { 0x00010040, 0x2ac22d29, 0x00000ac2, 0x00010001 }, { 0x00010001, 0x2ac00169, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0xfffffb30 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000800, 0x0219e002 }, { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 }, { 0x07000031, 0x24001ca8, 0x00000e00, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_hsw.inc000066400000000000000000000154661231401140700241600ustar00rootroot00000000000000/* * Copyright © 2010-2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Zhao Yakui */ /* GRF registers * r0 header * r1~r4 constant buffer (reserved) * r5 inline data * r6~r7 reserved * r8~r15 temporary registers * r16 write back of Oword Block Write */ /* * GRF 0 -- header */ define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ define(`inline_reg0', `r5') define(`buffer_offset', `inline_reg0.0') /* :ud, in units of Owords */ /* :ub, * bit0 indicates the frame type. 1 is the I-frame. 0 is P-B frame */ define(`mb_flag', `inline_reg0.4') define(`qp_flag', `inline_reg0.6') /* :ub */ define(`mb_x', `inline_reg0.8') /* :ub, */ define(`mb_y', `inline_reg0.9') /* :ub, */ define(`mb_xy', `inline_reg0.8') /* :uw, */ /* :uw, the picture width in macroblocks */ define(`width_in_mbs', `inline_reg0.10') /* :w, the number of macroblock commands being processed by the kernel */ define(`total_mbs', `inline_reg0.12') /* ub, the mb x/y of the last mb in slice */ define(`slice_end_x', `inline_reg0.16') define(`slice_end_y', `inline_reg0.17') /* :ud the forward reference picture list */ define(`fwd_ref', `inline_reg0.20') /* :ud the backward reference picture list */ define(`bwd_ref', `inline_reg0.24') /* * GRF 8~15 -- temporary registers */ define(`tmp_reg0', `r8') define(`tmp_reg1', `r9') define(`tmp_reg2', `r10') define(`tmp_reg3', `r11') define(`tmp_reg4', `r12') define(`tmp_reg5', `r13') define(`tmp_reg6', `r14') define(`tmp_reg7', `r15') define(`obw_m0', `tmp_reg7') define(`obw_wb', `null<1>:W') define(`obw_wb_length', `0') /* * GRF 26~27 */ define(`pak_object_reg0', `r26') define(`pak_object0_ud', `r26.0') define(`pak_object1_ud', `r26.4') define(`pak_object2_ud', `r26.8') define(`pak_object3_ud', `r26.12') define(`pak_object4_ud', `r26.16') define(`pak_object5_ud', `r26.20') define(`pak_object6_ud', `r26.24') define(`pak_object7_ud', `r26.28') define(`pak_object_reg1', `r27') define(`pak_object8_ud', `r27.0') define(`pak_object9_ud', `r27.4') define(`pak_object10_ud', `r27.8') define(`pak_object11_ud', `r27.12') /* * Message Payload registers */ define(`msg_ind', `64') define(`msg_reg0', `g64') define(`msg_reg1', `g65') define(`msg_reg2', `g66') define(`msg_reg3', `g67') define(`msg_reg4', `g68') define(`msg_reg5', `g69') define(`msg_reg6', `g70') define(`msg_reg7', `g71') define(`msg_reg8', `g72') define(`MV_BIND_IDX', `0') define(`MFC_BIND_IDX', `2') define(`ts_msg_ind', `112') define(`ts_msg_reg0', `r112') define(`MFC_AVC_PAK_OBJECT_DW0', `0x7149000a') define(`MFC_AVC_PAK_OBJECT_DW4', `0xFFFF0000') /* CBP for Y */ define(`MFC_AVC_PAK_OBJECT_DW5', `0x000F000F') define(`MFC_AVC_PAK_OBJECT_DW10', `0x0000000') define(`OBR_MESSAGE_TYPE', `0') define(`OBR_CACHE_TYPE', `10') define(`OBR_MESSAGE_FENCE', `7') define(`OBR_MF_NOCOMMIT', `0') define(`OBR_MF_COMMIT', `0x20') define(`OBR_CONTROL_0', `0') /* 1 OWord, low 128 bits */ define(`OBR_CONTROL_1', `1') /* 1 OWord, high 128 bits */ define(`OBR_CONTROL_2', `2') /* 2 OWords */ define(`OBR_CONTROL_4', `3') /* 4 OWords */ define(`OBR_CONTROL_8', `4') /* 8 OWords */ define(`OBR_HEADER_PRESENT', `1') define(`OBR_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ define(`OBW_CACHE_TYPE', `10') define(`OBW_MESSAGE_TYPE', `8') define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */ define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */ define(`OBW_CONTROL_2', `2') /* 2 OWords */ define(`OBW_CONTROL_4', `3') /* 4 OWords */ define(`OBW_CONTROL_8', `4') /* 8 OWords */ define(`OBW_HEADER_PRESENT', `1') define(`INTER_MASK', `0x03') define(`INTER_16X16MODE', `0x0') define(`INTER_16X8MODE', `0x01') define(`INTER_8X16MODE', `0x02') define(`INTER_8X8MODE', `0x03') define(`SUBSHAPE_MASK', `0xFF00') define(`mb_ind', `90') define(`mb_msg0', `r90') define(`mb_wb', `r91') define(`mb_intra_wb', `r91') define(`mb_inter_wb', `r92') define(`mb_mv0', `r93') define(`mb_mv1', `r94') define(`mb_mv2', `r95') define(`mb_mv3', `r96') define(`mb_temp', `r86') define(`cur_mb_x', `mb_temp.0') /* :uw, */ define(`cur_mb_y', `mb_temp.2') /* :uw, */ define(`cur_loop_count', `mb_temp.4') /* :uw, */ define(`mb_end', `r87') define(`end_mb_x', `mb_end.0') /* :uw, */ define(`end_mb_y', `mb_end.2') /* :uw, */ define(`end_loop_count', `mb_end.4') /* :uw, */ /* :ud the length of VME predict result for every mb. Units in owords */ define(`vme_len', `mb_end.8') define(`mb_cur_msg', `r88') define(`INTRA_SLICE', `0x0001') define(`MFC_AVC_PAK_LAST_MB', `0x0400') define(`MFC_AVC_INTER_MASK_DW3', `0x1F00FFFF') define(`MFC_AVC_INTRA_MASK_DW3', `0x0000C0FF') define(`INTER_MV8', `0x00400000') define(`INTER_MV32', `0x00600000') define(`MFC_AVC_PAK_CBP', `0x000E0000') define(`MFC_AVC_INTRA_FLAG', `0x00002000') define(`AVC_INTRA_MASK', `0x1F00') intel-driver-1.3.0/src/shaders/utils/mfc_batchbuffer_tail.asm000066400000000000000000000070741231401140700243130ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ __TAIL: (f0.1)jmpi (1) __EXIT ; __TAIL_LOOP: mov (8) msg_reg0.0<1>:ud tmp_slice_header<8,8,1>:ud {align1} ; send (16) msg_ind ob_read_wb null data_port( OB_CACHE_TYPE, OB_READ, OB_CONTROL_0, BIND_IDX_MFC_SLICE_HEADER, OB_WRITE_COMMIT_CATEGORY, OB_HEADER_PRESENT ) mlen 1 rlen ob_read_wb_len_slice_header {align1}; mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ; mov (8) msg_reg1.0<1>:ud ob_read_wb0<8,8,1>:ud {align1} ; send (16) msg_ind ob_write_wb null data_port( OB_CACHE_TYPE, OB_WRITE, OB_CONTROL_0, BIND_IDX_MFC_BATCHBUFFER, OB_WRITE_COMMIT_CATEGORY, OB_HEADER_PRESENT ) mlen 2 rlen ob_write_wb_length {align1}; /* the new offset */ add (1) tmp_slice_header.8<1>:ud tmp_slice_header.8<0,1,0>:ud 1:ud {align1} ; add (1) tmp_mfc_batchbuffer.8<1>:ud tmp_mfc_batchbuffer.8<0,1,0>:ud 1:ud {align1} ; add.z.f0.0 (1) tail_size<1>:w tail_size<0,1,0>:w -1:w {align1}; (-f0.0)jmpi (1) __TAIL_LOOP ; __DONE: and.z.f0.0 (1) null<1>:uw flags<0,1,0>:uw FLAG_MASK_LAST_SLICE {align1}; (f0.0)jmpi (1) __EXIT ; /* bind index 5, write 1 oword, msg type: 8(OWord Block Write) */ mov (8) msg_reg0.0<1>:ud tmp_mfc_batchbuffer<8,8,1>:ud {align1} ; mov (4) msg_reg1.0<1>:ud 0x0:ud {align1} ; mov (1) msg_reg1.4<1>:ud MI_BATCH_BUFFER_END {align1} ; send (16) msg_ind ob_write_wb null data_port( OB_CACHE_TYPE, OB_WRITE, OB_CONTROL_0, BIND_IDX_MFC_BATCHBUFFER, OB_WRITE_COMMIT_CATEGORY, OB_HEADER_PRESENT ) mlen 2 rlen ob_write_wb_length {align1}; intel-driver-1.3.0/src/shaders/vld/000077500000000000000000000000001231401140700171155ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/vld/Makefile000066400000000000000000000244621231401140700205650ustar00rootroot00000000000000# Makefile.in generated by automake 1.10.1 from Makefile.am. # i965_drv_video/shaders/vld/Makefile. Generated from Makefile.in by configure. # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. pkgdatadir = $(datadir)/libva pkglibdir = $(libdir)/libva pkgincludedir = $(includedir)/libva am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = x86_64-unknown-linux-gnu host_triplet = x86_64-unknown-linux-gnu subdir = i965_drv_video/shaders/vld DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) mkinstalldirs = $(install_sh) -d CONFIG_HEADER = $(top_builddir)/config.h CONFIG_CLEAN_FILES = SOURCES = DIST_SOURCES = DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ACLOCAL = aclocal -I /opt/X11R7/share/aclocal AMTAR = ${SHELL} /root/libva/missing --run tar AR = ar AUTOCONF = ${SHELL} /root/libva/missing --run autoconf AUTOHEADER = ${SHELL} /root/libva/missing --run autoheader AUTOMAKE = ${SHELL} /root/libva/missing --run automake-1.10 AWK = gawk CC = gcc CCDEPMODE = depmode=gcc3 CFLAGS = -g -O2 CPP = gcc -E CPPFLAGS = CXX = g++ CXXCPP = g++ -E CXXDEPMODE = depmode=gcc3 CXXFLAGS = -g -O2 CYGPATH_W = echo DEFS = -DHAVE_CONFIG_H DEPDIR = .deps DRM_CFLAGS = -I/opt/X11R7/include -I/opt/X11R7/include/drm DRM_LIBS = -L/opt/X11R7/lib -ldrm ECHO = echo ECHO_C = ECHO_N = -n ECHO_T = EGREP = /bin/grep -E EXEEXT = F77 = gfortran FFLAGS = -g -O2 GREP = /bin/grep INSTALL = /usr/bin/install -c INSTALL_DATA = ${INSTALL} -m 644 INSTALL_PROGRAM = ${INSTALL} INSTALL_SCRIPT = ${INSTALL} INSTALL_STRIP_PROGRAM = $(install_sh) -c -s LDFLAGS = LIBOBJS = LIBS = LIBTOOL = $(SHELL) $(top_builddir)/libtool LN_S = ln -s LTLIBOBJS = MAKEINFO = ${SHELL} /root/libva/missing --run makeinfo MKDIR_P = /bin/mkdir -p OBJEXT = o PACKAGE = libva PACKAGE_BUGREPORT = waldo.bastian@intel.com PACKAGE_NAME = libva PACKAGE_STRING = libva 0.29 PACKAGE_TARNAME = libva PACKAGE_VERSION = 0.29 PATH_SEPARATOR = : PKG_CONFIG = /usr/bin/pkg-config RANLIB = ranlib SED = /bin/sed SET_MAKE = SHELL = /bin/sh STRIP = strip VERSION = 0.29 abs_builddir = /root/libva/i965_drv_video/shaders/vld abs_srcdir = /root/libva/i965_drv_video/shaders/vld abs_top_builddir = /root/libva abs_top_srcdir = /root/libva ac_ct_CC = gcc ac_ct_CXX = g++ ac_ct_F77 = gfortran am__include = include am__leading_dot = . am__quote = am__tar = ${AMTAR} chof - "$$tardir" am__untar = ${AMTAR} xf - bindir = ${exec_prefix}/bin build = x86_64-unknown-linux-gnu build_alias = build_cpu = x86_64 build_os = linux-gnu build_vendor = unknown builddir = . datadir = ${datarootdir} datarootdir = ${prefix}/share docdir = ${datarootdir}/doc/${PACKAGE_TARNAME} dvidir = ${docdir} exec_prefix = ${prefix} gen4asm = no host = x86_64-unknown-linux-gnu host_alias = host_cpu = x86_64 host_os = linux-gnu host_vendor = unknown htmldir = ${docdir} includedir = ${prefix}/include infodir = ${datarootdir}/info install_sh = $(SHELL) /root/libva/install-sh libdir = ${exec_prefix}/lib libexecdir = ${exec_prefix}/libexec localedir = ${datarootdir}/locale localstatedir = ${prefix}/var mandir = ${datarootdir}/man mkdir_p = /bin/mkdir -p oldincludedir = /usr/include pdfdir = ${docdir} pkgconfigdir = ${exec_prefix}/lib/pkgconfig prefix = /opt/X11R7 program_transform_name = s,x,x, psdir = ${docdir} sbindir = ${exec_prefix}/sbin sharedstatedir = ${prefix}/com srcdir = . sysconfdir = ${prefix}/etc target_alias = top_builddir = ../../.. top_srcdir = ../../.. INTEL_G4I = addidct.g4i \ do_iq_intra.g4i \ do_iq_non_intra.g4i \ idct.g4i \ iq_intra.g4i \ iq_non_intra.g4i \ motion_field_uv.g4i \ motion_field_y.g4i \ motion_frame_uv.g4i \ motion_frame_y.g4i \ read_field_x0y0_uv.g4i \ read_field_x0y0_y.g4i \ read_field_x0y1_y.g4i \ read_field_x1y0_y.g4i \ read_field_x1y1_y.g4i \ read_frame_x0y0_uv.g4i \ read_frame_x0y0_y.g4i \ read_frame_x0y1_y.g4i \ read_frame_x1y0_y.g4i \ read_frame_x1y1_y.g4i INTEL_G4A = ipicture.g4a \ lib.g4a \ frame_forward.g4a \ frame_backward.g4a \ frame_f_b.g4a \ field_forward.g4a \ field_backward.g4a \ field_f_b.g4a INTEL_G4B = ipicture.g4b \ lib.g4b \ frame_forward.g4b \ frame_backward.g4b \ frame_f_b.g4b \ field_forward.g4b \ field_backward.g4b \ field_f_b.g4b EXTRA_DIST = $(INTEL_G4I) \ $(INTEL_G4A) \ $(INTEL_G4B) #SUFFIXES = .g4a .g4b #BUILT_SOURCES = $(INTEL_G4B) all: $(BUILT_SOURCES) $(MAKE) $(AM_MAKEFLAGS) all-am .SUFFIXES: .SUFFIXES: .g4a .g4b $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \ && exit 0; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu i965_drv_video/shaders/vld/Makefile'; \ cd $(top_srcdir) && \ $(AUTOMAKE) --gnu i965_drv_video/shaders/vld/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(top_srcdir)/configure: $(am__configure_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(ACLOCAL_M4): $(am__aclocal_m4_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh mostlyclean-libtool: -rm -f *.lo clean-libtool: -rm -rf .libs _libs tags: TAGS TAGS: ctags: CTAGS CTAGS: distdir: $(DISTFILES) @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ list='$(DISTFILES)'; \ dist_files=`for file in $$list; do echo $$file; done | \ sed -e "s|^$$srcdirstrip/||;t" \ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \ case $$dist_files in \ */*) $(MKDIR_P) `echo "$$dist_files" | \ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \ sort -u` ;; \ esac; \ for file in $$dist_files; do \ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ if test -d $$d/$$file; then \ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \ fi; \ cp -pR $$d/$$file $(distdir)$$dir || exit 1; \ else \ test -f $(distdir)/$$file \ || cp -p $$d/$$file $(distdir)/$$file \ || exit 1; \ fi; \ done check-am: all-am check: $(BUILT_SOURCES) $(MAKE) $(AM_MAKEFLAGS) check-am all-am: Makefile installdirs: install: $(BUILT_SOURCES) $(MAKE) $(AM_MAKEFLAGS) install-am install-exec: install-exec-am install-data: install-data-am uninstall: uninstall-am install-am: all-am @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am installcheck: installcheck-am install-strip: $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ `test -z '$(STRIP)' || \ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install mostlyclean-generic: clean-generic: distclean-generic: -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) maintainer-clean-generic: @echo "This command is intended for maintainers to use" @echo "it deletes files that may require special tools to rebuild." -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES) clean-local: clean: clean-am clean-am: clean-generic clean-libtool clean-local mostlyclean-am distclean: distclean-am -rm -f Makefile distclean-am: clean-am distclean-generic dvi: dvi-am dvi-am: html: html-am info: info-am info-am: install-data-am: install-dvi: install-dvi-am install-exec-am: install-html: install-html-am install-info: install-info-am install-man: install-pdf: install-pdf-am install-ps: install-ps-am installcheck-am: maintainer-clean: maintainer-clean-am -rm -f Makefile maintainer-clean-am: distclean-am maintainer-clean-generic mostlyclean: mostlyclean-am mostlyclean-am: mostlyclean-generic mostlyclean-libtool pdf: pdf-am pdf-am: ps: ps-am ps-am: uninstall-am: .MAKE: install-am install-strip .PHONY: all all-am check check-am clean clean-generic clean-libtool \ clean-local distclean distclean-generic distclean-libtool \ distdir dvi dvi-am html html-am info info-am install \ install-am install-data install-data-am install-dvi \ install-dvi-am install-exec install-exec-am install-html \ install-html-am install-info install-info-am install-man \ install-pdf install-pdf-am install-ps install-ps-am \ install-strip installcheck installcheck-am installdirs \ maintainer-clean maintainer-clean-generic mostlyclean \ mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ uninstall uninstall-am #.g4a.g4b: # m4 $*.g4a > $*.g4m && intel-gen4asm -o $@ $*.g4m && rm $*.g4m #$(INTEL_G4B): $(INTEL_G4I) #clean-local: # -rm -f $(INTEL_G4B) # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: intel-driver-1.3.0/src/shaders/vme/000077500000000000000000000000001231401140700171175ustar00rootroot00000000000000intel-driver-1.3.0/src/shaders/vme/Makefile.am000066400000000000000000000063211231401140700211550ustar00rootroot00000000000000VME_CORE = batchbuffer.asm intra_frame.asm inter_frame.asm VME7_CORE = batchbuffer.asm intra_frame_ivb.asm inter_frame_ivb.asm inter_bframe_ivb.asm mpeg2_inter_ivb.asm VME75_CORE = batchbuffer.asm intra_frame_haswell.asm inter_frame_haswell.asm inter_bframe_haswell.asm mpeg2_inter_haswell.asm VME8_CORE = intra_frame_gen8.asm inter_frame_gen8.asm inter_bframe_gen8.asm mpeg2_inter_gen8.asm INTEL_G6B = batchbuffer.g6b intra_frame.g6b inter_frame.g6b INTEL_G6A = batchbuffer.g6a intra_frame.g6a inter_frame.g6a INTEL_GEN6_INC = batchbuffer.inc vme.inc INTEL_GEN6_ASM = $(INTEL_G6A:%.g6a=%.gen6.asm) INTEL_G7B = batchbuffer.g7b intra_frame.g7b inter_frame.g7b intra_frame_ivb.g7b inter_frame_ivb.g7b inter_bframe_ivb.g7b mpeg2_inter_ivb.g7b INTEL_G7A = batchbuffer.g7a intra_frame.g7a inter_frame.g7a intra_frame_ivb.g7a inter_frame_ivb.g7a inter_bframe_ivb.g7a mpeg2_inter_ivb.g7a INTEL_GEN7_INC = batchbuffer.inc vme.inc vme7_mpeg2.inc vme7.inc INTEL_GEN7_ASM = $(INTEL_G7A:%.g7a=%.gen7.asm) INTEL_G75B = batchbuffer.g75b intra_frame_haswell.g75b inter_frame_haswell.g75b inter_bframe_haswell.g75b mpeg2_inter_haswell.g75b INTEL_G75A = batchbuffer.g75a intra_frame_haswell.g75a inter_frame_haswell.g75a inter_bframe_haswell.g75a mpeg2_inter_haswell.g75a INTEL_GEN75_INC = batchbuffer.inc vme75.inc vme75_mpeg2.inc INTEL_GEN75_ASM = $(INTEL_G75A:%.g75a=%.gen75.asm) INTEL_G8B = intra_frame_gen8.g8b inter_frame_gen8.g8b inter_bframe_gen8.g8b mpeg2_inter_gen8.g8b INTEL_G8A = intra_frame_gen8.g8a inter_frame_gen8.g8a inter_bframe_gen8.g8a mpeg2_inter_gen8.g8a INTEL_GEN8_INC = vme8.inc vme75_mpeg2.inc INTEL_GEN8_ASM = $(INTEL_G8A:%.g8a=%.gen8.asm) TARGETS = if HAVE_GEN4ASM TARGETS += $(INTEL_G6B) TARGETS += $(INTEL_G7B) TARGETS += $(INTEL_G75B) TARGETS += $(INTEL_G8B) endif all-local: $(TARGETS) SUFFIXES = .g6a .g6b .g7a .g7b .gen6.asm .gen7.asm .g75a .g75b .gen75.asm .g8a .g8b .gen8.asm if HAVE_GEN4ASM $(INTEL_GEN6_ASM): $(VME_CORE) $(INTEL_GEN6_INC) .g6a.gen6.asm: $(AM_V_GEN)cpp -P -DDEV_SNB $< > _vme0.$@ && \ m4 _vme0.$@ > $@ && \ rm _vme0.$@ .gen6.asm.g6b: $(AM_V_GEN)$(GEN4ASM) -g 6 -o $@ $< $(INTEL_GEN7_ASM): $(VME7_CORE) $(INTEL_GEN7_INC) .g7a.gen7.asm: $(AM_V_GEN)cpp -P -DDEV_IVB $< > _vme0.$@ && \ m4 _vme0.$@ > $@ && \ rm _vme0.$@ .gen7.asm.g7b: $(AM_V_GEN)$(GEN4ASM) -g 7 -o $@ $< $(INTEL_GEN75_ASM): $(VME75_CORE) $(INTEL_GEN75_INC) .g75a.gen75.asm: $(AM_V_GEN)cpp -P $< > _vme0.$@ && \ m4 _vme0.$@ > $@ && \ rm _vme0.$@ .gen75.asm.g75b: $(AM_V_GEN)$(GEN4ASM) -g 7.5 -o $@ $< $(INTEL_GEN8_ASM): $(VME8_CORE) $(INTEL_GEN8_INC) .g8a.gen8.asm: $(AM_V_GEN)cpp -P $< > _vme0.$@ && \ m4 _vme0.$@ > $@ && \ rm _vme0.$@ .gen8.asm.g8b: $(AM_V_GEN)$(GEN4ASM) -g 8 -o $@ $< endif CLEANFILES = $(INTEL_GEN6_ASM) $(INTEL_GEN7_ASM) $(INTEL_GEN75_ASM) $(INTEL_GEN8_ASM) EXTRA_DIST = \ $(INTEL_G6A) \ $(INTEL_G6B) \ $(INTEL_G75A) \ $(INTEL_G75B) \ $(INTEL_G7A) \ $(INTEL_G7B) \ $(INTEL_G8A) \ $(INTEL_G8B) \ $(INTEL_GEN6_INC) \ $(INTEL_GEN75_INC) \ $(INTEL_GEN7_INC) \ $(INTEL_GEN8_INC) \ $(VME75_CORE) \ $(VME7_CORE) \ $(VME8_CORE) \ $(VME_CORE) \ $(NULL) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/shaders/vme/batchbuffer.asm000066400000000000000000000133561231401140700221040ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ /* * __START */ __START: mov (16) tmp_reg0<1>:ud 0x0:ud {align1} ; mov (16) tmp_reg2<1>:ud 0x0:ud {align1} ; mov (1) obw_header.20<1>:ub thread_id_ub {align1}; /* dispatch id */ mov (8) media_object_ud<1>:ud 0x0:ud {align1} ; mov (1) media_object0_ud<1>:ud CMD_MEDIA_OBJECT {align1} ; mov (1) media_object1_ud<1>:ud mtype_ub<0,1,0>ub {align1}; mov (1) media_object6_width<1>:uw width_in_mb<0,1,0>:uw {align1}; mov (1) media_object7_flag<1>:uw transform_8x8_ub<0,1,0>ub {align1}; mov (1) media_object7_num_mbs<1>:uw NUM_MACROBLOCKS_PER_COMMAND:uw {align1} ; mov (1) width_per_row<1>:ud width_in_mb<0,1,0>:uw {align1} ; and.z.f0.1 (1) remainder_cmds<1>:ud total_mbs<0,1,0>:ud (NUM_MACROBLOCKS_PER_COMMAND - 1):ud {align1} ; and.z.f0.0 (1) total_mbs<1>:ud total_mbs<0,1,0>:ud -NUM_MACROBLOCKS_PER_COMMAND:ud {align1} ; (f0.0)jmpi (1) __REMAINDER ; __CMD_LOOP: mov (8) msg_reg0.0<1>:ud obw_header<8,8,1>:ud {align1}; mov (8) msg_reg1<1>:ud media_object_ud<8,8,1>:ud {align1}; /* bind index 5, write 2 oword, msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* (x, y) of the first macroblock */ add (1) count<1>:ud count<0,1,0>:ud NUM_MACROBLOCKS_PER_COMMAND:uw {align1} ; math (1) quotient<1>:ud count<0,1,0>:ud width_per_row<0,1,0>:ud intdivmod {align1} ; shl (1) quotient<1>:ud quotient<0,1,0>:ud 8:uw {align1} ; add (1) quotient<1>:ud quotient<0,1,0>:ud remainder<0,1,0>:ud {align1} ; mov (1) media_object6_xy<1>:uw quotient<0,1,0>:uw {align1} ; /* the new offset */ add (1) obw_header.8<1>:ud obw_header.8<0,1,0>:ud 2:uw {align1} ; add.z.f0.0 (1) total_mbs<1>:w total_mbs<0,1,0>:w -NUM_MACROBLOCKS_PER_COMMAND:w {align1} ; (-f0.0)jmpi (1) __CMD_LOOP ; __REMAINDER: (f0.1)jmpi (1) __DONE ; mov (1) media_object7_num_mbs<1>:uw remainder_cmds<0,1,0>:uw {align1} ; mov (8) msg_reg0.0<1>:ud obw_header<8,8,1>:ud {align1}; mov (8) msg_reg1<1>:ud media_object_ud<8,8,1>:ud {align1}; send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* the new offset */ add (1) obw_header.8<1>:ud obw_header.8<0,1,0>:ud 2:uw {align1} ; __DONE: /* bind index 5, write 1 oword, msg type: 8(OWord Block Write) */ mov (8) msg_reg0.0<1>:ud obw_header<8,8,1>:ud {align1} ; mov (4) msg_reg1.0<1>:ud 0x0:ud {align1} ; mov (1) msg_reg1.4<1>:ud MI_BATCH_BUFFER_END {align1} ; send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_0, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; __EXIT: mov (8) msg_reg0<1>:ud r0<8,8,1>:ud {align1} ; send (16) msg_ind acc0<1>ud null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT} ; intel-driver-1.3.0/src/shaders/vme/batchbuffer.g6a000066400000000000000000000023671231401140700220010ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ #include "batchbuffer.inc" #include "batchbuffer.asm" intel-driver-1.3.0/src/shaders/vme/batchbuffer.g6b000066400000000000000000000036741231401140700220040ustar00rootroot00000000000000 { 0x00800001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x21140231, 0x00000014, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00000001, 0x22000061, 0x00000000, 0x71000006 }, { 0x00000001, 0x22040221, 0x000000a5, 0x00000000 }, { 0x00000001, 0x221a0129, 0x000000a6, 0x00000000 }, { 0x00000001, 0x221c0229, 0x000000a4, 0x00000000 }, { 0x00000001, 0x221e0169, 0x00000000, 0x02000200 }, { 0x00000001, 0x21280121, 0x000000a6, 0x00000000 }, { 0x01000005, 0x21240c21, 0x020000a0, 0x000001ff }, { 0x01000005, 0x20a00c21, 0x000000a0, 0xfffffe00 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00600001, 0x20000022, 0x008d0100, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 }, { 0x05800031, 0x22401cdd, 0x00000000, 0x041b0205 }, { 0x00000040, 0x21202c21, 0x00000120, 0x02000200 }, { 0x0b000038, 0x21400421, 0x00000120, 0x00000128 }, { 0x00000009, 0x21402c21, 0x00000140, 0x00080008 }, { 0x00000040, 0x21400421, 0x00000140, 0x00000160 }, { 0x00000001, 0x22180129, 0x00000140, 0x00000000 }, { 0x00000040, 0x21082c21, 0x00000108, 0x00020002 }, { 0x01000040, 0x20a03dad, 0x000000a0, 0xfe00fe00 }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffffea }, { 0x00010020, 0x34001c00, 0x02001400, 0x0000000a }, { 0x00000001, 0x221e0129, 0x00000124, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d0100, 0x00000000 }, { 0x00600001, 0x20200022, 0x008d0200, 0x00000000 }, { 0x05800031, 0x22401cdd, 0x00000000, 0x041b0205 }, { 0x00000040, 0x21082c21, 0x00000108, 0x00020002 }, { 0x00600001, 0x20000022, 0x008d0100, 0x00000000 }, { 0x00400001, 0x20200062, 0x00000000, 0x00000000 }, { 0x00000001, 0x20240062, 0x00000000, 0x05000000 }, { 0x05800031, 0x22401cdd, 0x00000000, 0x041b0005 }, { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001cc0, 0x00000000, 0x82000010 }, intel-driver-1.3.0/src/shaders/vme/batchbuffer.g75a000066400000000000000000000000661231401140700220610ustar00rootroot00000000000000#include "batchbuffer.inc" #include "batchbuffer.asm" intel-driver-1.3.0/src/shaders/vme/batchbuffer.g75b000066400000000000000000000036741231401140700220720ustar00rootroot00000000000000 { 0x00800001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x21140231, 0x00000014, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00000001, 0x22000061, 0x00000000, 0x71000006 }, { 0x00000001, 0x22040221, 0x000000a5, 0x00000000 }, { 0x00000001, 0x221a0129, 0x000000a6, 0x00000000 }, { 0x00000001, 0x221c0229, 0x000000a4, 0x00000000 }, { 0x00000001, 0x221e0169, 0x00000000, 0x02000200 }, { 0x00000001, 0x21280121, 0x000000a6, 0x00000000 }, { 0x01000005, 0x21240c21, 0x020000a0, 0x000001ff }, { 0x01000005, 0x20a00c21, 0x000000a0, 0xfffffe00 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000b0 }, { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0205 }, { 0x00000040, 0x21202c21, 0x00000120, 0x02000200 }, { 0x0b000038, 0x21400421, 0x00000120, 0x00000128 }, { 0x00000009, 0x21402c21, 0x00000140, 0x00080008 }, { 0x00000040, 0x21400421, 0x00000140, 0x00000160 }, { 0x00000001, 0x22180129, 0x00000140, 0x00000000 }, { 0x00000040, 0x21082c21, 0x00000108, 0x00020002 }, { 0x01000040, 0x20a03dad, 0x000000a0, 0xfe00fe00 }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffff50 }, { 0x00010020, 0x34001c00, 0x02001400, 0x00000050 }, { 0x00000001, 0x221e0129, 0x00000124, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0205 }, { 0x00000040, 0x21082c21, 0x00000108, 0x00020002 }, { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 }, { 0x00400001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00000001, 0x28240061, 0x00000000, 0x05000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0005 }, { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca0, 0x00000800, 0x82000010 }, intel-driver-1.3.0/src/shaders/vme/batchbuffer.g7a000066400000000000000000000023671231401140700220020ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ #include "batchbuffer.inc" #include "batchbuffer.asm" intel-driver-1.3.0/src/shaders/vme/batchbuffer.g7b000066400000000000000000000036741231401140700220050ustar00rootroot00000000000000 { 0x00800001, 0x21000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x21400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x21140231, 0x00000014, 0x00000000 }, { 0x00600001, 0x22000061, 0x00000000, 0x00000000 }, { 0x00000001, 0x22000061, 0x00000000, 0x71000006 }, { 0x00000001, 0x22040221, 0x000000a5, 0x00000000 }, { 0x00000001, 0x221a0129, 0x000000a6, 0x00000000 }, { 0x00000001, 0x221c0229, 0x000000a4, 0x00000000 }, { 0x00000001, 0x221e0169, 0x00000000, 0x02000200 }, { 0x00000001, 0x21280121, 0x000000a6, 0x00000000 }, { 0x01000005, 0x21240c21, 0x020000a0, 0x000001ff }, { 0x01000005, 0x20a00c21, 0x000000a0, 0xfffffe00 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000016 }, { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0205 }, { 0x00000040, 0x21202c21, 0x00000120, 0x02000200 }, { 0x0b000038, 0x21400421, 0x00000120, 0x00000128 }, { 0x00000009, 0x21402c21, 0x00000140, 0x00080008 }, { 0x00000040, 0x21400421, 0x00000140, 0x00000160 }, { 0x00000001, 0x22180129, 0x00000140, 0x00000000 }, { 0x00000040, 0x21082c21, 0x00000108, 0x00020002 }, { 0x01000040, 0x20a03dad, 0x000000a0, 0xfe00fe00 }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffffea }, { 0x00010020, 0x34001c00, 0x02001400, 0x0000000a }, { 0x00000001, 0x221e0129, 0x00000124, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0205 }, { 0x00000040, 0x21082c21, 0x00000108, 0x00020002 }, { 0x00600001, 0x28000021, 0x008d0100, 0x00000000 }, { 0x00400001, 0x28200061, 0x00000000, 0x00000000 }, { 0x00000001, 0x28240061, 0x00000000, 0x05000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0005 }, { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca0, 0x00000800, 0x82000010 }, intel-driver-1.3.0/src/shaders/vme/batchbuffer.inc000066400000000000000000000130431231401140700220660ustar00rootroot00000000000000/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Xiang Haihao */ define(`BIND_IDX_VME', `0') define(`BIND_IDX_VME_REF0', `1') define(`BIND_IDX_VME_REF1', `2') define(`BIND_IDX_OUTPUT', `3') define(`BIND_IDX_INEP', `4') define(`BIND_IDX_VME_BATCHBUFFER', `5') #ifdef DEV_SNB define(`OBW_CACHE_TYPE', `5') #else define(`OBW_CACHE_TYPE', `10') #endif define(`OBW_MESSAGE_TYPE', `8') define(`OBW_BIND_IDX', `BIND_IDX_VME_BATCHBUFFER') define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */ define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */ define(`OBW_CONTROL_2', `2') /* 2 OWords */ define(`OBW_CONTROL_3', `3') /* 4 OWords */ define(`OBW_CONTROL_4', `4') /* 8 OWords */ #ifdef DEV_SNB define(`OBW_WRITE_COMMIT_CATEGORY', `1') /* write commit on Sandybrige */ #else define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ #endif define(`OBW_HEADER_PRESENT', `1') define(`CMD_MEDIA_OBJECT', `0x71000006:UD') define(`MI_BATCH_BUFFER_END', `0x05000000:UD') define(`NUM_MACROBLOCKS_PER_COMMAND', `512') /* GRF registers * r0 header * r1~r4 constant buffer (reserved) * r5 inline data * r6~r7 reserved * r8~r15 temporary registers * r16 media object command * r17 * r18 write back of Oword Block Write */ /* * GRF 0 -- header */ define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ /* * GRF 1~4 -- Constant Buffer (reserved) */ /* * GRF 5 -- inline data */ define(`inline_reg0', `r5') define(`total_mbs', `inline_reg0.0') /* the number of macroblocks in a picture */ define(`transform_8x8_ub', `inline_reg0.4') /* transform_8x8 flag */ define(`mtype_ub', `inline_reg0.5') /* 0: INTRA, 1: INTER */ define(`width_in_mb', `inline_reg0.6') /* the picture width in macroblocks */ /* * GRF 8~15 -- temporary registers */ define(`tmp_reg0', `r8') define(`obw_header', `tmp_reg0') define(`tmp_reg1', `r9') define(`count', `tmp_reg1.0') define(`remainder_cmds', `tmp_reg1.4') define(`width_per_row', `tmp_reg1.8') define(`tmp_reg2', `r10') define(`quotient', `tmp_reg2') define(`tmp_reg3', `r11') define(`remainder', `tmp_reg3') define(`tmp_reg4', `r12') define(`tmp_reg5', `r13') define(`tmp_reg6', `r14') define(`tmp_reg7', `r15') /* * GRF 16 */ define(`media_object_ud', `r16.0') define(`media_object0_ud', `r16.0') define(`media_object1_ud', `r16.4') define(`media_object2_ud', `r16.8') define(`media_object3_ud', `r16.12') define(`media_object4_ud', `r16.16') define(`media_object5_ud', `r16.20') define(`media_object6_ud', `r16.24') define(`media_object6_xy', `r16.24') define(`media_object6_x', `r16.24') define(`media_object6_y', `r16.25') define(`media_object6_width', `r16.26') define(`media_object7_ud', `r16.28') define(`media_object7_flag', `r16.28') define(`media_object7_num_mbs', `r16.30') /* * GRF 18 write back for Oword Block Write message */ #if DEV_SNB define(`obw_wb', `r18') define(`obw_wb_length', `1') #else /* * write commit is removed on Ivybridge */ define(`obw_wb', `null<1>:W') define(`obw_wb_length', `0') #endif /* * Message Payload registers */ #if DEV_SNB define(`msg_ind', `0') define(`msg_reg0', `m0') define(`msg_reg1', `m1') define(`msg_reg2', `m2') define(`msg_reg3', `m3') define(`msg_reg4', `m4') define(`msg_reg5', `m5') define(`msg_reg6', `m6') define(`msg_reg7', `m7') define(`msg_reg8', `m8') #else define(`msg_ind', `64') define(`msg_reg0', `g64') define(`msg_reg1', `g65') define(`msg_reg2', `g66') define(`msg_reg3', `g67') define(`msg_reg4', `g68') define(`msg_reg5', `g69') define(`msg_reg6', `g70') define(`msg_reg7', `g71') define(`msg_reg8', `g72') #endif intel-driver-1.3.0/src/shaders/vme/inter_bframe_gen8.asm000066400000000000000000001030661231401140700232050ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * Authors: Zhao Yakui */ // Modual name: Inter_bframe_haswell.asm // // Make inter predition estimation for Inter frame for B-frame // // // Now, begin source code.... // #define SAVE_RET add (1) RETURN_REG<1>:ud ip:ud 32:ud #define RETURN mov (1) ip:ud RETURN_REG<0,1,0>:ud /* * __START */ __INTER_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ; shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1}; mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1}; mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 24:UD {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* * Media Read Message -- fetch Luma neighbor edge pixels */ /* ROW */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1}; /* * Media Read Message -- fetch Chroma neighbor edge pixels */ /* ROW */ shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16 , y * 8 */ mul (1) read0_header.0<1>:D read0_header.0<0,1,0>:D 2:W {align1}; add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind CHROMA_ROW<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16, y * 8 */ mul (1) read1_header.0<1>:D read1_header.0<0,1,0>:D 2:W {align1}; add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_8X4 {align1}; mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind CHROMA_COL<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1}; mov (8) vme_m1.0<1>:ud 0:ud {align1}; mov (8) mb_mvp_ref.0<1>:ud 0:ud {align1}; mov (8) mb_ref_win.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1}; (f0.0) jmpi (1) __mb_hwdep_end; /* read back the data for MB A */ /* the layout of MB result is: rx.0(Available). rx.4(MVa), rX.8(MVb), rX.16(Pred_L0 flag), * rX.18 (Pred_L1 flag), rX.20(Forward reference ID), rX.22(Backwared reference ID) */ mov (8) mba_result.0<1>:ud 0x0:ud {align1}; mov (8) mbb_result.0<1>:ud 0x0:ud {align1}; mov (8) mbc_result.0<1>:ud 0x0:ud {align1}; mba_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; /* MB A doesn't exist. Zero MV. mba_flag is zero and ref ID = -1 */ (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; mov (1) mba_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB A */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* MV */ mov (2) mba_result.20<1>:w -1:w {align1}; mov (1) INPUT_ARG0.0<1>:ud mb_inter_wb.4<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.4<1>:ud mb_inter_wb.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud INTER_BLOCK1:ud {align1}; SAVE_RET {align1}; jmpi (1) mb_pred_func; mov (1) mb_pred_mode.0<1>:uw RET_ARG<0,1,0>:uw {align1}; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L0 {align1}; (f0.0) mov (1) mba_result.16<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mba_result.20<1>:w 0:w {align1}; (f0.0) mov (1) mba_result.4<1>:ud mb_mv1.8<0,1,0>:ud {align1}; (f0.0) jmpi (1) mbb_start; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L1 {align1}; (f0.0) mov (1) mba_result.18<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mba_result.22<1>:w 0:w {align1}; (f0.0) mov (1) mba_result.8<1>:ud mb_mv1.12<0,1,0>:ud {align1}; (f0.0) jmpi (1) mbb_start; mov (2) mba_result.4<1>:ud mb_mv1.8<2,2,1>:ud {align1}; mov (2) mba_result.16<1>:uw MB_PRED_FLAG {align1}; mov (2) mba_result.20<1>:w 0:w {align1}; mbb_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; /* MB B doesn't exist. Zero MV. mba_flag is zero */ /* If MB B doesn't exist, neither MB C nor D exists */ (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbb_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbc_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB B */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ mov (2) mbb_result.20<1>:w -1:w {align1}; mov (1) INPUT_ARG0.0<1>:ud mb_inter_wb.4<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.4<1>:ud mb_inter_wb.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud INTER_BLOCK2:ud {align1}; SAVE_RET {align1}; jmpi (1) mb_pred_func; mov (1) mb_pred_mode.0<1>:uw RET_ARG<0,1,0>:uw {align1}; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L0 {align1}; (f0.0) mov (1) mbb_result.16<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbb_result.20<1>:w 0:w {align1}; (f0.0) mov (1) mbb_result.4<1>:ud mb_mv2.16<0,1,0>:ud {align1}; (f0.0) jmpi (1) mbc_start; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L1 {align1}; (f0.0) mov (1) mbb_result.18<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbb_result.22<1>:w 0:w {align1}; (f0.0) mov (1) mbb_result.8<1>:ud mb_mv2.20<0,1,0>:ud {align1}; (f0.0) jmpi (1) mbc_start; mov (2) mbb_result.16<1>:uw MB_PRED_FLAG {align1}; mov (2) mbb_result.20<1>:w 0:w {align1}; mov (2) mbb_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1}; mbc_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_C:uw {align1}; /* MB C doesn't exist. Zero MV. mba_flag is zero */ /* Based on h264 spec the MB D will be replaced if MB C doesn't exist */ (f0.0) jmpi (1) mbd_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB C */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.20<1>:w -1:w {align1}; mov (1) INPUT_ARG0.0<1>:ud mb_inter_wb.4<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.4<1>:ud mb_inter_wb.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud INTER_BLOCK2:ud {align1}; SAVE_RET {align1}; jmpi (1) mb_pred_func; mov (1) mb_pred_mode.0<1>:uw RET_ARG<0,1,0>:uw {align1}; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L0 {align1}; (f0.0) mov (1) mbc_result.16<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbc_result.20<1>:w 0:w {align1}; (f0.0) mov (1) mbc_result.4<1>:ud mb_mv2.16<0,1,0>:ud {align1}; (f0.0) jmpi (1) mb_mvp_start; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L1 {align1}; (f0.0) mov (1) mbc_result.18<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbc_result.22<1>:w 0:w {align1}; (f0.0) mov (1) mbc_result.8<1>:ud mb_mv2.20<0,1,0>:ud {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (2) mbc_result.16<1>:uw MB_PRED_FLAG {align1}; mov (2) mbc_result.20<1>:w 0:w {align1}; mov (2) mbc_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1}; jmpi (1) mb_mvp_start; mbd_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_D:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (2) tmp_reg0.0<1>:w tmp_reg0.0<2,2,1>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB D */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ub NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.20<1>:w -1:w {align1}; mov (1) INPUT_ARG0.0<1>:ud mb_inter_wb.4<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.4<1>:ud mb_inter_wb.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud INTER_BLOCK3:ud {align1}; SAVE_RET {align1}; jmpi (1) mb_pred_func; mov (1) mb_pred_mode.0<1>:uw RET_ARG<0,1,0>:uw {align1}; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L0 {align1}; (f0.0) mov (1) mbc_result.16<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbc_result.20<1>:w 0:w {align1}; (f0.0) mov (1) mbc_result.4<1>:ud mb_mv3.24<0,1,0>:ud {align1}; (f0.0) jmpi (1) mb_mvp_start; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L1 {align1}; (f0.0) mov (1) mbc_result.18<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbc_result.22<1>:w 0:w {align1}; (f0.0) mov (1) mbc_result.8<1>:ud mb_mv3.28<0,1,0>:ud {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (2) mbc_result.16<1>:uw MB_PRED_FLAG {align1}; mov (2) mbc_result.20<1>:w 0:w {align1}; mov (2) mbc_result.4<1>:ud mb_mv3.24<2,2,1>:ud {align1}; mb_mvp_start: /*TODO: Add the skip prediction */ /* Check whether both MB B and C are inavailable */ add (1) tmp_reg0.0<1>:d mbb_result.0<0,1,0>:d mbc_result.0<0,1,0>:d {align1}; cmp.z.f0.0 (1) null:d tmp_reg0.0<0,1,0>:d 0:d {align1}; (-f0.0) jmpi (1) mb_median_start; cmp.nz.f0.0 (1) null:d mba_result.0<0,1,0>:d 0:d {align1}; (f0.0) mov (2) mbb_result.4<1>:ud mba_result.4<2,2,1>:ud {align1}; (f0.0) mov (2) mbc_result.4<1>:ud mba_result.4<2,2,1>:ud {align1}; (f0.0) mov (2) mbb_result.20<1>:uw mba_result.20<2,2,1>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:uw mba_result.20<2,2,1>:uw {align1}; (f0.0) mov (2) mb_mvp_ref.0<1>:ud mba_result.4<2,2,1>:ud {align1}; (-f0.0) mov (2) mb_mvp_ref.0<1>:ud 0:ud {align1}; jmpi (1) __mb_hwdep_end; mb_median_start: /* forward_MVP */ /* check whether only one neighbour MB has the same ref ID with the current MB */ mov (8) tmp_reg0.0<1>:ud 0:ud {align1}; cmp.z.f0.0 (1) null:d mba_result.20<0,1,0>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbb_result.20<0,1,0>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbc_result.20<0,1,0>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.4<0,1,0>:ud {align1}; cmp.e.f0.0 (1) null:d tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud tmp_reg0.4<0,1,0>:ud {align1}; (f0.0) jmpi (1) mvp_backward; mov (1) INPUT_ARG0.0<1>:w mba_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.4<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.0<1>:w RET_ARG<0,1,0>:w {align1}; mov (1) INPUT_ARG0.0<1>:w mba_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.6<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.2<1>:w RET_ARG<0,1,0>:w {align1}; mvp_backward: /* check whether only one neighbour MB has the same ref ID with the current MB */ mov (8) tmp_reg0.0<1>:ud 0:ud {align1}; cmp.z.f0.0 (1) null:d mba_result.22<0,1,0>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.8<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbb_result.22<0,1,0>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.8<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbc_result.22<0,1,0>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.8<0,1,0>:ud {align1}; cmp.e.f0.0 (1) null:d tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) mb_mvp_ref.4<1>:ud tmp_reg0.4<0,1,0>:ud {align1}; (f0.0) jmpi (1) __mb_hwdep_end; mov (1) INPUT_ARG0.0<1>:w mba_result.8<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.8<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.8<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.4<1>:w RET_ARG<0,1,0>:w {align1}; mov (1) INPUT_ARG0.0<1>:w mba_result.10<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.10<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.10<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.6<1>:w RET_ARG<0,1,0>:w {align1}; __mb_hwdep_end: asr (4) mb_ref_win.0<1>:w mb_mvp_ref.0<4,4,1>:w 2:w {align1}; add (4) mb_ref_win.8<1>:w mb_ref_win.0<4,4,1>:w 3:w {align1}; and (4) mb_ref_win.16<1>:uw mb_ref_win.8<4,4,1>:uw 0xFFFC:uw {align1}; /* m2, get the MV/Mb cost passed from constant buffer when spawning thread by MEDIA_OBJECT */ mov (8) vme_m2<1>:UD r1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* m3 cost center */ mov (8) vme_m3.0<1>:ud 0x0:ud {align1}; mov (8) vme_msg_3<1>:UD vme_m3.0<8,8,1>:UD {align1}; /* m4. skip center */ mov (8) vme_msg_4<1>:ud 0x0:ud {align1}; /* m5 */ mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1}; and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1}; mov (8) vme_msg_5<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; /* Use the Luma mode */ mov (1) tmp_reg0.0<1>:UW LUMA_INTRA_MODE:UW {align1}; mov (1) vme_msg_5.5<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* m6 */ mov (8) vme_msg_6<1>:UD 0x0:UD {align1}; mov (16) vme_msg_6.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1}; mov (1) vme_msg_6.16<1>:UD INTRA_PREDICTORE_MODE {align1}; /* the penalty for Intra mode */ mov (1) vme_msg_6.28<1>:UD 0x010101:UD {align1}; mov (1) vme_msg_6.20<1>:UW CHROMA_ROW.6<0,1,0>:UW {align1}; /* m7 */ mov (4) vme_msg_7.16<1>:UD CHROMA_ROW.8<4,4,1>:UD {align1}; mov (8) vme_msg_7.0<1>:UW CHROMA_COL.2<16,8,2>:UW {align1}; /* * SIC VME message */ /* m1 */ mov (1) intra_flag<1>:UW 0x0:UW {align1} ; and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1}; (f0.0) mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE {align1}; /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; /* Disable DC HAAR component when calculating HARR SATD block */ mov (1) tmp_reg0.0<1>:UW DC_HARR_DISABLE:UW {align1}; mov (1) vme_m1.30<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* m0 */ mov (1) vme_m0.12<1>:UD INTRA_SAD_HAAR:UD {align1}; /* 16x16 Source, Intra_harr */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_SIC_MESSAGE_TYPE ) mlen sic_vme_msg_length rlen vme_wb_length {align1}; /* * Oword Block Write message */ mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Distortion, Intra (17-16), */ mov (1) msg_reg1.16<1>:UW vme_wb.12<0,1,0>:UW {align1}; mov (1) msg_reg1.20<1>:UD vme_wb.8<0,1,0>:UD {align1}; /* VME clock counts */ mov (1) msg_reg1.24<1>:UD vme_wb.28<0,1,0>:UD {align1}; mov (1) msg_reg1.28<1>:UD obw_m0.8<0,1,0>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* IME search */ mov (1) vme_m0.12<1>:UD SEARCH_CTRL_DUAL_REFERENCE + INTER_PART_MASK + INTER_SAD_HAAR:UD {align1}; /* 16x16 Source, harr */ mov (1) vme_m0.22<1>:UW DREF_REGION_SIZE {align1}; /* Dual Reference Width&Height,32x32 */ mov (1) vme_m0.0<1>:UD vme_m0.8<0,1,0>:UD {align1}; /* Reference = (x-8,y-8)-(x+8,y+8) */ add (1) vme_m0.0<1>:W vme_m0.0<0,1,0>:W -8:W {align1}; add (1) vme_m0.2<1>:W vme_m0.2<0,1,0>:W -8:W {align1}; mov (1) vme_m0.0<1>:W -8:W {align1}; mov (1) vme_m0.2<1>:W -8:W {align1}; mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; (f0.0) add (1) vme_m0.0<1>:w vme_m0.0<0,1,0>:w 4:w {align1}; (f0.0) add (1) vme_m0.4<1>:w vme_m0.4<0,1,0>:w 4:w {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; (f0.0) add (1) vme_m0.2<1>:w vme_m0.2<0,1,0>:w 4:w {align1}; (f0.0) add (1) vme_m0.6<1>:w vme_m0.6<0,1,0>:w 4:w {align1}; add (2) vme_m0.0<1>:w vme_m0.0<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; add (2) vme_m0.4<1>:w vme_m0.4<2,2,1>:w mb_ref_win.20<2,2,1>:w {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; /* the Max MV number is passed by constant buffer */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; mov (1) vme_m1.8<1>:UD DSTART_CENTER + DSEARCH_PATH_LEN:UD {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* Setup the Cost center */ /* currently four 8x8 share the same cost center */ mov (4) vme_m3.0<2>:ud mb_mvp_ref.0<0,1,0>:ud {align1}; mov (4) vme_m3.4<2>:ud mb_mvp_ref.4<0,1,0>:ud {align1}; /* M4/M5 search path */ mov (1) vme_msg_4.0<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_4.4<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_4.8<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_4.12<1>:UD 0x000F0F0F:UD {align1}; mov (4) vme_msg_4.16<1>:UD 0x0:UD {align1}; mov (8) vme_msg_5.16<1>:UD 0x0:UD {align1}; send (8) vme_msg_ind vme_wb<1>:UD null vme( BIND_IDX_VME, 0, 0, VME_IME_MESSAGE_TYPE ) mlen ime_vme_msg_length rlen vme_wb_length {align1}; /* Set Macroblock-shape/mode for FBR */ mov (1) vme_m2.20<1>:UD 0x0:UD {align1}; mov (1) vme_m2.21<1>:UB vme_wb.25<0,1,0>:UB {align1}; mov (1) vme_m2.22<1>:UB vme_wb.26<0,1,0>:UB {align1}; and (1) tmp_reg0.0<1>:UW vme_wb.0<0,1,0>:UW 0x03:UW {align1}; mov (1) vme_m2.20<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* Send FBR message into CRE */ mov (8) vme_msg_4.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) vme_msg_5.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) vme_msg_6.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) vme_msg_7.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; /* 16x16 Source, 1/4 pixel, harr, BME ENABLE */ mov (1) vme_m0.12<1>:UD INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER + FBR_BME_ENABLE:UD {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (1) tmp_reg0.0<1>:uw BI_WEIGHT {align1}; mov (1) vme_m1.6<1>:UB tmp_reg0.0<0,1,0>:ub {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2.0<1>:UD vme_m2.0<8,8,1>:UD {align1}; mov (8) vme_msg_3.0<1>:UD vme_m3.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_FBR_MESSAGE_TYPE ) mlen fbr_vme_msg_length rlen vme_wb_length {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; /* write FME info */ mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Inter distortion of FME */ mov (1) msg_reg1.8<1>:UD vme_wb.8<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_m2.20<0,1,0>:UD {align1}; /* bind index 3, write oword (16bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_0, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Write FME/BME MV */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x01:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0.0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) msg_reg2.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) msg_reg3.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) msg_reg4.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; /* bind index 3, write 8 oword (128 bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_8, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 5 rlen obw_wb_length {align1}; /* Write FME/BME RefID */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x08:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb6.0<8,8,1>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Issue message fence so that the previous write message is committed */ send (16) mb_ind obw_wb NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_FENCE, OBR_MF_COMMIT, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; nop ; nop ; /* Compare three word data to get the min value */ word_imin: cmp.le.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; cmp.le.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; RETURN {align1}; /* Compare three word data to get the max value */ word_imax: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; cmp.ge.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; RETURN {align1}; word_imedian: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_a_ge_b; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; jmpi (1) cmp_end; cmp_a_ge_b: cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; cmp_end: RETURN {align1}; mb_pred_func: mov (8) TEMP_VAR0.0<1>:ud 0:ud {align1}; mov (1) TEMP_VAR0.0<1>:ub INPUT_ARG0.2<0,1,0>:ub {align1}; and (1) TEMP_VAR0.4<1>:uw INPUT_ARG0.4<0,1,0>:uw INTER_MASK:uw {align1}; /* INTER16x16 mode. The bit1-0 is the prediction mode */ cmp.e.f0.0 (1) null:uw TEMP_VAR0.4<0,1,0>:uw INTER_16X16MODE:uw {align1}; (f0.0) and (1) RET_ARG<1>:uw TEMP_VAR0.0<0,1,0>:uw PRED_MASK {align1}; (f0.0) jmpi (1) end_mb_pred; /* Check whether it is INTER8x8 mode. */ cmp.e.f0.0 (1) null:uw TEMP_VAR0.4<0,1,0>:uw INTER_8X8MODE:uw {align1}; (f0.0) jmpi (1) mb_pred_func_8; /* Check whether it is INTER16x8 mode. */ cmp.e.f0.0 (1) null:uw TEMP_VAR0.4<0,1,0>:uw INTER_16X8MODE:uw {align1}; (f0.0) jmpi (1) mb_pred_func_168; mb_pred_func_816: /* Block 0/2 uses the bit1-0. Block 1/3 uses the bit3-2 */ mov (1) TEMP_VAR0.8<1>:uw INPUT_ARG0.8<0,1,0>:uw {align1}; and.z.f0.0 (1) null:uw TEMP_VAR0.8<0,1,0>:uw INTER_BLOCK1:uw {align1}; (f0.0) and (1) RET_ARG<1>:uw TEMP_VAR0.0<0,1,0>:uw PRED_MASK {align1}; (f0.0) jmpi (1) end_mb_pred; shr (1) TEMP_VAR0.16<1>:uw TEMP_VAR0.0<0,1,0>:uw 2:uw {align1}; and (1) RET_ARG<1>:uw TEMP_VAR0.16<0,1,0>:uw PRED_MASK {align1}; jmpi (1) end_mb_pred; mb_pred_func_168: /* Block 0/1 uses the bit1-0. Block 2/3 uses the bit3-2 */ mov (1) TEMP_VAR0.8<1>:uw INPUT_ARG0.8<0,1,0>:uw {align1}; cmp.l.f0.0 (1) null:uw TEMP_VAR0.8<0,1,0>:uw INTER_BLOCK2:uw {align1}; (f0.0) and (1) RET_ARG<1>:uw TEMP_VAR0.0<0,1,0>:uw PRED_MASK {align1}; (f0.0) jmpi (1) end_mb_pred; shr (1) TEMP_VAR0.16<1>:uw TEMP_VAR0.0<0,1,0>:uw 2:uw {align1}; and (1) RET_ARG<1>:uw TEMP_VAR0.16<0,1,0>:uw PRED_MASK {align1}; jmpi (1) end_mb_pred; mb_pred_func_8: /* 8X8 mode. Every block uses two bits as the prediction mode. */ mul (1) TEMP_VAR0.8<1>:uw INPUT_ARG0.8<0,1,0>:uw 2:uw {align1}; shr (1) TEMP_VAR0.16<1>:uw TEMP_VAR0.0<0,1,0>:uw TEMP_VAR0.8<0,1,0>:uw {align1}; and (1) RET_ARG<1>:uw TEMP_VAR0.16<0,1,0>:uw PRED_MASK {align1}; end_mb_pred: RETURN {align1}; intel-driver-1.3.0/src/shaders/vme/inter_bframe_gen8.g8a000066400000000000000000000000651231401140700230770ustar00rootroot00000000000000#include "vme8.inc" #include "inter_bframe_gen8.asm" intel-driver-1.3.0/src/shaders/vme/inter_bframe_gen8.g8b000066400000000000000000000553411231401140700231070ustar00rootroot00000000000000 { 0x00800001, 0x24000608, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400608, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800608, 0x00000000, 0x00000000 }, { 0x00800001, 0x24c00608, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002228, 0x164500a0, 0x00040004 }, { 0x00000040, 0x24000a28, 0x1e000400, 0xfff8fff8 }, { 0x00000040, 0x24040a28, 0x1e000404, 0xffffffff }, { 0x00000001, 0x24080e08, 0x08000000, 0x0000001f }, { 0x00000001, 0x24142288, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202228, 0x164500a0, 0x00040004 }, { 0x00000040, 0x24200a28, 0x1e000420, 0xfffcfffc }, { 0x00000001, 0x24280e08, 0x08000000, 0x000f0003 }, { 0x00000001, 0x24342288, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482248, 0x164500a0, 0x00040004 }, { 0x00000001, 0x24542288, 0x00000014, 0x00000000 }, { 0x00000041, 0x24881208, 0x220000a2, 0x000000a1 }, { 0x00000040, 0x24880208, 0x22000488, 0x000000a0 }, { 0x00000041, 0x24880208, 0x06000488, 0x00000018 }, { 0x00000001, 0x24942288, 0x00000014, 0x00000000 }, { 0x00600001, 0x28000208, 0x008d0400, 0x00000000 }, { 0x04600031, 0x23800a88, 0x0e000800, 0x02190004 }, { 0x00600001, 0x28000208, 0x008d0420, 0x00000000 }, { 0x04600031, 0x23a00a88, 0x0e000800, 0x02290004 }, { 0x00200009, 0x24002228, 0x164500a0, 0x00030003 }, { 0x00000041, 0x24000a28, 0x1e000400, 0x00020002 }, { 0x00000040, 0x24000a28, 0x1e000400, 0xfff8fff8 }, { 0x00000040, 0x24040a28, 0x1e000404, 0xffffffff }, { 0x00600001, 0x28000208, 0x008d0400, 0x00000000 }, { 0x04600031, 0x26000a88, 0x0e000800, 0x02190006 }, { 0x00200009, 0x24202228, 0x164500a0, 0x00030003 }, { 0x00000041, 0x24200a28, 0x1e000420, 0x00020002 }, { 0x00000040, 0x24200a28, 0x1e000420, 0xfffcfffc }, { 0x00000001, 0x24280e08, 0x08000000, 0x00070003 }, { 0x00600001, 0x28000208, 0x008d0420, 0x00000000 }, { 0x04600031, 0x26200a88, 0x0e000800, 0x02190006 }, { 0x00600001, 0x24600608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ac00608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a800608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20001240, 0x160000a6, 0x00040004 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000d60 }, { 0x00600001, 0x2ae00608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b000608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b200608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b400608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00600060 }, { 0x00210001, 0x2af41e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000210 }, { 0x00000001, 0x2ae00e28, 0x08000000, 0x00000001 }, { 0x00200001, 0x24002248, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24001a68, 0x1e000400, 0xffffffff }, { 0x00000041, 0x2b481208, 0x120000a2, 0x00000402 }, { 0x00000040, 0x2b480208, 0x12000b48, 0x00000400 }, { 0x00000041, 0x2b480208, 0x06000b48, 0x00000018 }, { 0x00000001, 0x2b542288, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x02280303 }, { 0x05000010, 0x20001260, 0x12000b70, 0x00000b88 }, { 0x00210001, 0x2af41e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000160 }, { 0x00000040, 0x2b480208, 0x06000b48, 0x00000003 }, { 0x0a800031, 0x2ba00a08, 0x0e000b40, 0x02480403 }, { 0x00200001, 0x2af41e68, 0x18000000, 0xffffffff }, { 0x00000001, 0x2fa00208, 0x00000b84, 0x00000000 }, { 0x00000001, 0x2fa40208, 0x00000b80, 0x00000000 }, { 0x00000001, 0x2fa80608, 0x00000000, 0x00000001 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00001490 }, { 0x00000001, 0x2aa01248, 0x00000fe4, 0x00000000 }, { 0x01000010, 0x20001240, 0x16000aa0, 0x00000000 }, { 0x00010001, 0x2af01e48, 0x18000000, 0x00010001 }, { 0x00010001, 0x2af41e68, 0x18000000, 0x00000000 }, { 0x00010001, 0x2ae40208, 0x00000bc8, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000080 }, { 0x01000010, 0x20001240, 0x16000aa0, 0x00010001 }, { 0x00010001, 0x2af21e48, 0x18000000, 0x00010001 }, { 0x00010001, 0x2af61e68, 0x18000000, 0x00000000 }, { 0x00010001, 0x2ae80208, 0x00000bcc, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000030 }, { 0x00200001, 0x2ae40208, 0x00450bc8, 0x00000000 }, { 0x00200001, 0x2af01e48, 0x18000000, 0x00010001 }, { 0x00200001, 0x2af41e68, 0x18000000, 0x00000000 }, { 0x00600001, 0x2b400608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00100010 }, { 0x00210001, 0x2b141e68, 0x18000000, 0xffffffff }, { 0x00210001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x000006c0 }, { 0x00000001, 0x2b000e28, 0x08000000, 0x00000001 }, { 0x00200001, 0x24002248, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24021a68, 0x1e000402, 0xffffffff }, { 0x00000041, 0x2b481208, 0x120000a2, 0x00000402 }, { 0x00000040, 0x2b480208, 0x12000b48, 0x00000400 }, { 0x00000041, 0x2b480208, 0x06000b48, 0x00000018 }, { 0x00000001, 0x2b542288, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x02280303 }, { 0x05000010, 0x20001260, 0x12000b70, 0x00000b88 }, { 0x00210001, 0x2b141e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000160 }, { 0x00000040, 0x2b480208, 0x06000b48, 0x00000003 }, { 0x0a800031, 0x2ba00a08, 0x0e000b40, 0x02480403 }, { 0x00200001, 0x2b141e68, 0x18000000, 0xffffffff }, { 0x00000001, 0x2fa00208, 0x00000b84, 0x00000000 }, { 0x00000001, 0x2fa40208, 0x00000b80, 0x00000000 }, { 0x00000001, 0x2fa80608, 0x00000000, 0x00000002 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00001230 }, { 0x00000001, 0x2aa01248, 0x00000fe4, 0x00000000 }, { 0x01000010, 0x20001240, 0x16000aa0, 0x00000000 }, { 0x00010001, 0x2b101e48, 0x18000000, 0x00010001 }, { 0x00010001, 0x2b141e68, 0x18000000, 0x00000000 }, { 0x00010001, 0x2b040208, 0x00000bf0, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000080 }, { 0x01000010, 0x20001240, 0x16000aa0, 0x00010001 }, { 0x00010001, 0x2b121e48, 0x18000000, 0x00010001 }, { 0x00010001, 0x2b161e68, 0x18000000, 0x00000000 }, { 0x00010001, 0x2b080208, 0x00000bf4, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000030 }, { 0x00200001, 0x2b101e48, 0x18000000, 0x00010001 }, { 0x00200001, 0x2b141e68, 0x18000000, 0x00000000 }, { 0x00200001, 0x2b040208, 0x00450bf0, 0x00000000 }, { 0x00600001, 0x2b400608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00080008 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000230 }, { 0x00000001, 0x2b200e28, 0x08000000, 0x00000001 }, { 0x00200001, 0x24002248, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24021a68, 0x1e000402, 0xffffffff }, { 0x00000040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00000041, 0x2b481208, 0x120000a2, 0x00000402 }, { 0x00000040, 0x2b480208, 0x12000b48, 0x00000400 }, { 0x00000041, 0x2b480208, 0x06000b48, 0x00000018 }, { 0x00000001, 0x2b542288, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x02280303 }, { 0x05000010, 0x20001260, 0x12000b70, 0x00000b88 }, { 0x00210001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x000003c0 }, { 0x00000040, 0x2b480208, 0x06000b48, 0x00000003 }, { 0x0a800031, 0x2ba00a08, 0x0e000b40, 0x02480403 }, { 0x00200001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00000001, 0x2fa00208, 0x00000b84, 0x00000000 }, { 0x00000001, 0x2fa40208, 0x00000b80, 0x00000000 }, { 0x00000001, 0x2fa80608, 0x00000000, 0x00000002 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000fe0 }, { 0x00000001, 0x2aa01248, 0x00000fe4, 0x00000000 }, { 0x01000010, 0x20001240, 0x16000aa0, 0x00000000 }, { 0x00010001, 0x2b301e48, 0x18000000, 0x00010001 }, { 0x00010001, 0x2b341e68, 0x18000000, 0x00000000 }, { 0x00010001, 0x2b240208, 0x00000bf0, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x000002e0 }, { 0x01000010, 0x20001240, 0x16000aa0, 0x00010001 }, { 0x00010001, 0x2b321e48, 0x18000000, 0x00010001 }, { 0x00010001, 0x2b361e68, 0x18000000, 0x00000000 }, { 0x00010001, 0x2b280208, 0x00000bf4, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000290 }, { 0x00200001, 0x2b301e48, 0x18000000, 0x00010001 }, { 0x00200001, 0x2b341e68, 0x18000000, 0x00000000 }, { 0x00200001, 0x2b240208, 0x00450bf0, 0x00000000 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000250 }, { 0x00600001, 0x2b400608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00040004 }, { 0x00210001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000210 }, { 0x00000001, 0x2b200e28, 0x08000000, 0x00000001 }, { 0x00200001, 0x24002248, 0x004500a0, 0x00000000 }, { 0x00200040, 0x24001a68, 0x1e450400, 0xffffffff }, { 0x00000041, 0x2b481208, 0x120000a2, 0x00000402 }, { 0x00000040, 0x2b480208, 0x12000b48, 0x00000400 }, { 0x00000041, 0x2b480208, 0x06000b48, 0x00000018 }, { 0x00000001, 0x2b542288, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x02280303 }, { 0x05000010, 0x20001260, 0x12000b70, 0x00000b88 }, { 0x00210001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000160 }, { 0x00000040, 0x2b480208, 0x06000b48, 0x00000003 }, { 0x0a800031, 0x2ba00a88, 0x0e000b40, 0x02480403 }, { 0x00200001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00000001, 0x2fa00208, 0x00000b84, 0x00000000 }, { 0x00000001, 0x2fa40208, 0x00000b80, 0x00000000 }, { 0x00000001, 0x2fa80608, 0x00000000, 0x00000003 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000d80 }, { 0x00000001, 0x2aa01248, 0x00000fe4, 0x00000000 }, { 0x01000010, 0x20001240, 0x16000aa0, 0x00000000 }, { 0x00010001, 0x2b301e48, 0x18000000, 0x00010001 }, { 0x00010001, 0x2b341e68, 0x18000000, 0x00000000 }, { 0x00010001, 0x2b240208, 0x00000c18, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000080 }, { 0x01000010, 0x20001240, 0x16000aa0, 0x00010001 }, { 0x00010001, 0x2b321e48, 0x18000000, 0x00010001 }, { 0x00010001, 0x2b361e68, 0x18000000, 0x00000000 }, { 0x00010001, 0x2b280208, 0x00000c1c, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000030 }, { 0x00200001, 0x2b301e48, 0x18000000, 0x00010001 }, { 0x00200001, 0x2b341e68, 0x18000000, 0x00000000 }, { 0x00200001, 0x2b240208, 0x00450c18, 0x00000000 }, { 0x00000040, 0x24000a28, 0x0a000b00, 0x00000b20 }, { 0x01000010, 0x20000a20, 0x0e000400, 0x00000000 }, { 0x00110020, 0x34000000, 0x0e001400, 0x00000080 }, { 0x02000010, 0x20000a20, 0x0e000ae0, 0x00000000 }, { 0x00210001, 0x2b040208, 0x00450ae4, 0x00000000 }, { 0x00210001, 0x2b240208, 0x00450ae4, 0x00000000 }, { 0x00210001, 0x2b141248, 0x00450af4, 0x00000000 }, { 0x00210001, 0x2b341248, 0x00450af4, 0x00000000 }, { 0x00210001, 0x2ac00208, 0x00450ae4, 0x00000000 }, { 0x00310001, 0x2ac00608, 0x00000000, 0x00000000 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000320 }, { 0x00600001, 0x24000608, 0x00000000, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000af4, 0x00000000 }, { 0x00010040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00010001, 0x24040208, 0x00000ae4, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000b14, 0x00000000 }, { 0x00010040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00010001, 0x24040208, 0x00000b04, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000b34, 0x00000000 }, { 0x00010040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00010001, 0x24040208, 0x00000b24, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000400, 0x00010001 }, { 0x00010001, 0x2ac00208, 0x00000404, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000c0 }, { 0x00000001, 0x2fa01a68, 0x00000ae4, 0x00000000 }, { 0x00000001, 0x2fa41a68, 0x00000b04, 0x00000000 }, { 0x00000001, 0x2fa81a68, 0x00000b24, 0x00000000 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x000009d0 }, { 0x00000001, 0x2ac01a68, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2fa01a68, 0x00000ae6, 0x00000000 }, { 0x00000001, 0x2fa41a68, 0x00000b06, 0x00000000 }, { 0x00000001, 0x2fa81a68, 0x00000b26, 0x00000000 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000970 }, { 0x00000001, 0x2ac21a68, 0x00000fe4, 0x00000000 }, { 0x00600001, 0x24000608, 0x00000000, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000af6, 0x00000000 }, { 0x00010040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00010001, 0x24040208, 0x00000ae8, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000b16, 0x00000000 }, { 0x00010040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00010001, 0x24040208, 0x00000b08, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000b36, 0x00000000 }, { 0x00010040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00010001, 0x24040208, 0x00000b28, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000400, 0x00010001 }, { 0x00010001, 0x2ac40208, 0x00000404, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000c0 }, { 0x00000001, 0x2fa01a68, 0x00000ae8, 0x00000000 }, { 0x00000001, 0x2fa41a68, 0x00000b08, 0x00000000 }, { 0x00000001, 0x2fa81a68, 0x00000b28, 0x00000000 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000840 }, { 0x00000001, 0x2ac41a68, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2fa01a68, 0x00000aea, 0x00000000 }, { 0x00000001, 0x2fa41a68, 0x00000b0a, 0x00000000 }, { 0x00000001, 0x2fa81a68, 0x00000b2a, 0x00000000 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x000007e0 }, { 0x00000001, 0x2ac61a68, 0x00000fe4, 0x00000000 }, { 0x0040000c, 0x2a801a68, 0x1e690ac0, 0x00020002 }, { 0x00400040, 0x2a881a68, 0x1e690a80, 0x00030003 }, { 0x00400005, 0x2a901248, 0x16690a88, 0xfffcfffc }, { 0x00600001, 0x25600208, 0x008d0020, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d0560, 0x00000000 }, { 0x00600001, 0x25800608, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600208, 0x008d0580, 0x00000000 }, { 0x00600001, 0x28800608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23800608, 0x00000000, 0x00000000 }, { 0x00000005, 0x23840208, 0x06000384, 0xff000000 }, { 0x00600001, 0x28a00208, 0x008d0380, 0x00000000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00010001 }, { 0x00000001, 0x28a52288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28c00608, 0x00000000, 0x00000000 }, { 0x00800001, 0x28c02288, 0x00cf03a3, 0x00000000 }, { 0x00000001, 0x28d00608, 0x00000000, 0x11111111 }, { 0x00000001, 0x28dc0608, 0x00000000, 0x00010101 }, { 0x00000001, 0x28d41248, 0x00000606, 0x00000000 }, { 0x00400001, 0x28f00208, 0x00690608, 0x00000000 }, { 0x00600001, 0x28e01248, 0x00ae0622, 0x00000000 }, { 0x00000001, 0x247c1648, 0x10000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a4, 0x00010001 }, { 0x00010001, 0x247c0e88, 0x08000000, 0x00000002 }, { 0x00000001, 0x247d2288, 0x000000a5, 0x00000000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00200020 }, { 0x00000001, 0x247e2288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x00000001, 0x244c0608, 0x00000000, 0x00800000 }, { 0x00600001, 0x28000208, 0x008d0440, 0x00000000 }, { 0x0d600031, 0x21800a08, 0x0e000800, 0x10782000 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200208, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240208, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280208, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0208, 0x00000198, 0x00000000 }, { 0x00000001, 0x28301248, 0x0000018c, 0x00000000 }, { 0x00000001, 0x28340208, 0x00000188, 0x00000000 }, { 0x00000001, 0x28380208, 0x0000019c, 0x00000000 }, { 0x00000001, 0x283c0208, 0x00000488, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x040a0203 }, { 0x00000001, 0x244c0608, 0x00000000, 0x00200700 }, { 0x00000001, 0x24561648, 0x10000000, 0x20202020 }, { 0x00000001, 0x24400208, 0x00000448, 0x00000000 }, { 0x00000040, 0x24401a68, 0x1e000440, 0xfff8fff8 }, { 0x00000040, 0x24421a68, 0x1e000442, 0xfff8fff8 }, { 0x00000001, 0x24401e68, 0x18000000, 0xfff8fff8 }, { 0x00000001, 0x24421e68, 0x18000000, 0xfff8fff8 }, { 0x00000001, 0x24440208, 0x00000440, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00600060 }, { 0x00010040, 0x24401a68, 0x1e000440, 0x00040004 }, { 0x00010040, 0x24441a68, 0x1e000444, 0x00040004 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00100010 }, { 0x00010040, 0x24421a68, 0x1e000442, 0x00040004 }, { 0x00010040, 0x24461a68, 0x1e000446, 0x00040004 }, { 0x00200040, 0x24401a68, 0x1a450440, 0x00450a90 }, { 0x00200040, 0x24441a68, 0x1a450444, 0x00450a94 }, { 0x00600001, 0x28000208, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24600608, 0x00000000, 0x00000002 }, { 0x00000001, 0x24642288, 0x0000009c, 0x00000000 }, { 0x00000001, 0x24680608, 0x00000000, 0x00001212 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d0560, 0x00000000 }, { 0x00400001, 0x45800208, 0x00000ac0, 0x00000000 }, { 0x00400001, 0x45840208, 0x00000ac4, 0x00000000 }, { 0x00000001, 0x28800608, 0x00000000, 0x10010101 }, { 0x00000001, 0x28840608, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28880608, 0x00000000, 0x10010101 }, { 0x00000001, 0x288c0608, 0x00000000, 0x000f0f0f }, { 0x00400001, 0x28900608, 0x00000000, 0x00000000 }, { 0x00600001, 0x28b00608, 0x00000000, 0x00000000 }, { 0x08600031, 0x21800a08, 0x0e000800, 0x0c784000 }, { 0x00000001, 0x25740608, 0x00000000, 0x00000000 }, { 0x00000001, 0x25752288, 0x00000199, 0x00000000 }, { 0x00000001, 0x25762288, 0x0000019a, 0x00000000 }, { 0x00000005, 0x24001248, 0x16000180, 0x00030003 }, { 0x00000001, 0x25742288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28800208, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28a00208, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28c00208, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28e00208, 0x008d0200, 0x00000000 }, { 0x00000001, 0x244c0608, 0x00000000, 0x00203000 }, { 0x00600001, 0x28000208, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00200020 }, { 0x00000001, 0x24662288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d0560, 0x00000000 }, { 0x00600001, 0x28600208, 0x008d0580, 0x00000000 }, { 0x0d600031, 0x21800a08, 0x0e000800, 0x10786000 }, { 0x00000040, 0x24880208, 0x06000488, 0x00000002 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200208, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240208, 0x00000198, 0x00000000 }, { 0x00000001, 0x28280208, 0x00000188, 0x00000000 }, { 0x00000001, 0x282c0208, 0x00000574, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x040a0003 }, { 0x00000040, 0x24880208, 0x06000488, 0x00000001 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28600208, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28800208, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x0a0a0403 }, { 0x00000040, 0x24880208, 0x06000488, 0x00000008 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d0240, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x040a0203 }, { 0x0a800031, 0x20000a60, 0x0e000b40, 0x0219e003 }, { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24000a40, 0x0e000e00, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x06000010, 0x20001a60, 0x1a000fa0, 0x00000fa4 }, { 0x00010001, 0x2f601a68, 0x00000fa0, 0x00000000 }, { 0x00110001, 0x2f601a68, 0x00000fa4, 0x00000000 }, { 0x06000010, 0x20001a60, 0x1a000f60, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000f60, 0x00000000 }, { 0x00110001, 0x2fe41a68, 0x00000fa8, 0x00000000 }, { 0x00000001, 0x34000200, 0x00000fe0, 0x00000000 }, { 0x04000010, 0x20001a60, 0x1a000fa0, 0x00000fa4 }, { 0x00010001, 0x2f601a68, 0x00000fa0, 0x00000000 }, { 0x00110001, 0x2f601a68, 0x00000fa4, 0x00000000 }, { 0x04000010, 0x20001a60, 0x1a000f60, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000f60, 0x00000000 }, { 0x00110001, 0x2fe41a68, 0x00000fa8, 0x00000000 }, { 0x00000001, 0x34000200, 0x00000fe0, 0x00000000 }, { 0x04000010, 0x20001a60, 0x1a000fa0, 0x00000fa4 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000070 }, { 0x04000010, 0x20001a60, 0x1a000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000fa0, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000a0 }, { 0x04000010, 0x20001a60, 0x1a000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe41a68, 0x00000fa4, 0x00000000 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000060 }, { 0x04000010, 0x20001a60, 0x1a000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000fa4, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000030 }, { 0x04000010, 0x20001a60, 0x1a000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe41a68, 0x00000fa0, 0x00000000 }, { 0x00000001, 0x34000200, 0x00000fe0, 0x00000000 }, { 0x00600001, 0x2f600608, 0x00000000, 0x00000000 }, { 0x00000001, 0x2f602288, 0x00000fa2, 0x00000000 }, { 0x00000005, 0x2f641248, 0x16000fa4, 0x00030003 }, { 0x01000010, 0x20001240, 0x16000f64, 0x00000000 }, { 0x00010005, 0x2fe41248, 0x16000f60, 0x00030003 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000150 }, { 0x01000010, 0x20001240, 0x16000f64, 0x00030003 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000100 }, { 0x01000010, 0x20001240, 0x16000f64, 0x00010001 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000070 }, { 0x00000001, 0x2f681248, 0x00000fa8, 0x00000000 }, { 0x01000005, 0x20001240, 0x16000f68, 0x00010001 }, { 0x00010005, 0x2fe41248, 0x16000f60, 0x00030003 }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000d0 }, { 0x00000008, 0x2f701248, 0x16000f60, 0x00020002 }, { 0x00000005, 0x2fe41248, 0x16000f70, 0x00030003 }, { 0x00000020, 0x34000000, 0x0e001400, 0x000000a0 }, { 0x00000001, 0x2f681248, 0x00000fa8, 0x00000000 }, { 0x05000010, 0x20001240, 0x16000f68, 0x00020002 }, { 0x00010005, 0x2fe41248, 0x16000f60, 0x00030003 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000060 }, { 0x00000008, 0x2f701248, 0x16000f60, 0x00020002 }, { 0x00000005, 0x2fe41248, 0x16000f70, 0x00030003 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000030 }, { 0x00000041, 0x2f681248, 0x16000fa8, 0x00020002 }, { 0x00000008, 0x2f701248, 0x12000f60, 0x00000f68 }, { 0x00000005, 0x2fe41248, 0x16000f70, 0x00030003 }, { 0x00000001, 0x34000200, 0x00000fe0, 0x00000000 }, intel-driver-1.3.0/src/shaders/vme/inter_bframe_haswell.asm000066400000000000000000001014321231401140700237760ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * Authors: Zhao Yakui */ // Modual name: Inter_bframe_haswell.asm // // Make inter predition estimation for Inter frame for B-frame // // // Now, begin source code.... // #define SAVE_RET add (1) RETURN_REG<1>:ud ip:ud 32:ud #define RETURN mov (1) ip:ud RETURN_REG<0,1,0>:ud /* * __START */ __INTER_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ; shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1}; mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1}; mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 24:UD {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* * Media Read Message -- fetch Luma neighbor edge pixels */ /* ROW */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1}; /* * Media Read Message -- fetch Chroma neighbor edge pixels */ /* ROW */ shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16 , y * 8 */ mul (1) read0_header.0<1>:D read0_header.0<0,1,0>:D 2:W {align1}; add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind CHROMA_ROW<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16, y * 8 */ mul (1) read1_header.0<1>:D read1_header.0<0,1,0>:D 2:W {align1}; add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_8X4 {align1}; mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind CHROMA_COL<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1}; mov (8) vme_m1.0<1>:ud 0:ud {align1}; mov (8) mb_mvp_ref.0<1>:ud 0:ud {align1}; mov (8) mb_ref_win.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1}; (f0.0) jmpi (1) __mb_hwdep_end; /* read back the data for MB A */ /* the layout of MB result is: rx.0(Available). rx.4(MVa), rX.8(MVb), rX.16(Pred_L0 flag), * rX.18 (Pred_L1 flag), rX.20(Forward reference ID), rX.22(Backwared reference ID) */ mov (8) mba_result.0<1>:ud 0x0:ud {align1}; mov (8) mbb_result.0<1>:ud 0x0:ud {align1}; mov (8) mbc_result.0<1>:ud 0x0:ud {align1}; mba_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; /* MB A doesn't exist. Zero MV. mba_flag is zero and ref ID = -1 */ (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; mov (1) mba_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB A */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* MV */ mov (2) mba_result.4<1>:ud mb_mv1.8<2,2,1>:ud {align1}; mov (2) mba_result.20<1>:w -1:w {align1}; mov (1) INPUT_ARG0.0<1>:ud mb_inter_wb.4<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.4<1>:ud mb_inter_wb.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud INTER_BLOCK1:ud {align1}; SAVE_RET {align1}; jmpi (1) mb_pred_func; mov (1) mb_pred_mode.0<1>:uw RET_ARG<0,1,0>:uw {align1}; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L0 {align1}; (f0.0) mov (1) mba_result.16<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mba_result.20<1>:w 0:w {align1}; (f0.0) jmpi (1) mbb_start; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L1 {align1}; (f0.0) mov (1) mba_result.18<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mba_result.22<1>:w 0:w {align1}; (f0.0) jmpi (1) mbb_start; mov (2) mba_result.16<1>:uw MB_PRED_FLAG {align1}; mov (2) mba_result.20<1>:w 0:w {align1}; mbb_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; /* MB B doesn't exist. Zero MV. mba_flag is zero */ /* If MB B doesn't exist, neither MB C nor D exists */ (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbb_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbc_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB B */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ mov (2) mbb_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1}; mov (2) mbb_result.20<1>:w -1:w {align1}; mov (1) INPUT_ARG0.0<1>:ud mb_inter_wb.4<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.4<1>:ud mb_inter_wb.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud INTER_BLOCK2:ud {align1}; SAVE_RET {align1}; jmpi (1) mb_pred_func; mov (1) mb_pred_mode.0<1>:uw RET_ARG<0,1,0>:uw {align1}; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L0 {align1}; (f0.0) mov (1) mbb_result.16<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbb_result.20<1>:w 0:w {align1}; (f0.0) jmpi (1) mbc_start; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L1 {align1}; (f0.0) mov (1) mbb_result.18<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbb_result.22<1>:w 0:w {align1}; (f0.0) jmpi (1) mbc_start; mov (2) mbb_result.16<1>:uw MB_PRED_FLAG {align1}; mov (2) mbb_result.20<1>:w 0:w {align1}; mbc_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_C:uw {align1}; /* MB C doesn't exist. Zero MV. mba_flag is zero */ /* Based on h264 spec the MB D will be replaced if MB C doesn't exist */ (f0.0) jmpi (1) mbd_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB C */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1}; mov (2) mbc_result.20<1>:w -1:w {align1}; mov (1) INPUT_ARG0.0<1>:ud mb_inter_wb.4<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.4<1>:ud mb_inter_wb.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud INTER_BLOCK2:ud {align1}; SAVE_RET {align1}; jmpi (1) mb_pred_func; mov (1) mb_pred_mode.0<1>:uw RET_ARG<0,1,0>:uw {align1}; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L0 {align1}; (f0.0) mov (1) mbc_result.16<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbc_result.20<1>:w 0:w {align1}; (f0.0) jmpi (1) mb_mvp_start; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L1 {align1}; (f0.0) mov (1) mbc_result.18<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbc_result.22<1>:w 0:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (2) mbc_result.16<1>:uw MB_PRED_FLAG {align1}; mov (2) mbc_result.20<1>:w 0:w {align1}; jmpi (1) mb_mvp_start; mbd_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_D:uw {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (2) tmp_reg0.0<1>:w tmp_reg0.0<2,2,1>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB D */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ub NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv3.24<2,2,1>:ud {align1}; mov (2) mbc_result.20<1>:w -1:w {align1}; mov (1) INPUT_ARG0.0<1>:ud mb_inter_wb.4<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.4<1>:ud mb_inter_wb.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud INTER_BLOCK3:ud {align1}; SAVE_RET {align1}; jmpi (1) mb_pred_func; mov (1) mb_pred_mode.0<1>:uw RET_ARG<0,1,0>:uw {align1}; mov (1) mbc_result.18<1>:w MB_PRED_FLAG {align1}; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L0 {align1}; (f0.0) mov (1) mbc_result.16<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbc_result.20<1>:w 0:w {align1}; (f0.0) jmpi (1) mb_mvp_start; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L1 {align1}; (f0.0) mov (1) mbc_result.18<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbc_result.22<1>:w 0:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (2) mbc_result.16<1>:uw MB_PRED_FLAG {align1}; mov (2) mbc_result.20<1>:w 0:w {align1}; mb_mvp_start: /*TODO: Add the skip prediction */ /* Check whether both MB B and C are inavailable */ add (1) tmp_reg0.0<1>:d mbb_result.0<0,1,0>:d mbc_result.0<0,1,0>:d {align1}; cmp.z.f0.0 (1) null:d tmp_reg0.0<0,1,0>:d 0:d {align1}; (-f0.0) jmpi (1) mb_median_start; cmp.nz.f0.0 (1) null:d mba_result.0<0,1,0>:d 0:d {align1}; (f0.0) mov (2) mbb_result.4<1>:ud mba_result.4<2,2,1>:ud {align1}; (f0.0) mov (2) mbc_result.4<1>:ud mba_result.4<2,2,1>:ud {align1}; (f0.0) mov (2) mbb_result.20<1>:uw mba_result.20<2,2,1>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:uw mba_result.20<2,2,1>:uw {align1}; (f0.0) mov (2) mb_mvp_ref.0<1>:ud mba_result.4<2,2,1>:ud {align1}; (-f0.0) mov (2) mb_mvp_ref.0<1>:ud 0:ud {align1}; jmpi (1) __mb_hwdep_end; mb_median_start: /* forward_MVP */ /* check whether only one neighbour MB has the same ref ID with the current MB */ mov (8) tmp_reg0.0<1>:ud 0:ud {align1}; cmp.z.f0.0 (1) null:d mba_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbb_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbc_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.4<0,1,0>:ud {align1}; cmp.e.f0.0 (1) null:d tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud tmp_reg0.4<0,1,0>:ud {align1}; (f0.0) jmpi (1) mvp_backward; mov (1) INPUT_ARG0.0<1>:w mba_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.4<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.0<1>:w RET_ARG<0,1,0>:w {align1}; mov (1) INPUT_ARG0.0<1>:w mba_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.6<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.2<1>:w RET_ARG<0,1,0>:w {align1}; mvp_backward: /* check whether only one neighbour MB has the same ref ID with the current MB */ mov (8) tmp_reg0.0<1>:ud 0:ud {align1}; cmp.z.f0.0 (1) null:d mba_result.22<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.8<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbb_result.22<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.8<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbc_result.22<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.8<0,1,0>:ud {align1}; cmp.e.f0.0 (1) null:d tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) mb_mvp_ref.4<1>:ud tmp_reg0.4<0,1,0>:ud {align1}; (f0.0) jmpi (1) __mb_hwdep_end; mov (1) INPUT_ARG0.0<1>:w mba_result.8<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.8<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.8<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.4<1>:w RET_ARG<0,1,0>:w {align1}; mov (1) INPUT_ARG0.0<1>:w mba_result.10<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.10<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.10<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.6<1>:w RET_ARG<0,1,0>:w {align1}; __mb_hwdep_end: asr (4) mb_ref_win.0<1>:w mb_mvp_ref.0<4,4,1>:w 2:w {align1}; add (4) mb_ref_win.8<1>:w mb_ref_win.0<4,4,1>:w 3:w {align1}; and (4) mb_ref_win.16<1>:uw mb_ref_win.8<4,4,1>:uw 0xFFFC:uw {align1}; /* m2, get the MV/Mb cost passed from constant buffer when spawning thread by MEDIA_OBJECT */ mov (8) vme_m2<1>:UD r1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* m3 */ mov (8) vme_msg_3<1>:UD 0x0:UD {align1}; /* m4 */ mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1}; and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1}; mov (8) vme_msg_4<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; /* m5 */ mov (8) vme_msg_5<1>:UD 0x0:UD {align1}; mov (16) vme_msg_5.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1}; mov (1) vme_msg_5.16<1>:UD INTRA_PREDICTORE_MODE {align1}; /* the penalty for Intra mode */ mov (1) vme_msg_5.28<1>:UD 0x010101:UD {align1}; mov (1) vme_msg_5.20<1>:UW CHROMA_ROW.6<0,1,0>:UW {align1}; /* m6 */ mov (4) vme_msg_6.16<1>:UD CHROMA_ROW.8<4,4,1>:UD {align1}; mov (8) vme_msg_6.0<1>:UW CHROMA_COL.2<16,8,2>:UW {align1}; /* * SIC VME message */ /* m0 */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (1) tmp_reg0.0<1>:UW LUMA_INTRA_MODE:UW {align1}; /* Use the Luma mode */ mov (1) vme_msg_4.5<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* m1 */ mov (1) intra_flag<1>:UW 0x0:UW {align1} ; and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1}; (f0.0) mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE {align1}; /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; /* Disable DC HAAR component when calculating HARR SATD block */ mov (1) tmp_reg0.0<1>:UW DC_HARR_DISABLE:UW {align1}; mov (1) vme_m1.30<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; mov (1) vme_m0.12<1>:UD INTRA_SAD_HAAR:UD {align1}; /* 16x16 Source, Intra_harr */ /* m0 */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_SIC_MESSAGE_TYPE ) mlen sic_vme_msg_length rlen vme_wb_length {align1}; /* * Oword Block Write message */ mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Distortion, Intra (17-16), */ mov (1) msg_reg1.16<1>:UW vme_wb.12<0,1,0>:UW {align1}; mov (1) msg_reg1.20<1>:UD vme_wb.8<0,1,0>:UD {align1}; /* VME clock counts */ mov (1) msg_reg1.24<1>:UD vme_wb.28<0,1,0>:UD {align1}; mov (1) msg_reg1.28<1>:UD obw_m0.8<0,1,0>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* IME search */ mov (1) vme_m0.12<1>:UD SEARCH_CTRL_DUAL_REFERENCE + INTER_PART_MASK + INTER_SAD_HAAR:UD {align1}; /* 16x16 Source, harr */ mov (1) vme_m0.22<1>:UW DREF_REGION_SIZE {align1}; /* Dual Reference Width&Height,32x32 */ mov (1) vme_m0.0<1>:UD vme_m0.8<0,1,0>:UD {align1}; /* Reference = (x-8,y-8)-(x+8,y+8) */ add (1) vme_m0.0<1>:W vme_m0.0<0,1,0>:W -8:W {align1}; add (1) vme_m0.2<1>:W vme_m0.2<0,1,0>:W -8:W {align1}; mov (1) vme_m0.0<1>:W -8:W {align1}; mov (1) vme_m0.2<1>:W -8:W {align1}; mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; (f0.0) add (1) vme_m0.0<1>:w vme_m0.0<0,1,0>:w 4:w {align1}; (f0.0) add (1) vme_m0.4<1>:w vme_m0.4<0,1,0>:w 4:w {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; (f0.0) add (1) vme_m0.2<1>:w vme_m0.2<0,1,0>:w 4:w {align1}; (f0.0) add (1) vme_m0.6<1>:w vme_m0.6<0,1,0>:w 4:w {align1}; add (2) vme_m0.0<1>:w vme_m0.0<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; add (2) vme_m0.4<1>:w vme_m0.4<2,2,1>:w mb_ref_win.20<2,2,1>:w {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; /* the Max MV number is passed by constant buffer */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; mov (1) vme_m1.8<1>:UD DSTART_CENTER + DSEARCH_PATH_LEN:UD {align1}; /* Set the MV cost center */ mov (1) vme_m1.16<1>:ud mb_mvp_ref.0<0,1,0>:ud {align1}; mov (1) vme_m1.20<1>:ud mb_mvp_ref.4<0,1,0>:ud {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* M3/M4 search path */ mov (1) vme_msg_3.0<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_3.4<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_3.8<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_3.12<1>:UD 0x000F0F0F:UD {align1}; mov (4) vme_msg_3.16<1>:UD 0x0:UD {align1}; mov (8) vme_msg_4.16<1>:UD 0x0:UD {align1}; send (8) vme_msg_ind vme_wb<1>:UD null vme( BIND_IDX_VME, 0, 0, VME_IME_MESSAGE_TYPE ) mlen ime_vme_msg_length rlen vme_wb_length {align1}; /* Set Macroblock-shape/mode for FBR */ mov (1) vme_m2.20<1>:UD 0x0:UD {align1}; mov (1) vme_m2.21<1>:UB vme_wb.25<0,1,0>:UB {align1}; mov (1) vme_m2.22<1>:UB vme_wb.26<0,1,0>:UB {align1}; and (1) tmp_reg0.0<1>:UW vme_wb.0<0,1,0>:UW 0x03:UW {align1}; mov (1) vme_m2.20<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* Send FBR message into CRE */ mov (8) vme_msg_3.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) vme_msg_4.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) vme_msg_5.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) vme_msg_6.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; /* 16x16 Source, 1/4 pixel, harr, BME ENABLE */ mov (1) vme_m0.12<1>:UD INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER + FBR_BME_ENABLE:UD {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (1) tmp_reg0.0<1>:uw BI_WEIGHT {align1}; mov (1) vme_m1.6<1>:UB tmp_reg0.0<0,1,0>:ub {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2.0<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_FBR_MESSAGE_TYPE ) mlen fbr_vme_msg_length rlen vme_wb_length {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; /* write FME info */ mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Inter distortion of FME */ mov (1) msg_reg1.8<1>:UD vme_wb.8<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_m2.20<0,1,0>:UD {align1}; /* bind index 3, write oword (16bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_0, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Write FME/BME MV */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x01:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0.0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) msg_reg2.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) msg_reg3.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) msg_reg4.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; /* bind index 3, write 8 oword (128 bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_8, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 5 rlen obw_wb_length {align1}; /* Write FME/BME RefID */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x08:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb6.0<8,8,1>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Issue message fence so that the previous write message is committed */ send (16) mb_ind obw_wb NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_FENCE, OBR_MF_COMMIT, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; nop ; nop ; /* Compare three word data to get the min value */ word_imin: cmp.le.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; cmp.le.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; RETURN {align1}; /* Compare three word data to get the max value */ word_imax: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; cmp.ge.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; RETURN {align1}; word_imedian: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_a_ge_b; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; jmpi (1) cmp_end; cmp_a_ge_b: cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; cmp_end: RETURN {align1}; mb_pred_func: mov (8) TEMP_VAR0.0<1>:ud 0:ud {align1}; mov (1) TEMP_VAR0.0<1>:ub INPUT_ARG0.2<0,1,0>:ub {align1}; and (1) TEMP_VAR0.4<1>:uw INPUT_ARG0.4<0,1,0>:uw INTER_MASK:uw {align1}; /* INTER16x16 mode. The bit1-0 is the prediction mode */ cmp.e.f0.0 (1) null:uw TEMP_VAR0.4<1>:uw INTER_16X16MODE:uw {align1}; (f0.0) and (1) RET_ARG<1>:uw TEMP_VAR0.0<0,1,0>:uw PRED_MASK {align1}; (f0.0) jmpi (1) end_mb_pred; /* Check whether it is INTER8x8 mode. */ cmp.e.f0.0 (1) null:uw TEMP_VAR0.4<1>:uw INTER_8X8MODE:uw {align1}; (f0.0) jmpi (1) mb_pred_func_8; /* Check whether it is INTER16x8 mode. */ cmp.e.f0.0 (1) null:uw TEMP_VAR0.4<1>:uw INTER_16X8MODE:uw {align1}; (f0.0) jmpi (1) mb_pred_func_168; mb_pred_func_816: /* Block 0/2 uses the bit1-0. Block 1/3 uses the bit3-2 */ mov (1) TEMP_VAR0.8<1>:uw INPUT_ARG0.8<0,1,0>:uw {align1}; and.z.f0.0 (1) null:uw TEMP_VAR0.8<1>:uw INTER_BLOCK1:uw {align1}; (f0.0) and (1) RET_ARG<1>:uw TEMP_VAR0.0<0,1,0>:uw PRED_MASK {align1}; (f0.0) jmpi (1) end_mb_pred; shr (1) TEMP_VAR0.16<1>:uw TEMP_VAR0.0<0,1,0>:uw 2:uw {align1}; and (1) RET_ARG<1>:uw TEMP_VAR0.16<1>:uw PRED_MASK {align1}; jmpi (1) end_mb_pred; mb_pred_func_168: /* Block 0/1 uses the bit1-0. Block 2/3 uses the bit3-2 */ mov (1) TEMP_VAR0.8<1>:uw INPUT_ARG0.8<0,1,0>:uw {align1}; cmp.l.f0.0 (1) null:uw TEMP_VAR0.8<1>:uw INTER_BLOCK2:uw {align1}; (f0.0) and (1) RET_ARG<1>:uw TEMP_VAR0.0<0,1,0>:uw PRED_MASK {align1}; (f0.0) jmpi (1) end_mb_pred; shr (1) TEMP_VAR0.16<1>:uw TEMP_VAR0.0<0,1,0>:uw 2:uw {align1}; and (1) RET_ARG<1>:uw TEMP_VAR0.16<1>:uw PRED_MASK {align1}; jmpi (1) end_mb_pred; mb_pred_func_8: /* 8X8 mode. Every block uses two bits as the prediction mode. */ mul (1) TEMP_VAR0.8<1>:uw INPUT_ARG0.8<0,1,0>:uw 2:uw {align1}; shr (1) TEMP_VAR0.16<1>:uw TEMP_VAR0.0<0,1,0>:uw TEMP_VAR0.8<0,1,0>:uw {align1}; and (1) RET_ARG<1>:uw TEMP_VAR0.16<1>:uw PRED_MASK {align1}; end_mb_pred: RETURN {align1}; intel-driver-1.3.0/src/shaders/vme/inter_bframe_haswell.g75a000066400000000000000000000000711231401140700237560ustar00rootroot00000000000000#include "vme75.inc" #include "inter_bframe_haswell.asm" intel-driver-1.3.0/src/shaders/vme/inter_bframe_haswell.g75b000066400000000000000000000542731231401140700237740ustar00rootroot00000000000000 { 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 }, { 0x00000001, 0x24340231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000001, 0x24540231, 0x00000014, 0x00000000 }, { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 }, { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 }, { 0x00000041, 0x24880c21, 0x00000488, 0x00000018 }, { 0x00000001, 0x24940231, 0x00000014, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 }, { 0x04600031, 0x23801cb1, 0x00000800, 0x02190004 }, { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 }, { 0x04600031, 0x23a01cb1, 0x00000800, 0x02290004 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00030003 }, { 0x00000041, 0x24003ca5, 0x00000400, 0x00020002 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 }, { 0x04600031, 0x26001cb1, 0x00000800, 0x02190006 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00030003 }, { 0x00000041, 0x24203ca5, 0x00000420, 0x00020002 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x00070003 }, { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 }, { 0x04600031, 0x26201cb1, 0x00000800, 0x02190006 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a800061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002d28, 0x000000a6, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000ce0 }, { 0x00600001, 0x2ae00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00600060 }, { 0x00210001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x000001f0 }, { 0x00000001, 0x2ae000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24003dad, 0x00000400, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x00000018 }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280303 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00210001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000140 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2ae40021, 0x00450bc8, 0x00000000 }, { 0x00200001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00000001, 0x2fa00021, 0x00000b84, 0x00000000 }, { 0x00000001, 0x2fa40021, 0x00000b80, 0x00000000 }, { 0x00000001, 0x2fa80061, 0x00000000, 0x00000001 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000013e0 }, { 0x00000001, 0x2aa00129, 0x00000fe4, 0x00000000 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00000000 }, { 0x00010001, 0x2af001e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2af401ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000060 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00010001 }, { 0x00010001, 0x2af201e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2af601ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00200001, 0x2af001e9, 0x00000000, 0x00010001 }, { 0x00200001, 0x2af401ed, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00100010 }, { 0x00210001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000660 }, { 0x00000001, 0x2b0000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x00000018 }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280303 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00210001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000140 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2b040021, 0x00450bf0, 0x00000000 }, { 0x00200001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00000001, 0x2fa00021, 0x00000b84, 0x00000000 }, { 0x00000001, 0x2fa40021, 0x00000b80, 0x00000000 }, { 0x00000001, 0x2fa80061, 0x00000000, 0x00000002 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000011a0 }, { 0x00000001, 0x2aa00129, 0x00000fe4, 0x00000000 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00000000 }, { 0x00010001, 0x2b1001e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2b1401ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000060 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00010001 }, { 0x00010001, 0x2b1201e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2b1601ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00200001, 0x2b1001e9, 0x00000000, 0x00010001 }, { 0x00200001, 0x2b1401ed, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00080008 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000210 }, { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff }, { 0x00000040, 0x24003dad, 0x00000400, 0x00010001 }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x00000018 }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280303 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000380 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2b240021, 0x00450bf0, 0x00000000 }, { 0x00200001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00000001, 0x2fa00021, 0x00000b84, 0x00000000 }, { 0x00000001, 0x2fa40021, 0x00000b80, 0x00000000 }, { 0x00000001, 0x2fa80061, 0x00000000, 0x00000002 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000f70 }, { 0x00000001, 0x2aa00129, 0x00000fe4, 0x00000000 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00000000 }, { 0x00010001, 0x2b3001e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2b3401ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000002a0 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00010001 }, { 0x00010001, 0x2b3201e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2b3601ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000260 }, { 0x00200001, 0x2b3001e9, 0x00000000, 0x00010001 }, { 0x00200001, 0x2b3401ed, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000230 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000200 }, { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00200040, 0x24003dad, 0x00450400, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x00000018 }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280303 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000150 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01cb1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2b240021, 0x00450c18, 0x00000000 }, { 0x00200001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00000001, 0x2fa00021, 0x00000b84, 0x00000000 }, { 0x00000001, 0x2fa40021, 0x00000b80, 0x00000000 }, { 0x00000001, 0x2fa80061, 0x00000000, 0x00000003 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000d40 }, { 0x00000001, 0x2aa00129, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2b3201ed, 0x00000000, 0x00010001 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00000000 }, { 0x00010001, 0x2b3001e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2b3401ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000060 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00010001 }, { 0x00010001, 0x2b3201e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2b3601ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00200001, 0x2b3001e9, 0x00000000, 0x00010001 }, { 0x00200001, 0x2b3401ed, 0x00000000, 0x00000000 }, { 0x00000040, 0x240014a5, 0x00000b00, 0x00000b20 }, { 0x01000010, 0x20001ca4, 0x00000400, 0x00000000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x02000010, 0x20001ca4, 0x00000ae0, 0x00000000 }, { 0x00210001, 0x2b040021, 0x00450ae4, 0x00000000 }, { 0x00210001, 0x2b240021, 0x00450ae4, 0x00000000 }, { 0x00210001, 0x2b140129, 0x00450af4, 0x00000000 }, { 0x00210001, 0x2b340129, 0x00450af4, 0x00000000 }, { 0x00210001, 0x2ac00021, 0x00450ae4, 0x00000000 }, { 0x00310001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000320 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200af4, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000ae4, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b14, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b04, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b34, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b24, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200400, 0x00010001 }, { 0x00010001, 0x2ac00021, 0x00000404, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000c0 }, { 0x00000001, 0x2fa001ad, 0x00000ae4, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b04, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b24, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000009b0 }, { 0x00000001, 0x2ac001ad, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2fa001ad, 0x00000ae6, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b06, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b26, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000950 }, { 0x00000001, 0x2ac201ad, 0x00000fe4, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200af6, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000ae8, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b16, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b08, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b36, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b28, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200400, 0x00010001 }, { 0x00010001, 0x2ac40021, 0x00000404, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000c0 }, { 0x00000001, 0x2fa001ad, 0x00000ae8, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b08, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b28, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000820 }, { 0x00000001, 0x2ac401ad, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2fa001ad, 0x00000aea, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b0a, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b2a, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000007c0 }, { 0x00000001, 0x2ac601ad, 0x00000fe4, 0x00000000 }, { 0x0040000c, 0x2a803dad, 0x00690ac0, 0x00020002 }, { 0x00400040, 0x2a883dad, 0x00690a80, 0x00030003 }, { 0x00400005, 0x2a902d29, 0x00690a88, 0xfffcfffc }, { 0x00600001, 0x25600021, 0x008d0020, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00000001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00000005, 0x23840c21, 0x00000384, 0xff000000 }, { 0x00600001, 0x28800021, 0x008d0380, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00800001, 0x28a00231, 0x00cf03a3, 0x00000000 }, { 0x00000001, 0x28b00061, 0x00000000, 0x11111111 }, { 0x00000001, 0x28bc0061, 0x00000000, 0x00010101 }, { 0x00000001, 0x28b40129, 0x00000606, 0x00000000 }, { 0x00400001, 0x28d00021, 0x00690608, 0x00000000 }, { 0x00600001, 0x28c00129, 0x00ae0622, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00010001 }, { 0x00000001, 0x28850231, 0x00000400, 0x00000000 }, { 0x00000001, 0x247c0169, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, { 0x00010001, 0x247c00f1, 0x00000000, 0x00000002 }, { 0x00000001, 0x247d0231, 0x000000a5, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00200020 }, { 0x00000001, 0x247e0231, 0x00000400, 0x00000000 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00800000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x0d600031, 0x21801ca1, 0x00000800, 0x0e782000 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 }, { 0x00000001, 0x28300129, 0x0000018c, 0x00000000 }, { 0x00000001, 0x28340021, 0x00000188, 0x00000000 }, { 0x00000001, 0x28380021, 0x0000019c, 0x00000000 }, { 0x00000001, 0x283c0021, 0x00000488, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00200700 }, { 0x00000001, 0x24560169, 0x00000000, 0x20202020 }, { 0x00000001, 0x24400021, 0x00000448, 0x00000000 }, { 0x00000040, 0x24403dad, 0x00000440, 0xfff8fff8 }, { 0x00000040, 0x24423dad, 0x00000442, 0xfff8fff8 }, { 0x00000001, 0x244001ed, 0x00000000, 0xfff8fff8 }, { 0x00000001, 0x244201ed, 0x00000000, 0xfff8fff8 }, { 0x00000001, 0x24440021, 0x00000440, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00600060 }, { 0x00010040, 0x24403dad, 0x00000440, 0x00040004 }, { 0x00010040, 0x24443dad, 0x00000444, 0x00040004 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00100010 }, { 0x00010040, 0x24423dad, 0x00000442, 0x00040004 }, { 0x00010040, 0x24463dad, 0x00000446, 0x00040004 }, { 0x00200040, 0x244035ad, 0x00450440, 0x00450a90 }, { 0x00200040, 0x244435ad, 0x00450444, 0x00450a94 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00000002 }, { 0x00000001, 0x24640231, 0x0000009c, 0x00000000 }, { 0x00000001, 0x24680061, 0x00000000, 0x00001212 }, { 0x00000001, 0x24700021, 0x00000ac0, 0x00000000 }, { 0x00000001, 0x24740021, 0x00000ac4, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 }, { 0x00000001, 0x28600061, 0x00000000, 0x10010101 }, { 0x00000001, 0x28640061, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28680061, 0x00000000, 0x10010101 }, { 0x00000001, 0x286c0061, 0x00000000, 0x000f0f0f }, { 0x00400001, 0x28700061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28900061, 0x00000000, 0x00000000 }, { 0x08600031, 0x21801ca1, 0x00000800, 0x0a784000 }, { 0x00000001, 0x25740061, 0x00000000, 0x00000000 }, { 0x00000001, 0x25750231, 0x00000199, 0x00000000 }, { 0x00000001, 0x25760231, 0x0000019a, 0x00000000 }, { 0x00000005, 0x24002d29, 0x00000180, 0x00030003 }, { 0x00000001, 0x25740231, 0x00000400, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28a00021, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28c00021, 0x008d0200, 0x00000000 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00203000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00200020 }, { 0x00000001, 0x24660231, 0x00000400, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 }, { 0x0d600031, 0x21801ca1, 0x00000800, 0x0e786000 }, { 0x00000040, 0x24880c21, 0x00000488, 0x00000002 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000198, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000188, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000574, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0003 }, { 0x00000040, 0x24880c21, 0x00000488, 0x00000001 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x0a0a0403 }, { 0x00000040, 0x24880c21, 0x00000488, 0x00000008 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0240, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x0a800031, 0x20001cac, 0x00000b40, 0x0219e003 }, { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca8, 0x00000e00, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x06000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010001, 0x2f6001ad, 0x00000fa0, 0x00000000 }, { 0x00110001, 0x2f6001ad, 0x00000fa4, 0x00000000 }, { 0x06000010, 0x200035ac, 0x00000f60, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000f60, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010001, 0x2f6001ad, 0x00000fa0, 0x00000000 }, { 0x00110001, 0x2f6001ad, 0x00000fa4, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000f60, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000f60, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000070 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa0, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000a0 }, { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa4, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000060 }, { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa4, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa0, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x00600001, 0x2f600061, 0x00000000, 0x00000000 }, { 0x00000001, 0x2f600231, 0x00000fa2, 0x00000000 }, { 0x00000005, 0x2f642d29, 0x00000fa4, 0x00030003 }, { 0x01000010, 0x20002d28, 0x00200f64, 0x00000000 }, { 0x00010005, 0x2fe42d29, 0x00000f60, 0x00030003 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000150 }, { 0x01000010, 0x20002d28, 0x00200f64, 0x00030003 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000100 }, { 0x01000010, 0x20002d28, 0x00200f64, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000070 }, { 0x00000001, 0x2f680129, 0x00000fa8, 0x00000000 }, { 0x01000005, 0x20002d28, 0x00200f68, 0x00010001 }, { 0x00010005, 0x2fe42d29, 0x00000f60, 0x00030003 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000d0 }, { 0x00000008, 0x2f702d29, 0x00000f60, 0x00020002 }, { 0x00000005, 0x2fe42d29, 0x00200f70, 0x00030003 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000a0 }, { 0x00000001, 0x2f680129, 0x00000fa8, 0x00000000 }, { 0x05000010, 0x20002d28, 0x00200f68, 0x00020002 }, { 0x00010005, 0x2fe42d29, 0x00000f60, 0x00030003 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000060 }, { 0x00000008, 0x2f702d29, 0x00000f60, 0x00020002 }, { 0x00000005, 0x2fe42d29, 0x00200f70, 0x00030003 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x00000041, 0x2f682d29, 0x00000fa8, 0x00020002 }, { 0x00000008, 0x2f702529, 0x00000f60, 0x00000f68 }, { 0x00000005, 0x2fe42d29, 0x00200f70, 0x00030003 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, intel-driver-1.3.0/src/shaders/vme/inter_bframe_ivb.asm000066400000000000000000000726501231401140700231300ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * Authors: Zhao Yakui * */ // Modual name: InterFrame_ivy.asm // // Make intra predition estimation for Inter-B frame // // // Now, begin source code.... // #define SAVE_RET add (1) RETURN_REG<1>:ud ip:ud 32:ud #define RETURN mov (1) ip:ud RETURN_REG<0,1,0>:ud /* * __START */ __INTER_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ; shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1}; mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1}; mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* * Media Read Message -- fetch Luma neighbor edge pixels */ /* ROW */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1}; mov (8) mb_mvp_ref.0<1>:ud 0:ud {align1}; mov (8) mb_ref_win.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1}; (f0.0) jmpi (1) __mb_hwdep_end; /* read back the data for MB A */ /* the layout of MB result is: rx.0(Available). rx.4(MVa), rX.8(MVb), rX.16(Pred_L0 flag), * rX.18 (Pred_L1 flag), rX.20(Forward reference ID), rX.22(Backwared reference ID) */ mov (8) mba_result.0<1>:ud 0x0:ud {align1}; mov (8) mbb_result.0<1>:ud 0x0:ud {align1}; mov (8) mbc_result.0<1>:ud 0x0:ud {align1}; mba_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; /* MB A doesn't exist. Zero MV. mba_flag is zero and ref ID = -1 */ (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; mov (1) mba_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) mb_msg_tmp.8<1>:ud mb_msg0.8<0,1,0>:ud {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; /* bind index 3, read 1 oword (16bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_0, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ and.z.f0.0 (1) null<1>:ud mb_mode_wb.0 <0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (-f0.0) jmpi (1) mbb_start; mov (1) mb_msg0.8<1>:UD mb_msg_tmp.8<0,1,0>:ud {align1}; /* Read MV for MB A */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* MV */ mov (2) mba_result.4<1>:ud mb_mv1.8<2,2,1>:ud {align1}; mov (2) mba_result.20<1>:w -1:w {align1}; mov (1) INPUT_ARG0.0<1>:ud mb_mode_wb.4<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.4<1>:ud mb_mode_wb.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud INTER_BLOCK1:ud {align1}; SAVE_RET {align1}; jmpi (1) mb_pred_func; mov (1) mb_pred_mode.0<1>:uw RET_ARG<0,1,0>:uw {align1}; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L0 {align1}; (f0.0) mov (1) mba_result.16<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mba_result.20<1>:w 0:w {align1}; (f0.0) jmpi (1) mbb_start; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L1 {align1}; (f0.0) mov (1) mba_result.18<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mba_result.22<1>:w 0:w {align1}; (f0.0) jmpi (1) mbb_start; mov (2) mba_result.16<1>:uw MB_PRED_FLAG {align1}; mov (2) mba_result.20<1>:w 0:w {align1}; mbb_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; /* MB B doesn't exist. Zero MV. mba_flag is zero */ /* If MB B doesn't exist, neither MB C nor D exists */ (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbb_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) mb_msg_tmp.8<1>:ud mb_msg0.8<0,1,0>:ud {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_0, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ and.z.f0.0 (1) null<1>:ud mb_mode_wb.0 <0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (-f0.0) jmpi (1) mbc_start; mov (1) mb_msg0.8<1>:UD mb_msg_tmp.8<0,1,0>:ud {align1}; /* Read MV for MB B */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ mov (2) mbb_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1}; mov (2) mbb_result.20<1>:w -1:w {align1}; mov (1) INPUT_ARG0.0<1>:ud mb_mode_wb.4<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.4<1>:ud mb_mode_wb.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud INTER_BLOCK2:ud {align1}; SAVE_RET {align1}; jmpi (1) mb_pred_func; mov (1) mb_pred_mode.0<1>:uw RET_ARG<0,1,0>:uw {align1}; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L0 {align1}; (f0.0) mov (1) mbb_result.16<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbb_result.20<1>:w 0:w {align1}; (f0.0) jmpi (1) mbc_start; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L1 {align1}; (f0.0) mov (1) mbb_result.18<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbb_result.22<1>:w 0:w {align1}; (f0.0) jmpi (1) mbc_start; mov (2) mbb_result.16<1>:uw MB_PRED_FLAG {align1}; mbc_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_C:uw {align1}; /* MB C doesn't exist. Zero MV. mba_flag is zero */ /* Based on h264 spec the MB D will be replaced if MB C doesn't exist */ (f0.0) jmpi (1) mbd_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) mb_msg_tmp.8<1>:ud mb_msg0.8<0,1,0>:ud {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_0, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ and.z.f0.0 (1) null<1>:ud mb_mode_wb.0 <0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (-f0.0) jmpi (1) mb_mvp_start; mov (1) mb_msg0.8<1>:UD mb_msg_tmp.8<0,1,0>:ud {align1}; /* Read MV for MB C */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1}; mov (2) mbc_result.20<1>:w -1:w {align1}; mov (1) INPUT_ARG0.0<1>:ud mb_mode_wb.4<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.4<1>:ud mb_mode_wb.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud INTER_BLOCK2:ud {align1}; SAVE_RET {align1}; jmpi (1) mb_pred_func; mov (1) mb_pred_mode.0<1>:uw RET_ARG<0,1,0>:uw {align1}; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L0 {align1}; (f0.0) mov (1) mbc_result.16<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbc_result.20<1>:w 0:w {align1}; (f0.0) jmpi (1) mb_mvp_start; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L1 {align1}; (f0.0) mov (1) mbc_result.18<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbc_result.22<1>:w 0:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (2) mbc_result.16<1>:uw MB_PRED_FLAG {align1}; mov (2) mbc_result.20<1>:w 0:w {align1}; jmpi (1) mb_mvp_start; mbd_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_D:uw {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (2) tmp_reg0.0<1>:w tmp_reg0.0<2,2,1>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) mb_msg_tmp.8<1>:ud mb_msg0.8<0,1,0>:ud {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_0, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; and.z.f0.0 (1) null<1>:ud mb_mode_wb.0 <0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (-f0.0) jmpi (1) mb_mvp_start; mov (1) mb_msg0.8<1>:UD mb_msg_tmp.8<0,1,0>:ud {align1}; /* Read MV for MB D */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ub NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv3.24<2,2,1>:ud {align1}; mov (2) mbc_result.20<1>:w -1:w {align1}; mov (1) INPUT_ARG0.0<1>:ud mb_mode_wb.4<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.4<1>:ud mb_mode_wb.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud INTER_BLOCK3:ud {align1}; SAVE_RET {align1}; jmpi (1) mb_pred_func; mov (1) mb_pred_mode.0<1>:uw RET_ARG<0,1,0>:uw {align1}; mov (1) mbc_result.18<1>:w MB_PRED_FLAG {align1}; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L0 {align1}; (f0.0) mov (1) mbc_result.16<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbc_result.20<1>:w 0:w {align1}; (f0.0) jmpi (1) mb_mvp_start; cmp.e.f0.0 (1) null:uw mb_pred_mode.0<0,1,0>:uw PRED_L1 {align1}; (f0.0) mov (1) mbc_result.18<1>:uw MB_PRED_FLAG {align1}; (f0.0) mov (1) mbc_result.22<1>:w 0:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (2) mbc_result.16<1>:uw MB_PRED_FLAG {align1}; mov (2) mbc_result.20<1>:w 0:w {align1}; mb_mvp_start: /*TODO: Add the skip prediction */ /* Check whether both MB B and C are invailable */ add (1) tmp_reg0.0<1>:d mbb_result.0<0,1,0>:d mbc_result.0<0,1,0>:d {align1}; cmp.z.f0.0 (1) null:d tmp_reg0.0<0,1,0>:d 0:d {align1}; (-f0.0) jmpi (1) mb_median_start; cmp.nz.f0.0 (1) null:d mba_result.0<0,1,0>:d 0:d {align1}; (f0.0) mov (2) mbb_result.4<1>:ud mba_result.4<2,2,1>:ud {align1}; (f0.0) mov (2) mbc_result.4<1>:ud mba_result.4<2,2,1>:ud {align1}; (f0.0) mov (2) mbb_result.20<1>:uw mba_result.20<2,2,1>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:uw mba_result.20<2,2,1>:uw {align1}; (f0.0) mov (2) mb_mvp_ref.0<1>:ud mba_result.4<2,2,1>:ud {align1}; (-f0.0) mov (2) mb_mvp_ref.0<1>:ud 0:ud {align1}; jmpi (1) __mb_hwdep_end; mb_median_start: /* forward_MVP */ /* check whether only one neighbour MB has the same ref ID with the current MB */ mov (8) tmp_reg0.0<1>:ud 0:ud {align1}; cmp.z.f0.0 (1) null:d mba_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbb_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbc_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.4<0,1,0>:ud {align1}; cmp.e.f0.0 (1) null:d tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud tmp_reg0.4<0,1,0>:ud {align1}; (f0.0) jmpi (1) mvp_backward; mov (1) INPUT_ARG0.0<1>:w mba_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.4<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.0<1>:w RET_ARG<0,1,0>:w {align1}; mov (1) INPUT_ARG0.0<1>:w mba_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.6<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.2<1>:w RET_ARG<0,1,0>:w {align1}; mvp_backward: /* check whether only one neighbour MB has the same ref ID with the current MB */ mov (8) tmp_reg0.0<1>:ud 0:ud {align1}; cmp.z.f0.0 (1) null:d mba_result.22<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.8<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbb_result.22<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.8<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbc_result.22<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.8<0,1,0>:ud {align1}; cmp.e.f0.0 (1) null:d tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) mb_mvp_ref.4<1>:ud tmp_reg0.4<0,1,0>:ud {align1}; (f0.0) jmpi (1) __mb_hwdep_end; mov (1) INPUT_ARG0.0<1>:w mba_result.8<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.8<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.8<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.4<1>:w RET_ARG<0,1,0>:w {align1}; mov (1) INPUT_ARG0.0<1>:w mba_result.10<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.10<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.10<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.6<1>:w RET_ARG<0,1,0>:w {align1}; __mb_hwdep_end: asr (4) mb_ref_win.0<1>:w mb_mvp_ref.0<4,4,1>:w 2:w {align1}; add (4) mb_ref_win.8<1>:w mb_ref_win.0<4,4,1>:w 3:w {align1}; and (4) mb_ref_win.16<1>:uw mb_ref_win.8<4,4,1>:uw 0xFFFC:uw {align1}; /* m2 */ mov (8) vme_msg_2<1>:UD 0x0:UD {align1}; /* m3 */ mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1}; and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1}; mov (8) vme_msg_3<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; /* m4 */ mov (8) vme_msg_4<1>:UD 0x0 {align1}; mov (16) vme_msg_4.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1}; mov (1) vme_msg_4.16<1>:UD INTRA_PREDICTORE_MODE {align1}; /* m1 */ mov (8) vme_m1.0<1>:ud 0x0:ud {align1}; and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1}; (f0.0) mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE:uw {align1}; /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; /* M0 */ /* IME search */ mov (1) vme_m0.12<1>:UD SEARCH_CTRL_DUAL_REFERENCE + INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER:UD {align1}; /* 16x16 Source, 1/4 pixel, harr */ mov (1) vme_m0.22<1>:UW DREF_REGION_SIZE {align1}; /* Reference Width&Height, 48x40 */ mov (1) vme_m0.0<1>:UD vme_m0.8<0,1,0>:UD {align1}; mov (1) vme_m0.0<1>:W -8:W {align1}; mov (1) vme_m0.2<1>:W -8:W {align1}; mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; (f0.0) add (1) vme_m0.0<1>:w vme_m0.0<0,1,0>:w 4:w {align1}; (f0.0) add (1) vme_m0.4<1>:w vme_m0.4<0,1,0>:w 4:w {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; (f0.0) add (1) vme_m0.2<1>:w vme_m0.2<0,1,0>:w 4:w {align1}; (f0.0) add (1) vme_m0.6<1>:w vme_m0.6<0,1,0>:w 4:w {align1}; mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; add (2) vme_m0.0<1>:w vme_m0.0<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; add (2) vme_m0.4<1>:w vme_m0.4<2,2,1>:w mb_ref_win.20<2,2,1>:w {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; /* m1 */ mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; /* MV num is passed by constant buffer. R4.28 */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; add (1) vme_m1.4<1>:UD vme_m1.4<0,1,0>:UD FB_PRUNING_ENABLE:UD {align1}; add (1) vme_m1.6<1>:uw vme_m1.6<0,1,0>:uw BI_WEIGHT {align1}; mov (1) vme_m1.8<1>:UD DSTART_CENTER + DSEARCH_PATH_LEN:UD {align1}; /* Set the MV cost center */ mov (1) vme_m1.16<1>:ud mb_mvp_ref.0<0,1,0>:ud {align1}; mov (1) vme_m1.20<1>:ud mb_mvp_ref.4<0,1,0>:ud {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; send (8) vme_msg_ind vme_wb null vme( BIND_IDX_VME, 0, 0, VME_MESSAGE_TYPE_MIXED ) mlen vme_msg_length rlen vme_inter_wb_length {align1}; and.z.f0.0 (1) null<1>:ud vme_wb0.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0)jmpi (1) __INTRA_INFO ; __INTER_INFO: /* Write MV pairs */ mov (8) msg_reg0.0<1>:UD obw_m0.0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) msg_reg2.0<1>:UD vme_wb2.0<8,8,1>:UD {align1}; mov (8) msg_reg3.0<1>:UD vme_wb3.0<8,8,1>:UD {align1}; mov (8) msg_reg4.0<1>:UD vme_wb4.0<8,8,1>:UD {align1}; /* bind index 3, write 8 oword (128 bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_8, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 5 rlen obw_wb_length {align1}; mov (1) tmp_uw1<1>:uw 0:uw {align1} ; mov (1) tmp_ud1<1>:ud 0:ud {align1} ; and (1) tmp_uw1<1>:uw vme_wb0.2<0,1,0>:uw MV32_BIT_MASK:uw {align1} ; shr (1) tmp_uw1<1>:uw tmp_uw1<1>:uw MV32_BIT_SHIFT:uw {align1} ; mul (1) tmp_ud1<1>:ud tmp_uw1<0,1,0>:uw 96:uw {align1} ; add (1) tmp_ud1<1>:ud tmp_ud1<0,1,0>:ud 32:uw {align1} ; shl (1) tmp_uw1<1>:uw tmp_uw1<0,1,0>:uw MFC_MV32_BIT_SHIFT:uw {align1} ; add (1) tmp_uw1<1>:uw tmp_uw1<0,1,0>:uw MVSIZE_UW_BASE:uw {align1} ; add (1) tmp_uw1<1>:uw tmp_uw1<0,1,0>:uw CBP_DC_YUV_UW:uw {align1} ; mov (1) msg_reg1.0<1>:uw vme_wb0.0<0,1,0>:uw {align1} ; mov (1) msg_reg1.2<1>:uw tmp_uw1<0,1,0>:uw {align1} ; mov (1) msg_reg1.4<1>:UD vme_wb0.28<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:ud tmp_ud1<0,1,0>:ud {align1} ; mov (1) msg_reg1.12<1>:ud vme_wb0.0<0,1,0>:ud {align1} ; mov (1) msg_reg1.16<1>:ud 0x25:ud {align1} ; jmpi (1) __OUTPUT_INFO; __INTRA_INFO: mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; mov (1) msg_reg1.16<1>:ud 0x35:ud {align1} ; __OUTPUT_INFO: mov (1) msg_reg1.20<1>:ud obw_m0.8<0,1,0>:ud {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; mov (8) msg_reg0.0<1>:ud obw_m0.0<8,8,1>:ud {align1}; /* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; NOP; /* Issue message fence so that the previous write message is committed */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_FENCE, OBR_MF_COMMIT, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; nop ; nop ; /* Compare three word data to get the min value */ word_imin: cmp.le.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; cmp.le.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; RETURN {align1}; /* Compare three word data to get the max value */ word_imax: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; cmp.ge.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; RETURN {align1}; word_imedian: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_a_ge_b; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; jmpi (1) cmp_end; cmp_a_ge_b: cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; cmp_end: RETURN {align1}; /* This is to get the prediction mode for the correspongding partions/sub-mb * Parameter description: ARG0.0: INTER_SHAPE/PRED_MODE ARG0.4: INTER_MODE(16x16, 16x8, 8x16 or 8X8) ARG0.8: sub-mb block number(block 0/1/2/3) */ mb_pred_func: mov (8) TEMP_VAR0.0<1>:ud 0:ud {align1}; mov (1) TEMP_VAR0.0<1>:ub INPUT_ARG0.1<0,1,0>:ub {align1}; and (1) TEMP_VAR0.4<1>:uw INPUT_ARG0.4<0,1,0>:uw INTER_MASK:uw {align1}; /* INTER16x16 mode. The bit1-0 is the prediction mode */ cmp.e.f0.0 (1) null:uw TEMP_VAR0.4<1>:uw INTER_16X16MODE:uw {align1}; (f0.0) and (1) RET_ARG<1>:uw TEMP_VAR0.0<0,1,0>:uw PRED_MASK {align1}; (f0.0) jmpi (1) end_mb_pred; /* Check whether it is INTER8x8 mode. */ cmp.e.f0.0 (1) null:uw TEMP_VAR0.4<1>:uw INTER_8X8MODE:uw {align1}; (f0.0) jmpi (1) mb_pred_func_8; /* Check whether it is INTER16x8 mode. */ cmp.e.f0.0 (1) null:uw TEMP_VAR0.4<1>:uw INTER_16X8MODE:uw {align1}; (f0.0) jmpi (1) mb_pred_func_168; mb_pred_func_816: /* Block 0/2 uses the bit1-0. Block 1/3 uses the bit3-2 */ mov (1) TEMP_VAR0.8<1>:uw INPUT_ARG0.8<0,1,0>:uw {align1}; and.z.f0.0 (1) null:uw TEMP_VAR0.8<1>:uw INTER_BLOCK1:uw {align1}; (f0.0) and (1) RET_ARG<1>:uw TEMP_VAR0.0<0,1,0>:uw PRED_MASK {align1}; (f0.0) jmpi (1) end_mb_pred; shr (1) TEMP_VAR0.16<1>:uw TEMP_VAR0.0<0,1,0>:uw 2:uw {align1}; and (1) RET_ARG<1>:uw TEMP_VAR0.16<1>:uw PRED_MASK {align1}; jmpi (1) end_mb_pred; mb_pred_func_168: /* Block 0/1 uses the bit1-0. Block 2/3 uses the bit3-2 */ mov (1) TEMP_VAR0.8<1>:uw INPUT_ARG0.8<0,1,0>:uw {align1}; cmp.l.f0.0 (1) null:uw TEMP_VAR0.8<1>:uw INTER_BLOCK2:uw {align1}; (f0.0) and (1) RET_ARG<1>:uw TEMP_VAR0.0<0,1,0>:uw PRED_MASK {align1}; (f0.0) jmpi (1) end_mb_pred; shr (1) TEMP_VAR0.16<1>:uw TEMP_VAR0.0<0,1,0>:uw 2:uw {align1}; and (1) RET_ARG<1>:uw TEMP_VAR0.16<1>:uw PRED_MASK {align1}; jmpi (1) end_mb_pred; mb_pred_func_8: /* 8X8 mode. Every block uses two bits as the prediction mode. */ mul (1) TEMP_VAR0.8<1>:uw INPUT_ARG0.8<0,1,0>:uw 2:uw {align1}; shr (1) TEMP_VAR0.16<1>:uw TEMP_VAR0.0<0,1,0>:uw TEMP_VAR0.8<0,1,0>:uw {align1}; and (1) RET_ARG<1>:uw TEMP_VAR0.16<1>:uw PRED_MASK {align1}; end_mb_pred: RETURN {align1}; intel-driver-1.3.0/src/shaders/vme/inter_bframe_ivb.g7a000066400000000000000000000000641231401140700230140ustar00rootroot00000000000000#include "vme7.inc" #include "inter_bframe_ivb.asm" intel-driver-1.3.0/src/shaders/vme/inter_bframe_ivb.g7b000066400000000000000000000503101231401140700230140ustar00rootroot00000000000000 { 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 }, { 0x00000001, 0x24340231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000001, 0x24540231, 0x00000014, 0x00000000 }, { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 }, { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 }, { 0x00000041, 0x24880c21, 0x00000488, 0x0000000a }, { 0x00000001, 0x24940231, 0x00000014, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 }, { 0x04600031, 0x23801cb1, 0x00000800, 0x02190004 }, { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 }, { 0x04600031, 0x23a01cb1, 0x00000800, 0x02290004 }, { 0x00600001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a800061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002d28, 0x000000a6, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000001aa }, { 0x00600001, 0x2ae00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00600060 }, { 0x00210001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000042 }, { 0x00000001, 0x2ae000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24003dad, 0x00000400, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 }, { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 }, { 0x00310001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000028 }, { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2ae40021, 0x00450bc8, 0x00000000 }, { 0x00200001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00000001, 0x2fa00021, 0x00000b84, 0x00000000 }, { 0x00000001, 0x2fa40021, 0x00000b80, 0x00000000 }, { 0x00000001, 0x2fa80061, 0x00000000, 0x00000001 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000248 }, { 0x00000001, 0x2aa00129, 0x00000fe4, 0x00000000 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00000000 }, { 0x00010001, 0x2af001e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2af401ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00010001 }, { 0x00010001, 0x2af201e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2af601ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000004 }, { 0x00200001, 0x2af001e9, 0x00000000, 0x00010001 }, { 0x00200001, 0x2af401ed, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00100010 }, { 0x00210001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000d6 }, { 0x00000001, 0x2b0000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 }, { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 }, { 0x00310001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2b040021, 0x00450bf0, 0x00000000 }, { 0x00200001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00000001, 0x2fa00021, 0x00000b84, 0x00000000 }, { 0x00000001, 0x2fa40021, 0x00000b80, 0x00000000 }, { 0x00000001, 0x2fa80061, 0x00000000, 0x00000002 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000001fc }, { 0x00000001, 0x2aa00129, 0x00000fe4, 0x00000000 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00000000 }, { 0x00010001, 0x2b1001e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2b1401ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00010001 }, { 0x00010001, 0x2b1201e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2b1601ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00200001, 0x2b1001e9, 0x00000000, 0x00010001 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00080008 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000046 }, { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff }, { 0x00000040, 0x24003dad, 0x00000400, 0x00010001 }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 }, { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 }, { 0x00310001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000074 }, { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2b240021, 0x00450bf0, 0x00000000 }, { 0x00200001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00000001, 0x2fa00021, 0x00000b84, 0x00000000 }, { 0x00000001, 0x2fa40021, 0x00000b80, 0x00000000 }, { 0x00000001, 0x2fa80061, 0x00000000, 0x00000002 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000001b4 }, { 0x00000001, 0x2aa00129, 0x00000fe4, 0x00000000 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00000000 }, { 0x00010001, 0x2b3001e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2b3401ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000058 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00010001 }, { 0x00010001, 0x2b3201e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2b3601ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000050 }, { 0x00200001, 0x2b3001e9, 0x00000000, 0x00010001 }, { 0x00200001, 0x2b3401ed, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004a }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000044 }, { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00200040, 0x24003dad, 0x00450400, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 }, { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 }, { 0x00310001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0x0000002a }, { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 }, { 0x0a800031, 0x2ba01cb1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2b240021, 0x00450c18, 0x00000000 }, { 0x00200001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00000001, 0x2fa00021, 0x00000b84, 0x00000000 }, { 0x00000001, 0x2fa40021, 0x00000b80, 0x00000000 }, { 0x00000001, 0x2fa80061, 0x00000000, 0x00000003 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000016a }, { 0x00000001, 0x2aa00129, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2b3201ed, 0x00000000, 0x00010001 }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00000000 }, { 0x00010001, 0x2b3001e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2b3401ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x01000010, 0x20002d28, 0x00000aa0, 0x00010001 }, { 0x00010001, 0x2b3201e9, 0x00000000, 0x00010001 }, { 0x00010001, 0x2b3601ed, 0x00000000, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000004 }, { 0x00200001, 0x2b3001e9, 0x00000000, 0x00010001 }, { 0x00200001, 0x2b3401ed, 0x00000000, 0x00000000 }, { 0x00000040, 0x240014a5, 0x00000b00, 0x00000b20 }, { 0x01000010, 0x20001ca4, 0x00000400, 0x00000000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x02000010, 0x20001ca4, 0x00000ae0, 0x00000000 }, { 0x00210001, 0x2b040021, 0x00450ae4, 0x00000000 }, { 0x00210001, 0x2b240021, 0x00450ae4, 0x00000000 }, { 0x00210001, 0x2b140129, 0x00450af4, 0x00000000 }, { 0x00210001, 0x2b340129, 0x00450af4, 0x00000000 }, { 0x00210001, 0x2ac00021, 0x00450ae4, 0x00000000 }, { 0x00310001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000064 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200af4, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000ae4, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b14, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b04, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b34, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b24, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200400, 0x00010001 }, { 0x00010001, 0x2ac00021, 0x00000404, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x2fa001ad, 0x00000ae4, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b04, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b24, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000f8 }, { 0x00000001, 0x2ac001ad, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2fa001ad, 0x00000ae6, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b06, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b26, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000ec }, { 0x00000001, 0x2ac201ad, 0x00000fe4, 0x00000000 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200af6, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000ae8, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b16, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b08, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b36, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b28, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200400, 0x00010001 }, { 0x00010001, 0x2ac40021, 0x00000404, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x2fa001ad, 0x00000ae8, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b08, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b28, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000c6 }, { 0x00000001, 0x2ac401ad, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2fa001ad, 0x00000aea, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b0a, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b2a, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000ba }, { 0x00000001, 0x2ac601ad, 0x00000fe4, 0x00000000 }, { 0x0040000c, 0x2a803dad, 0x00690ac0, 0x00020002 }, { 0x00400040, 0x2a883dad, 0x00690a80, 0x00030003 }, { 0x00400005, 0x2a902d29, 0x00690a88, 0xfffcfffc }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00000005, 0x23840c21, 0x00000384, 0xff000000 }, { 0x00600001, 0x28600021, 0x008d0380, 0x00000000 }, { 0x00600001, 0x288000e1, 0x00000000, 0x00000000 }, { 0x00800001, 0x28800231, 0x00cf03a3, 0x00000000 }, { 0x00000001, 0x28900061, 0x00000000, 0x11111111 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, { 0x00010001, 0x247c0171, 0x00000000, 0x00020002 }, { 0x00000001, 0x247d0231, 0x000000a5, 0x00000000 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00203700 }, { 0x00000001, 0x24560169, 0x00000000, 0x20202020 }, { 0x00000001, 0x24400021, 0x00000448, 0x00000000 }, { 0x00000001, 0x244001ed, 0x00000000, 0xfff8fff8 }, { 0x00000001, 0x244201ed, 0x00000000, 0xfff8fff8 }, { 0x00000001, 0x24440021, 0x00000440, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00600060 }, { 0x00010040, 0x24403dad, 0x00000440, 0x00040004 }, { 0x00010040, 0x24443dad, 0x00000444, 0x00040004 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00100010 }, { 0x00010040, 0x24423dad, 0x00000442, 0x00040004 }, { 0x00010040, 0x24463dad, 0x00000446, 0x00040004 }, { 0x00000001, 0x24440021, 0x00000440, 0x00000000 }, { 0x00200040, 0x244035ad, 0x00450440, 0x00450a90 }, { 0x00200040, 0x244435ad, 0x00450444, 0x00450a94 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00000002 }, { 0x00000001, 0x24640231, 0x0000009c, 0x00000000 }, { 0x00000040, 0x24640c21, 0x00000464, 0x40000000 }, { 0x00000040, 0x24662d29, 0x00000466, 0x00200020 }, { 0x00000001, 0x24680061, 0x00000000, 0x00001212 }, { 0x00000001, 0x24700021, 0x00000ac0, 0x00000000 }, { 0x00000001, 0x24740021, 0x00000ac4, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x08600031, 0x21801cbd, 0x00000800, 0x0a686000 }, { 0x01000005, 0x20000c20, 0x00000180, 0x00002000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x0a0a0403 }, { 0x00000001, 0x25420169, 0x00000000, 0x00000000 }, { 0x00000001, 0x25440061, 0x00000000, 0x00000000 }, { 0x00000005, 0x25422d29, 0x00000182, 0x00200020 }, { 0x00000008, 0x25422d29, 0x00200542, 0x00050005 }, { 0x00000041, 0x25442d21, 0x00000542, 0x00600060 }, { 0x00000040, 0x25442c21, 0x00000544, 0x00200020 }, { 0x00000009, 0x25422d29, 0x00000542, 0x00050005 }, { 0x00000040, 0x25422d29, 0x00000542, 0x00400040 }, { 0x00000040, 0x25422d29, 0x00000542, 0x000e000e }, { 0x00000001, 0x28200129, 0x00000180, 0x00000000 }, { 0x00000001, 0x28220129, 0x00000542, 0x00000000 }, { 0x00000001, 0x28240021, 0x0000019c, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000544, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28300061, 0x00000000, 0x00000025 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 }, { 0x00000001, 0x28300061, 0x00000000, 0x00000035 }, { 0x00000001, 0x28340021, 0x00000488, 0x00000000 }, { 0x00000040, 0x24880c21, 0x00000488, 0x00000008 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x0219e003 }, { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca8, 0x00000e00, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x06000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010001, 0x2f6001ad, 0x00000fa0, 0x00000000 }, { 0x00110001, 0x2f6001ad, 0x00000fa4, 0x00000000 }, { 0x06000010, 0x200035ac, 0x00000f60, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000f60, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010001, 0x2f6001ad, 0x00000fa0, 0x00000000 }, { 0x00110001, 0x2f6001ad, 0x00000fa4, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000f60, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000f60, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000e }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa0, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa4, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa4, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa0, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x00600001, 0x2f600061, 0x00000000, 0x00000000 }, { 0x00000001, 0x2f600231, 0x00000fa1, 0x00000000 }, { 0x00000005, 0x2f642d29, 0x00000fa4, 0x00030003 }, { 0x01000010, 0x20002d28, 0x00200f64, 0x00000000 }, { 0x00010005, 0x2fe42d29, 0x00000f60, 0x00030003 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000002a }, { 0x01000010, 0x20002d28, 0x00200f64, 0x00030003 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x01000010, 0x20002d28, 0x00200f64, 0x00010001 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000e }, { 0x00000001, 0x2f680129, 0x00000fa8, 0x00000000 }, { 0x01000005, 0x20002d28, 0x00200f68, 0x00010001 }, { 0x00010005, 0x2fe42d29, 0x00000f60, 0x00030003 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000001a }, { 0x00000008, 0x2f702d29, 0x00000f60, 0x00020002 }, { 0x00000005, 0x2fe42d29, 0x00200f70, 0x00030003 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x00000001, 0x2f680129, 0x00000fa8, 0x00000000 }, { 0x05000010, 0x20002d28, 0x00200f68, 0x00020002 }, { 0x00010005, 0x2fe42d29, 0x00000f60, 0x00030003 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x00000008, 0x2f702d29, 0x00000f60, 0x00020002 }, { 0x00000005, 0x2fe42d29, 0x00200f70, 0x00030003 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x00000041, 0x2f682d29, 0x00000fa8, 0x00020002 }, { 0x00000008, 0x2f702529, 0x00000f60, 0x00000f68 }, { 0x00000005, 0x2fe42d29, 0x00200f70, 0x00030003 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, intel-driver-1.3.0/src/shaders/vme/inter_frame.asm000066400000000000000000000276101231401140700221220ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: IntraFrame.asm // // Make intra predition estimation for Intra frame // // // Now, begin source code.... // /* * __START */ __INTER_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg3.0<1>:UD 0x0:UD {align1}; shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1}; mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1}; mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* Source = (x, y) * 16 */ #ifdef DEV_SNB shl (2) vme_m0.0<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; add (1) vme_m0.0<1>:W vme_m0.0<0,1,0>:W -16:W {align1}; /* Reference = (x-16,y-12)-(x+32,y+24) */ add (1) vme_m0.2<1>:W vme_m0.2<0,1,0>:W -12:W {align1}; #else mov (1) vme_m0.0<1>:W -16:W {align1} ; /* Reference = (x-16,y-12)-(x+32,y+24) */ mov (1) vme_m0.2<1>:W -12:W {align1} ; #endif mov (1) vme_m0.12<1>:UD SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER:UD {align1}; /* 16x16 Source, 1/4 pixel, harr */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) vme_m0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 32x32 */ mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; mov (1) vme_m1.4<1>:UD FB_PRUNING_ENABLE:UD {align1}; /* MV num is passed by constant buffer. R4.28 */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; mov (1) vme_m1.8<1>:UD START_CENTER + SEARCH_PATH_LEN:UD {align1}; mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ __VME_LOOP: /* * Media Read Message -- fetch neighbor edge pixels */ /* ROW */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1}; /* * VME message */ /* m0 */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; /* m1 */ mov (1) intra_flag<1>:UW 0x0:UW {align1} ; and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1}; (f0.0) mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE {align1}; cmp.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB 0:UW {align1}; /* X != 0 */ (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_AE {align1}; /* A */ cmp.nz.f0.0 (1) null<1>:UW orig_y_ub<0,1,0>:UB 0:UW {align1}; /* Y != 0 */ (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_B {align1}; /* B */ mul.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB orig_y_ub<0,1,0>:UB {align1}; /* X * Y != 0 */ (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_D {align1}; /* D */ add (1) tmp_x_w<1>:W orig_x_ub<0,1,0>:UB 1:UW {align1}; /* X + 1 */ add (1) tmp_x_w<1>:W w_in_mb_uw<0,1,0>:UW -tmp_x_w<0,1,0>:W {align1}; /* width - (X + 1) */ mul.nz.f0.0 (1) null<1>:UD tmp_x_w<0,1,0>:W orig_y_ub<0,1,0>:UB {align1}; /* (width - (X + 1)) * Y != 0 */ (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_C {align1}; /* C */ and.nz.f0.0 (1) null<1>:UW slice_edge_ub<0,1,0>:UB 2:UW {align1}; (f0.0) and (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB 0xE0 {align1}; /* slice edge disable B,C,D*/ mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* m2 */ mov (8) vme_msg_2<1>:UD 0x0:UD {align1}; /* m3 */ mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1}; and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1}; mov (8) vme_msg_3<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; /* m4 */ mov (8) vme_msg_4<1>:UD 0x0 {align1}; mov (16) vme_msg_4.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1}; mov (1) vme_msg_4.16<1>:UD INTRA_PREDICTORE_MODE {align1}; send (8) vme_msg_ind vme_wb null vme( BIND_IDX_VME, 0, 0, VME_MESSAGE_TYPE_MIXED ) mlen vme_msg_length rlen vme_inter_wb_length {align1}; /* * Oword Block Write message */ /* MV pairs */ mov (8) msg_reg0.0<1>:UD obw_m0.0<8,8,1>:UD {align1}; #ifdef DEV_SNB mov (16) obw_m1.0<1>:UW vme_wb1.0<16,16,1>:UB {align1}; add (8) obw_m1.0<2>:W obw_m1.0<16,8,2>:W -64:W {align1}; add (8) obw_m1.2<2>:W obw_m1.2<16,8,2>:W -48:W {align1}; mov (16) obw_m2.0<1>:UW vme_wb1.16<16,16,1>:UB {align1}; add (8) obw_m2.0<2>:W obw_m2.0<16,8,2>:W -64:W {align1}; add (8) obw_m2.2<2>:W obw_m2.2<16,8,2>:W -48:W {align1}; mov (16) obw_m3.0<1>:UW vme_wb2.0<16,16,1>:UB {align1}; add (8) obw_m3.0<2>:W obw_m3.0<16,8,2>:W -64:W {align1}; add (8) obw_m3.2<2>:W obw_m3.2<16,8,2>:W -48:W {align1}; mov (16) obw_m4.0<1>:UW vme_wb2.16<16,16,1>:UB {align1}; add (8) obw_m4.0<2>:W obw_m4.0<16,8,2>:W -64:W {align1}; add (8) obw_m4.2<2>:W obw_m4.2<16,8,2>:W -48:W {align1}; #else mov (8) obw_m1.0<1>:ud vme_wb1.0<8,8,1>:ud {align1}; mov (8) obw_m2.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) obw_m3.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) obw_m4.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; #endif mov (8) msg_reg1.0<1>:UD obw_m1.0<8,8,1>:UD {align1}; mov (8) msg_reg2.0<1>:UD obw_m2.0<8,8,1>:UD {align1}; mov (8) msg_reg3.0<1>:UD obw_m3.0<8,8,1>:UD {align1}; mov (8) msg_reg4.0<1>:UD obw_m4.0<8,8,1>:UD {align1}; /* bind index 3, write 8 oword, msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_4, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 5 rlen obw_wb_length {align1}; /* other info */ add (1) msg_reg0.8<1>:UD obw_m0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1} ; and.z.f0.0 (1) null<1>:ud vme_wb0.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0)jmpi (1) __INTRA_INFO ; __INTER_INFO: mov (1) tmp_uw1<1>:uw 0:uw {align1} ; mov (1) tmp_ud1<1>:ud 0:ud {align1} ; (f0.0)and (1) tmp_uw1<1>:uw vme_wb0.2<0,1,0>:uw MV32_BIT_MASK:uw {align1} ; (f0.0)shr (1) tmp_uw1<1>:uw tmp_uw1<1>:uw MV32_BIT_SHIFT:uw {align1} ; (f0.0)mul (1) tmp_ud1<1>:ud tmp_uw1<0,1,0>:uw 96:uw {align1} ; (f0.0)add (1) tmp_ud1<1>:ud tmp_ud1<0,1,0>:ud 32:uw {align1} ; (f0.0)shl (1) tmp_uw1<1>:uw tmp_uw1<0,1,0>:uw MFC_MV32_BIT_SHIFT:uw {align1} ; (f0.0)add (1) tmp_uw1<1>:uw tmp_uw1<0,1,0>:uw MVSIZE_UW_BASE:uw {align1} ; add (1) tmp_uw1<1>:uw tmp_uw1<0,1,0>:uw CBP_DC_YUV_UW:uw {align1} ; mov (1) msg_reg1.0<1>:uw vme_wb0.0<0,1,0>:uw {align1} ; mov (1) msg_reg1.2<1>:uw tmp_uw1<0,1,0>:uw {align1} ; mov (1) msg_reg1.4<1>:UD vme_wb0.28<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:ud tmp_ud1<0,1,0>:ud {align1} ; jmpi (1) __OUTPUT_INFO ; __INTRA_INFO: mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; __OUTPUT_INFO: /* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_0, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; add (1) orig_x_ub<1>:ub orig_x_ub<0,1,0>:ub 1:uw {align1} ; add (1) vme_m0.8<1>:UW vme_m0.8<0,1,0>:UW 16:UW {align1}; /* X += 16 */ #ifdef DEV_SNB add (1) vme_m0.0<1>:W vme_m0.0<0,1,0>:W 16:W {align1}; /* X += 16 */ #endif cmp.e.f0.0 (1) null<1>:uw w_in_mb_uw<0,1,0>:uw orig_x_ub<0,1,0>:ub {align1}; /* (0, y + 1) */ (f0.0)mov (1) orig_x_ub<1>:ub 0:uw {align1} ; (f0.0)add (1) orig_y_ub<1>:ub orig_y_ub<0,1,0>:ub 1:uw {align1} ; (f0.0)mov (1) vme_m0.8<1>:uw 0:uw {align1} ; (f0.0)add (1) vme_m0.10<1>:uw vme_m0.10<0,1,0>:uw 16:uw {align1} ; #ifdef DEV_SNB (f0.0)mov (1) vme_m0.0<1>:w -16:W {align1}; /* Reference = (x-16,y-12)-(x+32,y+24) */ (f0.0)add (1) vme_m0.2<1>:w vme_m0.2<0,1,0>:w 16:w {align1}; #endif shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* Source = (x, y) * 16 */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UW {align1} ; add.z.f0.1 (1) num_macroblocks<1>:w num_macroblocks<0,1,0>:w -1:w {align1} ; (-f0.1)jmpi (1) __VME_LOOP ; __EXIT: /* * kill thread */ mov (8) msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; intel-driver-1.3.0/src/shaders/vme/inter_frame.g6a000066400000000000000000000000561231401140700220120ustar00rootroot00000000000000#include "vme.inc" #include "inter_frame.asm" intel-driver-1.3.0/src/shaders/vme/inter_frame.g6b000066400000000000000000000144431231401140700220200ustar00rootroot00000000000000 { 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 }, { 0x00000001, 0x24340231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00200009, 0x24402e29, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24403dad, 0x00000440, 0xfff0fff0 }, { 0x00000040, 0x24423dad, 0x00000442, 0xfff4fff4 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00203000 }, { 0x00000001, 0x24540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x24560169, 0x00000000, 0x28302830 }, { 0x00000001, 0x24600061, 0x00000000, 0x00000002 }, { 0x00000001, 0x24640061, 0x00000000, 0x40000000 }, { 0x00000001, 0x24640231, 0x0000009c, 0x00000000 }, { 0x00000001, 0x24680061, 0x00000000, 0x30003030 }, { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 }, { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 }, { 0x00000041, 0x24880c21, 0x00000488, 0x0000000a }, { 0x00000001, 0x24940231, 0x00000014, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 }, { 0x04600031, 0x22401cd1, 0x00000000, 0x02188004 }, { 0x00600001, 0x20000022, 0x008d0420, 0x00000000 }, { 0x04600031, 0x22801cd1, 0x00000000, 0x02288004 }, { 0x00600001, 0x20000022, 0x008d0440, 0x00000000 }, { 0x00000001, 0x247c0169, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, { 0x00010001, 0x247c00f1, 0x00000000, 0x00000002 }, { 0x02000010, 0x20002e28, 0x000000a0, 0x00000000 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000060 }, { 0x02000010, 0x20002e28, 0x000000a1, 0x00000000 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000010 }, { 0x02000041, 0x20004628, 0x000000a0, 0x000000a1 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000004 }, { 0x00000040, 0x25202e2d, 0x000000a0, 0x00010001 }, { 0x00000040, 0x2520352d, 0x000000a2, 0x00004520 }, { 0x02000041, 0x200045a0, 0x00000520, 0x000000a1 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000008 }, { 0x02000005, 0x20002e28, 0x000000a4, 0x00020002 }, { 0x00010005, 0x247d1e31, 0x0000047d, 0x000000e0 }, { 0x00600001, 0x20200022, 0x008d0460, 0x00000000 }, { 0x00600001, 0x20400062, 0x00000000, 0x00000000 }, { 0x00000001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00000005, 0x22440c21, 0x00000244, 0xff000000 }, { 0x00600001, 0x20400022, 0x008d0240, 0x00000000 }, { 0x00600001, 0x206000e2, 0x00000000, 0x00000000 }, { 0x00800001, 0x20600232, 0x00cf0283, 0x00000000 }, { 0x00000001, 0x20700062, 0x00000000, 0x11111111 }, { 0x08600031, 0x21801cdd, 0x00000000, 0x08486000 }, { 0x00600001, 0x20000022, 0x008d0480, 0x00000000 }, { 0x00800001, 0x24a00229, 0x00b101a0, 0x00000000 }, { 0x00600040, 0x44a03dad, 0x00ae04a0, 0xffc0ffc0 }, { 0x00600040, 0x44a23dad, 0x00ae04a2, 0xffd0ffd0 }, { 0x00800001, 0x24c00229, 0x00b101b0, 0x00000000 }, { 0x00600040, 0x44c03dad, 0x00ae04c0, 0xffc0ffc0 }, { 0x00600040, 0x44c23dad, 0x00ae04c2, 0xffd0ffd0 }, { 0x00800001, 0x24e00229, 0x00b101c0, 0x00000000 }, { 0x00600040, 0x44e03dad, 0x00ae04e0, 0xffc0ffc0 }, { 0x00600040, 0x44e23dad, 0x00ae04e2, 0xffd0ffd0 }, { 0x00800001, 0x25000229, 0x00b101d0, 0x00000000 }, { 0x00600040, 0x45003dad, 0x00ae0500, 0xffc0ffc0 }, { 0x00600040, 0x45023dad, 0x00ae0502, 0xffd0ffd0 }, { 0x00600001, 0x20200022, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x20400022, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x20600022, 0x008d04e0, 0x00000000 }, { 0x00600001, 0x20800022, 0x008d0500, 0x00000000 }, { 0x05800031, 0x22001cdd, 0x00000000, 0x0a1b0403 }, { 0x00000040, 0x20080c22, 0x00000488, 0x00000008 }, { 0x01000005, 0x20000c20, 0x00000180, 0x00002000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x0000001c }, { 0x00000001, 0x25420169, 0x00000000, 0x00000000 }, { 0x00000001, 0x25440061, 0x00000000, 0x00000000 }, { 0x00010005, 0x25422d29, 0x00000182, 0x00100010 }, { 0x00010008, 0x25422d29, 0x00200542, 0x00040004 }, { 0x00010041, 0x25442d21, 0x00000542, 0x00600060 }, { 0x00010040, 0x25442c21, 0x00000544, 0x00200020 }, { 0x00010009, 0x25422d29, 0x00000542, 0x00050005 }, { 0x00010040, 0x25422d29, 0x00000542, 0x00400040 }, { 0x00000040, 0x25422d29, 0x00000542, 0x000e000e }, { 0x00000001, 0x2020012a, 0x00000180, 0x00000000 }, { 0x00000001, 0x2022012a, 0x00000542, 0x00000000 }, { 0x00000001, 0x20240022, 0x0000019c, 0x00000000 }, { 0x00000001, 0x20280022, 0x00000544, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00000001, 0x20200022, 0x00000180, 0x00000000 }, { 0x00000001, 0x20240022, 0x00000190, 0x00000000 }, { 0x00000001, 0x20280022, 0x00000194, 0x00000000 }, { 0x00000001, 0x202c0022, 0x00000198, 0x00000000 }, { 0x05800031, 0x22001cdd, 0x00000000, 0x041b0003 }, { 0x00000040, 0x20a02e31, 0x000000a0, 0x00010001 }, { 0x00000040, 0x24482d29, 0x00000448, 0x00100010 }, { 0x00000040, 0x24403dad, 0x00000440, 0x00100010 }, { 0x01000010, 0x20004528, 0x000000a2, 0x000000a0 }, { 0x00010001, 0x20a00171, 0x00000000, 0x00000000 }, { 0x00010040, 0x20a12e31, 0x000000a1, 0x00010001 }, { 0x00010001, 0x24480169, 0x00000000, 0x00000000 }, { 0x00010040, 0x244a2d29, 0x0000044a, 0x00100010 }, { 0x00010001, 0x244001ed, 0x00000000, 0xfff0fff0 }, { 0x00010040, 0x24423dad, 0x00000442, 0x00100010 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24882c21, 0x00000488, 0x000a000a }, { 0x01000040, 0x20a63dad, 0x020000a6, 0xffffffff }, { 0x00110020, 0x34001c00, 0x02001400, 0xffffff50 }, { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001cc8, 0x00000000, 0x82000010 }, intel-driver-1.3.0/src/shaders/vme/inter_frame.g7a000066400000000000000000000000561231401140700220130ustar00rootroot00000000000000#include "vme.inc" #include "inter_frame.asm" intel-driver-1.3.0/src/shaders/vme/inter_frame.g7b000066400000000000000000000132171231401140700220170ustar00rootroot00000000000000 { 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 }, { 0x00000001, 0x24340231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000001, 0x244001ed, 0x00000000, 0xfff0fff0 }, { 0x00000001, 0x244201ed, 0x00000000, 0xfff4fff4 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00203000 }, { 0x00000001, 0x24540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x24560169, 0x00000000, 0x28302830 }, { 0x00000001, 0x24600061, 0x00000000, 0x00000002 }, { 0x00000001, 0x24640061, 0x00000000, 0x40000000 }, { 0x00000001, 0x24640231, 0x0000009c, 0x00000000 }, { 0x00000001, 0x24680061, 0x00000000, 0x30003030 }, { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 }, { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 }, { 0x00000041, 0x24880c21, 0x00000488, 0x0000000a }, { 0x00000001, 0x24940231, 0x00000014, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 }, { 0x04600031, 0x22401cb1, 0x00000800, 0x02190004 }, { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 }, { 0x04600031, 0x22801cb1, 0x00000800, 0x02290004 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x247c0169, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, { 0x00010001, 0x247c00f1, 0x00000000, 0x00000002 }, { 0x02000010, 0x20002e28, 0x000000a0, 0x00000000 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000060 }, { 0x02000010, 0x20002e28, 0x000000a1, 0x00000000 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000010 }, { 0x02000041, 0x20004628, 0x000000a0, 0x000000a1 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000004 }, { 0x00000040, 0x25202e2d, 0x000000a0, 0x00010001 }, { 0x00000040, 0x2520352d, 0x000000a2, 0x00004520 }, { 0x02000041, 0x200045a0, 0x00000520, 0x000000a1 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000008 }, { 0x02000005, 0x20002e28, 0x000000a4, 0x00020002 }, { 0x00010005, 0x247d1e31, 0x0000047d, 0x000000e0 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00000005, 0x22440c21, 0x00000244, 0xff000000 }, { 0x00600001, 0x28600021, 0x008d0240, 0x00000000 }, { 0x00600001, 0x288000e1, 0x00000000, 0x00000000 }, { 0x00800001, 0x28800231, 0x00cf0283, 0x00000000 }, { 0x00000001, 0x28900061, 0x00000000, 0x11111111 }, { 0x08600031, 0x21801cbd, 0x00000800, 0x0a686000 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x24a00021, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x24c00021, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x24e00021, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x25000021, 0x008d0200, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d04a0, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d04c0, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d04e0, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d0500, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x0a0a0403 }, { 0x00000040, 0x28080c21, 0x00000488, 0x00000008 }, { 0x01000005, 0x20000c20, 0x00000180, 0x00002000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x0000001c }, { 0x00000001, 0x25420169, 0x00000000, 0x00000000 }, { 0x00000001, 0x25440061, 0x00000000, 0x00000000 }, { 0x00010005, 0x25422d29, 0x00000182, 0x00200020 }, { 0x00010008, 0x25422d29, 0x00200542, 0x00050005 }, { 0x00010041, 0x25442d21, 0x00000542, 0x00600060 }, { 0x00010040, 0x25442c21, 0x00000544, 0x00200020 }, { 0x00010009, 0x25422d29, 0x00000542, 0x00050005 }, { 0x00010040, 0x25422d29, 0x00000542, 0x00400040 }, { 0x00000040, 0x25422d29, 0x00000542, 0x000e000e }, { 0x00000001, 0x28200129, 0x00000180, 0x00000000 }, { 0x00000001, 0x28220129, 0x00000542, 0x00000000 }, { 0x00000001, 0x28240021, 0x0000019c, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000544, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0003 }, { 0x00000040, 0x20a02e31, 0x000000a0, 0x00010001 }, { 0x00000040, 0x24482d29, 0x00000448, 0x00100010 }, { 0x01000010, 0x20004528, 0x000000a2, 0x000000a0 }, { 0x00010001, 0x20a00171, 0x00000000, 0x00000000 }, { 0x00010040, 0x20a12e31, 0x000000a1, 0x00010001 }, { 0x00010001, 0x24480169, 0x00000000, 0x00000000 }, { 0x00010040, 0x244a2d29, 0x0000044a, 0x00100010 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24882c21, 0x00000488, 0x000a000a }, { 0x01000040, 0x20a63dad, 0x020000a6, 0xffffffff }, { 0x00110020, 0x34001c00, 0x02001400, 0xffffff66 }, { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca8, 0x00000800, 0x82000010 }, intel-driver-1.3.0/src/shaders/vme/inter_frame_gen8.asm000066400000000000000000000651741231401140700230520ustar00rootroot00000000000000/* * Copyright © <2013>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: Inter_frame_gen8.asm // // Make inter predition estimation for Inter-frame on gen8 // // // Now, begin source code.... // #define SAVE_RET add (1) RETURN_REG<1>:ud ip:ud 32:ud #define RETURN mov (1) ip:ud RETURN_REG<0,1,0>:ud /* * __START */ __INTER_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ; shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1}; mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1}; mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 24:UD {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* * Media Read Message -- fetch Luma neighbor edge pixels */ /* ROW */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1}; /* * Media Read Message -- fetch Chroma neighbor edge pixels */ /* ROW */ shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16 , y * 8 */ mul (1) read0_header.0<1>:D read0_header.0<0,1,0>:D 2:W {align1}; add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind CHROMA_ROW<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16, y * 8 */ mul (1) read1_header.0<1>:D read1_header.0<0,1,0>:D 2:W {align1}; add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_8X4 {align1}; mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind CHROMA_COL<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1}; mov (8) mb_mvp_ref.0<1>:ud 0:ud {align1}; mov (8) mb_ref_win.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1}; (f0.0) jmpi (1) __mb_hwdep_end; /* read back the data for MB A */ /* the layout of MB result is: rx.0(Available). rx.4(MVa), rX.8(MVb), rX.16(Pred_L0 flag), * rX.18 (Pred_L1 flag), rX.20(Forward reference ID), rX.22(Backwared reference ID) */ mov (8) mba_result.0<1>:ud 0x0:ud {align1}; mov (8) mbb_result.0<1>:ud 0x0:ud {align1}; mov (8) mbc_result.0<1>:ud 0x0:ud {align1}; mba_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; /* MB A doesn't exist. Zero MV. mba_flag is zero and ref ID = -1 */ (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; mov (1) mba_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB A */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* MV */ mov (2) mba_result.4<1>:ud mb_mv1.8<2,2,1>:ud {align1}; mov (1) mba_result.16<1>:w MB_PRED_FLAG {align1}; mbb_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; /* MB B doesn't exist. Zero MV. mba_flag is zero */ /* If MB B doesn't exist, neither MB C nor D exists */ (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbb_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbc_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB B */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ mov (2) mbb_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1}; mov (1) mbb_result.16<1>:w MB_PRED_FLAG {align1}; mbc_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_C:uw {align1}; /* MB C doesn't exist. Zero MV. mba_flag is zero */ /* Based on h264 spec the MB D will be replaced if MB C doesn't exist */ (f0.0) jmpi (1) mbd_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB C */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1}; mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1}; jmpi (1) mb_mvp_start; mbd_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_D:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (2) tmp_reg0.0<1>:w tmp_reg0.0<2,2,1>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB D */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ub NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv3.24<2,2,1>:ud {align1}; mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1}; mb_mvp_start: /*TODO: Add the skip prediction */ /* Check whether both MB B and C are inavailable */ add (1) tmp_reg0.0<1>:d mbb_result.0<0,1,0>:d mbc_result.0<0,1,0>:d {align1}; cmp.z.f0.0 (1) null:d tmp_reg0.0<0,1,0>:d 0:d {align1}; (-f0.0) jmpi (1) mb_median_start; cmp.nz.f0.0 (1) null:d mba_result.0<0,1,0>:d 0:d {align1}; (f0.0) mov (1) mbb_result.4<1>:ud mba_result.4<0,1,0>:ud {align1}; (f0.0) mov (1) mbc_result.4<1>:ud mba_result.4<0,1,0>:ud {align1}; (f0.0) mov (1) mbb_result.20<1>:uw mba_result.20<0,1,0>:uw {align1}; (f0.0) mov (1) mbc_result.20<1>:uw mba_result.20<0,1,0>:uw {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud mba_result.4<0,1,0>:ud {align1}; (-f0.0) mov (1) mb_mvp_ref.0<1>:ud 0:ud {align1}; jmpi (1) __mb_hwdep_end; mb_median_start: /* check whether only one neighbour MB has the same ref ID with the current MB */ mov (8) tmp_reg0.0<1>:ud 0:ud {align1}; cmp.z.f0.0 (1) null:d mba_result.20<0,1,0>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbb_result.20<0,1,0>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbc_result.20<0,1,0>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.4<0,1,0>:ud {align1}; cmp.e.f0.0 (1) null:d tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud tmp_reg0.4<0,1,0>:ud {align1}; (f0.0) jmpi (1) __mb_hwdep_end; mov (1) INPUT_ARG0.0<1>:w mba_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.4<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.0<1>:w RET_ARG<0,1,0>:w {align1}; mov (1) INPUT_ARG0.0<1>:w mba_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.6<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.2<1>:w RET_ARG<0,1,0>:w {align1}; __mb_hwdep_end: asr (2) mb_ref_win.0<1>:w mb_mvp_ref.0<2,2,1>:w 2:w {align1}; add (2) mb_ref_win.8<1>:w mb_ref_win.0<2,2,1>:w 3:w {align1}; and (2) mb_ref_win.16<1>:uw mb_ref_win.8<2,2,1>:uw 0xFFFC:uw {align1}; /* m2, get the MV/Mb cost passed from constant buffer when spawning thread by MEDIA_OBJECT */ mov (8) vme_m2<1>:UD r1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* m3 FWD/BWD cost center*/ mov (8) vme_msg_3<1>:UD 0x0:UD {align1}; /* m4 skip center*/ mov (8) vme_msg_4<1>:UD 0x0:UD {align1}; /* m5 */ mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1}; and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1}; mov (8) vme_msg_5<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; /* Use the Luma mode */ mov (1) tmp_reg0.0<1>:UW LUMA_INTRA_MODE:UW {align1}; mov (1) vme_msg_5.5<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* m6 */ mov (8) vme_msg_6<1>:UD 0x0:UD {align1}; mov (16) vme_msg_6.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1}; mov (1) vme_msg_6.16<1>:UD INTRA_PREDICTORE_MODE {align1}; /* the penalty for Intra mode */ mov (1) vme_msg_6.28<1>:UD 0x010101:UD {align1}; mov (1) vme_msg_6.20<1>:UW CHROMA_ROW.6<0,1,0>:UW {align1}; /* m7 */ mov (4) vme_msg_7.16<1>:UD CHROMA_ROW.8<4,4,1>:UD {align1}; mov (8) vme_msg_7.0<1>:UW CHROMA_COL.2<16,8,2>:UW {align1}; /* * SIC VME message */ /* m1 */ mov (1) intra_flag<1>:UW 0x0:UW {align1} ; and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1}; (f0.0) mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE {align1}; /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; /* Disable DC HAAR component when calculating HARR SATD block */ mov (1) tmp_reg0.0<1>:UW DC_HARR_DISABLE:UW {align1}; mov (1) vme_m1.30<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* m0 */ mov (1) vme_m0.12<1>:UD INTRA_SAD_HAAR:UD {align1}; /* 16x16 Source, Intra_harr */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_SIC_MESSAGE_TYPE ) mlen sic_vme_msg_length rlen vme_wb_length {align1}; /* * Oword Block Write message */ mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Distortion, Intra (17-16), */ mov (1) msg_reg1.16<1>:UW vme_wb.12<0,1,0>:UW {align1}; mov (1) msg_reg1.20<1>:UD vme_wb.8<0,1,0>:UD {align1}; /* VME clock counts */ mov (1) msg_reg1.24<1>:UD vme_wb.28<0,1,0>:UD {align1}; mov (1) msg_reg1.28<1>:UD obw_m0.8<0,1,0>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* IME search */ mov (1) vme_m0.12<1>:UD SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR:UD {align1}; /* 16x16 Source, harr */ mov (1) vme_m0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 48x40 */ mov (1) vme_m0.0<1>:UD vme_m0.8<0,1,0>:UD {align1}; add (1) vme_m0.0<1>:W vme_m0.0<0,1,0>:W -16:W {align1}; /* Reference = (x-16,y-12)-(x+32,y+28) */ add (1) vme_m0.2<1>:W vme_m0.2<0,1,0>:W -12:W {align1}; mov (1) vme_m0.0<1>:W -16:W {align1}; mov (1) vme_m0.2<1>:W -12:W {align1}; mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; (f0.0) add (1) vme_m0.0<1>:w vme_m0.0<0,1,0>:w 12:w {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; (f0.0) add (1) vme_m0.2<1>:w vme_m0.2<0,1,0>:w 8:w {align1}; add (2) vme_m0.0<1>:w vme_m0.0<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; add (2) vme_m0.4<1>:w vme_m0.4<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; /* the Max MV number is passed by constant buffer */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; mov (1) vme_m1.8<1>:UD START_CENTER + SEARCH_PATH_LEN:UD {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* Setup the Cost center */ /* currently four 8x8 share the same cost center */ mov (4) vme_m3.0<2>:ud mb_mvp_ref.0<0,1,0>:ud {align1}; mov (4) vme_m3.4<2>:ud mb_mvp_ref.0<0,1,0>:ud {align1}; mov (8) vme_msg_3<1>:UD vme_m3.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* M4/M5 search path */ mov (1) vme_msg_4.0<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_4.4<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_4.8<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_4.12<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_4.16<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_4.20<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_4.24<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_4.28<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_5.0<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_5.4<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_5.8<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_5.12<1>:UD 0x000F0F0F:UD {align1}; mov (4) vme_msg_5.16<1>:UD 0x0:UD {align1}; send (8) vme_msg_ind vme_wb<1>:UD null vme( BIND_IDX_VME, 0, 0, VME_IME_MESSAGE_TYPE ) mlen ime_vme_msg_length rlen vme_wb_length {align1}; /* Set Macroblock-shape/mode for FBR */ mov (1) vme_m2.20<1>:UD 0x0:UD {align1}; mov (1) vme_m2.21<1>:UB vme_wb.25<0,1,0>:UB {align1}; mov (1) vme_m2.22<1>:UB vme_wb.26<0,1,0>:UB {align1}; and (1) tmp_reg0.0<1>:UW vme_wb.0<0,1,0>:UW 0x03:UW {align1}; mov (1) vme_m2.20<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* Send FBR message into CRE */ mov (8) vme_msg_4.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) vme_msg_5.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) vme_msg_6.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) vme_msg_7.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; mov (1) vme_m0.12<1>:UD INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER + FBR_BME_DISABLE:UD {align1}; /* 16x16 Source, 1/4 pixel, harr, BME disable */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2.0<1>:UD vme_m2.0<8,8,1>:UD {align1}; mov (8) vme_msg_3.0<1>:UD vme_m3.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_FBR_MESSAGE_TYPE ) mlen fbr_vme_msg_length rlen vme_wb_length {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; /* write FME info */ mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Inter distortion of FME */ mov (1) msg_reg1.8<1>:UD vme_wb.8<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_m2.20<0,1,0>:UD {align1}; /* bind index 3, write oword (16bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_0, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Write FME/BME MV */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x01:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0.0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) msg_reg2.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) msg_reg3.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) msg_reg4.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; /* bind index 3, write 8 oword (128 bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_8, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 5 rlen obw_wb_length {align1}; /* Write FME/BME RefID */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x08:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb6.0<8,8,1>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Issue message fence so that the previous write message is committed */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_FENCE, OBR_MF_COMMIT, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; nop ; nop ; /* Compare three word data to get the min value */ word_imin: cmp.le.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; cmp.le.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; RETURN {align1}; /* Compare three word data to get the max value */ word_imax: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; cmp.ge.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; RETURN {align1}; word_imedian: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_a_ge_b; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; jmpi (1) cmp_end; cmp_a_ge_b: cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; cmp_end: RETURN {align1}; intel-driver-1.3.0/src/shaders/vme/inter_frame_gen8.g8a000066400000000000000000000000641231401140700227340ustar00rootroot00000000000000#include "vme8.inc" #include "inter_frame_gen8.asm" intel-driver-1.3.0/src/shaders/vme/inter_frame_gen8.g8b000066400000000000000000000401641231401140700227420ustar00rootroot00000000000000 { 0x00800001, 0x24000608, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400608, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800608, 0x00000000, 0x00000000 }, { 0x00800001, 0x24c00608, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002228, 0x164500a0, 0x00040004 }, { 0x00000040, 0x24000a28, 0x1e000400, 0xfff8fff8 }, { 0x00000040, 0x24040a28, 0x1e000404, 0xffffffff }, { 0x00000001, 0x24080e08, 0x08000000, 0x0000001f }, { 0x00000001, 0x24142288, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202228, 0x164500a0, 0x00040004 }, { 0x00000040, 0x24200a28, 0x1e000420, 0xfffcfffc }, { 0x00000001, 0x24280e08, 0x08000000, 0x000f0003 }, { 0x00000001, 0x24342288, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482248, 0x164500a0, 0x00040004 }, { 0x00000001, 0x24542288, 0x00000014, 0x00000000 }, { 0x00000041, 0x24881208, 0x220000a2, 0x000000a1 }, { 0x00000040, 0x24880208, 0x22000488, 0x000000a0 }, { 0x00000041, 0x24880208, 0x06000488, 0x00000018 }, { 0x00000001, 0x24942288, 0x00000014, 0x00000000 }, { 0x00600001, 0x28000208, 0x008d0400, 0x00000000 }, { 0x04600031, 0x23800a88, 0x0e000800, 0x02190004 }, { 0x00600001, 0x28000208, 0x008d0420, 0x00000000 }, { 0x04600031, 0x23a00a88, 0x0e000800, 0x02290004 }, { 0x00200009, 0x24002228, 0x164500a0, 0x00030003 }, { 0x00000041, 0x24000a28, 0x1e000400, 0x00020002 }, { 0x00000040, 0x24000a28, 0x1e000400, 0xfff8fff8 }, { 0x00000040, 0x24040a28, 0x1e000404, 0xffffffff }, { 0x00600001, 0x28000208, 0x008d0400, 0x00000000 }, { 0x04600031, 0x26000a88, 0x0e000800, 0x02190006 }, { 0x00200009, 0x24202228, 0x164500a0, 0x00030003 }, { 0x00000041, 0x24200a28, 0x1e000420, 0x00020002 }, { 0x00000040, 0x24200a28, 0x1e000420, 0xfffcfffc }, { 0x00000001, 0x24280e08, 0x08000000, 0x00070003 }, { 0x00600001, 0x28000208, 0x008d0420, 0x00000000 }, { 0x04600031, 0x26200a88, 0x0e000800, 0x02190006 }, { 0x00600001, 0x2ac00608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a800608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20001240, 0x160000a6, 0x00040004 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000750 }, { 0x00600001, 0x2ae00608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b000608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b200608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b400608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00600060 }, { 0x00210001, 0x2af41e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000f0 }, { 0x00000001, 0x2ae00e28, 0x08000000, 0x00000001 }, { 0x00200001, 0x24002248, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24001a68, 0x1e000400, 0xffffffff }, { 0x00000041, 0x2b481208, 0x120000a2, 0x00000402 }, { 0x00000040, 0x2b480208, 0x12000b48, 0x00000400 }, { 0x00000041, 0x2b480208, 0x06000b48, 0x00000018 }, { 0x00000001, 0x2b542288, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x02280303 }, { 0x05000010, 0x20001260, 0x12000b70, 0x00000b88 }, { 0x00210001, 0x2af41e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000040 }, { 0x00000040, 0x2b480208, 0x06000b48, 0x00000003 }, { 0x0a800031, 0x2ba00a08, 0x0e000b40, 0x02480403 }, { 0x00200001, 0x2ae40208, 0x00450bc8, 0x00000000 }, { 0x00000001, 0x2af01e68, 0x18000000, 0x00010001 }, { 0x00600001, 0x2b400608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00100010 }, { 0x00210001, 0x2b141e68, 0x18000000, 0xffffffff }, { 0x00210001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000360 }, { 0x00000001, 0x2b000e28, 0x08000000, 0x00000001 }, { 0x00200001, 0x24002248, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24021a68, 0x1e000402, 0xffffffff }, { 0x00000041, 0x2b481208, 0x120000a2, 0x00000402 }, { 0x00000040, 0x2b480208, 0x12000b48, 0x00000400 }, { 0x00000041, 0x2b480208, 0x06000b48, 0x00000018 }, { 0x00000001, 0x2b542288, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x02280303 }, { 0x05000010, 0x20001260, 0x12000b70, 0x00000b88 }, { 0x00210001, 0x2b141e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000040 }, { 0x00000040, 0x2b480208, 0x06000b48, 0x00000003 }, { 0x0a800031, 0x2ba00a08, 0x0e000b40, 0x02480403 }, { 0x00200001, 0x2b040208, 0x00450bf0, 0x00000000 }, { 0x00000001, 0x2b101e68, 0x18000000, 0x00010001 }, { 0x00600001, 0x2b400608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00080008 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000110 }, { 0x00000001, 0x2b200e28, 0x08000000, 0x00000001 }, { 0x00200001, 0x24002248, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24021a68, 0x1e000402, 0xffffffff }, { 0x00000040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00000041, 0x2b481208, 0x120000a2, 0x00000402 }, { 0x00000040, 0x2b480208, 0x12000b48, 0x00000400 }, { 0x00000041, 0x2b480208, 0x06000b48, 0x00000018 }, { 0x00000001, 0x2b542288, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x02280303 }, { 0x05000010, 0x20001260, 0x12000b70, 0x00000b88 }, { 0x00210001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000180 }, { 0x00000040, 0x2b480208, 0x06000b48, 0x00000003 }, { 0x0a800031, 0x2ba00a08, 0x0e000b40, 0x02480403 }, { 0x00200001, 0x2b240208, 0x00450bf0, 0x00000000 }, { 0x00000001, 0x2b301e68, 0x18000000, 0x00010001 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000130 }, { 0x00600001, 0x2b400608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00040004 }, { 0x00210001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000f0 }, { 0x00000001, 0x2b200e28, 0x08000000, 0x00000001 }, { 0x00200001, 0x24002248, 0x004500a0, 0x00000000 }, { 0x00200040, 0x24001a68, 0x1e450400, 0xffffffff }, { 0x00000041, 0x2b481208, 0x120000a2, 0x00000402 }, { 0x00000040, 0x2b480208, 0x12000b48, 0x00000400 }, { 0x00000041, 0x2b480208, 0x06000b48, 0x00000018 }, { 0x00000001, 0x2b542288, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x02280303 }, { 0x05000010, 0x20001260, 0x12000b70, 0x00000b88 }, { 0x00210001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000040 }, { 0x00000040, 0x2b480208, 0x06000b48, 0x00000003 }, { 0x0a800031, 0x2ba00a88, 0x0e000b40, 0x02480403 }, { 0x00200001, 0x2b240208, 0x00450c18, 0x00000000 }, { 0x00000001, 0x2b301e68, 0x18000000, 0x00010001 }, { 0x00000040, 0x24000a28, 0x0a000b00, 0x00000b20 }, { 0x01000010, 0x20000a20, 0x0e000400, 0x00000000 }, { 0x00110020, 0x34000000, 0x0e001400, 0x00000080 }, { 0x02000010, 0x20000a20, 0x0e000ae0, 0x00000000 }, { 0x00010001, 0x2b040208, 0x00000ae4, 0x00000000 }, { 0x00010001, 0x2b240208, 0x00000ae4, 0x00000000 }, { 0x00010001, 0x2b141248, 0x00000af4, 0x00000000 }, { 0x00010001, 0x2b341248, 0x00000af4, 0x00000000 }, { 0x00010001, 0x2ac00208, 0x00000ae4, 0x00000000 }, { 0x00110001, 0x2ac00608, 0x00000000, 0x00000000 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000190 }, { 0x00600001, 0x24000608, 0x00000000, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000af4, 0x00000000 }, { 0x00010040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00010001, 0x24040208, 0x00000ae4, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000b14, 0x00000000 }, { 0x00010040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00010001, 0x24040208, 0x00000b04, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000b34, 0x00000000 }, { 0x00010040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00010001, 0x24040208, 0x00000b24, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000400, 0x00010001 }, { 0x00010001, 0x2ac00208, 0x00000404, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000c0 }, { 0x00000001, 0x2fa01a68, 0x00000ae4, 0x00000000 }, { 0x00000001, 0x2fa41a68, 0x00000b04, 0x00000000 }, { 0x00000001, 0x2fa81a68, 0x00000b24, 0x00000000 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000870 }, { 0x00000001, 0x2ac01a68, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2fa01a68, 0x00000ae6, 0x00000000 }, { 0x00000001, 0x2fa41a68, 0x00000b06, 0x00000000 }, { 0x00000001, 0x2fa81a68, 0x00000b26, 0x00000000 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000810 }, { 0x00000001, 0x2ac21a68, 0x00000fe4, 0x00000000 }, { 0x0020000c, 0x2a801a68, 0x1e450ac0, 0x00020002 }, { 0x00200040, 0x2a881a68, 0x1e450a80, 0x00030003 }, { 0x00200005, 0x2a901248, 0x16450a88, 0xfffcfffc }, { 0x00600001, 0x25600208, 0x008d0020, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d0560, 0x00000000 }, { 0x00600001, 0x28600608, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23800608, 0x00000000, 0x00000000 }, { 0x00000005, 0x23840208, 0x06000384, 0xff000000 }, { 0x00600001, 0x28a00208, 0x008d0380, 0x00000000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00010001 }, { 0x00000001, 0x28a52288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28c00608, 0x00000000, 0x00000000 }, { 0x00800001, 0x28c02288, 0x00cf03a3, 0x00000000 }, { 0x00000001, 0x28d00608, 0x00000000, 0x11111111 }, { 0x00000001, 0x28dc0608, 0x00000000, 0x00010101 }, { 0x00000001, 0x28d41248, 0x00000606, 0x00000000 }, { 0x00400001, 0x28f00208, 0x00690608, 0x00000000 }, { 0x00600001, 0x28e01248, 0x00ae0622, 0x00000000 }, { 0x00000001, 0x247c1648, 0x10000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a4, 0x00010001 }, { 0x00010001, 0x247c0e88, 0x08000000, 0x00000002 }, { 0x00000001, 0x247d2288, 0x000000a5, 0x00000000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00200020 }, { 0x00000001, 0x247e2288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x00000001, 0x244c0608, 0x00000000, 0x00800000 }, { 0x00600001, 0x28000208, 0x008d0440, 0x00000000 }, { 0x0d600031, 0x21800a08, 0x0e000800, 0x10782000 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200208, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240208, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280208, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0208, 0x00000198, 0x00000000 }, { 0x00000001, 0x28301248, 0x0000018c, 0x00000000 }, { 0x00000001, 0x28340208, 0x00000188, 0x00000000 }, { 0x00000001, 0x28380208, 0x0000019c, 0x00000000 }, { 0x00000001, 0x283c0208, 0x00000488, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x040a0203 }, { 0x00000001, 0x244c0608, 0x00000000, 0x00200000 }, { 0x00000001, 0x24561648, 0x10000000, 0x28302830 }, { 0x00000001, 0x24400208, 0x00000448, 0x00000000 }, { 0x00000040, 0x24401a68, 0x1e000440, 0xfff0fff0 }, { 0x00000040, 0x24421a68, 0x1e000442, 0xfff4fff4 }, { 0x00000001, 0x24401e68, 0x18000000, 0xfff0fff0 }, { 0x00000001, 0x24421e68, 0x18000000, 0xfff4fff4 }, { 0x00000001, 0x24440208, 0x00000440, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00600060 }, { 0x00010040, 0x24401a68, 0x1e000440, 0x000c000c }, { 0x01000005, 0x20002240, 0x160000a5, 0x00100010 }, { 0x00010040, 0x24421a68, 0x1e000442, 0x00080008 }, { 0x00200040, 0x24401a68, 0x1a450440, 0x00450a90 }, { 0x00200040, 0x24441a68, 0x1a450444, 0x00450a90 }, { 0x00600001, 0x28000208, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24600608, 0x00000000, 0x00000002 }, { 0x00000001, 0x24642288, 0x0000009c, 0x00000000 }, { 0x00000001, 0x24680608, 0x00000000, 0x30003030 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x00400001, 0x45800208, 0x00000ac0, 0x00000000 }, { 0x00400001, 0x45840208, 0x00000ac0, 0x00000000 }, { 0x00600001, 0x28600208, 0x008d0580, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d0560, 0x00000000 }, { 0x00000001, 0x28800608, 0x00000000, 0x01010101 }, { 0x00000001, 0x28840608, 0x00000000, 0x10010101 }, { 0x00000001, 0x28880608, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x288c0608, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28900608, 0x00000000, 0x01010101 }, { 0x00000001, 0x28940608, 0x00000000, 0x10010101 }, { 0x00000001, 0x28980608, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x289c0608, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28a00608, 0x00000000, 0x01010101 }, { 0x00000001, 0x28a40608, 0x00000000, 0x10010101 }, { 0x00000001, 0x28a80608, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x28ac0608, 0x00000000, 0x000f0f0f }, { 0x00400001, 0x28b00608, 0x00000000, 0x00000000 }, { 0x08600031, 0x21800a08, 0x0e000800, 0x0c784000 }, { 0x00000001, 0x25740608, 0x00000000, 0x00000000 }, { 0x00000001, 0x25752288, 0x00000199, 0x00000000 }, { 0x00000001, 0x25762288, 0x0000019a, 0x00000000 }, { 0x00000005, 0x24001248, 0x16000180, 0x00030003 }, { 0x00000001, 0x25742288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28800208, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28a00208, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28c00208, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28e00208, 0x008d0200, 0x00000000 }, { 0x00000001, 0x244c0608, 0x00000000, 0x00243000 }, { 0x00600001, 0x28000208, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d0560, 0x00000000 }, { 0x00600001, 0x28600208, 0x008d0580, 0x00000000 }, { 0x0d600031, 0x21800a08, 0x0e000800, 0x10786000 }, { 0x00000040, 0x24880208, 0x06000488, 0x00000002 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200208, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240208, 0x00000198, 0x00000000 }, { 0x00000001, 0x28280208, 0x00000188, 0x00000000 }, { 0x00000001, 0x282c0208, 0x00000574, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x040a0003 }, { 0x00000040, 0x24880208, 0x06000488, 0x00000001 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28600208, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28800208, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x0a0a0403 }, { 0x00000040, 0x24880208, 0x06000488, 0x00000008 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d0240, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x040a0203 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x0219e003 }, { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24000a40, 0x0e000e00, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x06000010, 0x20001a60, 0x1a000fa0, 0x00000fa4 }, { 0x00010001, 0x2f601a68, 0x00000fa0, 0x00000000 }, { 0x00110001, 0x2f601a68, 0x00000fa4, 0x00000000 }, { 0x06000010, 0x20001a60, 0x1a000f60, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000f60, 0x00000000 }, { 0x00110001, 0x2fe41a68, 0x00000fa8, 0x00000000 }, { 0x00000001, 0x34000200, 0x00000fe0, 0x00000000 }, { 0x04000010, 0x20001a60, 0x1a000fa0, 0x00000fa4 }, { 0x00010001, 0x2f601a68, 0x00000fa0, 0x00000000 }, { 0x00110001, 0x2f601a68, 0x00000fa4, 0x00000000 }, { 0x04000010, 0x20001a60, 0x1a000f60, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000f60, 0x00000000 }, { 0x00110001, 0x2fe41a68, 0x00000fa8, 0x00000000 }, { 0x00000001, 0x34000200, 0x00000fe0, 0x00000000 }, { 0x04000010, 0x20001a60, 0x1a000fa0, 0x00000fa4 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000070 }, { 0x04000010, 0x20001a60, 0x1a000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000fa0, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000a0 }, { 0x04000010, 0x20001a60, 0x1a000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe41a68, 0x00000fa4, 0x00000000 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000060 }, { 0x04000010, 0x20001a60, 0x1a000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000fa4, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000030 }, { 0x04000010, 0x20001a60, 0x1a000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe41a68, 0x00000fa0, 0x00000000 }, { 0x00000001, 0x34000200, 0x00000fe0, 0x00000000 }, intel-driver-1.3.0/src/shaders/vme/inter_frame_haswell.asm000066400000000000000000000646111231401140700236430ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: Inter_frame_haswell.asm // // Make inter predition estimation for Inter-frame on Haswell // // // Now, begin source code.... // #define SAVE_RET add (1) RETURN_REG<1>:ud ip:ud 32:ud #define RETURN mov (1) ip:ud RETURN_REG<0,1,0>:ud /* * __START */ __INTER_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ; shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1}; mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1}; mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 24:UD {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* * Media Read Message -- fetch Luma neighbor edge pixels */ /* ROW */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1}; /* * Media Read Message -- fetch Chroma neighbor edge pixels */ /* ROW */ shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16 , y * 8 */ mul (1) read0_header.0<1>:D read0_header.0<0,1,0>:D 2:W {align1}; add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind CHROMA_ROW<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16, y * 8 */ mul (1) read1_header.0<1>:D read1_header.0<0,1,0>:D 2:W {align1}; add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_8X4 {align1}; mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind CHROMA_COL<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1}; mov (8) mb_mvp_ref.0<1>:ud 0:ud {align1}; mov (8) mb_ref_win.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1}; (f0.0) jmpi (1) __mb_hwdep_end; /* read back the data for MB A */ /* the layout of MB result is: rx.0(Available). rx.4(MVa), rX.8(MVb), rX.16(Pred_L0 flag), * rX.18 (Pred_L1 flag), rX.20(Forward reference ID), rX.22(Backwared reference ID) */ mov (8) mba_result.0<1>:ud 0x0:ud {align1}; mov (8) mbb_result.0<1>:ud 0x0:ud {align1}; mov (8) mbc_result.0<1>:ud 0x0:ud {align1}; mba_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; /* MB A doesn't exist. Zero MV. mba_flag is zero and ref ID = -1 */ (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; mov (1) mba_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB A */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* MV */ mov (2) mba_result.4<1>:ud mb_mv1.8<2,2,1>:ud {align1}; mov (1) mba_result.16<1>:w MB_PRED_FLAG {align1}; mbb_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; /* MB B doesn't exist. Zero MV. mba_flag is zero */ /* If MB B doesn't exist, neither MB C nor D exists */ (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbb_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbc_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB B */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ mov (2) mbb_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1}; mov (1) mbb_result.16<1>:w MB_PRED_FLAG {align1}; mbc_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_C:uw {align1}; /* MB C doesn't exist. Zero MV. mba_flag is zero */ /* Based on h264 spec the MB D will be replaced if MB C doesn't exist */ (f0.0) jmpi (1) mbd_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB C */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1}; mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1}; jmpi (1) mb_mvp_start; mbd_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_D:uw {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (2) tmp_reg0.0<1>:w tmp_reg0.0<2,2,1>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB D */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ub NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv3.24<2,2,1>:ud {align1}; mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1}; mb_mvp_start: /*TODO: Add the skip prediction */ /* Check whether both MB B and C are inavailable */ add (1) tmp_reg0.0<1>:d mbb_result.0<0,1,0>:d mbc_result.0<0,1,0>:d {align1}; cmp.z.f0.0 (1) null:d tmp_reg0.0<0,1,0>:d 0:d {align1}; (-f0.0) jmpi (1) mb_median_start; cmp.nz.f0.0 (1) null:d mba_result.0<0,1,0>:d 0:d {align1}; (f0.0) mov (1) mbb_result.4<1>:ud mba_result.4<0,1,0>:ud {align1}; (f0.0) mov (1) mbc_result.4<1>:ud mba_result.4<0,1,0>:ud {align1}; (f0.0) mov (1) mbb_result.20<1>:uw mba_result.20<0,1,0>:uw {align1}; (f0.0) mov (1) mbc_result.20<1>:uw mba_result.20<0,1,0>:uw {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud mba_result.4<0,1,0>:ud {align1}; (-f0.0) mov (1) mb_mvp_ref.0<1>:ud 0:ud {align1}; jmpi (1) __mb_hwdep_end; mb_median_start: /* check whether only one neighbour MB has the same ref ID with the current MB */ mov (8) tmp_reg0.0<1>:ud 0:ud {align1}; cmp.z.f0.0 (1) null:d mba_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbb_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbc_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.4<0,1,0>:ud {align1}; cmp.e.f0.0 (1) null:d tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud tmp_reg0.4<0,1,0>:ud {align1}; (f0.0) jmpi (1) __mb_hwdep_end; mov (1) INPUT_ARG0.0<1>:w mba_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.4<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.0<1>:w RET_ARG<0,1,0>:w {align1}; mov (1) INPUT_ARG0.0<1>:w mba_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.6<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.2<1>:w RET_ARG<0,1,0>:w {align1}; __mb_hwdep_end: asr (2) mb_ref_win.0<1>:w mb_mvp_ref.0<2,2,1>:w 2:w {align1}; add (2) mb_ref_win.8<1>:w mb_ref_win.0<2,2,1>:w 3:w {align1}; and (2) mb_ref_win.16<1>:uw mb_ref_win.8<2,2,1>:uw 0xFFFC:uw {align1}; /* m2, get the MV/Mb cost passed from constant buffer when spawning thread by MEDIA_OBJECT */ mov (8) vme_m2<1>:UD r1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* m3 */ mov (8) vme_msg_3<1>:UD 0x0:UD {align1}; /* m4 */ mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1}; and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1}; mov (8) vme_msg_4<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; /* m5 */ mov (8) vme_msg_5<1>:UD 0x0:UD {align1}; mov (16) vme_msg_5.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1}; mov (1) vme_msg_5.16<1>:UD INTRA_PREDICTORE_MODE {align1}; /* the penalty for Intra mode */ mov (1) vme_msg_5.28<1>:UD 0x010101:UD {align1}; mov (1) vme_msg_5.20<1>:UW CHROMA_ROW.6<0,1,0>:UW {align1}; /* m6 */ mov (4) vme_msg_6.16<1>:UD CHROMA_ROW.8<4,4,1>:UD {align1}; mov (8) vme_msg_6.0<1>:UW CHROMA_COL.2<16,8,2>:UW {align1}; /* * SIC VME message */ /* m0 */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (1) tmp_reg0.0<1>:UW LUMA_INTRA_MODE:UW {align1}; /* Use the Luma mode */ mov (1) vme_msg_4.5<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* m1 */ mov (1) intra_flag<1>:UW 0x0:UW {align1} ; and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1}; (f0.0) mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE {align1}; /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; /* Disable DC HAAR component when calculating HARR SATD block */ mov (1) tmp_reg0.0<1>:UW DC_HARR_DISABLE:UW {align1}; mov (1) vme_m1.30<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; mov (1) vme_m0.12<1>:UD INTRA_SAD_HAAR:UD {align1}; /* 16x16 Source, Intra_harr */ /* m0 */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_SIC_MESSAGE_TYPE ) mlen sic_vme_msg_length rlen vme_wb_length {align1}; /* * Oword Block Write message */ mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Distortion, Intra (17-16), */ mov (1) msg_reg1.16<1>:UW vme_wb.12<0,1,0>:UW {align1}; mov (1) msg_reg1.20<1>:UD vme_wb.8<0,1,0>:UD {align1}; /* VME clock counts */ mov (1) msg_reg1.24<1>:UD vme_wb.28<0,1,0>:UD {align1}; mov (1) msg_reg1.28<1>:UD obw_m0.8<0,1,0>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* IME search */ mov (1) vme_m0.12<1>:UD SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR:UD {align1}; /* 16x16 Source, harr */ mov (1) vme_m0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 48x40 */ mov (1) vme_m0.0<1>:UD vme_m0.8<0,1,0>:UD {align1}; add (1) vme_m0.0<1>:W vme_m0.0<0,1,0>:W -16:W {align1}; /* Reference = (x-16,y-12)-(x+32,y+28) */ add (1) vme_m0.2<1>:W vme_m0.2<0,1,0>:W -12:W {align1}; mov (1) vme_m0.0<1>:W -16:W {align1}; mov (1) vme_m0.2<1>:W -12:W {align1}; mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; (f0.0) add (1) vme_m0.0<1>:w vme_m0.0<0,1,0>:w 12:w {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; (f0.0) add (1) vme_m0.2<1>:w vme_m0.2<0,1,0>:w 8:w {align1}; add (2) vme_m0.0<1>:w vme_m0.0<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; add (2) vme_m0.4<1>:w vme_m0.4<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; /* the Max MV number is passed by constant buffer */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; mov (1) vme_m1.8<1>:UD START_CENTER + SEARCH_PATH_LEN:UD {align1}; /* Set the MV cost center */ mov (1) vme_m1.16<1>:ud mb_mvp_ref.0<0,1,0>:ud {align1}; mov (1) vme_m1.20<1>:ud mb_mvp_ref.0<0,1,0>:ud {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* M3/M4 search path */ mov (1) vme_msg_3.0<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_3.4<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_3.8<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_3.12<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_3.16<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_3.20<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_3.24<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_3.28<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_4.0<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_4.4<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_4.8<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_4.12<1>:UD 0x000F0F0F:UD {align1}; mov (4) vme_msg_4.16<1>:UD 0x0:UD {align1}; send (8) vme_msg_ind vme_wb<1>:UD null vme( BIND_IDX_VME, 0, 0, VME_IME_MESSAGE_TYPE ) mlen ime_vme_msg_length rlen vme_wb_length {align1}; /* Set Macroblock-shape/mode for FBR */ mov (1) vme_m2.20<1>:UD 0x0:UD {align1}; mov (1) vme_m2.21<1>:UB vme_wb.25<0,1,0>:UB {align1}; mov (1) vme_m2.22<1>:UB vme_wb.26<0,1,0>:UB {align1}; and (1) tmp_reg0.0<1>:UW vme_wb.0<0,1,0>:UW 0x03:UW {align1}; mov (1) vme_m2.20<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* Send FBR message into CRE */ mov (8) vme_msg_3.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) vme_msg_4.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) vme_msg_5.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) vme_msg_6.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; mov (1) vme_m0.12<1>:UD INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER + FBR_BME_DISABLE:UD {align1}; /* 16x16 Source, 1/4 pixel, harr, BME disable */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2.0<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_FBR_MESSAGE_TYPE ) mlen fbr_vme_msg_length rlen vme_wb_length {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; /* write FME info */ mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Inter distortion of FME */ mov (1) msg_reg1.8<1>:UD vme_wb.8<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_m2.20<0,1,0>:UD {align1}; /* bind index 3, write oword (16bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_0, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Write FME/BME MV */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x01:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0.0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) msg_reg2.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) msg_reg3.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) msg_reg4.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; /* bind index 3, write 8 oword (128 bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_8, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 5 rlen obw_wb_length {align1}; /* Write FME/BME RefID */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x08:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb6.0<8,8,1>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Issue message fence so that the previous write message is committed */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_FENCE, OBR_MF_COMMIT, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; nop ; nop ; /* Compare three word data to get the min value */ word_imin: cmp.le.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; cmp.le.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; RETURN {align1}; /* Compare three word data to get the max value */ word_imax: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; cmp.ge.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; RETURN {align1}; word_imedian: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_a_ge_b; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; jmpi (1) cmp_end; cmp_a_ge_b: cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; cmp_end: RETURN {align1}; intel-driver-1.3.0/src/shaders/vme/inter_frame_haswell.g75a000066400000000000000000000000701231401140700236130ustar00rootroot00000000000000#include "vme75.inc" #include "inter_frame_haswell.asm" intel-driver-1.3.0/src/shaders/vme/inter_frame_haswell.g75b000066400000000000000000000377171231401140700236360ustar00rootroot00000000000000 { 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 }, { 0x00000001, 0x24340231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000001, 0x24540231, 0x00000014, 0x00000000 }, { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 }, { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 }, { 0x00000041, 0x24880c21, 0x00000488, 0x00000018 }, { 0x00000001, 0x24940231, 0x00000014, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 }, { 0x04600031, 0x23801cb1, 0x00000800, 0x02190004 }, { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 }, { 0x04600031, 0x23a01cb1, 0x00000800, 0x02290004 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00030003 }, { 0x00000041, 0x24003ca5, 0x00000400, 0x00020002 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 }, { 0x04600031, 0x26001cb1, 0x00000800, 0x02190006 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00030003 }, { 0x00000041, 0x24203ca5, 0x00000420, 0x00020002 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x00070003 }, { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 }, { 0x04600031, 0x26201cb1, 0x00000800, 0x02190006 }, { 0x00600001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a800061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002d28, 0x000000a6, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000740 }, { 0x00600001, 0x2ae00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00600060 }, { 0x00210001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000f0 }, { 0x00000001, 0x2ae000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24003dad, 0x00000400, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x00000018 }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280303 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00210001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2ae40021, 0x00450bc8, 0x00000000 }, { 0x00000001, 0x2af001ed, 0x00000000, 0x00010001 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00100010 }, { 0x00210001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000350 }, { 0x00000001, 0x2b0000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x00000018 }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280303 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00210001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2b040021, 0x00450bf0, 0x00000000 }, { 0x00000001, 0x2b1001ed, 0x00000000, 0x00010001 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00080008 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000110 }, { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff }, { 0x00000040, 0x24003dad, 0x00000400, 0x00010001 }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x00000018 }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280303 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000170 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2b240021, 0x00450bf0, 0x00000000 }, { 0x00000001, 0x2b3001ed, 0x00000000, 0x00010001 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000f0 }, { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00200040, 0x24003dad, 0x00450400, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x00000018 }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280303 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01cb1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2b240021, 0x00450c18, 0x00000000 }, { 0x00000001, 0x2b3001ed, 0x00000000, 0x00010001 }, { 0x00000040, 0x240014a5, 0x00000b00, 0x00000b20 }, { 0x01000010, 0x20001ca4, 0x00000400, 0x00000000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x02000010, 0x20001ca4, 0x00000ae0, 0x00000000 }, { 0x00010001, 0x2b040021, 0x00000ae4, 0x00000000 }, { 0x00010001, 0x2b240021, 0x00000ae4, 0x00000000 }, { 0x00010001, 0x2b140129, 0x00000af4, 0x00000000 }, { 0x00010001, 0x2b340129, 0x00000af4, 0x00000000 }, { 0x00010001, 0x2ac00021, 0x00000ae4, 0x00000000 }, { 0x00110001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000190 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200af4, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000ae4, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b14, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b04, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b34, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b24, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200400, 0x00010001 }, { 0x00010001, 0x2ac00021, 0x00000404, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000c0 }, { 0x00000001, 0x2fa001ad, 0x00000ae4, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b04, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b24, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000850 }, { 0x00000001, 0x2ac001ad, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2fa001ad, 0x00000ae6, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b06, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b26, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000007f0 }, { 0x00000001, 0x2ac201ad, 0x00000fe4, 0x00000000 }, { 0x0020000c, 0x2a803dad, 0x00450ac0, 0x00020002 }, { 0x00200040, 0x2a883dad, 0x00450a80, 0x00030003 }, { 0x00200005, 0x2a902d29, 0x00450a88, 0xfffcfffc }, { 0x00600001, 0x25600021, 0x008d0020, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00000001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00000005, 0x23840c21, 0x00000384, 0xff000000 }, { 0x00600001, 0x28800021, 0x008d0380, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00800001, 0x28a00231, 0x00cf03a3, 0x00000000 }, { 0x00000001, 0x28b00061, 0x00000000, 0x11111111 }, { 0x00000001, 0x28bc0061, 0x00000000, 0x00010101 }, { 0x00000001, 0x28b40129, 0x00000606, 0x00000000 }, { 0x00400001, 0x28d00021, 0x00690608, 0x00000000 }, { 0x00600001, 0x28c00129, 0x00ae0622, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00010001 }, { 0x00000001, 0x28850231, 0x00000400, 0x00000000 }, { 0x00000001, 0x247c0169, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, { 0x00010001, 0x247c00f1, 0x00000000, 0x00000002 }, { 0x00000001, 0x247d0231, 0x000000a5, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00200020 }, { 0x00000001, 0x247e0231, 0x00000400, 0x00000000 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00800000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x0d600031, 0x21801ca1, 0x00000800, 0x0e782000 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 }, { 0x00000001, 0x28300129, 0x0000018c, 0x00000000 }, { 0x00000001, 0x28340021, 0x00000188, 0x00000000 }, { 0x00000001, 0x28380021, 0x0000019c, 0x00000000 }, { 0x00000001, 0x283c0021, 0x00000488, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00200000 }, { 0x00000001, 0x24560169, 0x00000000, 0x28302830 }, { 0x00000001, 0x24400021, 0x00000448, 0x00000000 }, { 0x00000040, 0x24403dad, 0x00000440, 0xfff0fff0 }, { 0x00000040, 0x24423dad, 0x00000442, 0xfff4fff4 }, { 0x00000001, 0x244001ed, 0x00000000, 0xfff0fff0 }, { 0x00000001, 0x244201ed, 0x00000000, 0xfff4fff4 }, { 0x00000001, 0x24440021, 0x00000440, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00600060 }, { 0x00010040, 0x24403dad, 0x00000440, 0x000c000c }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00100010 }, { 0x00010040, 0x24423dad, 0x00000442, 0x00080008 }, { 0x00200040, 0x244035ad, 0x00450440, 0x00450a90 }, { 0x00200040, 0x244435ad, 0x00450444, 0x00450a90 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00000002 }, { 0x00000001, 0x24640231, 0x0000009c, 0x00000000 }, { 0x00000001, 0x24680061, 0x00000000, 0x30003030 }, { 0x00000001, 0x24700021, 0x00000ac0, 0x00000000 }, { 0x00000001, 0x24740021, 0x00000ac0, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 }, { 0x00000001, 0x28600061, 0x00000000, 0x01010101 }, { 0x00000001, 0x28640061, 0x00000000, 0x10010101 }, { 0x00000001, 0x28680061, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x286c0061, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28700061, 0x00000000, 0x01010101 }, { 0x00000001, 0x28740061, 0x00000000, 0x10010101 }, { 0x00000001, 0x28780061, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x287c0061, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28800061, 0x00000000, 0x01010101 }, { 0x00000001, 0x28840061, 0x00000000, 0x10010101 }, { 0x00000001, 0x28880061, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x288c0061, 0x00000000, 0x000f0f0f }, { 0x00400001, 0x28900061, 0x00000000, 0x00000000 }, { 0x08600031, 0x21801ca1, 0x00000800, 0x0a784000 }, { 0x00000001, 0x25740061, 0x00000000, 0x00000000 }, { 0x00000001, 0x25750231, 0x00000199, 0x00000000 }, { 0x00000001, 0x25760231, 0x0000019a, 0x00000000 }, { 0x00000005, 0x24002d29, 0x00000180, 0x00030003 }, { 0x00000001, 0x25740231, 0x00000400, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28a00021, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28c00021, 0x008d0200, 0x00000000 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00243000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 }, { 0x0d600031, 0x21801ca1, 0x00000800, 0x0e786000 }, { 0x00000040, 0x24880c21, 0x00000488, 0x00000002 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000198, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000188, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000574, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0003 }, { 0x00000040, 0x24880c21, 0x00000488, 0x00000001 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x0a0a0403 }, { 0x00000040, 0x24880c21, 0x00000488, 0x00000008 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0240, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x0219e003 }, { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca8, 0x00000e00, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x06000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010001, 0x2f6001ad, 0x00000fa0, 0x00000000 }, { 0x00110001, 0x2f6001ad, 0x00000fa4, 0x00000000 }, { 0x06000010, 0x200035ac, 0x00000f60, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000f60, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010001, 0x2f6001ad, 0x00000fa0, 0x00000000 }, { 0x00110001, 0x2f6001ad, 0x00000fa4, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000f60, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000f60, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000070 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa0, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000a0 }, { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa4, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000060 }, { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa4, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa0, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, intel-driver-1.3.0/src/shaders/vme/inter_frame_ivb.asm000066400000000000000000000550531231401140700227640ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * Authors: Zhao Yakui * */ // Modual name: InterFrame_ivy.asm // // Make inter predition estimation for Inter frame on Ivy // // // Now, begin source code.... // #define SAVE_RET add (1) RETURN_REG<1>:ud ip:ud 32:ud #define RETURN mov (1) ip:ud RETURN_REG<0,1,0>:ud /* * __START */ __INTER_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ; shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1}; mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1}; mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* * Media Read Message -- fetch Luma neighbor edge pixels */ /* ROW */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1}; mov (8) mb_mvp_ref.0<1>:ud 0:ud {align1}; mov (8) mb_ref_win.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1}; (f0.0) jmpi (1) __mb_hwdep_end; /* read back the data for MB A */ /* the layout of MB result is: rx.0(Available). rx.4(MVa), rX.8(MVb), rX.16(Pred_L0 flag), * rX.18 (Pred_L1 flag), rX.20(Forward reference ID), rX.22(Backwared reference ID) */ mov (8) mba_result.0<1>:ud 0x0:ud {align1}; mov (8) mbb_result.0<1>:ud 0x0:ud {align1}; mov (8) mbc_result.0<1>:ud 0x0:ud {align1}; mba_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; /* MB A doesn't exist. Zero MV. mba_flag is zero and ref ID = -1 */ (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; mov (1) mba_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) mb_msg_tmp.8<1>:ud mb_msg0.8<0,1,0>:ud {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; /* bind index 3, read 1 oword (16bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_0, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ and.z.f0.0 (1) null<1>:ud mb_mode_wb.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (-f0.0) jmpi (1) mbb_start; mov (1) mb_msg0.8<1>:UD mb_msg_tmp.8<0,1,0>:ud {align1}; /* Read MV for MB A */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* MV */ mov (2) mba_result.4<1>:ud mb_mv1.8<2,2,1>:ud {align1}; mov (1) mba_result.16<1>:w MB_PRED_FLAG {align1}; mbb_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; /* MB B doesn't exist. Zero MV. mba_flag is zero */ /* If MB B doesn't exist, neither MB C nor D exists */ (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbb_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) mb_msg_tmp.8<1>:ud mb_msg0.8<0,1,0>:ud {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_0, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ and.z.f0.0 (1) null<1>:ud mb_mode_wb.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (-f0.0) jmpi (1) mbc_start; mov (1) mb_msg0.8<1>:UD mb_msg_tmp.8<0,1,0>:ud {align1}; /* Read MV for MB B */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ mov (2) mbb_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1}; mov (1) mbb_result.16<1>:w MB_PRED_FLAG {align1}; mbc_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_C:uw {align1}; /* MB C doesn't exist. Zero MV. mba_flag is zero */ /* Based on h264 spec the MB D will be replaced if MB C doesn't exist */ (f0.0) jmpi (1) mbd_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) mb_msg_tmp.8<1>:ud mb_msg0.8<0,1,0>:ud {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_0, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ and.z.f0.0 (1) null<1>:ud mb_mode_wb.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (-f0.0) jmpi (1) mb_mvp_start; mov (1) mb_msg0.8<1>:UD mb_msg_tmp.8<0,1,0>:ud {align1}; /* Read MV for MB C */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1}; mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1}; jmpi (1) mb_mvp_start; mbd_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_D:uw {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (2) tmp_reg0.0<1>:w tmp_reg0.0<2,2,1>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) mb_msg_tmp.8<1>:ud mb_msg0.8<0,1,0>:ud {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_0, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; and.z.f0.0 (1) null<1>:ud mb_mode_wb.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (-f0.0) jmpi (1) mb_mvp_start; mov (1) mb_msg0.8<1>:UD mb_msg_tmp.8<0,1,0>:ud {align1}; /* Read MV for MB D */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ub NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_8, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 4 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv3.24<2,2,1>:ud {align1}; mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1}; mb_mvp_start: /*TODO: Add the skip prediction */ /* Check whether both MB B and C are invailable */ add (1) tmp_reg0.0<1>:d mbb_result.0<0,1,0>:d mbc_result.0<0,1,0>:d {align1}; cmp.z.f0.0 (1) null:d tmp_reg0.0<0,1,0>:d 0:d {align1}; (-f0.0) jmpi (1) mb_median_start; cmp.nz.f0.0 (1) null:d mba_result.0<0,1,0>:d 0:d {align1}; (f0.0) mov (1) mbb_result.4<1>:ud mba_result.4<0,1,0>:ud {align1}; (f0.0) mov (1) mbc_result.4<1>:ud mba_result.4<0,1,0>:ud {align1}; (f0.0) mov (1) mbb_result.20<1>:uw mba_result.20<0,1,0>:uw {align1}; (f0.0) mov (1) mbc_result.20<1>:uw mba_result.20<0,1,0>:uw {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud mba_result.4<0,1,0>:ud {align1}; (-f0.0) mov (1) mb_mvp_ref.0<1>:ud 0:ud {align1}; jmpi (1) __mb_hwdep_end; mb_median_start: /* check whether only one neighbour MB has the same ref ID with the current MB */ mov (8) tmp_reg0.0<1>:ud 0:ud {align1}; cmp.z.f0.0 (1) null:d mba_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbb_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbc_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.4<0,1,0>:ud {align1}; cmp.e.f0.0 (1) null:d tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud tmp_reg0.4<0,1,0>:ud {align1}; (f0.0) jmpi (1) __mb_hwdep_end; mov (1) INPUT_ARG0.0<1>:w mba_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.4<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.0<1>:w RET_ARG<0,1,0>:w {align1}; mov (1) INPUT_ARG0.0<1>:w mba_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.6<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.2<1>:w RET_ARG<0,1,0>:w {align1}; __mb_hwdep_end: asr (2) mb_ref_win.0<1>:w mb_mvp_ref.0<2,2,1>:w 2:w {align1}; add (2) mb_ref_win.8<1>:w mb_ref_win.0<2,2,1>:w 3:w {align1}; and (2) mb_ref_win.16<1>:uw mb_ref_win.8<2,2,1>:uw 0xFFFC:uw {align1}; /* m2 */ mov (8) vme_msg_2<1>:UD 0x0:UD {align1}; /* m3 */ mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1}; and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1}; mov (8) vme_msg_3<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; /* m4 */ mov (8) vme_msg_4<1>:UD 0x0 {align1}; mov (16) vme_msg_4.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1}; mov (1) vme_msg_4.16<1>:UD INTRA_PREDICTORE_MODE {align1}; /* m1 */ mov (8) vme_m1.0<1>:ud 0x0:ud {align1}; and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1}; (f0.0) mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE:uw {align1}; /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; /* M0 */ /* IME search */ mov (1) vme_m0.12<1>:UD SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER:UD {align1}; /* 16x16 Source, 1/4 pixel, harr */ mov (1) vme_m0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 48x40 */ mov (1) vme_m0.0<1>:UD vme_m0.8<0,1,0>:UD {align1}; mov (1) vme_m0.0<1>:W -16:W {align1}; mov (1) vme_m0.2<1>:W -12:W {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; (f0.0) add (1) vme_m0.0<1>:w vme_m0.0<0,1,0>:w 12:w {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; (f0.0) add (1) vme_m0.2<1>:w vme_m0.2<0,1,0>:w 8:w {align1}; mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; add (2) vme_m0.0<1>:w vme_m0.0<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; add (2) vme_m0.4<1>:w vme_m0.4<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; /* m1 */ mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; /* MV num is passed by constant buffer. R4.28 */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; add (1) vme_m1.4<1>:UD vme_m1.4<0,1,0>:UD FB_PRUNING_DISABLE:UD {align1}; mov (1) vme_m1.8<1>:UD START_CENTER + SEARCH_PATH_LEN:UD {align1}; /* Set the MV cost center */ mov (1) vme_m1.16<1>:ud mb_mvp_ref.0<0,1,0>:ud {align1}; mov (1) vme_m1.20<1>:ud mb_mvp_ref.0<0,1,0>:ud {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; send (8) vme_msg_ind vme_wb null vme( BIND_IDX_VME, 0, 0, VME_MESSAGE_TYPE_MIXED ) mlen vme_msg_length rlen vme_inter_wb_length {align1}; and.z.f0.0 (1) null<1>:ud vme_wb0.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0)jmpi (1) __INTRA_INFO ; __INTER_INFO: /* Write MV pairs */ mov (8) msg_reg0.0<1>:UD obw_m0.0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) msg_reg2.0<1>:UD vme_wb2.0<8,8,1>:UD {align1}; mov (8) msg_reg3.0<1>:UD vme_wb3.0<8,8,1>:UD {align1}; mov (8) msg_reg4.0<1>:UD vme_wb4.0<8,8,1>:UD {align1}; /* bind index 3, write 8 oword (128 bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_8, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 5 rlen obw_wb_length {align1}; mov (1) tmp_uw1<1>:uw 0:uw {align1} ; mov (1) tmp_ud1<1>:ud 0:ud {align1} ; and (1) tmp_uw1<1>:uw vme_wb0.2<0,1,0>:uw MV32_BIT_MASK:uw {align1} ; shr (1) tmp_uw1<1>:uw tmp_uw1<1>:uw MV32_BIT_SHIFT:uw {align1} ; mul (1) tmp_ud1<1>:ud tmp_uw1<0,1,0>:uw 96:uw {align1} ; add (1) tmp_ud1<1>:ud tmp_ud1<0,1,0>:ud 32:uw {align1} ; shl (1) tmp_uw1<1>:uw tmp_uw1<0,1,0>:uw MFC_MV32_BIT_SHIFT:uw {align1} ; add (1) tmp_uw1<1>:uw tmp_uw1<0,1,0>:uw MVSIZE_UW_BASE:uw {align1} ; add (1) tmp_uw1<1>:uw tmp_uw1<0,1,0>:uw CBP_DC_YUV_UW:uw {align1} ; mov (1) msg_reg1.0<1>:uw vme_wb0.0<0,1,0>:uw {align1} ; mov (1) msg_reg1.2<1>:uw tmp_uw1<0,1,0>:uw {align1} ; mov (1) msg_reg1.4<1>:UD vme_wb0.28<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:ud tmp_ud1<0,1,0>:ud {align1} ; mov (1) msg_reg1.12<1>:ud vme_wb0.0<0,1,0>:ud {align1} ; mov (1) msg_reg1.16<1>:ud 0x25:ud {align1} ; jmpi (1) __OUTPUT_INFO; __INTRA_INFO: mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; mov (1) msg_reg1.16<1>:ud 0x35:ud {align1} ; __OUTPUT_INFO: mov (1) msg_reg1.20<1>:ud obw_m0.8<0,1,0>:ud {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; mov (8) msg_reg0.0<1>:ud obw_m0.0<8,8,1>:ud {align1}; /* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Issue message fence so that the previous write message is committed */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_FENCE, OBR_MF_COMMIT, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; nop ; nop ; /* Compare three word data to get the min value */ word_imin: cmp.le.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; cmp.le.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; RETURN {align1}; /* Compare three word data to get the max value */ word_imax: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; cmp.ge.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; RETURN {align1}; word_imedian: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_a_ge_b; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; jmpi (1) cmp_end; cmp_a_ge_b: cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; cmp_end: RETURN {align1}; intel-driver-1.3.0/src/shaders/vme/inter_frame_ivb.g7a000066400000000000000000000000631231401140700226510ustar00rootroot00000000000000#include "vme7.inc" #include "inter_frame_ivb.asm" intel-driver-1.3.0/src/shaders/vme/inter_frame_ivb.g7b000066400000000000000000000332221231401140700226550ustar00rootroot00000000000000 { 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 }, { 0x00000001, 0x24340231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000001, 0x24540231, 0x00000014, 0x00000000 }, { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 }, { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 }, { 0x00000041, 0x24880c21, 0x00000488, 0x0000000a }, { 0x00000001, 0x24940231, 0x00000014, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 }, { 0x04600031, 0x23801cb1, 0x00000800, 0x02190004 }, { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 }, { 0x04600031, 0x23a01cb1, 0x00000800, 0x02290004 }, { 0x00600001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a800061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002d28, 0x000000a6, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000f8 }, { 0x00600001, 0x2ae00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b200061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00600060 }, { 0x00210001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00000001, 0x2ae000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24003dad, 0x00000400, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 }, { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 }, { 0x00310001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2ae40021, 0x00450bc8, 0x00000000 }, { 0x00000001, 0x2af001ed, 0x00000000, 0x00010001 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00100010 }, { 0x00210001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000076 }, { 0x00000001, 0x2b0000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 }, { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 }, { 0x00310001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2b040021, 0x00450bf0, 0x00000000 }, { 0x00000001, 0x2b1001ed, 0x00000000, 0x00010001 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00080008 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff }, { 0x00000040, 0x24003dad, 0x00000400, 0x00010001 }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 }, { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 }, { 0x00310001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000032 }, { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2b240021, 0x00450bf0, 0x00000000 }, { 0x00000001, 0x2b3001ed, 0x00000000, 0x00010001 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000028 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00200040, 0x24003dad, 0x00450400, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 }, { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 }, { 0x00310001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 }, { 0x0a800031, 0x2ba01cb1, 0x00000b40, 0x02480403 }, { 0x00200001, 0x2b240021, 0x00450c18, 0x00000000 }, { 0x00000001, 0x2b3001ed, 0x00000000, 0x00010001 }, { 0x00000040, 0x240014a5, 0x00000b00, 0x00000b20 }, { 0x01000010, 0x20001ca4, 0x00000400, 0x00000000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x02000010, 0x20001ca4, 0x00000ae0, 0x00000000 }, { 0x00010001, 0x2b040021, 0x00000ae4, 0x00000000 }, { 0x00010001, 0x2b240021, 0x00000ae4, 0x00000000 }, { 0x00010001, 0x2b140129, 0x00000af4, 0x00000000 }, { 0x00010001, 0x2b340129, 0x00000af4, 0x00000000 }, { 0x00010001, 0x2ac00021, 0x00000ae4, 0x00000000 }, { 0x00110001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000032 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200af4, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000ae4, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b14, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b04, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b34, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b24, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200400, 0x00010001 }, { 0x00010001, 0x2ac00021, 0x00000404, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x2fa001ad, 0x00000ae4, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b04, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b24, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000bc }, { 0x00000001, 0x2ac001ad, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2fa001ad, 0x00000ae6, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b06, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b26, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x000000b0 }, { 0x00000001, 0x2ac201ad, 0x00000fe4, 0x00000000 }, { 0x0020000c, 0x2a803dad, 0x00450ac0, 0x00020002 }, { 0x00200040, 0x2a883dad, 0x00450a80, 0x00030003 }, { 0x00200005, 0x2a902d29, 0x00450a88, 0xfffcfffc }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00000005, 0x23840c21, 0x00000384, 0xff000000 }, { 0x00600001, 0x28600021, 0x008d0380, 0x00000000 }, { 0x00600001, 0x288000e1, 0x00000000, 0x00000000 }, { 0x00800001, 0x28800231, 0x00cf03a3, 0x00000000 }, { 0x00000001, 0x28900061, 0x00000000, 0x11111111 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, { 0x00010001, 0x247c0171, 0x00000000, 0x00020002 }, { 0x00000001, 0x247d0231, 0x000000a5, 0x00000000 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00203000 }, { 0x00000001, 0x24560169, 0x00000000, 0x28302830 }, { 0x00000001, 0x24400021, 0x00000448, 0x00000000 }, { 0x00000001, 0x244001ed, 0x00000000, 0xfff0fff0 }, { 0x00000001, 0x244201ed, 0x00000000, 0xfff4fff4 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00600060 }, { 0x00010040, 0x24403dad, 0x00000440, 0x000c000c }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00100010 }, { 0x00010040, 0x24423dad, 0x00000442, 0x00080008 }, { 0x00000001, 0x24440021, 0x00000440, 0x00000000 }, { 0x00200040, 0x244035ad, 0x00450440, 0x00450a90 }, { 0x00200040, 0x244435ad, 0x00450444, 0x00450a90 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00000002 }, { 0x00000001, 0x24640231, 0x0000009c, 0x00000000 }, { 0x00000040, 0x24640c21, 0x00000464, 0x00000000 }, { 0x00000001, 0x24680061, 0x00000000, 0x30003030 }, { 0x00000001, 0x24700021, 0x00000ac0, 0x00000000 }, { 0x00000001, 0x24740021, 0x00000ac0, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x08600031, 0x21801cbd, 0x00000800, 0x0a686000 }, { 0x01000005, 0x20000c20, 0x00000180, 0x00002000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x0000002c }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x0a0a0403 }, { 0x00000001, 0x25420169, 0x00000000, 0x00000000 }, { 0x00000001, 0x25440061, 0x00000000, 0x00000000 }, { 0x00000005, 0x25422d29, 0x00000182, 0x00200020 }, { 0x00000008, 0x25422d29, 0x00200542, 0x00050005 }, { 0x00000041, 0x25442d21, 0x00000542, 0x00600060 }, { 0x00000040, 0x25442c21, 0x00000544, 0x00200020 }, { 0x00000009, 0x25422d29, 0x00000542, 0x00050005 }, { 0x00000040, 0x25422d29, 0x00000542, 0x00400040 }, { 0x00000040, 0x25422d29, 0x00000542, 0x000e000e }, { 0x00000001, 0x28200129, 0x00000180, 0x00000000 }, { 0x00000001, 0x28220129, 0x00000542, 0x00000000 }, { 0x00000001, 0x28240021, 0x0000019c, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000544, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28300061, 0x00000000, 0x00000025 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 }, { 0x00000001, 0x28300061, 0x00000000, 0x00000035 }, { 0x00000001, 0x28340021, 0x00000488, 0x00000000 }, { 0x00000040, 0x24880c21, 0x00000488, 0x00000008 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x0219e003 }, { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca8, 0x00000e00, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x06000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010001, 0x2f6001ad, 0x00000fa0, 0x00000000 }, { 0x00110001, 0x2f6001ad, 0x00000fa4, 0x00000000 }, { 0x06000010, 0x200035ac, 0x00000f60, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000f60, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010001, 0x2f6001ad, 0x00000fa0, 0x00000000 }, { 0x00110001, 0x2f6001ad, 0x00000fa4, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000f60, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000f60, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000e }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa0, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa4, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa4, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa0, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, intel-driver-1.3.0/src/shaders/vme/intra_frame.asm000066400000000000000000000161741231401140700221210ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: IntraFrame.asm // // Make intra predition estimation for Intra frame // // // Now, begin source code.... // /* * __START */ __INTRA_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1}; mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1}; mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* * Media Read Message -- fetch neighbor edge pixels */ /* ROW */ __INTRA_LOOP: mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1}; /* * VME message */ /* m0 */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; /* m1 */ mov (1) intra_flag<1>:UW 0x0:UW {align1} ; and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1}; (f0.0) mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE {align1}; cmp.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB 0:UW {align1}; /* X != 0 */ (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_AE {align1}; /* A */ cmp.nz.f0.0 (1) null<1>:UW orig_y_ub<0,1,0>:UB 0:UW {align1}; /* Y != 0 */ (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_B {align1}; /* B */ mul.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB orig_y_ub<0,1,0>:UB {align1}; /* X * Y != 0 */ (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_D {align1}; /* D */ add (1) tmp_x_w<1>:W orig_x_ub<0,1,0>:UB 1:UW {align1}; /* X + 1 */ add (1) tmp_x_w<1>:W w_in_mb_uw<0,1,0>:UW -tmp_x_w<0,1,0>:W {align1}; /* width - (X + 1) */ mul.nz.f0.0 (1) null<1>:UD tmp_x_w<0,1,0>:W orig_y_ub<0,1,0>:UB {align1}; /* (width - (X + 1)) * Y != 0 */ (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_C {align1}; /* C */ and.nz.f0.0 (1) null<1>:UW slice_edge_ub<0,1,0>:UB 2:UW {align1}; (f0.0) and (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB 0xE0 {align1}; /* slice edge disable B,C,D*/ mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* m2 */ mov (8) vme_msg_2<1>:UD 0x0:UD {align1}; /* m3 */ mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1}; and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1}; mov (8) vme_msg_3<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; /* m4 */ mov (8) vme_msg_4<1>:UD 0x0 {align1}; mov (16) vme_msg_4.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1}; mov (1) vme_msg_4.16<1>:UD INTRA_PREDICTORE_MODE {align1}; send (8) vme_msg_ind vme_wb null vme( BIND_IDX_VME, 0, 0, VME_MESSAGE_TYPE_INTRA ) mlen vme_msg_length rlen vme_intra_wb_length {align1}; /* * Oword Block Write message */ mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_0, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D 16:W {align1}; /* X offset: X += 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D 16:W {align1}; /* X offset: X += 16 */ add (1) vme_m0.8<1>:UW vme_m0.8<0,1,0>:UW 16:UW {align1}; /* Y = Y, X += 16 */ add (1) orig_x_ub<1>:ub orig_x_ub<0,1,0>:ub 1:uw {align1} ; cmp.e.f0.0 (1) null<1>:uw w_in_mb_uw<0,1,0>:uw orig_x_ub<0,1,0>:ub {align1}; (f0.0)mov (1) orig_x_ub<1>:ub 0:uw {align1} ; (f0.0)add (1) orig_y_ub<1>:ub orig_y_ub<0,1,0>:ub 1:uw {align1} ; (f0.0)mov (1) read0_header.0<1>:D -8:W {align1}; /* X offset */ (f0.0)add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D 16:W {align1}; /* Y offset */ (f0.0)mov (1) read1_header.0<1>:D -4:W {align1}; /* X offset */ (f0.0)add (1) read1_header.4<1>:D read1_header.4<0,1,0>:D 16:W {align1}; /* Y offset */ /* X = 0, Y += 16 */ (f0.0)mov (1) vme_m0.8<1>:UW 0:UW {align1}; (f0.0)add (1) vme_m0.10<1>:UW vme_m0.10<0,1,0>:UW 16:UW {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 1:uw {align1}; /* the new offset */ add.z.f0.0 (1) num_macroblocks<1>:w num_macroblocks<0,1,0>:w -1:w {align1} ; (-f0.0)jmpi (1) __INTRA_LOOP ; __EXIT: /* * kill thread */ mov (8) msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; intel-driver-1.3.0/src/shaders/vme/intra_frame.g6a000066400000000000000000000000571231401140700220070ustar00rootroot00000000000000#include "vme.inc" #include "intra_frame.asm" intel-driver-1.3.0/src/shaders/vme/intra_frame.g6b000066400000000000000000000074121231401140700220120ustar00rootroot00000000000000 { 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 }, { 0x00000001, 0x24340231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000001, 0x24540231, 0x00000014, 0x00000000 }, { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 }, { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 }, { 0x00000001, 0x24940231, 0x00000014, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 }, { 0x04600031, 0x22401cd1, 0x00000000, 0x02188004 }, { 0x00600001, 0x20000022, 0x008d0420, 0x00000000 }, { 0x04600031, 0x22801cd1, 0x00000000, 0x02288004 }, { 0x00600001, 0x20000022, 0x008d0440, 0x00000000 }, { 0x00000001, 0x247c0169, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, { 0x00010001, 0x247c00f1, 0x00000000, 0x00000002 }, { 0x02000010, 0x20002e28, 0x000000a0, 0x00000000 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000060 }, { 0x02000010, 0x20002e28, 0x000000a1, 0x00000000 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000010 }, { 0x02000041, 0x20004628, 0x000000a0, 0x000000a1 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000004 }, { 0x00000040, 0x25202e2d, 0x000000a0, 0x00010001 }, { 0x00000040, 0x2520352d, 0x000000a2, 0x00004520 }, { 0x02000041, 0x200045a0, 0x00000520, 0x000000a1 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000008 }, { 0x02000005, 0x20002e28, 0x000000a4, 0x00020002 }, { 0x00010005, 0x247d1e31, 0x0000047d, 0x000000e0 }, { 0x00600001, 0x20200022, 0x008d0460, 0x00000000 }, { 0x00600001, 0x20400062, 0x00000000, 0x00000000 }, { 0x00000001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00000005, 0x22440c21, 0x00000244, 0xff000000 }, { 0x00600001, 0x20400022, 0x008d0240, 0x00000000 }, { 0x00600001, 0x206000e2, 0x00000000, 0x00000000 }, { 0x00800001, 0x20600232, 0x00cf0283, 0x00000000 }, { 0x00000001, 0x20700062, 0x00000000, 0x11111111 }, { 0x08600031, 0x21801cdd, 0x00000000, 0x08184000 }, { 0x00600001, 0x20000022, 0x008d0480, 0x00000000 }, { 0x00000001, 0x20200022, 0x00000180, 0x00000000 }, { 0x00000001, 0x20240022, 0x00000190, 0x00000000 }, { 0x00000001, 0x20280022, 0x00000194, 0x00000000 }, { 0x00000001, 0x202c0022, 0x00000198, 0x00000000 }, { 0x05800031, 0x22001cdd, 0x00000000, 0x041b0003 }, { 0x00000040, 0x24003ca5, 0x00000400, 0x00100010 }, { 0x00000040, 0x24203ca5, 0x00000420, 0x00100010 }, { 0x00000040, 0x24482d29, 0x00000448, 0x00100010 }, { 0x00000040, 0x20a02e31, 0x000000a0, 0x00010001 }, { 0x01000010, 0x20004528, 0x000000a2, 0x000000a0 }, { 0x00010001, 0x20a00171, 0x00000000, 0x00000000 }, { 0x00010040, 0x20a12e31, 0x000000a1, 0x00010001 }, { 0x00010001, 0x240001e5, 0x00000000, 0xfff8fff8 }, { 0x00010040, 0x24043ca5, 0x00000404, 0x00100010 }, { 0x00010001, 0x242001e5, 0x00000000, 0xfffcfffc }, { 0x00010040, 0x24243ca5, 0x00000424, 0x00100010 }, { 0x00010001, 0x24480169, 0x00000000, 0x00000000 }, { 0x00010040, 0x244a2d29, 0x0000044a, 0x00100010 }, { 0x00000040, 0x24882c21, 0x00000488, 0x00010001 }, { 0x01000040, 0x20a63dad, 0x000000a6, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffff9a }, { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001cc8, 0x00000000, 0x82000010 }, intel-driver-1.3.0/src/shaders/vme/intra_frame.g7a000066400000000000000000000000571231401140700220100ustar00rootroot00000000000000#include "vme.inc" #include "intra_frame.asm" intel-driver-1.3.0/src/shaders/vme/intra_frame.g7b000066400000000000000000000074121231401140700220130ustar00rootroot00000000000000 { 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 }, { 0x00000001, 0x24340231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000001, 0x24540231, 0x00000014, 0x00000000 }, { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 }, { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 }, { 0x00000001, 0x24940231, 0x00000014, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 }, { 0x04600031, 0x22401cb1, 0x00000800, 0x02190004 }, { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 }, { 0x04600031, 0x22801cb1, 0x00000800, 0x02290004 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x247c0169, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, { 0x00010001, 0x247c00f1, 0x00000000, 0x00000002 }, { 0x02000010, 0x20002e28, 0x000000a0, 0x00000000 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000060 }, { 0x02000010, 0x20002e28, 0x000000a1, 0x00000000 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000010 }, { 0x02000041, 0x20004628, 0x000000a0, 0x000000a1 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000004 }, { 0x00000040, 0x25202e2d, 0x000000a0, 0x00010001 }, { 0x00000040, 0x2520352d, 0x000000a2, 0x00004520 }, { 0x02000041, 0x200045a0, 0x00000520, 0x000000a1 }, { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000008 }, { 0x02000005, 0x20002e28, 0x000000a4, 0x00020002 }, { 0x00010005, 0x247d1e31, 0x0000047d, 0x000000e0 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x22400061, 0x00000000, 0x00000000 }, { 0x00000005, 0x22440c21, 0x00000244, 0xff000000 }, { 0x00600001, 0x28600021, 0x008d0240, 0x00000000 }, { 0x00600001, 0x288000e1, 0x00000000, 0x00000000 }, { 0x00800001, 0x28800231, 0x00cf0283, 0x00000000 }, { 0x00000001, 0x28900061, 0x00000000, 0x11111111 }, { 0x08600031, 0x21801cbd, 0x00000800, 0x0a184000 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0003 }, { 0x00000040, 0x24003ca5, 0x00000400, 0x00100010 }, { 0x00000040, 0x24203ca5, 0x00000420, 0x00100010 }, { 0x00000040, 0x24482d29, 0x00000448, 0x00100010 }, { 0x00000040, 0x20a02e31, 0x000000a0, 0x00010001 }, { 0x01000010, 0x20004528, 0x000000a2, 0x000000a0 }, { 0x00010001, 0x20a00171, 0x00000000, 0x00000000 }, { 0x00010040, 0x20a12e31, 0x000000a1, 0x00010001 }, { 0x00010001, 0x240001e5, 0x00000000, 0xfff8fff8 }, { 0x00010040, 0x24043ca5, 0x00000404, 0x00100010 }, { 0x00010001, 0x242001e5, 0x00000000, 0xfffcfffc }, { 0x00010040, 0x24243ca5, 0x00000424, 0x00100010 }, { 0x00010001, 0x24480169, 0x00000000, 0x00000000 }, { 0x00010040, 0x244a2d29, 0x0000044a, 0x00100010 }, { 0x00000040, 0x24882c21, 0x00000488, 0x00010001 }, { 0x01000040, 0x20a63dad, 0x000000a6, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0xffffff9a }, { 0x00600001, 0x28000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca8, 0x00000800, 0x82000010 }, intel-driver-1.3.0/src/shaders/vme/intra_frame_gen8.asm000066400000000000000000000154761231401140700230460ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: IntraFrame_gen8.asm // // Make intra predition estimation for Intra frame on Gen8 // // // Now, begin source code.... // /* * __START */ __INTRA_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ; shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1}; mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1}; mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* * Media Read Message -- fetch Luma neighbor edge pixels */ /* ROW */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1}; /* * Media Read Message -- fetch Chroma neighbor edge pixels */ /* ROW */ shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16 , y * 8 */ mul (1) read0_header.0<1>:D read0_header.0<0,1,0>:D 2:W {align1}; add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind CHROMA_ROW<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16, y * 8 */ mul (1) read1_header.0<1>:D read1_header.0<0,1,0>:D 2:W {align1}; add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_8X4 {align1}; mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind CHROMA_COL<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1}; /* m2, get the MV/Mb cost passed by constant buffer when creating EU thread by MEDIA_OBJECT */ mov (8) vme_msg_2<1>:UD r1.0<8,8,1>:UD {align1}; /* m3. This is changed for FWD/BWD cost center */ mov (8) vme_msg_3<1>:UD 0x0:UD {align1}; /* m4.*/ mov (8) vme_msg_4<1>:ud 0x0:ud {align1}; /* m5 */ mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1}; and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1}; mov (8) vme_msg_5<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; mov (1) tmp_reg0.0<1>:UW LUMA_CHROMA_MODE:UW {align1}; /* Use the Luma mode */ mov (1) vme_msg_5.5<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* m6 */ mov (8) vme_msg_6<1>:UD 0x0:UD {align1}; mov (16) vme_msg_6.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1}; mov (1) vme_msg_6.16<1>:UD INTRA_PREDICTORE_MODE {align1}; /* the penalty for Intra mode */ mov (1) vme_msg_6.28<1>:UD 0x010101:UD {align1}; mov (1) vme_msg_6.20<1>:UW CHROMA_ROW.6<0,1,0>:UW {align1}; /* m7 */ mov (4) vme_msg_7.16<1>:UD CHROMA_ROW.8<4,4,1>:UD {align1}; mov (8) vme_msg_7.0<1>:UW CHROMA_COL.2<16,8,2>:UW {align1}; /* * VME message */ /* m1 */ mov (1) intra_flag<1>:UW 0x0:UW {align1} ; and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1}; (f0.0) mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE {align1}; /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; /* Disable DC HAAR component when calculating HARR SATD block */ mov (1) tmp_reg0.0<1>:UW DC_HARR_DISABLE:UW {align1}; mov (1) vme_m1.30<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* m0 */ /* 16x16 Source, Intra_harr */ add (1) vme_m0.12<1>:UD vme_m0.12<0,1,0>:ud INTRA_SAD_HAAR:UD {align1}; mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_SIC_MESSAGE_TYPE ) mlen sic_vme_msg_length rlen vme_wb_length {align1}; /* * Oword Block Write message */ mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Distortion, Intra (17-16), */ mov (1) msg_reg1.16<1>:UW vme_wb.12<0,1,0>:UW {align1}; mov (1) msg_reg1.20<1>:UD vme_wb.8<0,1,0>:UD {align1}; /* VME clock counts */ mov (1) msg_reg1.24<1>:UD vme_wb.28<0,1,0>:UD {align1}; mov (1) msg_reg1.28<1>:UD obw_m0.8<0,1,0>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; intel-driver-1.3.0/src/shaders/vme/intra_frame_gen8.g8a000066400000000000000000000000641231401140700227300ustar00rootroot00000000000000#include "vme8.inc" #include "intra_frame_gen8.asm" intel-driver-1.3.0/src/shaders/vme/intra_frame_gen8.g8b000066400000000000000000000075701231401140700227420ustar00rootroot00000000000000 { 0x00800001, 0x24000608, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400608, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800608, 0x00000000, 0x00000000 }, { 0x00800001, 0x24c00608, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002228, 0x164500a0, 0x00040004 }, { 0x00000040, 0x24000a28, 0x1e000400, 0xfff8fff8 }, { 0x00000040, 0x24040a28, 0x1e000404, 0xffffffff }, { 0x00000001, 0x24080e08, 0x08000000, 0x0000001f }, { 0x00000001, 0x24142288, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202228, 0x164500a0, 0x00040004 }, { 0x00000040, 0x24200a28, 0x1e000420, 0xfffcfffc }, { 0x00000001, 0x24280e08, 0x08000000, 0x000f0003 }, { 0x00000001, 0x24342288, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482248, 0x164500a0, 0x00040004 }, { 0x00000001, 0x24542288, 0x00000014, 0x00000000 }, { 0x00000041, 0x24881208, 0x220000a2, 0x000000a1 }, { 0x00000040, 0x24880208, 0x22000488, 0x000000a0 }, { 0x00000041, 0x24880208, 0x06000488, 0x00000002 }, { 0x00000001, 0x24942288, 0x00000014, 0x00000000 }, { 0x00600001, 0x28000208, 0x008d0400, 0x00000000 }, { 0x04600031, 0x23800a88, 0x0e000800, 0x02190004 }, { 0x00600001, 0x28000208, 0x008d0420, 0x00000000 }, { 0x04600031, 0x23a00a88, 0x0e000800, 0x02290004 }, { 0x00200009, 0x24002228, 0x164500a0, 0x00030003 }, { 0x00000041, 0x24000a28, 0x1e000400, 0x00020002 }, { 0x00000040, 0x24000a28, 0x1e000400, 0xfff8fff8 }, { 0x00000040, 0x24040a28, 0x1e000404, 0xffffffff }, { 0x00600001, 0x28000208, 0x008d0400, 0x00000000 }, { 0x04600031, 0x26000a88, 0x0e000800, 0x02190006 }, { 0x00200009, 0x24202228, 0x164500a0, 0x00030003 }, { 0x00000041, 0x24200a28, 0x1e000420, 0x00020002 }, { 0x00000040, 0x24200a28, 0x1e000420, 0xfffcfffc }, { 0x00000001, 0x24280e08, 0x08000000, 0x00070003 }, { 0x00600001, 0x28000208, 0x008d0420, 0x00000000 }, { 0x04600031, 0x26200a88, 0x0e000800, 0x02190006 }, { 0x00600001, 0x28400208, 0x008d0020, 0x00000000 }, { 0x00600001, 0x28600608, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800608, 0x00000000, 0x00000000 }, { 0x00000001, 0x23800608, 0x00000000, 0x00000000 }, { 0x00000005, 0x23840208, 0x06000384, 0xff000000 }, { 0x00600001, 0x28a00208, 0x008d0380, 0x00000000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00000000 }, { 0x00000001, 0x28a52288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28c00608, 0x00000000, 0x00000000 }, { 0x00800001, 0x28c02288, 0x00cf03a3, 0x00000000 }, { 0x00000001, 0x28d00608, 0x00000000, 0x11111111 }, { 0x00000001, 0x28dc0608, 0x00000000, 0x00010101 }, { 0x00000001, 0x28d41248, 0x00000606, 0x00000000 }, { 0x00400001, 0x28f00208, 0x00690608, 0x00000000 }, { 0x00600001, 0x28e01248, 0x00ae0622, 0x00000000 }, { 0x00000001, 0x247c1648, 0x10000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a4, 0x00010001 }, { 0x00010001, 0x247c0e88, 0x08000000, 0x00000002 }, { 0x00000001, 0x247d2288, 0x000000a5, 0x00000000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00200020 }, { 0x00000001, 0x247e2288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x00000040, 0x244c0208, 0x0600044c, 0x00800000 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x0d600031, 0x21800a08, 0x0e000800, 0x10782000 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200208, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240208, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280208, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0208, 0x00000198, 0x00000000 }, { 0x00000001, 0x28301248, 0x0000018c, 0x00000000 }, { 0x00000001, 0x28340208, 0x00000188, 0x00000000 }, { 0x00000001, 0x28380208, 0x0000019c, 0x00000000 }, { 0x00000001, 0x283c0208, 0x00000488, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x040a0203 }, { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24000a40, 0x0e000e00, 0x82000010 }, intel-driver-1.3.0/src/shaders/vme/intra_frame_haswell.asm000066400000000000000000000152261231401140700236350ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: IntraFrame.asm // // Make intra predition estimation for Intra frame // // // Now, begin source code.... // /* * __START */ __INTRA_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ; shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1}; mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1}; mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* * Media Read Message -- fetch Luma neighbor edge pixels */ /* ROW */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1}; /* * Media Read Message -- fetch Chroma neighbor edge pixels */ /* ROW */ shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16 , y * 8 */ mul (1) read0_header.0<1>:D read0_header.0<0,1,0>:D 2:W {align1}; add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind CHROMA_ROW<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16, y * 8 */ mul (1) read1_header.0<1>:D read1_header.0<0,1,0>:D 2:W {align1}; add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_8X4 {align1}; mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind CHROMA_COL<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1}; /* m2, get the MV/Mb cost passed by constant buffer when creating EU thread by MEDIA_OBJECT */ mov (8) vme_msg_2<1>:UD r1.0<8,8,1>:UD {align1}; /* m3 */ mov (8) vme_msg_3<1>:UD 0x0:UD {align1}; /* m4 */ mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1}; and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1}; mov (8) vme_msg_4<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; /* m5 */ mov (8) vme_msg_5<1>:UD 0x0:UD {align1}; mov (16) vme_msg_5.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1}; mov (1) vme_msg_5.16<1>:UD INTRA_PREDICTORE_MODE {align1}; /* the penalty for Intra mode */ mov (1) vme_msg_5.28<1>:UD 0x010101:UD {align1}; mov (1) vme_msg_5.20<1>:UW CHROMA_ROW.6<0,1,0>:UW {align1}; /* m6 */ mov (4) vme_msg_6.16<1>:UD CHROMA_ROW.8<4,4,1>:UD {align1}; mov (8) vme_msg_6.0<1>:UW CHROMA_COL.2<16,8,2>:UW {align1}; /* * VME message */ /* m0 */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (1) tmp_reg0.0<1>:UW LUMA_CHROMA_MODE:UW {align1}; /* Use the Luma mode */ mov (1) vme_msg_4.5<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* m1 */ mov (1) intra_flag<1>:UW 0x0:UW {align1} ; and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1}; (f0.0) mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE {align1}; /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; /* Disable DC HAAR component when calculating HARR SATD block */ mov (1) tmp_reg0.0<1>:UW DC_HARR_DISABLE:UW {align1}; mov (1) vme_m1.30<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* m0 */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_SIC_MESSAGE_TYPE ) mlen sic_vme_msg_length rlen vme_wb_length {align1}; /* * Oword Block Write message */ mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Distortion, Intra (17-16), */ mov (1) msg_reg1.16<1>:UW vme_wb.12<0,1,0>:UW {align1}; mov (1) msg_reg1.20<1>:UD vme_wb.8<0,1,0>:UD {align1}; /* VME clock counts */ mov (1) msg_reg1.24<1>:UD vme_wb.28<0,1,0>:UD {align1}; mov (1) msg_reg1.28<1>:UD obw_m0.8<0,1,0>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; intel-driver-1.3.0/src/shaders/vme/intra_frame_haswell.g75a000066400000000000000000000000701231401140700236070ustar00rootroot00000000000000#include "vme75.inc" #include "intra_frame_haswell.asm" intel-driver-1.3.0/src/shaders/vme/intra_frame_haswell.g75b000066400000000000000000000075011231401140700236160ustar00rootroot00000000000000 { 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 }, { 0x00000001, 0x24340231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000001, 0x24540231, 0x00000014, 0x00000000 }, { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 }, { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 }, { 0x00000041, 0x24880c21, 0x00000488, 0x00000002 }, { 0x00000001, 0x24940231, 0x00000014, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 }, { 0x04600031, 0x23801cb1, 0x00000800, 0x02190004 }, { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 }, { 0x04600031, 0x23a01cb1, 0x00000800, 0x02290004 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00030003 }, { 0x00000041, 0x24003ca5, 0x00000400, 0x00020002 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 }, { 0x04600031, 0x26001cb1, 0x00000800, 0x02190006 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00030003 }, { 0x00000041, 0x24203ca5, 0x00000420, 0x00020002 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x00070003 }, { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 }, { 0x04600031, 0x26201cb1, 0x00000800, 0x02190006 }, { 0x00600001, 0x28400021, 0x008d0020, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00000001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00000005, 0x23840c21, 0x00000384, 0xff000000 }, { 0x00600001, 0x28800021, 0x008d0380, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00800001, 0x28a00231, 0x00cf03a3, 0x00000000 }, { 0x00000001, 0x28b00061, 0x00000000, 0x11111111 }, { 0x00000001, 0x28bc0061, 0x00000000, 0x00010101 }, { 0x00000001, 0x28b40129, 0x00000606, 0x00000000 }, { 0x00400001, 0x28d00021, 0x00690608, 0x00000000 }, { 0x00600001, 0x28c00129, 0x00ae0622, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00000000 }, { 0x00000001, 0x28850231, 0x00000400, 0x00000000 }, { 0x00000001, 0x247c0169, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, { 0x00010001, 0x247c00f1, 0x00000000, 0x00000002 }, { 0x00000001, 0x247d0231, 0x000000a5, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00200020 }, { 0x00000001, 0x247e0231, 0x00000400, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x0d600031, 0x21801ca1, 0x00000800, 0x0e782000 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 }, { 0x00000001, 0x28300129, 0x0000018c, 0x00000000 }, { 0x00000001, 0x28340021, 0x00000188, 0x00000000 }, { 0x00000001, 0x28380021, 0x0000019c, 0x00000000 }, { 0x00000001, 0x283c0021, 0x00000488, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca8, 0x00000e00, 0x82000010 }, intel-driver-1.3.0/src/shaders/vme/intra_frame_ivb.asm000066400000000000000000000110101231401140700227410ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: IntraFrame.asm // // Make intra predition estimation for Intra frame // // // Now, begin source code.... // /* * __START */ __INTRA_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ; shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */ add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */ mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1}; mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */ mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1}; mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* * Media Read Message -- fetch Luma neighbor edge pixels */ /* ROW */ mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1}; /* COL */ mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1}; send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1}; /* m0 */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; /* m2 */ mov (8) vme_msg_2<1>:UD 0x0:UD {align1}; /* * VME message */ /* m0 */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; /* m1 */ mov (8) vme_m1.0<1>:ud 0x0:ud {align1}; and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1}; (f0.0) mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE:uw {align1}; /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* m2 */ mov (8) vme_msg_2<1>:UD 0x0:UD {align1}; /* m3 */ mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1}; and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1}; mov (8) vme_msg_3<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; /* m4 */ mov (8) vme_msg_4<1>:UD 0x0 {align1}; mov (16) vme_msg_4.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1}; mov (1) vme_msg_4.16<1>:UD INTRA_PREDICTORE_MODE {align1}; send (8) vme_msg_ind vme_wb null vme( BIND_IDX_VME, 0, 0, VME_MESSAGE_TYPE_INTRA ) mlen vme_msg_length rlen vme_intra_wb_length {align1}; /* * Oword Block Write message */ mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_0, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; intel-driver-1.3.0/src/shaders/vme/intra_frame_ivb.g7a000066400000000000000000000000641231401140700226460ustar00rootroot00000000000000#include "vme7.inc" #include "intra_frame_ivb.asm" intel-driver-1.3.0/src/shaders/vme/intra_frame_ivb.g7b000066400000000000000000000047421231401140700226560ustar00rootroot00000000000000 { 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 }, { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff }, { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 }, { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc }, { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 }, { 0x00000001, 0x24340231, 0x00000014, 0x00000000 }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000001, 0x24540231, 0x00000014, 0x00000000 }, { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 }, { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 }, { 0x00000001, 0x24940231, 0x00000014, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 }, { 0x04600031, 0x23801cb1, 0x00000800, 0x02190004 }, { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 }, { 0x04600031, 0x23a01cb1, 0x00000800, 0x02290004 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 }, { 0x00010001, 0x247c0171, 0x00000000, 0x00020002 }, { 0x00000001, 0x247d0231, 0x000000a5, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00000001, 0x23800061, 0x00000000, 0x00000000 }, { 0x00000005, 0x23840c21, 0x00000384, 0xff000000 }, { 0x00600001, 0x28600021, 0x008d0380, 0x00000000 }, { 0x00600001, 0x288000e1, 0x00000000, 0x00000000 }, { 0x00800001, 0x28800231, 0x00cf03a3, 0x00000000 }, { 0x00000001, 0x28900061, 0x00000000, 0x11111111 }, { 0x08600031, 0x21801cbd, 0x00000800, 0x0a184000 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0003 }, { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca8, 0x00000e00, 0x82000010 }, intel-driver-1.3.0/src/shaders/vme/mpeg2_inter_gen8.asm000066400000000000000000000740261231401140700227660ustar00rootroot00000000000000/* * Copyright © <2013>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: mpeg2_inter_gen8.asm // // Make inter predition estimation for MPEG2 Inter-frame on gen8 // // // Now, begin source code.... // #define SAVE_RET add (1) RETURN_REG<1>:ud ip:ud 32:ud #define RETURN mov (1) ip:ud RETURN_REG<0,1,0>:ud /* * __START */ __INTER_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ; shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 24:UD {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) pic_ref.0<1>:uw r4.24<2,2,1>:uw 4:uw {align1}; mov (2) pic_ref.16<1>:uw r4.20<2,2,1>:uw {align1}; mov (8) mb_mvp_ref.0<1>:ud 0:ud {align1}; mov (8) mb_ref_win.0<1>:ud 0:ud {align1}; mov (8) mba_result.0<1>:ud 0x0:ud {align1}; mov (8) mbb_result.0<1>:ud 0x0:ud {align1}; mov (8) mbc_result.0<1>:ud 0x0:ud {align1}; and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1}; (f0.0) jmpi (1) __mb_hwdep_end; /* read back the data for MB A */ /* the layout of MB result is: rx.0(Available). rx.4(MVa), rX.8(MVb), rX.16(Pred_L0 flag), * rX.18 (Pred_L1 flag), rX.20(Forward reference ID), rX.22(Backwared reference ID) */ mba_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; /* MB A doesn't exist. Zero MV. mba_flag is zero and ref ID = -1 */ (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; mov (1) mba_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB A */ /* bind index 3, read 2 oword (32 bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ /* MV */ mov (2) mba_result.4<1>:ud mb_mv0.0<2,2,1>:ud {align1}; mov (1) mba_result.16<1>:w MB_PRED_FLAG {align1}; mbb_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; /* MB B doesn't exist. Zero MV. mba_flag is zero */ /* If MB B doesn't exist, neither MB C nor D exists */ (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbb_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbc_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB B */ /* bind index 3, read 2 oword (32bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ mov (2) mbb_result.4<1>:ud mb_mv0.0<2,2,1>:ud {align1}; mov (1) mbb_result.16<1>:w MB_PRED_FLAG {align1}; mbc_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_C:uw {align1}; /* MB C doesn't exist. Zero MV. mba_flag is zero */ /* Based on h264 spec the MB D will be replaced if MB C doesn't exist */ (f0.0) jmpi (1) mbd_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB C */ /* bind index 3, read 2 oword (32bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv0.0<2,2,1>:ud {align1}; mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1}; jmpi (1) mb_mvp_start; mbd_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_D:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (2) tmp_reg0.0<1>:w tmp_reg0.0<2,2,1>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB D */ /* bind index 3, read 2 oword (32bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ub NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv0.0<2,2,1>:ud {align1}; mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1}; mb_mvp_start: /*TODO: Add the skip prediction */ /* Check whether both MB B and C are inavailable */ add (1) tmp_reg0.0<1>:d mbb_result.0<0,1,0>:d mbc_result.0<0,1,0>:d {align1}; cmp.z.f0.0 (1) null:d tmp_reg0.0<0,1,0>:d 0:d {align1}; (-f0.0) jmpi (1) mb_median_start; cmp.nz.f0.0 (1) null:d mba_result.0<0,1,0>:d 0:d {align1}; (f0.0) mov (1) mbb_result.4<1>:ud mba_result.4<0,1,0>:ud {align1}; (f0.0) mov (1) mbc_result.4<1>:ud mba_result.4<0,1,0>:ud {align1}; (f0.0) mov (1) mbb_result.20<1>:uw mba_result.20<0,1,0>:uw {align1}; (f0.0) mov (1) mbc_result.20<1>:uw mba_result.20<0,1,0>:uw {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud mba_result.4<0,1,0>:ud {align1}; (-f0.0) mov (1) mb_mvp_ref.0<1>:ud 0:ud {align1}; jmpi (1) __mb_hwdep_end; mb_median_start: /* check whether only one neighbour MB has the same ref ID with the current MB */ mov (8) tmp_reg0.0<1>:ud 0:ud {align1}; cmp.z.f0.0 (1) null:d mba_result.20<0,1,0>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbb_result.20<0,1,0>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbc_result.20<0,1,0>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.4<0,1,0>:ud {align1}; cmp.e.f0.0 (1) null:d tmp_reg0.0<0,1,0>:w 1:w {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud tmp_reg0.4<0,1,0>:ud {align1}; (f0.0) jmpi (1) __mb_hwdep_end; mov (1) INPUT_ARG0.0<1>:w mba_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.4<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.0<1>:w RET_ARG<0,1,0>:w {align1}; mov (1) INPUT_ARG0.0<1>:w mba_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.6<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.2<1>:w RET_ARG<0,1,0>:w {align1}; __mb_hwdep_end: mov (2) mv_cc_ref.0<1>:w mba_result.4<2,2,1>:w {align1}; /* Calibrate the ref window for MPEG2 */ mov (1) vme_m0.0<1>:W -16:W {align1}; mov (1) vme_m0.2<1>:W -12:W {align1}; mov (1) INPUT_ARG0.0<1>:ud vme_m0.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud vme_m0.8<0,1,0>:ud {align1}; mov (8) INPUT_ARG1.0<1>:ud pic_ref.0<8,8,1>:ud {align1}; SAVE_RET {align1}; jmpi (1) ref_boundary_check; mov (2) vme_m0.0<1>:w RET_ARG<2,2,1>:w {align1}; /* m2, get the MV/Mb cost passed from constant buffer when spawning thread by MEDIA_OBJECT */ mov (8) vme_m2<1>:UD r1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* m3 FWD/BWD cost center*/ mov (8) vme_msg_3<1>:UD 0x0:UD {align1}; /* m4 skip center*/ mov (8) vme_msg_4<1>:UD 0x0:UD {align1}; /* m5 */ mov (8) vme_msg_5<1>:UD 0x0:UD {align1}; /* Use the Luma mode */ mov (1) tmp_reg0.0<1>:UW LUMA_INTRA_MODE:UW {align1}; mov (1) vme_msg_5.5<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; mov (1) tmp_reg0.0<1>:UW INTRA16_DC_PRED:UW {align1}; mov (1) vme_msg_5.4<1>:ub tmp_reg0.0<0,1,0>:UB {align1}; /* m6 */ mov (8) vme_msg_6<1>:UD 0x0:UD {align1}; mov (1) vme_msg_6.16<1>:UD INTRA_PREDICTORE_MODE {align1}; /* the penalty for Intra mode */ mov (1) vme_msg_6.28<1>:UD 0x010101:UD {align1}; /* m7 */ mov (8) vme_msg_7.0<1>:ud 0x0:ud {align1}; /* * SIC VME message */ /* Disable Intra8x8/Intra4x4 Intra-prediction */ /* m1 */ mov (8) vme_m1.0<1>:ud 0x0:UD {align1}; mov (1) intra_flag<1>:UW 0x0:UW {align1} ; mov (1) tmp_reg0.0<1>:uw LUMA_INTRA_8x8_DISABLE:uw {align1}; add (1) tmp_reg0.0<1>:uw tmp_reg0.0<0,1,0>:uw LUMA_INTRA_4x4_DISABLE:uw {align1}; mov (1) intra_part_mask_ub<1>:UB tmp_reg0.0<0,1,0>:ub {align1}; /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; /* Enable DC HAAR component when calculating HARR SATD block */ mov (1) tmp_reg0.0<1>:UW DC_HARR_ENABLE:UW {align1}; mov (1) vme_m1.30<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* m0 */ mov (1) vme_m0.12<1>:UD INTRA_SAD_HAAR:UD {align1}; /* 16x16 Source, Intra_harr */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_SIC_MESSAGE_TYPE ) mlen sic_vme_msg_length rlen vme_wb_length {align1}; /* * Oword Block Write message */ mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Distortion, Intra (17-16), */ mov (1) msg_reg1.16<1>:UW vme_wb.12<0,1,0>:UW {align1}; mov (1) msg_reg1.20<1>:UD vme_wb.8<0,1,0>:UD {align1}; /* VME clock counts */ mov (1) msg_reg1.24<1>:UD vme_wb.28<0,1,0>:UD {align1}; mov (1) msg_reg1.28<1>:UD obw_m0.8<0,1,0>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* IME search */ mov (1) vme_m0.12<1>:UD SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR:UD {align1}; /* 16x16 Source, harr */ mov (1) vme_m0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 48x40 */ mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; /* the Max MV number is passed by constant buffer */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; mov (1) vme_m1.8<1>:UD START_CENTER + SEARCH_PATH_LEN:UD {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* Setup the Cost center */ /* currently four 8x8 share the same cost center */ mov (4) vme_m3.0<2>:ud mv_cc_ref.0<0,1,0>:ud {align1}; mov (4) vme_m3.4<2>:ud mv_cc_ref.0<0,1,0>:ud {align1}; mov (8) vme_msg_3<1>:UD vme_m3.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* M4/M5 search path */ mov (1) vme_msg_4.0<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_4.4<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_4.8<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_4.12<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_4.16<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_4.20<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_4.24<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_4.28<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_5.0<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_5.4<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_5.8<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_5.12<1>:UD 0x000F0F0F:UD {align1}; mov (4) vme_msg_5.16<1>:UD 0x0:UD {align1}; send (8) vme_msg_ind vme_wb<1>:UD null vme( BIND_IDX_VME, 0, 0, VME_IME_MESSAGE_TYPE ) mlen ime_vme_msg_length rlen vme_wb_length {align1}; /* Set Macroblock-shape/mode for FBR */ mov (1) vme_m2.20<1>:UD 0x0:UD {align1}; mov (1) vme_m2.21<1>:UB vme_wb.25<0,1,0>:UB {align1}; mov (1) vme_m2.22<1>:UB vme_wb.26<0,1,0>:UB {align1}; and (1) tmp_reg0.0<1>:UW vme_wb.0<0,1,0>:UW 0x03:UW {align1}; mov (1) vme_m2.20<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* Send FBR message into CRE */ mov (8) vme_msg_4.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) vme_msg_5.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) vme_msg_6.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) vme_msg_7.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; mov (1) vme_m0.12<1>:UD INTER_SAD_HAAR + SUB_PEL_MODE_HALF + FBR_BME_DISABLE:UD {align1}; /* 16x16 Source, 1/2 pixel, harr, BME disable */ /* Bilinear filter */ mov (1) tmp_reg0.0<1>:uw 0x04:uw {align1}; add (1) vme_m1.30<1>:ub vme_m1.30<0,1,0>:ub tmp_reg0.0<0,1,0>:ub {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2.0<1>:UD vme_m2.0<8,8,1>:UD {align1}; mov (8) vme_msg_3.0<1>:UD vme_m3.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_FBR_MESSAGE_TYPE ) mlen fbr_vme_msg_length rlen vme_wb_length {align1}; and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1}; (-f0.0) jmpi (1) vme_run_again; nop; vme_mv_output: add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; /* write FME info */ mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Inter distortion of FME */ mov (1) msg_reg1.8<1>:UD vme_wb.8<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_m2.20<0,1,0>:UD {align1}; /* bind index 3, write oword (16bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_0, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Write FME/BME MV */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x01:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0.0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) msg_reg2.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) msg_reg3.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) msg_reg4.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; /* bind index 3, write 2 oword (32 bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Write FME/BME RefID */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x08:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb6.0<8,8,1>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Issue message fence so that the previous write message is committed */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_FENCE, OBR_MF_COMMIT, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; nop ; nop ; word_imedian: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_a_ge_b; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; jmpi (1) cmp_end; cmp_a_ge_b: cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; cmp_end: RETURN {align1}; nop; nop; ref_boundary_check: /* The left/up coordinate of reference window */ add (2) TEMP_VAR0.0<1>:w INPUT_ARG0.8<2,2,1>:w INPUT_ARG0.0<2,2,1>:w {align1}; /* The right/bottom coordinate of reference window */ add (1) TEMP_VAR0.16<1>:w TEMP_VAR0.0<0,1,0>:w 48:w {align1}; add (1) TEMP_VAR0.18<1>:w TEMP_VAR0.2<0,1,0>:w 40:w {align1}; /* Firstly the MV range is checked */ mul (2) TEMP_VAR1.16<1>:w INPUT_ARG1.16<2,2,1>:w -1:w {align1}; add (2) TEMP_VAR1.0<1>:w INPUT_ARG0.8<2,2,1>:w TEMP_VAR1.16<2,2,1>:w {align1}; add (2) TEMP_VAR1.4<1>:w INPUT_ARG0.8<2,2,1>:w INPUT_ARG1.16<2,2,1>:w {align1}; cmp.l.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w TEMP_VAR1.0<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w TEMP_VAR1.0<0,1,0>:w {align1}; cmp.g.f0.0 (1) null:w TEMP_VAR0.16<0,1,0>:w TEMP_VAR1.4<0,1,0>:w {align1}; (f0.0) add (1) TEMP_VAR0.0<1>:w TEMP_VAR1.4<0,1,0>:w -48:w {align1}; cmp.l.f0.0 (1) null:w TEMP_VAR0.2<0,1,0>:w TEMP_VAR1.2<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.2<1>:w TEMP_VAR1.2<0,1,0>:w {align1}; cmp.g.f0.0 (1) null:w TEMP_VAR0.18<0,1,0>:w TEMP_VAR1.6<0,1,0>:w {align1}; (f0.0) add (1) TEMP_VAR0.2<1>:w TEMP_VAR1.6<0,1,0>:w -40:w {align1}; x_left_cmp: cmp.l.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w 0:w {align1}; (-f0.0) jmpi (1) x_right_cmp; (f0.0) mov (1) TEMP_VAR0.0<1>:w 0:w {align1}; jmpi (1) y_top_cmp; x_right_cmp: cmp.g.f0.0 (1) null:w TEMP_VAR0.16<0,1,0>:w INPUT_ARG1.0<0,1,0>:w {align1}; (-f0.0) jmpi (1) y_top_cmp; (f0.0) add (1) TEMP_VAR0.0<1>:w INPUT_ARG1.0<0,1,0>:w -48:w {align1}; y_top_cmp: cmp.l.f0.0 (1) null:w TEMP_VAR0.2<0,1,0>:w 0:w {align1}; (-f0.0) jmpi (1) y_bottom_cmp; (f0.0) mov (1) TEMP_VAR0.2<1>:w 0:w {align1}; jmpi (1) y_bottom_end; y_bottom_cmp: cmp.g.f0.0 (1) null:w TEMP_VAR0.18<0,1,0>:w INPUT_ARG1.2<0,1,0>:w {align1}; (f0.0) add (1) TEMP_VAR0.2<1>:w INPUT_ARG1.2<0,1,0>:w -40:w {align1}; y_bottom_end: mul (2) TEMP_VAR1.0<1>:w INPUT_ARG0.8<2,2,1>:w -1:w {align1}; add (2) RET_ARG<1>:w TEMP_VAR0.0<2,2,1>:w TEMP_VAR1.0<2,2,1>:w {align1}; RETURN {align1}; nop; nop; vme_run_again: asr (2) mb_ref_win.0<1>:w mb_mvp_ref.0<2,2,1>:w 2:w {align1}; mov (2) tmp_reg0.0<1>:w mb_ref_win.0<2,2,1>:w {align1}; add (2) mb_ref_win.8<1>:w mb_ref_win.0<2,2,1>:w 3:w {align1}; and (2) mb_ref_win.16<1>:uw mb_ref_win.8<2,2,1>:uw 0xFFFC:uw {align1}; cmp.l.f0.0 (1) null:w tmp_reg0.0<0,1,0>:w 0:w {align1}; (f0.0) mul (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1}; cmp.l.f0.0 (1) null:w tmp_reg0.2<0,1,0>:w 0:w {align1}; (f0.0) mul (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; cmp.ge.f0.0 (1) null:w tmp_reg0.0<0,1,0>:w 4:w {align1}; (f0.0) jmpi (1) vme_start; cmp.ge.f0.0 (1) null:w tmp_reg0.2<0,1,0>:w 4:w {align1}; (f0.0) jmpi (1) vme_start; jmpi (1) vme_done; vme_start: mov (8) tmp_vme_wb0.0<1>:ud vme_wb0.0<8,8,1>:ud {align1}; mov (8) tmp_vme_wb1.0<1>:ud vme_wb1.0<8,8,1>:ud {align1}; /* Calibrate the ref window for MPEG2 */ mov (1) vme_m0.0<1>:W -16:W {align1}; mov (1) vme_m0.2<1>:W -12:W {align1}; mov (1) INPUT_ARG0.8<1>:ud vme_m0.8<0,1,0>:ud {align1}; add (2) INPUT_ARG0.0<1>:w vme_m0.0<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; mov (8) INPUT_ARG1.0<1>:ud pic_ref.0<8,8,1>:ud {align1}; SAVE_RET {align1}; jmpi (1) ref_boundary_check; mov (2) vme_m0.0<1>:w RET_ARG<2,2,1>:w {align1}; /* IME search */ mov (1) vme_m0.12<1>:UD SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR:UD {align1}; /* 16x16 Source, harr */ mov (1) vme_m0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 48x40 */ mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (8) vme_m1.0<1>:ud 0x0:UD {align1}; mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; /* the Max MV number is passed by constant buffer */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; mov (1) vme_m1.8<1>:UD START_CENTER + SEARCH_PATH_LEN:UD {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* Setup the Cost center */ /* currently four 8x8 share the same cost center */ mov (4) vme_m3.0<2>:ud mv_cc_ref.0<0,1,0>:ud {align1}; mov (4) vme_m3.4<2>:ud mv_cc_ref.0<0,1,0>:ud {align1}; mov (8) vme_msg_3<1>:UD vme_m3.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* M4/M5 search path */ mov (1) vme_msg_4.0<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_4.4<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_4.8<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_4.12<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_4.16<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_4.20<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_4.24<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_4.28<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_5.0<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_5.4<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_5.8<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_5.12<1>:UD 0x000F0F0F:UD {align1}; mov (4) vme_msg_5.16<1>:UD 0x0:UD {align1}; send (8) vme_msg_ind vme_wb<1>:UD null vme( BIND_IDX_VME, 0, 0, VME_IME_MESSAGE_TYPE ) mlen ime_vme_msg_length rlen vme_wb_length {align1}; /* Set Macroblock-shape/mode for FBR */ mov (1) vme_m2.20<1>:UD 0x0:UD {align1}; mov (1) vme_m2.21<1>:UB vme_wb.25<0,1,0>:UB {align1}; mov (1) vme_m2.22<1>:UB vme_wb.26<0,1,0>:UB {align1}; and (1) tmp_reg0.0<1>:UW vme_wb.0<0,1,0>:UW 0x03:UW {align1}; mov (1) vme_m2.20<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* Send FBR message into CRE */ mov (8) vme_msg_4.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) vme_msg_5.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) vme_msg_6.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) vme_msg_7.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; mov (1) vme_m0.12<1>:UD INTER_SAD_HAAR + SUB_PEL_MODE_HALF + FBR_BME_DISABLE:UD {align1}; /* 16x16 Source, 1/2 pixel, harr, BME disable */ /* Bilinear filter */ mov (1) tmp_reg0.0<1>:uw 0x04:uw {align1}; add (1) vme_m1.30<1>:ub vme_m1.30<0,1,0>:ub tmp_reg0.0<0,1,0>:ub {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2.0<1>:UD vme_m2.0<8,8,1>:UD {align1}; mov (8) vme_msg_3.0<1>:UD vme_m3.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_FBR_MESSAGE_TYPE ) mlen fbr_vme_msg_length rlen vme_wb_length {align1}; cmp.l.f0.0 (1) null:uw vme_wb0.8<0,1,0>:uw tmp_vme_wb0.8<0,1,0>:uw {align1}; (f0.0) jmpi (1) vme_done; mov (8) vme_wb0.0<1>:ud tmp_vme_wb0.0<8,8,1>:ud {align1}; mov (8) vme_wb1.0<1>:ud tmp_vme_wb1.0<8,8,1>:ud {align1}; vme_done: jmpi (1) vme_mv_output; nop; nop; nop; intel-driver-1.3.0/src/shaders/vme/mpeg2_inter_gen8.g8a000066400000000000000000000001171231401140700226530ustar00rootroot00000000000000#include "vme8.inc" #include "vme75_mpeg2.inc" #include "mpeg2_inter_gen8.asm" intel-driver-1.3.0/src/shaders/vme/mpeg2_inter_gen8.g8b000066400000000000000000000476651231401140700226770ustar00rootroot00000000000000 { 0x00800001, 0x24000608, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400608, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800608, 0x00000000, 0x00000000 }, { 0x00800001, 0x24c00608, 0x00000000, 0x00000000 }, { 0x00200009, 0x24482248, 0x164500a0, 0x00040004 }, { 0x00000001, 0x24542288, 0x00000014, 0x00000000 }, { 0x00000041, 0x24881208, 0x220000a2, 0x000000a1 }, { 0x00000040, 0x24880208, 0x22000488, 0x000000a0 }, { 0x00000041, 0x24880208, 0x06000488, 0x00000018 }, { 0x00000001, 0x24942288, 0x00000014, 0x00000000 }, { 0x00200009, 0x2a401248, 0x16450098, 0x00040004 }, { 0x00200001, 0x2a501248, 0x00450094, 0x00000000 }, { 0x00600001, 0x2ac00608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a800608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ae00608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b000608, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b200608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20001240, 0x160000a6, 0x00040004 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000720 }, { 0x00600001, 0x2b400608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00600060 }, { 0x00210001, 0x2af41e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000f0 }, { 0x00000001, 0x2ae00e28, 0x08000000, 0x00000001 }, { 0x00200001, 0x24002248, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24001a68, 0x1e000400, 0xffffffff }, { 0x00000041, 0x2b481208, 0x120000a2, 0x00000402 }, { 0x00000040, 0x2b480208, 0x12000b48, 0x00000400 }, { 0x00000041, 0x2b480208, 0x06000b48, 0x00000018 }, { 0x00000001, 0x2b542288, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x02280303 }, { 0x05000010, 0x20001260, 0x12000b70, 0x00000b88 }, { 0x00210001, 0x2af41e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000040 }, { 0x00000040, 0x2b480208, 0x06000b48, 0x00000003 }, { 0x0a800031, 0x2ba00a08, 0x0e000b40, 0x02180203 }, { 0x00200001, 0x2ae40208, 0x00450ba0, 0x00000000 }, { 0x00000001, 0x2af01e68, 0x18000000, 0x00010001 }, { 0x00600001, 0x2b400608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00100010 }, { 0x00210001, 0x2b141e68, 0x18000000, 0xffffffff }, { 0x00210001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000360 }, { 0x00000001, 0x2b000e28, 0x08000000, 0x00000001 }, { 0x00200001, 0x24002248, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24021a68, 0x1e000402, 0xffffffff }, { 0x00000041, 0x2b481208, 0x120000a2, 0x00000402 }, { 0x00000040, 0x2b480208, 0x12000b48, 0x00000400 }, { 0x00000041, 0x2b480208, 0x06000b48, 0x00000018 }, { 0x00000001, 0x2b542288, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x02280303 }, { 0x05000010, 0x20001260, 0x12000b70, 0x00000b88 }, { 0x00210001, 0x2b141e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000040 }, { 0x00000040, 0x2b480208, 0x06000b48, 0x00000003 }, { 0x0a800031, 0x2ba00a08, 0x0e000b40, 0x02180203 }, { 0x00200001, 0x2b040208, 0x00450ba0, 0x00000000 }, { 0x00000001, 0x2b101e68, 0x18000000, 0x00010001 }, { 0x00600001, 0x2b400608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00080008 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000110 }, { 0x00000001, 0x2b200e28, 0x08000000, 0x00000001 }, { 0x00200001, 0x24002248, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24021a68, 0x1e000402, 0xffffffff }, { 0x00000040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00000041, 0x2b481208, 0x120000a2, 0x00000402 }, { 0x00000040, 0x2b480208, 0x12000b48, 0x00000400 }, { 0x00000041, 0x2b480208, 0x06000b48, 0x00000018 }, { 0x00000001, 0x2b542288, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x02280303 }, { 0x05000010, 0x20001260, 0x12000b70, 0x00000b88 }, { 0x00210001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000180 }, { 0x00000040, 0x2b480208, 0x06000b48, 0x00000003 }, { 0x0a800031, 0x2ba00a08, 0x0e000b40, 0x02180203 }, { 0x00200001, 0x2b240208, 0x00450ba0, 0x00000000 }, { 0x00000001, 0x2b301e68, 0x18000000, 0x00010001 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000130 }, { 0x00600001, 0x2b400608, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002240, 0x160000a5, 0x00040004 }, { 0x00210001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000f0 }, { 0x00000001, 0x2b200e28, 0x08000000, 0x00000001 }, { 0x00200001, 0x24002248, 0x004500a0, 0x00000000 }, { 0x00200040, 0x24001a68, 0x1e450400, 0xffffffff }, { 0x00000041, 0x2b481208, 0x120000a2, 0x00000402 }, { 0x00000040, 0x2b480208, 0x12000b48, 0x00000400 }, { 0x00000041, 0x2b480208, 0x06000b48, 0x00000018 }, { 0x00000001, 0x2b542288, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x02280303 }, { 0x05000010, 0x20001260, 0x12000b70, 0x00000b88 }, { 0x00210001, 0x2b341e68, 0x18000000, 0xffffffff }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000040 }, { 0x00000040, 0x2b480208, 0x06000b48, 0x00000003 }, { 0x0a800031, 0x2ba00a88, 0x0e000b40, 0x02180203 }, { 0x00200001, 0x2b240208, 0x00450ba0, 0x00000000 }, { 0x00000001, 0x2b301e68, 0x18000000, 0x00010001 }, { 0x00000040, 0x24000a28, 0x0a000b00, 0x00000b20 }, { 0x01000010, 0x20000a20, 0x0e000400, 0x00000000 }, { 0x00110020, 0x34000000, 0x0e001400, 0x00000080 }, { 0x02000010, 0x20000a20, 0x0e000ae0, 0x00000000 }, { 0x00010001, 0x2b040208, 0x00000ae4, 0x00000000 }, { 0x00010001, 0x2b240208, 0x00000ae4, 0x00000000 }, { 0x00010001, 0x2b141248, 0x00000af4, 0x00000000 }, { 0x00010001, 0x2b341248, 0x00000af4, 0x00000000 }, { 0x00010001, 0x2ac00208, 0x00000ae4, 0x00000000 }, { 0x00110001, 0x2ac00608, 0x00000000, 0x00000000 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000190 }, { 0x00600001, 0x24000608, 0x00000000, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000af4, 0x00000000 }, { 0x00010040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00010001, 0x24040208, 0x00000ae4, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000b14, 0x00000000 }, { 0x00010040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00010001, 0x24040208, 0x00000b04, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000b34, 0x00000000 }, { 0x00010040, 0x24001a68, 0x1e000400, 0x00010001 }, { 0x00010001, 0x24040208, 0x00000b24, 0x00000000 }, { 0x01000010, 0x20001a20, 0x1e000400, 0x00010001 }, { 0x00010001, 0x2ac00208, 0x00000404, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000c0 }, { 0x00000001, 0x2fa01a68, 0x00000ae4, 0x00000000 }, { 0x00000001, 0x2fa41a68, 0x00000b04, 0x00000000 }, { 0x00000001, 0x2fa81a68, 0x00000b24, 0x00000000 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000780 }, { 0x00000001, 0x2ac01a68, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2fa01a68, 0x00000ae6, 0x00000000 }, { 0x00000001, 0x2fa41a68, 0x00000b06, 0x00000000 }, { 0x00000001, 0x2fa81a68, 0x00000b26, 0x00000000 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000720 }, { 0x00000001, 0x2ac21a68, 0x00000fe4, 0x00000000 }, { 0x00200001, 0x2a201a68, 0x00450ae4, 0x00000000 }, { 0x00000001, 0x24401e68, 0x18000000, 0xfff0fff0 }, { 0x00000001, 0x24421e68, 0x18000000, 0xfff4fff4 }, { 0x00000001, 0x2fa00208, 0x00000440, 0x00000000 }, { 0x00000001, 0x2fa80208, 0x00000448, 0x00000000 }, { 0x00600001, 0x2fc00208, 0x008d0a40, 0x00000000 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0x000007b0 }, { 0x00200001, 0x24401a68, 0x00450fe4, 0x00000000 }, { 0x00600001, 0x25600208, 0x008d0020, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d0560, 0x00000000 }, { 0x00600001, 0x28600608, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800608, 0x00000000, 0x00000000 }, { 0x00600001, 0x28a00608, 0x00000000, 0x00000000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00010001 }, { 0x00000001, 0x28a52288, 0x00000400, 0x00000000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00bb00bb }, { 0x00000001, 0x28a42288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28c00608, 0x00000000, 0x00000000 }, { 0x00000001, 0x28d00608, 0x00000000, 0x11111111 }, { 0x00000001, 0x28dc0608, 0x00000000, 0x00010101 }, { 0x00600001, 0x28e00608, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600608, 0x00000000, 0x00000000 }, { 0x00000001, 0x247c1648, 0x10000000, 0x00000000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00020002 }, { 0x00000040, 0x24001248, 0x16000400, 0x00040004 }, { 0x00000001, 0x247c2288, 0x00000400, 0x00000000 }, { 0x00000001, 0x247d2288, 0x000000a5, 0x00000000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00000000 }, { 0x00000001, 0x247e2288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x00000001, 0x244c0608, 0x00000000, 0x00800000 }, { 0x00600001, 0x28000208, 0x008d0440, 0x00000000 }, { 0x0d600031, 0x21800a08, 0x0e000800, 0x10782000 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200208, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240208, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280208, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0208, 0x00000198, 0x00000000 }, { 0x00000001, 0x28301248, 0x0000018c, 0x00000000 }, { 0x00000001, 0x28340208, 0x00000188, 0x00000000 }, { 0x00000001, 0x28380208, 0x0000019c, 0x00000000 }, { 0x00000001, 0x283c0208, 0x00000488, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x040a0203 }, { 0x00000001, 0x244c0608, 0x00000000, 0x7e200000 }, { 0x00000001, 0x24561648, 0x10000000, 0x28302830 }, { 0x00000001, 0x24440208, 0x00000440, 0x00000000 }, { 0x00600001, 0x28000208, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24600608, 0x00000000, 0x00000002 }, { 0x00000001, 0x24642288, 0x0000009c, 0x00000000 }, { 0x00000001, 0x24680608, 0x00000000, 0x30003030 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x00400001, 0x45800208, 0x00000a20, 0x00000000 }, { 0x00400001, 0x45840208, 0x00000a20, 0x00000000 }, { 0x00600001, 0x28600208, 0x008d0580, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d0560, 0x00000000 }, { 0x00000001, 0x28800608, 0x00000000, 0x01010101 }, { 0x00000001, 0x28840608, 0x00000000, 0x10010101 }, { 0x00000001, 0x28880608, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x288c0608, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28900608, 0x00000000, 0x01010101 }, { 0x00000001, 0x28940608, 0x00000000, 0x10010101 }, { 0x00000001, 0x28980608, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x289c0608, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28a00608, 0x00000000, 0x01010101 }, { 0x00000001, 0x28a40608, 0x00000000, 0x10010101 }, { 0x00000001, 0x28a80608, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x28ac0608, 0x00000000, 0x000f0f0f }, { 0x00400001, 0x28b00608, 0x00000000, 0x00000000 }, { 0x08600031, 0x21800a08, 0x0e000800, 0x0c784000 }, { 0x00000001, 0x25740608, 0x00000000, 0x00000000 }, { 0x00000001, 0x25752288, 0x00000199, 0x00000000 }, { 0x00000001, 0x25762288, 0x0000019a, 0x00000000 }, { 0x00000005, 0x24001248, 0x16000180, 0x00030003 }, { 0x00000001, 0x25742288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28800208, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28a00208, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28c00208, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28e00208, 0x008d0200, 0x00000000 }, { 0x00000001, 0x244c0608, 0x00000000, 0x00241000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00040004 }, { 0x00000040, 0x247e2288, 0x2200047e, 0x00000400 }, { 0x00600001, 0x28000208, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d0560, 0x00000000 }, { 0x00600001, 0x28600208, 0x008d0580, 0x00000000 }, { 0x0d600031, 0x21800a08, 0x0e000800, 0x10786000 }, { 0x01000005, 0x20001240, 0x160000a6, 0x00040004 }, { 0x00110020, 0x34000000, 0x0e001400, 0x000004a0 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000040, 0x24880208, 0x06000488, 0x00000002 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200208, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240208, 0x00000198, 0x00000000 }, { 0x00000001, 0x28280208, 0x00000188, 0x00000000 }, { 0x00000001, 0x282c0208, 0x00000574, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x040a0003 }, { 0x00000040, 0x24880208, 0x06000488, 0x00000001 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28600208, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28800208, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x040a0203 }, { 0x00000040, 0x24880208, 0x06000488, 0x00000008 }, { 0x00600001, 0x28000208, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d0240, 0x00000000 }, { 0x0a800031, 0x20000a60, 0x0e000800, 0x040a0203 }, { 0x0a800031, 0x2b600a08, 0x0e000b40, 0x0219e003 }, { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24000a40, 0x0e000e00, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x04000010, 0x20001a60, 0x1a000fa0, 0x00000fa4 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000070 }, { 0x04000010, 0x20001a60, 0x1a000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000fa0, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x000000a0 }, { 0x04000010, 0x20001a60, 0x1a000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe41a68, 0x00000fa4, 0x00000000 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000060 }, { 0x04000010, 0x20001a60, 0x1a000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000fa4, 0x00000000 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000030 }, { 0x04000010, 0x20001a60, 0x1a000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe41a68, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe41a68, 0x00000fa0, 0x00000000 }, { 0x00000001, 0x34000200, 0x00000fe0, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00200040, 0x2f601a68, 0x1a450fa8, 0x00450fa0 }, { 0x00000040, 0x2f701a68, 0x1e000f60, 0x00300030 }, { 0x00000040, 0x2f721a68, 0x1e000f62, 0x00280028 }, { 0x00200041, 0x2f901a68, 0x1e450fd0, 0xffffffff }, { 0x00200040, 0x2f801a68, 0x1a450fa8, 0x00450f90 }, { 0x00200040, 0x2f841a68, 0x1a450fa8, 0x00450fd0 }, { 0x05000010, 0x20001a60, 0x1a000f60, 0x00000f80 }, { 0x00010001, 0x2f601a68, 0x00000f80, 0x00000000 }, { 0x03000010, 0x20001a60, 0x1a000f70, 0x00000f84 }, { 0x00010040, 0x2f601a68, 0x1e000f84, 0xffd0ffd0 }, { 0x05000010, 0x20001a60, 0x1a000f62, 0x00000f82 }, { 0x00010001, 0x2f621a68, 0x00000f82, 0x00000000 }, { 0x03000010, 0x20001a60, 0x1a000f72, 0x00000f86 }, { 0x00010040, 0x2f621a68, 0x1e000f86, 0xffd8ffd8 }, { 0x05000010, 0x20001a60, 0x1e000f60, 0x00000000 }, { 0x00110020, 0x34000000, 0x0e001400, 0x00000020 }, { 0x00010001, 0x2f601e68, 0x18000000, 0x00000000 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000030 }, { 0x03000010, 0x20001a60, 0x1a000f70, 0x00000fc0 }, { 0x00110020, 0x34000000, 0x0e001400, 0x00000010 }, { 0x00010040, 0x2f601a68, 0x1e000fc0, 0xffd0ffd0 }, { 0x05000010, 0x20001a60, 0x1e000f62, 0x00000000 }, { 0x00110020, 0x34000000, 0x0e001400, 0x00000020 }, { 0x00010001, 0x2f621e68, 0x18000000, 0x00000000 }, { 0x00000020, 0x34000000, 0x0e001400, 0x00000020 }, { 0x03000010, 0x20001a60, 0x1a000f72, 0x00000fc2 }, { 0x00010040, 0x2f621a68, 0x1e000fc2, 0xffd8ffd8 }, { 0x00200041, 0x2f801a68, 0x1e450fa8, 0xffffffff }, { 0x00200040, 0x2fe41a68, 0x1a450f60, 0x00450f80 }, { 0x00000001, 0x34000200, 0x00000fe0, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0020000c, 0x2a801a68, 0x1e450ac0, 0x00020002 }, { 0x00200001, 0x24001a68, 0x00450a80, 0x00000000 }, { 0x00200040, 0x2a881a68, 0x1e450a80, 0x00030003 }, { 0x00200005, 0x2a901248, 0x16450a88, 0xfffcfffc }, { 0x05000010, 0x20001a60, 0x1e000400, 0x00000000 }, { 0x00010041, 0x24001a68, 0x1e000400, 0xffffffff }, { 0x05000010, 0x20001a60, 0x1e000402, 0x00000000 }, { 0x00010041, 0x24021a68, 0x1e000402, 0xffffffff }, { 0x04000010, 0x20001a60, 0x1e000400, 0x00040004 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000030 }, { 0x04000010, 0x20001a60, 0x1e000402, 0x00040004 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000010 }, { 0x00000020, 0x34000000, 0x0e001400, 0x000003a0 }, { 0x00600001, 0x2c800208, 0x008d0180, 0x00000000 }, { 0x00600001, 0x2ca00208, 0x008d01a0, 0x00000000 }, { 0x00000001, 0x24401e68, 0x18000000, 0xfff0fff0 }, { 0x00000001, 0x24421e68, 0x18000000, 0xfff4fff4 }, { 0x00000001, 0x2fa80208, 0x00000448, 0x00000000 }, { 0x00200040, 0x2fa01a68, 0x1a450440, 0x00450a90 }, { 0x00600001, 0x2fc00208, 0x008d0a40, 0x00000000 }, { 0x00000040, 0x2fe00008, 0x06001400, 0x00000020 }, { 0x00000020, 0x34000000, 0x0e001400, 0xfffffca0 }, { 0x00200001, 0x24401a68, 0x00450fe4, 0x00000000 }, { 0x00000001, 0x244c0608, 0x00000000, 0x7e200000 }, { 0x00000001, 0x24561648, 0x10000000, 0x28302830 }, { 0x00000001, 0x24440208, 0x00000440, 0x00000000 }, { 0x00600001, 0x28000208, 0x008d0440, 0x00000000 }, { 0x00600001, 0x24600608, 0x00000000, 0x00000000 }, { 0x00000001, 0x24600608, 0x00000000, 0x00000002 }, { 0x00000001, 0x24642288, 0x0000009c, 0x00000000 }, { 0x00000001, 0x24680608, 0x00000000, 0x30003030 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x00400001, 0x45800208, 0x00000a20, 0x00000000 }, { 0x00400001, 0x45840208, 0x00000a20, 0x00000000 }, { 0x00600001, 0x28600208, 0x008d0580, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d0560, 0x00000000 }, { 0x00000001, 0x28800608, 0x00000000, 0x01010101 }, { 0x00000001, 0x28840608, 0x00000000, 0x10010101 }, { 0x00000001, 0x28880608, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x288c0608, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28900608, 0x00000000, 0x01010101 }, { 0x00000001, 0x28940608, 0x00000000, 0x10010101 }, { 0x00000001, 0x28980608, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x289c0608, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28a00608, 0x00000000, 0x01010101 }, { 0x00000001, 0x28a40608, 0x00000000, 0x10010101 }, { 0x00000001, 0x28a80608, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x28ac0608, 0x00000000, 0x000f0f0f }, { 0x00400001, 0x28b00608, 0x00000000, 0x00000000 }, { 0x08600031, 0x21800a08, 0x0e000800, 0x0c784000 }, { 0x00000001, 0x25740608, 0x00000000, 0x00000000 }, { 0x00000001, 0x25752288, 0x00000199, 0x00000000 }, { 0x00000001, 0x25762288, 0x0000019a, 0x00000000 }, { 0x00000005, 0x24001248, 0x16000180, 0x00030003 }, { 0x00000001, 0x25742288, 0x00000400, 0x00000000 }, { 0x00600001, 0x28800208, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28a00208, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28c00208, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28e00208, 0x008d0200, 0x00000000 }, { 0x00000001, 0x244c0608, 0x00000000, 0x00241000 }, { 0x00000001, 0x24001648, 0x10000000, 0x00040004 }, { 0x00000040, 0x247e2288, 0x2200047e, 0x00000400 }, { 0x00600001, 0x28000208, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200208, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400208, 0x008d0560, 0x00000000 }, { 0x00600001, 0x28600208, 0x008d0580, 0x00000000 }, { 0x0d600031, 0x21800a08, 0x0e000800, 0x10786000 }, { 0x05000010, 0x20001240, 0x12000188, 0x00000c88 }, { 0x00010020, 0x34000000, 0x0e001400, 0x00000020 }, { 0x00600001, 0x21800208, 0x008d0c80, 0x00000000 }, { 0x00600001, 0x21a00208, 0x008d0ca0, 0x00000000 }, { 0x00000020, 0x34000000, 0x0e001400, 0xfffff6f0 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/vme/mpeg2_inter_haswell.asm000066400000000000000000000733631231401140700235670ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * Author : Zhao Yakui */ // Modual name: mpeg2_inter_haswell.asm // // Make MPEG2 inter predition estimation for Inter-frame on Haswell // // // Now, begin source code.... // #define SAVE_RET add (1) RETURN_REG<1>:ud ip:ud 32:ud #define RETURN mov (1) ip:ud RETURN_REG<0,1,0>:ud /* * __START */ __INTER_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ; shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 24:UD {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) pic_ref.0<1>:uw r4.24<2,2,1>:uw 4:uw {align1}; mov (2) pic_ref.16<1>:uw r4.20<2,2,1>:uw {align1}; mov (8) mb_mvp_ref.0<1>:ud 0:ud {align1}; mov (8) mb_ref_win.0<1>:ud 0:ud {align1}; mov (8) mba_result.0<1>:ud 0x0:ud {align1}; mov (8) mbb_result.0<1>:ud 0x0:ud {align1}; mov (8) mbc_result.0<1>:ud 0x0:ud {align1}; and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1}; (f0.0) jmpi (1) __mb_hwdep_end; /* read back the data for MB A */ /* the layout of MB result is: rx.0(Available). rx.4(MVa), rX.8(MVb), rX.16(Pred_L0 flag), * rX.18 (Pred_L1 flag), rX.20(Forward reference ID), rX.22(Backwared reference ID) */ mba_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; /* MB A doesn't exist. Zero MV. mba_flag is zero and ref ID = -1 */ (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; mov (1) mba_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB A */ /* bind index 3, read 2 oword (16bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ /* MV */ mov (2) mba_result.4<1>:ud mb_mv0.0<2,2,1>:ud {align1}; mov (1) mba_result.16<1>:w MB_PRED_FLAG {align1}; mbb_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; /* MB B doesn't exist. Zero MV. mba_flag is zero */ /* If MB B doesn't exist, neither MB C nor D exists */ (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbb_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbc_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB B */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ mov (2) mbb_result.4<1>:ud mb_mv0.0<2,2,1>:ud {align1}; mov (1) mbb_result.16<1>:w MB_PRED_FLAG {align1}; mbc_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_C:uw {align1}; /* MB C doesn't exist. Zero MV. mba_flag is zero */ /* Based on h264 spec the MB D will be replaced if MB C doesn't exist */ (f0.0) jmpi (1) mbd_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; /* TODO: RefID is required after multi-references are added */ cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB C */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv0.0<2,2,1>:ud {align1}; mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1}; jmpi (1) mb_mvp_start; mbd_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_D:uw {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (2) tmp_reg0.0<1>:w tmp_reg0.0<2,2,1>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_4, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 2 {align1}; cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1}; /* Read MV for MB D */ /* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ub NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv0.0<2,2,1>:ud {align1}; mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1}; mb_mvp_start: /*TODO: Add the skip prediction */ /* Check whether both MB B and C are inavailable */ add (1) tmp_reg0.0<1>:d mbb_result.0<0,1,0>:d mbc_result.0<0,1,0>:d {align1}; cmp.z.f0.0 (1) null:d tmp_reg0.0<0,1,0>:d 0:d {align1}; (-f0.0) jmpi (1) mb_median_start; cmp.nz.f0.0 (1) null:d mba_result.0<0,1,0>:d 0:d {align1}; (f0.0) mov (1) mbb_result.4<1>:ud mba_result.4<0,1,0>:ud {align1}; (f0.0) mov (1) mbc_result.4<1>:ud mba_result.4<0,1,0>:ud {align1}; (f0.0) mov (1) mbb_result.20<1>:uw mba_result.20<0,1,0>:uw {align1}; (f0.0) mov (1) mbc_result.20<1>:uw mba_result.20<0,1,0>:uw {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud mba_result.4<0,1,0>:ud {align1}; (-f0.0) mov (1) mb_mvp_ref.0<1>:ud 0:ud {align1}; jmpi (1) __mb_hwdep_end; mb_median_start: /* check whether only one neighbour MB has the same ref ID with the current MB */ mov (8) tmp_reg0.0<1>:ud 0:ud {align1}; cmp.z.f0.0 (1) null:d mba_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbb_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbc_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.4<0,1,0>:ud {align1}; cmp.e.f0.0 (1) null:d tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud tmp_reg0.4<0,1,0>:ud {align1}; (f0.0) jmpi (1) __mb_hwdep_end; mov (1) INPUT_ARG0.0<1>:w mba_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.4<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.0<1>:w RET_ARG<0,1,0>:w {align1}; mov (1) INPUT_ARG0.0<1>:w mba_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.6<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.2<1>:w RET_ARG<0,1,0>:w {align1}; __mb_hwdep_end: mov (2) mv_cc_ref.0<1>:w mba_result.4<2,2,1>:w {align1}; /* Calibrate the ref window for MPEG2 */ mov (1) vme_m0.0<1>:W -16:W {align1}; mov (1) vme_m0.2<1>:W -12:W {align1}; mov (1) INPUT_ARG0.0<1>:ud vme_m0.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud vme_m0.8<0,1,0>:ud {align1}; mov (8) INPUT_ARG1.0<1>:ud pic_ref.0<8,8,1>:ud {align1}; SAVE_RET {align1}; jmpi (1) ref_boundary_check; mov (2) vme_m0.0<1>:w RET_ARG<2,2,1>:w {align1}; /* m2, get the MV/Mb cost passed from constant buffer when spawning thread by MEDIA_OBJECT */ mov (8) vme_m2<1>:UD r1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* m3 */ mov (8) vme_msg_3<1>:UD 0x0:UD {align1}; /* the neighbour pixel is zero for MPEG2 Intra-prediction */ /* m4 */ mov (8) vme_msg_4<1>:UD 0:UD {align1}; mov (1) tmp_reg0.0<1>:UW LUMA_INTRA_MODE:UW {align1}; /* Use the Luma mode */ mov (1) vme_msg_4.5<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; mov (1) tmp_reg0.0<1>:UW INTRA16_DC_PRED:UW {align1}; mov (1) vme_msg_4.4<1>:ub tmp_reg0.0<0,1,0>:UB {align1}; /* m5 */ mov (8) vme_msg_5<1>:UD 0x0:UD {align1}; mov (1) vme_msg_5.16<1>:UD INTRA_PREDICTORE_MODE {align1}; /* the penalty for Intra mode */ mov (1) vme_msg_5.28<1>:UD 0x010101:UD {align1}; /* m6 */ mov (8) vme_msg_6.0<1>:UD 0:Ud {align1}; /* * SIC VME message */ /* m0 */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; /* Disable Intra8x8/Intra4x4 Intra-prediction */ /* m1 */ mov (8) vme_m1.0<1>:ud 0x0:UD {align1}; mov (1) intra_flag<1>:UW 0x0:UW {align1} ; mov (1) tmp_reg0.0<1>:uw LUMA_INTRA_8x8_DISABLE:uw {align1}; add (1) tmp_reg0.0<1>:uw tmp_reg0.0<0,1,0>:uw LUMA_INTRA_4x4_DISABLE:uw {align1}; mov (1) intra_part_mask_ub<1>:UB tmp_reg0.0<0,1,0>:ub {align1}; /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; /* Enable DC HAAR component when calculating HARR SATD block */ mov (1) tmp_reg0.0<1>:UW DC_HARR_ENABLE:UW {align1}; mov (1) vme_m1.30<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; mov (1) vme_m0.12<1>:UD INTRA_SAD_HAAR:UD {align1}; /* 16x16 Source, Intra_harr */ /* m0 */ mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_SIC_MESSAGE_TYPE ) mlen sic_vme_msg_length rlen vme_wb_length {align1}; /* * Oword Block Write message */ mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Distortion, Intra (17-16), */ mov (1) msg_reg1.16<1>:UW vme_wb.12<0,1,0>:UW {align1}; mov (1) msg_reg1.20<1>:UD vme_wb.8<0,1,0>:UD {align1}; /* VME clock counts */ mov (1) msg_reg1.24<1>:UD vme_wb.28<0,1,0>:UD {align1}; mov (1) msg_reg1.28<1>:UD obw_m0.8<0,1,0>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* IME search */ mov (1) vme_m0.12<1>:UD SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR:UD {align1}; /* 16x16 Source, harr */ mov (1) vme_m0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 48x40 */ mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; /* the Max MV number is passed by constant buffer */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; mov (1) vme_m1.8<1>:UD START_CENTER + SEARCH_PATH_LEN:UD {align1}; /* Set the MV cost center */ mov (1) vme_m1.16<1>:ud mv_cc_ref.0<0,1,0>:ud {align1}; mov (1) vme_m1.20<1>:ud mv_cc_ref.0<0,1,0>:ud {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* M3/M4 search path */ mov (1) vme_msg_3.0<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_3.4<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_3.8<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_3.12<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_3.16<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_3.20<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_3.24<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_3.28<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_4.0<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_4.4<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_4.8<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_4.12<1>:UD 0x000F0F0F:UD {align1}; mov (4) vme_msg_4.16<1>:UD 0x0:UD {align1}; send (8) vme_msg_ind vme_wb<1>:UD null vme( BIND_IDX_VME, 0, 0, VME_IME_MESSAGE_TYPE ) mlen ime_vme_msg_length rlen vme_wb_length {align1}; /* Set Macroblock-shape/mode for FBR */ mov (1) vme_m2.20<1>:UD 0x0:UD {align1}; mov (1) vme_m2.21<1>:UB vme_wb.25<0,1,0>:UB {align1}; mov (1) vme_m2.22<1>:UB vme_wb.26<0,1,0>:UB {align1}; and (1) tmp_reg0.0<1>:UW vme_wb.0<0,1,0>:UW 0x03:UW {align1}; mov (1) vme_m2.20<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* Send FBR message into CRE */ mov (8) vme_msg_3.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) vme_msg_4.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) vme_msg_5.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) vme_msg_6.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; mov (1) vme_m0.12<1>:UD INTER_SAD_HAAR + SUB_PEL_MODE_HALF + FBR_BME_DISABLE:UD {align1}; /* 16x16 Source, 1/2 pixel, harr, BME disable */ /* Bilinear filter */ mov (1) tmp_reg0.0<1>:uw 0x04:uw {align1}; add (1) vme_m1.30<1>:ub vme_m1.30<0,1,0>:ub tmp_reg0.0<0,1,0>:ub {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2.0<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_FBR_MESSAGE_TYPE ) mlen fbr_vme_msg_length rlen vme_wb_length {align1}; and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1}; (-f0.0) jmpi (1) vme_run_again; nop; vme_mv_output: add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; /* write FME info */ mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.24<0,1,0>:UD {align1}; /* Inter distortion of FME */ mov (1) msg_reg1.8<1>:UD vme_wb.8<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_m2.20<0,1,0>:UD {align1}; /* bind index 3, write oword (16bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_0, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Write FME/BME MV */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x01:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0.0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) msg_reg2.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) msg_reg3.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) msg_reg4.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; /* bind index 3, write 8 oword (128 bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Write FME/BME RefID */ add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x08:UD {align1}; mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb6.0<8,8,1>:UD {align1}; /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Issue message fence so that the previous write message is committed */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_FENCE, OBR_MF_COMMIT, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; nop ; nop ; word_imedian: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_a_ge_b; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; jmpi (1) cmp_end; cmp_a_ge_b: cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; cmp_end: RETURN {align1}; nop; nop; ref_boundary_check: /* The left/up coordinate of reference window */ add (2) TEMP_VAR0.0<1>:w INPUT_ARG0.8<2,2,1>:w INPUT_ARG0.0<2,2,1>:w {align1}; /* The right/bottom coordinate of reference window */ add (1) TEMP_VAR0.16<1>:w TEMP_VAR0.0<0,1,0>:w 48:w {align1}; add (1) TEMP_VAR0.18<1>:w TEMP_VAR0.2<0,1,0>:w 40:w {align1}; /* Firstly the MV range is checked */ mul (2) TEMP_VAR1.16<1>:w INPUT_ARG1.16<2,2,1>:w -1:w {align1}; add (2) TEMP_VAR1.0<1>:w INPUT_ARG0.8<2,2,1>:w TEMP_VAR1.16<2,2,1>:w {align1}; add (2) TEMP_VAR1.4<1>:w INPUT_ARG0.8<2,2,1>:w INPUT_ARG1.16<2,2,1>:w {align1}; cmp.l.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w TEMP_VAR1.0<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w TEMP_VAR1.0<0,1,0>:w {align1}; cmp.g.f0.0 (1) null:w TEMP_VAR0.16<0,1,0>:w TEMP_VAR1.4<0,1,0>:w {align1}; (f0.0) add (1) TEMP_VAR0.0<1>:w TEMP_VAR1.4<0,1,0>:w -48:w {align1}; cmp.l.f0.0 (1) null:w TEMP_VAR0.2<0,1,0>:w TEMP_VAR1.2<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.2<1>:w TEMP_VAR1.2<0,1,0>:w {align1}; cmp.g.f0.0 (1) null:w TEMP_VAR0.18<0,1,0>:w TEMP_VAR1.6<0,1,0>:w {align1}; (f0.0) add (1) TEMP_VAR0.2<1>:w TEMP_VAR1.6<0,1,0>:w -40:w {align1}; x_left_cmp: cmp.l.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w 0:w {align1}; (-f0.0) jmpi (1) x_right_cmp; (f0.0) mov (1) TEMP_VAR0.0<1>:w 0:w {align1}; jmpi (1) y_top_cmp; x_right_cmp: cmp.g.f0.0 (1) null:w TEMP_VAR0.16<0,1,0>:w INPUT_ARG1.0<0,1,0>:w {align1}; (-f0.0) jmpi (1) y_top_cmp; (f0.0) add (1) TEMP_VAR0.0<1>:w INPUT_ARG1.0<0,1,0>:w -48:w {align1}; y_top_cmp: cmp.l.f0.0 (1) null:w TEMP_VAR0.2<0,1,0>:w 0:w {align1}; (-f0.0) jmpi (1) y_bottom_cmp; (f0.0) mov (1) TEMP_VAR0.2<1>:w 0:w {align1}; jmpi (1) y_bottom_end; y_bottom_cmp: cmp.g.f0.0 (1) null:w TEMP_VAR0.18<0,1,0>:w INPUT_ARG1.2<0,1,0>:w {align1}; (f0.0) add (1) TEMP_VAR0.2<1>:w INPUT_ARG1.2<0,1,0>:w -40:w {align1}; y_bottom_end: mul (2) TEMP_VAR1.0<1>:w INPUT_ARG0.8<2,2,1>:w -1:w {align1}; add (2) RET_ARG<1>:w TEMP_VAR0.0<2,2,1>:w TEMP_VAR1.0<2,2,1>:w {align1}; RETURN {align1}; nop; nop; vme_run_again: asr (2) mb_ref_win.0<1>:w mb_mvp_ref.0<2,2,1>:w 2:w {align1}; mov (2) tmp_reg0.0<1>:w mb_ref_win.0<2,2,1>:w {align1}; add (2) mb_ref_win.8<1>:w mb_ref_win.0<2,2,1>:w 3:w {align1}; and (2) mb_ref_win.16<1>:uw mb_ref_win.8<2,2,1>:uw 0xFFFC:uw {align1}; cmp.l.f0.0 (1) null:w tmp_reg0.0<0,1,0>:w 0:w {align1}; (f0.0) mul (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1}; cmp.l.f0.0 (1) null:w tmp_reg0.2<0,1,0>:w 0:w {align1}; (f0.0) mul (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; cmp.ge.f0.0 (1) null:w tmp_reg0.0<0,1,0>:w 4:w {align1}; (f0.0) jmpi (1) vme_start; cmp.ge.f0.0 (1) null:w tmp_reg0.2<0,1,0>:w 4:w {align1}; (f0.0) jmpi (1) vme_start; jmpi (1) vme_done; vme_start: mov (8) tmp_vme_wb0.0<1>:ud vme_wb0.0<8,8,1>:ud {align1}; mov (8) tmp_vme_wb1.0<1>:ud vme_wb1.0<8,8,1>:ud {align1}; /* Calibrate the ref window for MPEG2 */ mov (1) vme_m0.0<1>:W -16:W {align1}; mov (1) vme_m0.2<1>:W -12:W {align1}; mov (4) INPUT_ARG0.0<1>:ud vme_m0.0<4,4,1>:ud {align1}; add (2) INPUT_ARG0.0<1>:w INPUT_ARG0.0<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; mov (8) INPUT_ARG1.0<1>:ud pic_ref.0<8,8,1>:ud {align1}; SAVE_RET {align1}; jmpi (1) ref_boundary_check; mov (2) vme_m0.0<1>:w RET_ARG<2,2,1>:w {align1}; /* IME search */ mov (1) vme_m0.12<1>:UD SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR:UD {align1}; /* 16x16 Source, harr */ mov (1) vme_m0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 48x40 */ mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (8) vme_m1.0<1>:ud 0x0:UD {align1}; mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; /* the Max MV number is passed by constant buffer */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; mov (1) vme_m1.8<1>:UD START_CENTER + SEARCH_PATH_LEN:UD {align1}; /* Set the MV cost center */ mov (1) vme_m1.16<1>:ud mv_cc_ref.0<0,1,0>:ud {align1}; mov (1) vme_m1.20<1>:ud mv_cc_ref.0<0,1,0>:ud {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* M3/M4 search path */ mov (1) vme_msg_3.0<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_3.4<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_3.8<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_3.12<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_3.16<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_3.20<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_3.24<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_3.28<1>:UD 0x100F0F0F:UD {align1}; mov (1) vme_msg_4.0<1>:UD 0x01010101:UD {align1}; mov (1) vme_msg_4.4<1>:UD 0x10010101:UD {align1}; mov (1) vme_msg_4.8<1>:UD 0x0F0F0F0F:UD {align1}; mov (1) vme_msg_4.12<1>:UD 0x000F0F0F:UD {align1}; mov (4) vme_msg_4.16<1>:UD 0x0:UD {align1}; send (8) vme_msg_ind vme_wb<1>:UD null vme( BIND_IDX_VME, 0, 0, VME_IME_MESSAGE_TYPE ) mlen ime_vme_msg_length rlen vme_wb_length {align1}; /* Set Macroblock-shape/mode for FBR */ mov (1) vme_m2.20<1>:UD 0x0:UD {align1}; mov (1) vme_m2.21<1>:UB vme_wb.25<0,1,0>:UB {align1}; mov (1) vme_m2.22<1>:UB vme_wb.26<0,1,0>:UB {align1}; and (1) tmp_reg0.0<1>:UW vme_wb.0<0,1,0>:UW 0x03:UW {align1}; mov (1) vme_m2.20<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; /* Send FBR message into CRE */ mov (8) vme_msg_3.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; mov (8) vme_msg_4.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; mov (8) vme_msg_5.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; mov (8) vme_msg_6.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; mov (1) vme_m0.12<1>:UD INTER_SAD_HAAR + SUB_PEL_MODE_HALF + FBR_BME_DISABLE:UD {align1}; /* 16x16 Source, 1/2 pixel, harr, BME disable */ /* Bilinear filter */ mov (1) tmp_reg0.0<1>:uw 0x04:uw {align1}; add (1) vme_m1.30<1>:ub vme_m1.30<0,1,0>:ub tmp_reg0.0<0,1,0>:ub {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; mov (8) vme_msg_2.0<1>:UD vme_m2.0<8,8,1>:UD {align1}; /* after verification it will be passed by using payload */ send (8) vme_msg_ind vme_wb<1>:UD null cre( BIND_IDX_VME, VME_FBR_MESSAGE_TYPE ) mlen fbr_vme_msg_length rlen vme_wb_length {align1}; cmp.l.f0.0 (1) null:uw vme_wb0.8<0,1,0>:uw tmp_vme_wb0.8<0,1,0>:uw {align1}; (f0.0) jmpi (1) vme_done; mov (8) vme_wb0.0<1>:ud tmp_vme_wb0.0<8,8,1>:ud {align1}; mov (8) vme_wb1.0<1>:ud tmp_vme_wb1.0<8,8,1>:ud {align1}; vme_done: jmpi (1) vme_mv_output; nop; nop; nop; intel-driver-1.3.0/src/shaders/vme/mpeg2_inter_haswell.g75a000066400000000000000000000001231231401140700235320ustar00rootroot00000000000000#include "vme75.inc" #include "vme75_mpeg2.inc" #include "mpeg2_inter_haswell.asm" intel-driver-1.3.0/src/shaders/vme/mpeg2_inter_haswell.g75b000066400000000000000000000472421231401140700235500ustar00rootroot00000000000000 { 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000001, 0x24540231, 0x00000014, 0x00000000 }, { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 }, { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 }, { 0x00000041, 0x24880c21, 0x00000488, 0x00000018 }, { 0x00000001, 0x24940231, 0x00000014, 0x00000000 }, { 0x00200009, 0x2a402d29, 0x00450098, 0x00040004 }, { 0x00200001, 0x2a500129, 0x00450094, 0x00000000 }, { 0x00600001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ae00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b200061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002d28, 0x000000a6, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000710 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00600060 }, { 0x00210001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000f0 }, { 0x00000001, 0x2ae000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24003dad, 0x00000400, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x00000018 }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280303 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00210001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02180203 }, { 0x00200001, 0x2ae40021, 0x00450ba0, 0x00000000 }, { 0x00000001, 0x2af001ed, 0x00000000, 0x00010001 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00100010 }, { 0x00210001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000350 }, { 0x00000001, 0x2b0000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x00000018 }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280303 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00210001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02180203 }, { 0x00200001, 0x2b040021, 0x00450ba0, 0x00000000 }, { 0x00000001, 0x2b1001ed, 0x00000000, 0x00010001 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00080008 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000110 }, { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff }, { 0x00000040, 0x24003dad, 0x00000400, 0x00010001 }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x00000018 }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280303 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000170 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02180203 }, { 0x00200001, 0x2b240021, 0x00450ba0, 0x00000000 }, { 0x00000001, 0x2b3001ed, 0x00000000, 0x00010001 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000120 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000f0 }, { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00200040, 0x24003dad, 0x00450400, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x00000018 }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x02280303 }, { 0x05000010, 0x2000252c, 0x00000b70, 0x00000b88 }, { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000040 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000003 }, { 0x0a800031, 0x2ba01cb1, 0x00000b40, 0x02180203 }, { 0x00200001, 0x2b240021, 0x00450ba0, 0x00000000 }, { 0x00000001, 0x2b3001ed, 0x00000000, 0x00010001 }, { 0x00000040, 0x240014a5, 0x00000b00, 0x00000b20 }, { 0x01000010, 0x20001ca4, 0x00000400, 0x00000000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000080 }, { 0x02000010, 0x20001ca4, 0x00000ae0, 0x00000000 }, { 0x00010001, 0x2b040021, 0x00000ae4, 0x00000000 }, { 0x00010001, 0x2b240021, 0x00000ae4, 0x00000000 }, { 0x00010001, 0x2b140129, 0x00000af4, 0x00000000 }, { 0x00010001, 0x2b340129, 0x00000af4, 0x00000000 }, { 0x00010001, 0x2ac00021, 0x00000ae4, 0x00000000 }, { 0x00110001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000190 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200af4, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000ae4, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b14, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b04, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b34, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b24, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200400, 0x00010001 }, { 0x00010001, 0x2ac00021, 0x00000404, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000c0 }, { 0x00000001, 0x2fa001ad, 0x00000ae4, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b04, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b24, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000760 }, { 0x00000001, 0x2ac001ad, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2fa001ad, 0x00000ae6, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b06, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b26, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000700 }, { 0x00000001, 0x2ac201ad, 0x00000fe4, 0x00000000 }, { 0x00200001, 0x2a2001ad, 0x00450ae4, 0x00000000 }, { 0x00000001, 0x244001ed, 0x00000000, 0xfff0fff0 }, { 0x00000001, 0x244201ed, 0x00000000, 0xfff4fff4 }, { 0x00000001, 0x2fa00021, 0x00000440, 0x00000000 }, { 0x00000001, 0x2fa80021, 0x00000448, 0x00000000 }, { 0x00600001, 0x2fc00021, 0x008d0a40, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000790 }, { 0x00200001, 0x244001ad, 0x00450fe4, 0x00000000 }, { 0x00600001, 0x25600021, 0x008d0020, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00010001 }, { 0x00000001, 0x28850231, 0x00000400, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00bb00bb }, { 0x00000001, 0x28840231, 0x00000400, 0x00000000 }, { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 }, { 0x00000001, 0x28b00061, 0x00000000, 0x11111111 }, { 0x00000001, 0x28bc0061, 0x00000000, 0x00010101 }, { 0x00600001, 0x28c00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00000001, 0x247c0169, 0x00000000, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00020002 }, { 0x00000040, 0x24002d29, 0x00000400, 0x00040004 }, { 0x00000001, 0x247c0231, 0x00000400, 0x00000000 }, { 0x00000001, 0x247d0231, 0x000000a5, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00000000 }, { 0x00000001, 0x247e0231, 0x00000400, 0x00000000 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00800000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x0d600031, 0x21801ca1, 0x00000800, 0x0e782000 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 }, { 0x00000001, 0x28300129, 0x0000018c, 0x00000000 }, { 0x00000001, 0x28340021, 0x00000188, 0x00000000 }, { 0x00000001, 0x28380021, 0x0000019c, 0x00000000 }, { 0x00000001, 0x283c0021, 0x00000488, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x00000001, 0x244c0061, 0x00000000, 0x7e200000 }, { 0x00000001, 0x24560169, 0x00000000, 0x28302830 }, { 0x00000001, 0x24440021, 0x00000440, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00000002 }, { 0x00000001, 0x24640231, 0x0000009c, 0x00000000 }, { 0x00000001, 0x24680061, 0x00000000, 0x30003030 }, { 0x00000001, 0x24700021, 0x00000a20, 0x00000000 }, { 0x00000001, 0x24740021, 0x00000a20, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 }, { 0x00000001, 0x28600061, 0x00000000, 0x01010101 }, { 0x00000001, 0x28640061, 0x00000000, 0x10010101 }, { 0x00000001, 0x28680061, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x286c0061, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28700061, 0x00000000, 0x01010101 }, { 0x00000001, 0x28740061, 0x00000000, 0x10010101 }, { 0x00000001, 0x28780061, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x287c0061, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28800061, 0x00000000, 0x01010101 }, { 0x00000001, 0x28840061, 0x00000000, 0x10010101 }, { 0x00000001, 0x28880061, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x288c0061, 0x00000000, 0x000f0f0f }, { 0x00400001, 0x28900061, 0x00000000, 0x00000000 }, { 0x08600031, 0x21801ca1, 0x00000800, 0x0a784000 }, { 0x00000001, 0x25740061, 0x00000000, 0x00000000 }, { 0x00000001, 0x25750231, 0x00000199, 0x00000000 }, { 0x00000001, 0x25760231, 0x0000019a, 0x00000000 }, { 0x00000005, 0x24002d29, 0x00000180, 0x00030003 }, { 0x00000001, 0x25740231, 0x00000400, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28a00021, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28c00021, 0x008d0200, 0x00000000 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00241000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00040004 }, { 0x00000040, 0x247e4631, 0x0000047e, 0x00000400 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 }, { 0x0d600031, 0x21801ca1, 0x00000800, 0x0e786000 }, { 0x01000005, 0x20002d28, 0x000000a6, 0x00040004 }, { 0x00110020, 0x34001c00, 0x00001400, 0x000004a0 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00000040, 0x24880c21, 0x00000488, 0x00000002 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000198, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000188, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000574, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0003 }, { 0x00000040, 0x24880c21, 0x00000488, 0x00000001 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d0200, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x00000040, 0x24880c21, 0x00000488, 0x00000008 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0240, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x0a800031, 0x2b601ca1, 0x00000b40, 0x0219e003 }, { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca8, 0x00000e00, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000070 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa0, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000a0 }, { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa4, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000060 }, { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa4, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa0, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00200040, 0x2f6035ad, 0x00450fa8, 0x00450fa0 }, { 0x00000040, 0x2f703dad, 0x00000f60, 0x00300030 }, { 0x00000040, 0x2f723dad, 0x00000f62, 0x00280028 }, { 0x00200041, 0x2f903dad, 0x00450fd0, 0xffffffff }, { 0x00200040, 0x2f8035ad, 0x00450fa8, 0x00450f90 }, { 0x00200040, 0x2f8435ad, 0x00450fa8, 0x00450fd0 }, { 0x05000010, 0x200035ac, 0x00000f60, 0x00000f80 }, { 0x00010001, 0x2f6001ad, 0x00000f80, 0x00000000 }, { 0x03000010, 0x200035ac, 0x00000f70, 0x00000f84 }, { 0x00010040, 0x2f603dad, 0x00000f84, 0xffd0ffd0 }, { 0x05000010, 0x200035ac, 0x00000f62, 0x00000f82 }, { 0x00010001, 0x2f6201ad, 0x00000f82, 0x00000000 }, { 0x03000010, 0x200035ac, 0x00000f72, 0x00000f86 }, { 0x00010040, 0x2f623dad, 0x00000f86, 0xffd8ffd8 }, { 0x05000010, 0x20003dac, 0x00000f60, 0x00000000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00010001, 0x2f6001ed, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x03000010, 0x200035ac, 0x00000f70, 0x00000fc0 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00010040, 0x2f603dad, 0x00000fc0, 0xffd0ffd0 }, { 0x05000010, 0x20003dac, 0x00000f62, 0x00000000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00010001, 0x2f6201ed, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x03000010, 0x200035ac, 0x00000f72, 0x00000fc2 }, { 0x00010040, 0x2f623dad, 0x00000fc2, 0xffd8ffd8 }, { 0x00200041, 0x2f803dad, 0x00450fa8, 0xffffffff }, { 0x00200040, 0x2fe435ad, 0x00450f60, 0x00450f80 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0020000c, 0x2a803dad, 0x00450ac0, 0x00020002 }, { 0x00200001, 0x240001ad, 0x00450a80, 0x00000000 }, { 0x00200040, 0x2a883dad, 0x00450a80, 0x00030003 }, { 0x00200005, 0x2a902d29, 0x00450a88, 0xfffcfffc }, { 0x05000010, 0x20003dac, 0x00000400, 0x00000000 }, { 0x00010041, 0x24003dad, 0x00000400, 0xffffffff }, { 0x05000010, 0x20003dac, 0x00000402, 0x00000000 }, { 0x00010041, 0x24023dad, 0x00000402, 0xffffffff }, { 0x04000010, 0x20003dac, 0x00000400, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000030 }, { 0x04000010, 0x20003dac, 0x00000402, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000380 }, { 0x00600001, 0x2c800021, 0x008d0180, 0x00000000 }, { 0x00600001, 0x2ca00021, 0x008d01a0, 0x00000000 }, { 0x00000001, 0x244001ed, 0x00000000, 0xfff0fff0 }, { 0x00000001, 0x244201ed, 0x00000000, 0xfff4fff4 }, { 0x00400001, 0x2fa00021, 0x00690440, 0x00000000 }, { 0x00200040, 0x2fa035ad, 0x00450fa0, 0x00450a90 }, { 0x00600001, 0x2fc00021, 0x008d0a40, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0xfffffca0 }, { 0x00200001, 0x244001ad, 0x00450fe4, 0x00000000 }, { 0x00000001, 0x244c0061, 0x00000000, 0x7e200000 }, { 0x00000001, 0x24560169, 0x00000000, 0x28302830 }, { 0x00000001, 0x24440021, 0x00000440, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00000002 }, { 0x00000001, 0x24640231, 0x0000009c, 0x00000000 }, { 0x00000001, 0x24680061, 0x00000000, 0x30003030 }, { 0x00000001, 0x24700021, 0x00000a20, 0x00000000 }, { 0x00000001, 0x24740021, 0x00000a20, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 }, { 0x00000001, 0x28600061, 0x00000000, 0x01010101 }, { 0x00000001, 0x28640061, 0x00000000, 0x10010101 }, { 0x00000001, 0x28680061, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x286c0061, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28700061, 0x00000000, 0x01010101 }, { 0x00000001, 0x28740061, 0x00000000, 0x10010101 }, { 0x00000001, 0x28780061, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x287c0061, 0x00000000, 0x100f0f0f }, { 0x00000001, 0x28800061, 0x00000000, 0x01010101 }, { 0x00000001, 0x28840061, 0x00000000, 0x10010101 }, { 0x00000001, 0x28880061, 0x00000000, 0x0f0f0f0f }, { 0x00000001, 0x288c0061, 0x00000000, 0x000f0f0f }, { 0x00400001, 0x28900061, 0x00000000, 0x00000000 }, { 0x08600031, 0x21801ca1, 0x00000800, 0x0a784000 }, { 0x00000001, 0x25740061, 0x00000000, 0x00000000 }, { 0x00000001, 0x25750231, 0x00000199, 0x00000000 }, { 0x00000001, 0x25760231, 0x0000019a, 0x00000000 }, { 0x00000005, 0x24002d29, 0x00000180, 0x00030003 }, { 0x00000001, 0x25740231, 0x00000400, 0x00000000 }, { 0x00600001, 0x28600021, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28a00021, 0x008d01e0, 0x00000000 }, { 0x00600001, 0x28c00021, 0x008d0200, 0x00000000 }, { 0x00000001, 0x244c0061, 0x00000000, 0x00241000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00040004 }, { 0x00000040, 0x247e4631, 0x0000047e, 0x00000400 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 }, { 0x0d600031, 0x21801ca1, 0x00000800, 0x0e786000 }, { 0x05000010, 0x20002528, 0x00000188, 0x00000c88 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000020 }, { 0x00600001, 0x21800021, 0x008d0c80, 0x00000000 }, { 0x00600001, 0x21a00021, 0x008d0ca0, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0xfffff710 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/vme/mpeg2_inter_ivb.asm000066400000000000000000000620611231401140700227010ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * Authors: Zhao Yakui * */ // Modual name: mpeg2_inter_ivb.asm // // Make inter predition estimation for Mpeg2 Inter frame on Ivy // // // Now, begin source code.... // #define SAVE_RET add (1) RETURN_REG<1>:ud ip:ud 32:ud #define RETURN mov (1) ip:ud RETURN_REG<0,1,0>:ud /* * __START */ __INTER_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ; mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ; shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */ mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1}; mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ shl (2) pic_ref.0<1>:uw r4.24<2,2,1>:uw 4:uw {align1}; mov (2) pic_ref.16<1>:uw r4.20<2,2,1>:uw {align1}; mov (8) mb_mvp_ref.0<1>:ud 0:ud {align1}; mov (8) mb_ref_win.0<1>:ud 0:ud {align1}; mov (8) mba_result.0<1>:ud 0x0:ud {align1}; mov (8) mbb_result.0<1>:ud 0x0:ud {align1}; mov (8) mbc_result.0<1>:ud 0x0:ud {align1}; and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1}; (f0.0) jmpi (1) __mb_hwdep_end; /* read back the data for MB A */ /* the layout of MB result is: rx.0(Available). rx.4(MVa), rX.8(MVb), rX.16(Pred_L0 flag), * rX.18 (Pred_L1 flag), rX.20(Forward reference ID), rX.22(Backwared reference ID) */ mba_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1}; /* MB A doesn't exist. Zero MV. mba_flag is zero and ref ID = -1 */ (f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mbb_start; mov (1) mba_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) mb_msg_tmp.8<1>:ud mb_msg0.8<0,1,0>:ud {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; /* bind index 3, read 1 oword (16bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_0, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ and.z.f0.0 (1) null<1>:ud mb_mode_wb.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0) mov (2) mba_result.20<1>:w -1:w {align1}; (-f0.0) jmpi (1) mbb_start; mov (1) mb_msg0.8<1>:UD mb_msg_tmp.8<0,1,0>:ud {align1}; /* Read MV for MB A */ /* bind index 3, read 2 oword (16bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ /* MV */ mov (2) mba_result.4<1>:ud mb_mv0.0<2,2,1>:ud {align1}; mov (1) mba_result.16<1>:w MB_PRED_FLAG {align1}; mbb_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1}; /* MB B doesn't exist. Zero MV. mba_flag is zero */ /* If MB B doesn't exist, neither MB C nor D exists */ (f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbb_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) mb_msg_tmp.8<1>:ud mb_msg0.8<0,1,0>:ud {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_0, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ and.z.f0.0 (1) null<1>:ud mb_mode_wb.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0) mov (2) mbb_result.20<1>:w -1:w {align1}; (-f0.0) jmpi (1) mbc_start; mov (1) mb_msg0.8<1>:UD mb_msg_tmp.8<0,1,0>:ud {align1}; /* Read MV for MB B */ /* bind index 3, read 2 oword (16bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ mov (2) mbb_result.4<1>:ud mb_mv0.0<2,2,1>:ud {align1}; mov (1) mbb_result.16<1>:w MB_PRED_FLAG {align1}; mbc_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_C:uw {align1}; /* MB C doesn't exist. Zero MV. mba_flag is zero */ /* Based on h264 spec the MB D will be replaced if MB C doesn't exist */ (f0.0) jmpi (1) mbd_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) mb_msg_tmp.8<1>:ud mb_msg0.8<0,1,0>:ud {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_0, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ and.z.f0.0 (1) null<1>:ud mb_mode_wb.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (-f0.0) jmpi (1) mb_mvp_start; mov (1) mb_msg0.8<1>:UD mb_msg_tmp.8<0,1,0>:ud {align1}; /* Read MV for MB C */ /* bind index 3, read 2 oword (16bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv0.0<2,2,1>:ud {align1}; mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1}; jmpi (1) mb_mvp_start; mbd_start: mov (8) mb_msg0.0<1>:ud 0:ud {align1}; and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_D:uw {align1}; (f0.0) jmpi (1) mb_mvp_start; mov (1) mbc_result.0<1>:d MB_AVAIL {align1}; mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1}; add (2) tmp_reg0.0<1>:w tmp_reg0.0<2,2,1>:w -1:w {align1}; mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1}; mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1}; mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */ mov (1) mb_msg_tmp.8<1>:ud mb_msg0.8<0,1,0>:ud {align1}; add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; /* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_0, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; and.z.f0.0 (1) null<1>:ud mb_mode_wb.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0) mov (2) mbc_result.20<1>:w -1:w {align1}; (-f0.0) jmpi (1) mb_mvp_start; mov (1) mb_msg0.8<1>:UD mb_msg_tmp.8<0,1,0>:ud {align1}; /* Read MV for MB D */ /* bind index 3, read 2 oword (16bytes), msg type: 0(OWord Block Read) */ send (16) mb_ind mb_mv0.0<1>:ub NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_TYPE, OBR_CONTROL_2, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; /* TODO: RefID is required after multi-references are added */ /* Forward MV */ mov (2) mbc_result.4<1>:ud mb_mv0.0<2,2,1>:ud {align1}; mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1}; mb_mvp_start: /*TODO: Add the skip prediction */ /* Check whether both MB B and C are invailable */ add (1) tmp_reg0.0<1>:d mbb_result.0<0,1,0>:d mbc_result.0<0,1,0>:d {align1}; cmp.z.f0.0 (1) null:d tmp_reg0.0<0,1,0>:d 0:d {align1}; (-f0.0) jmpi (1) mb_median_start; cmp.nz.f0.0 (1) null:d mba_result.0<0,1,0>:d 0:d {align1}; (f0.0) mov (1) mbb_result.4<1>:ud mba_result.4<0,1,0>:ud {align1}; (f0.0) mov (1) mbc_result.4<1>:ud mba_result.4<0,1,0>:ud {align1}; (f0.0) mov (1) mbb_result.20<1>:uw mba_result.20<0,1,0>:uw {align1}; (f0.0) mov (1) mbc_result.20<1>:uw mba_result.20<0,1,0>:uw {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud mba_result.4<0,1,0>:ud {align1}; (-f0.0) mov (1) mb_mvp_ref.0<1>:ud 0:ud {align1}; jmpi (1) __mb_hwdep_end; mb_median_start: /* check whether only one neighbour MB has the same ref ID with the current MB */ mov (8) tmp_reg0.0<1>:ud 0:ud {align1}; cmp.z.f0.0 (1) null:d mba_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbb_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.4<0,1,0>:ud {align1}; cmp.z.f0.0 (1) null:d mbc_result.20<1>:w 0:w {align1}; (f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.4<0,1,0>:ud {align1}; cmp.e.f0.0 (1) null:d tmp_reg0.0<1>:w 1:w {align1}; (f0.0) mov (1) mb_mvp_ref.0<1>:ud tmp_reg0.4<0,1,0>:ud {align1}; (f0.0) jmpi (1) __mb_hwdep_end; mov (1) INPUT_ARG0.0<1>:w mba_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.4<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.4<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.0<1>:w RET_ARG<0,1,0>:w {align1}; mov (1) INPUT_ARG0.0<1>:w mba_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.4<1>:w mbb_result.6<0,1,0>:w {align1}; mov (1) INPUT_ARG0.8<1>:w mbc_result.6<0,1,0>:w {align1}; SAVE_RET {align1}; jmpi (1) word_imedian; mov (1) mb_mvp_ref.2<1>:w RET_ARG<0,1,0>:w {align1}; __mb_hwdep_end: mov (2) mv_cc_ref.0<1>:w mba_result.4<2,2,1>:w {align1}; /* Calibrate the ref window for MPEG2 */ mov (1) vme_m0.0<1>:W -16:W {align1}; mov (1) vme_m0.2<1>:W -12:W {align1}; mov (1) INPUT_ARG0.0<1>:ud vme_m0.0<0,1,0>:ud {align1}; mov (1) INPUT_ARG0.8<1>:ud vme_m0.8<0,1,0>:ud {align1}; mov (8) INPUT_ARG1.0<1>:ud pic_ref.0<8,8,1>:ud {align1}; SAVE_RET {align1}; jmpi (1) ref_boundary_check; mov (2) vme_m0.0<1>:w RET_ARG<2,2,1>:w {align1}; /* m2 */ mov (8) vme_msg_2<1>:UD 0x0:UD {align1}; /* m3 */ mov (8) vme_msg_3<1>:UD 0x0:UD {align1}; /* Use the Luma mode */ mov (1) tmp_reg0.0<1>:UW INTRA16_DC_PRED:UW {align1}; mov (1) vme_msg_3.4<1>:ub tmp_reg0.0<0,1,0>:UB {align1}; /* m4 */ mov (8) vme_msg_4<1>:UD 0x0:UD {align1}; mov (1) vme_msg_4.16<1>:UD INTRA_PREDICTORE_MODE {align1}; /* m1 */ mov (8) vme_m1.0<1>:ud 0x0:ud {align1}; mov (1) intra_flag<1>:UW 0x0:UW {align1} ; mov (1) tmp_reg0.0<1>:uw LUMA_INTRA_8x8_DISABLE:uw {align1}; add (1) tmp_reg0.0<1>:uw tmp_reg0.0<0,1,0>:uw LUMA_INTRA_4x4_DISABLE:uw {align1}; mov (1) intra_part_mask_ub<1>:UB tmp_reg0.0<0,1,0>:ub {align1}; /* m1 */ /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; /* M0 */ /* IME search */ mov (1) vme_m0.12<1>:UD SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_HALF:UD {align1}; /* 16x16 Source, 1/2 pixel, harr */ mov (1) vme_m0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 48x40 */ mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; add (2) vme_m0.0<1>:w vme_m0.0<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; add (2) vme_m0.4<1>:w vme_m0.4<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; /* m1 */ mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; /* MV num is passed by constant buffer. R4.28 */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; add (1) vme_m1.4<1>:UD vme_m1.4<0,1,0>:UD FB_PRUNING_DISABLE:UD {align1}; mov (1) vme_m1.8<1>:UD START_CENTER + SEARCH_PATH_LEN:UD {align1}; /* Bilinear filter */ mov (1) tmp_reg0.0<1>:uw 0x04:uw {align1}; add (1) vme_m1.30<1>:ub vme_m1.30<0,1,0>:ub tmp_reg0.0<0,1,0>:ub {align1}; /* Set the MV cost center */ mov (1) vme_m1.16<1>:ud mv_cc_ref.0<0,1,0>:ud {align1}; mov (1) vme_m1.20<1>:ud mv_cc_ref.0<0,1,0>:ud {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; send (8) vme_msg_ind vme_wb null vme( BIND_IDX_VME, 0, 0, VME_MESSAGE_TYPE_MIXED ) mlen vme_msg_length rlen vme_inter_wb_length {align1}; and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1}; (-f0.0) jmpi (1) vme_run_again; vme_mv_output: and.z.f0.0 (1) null<1>:ud vme_wb0.0<0,1,0>:ud INTRAMBFLAG_MASK:ud {align1} ; (-f0.0)jmpi (1) __INTRA_INFO ; __INTER_INFO: /* Write MV pairs */ mov (8) msg_reg0.0<1>:UD obw_m0.0<8,8,1>:UD {align1}; mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; /* bind index 3, write 8 oword (128 bytes), msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; mov (1) msg_reg1.0<1>:ud vme_wb0.0<0,1,0>:ud {align1} ; mov (1) msg_reg1.4<1>:UD vme_wb0.28<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:ud tmp_ud1<0,1,0>:ud {align1} ; mov (1) msg_reg1.12<1>:ud vme_wb0.0<0,1,0>:ud {align1} ; mov (1) msg_reg1.16<1>:ud 0x25:ud {align1} ; jmpi (1) __OUTPUT_INFO; __INTRA_INFO: mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1}; mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1}; mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1}; mov (1) msg_reg1.16<1>:ud 0x35:ud {align1} ; __OUTPUT_INFO: mov (1) msg_reg1.20<1>:ud obw_m0.8<0,1,0>:ud {align1}; add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD INTER_VME_OUTPUT_MV_IN_OWS:UD {align1}; mov (8) msg_reg0.0<1>:ud obw_m0.0<8,8,1>:ud {align1}; /* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */ send (16) msg_ind obw_wb null data_port( OBW_CACHE_TYPE, OBW_MESSAGE_TYPE, OBW_CONTROL_2, OBW_BIND_IDX, OBW_WRITE_COMMIT_CATEGORY, OBW_HEADER_PRESENT ) mlen 2 rlen obw_wb_length {align1}; /* Issue message fence so that the previous write message is committed */ send (16) mb_ind mb_wb.0<1>:ud NULL data_port( OBR_CACHE_TYPE, OBR_MESSAGE_FENCE, OBR_MF_COMMIT, OBR_BIND_IDX, OBR_WRITE_COMMIT_CATEGORY, OBR_HEADER_PRESENT ) mlen 1 rlen 1 {align1}; __EXIT: /* * kill thread */ mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1}; send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; nop ; nop ; word_imedian: cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_a_ge_b; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; jmpi (1) cmp_end; cmp_a_ge_b: cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1}; (f0.0) jmpi (1) cmp_end; cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1}; (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1}; (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1}; cmp_end: RETURN {align1}; nop; nop; ref_boundary_check: /* The left/up coordinate of reference window */ add (2) TEMP_VAR0.0<1>:w INPUT_ARG0.8<2,2,1>:w INPUT_ARG0.0<2,2,1>:w {align1}; /* The right/bottom coordinate of reference window */ add (1) TEMP_VAR0.16<1>:w TEMP_VAR0.0<0,1,0>:w 48:w {align1}; add (1) TEMP_VAR0.18<1>:w TEMP_VAR0.2<0,1,0>:w 40:w {align1}; /* Firstly the MV range is checked */ mul (2) TEMP_VAR1.16<1>:w INPUT_ARG1.16<2,2,1>:w -1:w {align1}; add (2) TEMP_VAR1.0<1>:w INPUT_ARG0.8<2,2,1>:w TEMP_VAR1.16<2,2,1>:w {align1}; add (2) TEMP_VAR1.4<1>:w INPUT_ARG0.8<2,2,1>:w INPUT_ARG1.16<2,2,1>:w {align1}; cmp.l.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w TEMP_VAR1.0<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.0<1>:w TEMP_VAR1.0<0,1,0>:w {align1}; cmp.g.f0.0 (1) null:w TEMP_VAR0.16<0,1,0>:w TEMP_VAR1.4<0,1,0>:w {align1}; (f0.0) add (1) TEMP_VAR0.0<1>:w TEMP_VAR1.4<0,1,0>:w -48:w {align1}; cmp.l.f0.0 (1) null:w TEMP_VAR0.2<0,1,0>:w TEMP_VAR1.2<0,1,0>:w {align1}; (f0.0) mov (1) TEMP_VAR0.2<1>:w TEMP_VAR1.2<0,1,0>:w {align1}; cmp.g.f0.0 (1) null:w TEMP_VAR0.18<0,1,0>:w TEMP_VAR1.6<0,1,0>:w {align1}; (f0.0) add (1) TEMP_VAR0.2<1>:w TEMP_VAR1.6<0,1,0>:w -40:w {align1}; x_left_cmp: cmp.l.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w 0:w {align1}; (-f0.0) jmpi (1) x_right_cmp; (f0.0) mov (1) TEMP_VAR0.0<1>:w 0:w {align1}; jmpi (1) y_top_cmp; x_right_cmp: cmp.g.f0.0 (1) null:w TEMP_VAR0.16<0,1,0>:w INPUT_ARG1.0<0,1,0>:w {align1}; (-f0.0) jmpi (1) y_top_cmp; (f0.0) add (1) TEMP_VAR0.0<1>:w INPUT_ARG1.0<0,1,0>:w -48:w {align1}; y_top_cmp: cmp.l.f0.0 (1) null:w TEMP_VAR0.2<0,1,0>:w 0:w {align1}; (-f0.0) jmpi (1) y_bottom_cmp; (f0.0) mov (1) TEMP_VAR0.2<1>:w 0:w {align1}; jmpi (1) y_bottom_end; y_bottom_cmp: cmp.g.f0.0 (1) null:w TEMP_VAR0.18<0,1,0>:w INPUT_ARG1.2<0,1,0>:w {align1}; (f0.0) add (1) TEMP_VAR0.2<1>:w INPUT_ARG1.2<0,1,0>:w -40:w {align1}; y_bottom_end: mul (2) TEMP_VAR1.0<1>:w INPUT_ARG0.8<2,2,1>:w -1:w {align1}; add (2) RET_ARG<1>:w TEMP_VAR0.0<2,2,1>:w TEMP_VAR1.0<2,2,1>:w {align1}; RETURN {align1}; nop; nop; vme_run_again: asr (2) mb_ref_win.0<1>:w mb_mvp_ref.0<2,2,1>:w 2:w {align1}; mov (2) tmp_reg0.0<1>:w mb_ref_win.0<2,2,1>:w {align1}; add (2) mb_ref_win.8<1>:w mb_ref_win.0<2,2,1>:w 3:w {align1}; and (2) mb_ref_win.16<1>:uw mb_ref_win.8<2,2,1>:uw 0xFFFC:uw {align1}; cmp.l.f0.0 (1) null:w tmp_reg0.0<0,1,0>:w 0:w {align1}; (f0.0) mul (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1}; cmp.l.f0.0 (1) null:w tmp_reg0.2<0,1,0>:w 0:w {align1}; (f0.0) mul (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1}; cmp.ge.f0.0 (1) null:w tmp_reg0.0<0,1,0>:w 4:w {align1}; (f0.0) jmpi (1) vme_start; cmp.ge.f0.0 (1) null:w tmp_reg0.2<0,1,0>:w 4:w {align1}; (f0.0) jmpi (1) vme_start; jmpi (1) vme_done; vme_start: mov (8) tmp_vme_wb0.0<1>:ud vme_wb0.0<8,8,1>:ud {align1}; mov (8) tmp_vme_wb1.0<1>:ud vme_wb1.0<8,8,1>:ud {align1}; /* Calibrate the ref window for MPEG2 */ mov (1) vme_m0.0<1>:W -16:W {align1}; mov (1) vme_m0.2<1>:W -12:W {align1}; mov (1) INPUT_ARG0.8<1>:ud vme_m0.8<0,1,0>:ud {align1}; add (2) INPUT_ARG0.0<1>:w vme_m0.0<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1}; mov (8) INPUT_ARG1.0<1>:ud pic_ref.0<8,8,1>:ud {align1}; SAVE_RET {align1}; jmpi (1) ref_boundary_check; mov (2) vme_m0.0<1>:w RET_ARG<2,2,1>:w {align1}; /* m2 */ mov (8) vme_msg_2<1>:UD 0x0:UD {align1}; /* m3 */ mov (8) vme_msg_3<1>:UD 0x0:UD {align1}; /* m4 */ mov (8) vme_msg_4<1>:UD 0x0:UD {align1}; /* m1 */ mov (8) vme_m1.0<1>:ud 0x0:ud {align1}; mov (1) intra_flag<1>:UW 0x0:UW {align1} ; mov (1) tmp_reg0.0<1>:uw LUMA_INTRA_8x8_DISABLE:uw {align1}; add (1) tmp_reg0.0<1>:uw tmp_reg0.0<0,1,0>:uw LUMA_INTRA_4x4_DISABLE:uw {align1}; mov (1) intra_part_mask_ub<1>:UB tmp_reg0.0<0,1,0>:ub {align1}; /* m1 */ /* assign MB intra struct from the thread payload*/ mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1}; /* M0 */ /* IME search */ mov (1) vme_m0.12<1>:UD SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_HALF:UD {align1}; /* 16x16 Source, 1/2 pixel, harr */ mov (1) vme_m0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 48x40 */ mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1}; mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1}; /* m1 */ mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ; /* MV num is passed by constant buffer. R4.28 */ mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1}; add (1) vme_m1.4<1>:UD vme_m1.4<0,1,0>:UD FB_PRUNING_DISABLE:UD {align1}; mov (1) vme_m1.8<1>:UD START_CENTER + SEARCH_PATH_LEN:UD {align1}; /* Bilinear filter */ mov (1) tmp_reg0.0<1>:uw 0x04:uw {align1}; add (1) vme_m1.30<1>:ub vme_m1.30<0,1,0>:ub tmp_reg0.0<0,1,0>:ub {align1}; /* Set the MV cost center */ mov (1) vme_m1.16<1>:ud mv_cc_ref.0<0,1,0>:ud {align1}; mov (1) vme_m1.20<1>:ud mv_cc_ref.0<0,1,0>:ud {align1}; mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1}; send (8) vme_msg_ind vme_wb null vme( BIND_IDX_VME, 0, 0, VME_MESSAGE_TYPE_INTER ) mlen vme_msg_length rlen vme_inter_wb_length {align1}; cmp.l.f0.0 (1) null:uw vme_wb0.6<0,1,0>:uw tmp_vme_wb0.6<0,1,0>:uw {align1}; (f0.0) jmpi (1) vme_done; mov (8) vme_wb0.0<1>:ud tmp_vme_wb0.0<8,8,1>:ud {align1}; mov (8) vme_wb1.0<1>:ud tmp_vme_wb1.0<8,8,1>:ud {align1}; vme_done: jmpi (1) vme_mv_output; nop; nop; nop; intel-driver-1.3.0/src/shaders/vme/mpeg2_inter_ivb.g7a000066400000000000000000000001151231401140700225670ustar00rootroot00000000000000#include "vme7.inc" #include "vme7_mpeg2.inc" #include "mpeg2_inter_ivb.asm" intel-driver-1.3.0/src/shaders/vme/mpeg2_inter_ivb.g7b000066400000000000000000000410541231401140700225770ustar00rootroot00000000000000 { 0x00800001, 0x24000061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24400061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24800061, 0x00000000, 0x00000000 }, { 0x00800001, 0x24c00061, 0x00000000, 0x00000000 }, { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 }, { 0x00000001, 0x24540231, 0x00000014, 0x00000000 }, { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 }, { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 }, { 0x00000041, 0x24880c21, 0x00000488, 0x0000000a }, { 0x00000001, 0x24940231, 0x00000014, 0x00000000 }, { 0x00200009, 0x2a402d29, 0x00450098, 0x00040004 }, { 0x00200001, 0x2a500129, 0x00450094, 0x00000000 }, { 0x00600001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2a800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2ae00061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b000061, 0x00000000, 0x00000000 }, { 0x00600001, 0x2b200061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002d28, 0x000000a6, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x000000f2 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00600060 }, { 0x00210001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00000001, 0x2ae000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24003dad, 0x00000400, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 }, { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 }, { 0x00310001, 0x2af401ed, 0x00000000, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02180203 }, { 0x00200001, 0x2ae40021, 0x00450ba0, 0x00000000 }, { 0x00000001, 0x2af001ed, 0x00000000, 0x00010001 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00100010 }, { 0x00210001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00210001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000076 }, { 0x00000001, 0x2b0000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 }, { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 }, { 0x00310001, 0x2b1401ed, 0x00000000, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02180203 }, { 0x00200001, 0x2b040021, 0x00450ba0, 0x00000000 }, { 0x00000001, 0x2b1001ed, 0x00000000, 0x00010001 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00080008 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000026 }, { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00000040, 0x24023dad, 0x00000402, 0xffffffff }, { 0x00000040, 0x24003dad, 0x00000400, 0x00010001 }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 }, { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 }, { 0x00310001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000032 }, { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 }, { 0x0a800031, 0x2ba01ca1, 0x00000b40, 0x02180203 }, { 0x00200001, 0x2b240021, 0x00450ba0, 0x00000000 }, { 0x00000001, 0x2b3001ed, 0x00000000, 0x00010001 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000028 }, { 0x00600001, 0x2b400061, 0x00000000, 0x00000000 }, { 0x01000005, 0x20002e28, 0x000000a5, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000022 }, { 0x00000001, 0x2b2000e5, 0x00000000, 0x00000001 }, { 0x00200001, 0x24000229, 0x004500a0, 0x00000000 }, { 0x00200040, 0x24003dad, 0x00450400, 0xffffffff }, { 0x00000041, 0x2b482521, 0x000000a2, 0x00000402 }, { 0x00000040, 0x2b482421, 0x00000b48, 0x00000400 }, { 0x00000041, 0x2b480c21, 0x00000b48, 0x0000000a }, { 0x00000001, 0x2b540231, 0x00000014, 0x00000000 }, { 0x00000001, 0x2b680021, 0x00000b48, 0x00000000 }, { 0x00000040, 0x2b480c21, 0x00000b48, 0x00000008 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x02180003 }, { 0x01000005, 0x20000c20, 0x00000b80, 0x00002000 }, { 0x00310001, 0x2b3401ed, 0x00000000, 0xffffffff }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000008 }, { 0x00000001, 0x2b480021, 0x00000b68, 0x00000000 }, { 0x0a800031, 0x2ba01cb1, 0x00000b40, 0x02180203 }, { 0x00200001, 0x2b240021, 0x00450ba0, 0x00000000 }, { 0x00000001, 0x2b3001ed, 0x00000000, 0x00010001 }, { 0x00000040, 0x240014a5, 0x00000b00, 0x00000b20 }, { 0x01000010, 0x20001ca4, 0x00000400, 0x00000000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000010 }, { 0x02000010, 0x20001ca4, 0x00000ae0, 0x00000000 }, { 0x00010001, 0x2b040021, 0x00000ae4, 0x00000000 }, { 0x00010001, 0x2b240021, 0x00000ae4, 0x00000000 }, { 0x00010001, 0x2b140129, 0x00000af4, 0x00000000 }, { 0x00010001, 0x2b340129, 0x00000af4, 0x00000000 }, { 0x00010001, 0x2ac00021, 0x00000ae4, 0x00000000 }, { 0x00110001, 0x2ac00061, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000032 }, { 0x00600001, 0x24000061, 0x00000000, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200af4, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000ae4, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b14, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b04, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200b34, 0x00000000 }, { 0x00010040, 0x24003dad, 0x00200400, 0x00010001 }, { 0x00010001, 0x24040021, 0x00000b24, 0x00000000 }, { 0x01000010, 0x20003da4, 0x00200400, 0x00010001 }, { 0x00010001, 0x2ac00021, 0x00000404, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000018 }, { 0x00000001, 0x2fa001ad, 0x00000ae4, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b04, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b24, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000008e }, { 0x00000001, 0x2ac001ad, 0x00000fe4, 0x00000000 }, { 0x00000001, 0x2fa001ad, 0x00000ae6, 0x00000000 }, { 0x00000001, 0x2fa401ad, 0x00000b06, 0x00000000 }, { 0x00000001, 0x2fa801ad, 0x00000b26, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000082 }, { 0x00000001, 0x2ac201ad, 0x00000fe4, 0x00000000 }, { 0x00200001, 0x2a2001ad, 0x00450ae4, 0x00000000 }, { 0x00000001, 0x244001ed, 0x00000000, 0xfff0fff0 }, { 0x00000001, 0x244201ed, 0x00000000, 0xfff4fff4 }, { 0x00000001, 0x2fa00021, 0x00000440, 0x00000000 }, { 0x00000001, 0x2fa80021, 0x00000448, 0x00000000 }, { 0x00600001, 0x2fc00021, 0x008d0a40, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000094 }, { 0x00200001, 0x244001ad, 0x00450fe4, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00bb00bb }, { 0x00000001, 0x28640231, 0x00000400, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00000001, 0x28900061, 0x00000000, 0x11111111 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00000001, 0x247c0169, 0x00000000, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00020002 }, { 0x00000040, 0x24002d29, 0x00000400, 0x00040004 }, { 0x00000001, 0x247c0231, 0x00000400, 0x00000000 }, { 0x00000001, 0x247d0231, 0x000000a5, 0x00000000 }, { 0x00000001, 0x244c0061, 0x00000000, 0x7e201000 }, { 0x00000001, 0x24560169, 0x00000000, 0x28302830 }, { 0x00000001, 0x24440021, 0x00000440, 0x00000000 }, { 0x00200040, 0x244035ad, 0x00450440, 0x00450a90 }, { 0x00200040, 0x244435ad, 0x00450444, 0x00450a90 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00000002 }, { 0x00000001, 0x24640231, 0x0000009c, 0x00000000 }, { 0x00000040, 0x24640c21, 0x00000464, 0x00000000 }, { 0x00000001, 0x24680061, 0x00000000, 0x30003030 }, { 0x00000001, 0x24000169, 0x00000000, 0x00040004 }, { 0x00000040, 0x247e4631, 0x0000047e, 0x00000400 }, { 0x00000001, 0x24700021, 0x00000a20, 0x00000000 }, { 0x00000001, 0x24740021, 0x00000a20, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x08600031, 0x21801cbd, 0x00000800, 0x0a686000 }, { 0x01000005, 0x20002d28, 0x000000a6, 0x00040004 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000096 }, { 0x01000005, 0x20000c20, 0x00000180, 0x00002000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000012 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d01a0, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x0000019c, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000544, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28300061, 0x00000000, 0x00000025 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000a }, { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, { 0x00000001, 0x28240021, 0x00000190, 0x00000000 }, { 0x00000001, 0x28280021, 0x00000194, 0x00000000 }, { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 }, { 0x00000001, 0x28300061, 0x00000000, 0x00000035 }, { 0x00000001, 0x28340021, 0x00000488, 0x00000000 }, { 0x00000040, 0x24880c21, 0x00000488, 0x00000008 }, { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x0a800031, 0x2b801ca1, 0x00000b40, 0x0219e003 }, { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001ca8, 0x00000e00, 0x82000010 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa4 }, { 0x00010020, 0x34001c00, 0x00001400, 0x0000000e }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa0, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000014 }, { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa4, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000000c }, { 0x04000010, 0x200035ac, 0x00000fa4, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa4, 0x00000000 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x04000010, 0x200035ac, 0x00000fa0, 0x00000fa8 }, { 0x00010001, 0x2fe401ad, 0x00000fa8, 0x00000000 }, { 0x00110001, 0x2fe401ad, 0x00000fa0, 0x00000000 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x00200040, 0x2f6035ad, 0x00450fa8, 0x00450fa0 }, { 0x00000040, 0x2f703dad, 0x00000f60, 0x00300030 }, { 0x00000040, 0x2f723dad, 0x00000f62, 0x00280028 }, { 0x00200041, 0x2f903dad, 0x00450fd0, 0xffffffff }, { 0x00200040, 0x2f8035ad, 0x00450fa8, 0x00450f90 }, { 0x00200040, 0x2f8435ad, 0x00450fa8, 0x00450fd0 }, { 0x05000010, 0x200035ac, 0x00000f60, 0x00000f80 }, { 0x00010001, 0x2f6001ad, 0x00000f80, 0x00000000 }, { 0x03000010, 0x200035ac, 0x00000f70, 0x00000f84 }, { 0x00010040, 0x2f603dad, 0x00000f84, 0xffd0ffd0 }, { 0x05000010, 0x200035ac, 0x00000f62, 0x00000f82 }, { 0x00010001, 0x2f6201ad, 0x00000f82, 0x00000000 }, { 0x03000010, 0x200035ac, 0x00000f72, 0x00000f86 }, { 0x00010040, 0x2f623dad, 0x00000f86, 0xffd8ffd8 }, { 0x05000010, 0x20003dac, 0x00000f60, 0x00000000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000004 }, { 0x00010001, 0x2f6001ed, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x03000010, 0x200035ac, 0x00000f70, 0x00000fc0 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00010040, 0x2f603dad, 0x00000fc0, 0xffd0ffd0 }, { 0x05000010, 0x20003dac, 0x00000f62, 0x00000000 }, { 0x00110020, 0x34001c00, 0x00001400, 0x00000004 }, { 0x00010001, 0x2f6201ed, 0x00000000, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0x00000004 }, { 0x03000010, 0x200035ac, 0x00000f72, 0x00000fc2 }, { 0x00010040, 0x2f623dad, 0x00000fc2, 0xffd8ffd8 }, { 0x00200041, 0x2f803dad, 0x00450fa8, 0xffffffff }, { 0x00200040, 0x2fe435ad, 0x00450f60, 0x00450f80 }, { 0x00000001, 0x34000020, 0x00000fe0, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0020000c, 0x2a803dad, 0x00450ac0, 0x00020002 }, { 0x00200001, 0x240001ad, 0x00450a80, 0x00000000 }, { 0x00200040, 0x2a883dad, 0x00450a80, 0x00030003 }, { 0x00200005, 0x2a902d29, 0x00450a88, 0xfffcfffc }, { 0x05000010, 0x20003dac, 0x00000400, 0x00000000 }, { 0x00010041, 0x24003dad, 0x00000400, 0xffffffff }, { 0x05000010, 0x20003dac, 0x00000402, 0x00000000 }, { 0x00010041, 0x24023dad, 0x00000402, 0xffffffff }, { 0x04000010, 0x20003dac, 0x00000400, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000006 }, { 0x04000010, 0x20003dac, 0x00000402, 0x00040004 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000002 }, { 0x00000020, 0x34001c00, 0x00001400, 0x0000004a }, { 0x00600001, 0x2c800021, 0x008d0180, 0x00000000 }, { 0x00600001, 0x2ca00021, 0x008d01a0, 0x00000000 }, { 0x00000001, 0x244001ed, 0x00000000, 0xfff0fff0 }, { 0x00000001, 0x244201ed, 0x00000000, 0xfff4fff4 }, { 0x00000001, 0x2fa80021, 0x00000448, 0x00000000 }, { 0x00200040, 0x2fa035ad, 0x00450440, 0x00450a90 }, { 0x00600001, 0x2fc00021, 0x008d0a40, 0x00000000 }, { 0x00000040, 0x2fe00c01, 0x00001400, 0x00000020 }, { 0x00000020, 0x34001c00, 0x00001400, 0xffffff94 }, { 0x00200001, 0x244001ad, 0x00450fe4, 0x00000000 }, { 0x00600001, 0x28400061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28600061, 0x00000000, 0x00000000 }, { 0x00600001, 0x28800061, 0x00000000, 0x00000000 }, { 0x00600001, 0x24600061, 0x00000000, 0x00000000 }, { 0x00000001, 0x247c0169, 0x00000000, 0x00000000 }, { 0x00000001, 0x24000169, 0x00000000, 0x00020002 }, { 0x00000040, 0x24002d29, 0x00000400, 0x00040004 }, { 0x00000001, 0x247c0231, 0x00000400, 0x00000000 }, { 0x00000001, 0x247d0231, 0x000000a5, 0x00000000 }, { 0x00000001, 0x244c0061, 0x00000000, 0x7e201000 }, { 0x00000001, 0x24560169, 0x00000000, 0x28302830 }, { 0x00000001, 0x24440021, 0x00000440, 0x00000000 }, { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 }, { 0x00000001, 0x24600061, 0x00000000, 0x00000002 }, { 0x00000001, 0x24640231, 0x0000009c, 0x00000000 }, { 0x00000040, 0x24640c21, 0x00000464, 0x00000000 }, { 0x00000001, 0x24680061, 0x00000000, 0x30003030 }, { 0x00000001, 0x24000169, 0x00000000, 0x00040004 }, { 0x00000040, 0x247e4631, 0x0000047e, 0x00000400 }, { 0x00000001, 0x24700021, 0x00000a20, 0x00000000 }, { 0x00000001, 0x24740021, 0x00000a20, 0x00000000 }, { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 }, { 0x08600031, 0x21801cbd, 0x00000800, 0x0a682000 }, { 0x05000010, 0x20002528, 0x00000186, 0x00000c86 }, { 0x00010020, 0x34001c00, 0x00001400, 0x00000004 }, { 0x00600001, 0x21800021, 0x008d0c80, 0x00000000 }, { 0x00600001, 0x21a00021, 0x008d0ca0, 0x00000000 }, { 0x00000020, 0x34001c00, 0x00001400, 0xffffff04 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, intel-driver-1.3.0/src/shaders/vme/vme.inc000066400000000000000000000176461231401140700204170ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: ME_header.inc // // Global symbols define // /* * Constant */ define(`VME_MESSAGE_TYPE_INTER', `1') define(`VME_MESSAGE_TYPE_INTRA', `2') define(`VME_MESSAGE_TYPE_MIXED', `3') define(`BLOCK_32X1', `0x0000001F') define(`BLOCK_4X16', `0x000F0003') define(`LUMA_INTRA_16x16_DISABLE', `0x1') define(`LUMA_INTRA_8x8_DISABLE', `0x2') define(`LUMA_INTRA_4x4_DISABLE', `0x4') define(`INTRA_PRED_AVAIL_FLAG_AE', `0x60') define(`INTRA_PRED_AVAIL_FLAG_B', `0x10') define(`INTRA_PRED_AVAIL_FLAG_C', `0x8') define(`INTRA_PRED_AVAIL_FLAG_D', `0x4') define(`BIND_IDX_VME', `0') define(`BIND_IDX_VME_REF0', `1') define(`BIND_IDX_VME_REF1', `2') define(`BIND_IDX_OUTPUT', `3') define(`BIND_IDX_INEP', `4') define(`SUB_PEL_MODE_INTEGER', `0x00000000') define(`SUB_PEL_MODE_HALF', `0x00001000') define(`SUB_PEL_MODE_QUARTER', `0x00003000') define(`INTER_SAD_NONE', `0x00000000') define(`INTER_SAD_HAAR', `0x00200000') define(`INTRA_SAD_NONE', `0x00000000') define(`INTRA_SAD_HAAR', `0x00800000') define(`INTER_PART_MASK', `0x00000000') define(`SEARCH_CTRL_SINGLE', `0x00000000') define(`SEARCH_CTRL_DUAL_START', `0x00000100') define(`SEARCH_CTRL_DUAL_RECORD', `0x00000300') define(`SEARCH_CTRL_DUAL_REFERENCE', `0x00000700') define(`REF_REGION_SIZE', `0x2830:UW') define(`BI_SUB_MB_PART_MASK', `0x0c000000') define(`MAX_NUM_MV', `0x00000020') define(`FB_PRUNING_ENABLE', `0x40000000') define(`SEARCH_PATH_LEN', `0x00003030') define(`START_CENTER', `0x30000000') define(`ADAPTIVE_SEARCH_ENABLE', `0x00000002') define(`INTRA_PREDICTORE_MODE', `0x11111111:UD') define(`INTER_VME_OUTPUT_IN_OWS', `10') define(`INTER_VME_OUTPUT_MV_IN_OWS', `8') define(`INTRAMBFLAG_MASK', `0x00002000') define(`MVSIZE_UW_BASE', `0x0040') define(`MFC_MV32_BIT_SHIFT', `5') define(`CBP_DC_YUV_UW', `0x000E') #ifdef DEV_SNB define(`MV32_BIT_MASK', `0x0010') define(`MV32_BIT_SHIFT', `4') define(`OBW_CACHE_TYPE', `5') #else define(`MV32_BIT_MASK', `0x0020') define(`MV32_BIT_SHIFT', `5') define(`OBW_CACHE_TYPE', `10') #endif define(`OBW_MESSAGE_TYPE', `8') define(`OBW_BIND_IDX', `BIND_IDX_OUTPUT') define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */ define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */ define(`OBW_CONTROL_2', `2') /* 2 OWords */ define(`OBW_CONTROL_3', `3') /* 4 OWords */ define(`OBW_CONTROL_4', `4') /* 8 OWords */ #ifdef DEV_SNB define(`OBW_WRITE_COMMIT_CATEGORY', `1') /* write commit on Sandybrige */ #else define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ #endif define(`OBW_HEADER_PRESENT', `1') /* GRF registers * r0 header * r1~r4 constant buffer (reserved) * r5 inline data * r6~r11 reserved * r12 write back of VME message * r13 write back of Oword Block Write */ /* * GRF 0 -- header */ define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ /* * GRF 1~4 -- Constant Buffer (reserved) */ /* * GRF 5 -- inline data */ define(`inline_reg0', `r5') define(`w_in_mb_uw', `inline_reg0.2') define(`orig_xy_ub', `inline_reg0.0') define(`orig_x_ub', `inline_reg0.0') /* in macroblock */ define(`orig_y_ub', `inline_reg0.1') define(`transform_8x8_ub', `inline_reg0.4') define(`slice_edge_ub', `inline_reg0.4') define(`num_macroblocks', `inline_reg0.6') /* * GRF 6~11 -- reserved */ /* * GRF 12~15 -- write back for VME message */ define(`vme_wb', `r12') define(`vme_wb0', `r12') define(`vme_wb1', `r13') define(`vme_wb2', `r14') define(`vme_wb3', `r15') #ifdef DEV_SNB /* * GRF 16 -- write back for Oword Block Write message with write commit bit */ define(`obw_wb', `r16') define(`obw_wb_length', `1') #else /* * GRF 16 -- write back for VME message */ define(`vme_wb4', `r16') define(`obw_wb', `null<1>:W') define(`obw_wb_length', `0') #endif /* * GRF 18~21 -- Intra Neighbor Edge Pixels */ define(`INEP_ROW', `r18') define(`INEP_COL0', `r20') define(`INEP_COL1', `r21') /* * temporary registers */ define(`tmp_reg0', `r32') define(`read0_header', `tmp_reg0') define(`tmp_reg1', `r33') define(`read1_header', `tmp_reg1') define(`tmp_reg2', `r34') define(`vme_m0', `tmp_reg2') define(`tmp_reg3', `r35') define(`vme_m1', `tmp_reg3') define(`intra_flag', `vme_m1.28') define(`intra_part_mask_ub', `vme_m1.28') define(`mb_intra_struct_ub', `vme_m1.29') define(`tmp_reg4', `r36') define(`obw_m0', `tmp_reg4') define(`tmp_reg5', `r37') define(`obw_m1', `tmp_reg5') define(`tmp_reg6', `r38') define(`obw_m2', `tmp_reg6') define(`tmp_reg7', `r39') define(`obw_m3', `tmp_reg7') define(`tmp_reg8', `r40') define(`obw_m4', `tmp_reg8') define(`tmp_reg9', `r41') define(`tmp_x_w', `tmp_reg9.0') define(`tmp_rega', `r42') define(`tmp_ud0', `tmp_rega.0') define(`tmp_ud1', `tmp_rega.4') define(`tmp_ud2', `tmp_rega.8') define(`tmp_ud3', `tmp_rega.12') define(`tmp_uw0', `tmp_rega.0') define(`tmp_uw1', `tmp_rega.2') define(`tmp_uw2', `tmp_rega.4') define(`tmp_uw3', `tmp_rega.6') define(`tmp_uw4', `tmp_rega.8') define(`tmp_uw5', `tmp_rega.10') define(`tmp_uw6', `tmp_rega.12') define(`tmp_uw7', `tmp_rega.14') /* * MRF registers */ #ifdef DEV_SNB define(`msg_ind', `0') define(`msg_reg0', `m0') /* m0 */ define(`msg_reg1', `m1') /* m1 */ define(`msg_reg2', `m2') /* m2 */ define(`msg_reg3', `m3') /* m3 */ define(`msg_reg4', `m4') /* m4 */ #else define(`msg_ind', `64') define(`msg_reg0', `g64') define(`msg_reg1', `g65') define(`msg_reg2', `g66') define(`msg_reg3', `g67') define(`msg_reg4', `g68') #endif /* * VME message payload */ #ifdef DEV_SNB define(`vme_msg_length', `4') define(`vme_inter_wb_length', `4') #else define(`vme_msg_length', `5') define(`vme_inter_wb_length', `6') #endif define(`vme_intra_wb_length', `1') define(`vme_msg_ind', `msg_ind') define(`vme_msg_0', `msg_reg0') define(`vme_msg_1', `msg_reg1') define(`vme_msg_2', `msg_reg2') #ifdef DEV_SNB define(`vme_msg_3', `vme_msg_2') define(`vme_msg_4', `msg_reg3') #else define(`vme_msg_3', `msg_reg3') define(`vme_msg_4', `msg_reg4') #endif intel-driver-1.3.0/src/shaders/vme/vme7.inc000066400000000000000000000243401231401140700204730ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: ME_header.inc // // Global symbols define // /* * Constant */ define(`VME_MESSAGE_TYPE_INTER', `1') define(`VME_MESSAGE_TYPE_INTRA', `2') define(`VME_MESSAGE_TYPE_MIXED', `3') define(`BLOCK_32X1', `0x0000001F') define(`BLOCK_4X16', `0x000F0003') define(`LUMA_INTRA_16x16_DISABLE', `0x1') define(`LUMA_INTRA_8x8_DISABLE', `0x2') define(`LUMA_INTRA_4x4_DISABLE', `0x4') define(`INTRA_PRED_AVAIL_FLAG_AE', `0x60') define(`INTRA_PRED_AVAIL_FLAG_B', `0x10') define(`INTRA_PRED_AVAIL_FLAG_C', `0x8') define(`INTRA_PRED_AVAIL_FLAG_D', `0x4') define(`BIND_IDX_VME', `0') define(`BIND_IDX_VME_REF0', `1') define(`BIND_IDX_VME_REF1', `2') define(`BIND_IDX_OUTPUT', `3') define(`BIND_IDX_INEP', `4') define(`SUB_PEL_MODE_INTEGER', `0x00000000') define(`SUB_PEL_MODE_HALF', `0x00001000') define(`SUB_PEL_MODE_QUARTER', `0x00003000') define(`INTER_SAD_NONE', `0x00000000') define(`INTER_SAD_HAAR', `0x00200000') define(`INTRA_SAD_NONE', `0x00000000') define(`INTRA_SAD_HAAR', `0x00800000') define(`INTER_PART_MASK', `0x00000000') define(`SEARCH_CTRL_SINGLE', `0x00000000') define(`SEARCH_CTRL_DUAL_START', `0x00000100') define(`SEARCH_CTRL_DUAL_RECORD', `0x00000300') define(`SEARCH_CTRL_DUAL_REFERENCE', `0x00000700') define(`REF_REGION_SIZE', `0x2830:UW') define(`BI_SUB_MB_PART_MASK', `0x0c000000') define(`MAX_NUM_MV', `0x00000020') define(`FB_PRUNING_ENABLE', `0x40000000') define(`FB_PRUNING_DISABLE', `0x00000000') define(`SEARCH_PATH_LEN', `0x00003030') define(`START_CENTER', `0x30000000') define(`ADAPTIVE_SEARCH_ENABLE', `0x00000002') define(`INTRA_PREDICTORE_MODE', `0x11111111:UD') define(`INTER_VME_OUTPUT_IN_OWS', `10') define(`INTER_VME_OUTPUT_MV_IN_OWS', `8') define(`INTRAMBFLAG_MASK', `0x00002000') define(`MVSIZE_UW_BASE', `0x0040') define(`MFC_MV32_BIT_SHIFT', `5') define(`CBP_DC_YUV_UW', `0x000E') define(`DC_HARR_ENABLE', `0x0000') define(`DC_HARR_DISABLE', `0x0020') define(`MV32_BIT_MASK', `0x0020') define(`MV32_BIT_SHIFT', `5') define(`OBW_CACHE_TYPE', `10') define(`OBW_MESSAGE_TYPE', `8') define(`OBW_BIND_IDX', `BIND_IDX_OUTPUT') define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */ define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */ define(`OBW_CONTROL_2', `2') /* 2 OWords */ define(`OBW_CONTROL_3', `3') /* 4 OWords */ define(`OBW_CONTROL_8', `4') /* 8 OWords */ define(`FME_REPART_ENABLE', `0x80000000') define(`FME_REPART_DISABLE', `0x00000000') define(`FME_SINGLE_PARTION', `0x00000000') define(`FME_MUL_PARTION', `0x00000008') define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ define(`OBW_HEADER_PRESENT', `1') /* GRF registers * r0 header * r1~r4 constant buffer (reserved) * r5 inline data * r6~r11 reserved * r12 write back of VME message * r13 write back of Oword Block Write */ /* * GRF 0 -- header */ define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ /* * GRF 1~4 -- Constant Buffer (reserved) */ /* * GRF 5 -- inline data */ define(`inline_reg0', `r5') define(`w_in_mb_uw', `inline_reg0.2') define(`orig_xy_ub', `inline_reg0.0') define(`orig_x_ub', `inline_reg0.0') /* in macroblock */ define(`orig_y_ub', `inline_reg0.1') define(`transform_8x8_ub', `inline_reg0.4') define(`input_mb_intra_ub', `inline_reg0.5') define(`num_macroblocks', `inline_reg0.6') /* * GRF 6~11 -- reserved */ /* * GRF 12~15 -- write back for VME message */ define(`vme_wb', `r12') define(`vme_wb0', `r12') define(`vme_wb1', `r13') define(`vme_wb2', `r14') define(`vme_wb3', `r15') define(`vme_wb4', `r16') define(`vme_wb5', `r17') define(`vme_wb6', `r18') /* * GRF 24 -- write for VME output message */ define(`obw_wb', `null<1>:W') define(`obw_wb_length', `0') /* * GRF 28~30 -- Intra Neighbor Edge Pixels */ define(`INEP_ROW', `r28') define(`INEP_COL0', `r29') define(`INEP_COL1', `r30') /* * temporary registers */ define(`tmp_reg0', `r32') define(`read0_header', `tmp_reg0') define(`tmp_reg1', `r33') define(`read1_header', `tmp_reg1') define(`tmp_reg2', `r34') define(`vme_m0', `tmp_reg2') define(`tmp_reg3', `r35') define(`vme_m1', `tmp_reg3') define(`intra_flag', `vme_m1.28') define(`intra_part_mask_ub', `vme_m1.28') define(`mb_intra_struct_ub', `vme_m1.29') define(`tmp_reg4', `r36') define(`obw_m0', `tmp_reg4') define(`tmp_reg5', `r37') define(`obw_m1', `tmp_reg5') define(`tmp_reg6', `r38') define(`obw_m2', `tmp_reg6') define(`tmp_reg7', `r39') define(`obw_m3', `tmp_reg7') define(`tmp_reg8', `r40') define(`obw_m4', `tmp_reg8') define(`tmp_reg9', `r41') define(`tmp_x_w', `tmp_reg9.0') define(`tmp_rega', `r42') define(`tmp_ud0', `tmp_rega.0') define(`tmp_ud1', `tmp_rega.4') define(`tmp_ud2', `tmp_rega.8') define(`tmp_ud3', `tmp_rega.12') define(`tmp_uw0', `tmp_rega.0') define(`tmp_uw1', `tmp_rega.2') define(`tmp_uw2', `tmp_rega.4') define(`tmp_uw3', `tmp_rega.6') define(`tmp_uw4', `tmp_rega.8') define(`tmp_uw5', `tmp_rega.10') define(`tmp_uw6', `tmp_rega.12') define(`tmp_uw7', `tmp_rega.14') define(`vme_m2', `r43') /* * MRF registers */ define(`msg_ind', `64') define(`msg_reg0', `r64') define(`msg_reg1', `r65') define(`msg_reg2', `r66') define(`msg_reg3', `r67') define(`msg_reg4', `r68') define(`msg_reg5', `r69') define(`msg_reg6', `r70') define(`msg_reg7', `r71') define(`msg_reg8', `r72') define(`msg_reg9', `r73') define(`ts_msg_ind', `112') define(`ts_msg_reg0', `r112') /* * VME message payload */ define(`vme_msg_length', `5') define(`vme_inter_wb_length', `6') define(`vme_intra_wb_length', `1') define(`vme_msg_ind', `msg_ind') define(`vme_msg_0', `msg_reg0') define(`vme_msg_1', `msg_reg1') define(`vme_msg_2', `msg_reg2') define(`vme_msg_3', `msg_reg3') define(`vme_msg_4', `msg_reg4') define(`vme_msg_5', `msg_reg5') define(`vme_msg_6', `msg_reg6') define(`vme_msg_7', `msg_reg7') define(`vme_msg_8', `msg_reg8') define(`vme_msg_9', `msg_reg9') define(`RETURN_REG', `r127.0') define(`RET_ARG', `r127.4') /* Now at most two registers are used for input parameter */ define(`INPUT_ARG0', `r125') define(`INPUT_ARG1', `r126') /* Two temporal registers are used in the function */ define(`TEMP_VAR0', `r123') define(`TEMP_VAR1', `r124') define(`OBR_MESSAGE_TYPE', `0') define(`OBR_CACHE_TYPE', `10') define(`OBR_BIND_IDX', `BIND_IDX_OUTPUT') define(`OBR_CONTROL_0', `0') /* 1 OWord, low 128 bits */ define(`OBR_CONTROL_1', `1') /* 1 OWord, high 128 bits */ define(`OBR_CONTROL_2', `2') /* 2 OWords */ define(`OBR_CONTROL_4', `3') /* 4 OWords */ define(`OBR_CONTROL_8', `4') /* 8 OWords */ define(`OBR_WRITE_COMMIT_CATEGORY', `0') /* category on SNB+ for Data port */ define(`OBR_HEADER_PRESENT', `1') define(`mb_hwdep', `r5.6') define(`MB_AVAIL', `1:d') define(`MB_PRED_FLAG', `1:w') define(`mb_pred_mode', `r85') define(`mb_mvp_ref', `r86') define(`mba_result', `r87') define(`mbb_result', `r88') define(`mbc_result', `r89') define(`mb_ind', `90') define(`mb_msg0', `r90') define(`mb_msg_tmp', `r91') define(`mb_wb', `r92') define(`mb_mode_wb', `r92') define(`mb_mv0', `r93') define(`mb_mv1', `r94') define(`mb_mv2', `r95') define(`mb_mv3', `r96') define(`mb_ref', `r97') define(`mb_ref_win', `r84') define(`DREF_REGION_SIZE', `0x2020:UW') define(`PRED_L0', `0x0':uw) define(`PRED_L1', `0x1':uw) define(`PRED_BI', `0x2':uw) define(`PRED_DIRECT', `0x3':uw) define(`PRED_MASK', `0x3':uw) /* The MAX search len per reference is 16 */ define(`DSEARCH_PATH_LEN', `0x00001212') define(`BI_WEIGHT', `0x20':uw) define(`DSTART_CENTER', `0x00000000') define(`INTER_MASK', `0x03') define(`INTER_16X16MODE', `0x0') define(`INTER_16X8MODE', `0x01') define(`INTER_8X16MODE', `0x02') define(`INTER_8X8MODE', `0x03') define(`INTER_BLOCK0', `0x0') define(`INTER_BLOCK1', `0x1') define(`INTER_BLOCK2', `0x2') define(`INTER_BLOCK3', `0x3') define(`INTER_16X8MODE', `0x01') define(`INTER_8X16MODE', `0x02') define(`OBR_MESSAGE_FENCE', `7') define(`OBR_MF_NOCOMMIT', `0') define(`OBR_MF_COMMIT', `0x20') intel-driver-1.3.0/src/shaders/vme/vme75.inc000066400000000000000000000253531231401140700205650ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: ME_header.inc // // Global symbols define // /* * Constant */ define(`VME_MESSAGE_TYPE_INTER', `1') define(`VME_MESSAGE_TYPE_INTRA', `2') define(`VME_MESSAGE_TYPE_MIXED', `3') define(`VME_SIC_MESSAGE_TYPE', `1') define(`VME_IME_MESSAGE_TYPE', `2') define(`VME_FBR_MESSAGE_TYPE', `3') define(`BLOCK_32X1', `0x0000001F') define(`BLOCK_4X16', `0x000F0003') define(`BLOCK_8X4', `0x00070003') define(`LUMA_INTRA_16x16_DISABLE', `0x1') define(`LUMA_INTRA_8x8_DISABLE', `0x2') define(`LUMA_INTRA_4x4_DISABLE', `0x4') define(`INTRA_PRED_AVAIL_FLAG_AE', `0x60') define(`INTRA_PRED_AVAIL_FLAG_B', `0x10') define(`INTRA_PRED_AVAIL_FLAG_C', `0x8') define(`INTRA_PRED_AVAIL_FLAG_D', `0x4') define(`BIND_IDX_VME', `0') define(`BIND_IDX_VME_REF0', `1') define(`BIND_IDX_VME_REF1', `2') define(`BIND_IDX_OUTPUT', `3') define(`BIND_IDX_INEP', `4') define(`SUB_PEL_MODE_INTEGER', `0x00000000') define(`SUB_PEL_MODE_HALF', `0x00001000') define(`SUB_PEL_MODE_QUARTER', `0x00003000') define(`INTER_SAD_NONE', `0x00000000') define(`INTER_SAD_HAAR', `0x00200000') define(`INTRA_SAD_NONE', `0x00000000') define(`INTRA_SAD_HAAR', `0x00800000') define(`INTER_PART_MASK', `0x00000000') define(`SEARCH_CTRL_SINGLE', `0x00000000') define(`SEARCH_CTRL_DUAL_START', `0x00000100') define(`SEARCH_CTRL_DUAL_RECORD', `0x00000300') define(`SEARCH_CTRL_DUAL_REFERENCE', `0x00000700') define(`REF_REGION_SIZE', `0x2830:UW') define(`BI_SUB_MB_PART_MASK', `0x0c000000') define(`MAX_NUM_MV', `0x00000020') define(`FB_PRUNING_ENABLE', `0x40000000') define(`SEARCH_PATH_LEN', `0x00003030') define(`START_CENTER', `0x30000000') define(`ADAPTIVE_SEARCH_ENABLE', `0x00000002') define(`INTRA_PREDICTORE_MODE', `0x11111111:UD') define(`INTER_VME_OUTPUT_IN_OWS', `10') define(`INTER_VME_OUTPUT_MV_IN_OWS', `8') define(`INTRAMBFLAG_MASK', `0x00002000') define(`MVSIZE_UW_BASE', `0x0040') define(`MFC_MV32_BIT_SHIFT', `5') define(`CBP_DC_YUV_UW', `0x000E') define(`DC_HARR_ENABLE', `0x0000') define(`DC_HARR_DISABLE', `0x0020') define(`MV32_BIT_MASK', `0x0020') define(`MV32_BIT_SHIFT', `5') define(`OBW_CACHE_TYPE', `10') define(`OBW_MESSAGE_TYPE', `8') define(`OBW_BIND_IDX', `BIND_IDX_OUTPUT') define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */ define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */ define(`OBW_CONTROL_2', `2') /* 2 OWords */ define(`OBW_CONTROL_3', `3') /* 4 OWords */ define(`OBW_CONTROL_8', `4') /* 8 OWords */ define(`FBR_BME_ENABLE', `0x00000000') define(`FBR_BME_DISABLE', `0x00040000') define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ define(`OBW_HEADER_PRESENT', `1') /* GRF registers * r0 header * r1~r4 constant buffer (reserved) * r5 inline data * r6~r11 reserved * r12 write back of VME message * r13 write back of Oword Block Write */ /* * GRF 0 -- header */ define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ /* * GRF 1~4 -- Constant Buffer (reserved) */ /* * GRF 5 -- inline data */ define(`inline_reg0', `r5') define(`w_in_mb_uw', `inline_reg0.2') define(`orig_xy_ub', `inline_reg0.0') define(`orig_x_ub', `inline_reg0.0') /* in macroblock */ define(`orig_y_ub', `inline_reg0.1') define(`transform_8x8_ub', `inline_reg0.4') define(`input_mb_intra_ub', `inline_reg0.5') define(`num_macroblocks', `inline_reg0.6') /* * GRF 6~11 -- reserved */ /* * GRF 12~15 -- write back for VME message */ define(`vme_wb', `r12') define(`vme_wb0', `r12') define(`vme_wb1', `r13') define(`vme_wb2', `r14') define(`vme_wb3', `r15') define(`vme_wb4', `r16') define(`vme_wb5', `r17') define(`vme_wb6', `r18') define(`vme_ime_wb7', `r19') define(`vme_ime_wb8', `r20') define(`vme_ime_wb9', `r21') define(`vme_ime_wb10', `r22') /* * GRF 24 -- write for VME output message */ define(`obw_wb', `null<1>:W') define(`obw_wb_length', `0') /* * GRF 28~30 -- Intra Neighbor Edge Pixels */ define(`INEP_ROW', `r28') define(`INEP_COL0', `r29') define(`INEP_COL1', `r30') /* * GRF 48~50 -- Chroma Neighbor Edge Pixels */ define(`CHROMA_ROW', `r48') define(`CHROMA_COL', `r49') /* * temporary registers */ define(`tmp_reg0', `r32') define(`read0_header', `tmp_reg0') define(`tmp_reg1', `r33') define(`read1_header', `tmp_reg1') define(`tmp_reg2', `r34') define(`vme_m0', `tmp_reg2') define(`tmp_reg3', `r35') define(`vme_m1', `tmp_reg3') define(`intra_flag', `vme_m1.28') define(`intra_part_mask_ub', `vme_m1.28') define(`mb_intra_struct_ub', `vme_m1.29') define(`tmp_reg4', `r36') define(`obw_m0', `tmp_reg4') define(`tmp_reg5', `r37') define(`obw_m1', `tmp_reg5') define(`tmp_reg6', `r38') define(`obw_m2', `tmp_reg6') define(`tmp_reg7', `r39') define(`obw_m3', `tmp_reg7') define(`tmp_reg8', `r40') define(`obw_m4', `tmp_reg8') define(`tmp_reg9', `r41') define(`tmp_x_w', `tmp_reg9.0') define(`tmp_rega', `r42') define(`tmp_ud0', `tmp_rega.0') define(`tmp_ud1', `tmp_rega.4') define(`tmp_ud2', `tmp_rega.8') define(`tmp_ud3', `tmp_rega.12') define(`tmp_uw0', `tmp_rega.0') define(`tmp_uw1', `tmp_rega.2') define(`tmp_uw2', `tmp_rega.4') define(`tmp_uw3', `tmp_rega.6') define(`tmp_uw4', `tmp_rega.8') define(`tmp_uw5', `tmp_rega.10') define(`tmp_uw6', `tmp_rega.12') define(`tmp_uw7', `tmp_rega.14') define(`vme_m2', `r43') /* * MRF registers */ define(`msg_ind', `64') define(`msg_reg0', `r64') define(`msg_reg1', `r65') define(`msg_reg2', `r66') define(`msg_reg3', `r67') define(`msg_reg4', `r68') define(`msg_reg5', `r69') define(`msg_reg6', `r70') define(`msg_reg7', `r71') define(`msg_reg8', `r72') define(`msg_reg9', `r73') define(`ts_msg_ind', `112') define(`ts_msg_reg0', `r112') /* * VME message payload */ define(`vme_intra_wb_length', `1') define(`vme_wb_length', `7') define(`sic_vme_msg_length', `7') define(`fbr_vme_msg_length', `7') define(`ime_vme_msg_length', `5') define(`vme_msg_ind', `msg_ind') define(`vme_msg_0', `msg_reg0') define(`vme_msg_1', `msg_reg1') define(`vme_msg_2', `msg_reg2') define(`vme_msg_3', `msg_reg3') define(`vme_msg_4', `msg_reg4') define(`vme_msg_5', `msg_reg5') define(`vme_msg_6', `msg_reg6') define(`vme_msg_7', `msg_reg7') define(`vme_msg_8', `msg_reg8') define(`vme_msg_9', `msg_reg9') define(`BIND_IDX_CBCR', `6') define(`LUMA_CHROMA_MODE', `0x0') define(`LUMA_INTRA_MODE', `0x1') define(`LUMA_INTRA_DISABLE', `0x2') define(`RETURN_REG', `r127.0') define(`RET_ARG', `r127.4') /* Now at most two registers are used for input parameter */ define(`INPUT_ARG0', `r125') define(`INPUT_ARG1', `r126') /* Two temporal registers are used in the function */ define(`TEMP_VAR0', `r123') define(`TEMP_VAR1', `r124') define(`OBR_MESSAGE_TYPE', `0') define(`OBR_CACHE_TYPE', `10') define(`OBR_BIND_IDX', `BIND_IDX_OUTPUT') define(`OBR_CONTROL_0', `0') /* 1 OWord, low 128 bits */ define(`OBR_CONTROL_1', `1') /* 1 OWord, high 128 bits */ define(`OBR_CONTROL_2', `2') /* 2 OWords */ define(`OBR_CONTROL_4', `3') /* 4 OWords */ define(`OBR_CONTROL_8', `4') /* 8 OWords */ define(`OBR_WRITE_COMMIT_CATEGORY', `0') /* category on SNB+ for Data port */ define(`OBR_HEADER_PRESENT', `1') define(`mb_hwdep', `r5.6') define(`MB_AVAIL', `1:d') define(`MB_PRED_FLAG', `1:w') define(`mb_pred_mode', `r85') define(`mb_mvp_ref', `r86') define(`mba_result', `r87') define(`mbb_result', `r88') define(`mbc_result', `r89') define(`mb_ind', `90') define(`mb_msg0', `r90') define(`mb_wb', `r91') define(`mb_intra_wb', `r91') define(`mb_inter_wb', `r92') define(`mb_mv0', `r93') define(`mb_mv1', `r94') define(`mb_mv2', `r95') define(`mb_mv3', `r96') define(`mb_ref', `r97') define(`mb_ref_win', `r84') define(`DREF_REGION_SIZE', `0x2020:UW') define(`PRED_L0', `0x0':uw) define(`PRED_L1', `0x1':uw) define(`PRED_BI', `0x2':uw) define(`PRED_DIRECT', `0x3':uw) define(`PRED_MASK', `0x3':uw) /* The MAX search len per reference is 16 */ define(`DSEARCH_PATH_LEN', `0x00001212') define(`BI_WEIGHT', `0x20':uw) define(`DSTART_CENTER', `0x00000000') define(`INTER_MASK', `0x03') define(`INTER_16X16MODE', `0x0') define(`INTER_16X8MODE', `0x01') define(`INTER_8X16MODE', `0x02') define(`INTER_8X8MODE', `0x03') define(`INTER_BLOCK0', `0x0') define(`INTER_BLOCK1', `0x1') define(`INTER_BLOCK2', `0x2') define(`INTER_BLOCK3', `0x3') define(`INTER_16X8MODE', `0x01') define(`INTER_8X16MODE', `0x02') define(`OBR_MESSAGE_FENCE', `7') define(`OBR_MF_NOCOMMIT', `0') define(`OBR_MF_COMMIT', `0x20') intel-driver-1.3.0/src/shaders/vme/vme75_mpeg2.inc000066400000000000000000000017041231401140700216510ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: ME_header.inc // // Global symbols define // /* * Constant */ define(`INTER_PART_MASK', `0x7e000000') define(`mpeg2_ref', `r83') define(`pic_ref', `r82') define(`INTRA16_DC_PRED', `0xBB') /* Cost center ref */ define(`mv_cc_ref', `r81') define(`tmp_vme_wb0', `r100') define(`tmp_vme_wb1', `r101') define(`tmp_vme_wb2', `r102') define(`tmp_vme_wb3', `r103') define(`tmp_vme_wb4', `r104') define(`tmp_vme_wb5', `r105') define(`tmp_vme_wb6', `r106') define(`tmp_vme_wb7', `r107') define(`tmp_vme_wb8', `r108') define(`tmp_vme_wb9', `r109') intel-driver-1.3.0/src/shaders/vme/vme7_mpeg2.inc000066400000000000000000000017061231401140700215660ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: ME_header.inc // // Global symbols define // /* * Constant */ define(`INTER_PART_MASK', `0x7e000000') define(`mpeg2_ref', `r83') define(`pic_ref', `r82') define(`INTRA16_DC_PRED', `0xBB') /* Cost center ref */ define(`mv_cc_ref', `r81') define(`tmp_vme_wb0', `r100') define(`tmp_vme_wb1', `r101') define(`tmp_vme_wb2', `r102') define(`tmp_vme_wb3', `r103') define(`tmp_vme_wb4', `r104') define(`tmp_vme_wb5', `r105') define(`tmp_vme_wb6', `r106') define(`tmp_vme_wb7', `r107') define(`tmp_vme_wb8', `r108') define(`tmp_vme_wb9', `r109') intel-driver-1.3.0/src/shaders/vme/vme8.inc000066400000000000000000000254341231401140700205010ustar00rootroot00000000000000/* * Copyright © <2010>, Intel Corporation. * * This program is licensed under the terms and conditions of the * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at * http://www.opensource.org/licenses/eclipse-1.0.php. * */ // Modual name: ME_header.inc for Gen8 // // Global symbols define // /* * Constant */ define(`VME_MESSAGE_TYPE_INTER', `1') define(`VME_MESSAGE_TYPE_INTRA', `2') define(`VME_MESSAGE_TYPE_MIXED', `3') define(`VME_SIC_MESSAGE_TYPE', `1') define(`VME_IME_MESSAGE_TYPE', `2') define(`VME_FBR_MESSAGE_TYPE', `3') define(`BLOCK_32X1', `0x0000001F') define(`BLOCK_4X16', `0x000F0003') define(`BLOCK_8X4', `0x00070003') define(`LUMA_INTRA_16x16_DISABLE', `0x1') define(`LUMA_INTRA_8x8_DISABLE', `0x2') define(`LUMA_INTRA_4x4_DISABLE', `0x4') define(`INTRA_PRED_AVAIL_FLAG_AE', `0x60') define(`INTRA_PRED_AVAIL_FLAG_B', `0x10') define(`INTRA_PRED_AVAIL_FLAG_C', `0x8') define(`INTRA_PRED_AVAIL_FLAG_D', `0x4') define(`BIND_IDX_VME', `0') define(`BIND_IDX_VME_REF0', `1') define(`BIND_IDX_VME_REF1', `2') define(`BIND_IDX_OUTPUT', `3') define(`BIND_IDX_INEP', `4') define(`SUB_PEL_MODE_INTEGER', `0x00000000') define(`SUB_PEL_MODE_HALF', `0x00001000') define(`SUB_PEL_MODE_QUARTER', `0x00003000') define(`INTER_SAD_NONE', `0x00000000') define(`INTER_SAD_HAAR', `0x00200000') define(`INTRA_SAD_NONE', `0x00000000') define(`INTRA_SAD_HAAR', `0x00800000') define(`INTER_PART_MASK', `0x00000000') define(`SEARCH_CTRL_SINGLE', `0x00000000') define(`SEARCH_CTRL_DUAL_START', `0x00000100') define(`SEARCH_CTRL_DUAL_RECORD', `0x00000300') define(`SEARCH_CTRL_DUAL_REFERENCE', `0x00000700') define(`REF_REGION_SIZE', `0x2830:UW') define(`BI_SUB_MB_PART_MASK', `0x0c000000') define(`MAX_NUM_MV', `0x00000020') define(`FB_PRUNING_ENABLE', `0x40000000') define(`SEARCH_PATH_LEN', `0x00003030') define(`START_CENTER', `0x30000000') define(`ADAPTIVE_SEARCH_ENABLE', `0x00000002') define(`INTRA_PREDICTORE_MODE', `0x11111111:UD') define(`INTER_VME_OUTPUT_IN_OWS', `10') define(`INTER_VME_OUTPUT_MV_IN_OWS', `8') define(`INTRAMBFLAG_MASK', `0x00002000') define(`MVSIZE_UW_BASE', `0x0040') define(`MFC_MV32_BIT_SHIFT', `5') define(`CBP_DC_YUV_UW', `0x000E') define(`DC_HARR_ENABLE', `0x0000') define(`DC_HARR_DISABLE', `0x0020') define(`MV32_BIT_MASK', `0x0020') define(`MV32_BIT_SHIFT', `5') define(`OBW_CACHE_TYPE', `10') define(`OBW_MESSAGE_TYPE', `8') define(`OBW_BIND_IDX', `BIND_IDX_OUTPUT') define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */ define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */ define(`OBW_CONTROL_2', `2') /* 2 OWords */ define(`OBW_CONTROL_3', `3') /* 4 OWords */ define(`OBW_CONTROL_8', `4') /* 8 OWords */ define(`FBR_BME_ENABLE', `0x00000000') define(`FBR_BME_DISABLE', `0x00040000') define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ define(`OBW_HEADER_PRESENT', `1') /* GRF registers * r0 header * r1~r4 constant buffer (reserved) * r5 inline data * r6~r11 reserved * r12 write back of VME message * r13 write back of Oword Block Write */ /* * GRF 0 -- header */ define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ /* * GRF 1~4 -- Constant Buffer (reserved) */ /* * GRF 5 -- inline data */ define(`inline_reg0', `r5') define(`w_in_mb_uw', `inline_reg0.2') define(`orig_xy_ub', `inline_reg0.0') define(`orig_x_ub', `inline_reg0.0') /* in macroblock */ define(`orig_y_ub', `inline_reg0.1') define(`transform_8x8_ub', `inline_reg0.4') define(`input_mb_intra_ub', `inline_reg0.5') define(`num_macroblocks', `inline_reg0.6') /* * GRF 6~11 -- reserved */ /* * GRF 12~15 -- write back for VME message */ define(`vme_wb', `r12') define(`vme_wb0', `r12') define(`vme_wb1', `r13') define(`vme_wb2', `r14') define(`vme_wb3', `r15') define(`vme_wb4', `r16') define(`vme_wb5', `r17') define(`vme_wb6', `r18') define(`vme_ime_wb7', `r19') define(`vme_ime_wb8', `r20') define(`vme_ime_wb9', `r21') define(`vme_ime_wb10', `r22') /* * GRF 24 -- write for VME output message */ define(`obw_wb', `null<1>:W') define(`obw_wb_length', `0') /* * GRF 28~30 -- Intra Neighbor Edge Pixels */ define(`INEP_ROW', `r28') define(`INEP_COL0', `r29') define(`INEP_COL1', `r30') /* * GRF 48~50 -- Chroma Neighbor Edge Pixels */ define(`CHROMA_ROW', `r48') define(`CHROMA_COL', `r49') /* * temporary registers */ define(`tmp_reg0', `r32') define(`read0_header', `tmp_reg0') define(`tmp_reg1', `r33') define(`read1_header', `tmp_reg1') define(`tmp_reg2', `r34') define(`vme_m0', `tmp_reg2') define(`tmp_reg3', `r35') define(`vme_m1', `tmp_reg3') define(`intra_flag', `vme_m1.28') define(`intra_part_mask_ub', `vme_m1.28') define(`mb_intra_struct_ub', `vme_m1.29') define(`tmp_reg4', `r36') define(`obw_m0', `tmp_reg4') define(`tmp_reg5', `r37') define(`obw_m1', `tmp_reg5') define(`tmp_reg6', `r38') define(`obw_m2', `tmp_reg6') define(`tmp_reg7', `r39') define(`obw_m3', `tmp_reg7') define(`tmp_reg8', `r40') define(`obw_m4', `tmp_reg8') define(`tmp_reg9', `r41') define(`tmp_x_w', `tmp_reg9.0') define(`tmp_rega', `r42') define(`tmp_ud0', `tmp_rega.0') define(`tmp_ud1', `tmp_rega.4') define(`tmp_ud2', `tmp_rega.8') define(`tmp_ud3', `tmp_rega.12') define(`tmp_uw0', `tmp_rega.0') define(`tmp_uw1', `tmp_rega.2') define(`tmp_uw2', `tmp_rega.4') define(`tmp_uw3', `tmp_rega.6') define(`tmp_uw4', `tmp_rega.8') define(`tmp_uw5', `tmp_rega.10') define(`tmp_uw6', `tmp_rega.12') define(`tmp_uw7', `tmp_rega.14') define(`vme_m2', `r43') define(`vme_m3', `r44') /* * MRF registers */ define(`msg_ind', `64') define(`msg_reg0', `r64') define(`msg_reg1', `r65') define(`msg_reg2', `r66') define(`msg_reg3', `r67') define(`msg_reg4', `r68') define(`msg_reg5', `r69') define(`msg_reg6', `r70') define(`msg_reg7', `r71') define(`msg_reg8', `r72') define(`msg_reg9', `r73') define(`ts_msg_ind', `112') define(`ts_msg_reg0', `r112') /* * VME message payload */ define(`vme_intra_wb_length', `1') define(`vme_wb_length', `7') define(`sic_vme_msg_length', `8') define(`fbr_vme_msg_length', `8') define(`ime_vme_msg_length', `6') define(`vme_msg_ind', `msg_ind') define(`vme_msg_0', `msg_reg0') define(`vme_msg_1', `msg_reg1') define(`vme_msg_2', `msg_reg2') define(`vme_msg_3', `msg_reg3') define(`vme_msg_4', `msg_reg4') define(`vme_msg_5', `msg_reg5') define(`vme_msg_6', `msg_reg6') define(`vme_msg_7', `msg_reg7') define(`vme_msg_8', `msg_reg8') define(`vme_msg_9', `msg_reg9') define(`BIND_IDX_CBCR', `6') define(`LUMA_CHROMA_MODE', `0x0') define(`LUMA_INTRA_MODE', `0x1') define(`LUMA_INTRA_DISABLE', `0x2') define(`RETURN_REG', `r127.0') define(`RET_ARG', `r127.4') /* Now at most two registers are used for input parameter */ define(`INPUT_ARG0', `r125') define(`INPUT_ARG1', `r126') /* Two temporal registers are used in the function */ define(`TEMP_VAR0', `r123') define(`TEMP_VAR1', `r124') define(`OBR_MESSAGE_TYPE', `0') define(`OBR_CACHE_TYPE', `10') define(`OBR_BIND_IDX', `BIND_IDX_OUTPUT') define(`OBR_CONTROL_0', `0') /* 1 OWord, low 128 bits */ define(`OBR_CONTROL_1', `1') /* 1 OWord, high 128 bits */ define(`OBR_CONTROL_2', `2') /* 2 OWords */ define(`OBR_CONTROL_4', `3') /* 4 OWords */ define(`OBR_CONTROL_8', `4') /* 8 OWords */ define(`OBR_WRITE_COMMIT_CATEGORY', `0') /* category on SNB+ for Data port */ define(`OBR_HEADER_PRESENT', `1') define(`mb_hwdep', `r5.6') define(`MB_AVAIL', `1:d') define(`MB_PRED_FLAG', `1:w') define(`mb_pred_mode', `r85') define(`mb_mvp_ref', `r86') define(`mba_result', `r87') define(`mbb_result', `r88') define(`mbc_result', `r89') define(`mb_ind', `90') define(`mb_msg0', `r90') define(`mb_wb', `r91') define(`mb_intra_wb', `r91') define(`mb_inter_wb', `r92') define(`mb_mv0', `r93') define(`mb_mv1', `r94') define(`mb_mv2', `r95') define(`mb_mv3', `r96') define(`mb_ref', `r97') define(`mb_ref_win', `r84') define(`DREF_REGION_SIZE', `0x2020:UW') define(`PRED_L0', `0x0':uw) define(`PRED_L1', `0x1':uw) define(`PRED_BI', `0x2':uw) define(`PRED_DIRECT', `0x3':uw) define(`PRED_MASK', `0x3':uw) /* The MAX search len per reference is 16 */ define(`DSEARCH_PATH_LEN', `0x00001212') define(`BI_WEIGHT', `0x20':uw) define(`DSTART_CENTER', `0x00000000') define(`INTER_MASK', `0x03') define(`INTER_16X16MODE', `0x0') define(`INTER_16X8MODE', `0x01') define(`INTER_8X16MODE', `0x02') define(`INTER_8X8MODE', `0x03') define(`INTER_BLOCK0', `0x0') define(`INTER_BLOCK1', `0x1') define(`INTER_BLOCK2', `0x2') define(`INTER_BLOCK3', `0x3') define(`INTER_16X8MODE', `0x01') define(`INTER_8X16MODE', `0x02') define(`OBR_MESSAGE_FENCE', `7') define(`OBR_MF_NOCOMMIT', `0') define(`OBR_MF_COMMIT', `0x20') intel-driver-1.3.0/src/sysdeps.h000066400000000000000000000027321231401140700165460ustar00rootroot00000000000000/* * Copyright (C) 2012 Intel Corporation. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef SYSDEPS_H #define SYSDEPS_H #ifdef ANDROID # include "config_android.h" #else #ifdef HAVE_CONFIG_H # include "config.h" #endif #endif /* ANDROID */ #include #include #include #include #include #include #endif /* SYSDEPS_H */ intel-driver-1.3.0/src/va_backend_compat.h000066400000000000000000000034211231401140700204700ustar00rootroot00000000000000/* * Copyright (C) 2012 Intel Corporation. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef VA_BACKEND_COMPAT_H #define VA_BACKEND_COMPAT_H #include #if VA_CHECK_VERSION(0,33,0) # include # define VA_CHECK_DRM_AUTH_TYPE(ctx, type) \ (((struct drm_state *)(ctx)->drm_state)->auth_type == (type)) #else # include # define VA_CHECK_DRM_AUTH_TYPE(ctx, type) \ (((struct dri_state *)(ctx)->dri_state)->driConnectedFlag == (type)) # define drm_state dri_state # define VA_DRM_AUTH_DRI1 VA_DRI1 # define VA_DRM_AUTH_DRI2 VA_DRI2 # define VA_DRM_AUTH_CUSTOM VA_DUMMY #endif #endif /* VA_BACKEND_COMPAT_H */ intel-driver-1.3.0/src/wayland-drm-client-protocol.h000066400000000000000000000143241231401140700224060ustar00rootroot00000000000000/* * Copyright © 2008-2011 Kristian Høgsberg * Copyright © 2010-2011 Intel Corporation * * Permission to use, copy, modify, distribute, and sell this * software and its documentation for any purpose is hereby granted * without fee, provided that\n the above copyright notice appear in * all copies and that both that copyright notice and this permission * notice appear in supporting documentation, and that the name of * the copyright holders not be used in advertising or publicity * pertaining to distribution of the software without specific, * written prior permission. The copyright holders make no * representations about the suitability of this software for any * purpose. It is provided "as is" without express or implied * warranty. * * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS * SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND * FITNESS, IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF * THIS SOFTWARE. */ #ifndef DRM_CLIENT_PROTOCOL_H #define DRM_CLIENT_PROTOCOL_H #ifdef __cplusplus extern "C" { #endif #include #include #include "wayland-client.h" struct wl_client; struct wl_resource; struct wl_drm; extern const struct wl_interface wl_drm_interface; #ifndef WL_DRM_ERROR_ENUM #define WL_DRM_ERROR_ENUM enum wl_drm_error { WL_DRM_ERROR_AUTHENTICATE_FAIL = 0, WL_DRM_ERROR_INVALID_FORMAT = 1, WL_DRM_ERROR_INVALID_NAME = 2, }; #endif /* WL_DRM_ERROR_ENUM */ #ifndef WL_DRM_FORMAT_ENUM #define WL_DRM_FORMAT_ENUM enum wl_drm_format { WL_DRM_FORMAT_C8 = 0x20203843, WL_DRM_FORMAT_RGB332 = 0x38424752, WL_DRM_FORMAT_BGR233 = 0x38524742, WL_DRM_FORMAT_XRGB4444 = 0x32315258, WL_DRM_FORMAT_XBGR4444 = 0x32314258, WL_DRM_FORMAT_RGBX4444 = 0x32315852, WL_DRM_FORMAT_BGRX4444 = 0x32315842, WL_DRM_FORMAT_ARGB4444 = 0x32315241, WL_DRM_FORMAT_ABGR4444 = 0x32314241, WL_DRM_FORMAT_RGBA4444 = 0x32314152, WL_DRM_FORMAT_BGRA4444 = 0x32314142, WL_DRM_FORMAT_XRGB1555 = 0x35315258, WL_DRM_FORMAT_XBGR1555 = 0x35314258, WL_DRM_FORMAT_RGBX5551 = 0x35315852, WL_DRM_FORMAT_BGRX5551 = 0x35315842, WL_DRM_FORMAT_ARGB1555 = 0x35315241, WL_DRM_FORMAT_ABGR1555 = 0x35314241, WL_DRM_FORMAT_RGBA5551 = 0x35314152, WL_DRM_FORMAT_BGRA5551 = 0x35314142, WL_DRM_FORMAT_RGB565 = 0x36314752, WL_DRM_FORMAT_BGR565 = 0x36314742, WL_DRM_FORMAT_RGB888 = 0x34324752, WL_DRM_FORMAT_BGR888 = 0x34324742, WL_DRM_FORMAT_XRGB8888 = 0x34325258, WL_DRM_FORMAT_XBGR8888 = 0x34324258, WL_DRM_FORMAT_RGBX8888 = 0x34325852, WL_DRM_FORMAT_BGRX8888 = 0x34325842, WL_DRM_FORMAT_ARGB8888 = 0x34325241, WL_DRM_FORMAT_ABGR8888 = 0x34324241, WL_DRM_FORMAT_RGBA8888 = 0x34324152, WL_DRM_FORMAT_BGRA8888 = 0x34324142, WL_DRM_FORMAT_XRGB2101010 = 0x30335258, WL_DRM_FORMAT_XBGR2101010 = 0x30334258, WL_DRM_FORMAT_RGBX1010102 = 0x30335852, WL_DRM_FORMAT_BGRX1010102 = 0x30335842, WL_DRM_FORMAT_ARGB2101010 = 0x30335241, WL_DRM_FORMAT_ABGR2101010 = 0x30334241, WL_DRM_FORMAT_RGBA1010102 = 0x30334152, WL_DRM_FORMAT_BGRA1010102 = 0x30334142, WL_DRM_FORMAT_YUYV = 0x56595559, WL_DRM_FORMAT_YVYU = 0x55595659, WL_DRM_FORMAT_UYVY = 0x59565955, WL_DRM_FORMAT_VYUY = 0x59555956, WL_DRM_FORMAT_AYUV = 0x56555941, WL_DRM_FORMAT_NV12 = 0x3231564e, WL_DRM_FORMAT_NV21 = 0x3132564e, WL_DRM_FORMAT_NV16 = 0x3631564e, WL_DRM_FORMAT_NV61 = 0x3136564e, WL_DRM_FORMAT_YUV410 = 0x39565559, WL_DRM_FORMAT_YVU410 = 0x39555659, WL_DRM_FORMAT_YUV411 = 0x31315559, WL_DRM_FORMAT_YVU411 = 0x31315659, WL_DRM_FORMAT_YUV420 = 0x32315559, WL_DRM_FORMAT_YVU420 = 0x32315659, WL_DRM_FORMAT_YUV422 = 0x36315559, WL_DRM_FORMAT_YVU422 = 0x36315659, WL_DRM_FORMAT_YUV444 = 0x34325559, WL_DRM_FORMAT_YVU444 = 0x34325659, }; #endif /* WL_DRM_FORMAT_ENUM */ struct wl_drm_listener { /** * device - device * @name: name */ void (*device)(void *data, struct wl_drm *wl_drm, const char *name); /** * format - format * @format: format */ void (*format)(void *data, struct wl_drm *wl_drm, uint32_t format); /** * authenticated - authenticated */ void (*authenticated)(void *data, struct wl_drm *wl_drm); }; static inline int wl_drm_add_listener(struct wl_drm *wl_drm, const struct wl_drm_listener *listener, void *data) { return wl_proxy_add_listener((struct wl_proxy *) wl_drm, (void (**)(void)) listener, data); } #define WL_DRM_AUTHENTICATE 0 #define WL_DRM_CREATE_BUFFER 1 #define WL_DRM_CREATE_PLANAR_BUFFER 2 static inline void wl_drm_set_user_data(struct wl_drm *wl_drm, void *user_data) { wl_proxy_set_user_data((struct wl_proxy *) wl_drm, user_data); } static inline void * wl_drm_get_user_data(struct wl_drm *wl_drm) { return wl_proxy_get_user_data((struct wl_proxy *) wl_drm); } static inline void wl_drm_destroy(struct wl_drm *wl_drm) { wl_proxy_destroy((struct wl_proxy *) wl_drm); } static inline void wl_drm_authenticate(struct wl_drm *wl_drm, uint32_t id) { wl_proxy_marshal((struct wl_proxy *) wl_drm, WL_DRM_AUTHENTICATE, id); } static inline struct wl_buffer * wl_drm_create_buffer(struct wl_drm *wl_drm, uint32_t name, int32_t width, int32_t height, uint32_t stride, uint32_t format) { struct wl_proxy *id; id = wl_proxy_create((struct wl_proxy *) wl_drm, &wl_buffer_interface); if (!id) return NULL; wl_proxy_marshal((struct wl_proxy *) wl_drm, WL_DRM_CREATE_BUFFER, id, name, width, height, stride, format); return (struct wl_buffer *) id; } static inline struct wl_buffer * wl_drm_create_planar_buffer(struct wl_drm *wl_drm, uint32_t name, int32_t width, int32_t height, uint32_t format, int32_t offset0, int32_t stride0, int32_t offset1, int32_t stride1, int32_t offset2, int32_t stride2) { struct wl_proxy *id; id = wl_proxy_create((struct wl_proxy *) wl_drm, &wl_buffer_interface); if (!id) return NULL; wl_proxy_marshal((struct wl_proxy *) wl_drm, WL_DRM_CREATE_PLANAR_BUFFER, id, name, width, height, format, offset0, stride0, offset1, stride1, offset2, stride2); return (struct wl_buffer *) id; } #ifdef __cplusplus } #endif #endif intel-driver-1.3.0/src/wayland/000077500000000000000000000000001231401140700163365ustar00rootroot00000000000000intel-driver-1.3.0/src/wayland/Makefile.am000066400000000000000000000024361231401140700203770ustar00rootroot00000000000000# Copyright (C) 2012 Intel Corporation. All Rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the # "Software"), to deal in the Software without restriction, including # without limitation the rights to use, copy, modify, merge, publish, # distribute, sub license, and/or sell copies of the Software, and to # permit persons to whom the Software is furnished to do so, subject to # the following conditions: # # The above copyright notice and this permission notice (including the # next paragraph) shall be included in all copies or substantial portions # of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. # IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR # ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, # TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE # SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. EXTRA_DIST = \ wayland-drm.xml \ $(NULL) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in intel-driver-1.3.0/src/wayland/wayland-drm.xml000066400000000000000000000151171231401140700213040ustar00rootroot00000000000000 Copyright © 2008-2011 Kristian Høgsberg Copyright © 2010-2011 Intel Corporation Permission to use, copy, modify, distribute, and sell this software and its documentation for any purpose is hereby granted without fee, provided that\n the above copyright notice appear in all copies and that both that copyright notice and this permission notice appear in supporting documentation, and that the name of the copyright holders not be used in advertising or publicity pertaining to distribution of the software without specific, written prior permission. The copyright holders make no representations about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.