inteltool-0.0+r4091.orig/0000700000175000017500000000000011167766061013257 5ustar uweuweinteltool-0.0+r4091.orig/inteltool.80000600000175000017500000000360211012653667015360 0ustar uweuwe.TH INTELTOOL 8 "May 14, 2008" .SH NAME inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters .SH SYNOPSIS .B inteltool \fR[\fB\-vh?grpmedPMa\fR] .SH DESCRIPTION .B inteltool is a handy little tool for dumping the configuration space of Intel(R) CPUs, northbridges and southbridges. .sp This tool has been developed for the coreboot project (see .B http://coreboot.org for details on coreboot). .SH OPTIONS .TP .B "\-h, \-\-help" Show a help text and exit. .TP .B "\-v, \-\-version" Show version information and exit. .TP .B "\-a, \-\-all" Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge and Intel(R) Core CPU MSRs. .TP .B "\-g, \-\-gpio" Dump I/O Controller Hub (ICH) southbridge GPIO registers. .TP .B "\-r, \-\-rcba" Dump I/O Controller Hub (ICH) southbridge RCBA registers. .TP .B "\-p, \-\-pmbase" Dump I/O Controller Hub (ICH) southbridge PMBASE registers. .TP .B "\-m, \-\-mchbar" Dump Intel(R) northbridge MCHBAR registers. .TP .B "\-e, \-\-epbar" Dump Intel(R) northbridge EPBAR registers. .TP .B "\-d, \-\-dmibar" Dump Intel(R) northbridge DMIBAR registers. .TP .B "\-P, \-\-pciexbar" Dump Intel(R) northbridge PCIEXBAR registers. .TP .B "\-M, \-\-msrs" Dump Intel(R) CPU MSRs. .SH BUGS Please report any bugs at .BR http://tracker.coreboot.org/trac/coreboot/newticket "," or on the coreboot mailing list .RB "(" http://coreboot.org/Mailinglist ")." .SH LICENCE .B inteltool is covered by the GNU General Public License (GPL), version 2. .SH COPYRIGHT Copyright (C) 2008 coresystems GmbH .SH AUTHORS Stefan Reinauer .PP This manual page was written by Stefan Reinauer . It is licensed under the terms of the GNU GPL (version 2). .sp Intel(R) is a registered trademark of Intel Corporation. Other product and/or company names mentioned herein may be trademarks or registered trademarks of their respective owners. inteltool-0.0+r4091.orig/gpio.c0000600000175000017500000001112311115772274014355 0ustar uweuwe/* * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2008 by coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include "inteltool.h" static const io_register_t ich0_gpio_registers[] = { { 0x00, 4, "GPIO_USE_SEL" }, { 0x04, 4, "GP_IO_SEL" }, { 0x08, 4, "RESERVED" }, { 0x0c, 4, "GP_LVL" }, { 0x10, 4, "RESERVED" }, { 0x14, 4, "GPO_TTL" }, { 0x18, 4, "GPO_BLINK" }, { 0x1c, 4, "RESERVED" }, { 0x20, 4, "RESERVED" }, { 0x24, 4, "RESERVED" }, { 0x28, 4, "RESERVED" }, { 0x2c, 4, "GPI_INV" }, { 0x30, 4, "RESERVED" }, { 0x34, 4, "RESERVED" }, { 0x38, 4, "RESERVED" }, { 0x3C, 4, "RESERVED" } }; static const io_register_t ich4_gpio_registers[] = { { 0x00, 4, "GPIO_USE_SEL" }, { 0x04, 4, "GP_IO_SEL" }, { 0x08, 4, "RESERVED" }, { 0x0c, 4, "GP_LVL" }, { 0x10, 4, "RESERVED" }, { 0x14, 4, "GPO_TTL" }, { 0x18, 4, "GPO_BLINK" }, { 0x1c, 4, "RESERVED" }, { 0x20, 4, "RESERVED" }, { 0x24, 4, "RESERVED" }, { 0x28, 4, "RESERVED" }, { 0x2c, 4, "GPI_INV" }, { 0x30, 4, "GPIO_USE_SEL2" }, { 0x34, 4, "GP_IO_SEL2" }, { 0x38, 4, "GP_LVL2" }, { 0x3C, 4, "RESERVED" } }; static const io_register_t ich7_gpio_registers[] = { { 0x00, 4, "GPIO_USE_SEL" }, { 0x04, 4, "GP_IO_SEL" }, { 0x08, 4, "RESERVED" }, { 0x0c, 4, "GP_LVL" }, { 0x10, 4, "RESERVED" }, { 0x14, 4, "RESERVED" }, { 0x18, 4, "GPO_BLINK" }, { 0x1c, 4, "RESERVED" }, { 0x20, 4, "RESERVED" }, { 0x24, 4, "RESERVED" }, { 0x28, 4, "RESERVED" }, { 0x2c, 4, "GPI_INV" }, { 0x30, 4, "GPIO_USE_SEL2" }, { 0x34, 4, "GP_IO_SEL2" }, { 0x38, 4, "GP_LVL2" }, { 0x3C, 4, "RESERVED" } }; static const io_register_t ich8_gpio_registers[] = { { 0x00, 4, "GPIO_USE_SEL" }, { 0x04, 4, "GP_IO_SEL" }, { 0x08, 4, "RESERVED" }, { 0x0c, 4, "GP_LVL" }, { 0x10, 4, "GPIO_USE_SEL Override (LOW)" }, { 0x14, 4, "RESERVED" }, { 0x18, 4, "GPO_BLINK" }, { 0x1c, 4, "GP_SER_BLINK" }, { 0x20, 4, "GP_SB_CMDSTS" }, { 0x24, 4, "GP_SB_DATA" }, { 0x28, 4, "RESERVED" }, { 0x2c, 4, "GPI_INV" }, { 0x30, 4, "GPIO_USE_SEL2" }, { 0x34, 4, "GP_IO_SEL2" }, { 0x38, 4, "GP_LVL2" }, { 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" } }; int print_gpios(struct pci_dev *sb) { int i, size; uint16_t gpiobase; const io_register_t *gpio_registers; printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_ICH8M: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich8_gpio_registers; size = ARRAY_SIZE(ich8_gpio_registers); break; case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich7_gpio_registers; size = ARRAY_SIZE(ich7_gpio_registers); break; case PCI_DEVICE_ID_INTEL_ICH4: case PCI_DEVICE_ID_INTEL_ICH4M: gpiobase = pci_read_word(sb, 0x58) & 0xfffc; gpio_registers = ich4_gpio_registers; size = ARRAY_SIZE(ich4_gpio_registers); break; case PCI_DEVICE_ID_INTEL_ICH: case PCI_DEVICE_ID_INTEL_ICH0: gpiobase = pci_read_word(sb, 0x58) & 0xfffc; gpio_registers = ich0_gpio_registers; size = ARRAY_SIZE(ich0_gpio_registers); break; case 0x1234: // Dummy for non-existent functionality printf("This southbridge does not have GPIOBASE.\n"); return 1; default: printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n"); return 1; } printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase); for (i = 0; i < size; i++) { switch (gpio_registers[i].size) { case 4: printf("gpiobase+0x%04x: 0x%08x (%s)\n", gpio_registers[i].addr, inl(gpiobase+gpio_registers[i].addr), gpio_registers[i].name); break; case 2: printf("gpiobase+0x%04x: 0x%04x (%s)\n", gpio_registers[i].addr, inw(gpiobase+gpio_registers[i].addr), gpio_registers[i].name); break; case 1: printf("gpiobase+0x%04x: 0x%02x (%s)\n", gpio_registers[i].addr, inb(gpiobase+gpio_registers[i].addr), gpio_registers[i].name); break; } } return 0; } inteltool-0.0+r4091.orig/inteltool.h0000600000175000017500000000442111115772274015440 0ustar uweuwe/* * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2008 by coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #ifndef DARWIN #include #else /* DirectIO is available here: * http://www.coresystems.de/en/directio */ #include #endif #include #define INTELTOOL_VERSION "1.0" /* Tested chipsets: */ #define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_DEVICE_ID_INTEL_ICH 0x2410 #define PCI_DEVICE_ID_INTEL_ICH0 0x2420 #define PCI_DEVICE_ID_INTEL_ICH2 0x2440 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 #define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc #define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 #define PCI_DEVICE_ID_INTEL_PM965 0x2a00 #define PCI_DEVICE_ID_INTEL_82975X 0x277c #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) #ifndef DARWIN typedef struct { uint32_t hi, lo; } msr_t; #endif typedef struct { uint16_t addr; int size; char *name; } io_register_t; void *map_physical(unsigned long phys_addr, int len); void unmap_physical(void *virt_addr, int len); unsigned int cpuid(unsigned int op); int print_intel_core_msrs(void); int print_mchbar(struct pci_dev *nb); int print_pmbase(struct pci_dev *sb); int print_rcba(struct pci_dev *sb); int print_gpios(struct pci_dev *sb); int print_epbar(struct pci_dev *nb); int print_dmibar(struct pci_dev *nb); int print_pciexbar(struct pci_dev *nb); inteltool-0.0+r4091.orig/pcie.c0000600000175000017500000001267711115772274014356 0ustar uweuwe/* * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2008 by coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include #include "inteltool.h" /* * Egress Port Root Complex MMIO configuration space */ int print_epbar(struct pci_dev *nb) { int i, size = (4 * 1024); volatile uint8_t *epbar; uint64_t epbar_phys; printf("\n============= EPBAR =============\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: case PCI_DEVICE_ID_INTEL_82975X: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_PM965: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have EPBAR.\n"); return 1; default: printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n"); return 1; } epbar = map_physical(epbar_phys, size); if (epbar == NULL) { perror("Error mapping EPBAR"); exit(1); } printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(epbar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i)); } unmap_physical((void *)epbar, size); return 0; } /* * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space */ int print_dmibar(struct pci_dev *nb) { int i, size = (4 * 1024); volatile uint8_t *dmibar; uint64_t dmibar_phys; printf("\n============= DMIBAR ============\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: case PCI_DEVICE_ID_INTEL_82975X: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_PM965: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have DMIBAR.\n"); return 1; default: printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); return 1; } dmibar = map_physical(dmibar_phys, size); if (dmibar == NULL) { perror("Error mapping DMIBAR"); exit(1); } printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(dmibar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i)); } unmap_physical((void *)dmibar, size); return 0; } /* * PCIe MMIO configuration space */ int print_pciexbar(struct pci_dev *nb) { uint64_t pciexbar_reg; uint64_t pciexbar_phys; volatile uint8_t *pciexbar; int max_busses, devbase, i; int bus, dev, fn; printf("========= PCIEXBAR ========\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: case PCI_DEVICE_ID_INTEL_82975X: pciexbar_reg = pci_read_long(nb, 0x48); break; case PCI_DEVICE_ID_INTEL_PM965: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; case 0x1234: // Dummy for non-existent functionality printf("Error: This northbrigde does not have PCIEXBAR.\n"); return 1; default: printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n"); return 1; } if (!(pciexbar_reg & (1 << 0))) { printf("PCIEXBAR register is disabled.\n"); return 0; } switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB pciexbar_phys = pciexbar_reg & (0xff << 28); max_busses = 256; break; case 1: // 128M pciexbar_phys = pciexbar_reg & (0x1ff << 27); max_busses = 128; break; case 2: // 64M pciexbar_phys = pciexbar_reg & (0x3ff << 26); max_busses = 64; break; default: // RSVD printf("Undefined address base. Bailing out.\n"); return 1; } printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys); pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024)); if (pciexbar == NULL) { perror("Error mapping PCIEXBAR"); exit(1); } for (bus = 0; bus < max_busses; bus++) { for (dev = 0; dev < 32; dev++) { for (fn = 0; fn < 8; fn++) { devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024); if (*(uint16_t *)(pciexbar + devbase) == 0xffff) continue; /* This is a heuristics. Anyone got a better check? */ if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) && (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) { #if DEBUG printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn); #endif continue; } printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn); for (i = 0; i < 4096; i++) { if((i % 0x10) == 0) printf("\n%04x:", i); printf(" %02x", *(pciexbar+devbase+i)); } printf("\n"); } } } unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024)); return 0; } inteltool-0.0+r4091.orig/powermgt.c0000600000175000017500000001322511115772274015270 0ustar uweuwe/* * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2008 by coresystems GmbH * written by Stefan Reinauer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include "inteltool.h" static const io_register_t ich7_pm_registers[] = { { 0x00, 2, "PM1_STS" }, { 0x02, 2, "PM1_EN" }, { 0x04, 4, "PM1_CNT" }, { 0x08, 4, "PM1_TMR" }, { 0x0c, 4, "RESERVED" }, { 0x10, 4, "PROC_CNT" }, #if DANGEROUS_REGISTERS /* These registers return 0 on read, but reading them may cause * the system to enter C2/C3/C4 state, which might hang the system. */ { 0x14, 1, "LV2 (Mobile/Ultra Mobile)" }, { 0x15, 1, "LV3 (Mobile/Ultra Mobile)" }, { 0x16, 1, "LV4 (Mobile/Ultra Mobile)" }, #endif { 0x17, 1, "RESERVED" }, { 0x18, 4, "RESERVED" }, { 0x1c, 4, "RESERVED" }, { 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" }, { 0x21, 1, "RESERVED" }, { 0x22, 2, "RESERVED" }, { 0x24, 4, "RESERVED" }, { 0x28, 4, "GPE0_STS" }, { 0x2C, 4, "GPE0_EN" }, { 0x30, 4, "SMI_EN" }, { 0x34, 4, "SMI_STS" }, { 0x38, 2, "ALT_GP_SMI_EN" }, { 0x3a, 2, "ALT_GP_SMI_STS" }, { 0x3c, 4, "RESERVED" }, { 0x40, 2, "RESERVED" }, { 0x42, 1, "GPE_CNTL" }, { 0x43, 1, "RESERVED" }, { 0x44, 2, "DEVACT_STS" }, { 0x46, 2, "RESERVED" }, { 0x48, 4, "RESERVED" }, { 0x4c, 4, "RESERVED" }, { 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" }, { 0x51, 1, "RESERVED" }, { 0x52, 2, "RESERVED" }, { 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" }, { 0x58, 4, "RESERVED" }, { 0x5c, 4, "RESERVED" }, /* Here start the TCO registers */ { 0x60, 2, "TCO_RLD" }, { 0x62, 1, "TCO_DAT_IN" }, { 0x63, 1, "TCO_DAT_OUT" }, { 0x64, 2, "TCO1_STS" }, { 0x66, 2, "TCO2_STS" }, { 0x68, 2, "TCO1_CNT" }, { 0x6a, 2, "TCO2_CNT" }, { 0x6c, 2, "TCO_MESSAGE" }, { 0x6e, 1, "TCO_WDCNT" }, { 0x6f, 1, "RESERVED" }, { 0x70, 1, "SW_IRQ_GEN" }, { 0x71, 1, "RESERVED" }, { 0x72, 2, "TCO_TMR" }, { 0x74, 4, "RESERVED" }, { 0x78, 4, "RESERVED" }, { 0x7c, 4, "RESERVED" }, }; static const io_register_t ich8_pm_registers[] = { { 0x00, 2, "PM1_STS" }, { 0x02, 2, "PM1_EN" }, { 0x04, 4, "PM1_CNT" }, { 0x08, 4, "PM1_TMR" }, { 0x0c, 4, "RESERVED" }, { 0x10, 4, "PROC_CNT" }, #if DANGEROUS_REGISTERS /* These registers return 0 on read, but reading them may cause * the system to enter Cx states, which might hang the system. */ { 0x14, 1, "LV2 (Mobile)" }, { 0x15, 1, "LV3 (Mobile)" }, { 0x16, 1, "LV4 (Mobile)" }, { 0x17, 1, "LV5 (Mobile)" }, { 0x18, 1, "LV6 (Mobile)" }, #endif { 0x19, 1, "RESERVED" }, { 0x1a, 2, "RESERVED" }, { 0x1c, 4, "RESERVED" }, { 0x20, 1, "PM2_CNT (Mobile)" }, { 0x21, 1, "RESERVED" }, { 0x22, 2, "RESERVED" }, { 0x24, 4, "RESERVED" }, { 0x28, 4, "GPE0_STS" }, { 0x2C, 4, "GPE0_EN" }, { 0x30, 4, "SMI_EN" }, { 0x34, 4, "SMI_STS" }, { 0x38, 2, "ALT_GP_SMI_EN" }, { 0x3a, 2, "ALT_GP_SMI_STS" }, { 0x3c, 4, "RESERVED" }, { 0x40, 2, "RESERVED" }, { 0x42, 1, "GPE_CNTL" }, { 0x43, 1, "RESERVED" }, { 0x44, 2, "DEVACT_STS" }, { 0x46, 2, "RESERVED" }, { 0x48, 4, "RESERVED" }, { 0x4c, 4, "RESERVED" }, { 0x50, 1, "SS_CNT (Mobile)" }, { 0x51, 1, "RESERVED" }, { 0x52, 2, "RESERVED" }, { 0x54, 4, "C3_RES (Mobile)" }, { 0x58, 4, "C5_RES (Mobile)" }, { 0x5c, 4, "RESERVED" }, /* Here start the TCO registers */ { 0x60, 2, "TCO_RLD" }, { 0x62, 1, "TCO_DAT_IN" }, { 0x63, 1, "TCO_DAT_OUT" }, { 0x64, 2, "TCO1_STS" }, { 0x66, 2, "TCO2_STS" }, { 0x68, 2, "TCO1_CNT" }, { 0x6a, 2, "TCO2_CNT" }, { 0x6c, 2, "TCO_MESSAGE" }, { 0x6e, 1, "TCO_WDCNT" }, { 0x6f, 1, "RESERVED" }, { 0x70, 1, "SW_IRQ_GEN" }, { 0x71, 1, "RESERVED" }, { 0x72, 2, "TCO_TMR" }, { 0x74, 4, "RESERVED" }, { 0x78, 4, "RESERVED" }, { 0x7c, 4, "RESERVED" }, }; int print_pmbase(struct pci_dev *sb) { int i, size; uint16_t pmbase; const io_register_t *pm_registers; printf("\n============= PMBASE ============\n\n"); switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich7_pm_registers; size = ARRAY_SIZE(ich7_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH8M: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich8_pm_registers; size = ARRAY_SIZE(ich8_pm_registers); break; case 0x1234: // Dummy for non-existent functionality printf("This southbridge does not have PMBASE.\n"); return 1; default: printf("Error: Dumping PMBASE on this southbridge is not (yet) supported.\n"); return 1; } printf("PMBASE = 0x%04x (IO)\n\n", pmbase); for (i = 0; i < size; i++) { switch (pm_registers[i].size) { case 4: printf("pmbase+0x%04x: 0x%08x (%s)\n", pm_registers[i].addr, inl(pmbase+pm_registers[i].addr), pm_registers[i].name); break; case 2: printf("pmbase+0x%04x: 0x%04x (%s)\n", pm_registers[i].addr, inw(pmbase+pm_registers[i].addr), pm_registers[i].name); break; case 1: printf("pmbase+0x%04x: 0x%02x (%s)\n", pm_registers[i].addr, inb(pmbase+pm_registers[i].addr), pm_registers[i].name); break; } } return 0; } inteltool-0.0+r4091.orig/cpu.c0000600000175000017500000002270211115772274014213 0ustar uweuwe/* * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2008 by coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include #include #include #include #include #include "inteltool.h" int fd_msr; unsigned int cpuid(unsigned int op) { unsigned int ret; unsigned int dummy2, dummy3, dummy4; asm volatile ( "pushl %%ebx \n" "cpuid \n" "movl %%ebx, %1 \n" "popl %%ebx \n" : "=a" (ret), "=r" (dummy2), "=c" (dummy3), "=d" (dummy4) : "a" (op) : "cc" ); return ret; } #ifndef DARWIN int msr_readerror = 0; msr_t rdmsr(int addr) { uint8_t buf[8]; msr_t msr = { 0xffffffff, 0xffffffff }; if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { perror("Could not lseek() to MSR"); close(fd_msr); exit(1); } if (read(fd_msr, buf, 8) == 8) { msr.lo = *(uint32_t *)buf; msr.hi = *(uint32_t *)(buf + 4); return msr; } if (errno == 5) { printf(" (*)"); // Not all bits of the MSR could be read msr_readerror = 1; } else { // A severe error. perror("Could not read() MSR"); close(fd_msr); exit(1); } return msr; } #endif int print_intel_core_msrs(void) { unsigned int i, core, id; msr_t msr; #define IA32_PLATFORM_ID 0x0017 #define EBL_CR_POWERON 0x002a #define FSB_CLK_STS 0x00cd #define IA32_TIME_STAMP_COUNTER 0x0010 #define IA32_APIC_BASE 0x001b typedef struct { int number; char *name; } msr_entry_t; static const msr_entry_t model6ex_global_msrs[] = { { 0x0017, "IA32_PLATFORM_ID" }, { 0x002a, "EBL_CR_POWERON" }, { 0x00cd, "FSB_CLOCK_STS" }, { 0x00ce, "FSB_CLOCK_VCC" }, { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" }, { 0x00e3, "PMG_IO_BASE_ADDR" }, { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, { 0x00ee, "EXT_CONFIG" }, { 0x011e, "BBL_CR_CTL3" }, { 0x0194, "CLOCK_FLEX_MAX" }, { 0x0198, "IA32_PERF_STATUS" }, { 0x01a0, "IA32_MISC_ENABLES" }, { 0x01aa, "PIC_SENS_CFG" }, { 0x0400, "IA32_MC0_CTL" }, { 0x0401, "IA32_MC0_STATUS" }, { 0x0402, "IA32_MC0_ADDR" }, //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO { 0x040c, "IA32_MC4_CTL" }, { 0x040d, "IA32_MC4_STATUS" }, { 0x040e, "IA32_MC4_ADDR" }, //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO }; static const msr_entry_t model6ex_per_core_msrs[] = { { 0x0010, "IA32_TIME_STAMP_COUNTER" }, { 0x001b, "IA32_APIC_BASE" }, { 0x003a, "IA32_FEATURE_CONTROL" }, { 0x003f, "IA32_TEMPERATURE_OFFSET" }, //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO { 0x008b, "IA32_BIOS_SIGN_ID" }, { 0x00e7, "IA32_MPERF" }, { 0x00e8, "IA32_APERF" }, { 0x00fe, "IA32_MTRRCAP" }, { 0x015f, "DTS_CAL_CTRL" }, { 0x0179, "IA32_MCG_CAP" }, { 0x017a, "IA32_MCG_STATUS" }, { 0x0199, "IA32_PERF_CONTROL" }, { 0x019a, "IA32_CLOCK_MODULATION" }, { 0x019b, "IA32_THERM_INTERRUPT" }, { 0x019c, "IA32_THERM_STATUS" }, { 0x019d, "GV_THERM" }, { 0x01d9, "IA32_DEBUGCTL" }, { 0x0200, "IA32_MTRR_PHYSBASE0" }, { 0x0201, "IA32_MTRR_PHYSMASK0" }, { 0x0202, "IA32_MTRR_PHYSBASE1" }, { 0x0203, "IA32_MTRR_PHYSMASK1" }, { 0x0204, "IA32_MTRR_PHYSBASE2" }, { 0x0205, "IA32_MTRR_PHYSMASK2" }, { 0x0206, "IA32_MTRR_PHYSBASE3" }, { 0x0207, "IA32_MTRR_PHYSMASK3" }, { 0x0208, "IA32_MTRR_PHYSBASE4" }, { 0x0209, "IA32_MTRR_PHYSMASK4" }, { 0x020a, "IA32_MTRR_PHYSBASE5" }, { 0x020b, "IA32_MTRR_PHYSMASK5" }, { 0x020c, "IA32_MTRR_PHYSBASE6" }, { 0x020d, "IA32_MTRR_PHYSMASK6" }, { 0x020e, "IA32_MTRR_PHYSBASE7" }, { 0x020f, "IA32_MTRR_PHYSMASK7" }, { 0x0250, "IA32_MTRR_FIX64K_00000" }, { 0x0258, "IA32_MTRR_FIX16K_80000" }, { 0x0259, "IA32_MTRR_FIX16K_A0000" }, { 0x0268, "IA32_MTRR_FIX4K_C0000" }, { 0x0269, "IA32_MTRR_FIX4K_C8000" }, { 0x026a, "IA32_MTRR_FIX4K_D0000" }, { 0x026b, "IA32_MTRR_FIX4K_D8000" }, { 0x026c, "IA32_MTRR_FIX4K_E0000" }, { 0x026d, "IA32_MTRR_FIX4K_E8000" }, { 0x026e, "IA32_MTRR_FIX4K_F0000" }, { 0x026f, "IA32_MTRR_FIX4K_F8000" }, { 0x02ff, "IA32_MTRR_DEF_TYPE" }, //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO }; static const msr_entry_t model6fx_global_msrs[] = { { 0x0017, "IA32_PLATFORM_ID" }, { 0x002a, "EBL_CR_POWERON" }, { 0x003f, "IA32_TEMPERATURE_OFFSET" }, { 0x00a8, "EMTTM_CR_TABLE0" }, { 0x00a9, "EMTTM_CR_TABLE1" }, { 0x00aa, "EMTTM_CR_TABLE2" }, { 0x00ab, "EMTTM_CR_TABLE3" }, { 0x00ac, "EMTTM_CR_TABLE4" }, { 0x00ad, "EMTTM_CR_TABLE5" }, { 0x00cd, "FSB_CLOCK_STS" }, { 0x00e2, "PMG_CST_CONFIG_CONTROL" }, { 0x00e3, "PMG_IO_BASE_ADDR" }, { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, { 0x00ee, "EXT_CONFIG" }, { 0x011e, "BBL_CR_CTL3" }, { 0x0194, "CLOCK_FLEX_MAX" }, { 0x0198, "IA32_PERF_STATUS" }, { 0x01a0, "IA32_MISC_ENABLES" }, { 0x01aa, "PIC_SENS_CFG" }, { 0x0400, "IA32_MC0_CTL" }, { 0x0401, "IA32_MC0_STATUS" }, { 0x0402, "IA32_MC0_ADDR" }, //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO { 0x040c, "IA32_MC4_CTL" }, { 0x040d, "IA32_MC4_STATUS" }, { 0x040e, "IA32_MC4_ADDR" }, //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO }; static const msr_entry_t model6fx_per_core_msrs[] = { { 0x0010, "IA32_TIME_STAMP_COUNTER" }, { 0x001b, "IA32_APIC_BASE" }, { 0x003a, "IA32_FEATURE_CONTROL" }, //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO { 0x008b, "IA32_BIOS_SIGN_ID" }, { 0x00e1, "SMM_CST_MISC_INFO" }, { 0x00e7, "IA32_MPERF" }, { 0x00e8, "IA32_APERF" }, { 0x00fe, "IA32_MTRRCAP" }, { 0x0179, "IA32_MCG_CAP" }, { 0x017a, "IA32_MCG_STATUS" }, { 0x0199, "IA32_PERF_CONTROL" }, { 0x019a, "IA32_THERM_CTL" }, { 0x019b, "IA32_THERM_INTERRUPT" }, { 0x019c, "IA32_THERM_STATUS" }, { 0x019d, "MSR_THERM2_CTL" }, { 0x01d9, "IA32_DEBUGCTL" }, { 0x0200, "IA32_MTRR_PHYSBASE0" }, { 0x0201, "IA32_MTRR_PHYSMASK0" }, { 0x0202, "IA32_MTRR_PHYSBASE1" }, { 0x0203, "IA32_MTRR_PHYSMASK1" }, { 0x0204, "IA32_MTRR_PHYSBASE2" }, { 0x0205, "IA32_MTRR_PHYSMASK2" }, { 0x0206, "IA32_MTRR_PHYSBASE3" }, { 0x0207, "IA32_MTRR_PHYSMASK3" }, { 0x0208, "IA32_MTRR_PHYSBASE4" }, { 0x0209, "IA32_MTRR_PHYSMASK4" }, { 0x020a, "IA32_MTRR_PHYSBASE5" }, { 0x020b, "IA32_MTRR_PHYSMASK5" }, { 0x020c, "IA32_MTRR_PHYSBASE6" }, { 0x020d, "IA32_MTRR_PHYSMASK6" }, { 0x020e, "IA32_MTRR_PHYSBASE7" }, { 0x020f, "IA32_MTRR_PHYSMASK7" }, { 0x0250, "IA32_MTRR_FIX64K_00000" }, { 0x0258, "IA32_MTRR_FIX16K_80000" }, { 0x0259, "IA32_MTRR_FIX16K_A0000" }, { 0x0268, "IA32_MTRR_FIX4K_C0000" }, { 0x0269, "IA32_MTRR_FIX4K_C8000" }, { 0x026a, "IA32_MTRR_FIX4K_D0000" }, { 0x026b, "IA32_MTRR_FIX4K_D8000" }, { 0x026c, "IA32_MTRR_FIX4K_E0000" }, { 0x026d, "IA32_MTRR_FIX4K_E8000" }, { 0x026e, "IA32_MTRR_FIX4K_F0000" }, { 0x026f, "IA32_MTRR_FIX4K_F8000" }, { 0x02ff, "IA32_MTRR_DEF_TYPE" }, //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO }; typedef struct { unsigned int model; const msr_entry_t *global_msrs; unsigned int num_global_msrs; const msr_entry_t *per_core_msrs; unsigned int num_per_core_msrs; } cpu_t; cpu_t cpulist[] = { { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, }; cpu_t *cpu = NULL; /* Get CPU family and model, not the stepping * (TODO: extended family/model) */ id = cpuid(1) & 0xff0; for (i = 0; i < ARRAY_SIZE(cpulist); i++) { if(cpulist[i].model == id) { cpu = &cpulist[i]; break; } } if (!cpu) { printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id); return -1; } #ifndef DARWIN fd_msr = open("/dev/cpu/0/msr", O_RDWR); if (fd_msr < 0) { perror("Error while opening /dev/cpu/0/msr"); printf("Did you run 'modprobe msr'?\n"); return -1; } #endif printf("\n===================== SHARED MSRs (All Cores) =====================\n"); for (i = 0; i < cpu->num_global_msrs; i++) { msr = rdmsr(cpu->global_msrs[i].number); printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", cpu->global_msrs[i].number, msr.hi, msr.lo, cpu->global_msrs[i].name); } close(fd_msr); for (core = 0; core < 8; core++) { #ifndef DARWIN char msrfilename[64]; memset(msrfilename, 0, 64); sprintf(msrfilename, "/dev/cpu/%d/msr", core); fd_msr = open(msrfilename, O_RDWR); /* If the file is not there, we're probably through. No error, * since we successfully opened /dev/cpu/0/msr before. */ if (fd_msr < 0) break; #endif printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); for (i = 0; i < cpu->num_per_core_msrs; i++) { msr = rdmsr(cpu->per_core_msrs[i].number); printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", cpu->per_core_msrs[i].number, msr.hi, msr.lo, cpu->per_core_msrs[i].name); } #ifndef DARWIN close(fd_msr); #endif } #ifndef DARWIN if (msr_readerror) printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n"); #endif return 0; } inteltool-0.0+r4091.orig/rootcmplx.c0000600000175000017500000000363111115772274015453 0ustar uweuwe/* * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2008 by coresystems GmbH * written by Stefan Reinauer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include #include "inteltool.h" int print_rcba(struct pci_dev *sb) { int i, size = 0x4000; volatile uint8_t *rcba; uint32_t rcba_phys; printf("\n============= RCBA ==============\n\n"); switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: case PCI_DEVICE_ID_INTEL_ICH8M: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_ICH: case PCI_DEVICE_ID_INTEL_ICH0: case PCI_DEVICE_ID_INTEL_ICH4: case PCI_DEVICE_ID_INTEL_ICH4M: printf("This southbridge does not have RCBA.\n"); return 1; default: printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n"); return 1; } rcba = map_physical(rcba_phys, size); if (rcba == NULL) { perror("Error mapping RCBA"); exit(1); } printf("RCBA = 0x%08x (MEM)\n\n", rcba_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(rcba + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba + i)); } unmap_physical((void *)rcba, size); return 0; } inteltool-0.0+r4091.orig/memory.c0000600000175000017500000000370111115772274014732 0ustar uweuwe/* * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2008 by coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include #include "inteltool.h" /* * (G)MCH MMIO Config Space */ int print_mchbar(struct pci_dev *nb) { int i, size = (16 * 1024); volatile uint8_t *mchbar; uint64_t mchbar_phys; printf("\n============= MCHBAR ============\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: case PCI_DEVICE_ID_INTEL_82975X: mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_PM965: mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have MCHBAR.\n"); return 1; default: printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); return 1; } mchbar = map_physical(mchbar_phys, size); if (mchbar == NULL) { perror("Error mapping MCHBAR"); exit(1); } printf("MCHBAR = 0x%08llx (MEM)\n\n", mchbar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(mchbar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i)); } unmap_physical((void *)mchbar, size); return 0; } inteltool-0.0+r4091.orig/inteltool.c0000600000175000017500000001710611115772274015437 0ustar uweuwe/* * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2008 by coresystems GmbH * written by Stefan Reinauer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include #include #include #include #include "inteltool.h" static const struct { uint16_t vendor_id, device_id; char *name; } supported_chips_list[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } }; #ifndef DARWIN static int fd_mem; void *map_physical(unsigned long phys_addr, int len) { void *virt_addr; virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t) phys_addr); if (virt_addr == MAP_FAILED) { printf("Error mapping physical memory 0x%08x[0x%x]\n", phys_addr, len); return NULL; } return virt_addr; } void unmap_physical(void *virt_addr, int len) { munmap(virt_addr, len); } #endif void print_version(void) { printf("inteltool v%s -- ", INTELTOOL_VERSION); printf("Copyright (C) 2008 coresystems GmbH\n\n"); printf( "This program is free software: you can redistribute it and/or modify\n" "it under the terms of the GNU General Public License as published by\n" "the Free Software Foundation, version 2 of the License.\n\n" "This program is distributed in the hope that it will be useful,\n" "but WITHOUT ANY WARRANTY; without even the implied warranty of\n" "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n" "GNU General Public License for more details.\n\n" "You should have received a copy of the GNU General Public License\n" "along with this program. If not, see .\n\n"); } void print_usage(const char *name) { printf("usage: %s [-vh?grpmedPMa]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" " -g | --gpio: dump soutbridge GPIO registers\n" " -r | --rcba: dump soutbridge RCBA registers\n" " -p | --pmbase: dump soutbridge Power Management registers\n\n" " -m | --mchbar: dump northbridge Memory Controller registers\n" " -e | --epbar: dump northbridge EPBAR registers\n" " -d | --dmibar: dump northbridge DMIBAR registers\n" " -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n" " -M | --msrs: dump CPU MSRs\n" " -a | --all: dump all known registers\n" "\n"); exit(1); } int main(int argc, char *argv[]) { struct pci_access *pacc; struct pci_dev *sb, *nb; int i, opt, option_index = 0; unsigned int id; char *sbname = "unknown", *nbname = "unknown"; int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0; int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; int dump_pciexbar = 0, dump_coremsrs = 0; static struct option long_options[] = { {"version", 0, 0, 'v'}, {"help", 0, 0, 'h'}, {"gpios", 0, 0, 'g'}, {"mchbar", 0, 0, 'm'}, {"rcba", 0, 0, 'r'}, {"pmbase", 0, 0, 'p'}, {"epbar", 0, 0, 'e'}, {"dmibar", 0, 0, 'd'}, {"pciexpress", 0, 0, 'P'}, {"msrs", 0, 0, 'M'}, {"all", 0, 0, 'a'}, {0, 0, 0, 0} }; while ((opt = getopt_long(argc, argv, "vh?grpmedPMa", long_options, &option_index)) != EOF) { switch (opt) { case 'v': print_version(); exit(0); break; case 'g': dump_gpios = 1; break; case 'm': dump_mchbar = 1; break; case 'r': dump_rcba = 1; break; case 'p': dump_pmbase = 1; break; case 'e': dump_epbar = 1; break; case 'd': dump_dmibar = 1; break; case 'P': dump_pciexbar = 1; break; case 'M': dump_coremsrs = 1; break; case 'a': dump_gpios = 1; dump_mchbar = 1; dump_rcba = 1; dump_pmbase = 1; dump_epbar = 1; dump_dmibar = 1; dump_pciexbar = 1; dump_coremsrs = 1; break; case 'h': case '?': default: print_usage(argv[0]); exit(0); break; } } if (iopl(3)) { printf("You need to be root.\n"); exit(1); } #ifndef DARWIN if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { perror("Can not open /dev/mem"); exit(1); } #endif pacc = pci_alloc(); pci_init(pacc); pci_scan_bus(pacc); /* Find the required devices */ sb = pci_get_dev(pacc, 0, 0, 0x1f, 0); if (!sb) { printf("No southbridge found.\n"); exit(1); } pci_fill_info(sb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS); if (sb->vendor_id != PCI_VENDOR_ID_INTEL) { printf("Not an Intel(R) southbridge.\n"); exit(1); } nb = pci_get_dev(pacc, 0, 0, 0x00, 0); if (!nb) { printf("No northbridge found.\n"); exit(1); } pci_fill_info(nb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS); if (nb->vendor_id != PCI_VENDOR_ID_INTEL) { printf("Not an Intel(R) northbridge.\n"); exit(1); } id = cpuid(1); printf("Intel CPU: Family %x, Model %x\n", (id >> 8) & 0xf, (id >> 4) & 0xf); /* Determine names */ for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) if (nb->device_id == supported_chips_list[i].device_id) nbname = supported_chips_list[i].name; for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) if (sb->device_id == supported_chips_list[i].device_id) sbname = supported_chips_list[i].name; printf("Intel Northbridge: %04x:%04x (%s)\n", nb->vendor_id, nb->device_id, nbname); printf("Intel Southbridge: %04x:%04x (%s)\n", sb->vendor_id, sb->device_id, sbname); /* Now do the deed */ if (dump_gpios) { print_gpios(sb); printf("\n\n"); } if (dump_rcba) { print_rcba(sb); printf("\n\n"); } if (dump_pmbase) { print_pmbase(sb); printf("\n\n"); } if (dump_mchbar) { print_mchbar(nb); printf("\n\n"); } if (dump_epbar) { print_epbar(nb); printf("\n\n"); } if (dump_dmibar) { print_dmibar(nb); printf("\n\n"); } if (dump_pciexbar) { print_pciexbar(nb); printf("\n\n"); } if (dump_coremsrs) { print_intel_core_msrs(); printf("\n\n"); } /* Clean up */ pci_free_dev(nb); pci_free_dev(sb); pci_cleanup(pacc); return 0; } inteltool-0.0+r4091.orig/Makefile0000600000175000017500000000430011115772274014712 0ustar uweuwe# # Makefile for inteltool utility # # Copyright (C) 2008 by coresystems GmbH # written by Stefan Reinauer # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # PROGRAM = inteltool CC = gcc INSTALL = /usr/bin/install PREFIX = /usr/local CFLAGS = -O2 -g -Wall -W LDFLAGS = -lpci -lz OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) CFLAGS += -DDARWIN -I/usr/local/include LDFLAGS = -framework IOKit -framework DirectIO -L/usr/local/lib -lpci -lz # OBJS += darwinio.o endif all: pciutils dep $(PROGRAM) $(PROGRAM): $(OBJS) $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) clean: rm -f $(PROGRAM) *.o *~ distclean: clean rm -f .dependencies dep: @$(CC) $(CFLAGS) -MM *.c > .dependencies pciutils: @printf "\nChecking for pciutils and zlib... " @$(shell ( printf "#include \n"; \ printf "struct pci_access *pacc;\n"; \ printf "int main(int argc, char **argv)\n"; \ printf "{ pacc = pci_alloc(); return 0; }\n"; ) > .test.c ) @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ printf "found.\n" || ( printf "not found.\n\n"; \ printf "Please install pciutils-devel and zlib-devel.\n"; \ printf "See README for more information.\n\n"; \ rm -f .test.c .test; exit 1) @rm -rf .test.c .test .test.dSYM install: $(PROGRAM) $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 $(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 .PHONY: all clean distclean dep pciutils -include .dependencies