pax_global_header 0000666 0000000 0000000 00000000064 13344175732 0014523 g ustar 00root root 0000000 0000000 52 comment=64cb60f754c5e1450c57cb0ec99b0117f45e9d86
jnr-a64asm-jnr-a64asm-1.0.0/ 0000775 0000000 0000000 00000000000 13344175732 0015263 5 ustar 00root root 0000000 0000000 jnr-a64asm-jnr-a64asm-1.0.0/LICENSE 0000664 0000000 0000000 00000001037 13344175732 0016271 0 ustar 00root root 0000000 0000000
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
jnr-a64asm-jnr-a64asm-1.0.0/README.md 0000664 0000000 0000000 00000000244 13344175732 0016542 0 ustar 00root root 0000000 0000000 This is a pure-java port of asmjit for AARCH64 architecture
(http://code.google.com/p/asmjit/)
This is remote assembler for jnr-ffi to support aarch64 architecture
jnr-a64asm-jnr-a64asm-1.0.0/pom.xml 0000664 0000000 0000000 00000004723 13344175732 0016606 0 ustar 00root root 0000000 0000000
4.0.0
org.sonatype.oss
oss-parent
7
com.github.jnr
jnr-a64asm
jar
1.0.0
jnr-a64asm
A pure-java A64 assembler
The Apache Software License, Version 2.0
http://www.apache.org/licenses/LICENSE-2.0.txt
repo
scm:git:git@github.com:jnr/jnr-a64asm.git
scm:git:git@github.com:jnr/jnr-a64asm.git
git@github.com:jnr/jnr-a64asm.git
HEAD
ossdev
ossdev
ossdev@puresoftware.com
junit
junit
4.8.2
test
UTF-8
1.7
1.7
org.apache.maven.plugins
maven-javadoc-plugin
2.9.1
attach-javadocs
jar
-Xdoclint:none
org.apache.maven.plugins
maven-source-plugin
2.2.1
attach-sources
jar
jnr-a64asm-jnr-a64asm-1.0.0/src/ 0000775 0000000 0000000 00000000000 13344175732 0016052 5 ustar 00root root 0000000 0000000 jnr-a64asm-jnr-a64asm-1.0.0/src/main/ 0000775 0000000 0000000 00000000000 13344175732 0016776 5 ustar 00root root 0000000 0000000 jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/ 0000775 0000000 0000000 00000000000 13344175732 0017717 5 ustar 00root root 0000000 0000000 jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/ 0000775 0000000 0000000 00000000000 13344175732 0020510 5 ustar 00root root 0000000 0000000 jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/ 0000775 0000000 0000000 00000000000 13344175732 0021603 5 ustar 00root root 0000000 0000000 jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Asm.java 0000664 0000000 0000000 00000017432 13344175732 0023175 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import static jnr.a64asm.REG.*;
import static jnr.a64asm.SIZE.*;
public final class Asm {
private Asm() {}
public static final CPU_A64 Aarch_64 = CPU_A64.A64;
/** No register, can be used only in @c Mem operand. */
public static final Register no_reg = new Register(NO_REG, 0);
/** 64 bit General purpose register. */
public static final Register x0 = Register.gpr(REG_X0);
/** 64 bit General purpose register. */
public static final Register x1 = Register.gpr(REG_X1);
/** 64 bit General purpose register. */
public static final Register x2 = Register.gpr(REG_X2);
/** 64 bit General purpose register. */
public static final Register x3 = Register.gpr(REG_X3);
/** 64 bit General purpose register. */
public static final Register x4 = Register.gpr(REG_X4);
/** 64 bit General purpose register. */
public static final Register x5 = Register.gpr(REG_X5);
/** 64 bit General purpose register. */
public static final Register x6 = Register.gpr(REG_X6);
/** 64 bit General purpose register. */
public static final Register x7 = Register.gpr(REG_X7);
/** frame pointer */
public static final Register fp = Register.gpr(REG_X29);
/** link register */
public static final Register lr = Register.gpr(REG_X30);
/** stack pointer */
public static final Register sp = Register.gpr(REG_X31);
/** 64 bit 15 Spare General purpose register (64 bit mode only). */
public static final Register w0 = Register.gpr(REG_W0);
public static final Register w1 = Register.gpr(REG_W1);
public static final Register w2 = Register.gpr(REG_W2);
public static final Register w3 = Register.gpr(REG_W3);
public static final Register w4 = Register.gpr(REG_W4);
public static final Register w5 = Register.gpr(REG_W5);
public static final Register w6 = Register.gpr(REG_W6);
public static final Register w7 = Register.gpr(REG_W7);
public static final Register w8 = Register.gpr(REG_W8);
public static final Register w9 = Register.gpr(REG_W9);
public static final Register w10 = Register.gpr(REG_W10);
public static final Register w11 = Register.gpr(REG_W11);
public static final Register w12 = Register.gpr(REG_W12);
public static final Register w13 = Register.gpr(REG_W13);
public static final Register w14 = Register.gpr(REG_W14);
public static final Register w15 = Register.gpr(REG_W15);
static final Mem _ptr_build(Label label, long disp, int ptrSize) {
return new Mem(label, disp, ptrSize);
}
static final Mem _ptr_build(Label label, Register index, int shift, long disp, int ptrSize) {
return new Mem(label, index, shift, disp, ptrSize);
}
/** Absolute addressing */
static final Mem _ptr_build_abs(long target, long disp, int ptrSize) {
return new Mem(target, disp, ptrSize);
}
static final Mem _ptr_build_abs(long target, Register index, int shift, long disp, int ptrSize) {
return new Mem(target, index, shift, disp, ptrSize);
}
static final Mem _ptr_build(Register base, long disp, int ptrSize) {
return new Mem(base, disp, ptrSize);
}
static final Mem _ptr_build(Register base, Register index, int shift, long disp, int ptrSize) {
return new Mem(base, index, shift, disp, ptrSize);
}
// ============================================================================
// [AsmJit::Mem - ptr[displacement]]
// ============================================================================
/** Create pointer operand with not specified size. */
public static final Mem ptr(Label label, long disp) {
return _ptr_build(label, disp, 0);
}
/** Create pointer operand with not specified size. */
public static final Mem ptr(Label label) {
return _ptr_build(label, 0, 0);
}
/** Create word (2 Bytes) pointer operand. */
public static final Mem word_ptr(Label label, long disp) {
return _ptr_build(label, disp, SIZE_WORD);
}
/** Create word (2 Bytes) pointer operand. */
public static final Mem word_ptr(Label label) {
return _ptr_build(label, 0, SIZE_WORD);
}
/** Create dword (4 Bytes) pointer operand. */
public static final Mem dword_ptr(Label label, long disp) {
return _ptr_build(label, disp, SIZE_DWORD);
}
/** Create dword (4 Bytes) pointer operand. */
public static final Mem dword_ptr(Label label) {
return _ptr_build(label, 0, SIZE_DWORD);
}
/** Create pointer operand with not specified size. */
public static final Mem ptr(Label label, Register index, int shift, long disp) {
return _ptr_build(label, index, shift, disp, 0);
}
/** Create dword (4 Bytes) pointer operand. */
public static final Mem word_ptr(Label label, Register index, int shift, long disp) {
return _ptr_build(label, index, shift, disp, SIZE_WORD);
}
/** Create qword (8 Bytes) pointer operand. */
public static final Mem dword_ptr(Label label, Register index, int shift, long disp) {
return _ptr_build(label, index, shift, disp, SIZE_DWORD);
}
public static final Mem word_ptr_abs(long target, Register index, int shift, long disp) {
return _ptr_build_abs(target, index, shift, disp, SIZE_WORD);
}
public static final Mem dword_ptr_abs(long target, Register index, int shift, long disp) {
return _ptr_build_abs(target, index, shift, disp, SIZE_DWORD);
}
// ============================================================================
// [AsmJit::Mem - ptr[base + displacement]]
// ============================================================================
/** Create pointer operand with not specified size. */
public static final Mem ptr(Register base, long disp) {
return _ptr_build(base, disp, 0);
}
/** Create word (4 Bytes) pointer operand. */
public static final Mem word_ptr(Register base, long disp) {
return _ptr_build(base, disp, SIZE_WORD);
}
/** Create dword (8 Bytes) pointer operand. */
public static final Mem dword_ptr(Register base, long disp) {
return _ptr_build(base, disp, SIZE_DWORD);
}
// ============================================================================
// [AsmJit::Mem - ptr[base + (index << shift) + displacement]]
// ============================================================================
/** Create pointer operand with not specified size. */
public static final Mem ptr(Register base, Register index, int shift, long disp) {
return _ptr_build(base, index, shift, disp, 0);
}
/** Create word (2 Bytes) pointer operand. */
public static final Mem word_ptr(Register base, Register index, int shift, long disp) {
return _ptr_build(base, index, shift, disp, SIZE_WORD);
}
/** Create dword (4 Bytes) pointer operand. */
public static final Mem dword_ptr(Register base, Register index, int shift, long disp) {
return _ptr_build(base, index, shift, disp, SIZE_DWORD);
}
public static final Immediate imm(long value) {
return Immediate.imm(value);
}
public static final Immediate uimm(long value) {
return Immediate.imm(value);
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Assembler_A64.java 0000664 0000000 0000000 00000127610 13344175732 0025004 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import java.nio.ByteBuffer;
import java.util.LinkedList;
import java.util.List;
import static jnr.a64asm.INST_CODE.*;
import static jnr.a64asm.InstructionGroup.*;
import static jnr.a64asm.OP.*;
import static jnr.a64asm.OperandFlags.*;
import static jnr.a64asm.RELOC_MODE.*;
import static jnr.a64asm.REG.*;
import static jnr.a64asm.Util.*;
import static jnr.a64asm.SIZE.*;
import static jnr.a64asm.PrefOp.*;
/**
* Low level code generation.
*/
public final class Assembler_A64 extends Serializer {
private final CodeBuffer _buffer = new CodeBuffer();
private final List _relocData = new LinkedList();
private final CpuInfo cpuInfo = CpuInfo.GENERIC;
private int _properties = 0;
private final Logger _logger = null;
private final CPU_A64 cpu;
@Override
boolean is64() {
return cpu == CPU_A64.A64;
}
private static final int intValue(boolean b) {
return b ? 1 : 0;
}
public static final CPU_A64 Aarch_64 = CPU_A64.Aarch64;
public Assembler_A64(CPU_A64 cpu) {
this.cpu = cpu;
}
public final int offset() {
return _buffer.offset();
}
/** Gets the required size of memory required to store all the generated code */
public final int codeSize() {
return _buffer.offset();
}
//! @brief Set byte at position @a pos.
public final byte getByteAt(int pos) {
return _buffer.getByteAt(pos);
}
//! @brief Set word at position @a pos.
public final short getWordAt(int pos) {
return _buffer.getWordAt(pos);
}
//! @brief Set word at position @a pos.
public final int getDWordAt(int pos) {
return _buffer.getDWordAt(pos);
}
//! @brief Set word at position @a pos.
public final long getQWordAt(int pos) {
return _buffer.getQWordAt(pos);
}
//! @brief Set byte at position @a pos.
public final void setByteAt(int pos, byte x) {
_buffer.setByteAt(pos, x);
}
//! @brief Set word at position @a pos.
public final void setWordAt(int pos, short x) {
_buffer.setWordAt(pos, x);
}
//! @brief Set word at position @a pos.
public final void setDWordAt(int pos, int x) {
_buffer.setDWordAt(pos, x);
}
//! @brief Set word at position @a pos.
public final void setQWordAt(int pos, long x) {
_buffer.setQWordAt(pos, x);
}
//! @brief Set word at position @a pos.
public final int getInt32At(int pos) {
return (int) _buffer.getDWordAt(pos);
}
//! @brief Set int32 at position @a pos.
public final void setInt32At(int pos, long x) {
_buffer.setDWordAt(pos, (int) x);
}
public final void setVarAt(int pos, long i, boolean isUnsigned, int size) {
switch (size) {
case 1:
setByteAt(pos, (byte) i);
break;
case 2:
setWordAt(pos, (short) i);
break;
case 4:
setDWordAt(pos, (int) i);
break;
case 8:
setQWordAt(pos, i);
default:
throw new IllegalArgumentException("invalid size");
}
}
/** Emit Byte to internal buffer. */
final void _emitByte(int x) {
_buffer.emitByte((byte) x);
}
/** Emit Word (2 bytes) to internal buffer. */
final void _emitWord(int x) {
_buffer.emitWord((short) x);
}
/** Emit DWord (4 bytes) to internal buffer. */
final void _emitDWord(int x) {
_buffer.emitDWord(x);
}
/** Emit QWord (8 bytes) to internal buffer. */
final void _emitQWord(long x) {
_buffer.emitQWord(x);
}
/** Emit Int32 (4 bytes) to internal buffer. */
final void _emitInt32(int x) {
_buffer.emitDWord(x);
}
/** Emit system signed integer (4 or 8 bytes) to internal buffer. */
final void _emitSysInt(long x) {
if (is64()) {
_buffer.emitQWord(x);
} else {
_buffer.emitDWord((int) x);
}
}
//! @brief Emit single @a opCode without operands.
final void _emitOpCode(int opCode) {
if ((opCode & 0xFF000000) != 0) {
_emitByte((byte) ((opCode & 0xFF000000) >> 24));
}
if ((opCode & 0x00FF0000) != 0) {
_emitByte((byte) ((opCode & 0x00FF0000) >> 16));
}
if ((opCode & 0x0000FF00) != 0) {
_emitByte((byte) ((opCode & 0x0000FF00) >> 8));
}
_emitByte((byte) (opCode & 0x000000FF));
}
void _emitImmediate(Immediate imm, int size) {
switch (size) {
case 1:
_emitByte(imm.byteValue());
break;
case 2:
_emitWord(imm.shortValue());
break;
case 4:
_emitDWord(imm.intValue());
break;
case 8:
if (!is64()) {
throw new IllegalArgumentException("64 bit immediate values not supported for 32bit");
}
_emitQWord(imm.longValue());
break;
default:
throw new IllegalArgumentException("invalid immediate operand size");
}
}
void _emita64(INST_CODE code, Operand o1, Operand o2, Operand o3, Operand o4, Operand o5) {
InstructionDescription id = InstructionDescription.find(code);
switch(id.group){
case addsub_carry:
case addsub_ext:
{
int inst_to_emit = 0;
if ((o1.isReg() && o2.isReg() && o3.isReg()) || (o4 != null && o4.isExtend())){
Register regD = (Register) o1;
Register regN = (Register) o2;
Register regM = (Register) o3;
Ext extV = null;
if(o4 != _none && o4.isExtend())
extV = (Ext) o4;
if(o1.size() == SIZE_DWORD){
inst_to_emit |= 1 << 31;
}
inst_to_emit |= regD.code & 0b11111;
inst_to_emit |= (regN.code & 0b11111) << 5;
inst_to_emit |= (regM.code & 0b11111) << 16;
if((id.group == addsub_ext) && (extV != null)){
inst_to_emit |= (extV.value() & 0b111) << 10;
inst_to_emit |= (extV.type() & 0b111) << 13;
}
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case addsub_imm:
case addsub_shift:
{
int inst_to_emit = 0;
if ((o1 != _none && o1.isReg()) && (o2 != _none && o2.isReg())){
Register regD = (Register) o1;
Register regN = (Register) o2;
Immediate val = null ;
if(o3 != _none && o3.isImm())
val = (Immediate) o3;
Shift sft = null;
if(o4 != _none)
sft = (Shift) o4;
Register regM = null;
if(o3 != _none && o3.isReg())
regM = (Register) o3;
if(o1.size() == SIZE_DWORD)
inst_to_emit |= 1 << 31;
inst_to_emit |= regD.code & 0b11111;
inst_to_emit |= (regN.code & 0b11111) << 16;
if(id.group == addsub_shift){
if(regM != null)
inst_to_emit |= (regM.code & 0b11111) << 16;
if (sft != null)
inst_to_emit |= (sft.value() & 0b111111) << 10;
}
else {
if (val != null)
inst_to_emit |= (val.value() & 0xfff) << 10;
}
if(sft != null)
inst_to_emit |= (sft.type() & 0b11) << 22;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case bitfield:
{
int inst_to_emit = 0;
if (o1.isReg() && o2.isReg()){
Register regD = (Register) o1;
Register regN = (Register) o2;
Immediate val1 = null ;
if(o3.isImm())
val1 = (Immediate) o3;
Immediate val2 = null;
if(o4.isImm())
val2 = (Immediate) o4;
if(o1.size() == SIZE_DWORD){
inst_to_emit |= 1 << 31;
inst_to_emit |= 1 << 22;
}
inst_to_emit |= regD.code & 0b11111;
inst_to_emit |= (regN.code & 0b11111) << 5;
if (val1 != null)
inst_to_emit |= (val1.value() & 0b111111) << 10;
if (val2 != null)
inst_to_emit |= (val2.value() & 0b111111) << 16;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case branch_imm:
{
int inst_to_emit = 0;
if (o1 != _none){
Immediate mem = (Immediate) o1;
/* Is the program label to be unconditionally branched to. Its offset from the address of this instruction,
in the range +/-128MB, is encoded as "imm26" times 4.*/
_emitJmpOrCallReloc(branch_imm, mem.value());
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case branch_reg:
{
int inst_to_emit = 0;
Register regN = null;
if(o1 != _none && o1 != null && o1.isReg()) /*because at jnr-ffi level this is called like this a.ret((Register)null);*/
regN = (Register) o1;
if (regN != null)
inst_to_emit |= (regN.code & 0b11111) << 5;
if(regN == null && id.code == INST_RET_BRANCH_REG)
inst_to_emit |= 0b11110 << 5; /*in the case of RET default location is X30*/
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
break;
}
case compbranch:
{
int inst_to_emit = 0;
if (o1.isReg() && o2.isLabel()){
Register regD = (Register) o1;
Label labl = (Label) o2;
if(o1.size() == SIZE_DWORD)
inst_to_emit |= 1 << 31;
inst_to_emit |= regD.code & 0b11111;
inst_to_emit |= (labl.position() & 0x7ffff) << 5;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case condbranch:
{
int inst_to_emit = 0;
if (o1.isImm()){
Immediate imm19 = (Immediate) o1;
if (imm19 != null)
inst_to_emit |= (imm19.value() & 0x7ffff) << 5;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case condcmp_imm:
case condcmp_reg:
{
int inst_to_emit = 0;
if (o1.isReg() && o2.isImm()){
Register regD = (Register) o1;
Register regM = (Register) o2;
Immediate val = (Immediate) o2;
Immediate nzcv = (Immediate) o3;
Conditions cond = (Conditions) o4;
if (regD != null)
inst_to_emit |= regD.code & 0b11111;
if (id.group == condcmp_reg && regM != null)
inst_to_emit |= (regM.code & 0b11111) << 16;
else{
if (val != null)
inst_to_emit |= (val.value() & 0b11111) << 16;
}
if (nzcv != null)
inst_to_emit |= nzcv.value() & 0b1111;
if (cond != null)
inst_to_emit |= (cond.value() & 0b1111) << 12;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case condsel:
{
int inst_to_emit = 0;
if (o1.isReg()){
Register regD = (Register) o1;
Register regN = (Register) o2;
Register regM = (Register) o3;
Conditions cond0 = (Conditions) o4;
Conditions cond1 = (Conditions) o3;
Conditions cond2 = (Conditions) o2;
if (regD != null)
inst_to_emit |= regD.code & 0b11111;
if(o4.isCond() && ((cond0.value() & 0b1110) != 0b1110)){
inst_to_emit |= (cond0.value() ^ 0b1) << 12;
inst_to_emit |= (regN.code & 0b11111) << 5;
inst_to_emit |= (regM.code & 0b11111) << 16;
}
else if(o3.isCond() && ((cond1.value() & 0b1110) != 0b1110)){
inst_to_emit |= (cond1.value() ^ 0b1) << 12;
inst_to_emit |= (regN.code & 0b11111) << 5;
inst_to_emit |= (0b11111) << 16; /*regM is 0b11111 if not explicitly mentioned in ASM inst*/
}
else if(o2.isCond() && ((cond2.value() & 0b1110) != 0b1110)){
inst_to_emit |= (cond1.value() ^ 0b1) << 12;
inst_to_emit |= (0b11111) << 5;
inst_to_emit |= (0b11111) << 16; /*regM&N is 0b11111 if not explicitly mentioned in ASM inst*/
}
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case dp_1src:
case dp_2src:
case dp_3src:
{
int inst_to_emit = 0;
if (o1.isReg() && o2.isReg()){
Register regD = (Register) o1;
Register regN = (Register) o2;
Register regM = (Register) o3;
Register regA = (Register) o4;
if (regD != null)
inst_to_emit |= regD.code & 0b11111;
if (regN != null)
inst_to_emit |= (regN.code & 0b11111) << 5;
if (regM != null && (id.group == dp_2src || id.group == dp_3src))
inst_to_emit |= (regM.code & 0b11111) << 16;
if (regA != null && id.group == dp_3src)
inst_to_emit |= (regA.code & 0b11111) << 10;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case exception:
{
int inst_to_emit = 0;
if (o1.isImm()){
Immediate imm16 = (Immediate) o1;
if(imm16 != null)
inst_to_emit |= (imm16.value() & 0xffff) << 5;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case extract:
{
int inst_to_emit = 0;
if (o1.isReg() && o2.isReg()){
Register regD = (Register) o1;
Register regN = (Register) o2;
Register regM = (Register) o3;
Immediate imm6 = (Immediate) o4;
Immediate imm6_1 = (Immediate) o3;
if (regD != null)
inst_to_emit |= regD.code & 0b11111;
if (regN != null)
inst_to_emit |= (regN.code & 0b11111) << 5;
if (o3.isReg() && regM != null){
inst_to_emit |= (regM.code & 0b11111) << 16;
inst_to_emit |= (imm6.value() & 0b111111) << 10;
}
else if (o3.isImm() && imm6_1 != null ){
inst_to_emit |= (imm6_1.value() & 0b111111) << 10;
inst_to_emit |= (regN.code & 0b11111) << 16; /*in the case of ROR Rn and Rm will hold same value*/
}
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case ldst_imm9:
case ldst_pos:
{
int inst_to_emit = 0;
if (o1.isReg() || id.code == INST_PRFM_LDST_POS__IMMEDIATE){
Register regD = null;
PRFOP_ENUM pfrop = null;
if(id.code == INST_PRFM_LDST_POS__IMMEDIATE && o1 != null)
pfrop = (PRFOP_ENUM)o1;
else if(o1 != _none)
regD = (Register) o1;
Register regN = null;
Post_index postindex = null;
Pre_index preindex = null;
Offset offset = null;
Immediate imm9 = null;
Immediate imm12 = null;
if(o2 != _none && o2.isReg())
regN = (Register) o2;
else if((o2 != _none) && (o2.isPreIndex() || o2.isPostIndex() || o2.isOffset())){
if(o2.isPreIndex()) {
preindex = (Pre_index)o2;
regN = preindex.getRegister();
imm9 = preindex.getPreIndex();
}
else if(o2.isPostIndex()){
postindex = (Post_index)o2;
regN = postindex.getRegister();
imm9 = postindex.getPostIndex();
}
else{
offset = (Offset)o2;
regN = offset.getRegister();
imm12 = offset.getOffset();
}
}
if(o3 != _none && id.group == ldst_imm9 && !(o2.isPreIndex() || o2.isPostIndex()))
imm9 = (Immediate)o3;
if(o3 != _none && id.group == ldst_pos && !(o2.isPreIndex() || o2.isPostIndex()))
imm12 = (Immediate) o3;
if(o1.size() == SIZE_DWORD && id.code != INST_PRFM_LDST_POS__IMMEDIATE && id.code != INST_LDRSW_IMM_OFF && id.code != INST_LDRH_IMM_OFF && id.code != INST_LDRSH_IMM_OFF && id.code != INST_LDRB_IMM_OFF && id.code != INST_LDRSB_IMM_OFF)
inst_to_emit |= 1 << 30;
if(o1.size() == SIZE_WORD && id.code != INST_LDRB_IMM_OFF && (id.code == INST_LDRSH_IMM_OFF || id.code == INST_LDRSB_IMM_OFF) )
inst_to_emit |= 1 << 22;
if (regD != null)
inst_to_emit |= regD.code & 0b11111;
else if (pfrop != null)
inst_to_emit |= pfrop.intValue() & 0b11111; /*in case of prfm inst*/
if (regN != null)
inst_to_emit |= (regN.code & 0b11111) << 5;
if (id.group == ldst_imm9)
inst_to_emit |= (imm9.value() & 0x1ff) << 12;
else if(id.group == ldst_pos && (id.code == INST_LDRB_IMM_OFF || id.code == INST_LDRSB_IMM_OFF))
inst_to_emit |= (imm12.value() & 0xfff) << 10;
else if(id.group == ldst_pos && (id.code == INST_LDRH_IMM_OFF || id.code == INST_LDRSH_IMM_OFF))
inst_to_emit |= (imm12.value()>>1 & 0xfff) << 10;
else if(id.group == ldst_pos)
inst_to_emit |= (imm12.value()>>((id.code == INST_LDRSW_IMM_OFF)?(2):(3)) & 0xfff) << 10; /* Is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as /8.*/
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case ldst_imm9_2reg:
case ldst_pos_2reg:
{
int inst_to_emit = 0;
if (o1.isReg()){
Register regT = (Register) o1;
Register regT2 = (Register) o2;
Post_index postindex = null;
Pre_index preindex = null;
Offset offset = null;
Immediate imm7 = null;
Register regN = null;
if(o3 != _none && o3.isPreIndex() || o3.isPostIndex() || o3.isOffset()){
if(o3.isPreIndex()) {
preindex = (Pre_index)o3;
regN = preindex.getRegister();
imm7 = preindex.getPreIndex();
}
else if(o3.isPostIndex()){
postindex = (Post_index)o3;
regN = postindex.getRegister();
imm7 = postindex.getPostIndex();
}
else{
offset = (Offset)o3;
regN = offset.getRegister();
imm7 = offset.getOffset();
}
}
if(o1.size() == SIZE_DWORD)
inst_to_emit |= 1 << 31;
if (regT != null)
inst_to_emit |= regT.code & 0b11111;
if (regN != null)
inst_to_emit |= (regN.code & 0b11111) << 5;
if (regT2 != null)
inst_to_emit |= (regT2.code & 0b11111) << 10;
/* For the 32-bit variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256
to 252, defaulting to 0 and encoded in the "imm7" field as /4.
For the 64-bit variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512
to 504, defaulting to 0 and encoded in the "imm7" field as /8. */
if(imm7 != null)
inst_to_emit |= ((imm7.value()>>((o1.size() == SIZE_DWORD)?(3):(2))) & 0b1111111) << 15;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case ldst_regoff:
{
int inst_to_emit = 0;
if ((o1.isReg() && o2.isReg()) || id.code == INST_PRFM_LDST_REGOFF__REGISTER){
Register regD = null;
PRFOP_ENUM pfrop = null;
if(id.code == INST_PRFM_LDST_REGOFF__REGISTER)
pfrop = (PRFOP_ENUM) o1;
else
regD = (Register) o1;
Register regN = (Register) o2;
Register regM = (Register) o3;
Ext extnd = (Ext) o3;
if(o1.size() == SIZE_DWORD && id.code != INST_PRFM_LDST_REGOFF__REGISTER)
inst_to_emit |= 1 << 30;
if (regD != null)
inst_to_emit |= regD.code & 0b11111;
else
inst_to_emit |= pfrop.intValue() & 0b11111;
if (regN != null)
inst_to_emit |= (regN.code & 0b11111) << 5;
if (regM != null)
inst_to_emit |= (regM.code & 0b11111) << 16;
if (o4 != null && o4.isExtend()){
inst_to_emit |= (extnd.value() == 3 || extnd.value() == 2) ? (0b1 << 12) : (0);
inst_to_emit |= (extnd.type() & 0b111) << 13;
}
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case ldst_unpriv:
case ldst_unscaled:
{
int inst_to_emit = 0;
if (o1.isReg() && o2.isReg() || id.code == INST_PRFUM_LDST_UNSCALED){
Register regD = null;
PRFOP_ENUM pfrop = null;
if(id.code == INST_PRFUM_LDST_UNSCALED)
pfrop = (PRFOP_ENUM) o1;
else
regD = (Register) o1;
Register regN = (Register) o2;
Immediate imm9 = (Immediate) o3;
if (regD != null)
inst_to_emit |= regD.code & 0b11111;
else
inst_to_emit |= pfrop.intValue() & 0b11111;
if (regN != null)
inst_to_emit |= (regN.code & 0b11111) << 5;
if (o3 != null && o3.isImm())
inst_to_emit |= (imm9.value() & 0x1ff) << 12;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case ldstexcl:
case ldstexcl_op3:
{
int inst_to_emit = 0;
Register regD = (Register) o1;
Register regN = (Register) o2;
Register regM = null;
Offset offset = null;
if(o3 != null && o3.isReg())
regM = (Register) o3;
else if (o3 != null && o3.isOffset()){
offset = (Offset) o3;
regM = offset.getRegister();
}
inst_to_emit |= (regD.code & 0b11111) << 16;
inst_to_emit |= regN.code & 0b11111;
if(id.group == ldstexcl_op3 && regM != null)
inst_to_emit |= (regM.code & 0b11111) << 5;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
break;
}
case ldstexcl_op4:
{
int inst_to_emit = 0;
Register regS = (Register) o1;
Register regt = (Register) o2;
Register regt2 = (Register) o3;
Register regN = (Register) o3;
inst_to_emit |= (regS.code & 0b11111) << 16;
inst_to_emit |= regt.code & 0b11111;
inst_to_emit |= (regt2.code & 0b11111) << 10;
inst_to_emit |= (regN.code & 0b11111) << 5;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
break;
}
case ldstnapair_offs:
case ldstpair_off:
case ldstpair_indexed:
{
int inst_to_emit = 0;
if (o1.isReg() && o2.isReg()){
Register regD = (Register) o1;
Register regN = (Register) o2;
Register regM = null;
Pre_index preindex = null;
Post_index posindex = null;
Immediate imm7 = null;
if (o3.isReg())
regM = (Register) o3;
else if (o3.isPostIndex()){
posindex = (Post_index) o3;
regM = posindex.getRegister();
imm7 = posindex.getPostIndex();
}
else if(o3.isPreIndex()){
preindex = (Pre_index) o3;
regM = preindex.getRegister();
imm7 = preindex.getPreIndex();
}
if(o4 != _none && o4.isImm())
imm7 = (Immediate) o4;
if (id.group == ldstexcl || id.group == ldstnapair_offs){
if(o1.size() == SIZE_DWORD )
inst_to_emit |= 0b1 << 30;
else if(o1.size() == SIZE_QWORD )
inst_to_emit |= 0b1 << 31;
}
else{
if(o1.size() == SIZE_DWORD)
inst_to_emit |= 0b1 << 31;
}
inst_to_emit |= regD.code & 0b11111;
inst_to_emit |= (regN.code & 0b11111) << 10;
inst_to_emit |= (regM.code & 0b11111) << 5;
/* For the 32-bit variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256
to 252, defaulting to 0 and encoded in the "imm7" field as /4.
For the 64-bit variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512
to 504, defaulting to 0 and encoded in the "imm7" field as /8. */
if(imm7 != null)
inst_to_emit |= ((imm7.value()>>((o1.size() == SIZE_DWORD)?(3):(2))) & 0b1111111) << 15;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case loadlit:
{
int inst_to_emit = 0;
if (o1.isReg() || id.code == INST_PRFM_LOADLIT__LITERAL){
Register regD = null;
PRFOP_ENUM prfop = null;
if(id.code == INST_PRFM_LOADLIT__LITERAL)
prfop = (PRFOP_ENUM)o1;
else
regD = (Register) o1;
Immediate lbl = (Immediate) o2;
if(o1.size() == SIZE_DWORD && id.code != INST_PRFM_LOADLIT__LITERAL)
inst_to_emit |= 0b1 << 30;
if(id.code == INST_PRFM_LOADLIT__LITERAL)
inst_to_emit |= prfop.intValue() & 0b11111;
else
inst_to_emit |= regD.code & 0b11111;
/* Is the program label from which the data is to be loaded. Its offset from the address of this
instruction, in the range +/-1MB, is encoded as "imm19" times 4.*/
inst_to_emit |= (lbl.value()>>2 & 0x7fff) << 5;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case log_imm:
{
int inst_to_emit = 0;
if (o1.isReg() && o2.isReg() && o3.isImm()){
Register regD = (Register) o1;
Register regN = (Register) o2;
Immediate imm = (Immediate) o3;
if(o1.size() == SIZE_DWORD)
inst_to_emit |= 0b1 << 31;
else
inst_to_emit &= ~(0b1 << 22);
inst_to_emit |= regD.code & 0b11111;
inst_to_emit |= (regN.code & 0b11111) << 5;
if(o1.size() == SIZE_DWORD)
inst_to_emit |= (imm.value() & 0x1fff) << 10;
else
inst_to_emit |= (imm.value() & 0xfff) << 10;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case log_shift:
{
int inst_to_emit = 0;
if (o1.isReg() && o2.isReg()){
Register regD = (Register) o1;
Register regN = (Register) o2;
Register regM = null;
if(o3 != _none) regM = (Register) o3;
Shift sft = null;
if(o4 != _none)
sft = (Shift) o4;
if(o1.size() == SIZE_DWORD)
inst_to_emit |= 0b1 << 31;
inst_to_emit |= regD.code & 0b11111;
if(id.code == INST_MOV_LOG_SHIFT){
inst_to_emit |= (regN.code & 0b11111) << 5;
}
else{
inst_to_emit |= (regN.code & 0b11111) << 5;
inst_to_emit |= (regM.code & 0b11111) << 16;
}
if(sft != null){
inst_to_emit |= (sft.value() & 0b111111) << 10;
inst_to_emit |= (sft.type() & 0b11) << 22;
}
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case movewide:
{
int inst_to_emit = 0;
if (o1.isReg() && o2.isImm()){
Register regD = (Register) o1;
Immediate imm16 = (Immediate) o2;
Shift sft = null;
if(o3 != _none)
sft = (Shift) o3;
if(o1.size() == SIZE_DWORD)
inst_to_emit |= 0b1 << 31;
inst_to_emit |= regD.code & 0b11111;
inst_to_emit |= (imm16.value() & 0xffff) << 5;
if(sft != null && sft.value()%16 == 0 && sft.value() < 49 ) /*shift val can be 0, 16, 32, 48 only*/
inst_to_emit |= (sft.value()>>4 & 0b11) << 21; // type is LSL only,
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case pcreladdr:
{
int inst_to_emit = 0;
if (o1.isReg() && o2.isImm()){
Register regD = (Register) o1;
Immediate imm16 = (Immediate) o2;
inst_to_emit |= regD.code & 0b11111;
/* the program label whose 4KB page address is to be calculated. Its offset from the page address of
this instruction, in the range +/-4GB, is encoded as "immhi:immlo" times 4096.*/
long imm = imm16.value() >> 12;
inst_to_emit |= (imm>>2 & 0x7ffff) << 5;
inst_to_emit |= (imm & 0b11) << 29;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
}
case ic_system:
{
int inst_to_emit = 0;
if(id.code == INST_NOP_IC_SYSTEM || id.code == INST_YIELD_IC_SYSTEM || id.code == INST_WFE_IC_SYSTEM || id.code == INST_WFI_IC_SYSTEM || id.code == INST_SEV_IC_SYSTEM || id.code == INST_SEVL_IC_SYSTEM )
inst_to_emit |= id.opcode;
else if(id.code == INST_HINT_IC_SYSTEM || id.code == INST_CLREX_IC_SYSTEM || id.code == INST_DSB_IC_SYSTEM || id.code == INST_DMB_IC_SYSTEM || id.code == INST_ISB_IC_SYSTEM){
Immediate imm = (Immediate) o1;
if(id.code == INST_HINT_IC_SYSTEM)
inst_to_emit |= (imm.value() & 0b1111111) << 5; /* Is a 7-bit unsigned immediate, in the range 0 to 127, encoded in "CRm:op2".*/
else
inst_to_emit |= (imm.value() & 0b1111) << 8;
}
else if(id.code == INST_MSR_IC_SYSTEM_X){
SysRegister sysrt = (SysRegister) o1;
Register rt = (Register) o2;
SysRegDescription sysregid = SysRegDescription.find(sysrt.getEnum());
inst_to_emit |= (sysregid.reg_code & 0xffff) << 5;
inst_to_emit |= rt.code & 0b11111;
}
else if(id.code == INST_SYS_IC_SYSTEM || id.code == INST_SYSL_IC_SYSTEM){
Immediate imm3_op1 = (Immediate) o1;
Register Rt = (Register) o1;
Register cRn = (Register) o2;
Immediate imm3_op1_2 = (Immediate) o2;
Register cRm = (Register) o3;
Register cRn_2 = (Register) o3;
Immediate imm3_op2_4 = (Immediate) o4;
Register cRm_2 = (Register) o4;
Register rt = null;
Immediate imm3_op2_5_2 = null;
if(o5 != null){
rt = (Register) o5;
imm3_op2_5_2 = (Immediate) o5;
}
inst_to_emit |= (((id.code == INST_SYS_IC_SYSTEM) ? (imm3_op1.value()) : (imm3_op1_2.value())) & 0b111) << 16;
inst_to_emit |= (((id.code == INST_SYS_IC_SYSTEM) ? (cRn.code()) : (cRn_2.code())) & 0b1111) << 12;
inst_to_emit |= (((id.code == INST_SYS_IC_SYSTEM) ? (cRm.code()) : (cRm_2.code())) & 0b1111) << 8;
inst_to_emit |= (((id.code == INST_SYS_IC_SYSTEM) ? (imm3_op2_4.value()) : (imm3_op2_5_2.value())) & 0b111) << 5;
if(id.code == INST_SYS_IC_SYSTEM)
if(rt != null)
inst_to_emit |= rt.code() & 0b11111;
else
inst_to_emit |= 0b11111; /* Is the 64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.*/
else
inst_to_emit |= Rt.code() & 0b11111;
}
else
throw new IllegalArgumentException("illegal arguments");
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
break;
}
case testbranch:
{
int inst_to_emit = 0;
if (o1.isReg()){
Register regD = (Register) o1;
Immediate imm = (Immediate) o2;
Immediate lbl_imm14 = (Immediate) o3;
inst_to_emit |= regD.code & 0b11111;
/* Is the bit number to be tested, in the range 0 to 63, encoded in "b5:b40".*/
inst_to_emit |= (imm.value() & 0b11111) << 19;
inst_to_emit |= (imm.value()>>5 & 0b1) << 31;
inst_to_emit |= (lbl_imm14.value() & 0x3fff) << 5;
inst_to_emit |= id.opcode;
_emitInt32(inst_to_emit);
}
else
throw new IllegalArgumentException("illegal arguments");
break;
} /*END of case testbranch:*/
} /*END of switch(id.group)*/
} /*END of void _emita64(INST_CODE code, Operand o1, Operand o2, Operand o3, Operand o4, Operand o5)*/
void _emitJmpOrCallReloc(InstructionGroup instruction, long target) {
RelocData rd = new RelocData(RelocData.Type.ABSOLUTE_TO_RELATIVE_TRAMPOLINE, 4, offset(), target);
_relocData.add(rd);
// Emit dummy 32-bit integer (will be overwritten by relocCode()).
_emitInt32(0);
}
public void relocCode(ByteBuffer buffer, long address) {
// Copy code to virtual memory (this is a given _dst pointer).
int csize = codeSize();
// We are copying exactly size of generated code. Extra code for trampolines
// is generated on-the-fly by relocator (this code not exists at now).
_buffer.copyTo(buffer);
// Relocate recorded locations.
for (RelocData r : _relocData) {
long val;
// Be sure that reloc data structure is correct.
assert ((r.offset + r.size) <= csize);
switch (r.type) {
case ABSOLUTE_TO_ABSOLUTE:
val = r.destination;
break;
case RELATIVE_TO_ABSOLUTE:
val = address + r.destination;
break;
case ABSOLUTE_TO_RELATIVE:
case ABSOLUTE_TO_RELATIVE_TRAMPOLINE:
if ( (r.destination-(address+r.offset)) > (128*1024*1024) )
System.out.println("IMPOSSIBLE JUMP : ADDRESS AHEAD OF RANGE of 128MB");
if ( (r.destination-(address+r.offset)) < -(128*1024*1024) )
System.out.println("IMPOSSIBLE JUMP : ADDRESS BELOW OF RANGE of 128MB");
val = ((r.destination)-(address+r.offset))/4;
break;
default:
throw new IllegalStateException("invalid relocation type");
}
switch (r.size) {
case 4:
val &= (int)0x3FFFFFF; /*mask for imm27 val*/
val |= 0x94000000; /*opcode for BL*/
buffer.putInt(r.offset, (int) val);
break;
case 8:
buffer.putLong(r.offset, val);
break;
default:
throw new IllegalStateException("invalid relocation size");
}
}
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/BaseReg.java 0000664 0000000 0000000 00000002340 13344175732 0023755 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import static jnr.a64asm.REG.*;
public abstract class BaseReg extends Operand {
public final int code;
public BaseReg(int code, int size) {
super(OP.OP_REG, size);
this.code = code;
}
//! @brief Return register type, see @c REG.
public final int type() {
return code() & REGTYPE_MASK;
}
//! @brief Return register code, see @c REG.
public final int code() {
return code;
}
//! @brief Return register index (value from 0 to 7/15).
public final int index() {
return code() & REGCODE_MASK;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/CONDITION.java 0000664 0000000 0000000 00000003407 13344175732 0024000 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public enum CONDITION {
//! @brief No condition code.
C_NO_CONDITION (-1),
// Condition codes from processor manuals.
C_EQ (0x0),
C_NE (0x1),
C_CS (0x2),
C_CC (0x3),
C_MI (0x4),
C_PL (0x5),
C_VS (0x6),
C_VC (0x7),
C_HI (0x8),
C_LS (0x9),
C_GE (0x10),
C_LT (0x11),
C_GT (0x12),
C_LE (0x13),
C_AL (0x14),
C_NV (0x15),
C_HS (0x2),
C_LO (0x3) ,
// Simplified condition codes
C_EQUAL (0x0),
C_NOT_EQUAL (0x1),
C_ABOVE_EQUAL (0x2),
C_BELOW (0x3),
C_SIGN (0x4),
C_POSITIVE_ZERO (0x5),
C_OVERFLOW (0x6),
C_NO_OVERFLOW (0x7),
C_ABOVE (0x8),
C_BELOW_EQUAL (0x9),
C_GREATER_EQUAL (0xA),
C_LESS (0xB),
C_GREATER (0xC),
C_LESS_EQUAL (0xD),
C_DEFAULT (0xE),
// aliases
C_ZERO (0x0),
C_NOT_ZERO (0x1),
C_NEGATIVE (0x4),
C_POSITIVE (0x5);
private final int value;
CONDITION(int value) {
this.value = value;
}
public final int value() {
return this.value;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/CPU_A64.java 0000664 0000000 0000000 00000001464 13344175732 0023514 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public enum CPU_A64 {
Aarch32, Aarch64, X86_32, X86_64;
public static final CPU_A64 I386 = X86_32;
public static final CPU_A64 A64 = Aarch64;
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/CodeBuffer.java 0000664 0000000 0000000 00000005223 13344175732 0024454 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import java.nio.ByteBuffer;
import java.nio.ByteOrder;
final class CodeBuffer {
private ByteBuffer buf;
public CodeBuffer() {
buf = ByteBuffer.allocate(128).order(ByteOrder.LITTLE_ENDIAN);
}
public final void ensureSpace() {
if (buf.remaining() < 16) {
grow();
}
}
public void grow() {
int newSize = buf.capacity() * 2;
ByteBuffer newBuffer = ByteBuffer.allocate(newSize).order(ByteOrder.BIG_ENDIAN);
// Copy the data over
buf.flip();
newBuffer.put(buf);
buf = newBuffer;
}
final void copyTo(ByteBuffer dst) {
ByteBuffer dup = buf.duplicate();
dup.flip();
dst.put(dup);
}
public final int offset() {
return buf.position();
}
public int capacity() {
return buf.capacity();
}
public final void emitByte(byte x) {
buf.put(x);
}
public final void emitWord(short x) {
buf.putShort(x);
}
public final void emitDWord(int x) {
buf.putInt(x);
}
public final void emitQWord(long x) {
buf.putLong(x);
}
public final void emitData(ByteBuffer data, int len) {
ByteBuffer dup = data.duplicate();
if (dup.remaining() > len) {
dup.limit(dup.position() + len);
}
buf.put(dup);
}
public final byte getByteAt(int pos) {
return buf.get(pos);
}
public final short getWordAt(int pos) {
return buf.getShort(pos);
}
public final int getDWordAt(int pos) {
return buf.getInt(pos);
}
public final long getQWordAt(int pos) {
return buf.getLong(pos);
}
public final void setByteAt(int pos, byte x) {
buf.put(pos, x);
}
public final void setWordAt(int pos, short x) {
buf.putShort(pos, x);
}
public final void setDWordAt(int pos, int x) {
buf.putInt(pos, x);
}
public final void setQWordAt(int pos, long x) {
buf.putLong(pos, x);
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Conditions.java 0000664 0000000 0000000 00000001602 13344175732 0024556 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public final class Conditions extends Operand {
private final int value;
public Conditions(int value) {
super(OP.OP_COND, 0);
this.value = value;
}
public long value() {
return value;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/CpuInfo.java 0000664 0000000 0000000 00000002035 13344175732 0024011 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
/*
* Information about target CPU
*/
public class CpuInfo {
final Vendor vendor;
final int family;
public enum Vendor {
INTEL,
AMD,
ARM,
GENERIC;
}
public static final CpuInfo GENERIC = new CpuInfo(Vendor.GENERIC, 0);
public CpuInfo(Vendor vendor, int family) {
this.vendor = vendor;
this.family = family;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/ERROR_CODE.java 0000664 0000000 0000000 00000003320 13344175732 0024127 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public enum ERROR_CODE {
/** No error (success). */
ERROR_NONE,
/** Memory allocation error (@c ASMJIT_MALLOC returned @c NULL). */
ERROR_NO_HEAP_MEMORY,
/** Virtual memory allocation error (@c VirtualMemory returned @c NULL). */
ERROR_NO_VIRTUAL_MEMORY,
/** Unknown instruction. This happens only if instruction code is
*out of bounds. Shouldn't happen. */
ERROR_UNKNOWN_INSTRUCTION,
/**
* Illegal instruction.
*
* Usually generated by AsmJit::AssemblerCore class when emitting instruction
* opcode. If this error is generated the target buffer is not affected by
* this invalid instruction. In debug mode you get assertion failure instead.
*/
ERROR_ILLEGAL_INSTRUCTION,
/** Illegal addressing used (unencodable). */
ERROR_ILLEGAL_ADDRESING,
/** Short jump instruction used, but displacement is out of bounds. */
ERROR_ILLEGAL_SHORT_JUMP,
/** Count of error codes by AsmJit. Can grow in future. */
_ERROR_COUNT;
public final int intValue() {
return ordinal();
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/EXTEND_ENUM.java 0000664 0000000 0000000 00000001517 13344175732 0024265 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public enum EXTEND_ENUM {
UXTB,
UXTH,
UXTW,
LSL,
UXTX,
SXTB,
SXTH,
SXTW,
SXTX;
public final int intValue() {
return ordinal();
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Ext.java 0000664 0000000 0000000 00000001755 13344175732 0023216 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public final class Ext extends Operand {
private final long value;
private final long type;
public Ext(long type, long value) {
super(OP.OP_EXT, 0);
this.value = value;
this.type = type;
}
public long value() {
return value;
}
public long type() {
return type;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/ExtendedValue.java 0000664 0000000 0000000 00000001470 13344175732 0025205 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public class ExtendedValue{
boolean lsl;
int value;
ExtendedValue(boolean lsl, int value){
this.lsl = lsl;
this.value = value;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/INST_CODE.java 0000664 0000000 0000000 00000017030 13344175732 0024016 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public enum INST_CODE {
INST_ADC_ADDSUB_CARRY,
INST_ADCS_ADDSUB_CARRY,
INST_ADD_ADDSUB_IMM,
INST_ADD_ADDSUB_IMM_SP,
INST_ADD_ADDSUB_SHIFT,
INST_ADD_EXT_ADDSUB_EXT,
INST_ADDS_ADDSUB_EXT,
INST_ADDS_ADDSUB_SHIFT,
INST_ADDS_ADDSUB_IMM,
INST_ADR_PCRELADDR,
INST_ADRP_PCRELADDR,
INST_AND_LOG_IMM,
INST_AND_LOG_SHIFT,
INST_ANDS_LOG_IMM,
INST_ANDS_LOG_SHIFT,
INST_ASR_BITFIELD,
INST_ASR_DP_2SRC,
INST_ASRV_DP_2SRC,
INST_AT_IC_SYSTEM,
INST_B_C_CONDBRANCH,
INST_B_BRANCH_IMM,
INST_BCC_CONDBRANCH,
INST_BCS_CONDBRANCH,
INST_BEQ_CONDBRANCH,
INST_BFI_BITFIELD,
INST_BFM_BITFIELD,
INST_BFXIL_BITFIELD,
INST_BGE_CONDBRANCH,
INST_BGT_CONDBRANCH,
INST_BHI_CONDBRANCH,
INST_BHS_CONDBRANCH,
INST_BIC_LOG_IMM,
INST_BIC_LOG_SHIFT,
INST_BICS_LOG_SHIFT,
INST_BL_BRANCH_IMM,
INST_BLE_CONDBRANCH,
INST_BLO_CONDBRANCH,
INST_BLR_BRANCH_REG,
INST_BLS_CONDBRANCH,
INST_BLT_CONDBRANCH,
INST_BMI_CONDBRANCH,
INST_BNE_CONDBRANCH,
INST_BPL_CONDBRANCH,
INST_BR_BRANCH_REG,
INST_BRK_EXCEPTION,
INST_BVC_CONDBRANCH,
INST_BVS_CONDBRANCH,
INST_CBNZ_COMPBRANCH,
INST_CBZ_COMPBRANCH,
INST_CCMN_CONDCMP_IMM,
INST_CCMN_CONDCMP_REG,
INST_CCMP_CONDCMP_IMM,
INST_CCMP_CONDCMP_REG,
INST_CINC_CONDSEL,
INST_CINV_CONDSEL,
INST_CLREX_IC_SYSTEM,
INST_CLS_DP_1SRC,
INST_CLZ_DP_1SRC,
INST_CMN_ADDSUB_EXT,
INST_CMN_ADDSUB_IMM,
INST_CMN_ADDSUB_SHIFT,
INST_CMP_ADDSUB_EXT,
INST_CMP_ADDSUB_IMM,
INST_CMP_ADDSUB_SHIFT,
INST_CNEG_CONDSEL,
INST_CSEL_CONDSEL,
INST_CSET_CONDSEL,
INST_CSETM_CONDSEL,
INST_CSINC_CONDSEL,
INST_CSINV_CONDSEL,
INST_CSNEG_CONDSEL,
INST_DC_IC_SYSTEM,
INST_DCPS1_EXCEPTION,
INST_DCPS2_EXCEPTION,
INST_DCPS3_EXCEPTION,
INST_DMB_IC_SYSTEM,
INST_DRPS_BRANCH_REG,
INST_DSB_IC_SYSTEM,
INST_EON_LOG_SHIFT,
INST_EOR_LOG_IMM,
INST_EOR_LOG_SHIFT,
INST_ERET_BRANCH_REG,
INST_EXTR_EXTRACT,
INST_HINT_IC_SYSTEM,
INST_HLT_EXCEPTION,
INST_HVC_EXCEPTION,
INST_IC_IC_SYSTEM,
INST_ISB_IC_SYSTEM,
INST_LDAR_LDSTEXCL,
INST_LDARB_LDSTEXCL,
INST_LDARH_LDSTEXCL,
INST_LDAXP_LDSTEXCL,
INST_LDAXR_LDSTEXCL,
INST_LDAXRB_LDSTEXCL,
INST_LDAXRH_LDSTEXCL,
INST_LDNP_LDSTNAPAIR_OFFS,
INST_LDNP_LDSTNAPAIR_OFFS_V,
INST_LDP_POST_INDEXED_IDST_IMM9,
INST_LDP_PRE_INDEXED_IDST_IMM9,
INST_LDP_LDSTPAIR_INDEXED_V,
INST_LDP_LDSTPAIR_OFF_LDST_POS,
INST_LDP_LDSTPAIR_OFF_V,
INST_LDPSW_POST_INDEXED,
INST_LDPSW_PRE_INDEXED,
INST_LDPSW_OFF,
INST_LDR_IMM_POST,
INST_LDR_IMM_OFF,
INST_LDR_REG,
INST_LDR_IMM_PRE,
INST_LDR_LOADLIT,
INST_LDRB_IMM_POST,
INST_LDRB_IMM_PRE,
INST_LDRB_IMM_OFF,
INST_LDRB_REG,
INST_LDRH_IMM_POST,
INST_LDRH_IMM_PRE,
INST_LDRH_IMM_OFF,
INST_LDRH_REG,
INST_LDRSB_IMM_POST,
INST_LDRSB_IMM_PRE,
INST_LDRSB_IMM_OFF,
INST_LDRSB_REG,
INST_LDRSH_IMM_POST,
INST_LDRSH_IMM_PRE,
INST_LDRSH_IMM_OFF,
INST_LDRSH_REG,
INST_LDRSW_IMM_POST,
INST_LDRSW_IMM_PRE,
INST_LDRSW_IMM_OFF,
INST_LDRSW_REG,
INST_LDRSW_LOADLIT,
INST_LDTR_LDST_UNPRIV,
INST_LDTRB_LDST_UNPRIV,
INST_LDTRH_LDST_UNPRIV,
INST_LDTRSB_LDST_UNPRIV,
INST_LDTRSH_LDST_UNPRIV,
INST_LDTRSW_LDST_UNPRIV,
INST_LDUR_LDST_UNSCALED,
INST_LDUR_LDST_UNSCALED_X,
INST_LDURB_LDST_UNSCALED,
INST_LDURH_LDST_UNSCALED,
INST_LDURSB_LDST_UNSCALED,
INST_LDURSH_LDST_UNSCALED,
INST_LDURSW_LDST_UNSCALED,
INST_LDXP_LDSTEXCL,
INST_LDXR_LDSTEXCL,
INST_LDXRB_LDSTEXCL,
INST_LDXRH_LDSTEXCL,
INST_LSL_BITFIELD,
INST_LSL_DP_2SRC,
INST_LSLV_DP_2SRC,
INST_LSR_BITFIELD,
INST_LSR_DP_2SRC,
INST_LSRV_DP_2SRC,
INST_MADD_DP_3SRC,
INST_MNEG_DP_3SRC,
INST_MOV_ADDSUB_IMM,
INST_MOV_LOG_IMM,
INST_MOV_LOG_SHIFT,
INST_MOV_MOVEWIDE,
INST_MOV_MOVEWIDE_X,
INST_MOVK_MOVEWIDE,
INST_MOVN_MOVEWIDE,
INST_MOVZ_MOVEWIDE,
INST_MRS_IC_SYSTEM,
INST_MSR_IC_SYSTEM,
INST_MSR_IC_SYSTEM_X,
INST_MSUB_DP_3SRC,
INST_MUL_DP_3SRC,
INST_MVN_LOG_SHIFT,
INST_NEG_ADDSUB_SHIFT,
INST_NEGS_ADDSUB_SHIFT,
INST_NGC_ADDSUB_CARRY,
INST_NGCS_ADDSUB_CARRY,
INST_NOP_IC_SYSTEM,
INST_ORN_LOG_SHIFT,
INST_ORR_LOG_IMM,
INST_ORR_LOG_SHIFT,
INST_PRFM_LDST_POS__IMMEDIATE,
INST_PRFM_LDST_REGOFF__REGISTER,
INST_PRFM_LDST_UNSCALED,
INST_PRFM_LOADLIT__LITERAL,
INST_PRFUM_LDST_UNSCALED,
INST_RBIT_DP_1SRC,
INST_RET_BRANCH_REG,
INST_REV_DP_1SRC,
INST_REV_DP_1SRC_X,
INST_REV16_DP_1SRC,
INST_REV32_DP_1SRC,
INST_ROR_DP_2SRC,
INST_ROR_EXTRACT,
INST_RORV_DP_2SRC,
INST_SBC_ADDSUB_CARRY,
INST_SBCS_ADDSUB_CARRY,
INST_SBFIZ_BITFIELD,
INST_SBFM_BITFIELD,
INST_SBFX_BITFIELD,
INST_SDIV_DP_2SRC,
INST_SEV_IC_SYSTEM,
INST_SEVL_IC_SYSTEM,
INST_SMADDL_DP_3SRC,
INST_SMC_EXCEPTION,
INST_SMNEGL_DP_3SRC,
INST_SMSUBL_DP_3SRC,
INST_SMULH_DP_3SRC,
INST_SMULL_DP_3SRC,
INST_STLR_LDSTEXCL,
INST_STLRB_LDSTEXCL,
INST_STLRH_LDSTEXCL,
INST_STLXP_LDSTEXCL,
INST_STLXR_LDSTEXCL,
INST_STLXRB_LDSTEXCL,
INST_STLXRH_LDSTEXCL,
INST_STNP_LDSTNAPAIR_OFFS,
INST_STNP_LDSTNAPAIR_OFFS_X,
INST_STP_LDSTPAIR_INDEXED_POST,
INST_STP_LDSTPAIR_INDEXED_PRE,
INST_STP_LDSTPAIR_OFF,
INST_STR_LDST_IMM9_PRE,
INST_STR_LDST_IMM9_POST,
INST_STR_LDST_POS,
INST_STR_LDST_REGOFF,
INST_STRB_LDST_IMM9_POST,
INST_STRB_LDST_OFFSET,
INST_STRB_LDST_REGOFF,
INST_STRB_LDST_PRE,
INST_STRH_LDST_IMM_PRE,
INST_STRH_LDST_IMM_POST,
INST_STRH_LDST_IMM_OFF,
INST_STRH_LDST_REGOFF,
INST_STTR_LDST_UNPRIV,
INST_STTRB_LDST_UNPRIV,
INST_STTRH_LDST_UNPRIV,
INST_STUR_LDST_UNSCALED,
INST_STUR_LDST_UNSCALED_X,
INST_STURB_LDST_UNSCALED,
INST_STURH_LDST_UNSCALED,
INST_STXP_LDSTEXCL,
INST_STXR_LDSTEXCL,
INST_STXRB_LDSTEXCL,
INST_STXRH_LDSTEXCL,
INST_SUB_ADDSUB_EXT,
INST_SUB_ADDSUB_IMM,
INST_SUB_ADDSUB_SHIFT,
INST_SUBS_ADDSUB_EXT,
INST_SUBS_ADDSUB_IMM,
INST_SUBS_ADDSUB_SHIFT,
INST_SVC_EXCEPTION,
INST_SXTB_BITFIELD,
INST_SXTH_BITFIELD,
INST_SXTW_BITFIELD,
INST_SYS_IC_SYSTEM,
INST_SYSL_IC_SYSTEM,
INST_TBNZ_TESTBRANCH,
INST_TBZ_TESTBRANCH,
INST_TLBI_IC_SYSTEM,
INST_TST_LOG_IMM,
INST_TST_LOG_SHIFT,
INST_UBFIZ_BITFIELD,
INST_UBFM_BITFIELD,
INST_UBFX_BITFIELD,
INST_UDIV_DP_2SRC,
INST_UMADDL_DP_3SRC,
INST_UMNEGL_DP_3SRC,
INST_UMSUBL_DP_3SRC,
INST_UMULH_DP_3SRC,
INST_UMULL_DP_3SRC,
INST_UXTB_BITFIELD,
INST_UXTH_BITFIELD,
INST_UXTW_LOG_SHIFT,
INST_WFE_IC_SYSTEM,
INST_WFI_IC_SYSTEM,
INST_YIELD_IC_SYSTEM;
public static final INST_CODE valueOf(int idx) {
return values()[idx];
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Immediate.java 0000664 0000000 0000000 00000003401 13344175732 0024342 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public final class Immediate extends Operand {
private final long value;
private final boolean isUnsigned;
private final RELOC_MODE relocMode;
public Immediate(long value, boolean isUnsigned) {
super(OP.OP_IMM, 0);
this.value = value;
this.isUnsigned = isUnsigned;
this.relocMode = RELOC_MODE.RELOC_NONE;
}
public long value() {
return value;
}
public final byte byteValue() {
return (byte) value;
}
public final short shortValue() {
return (short) value;
}
public final int intValue() {
return (int) value;
}
public final long longValue() {
return value;
}
/** Return true if immediate is unsigned value. */
public final boolean isUnsigned() {
return isUnsigned;
}
/** Return relocation mode. */
RELOC_MODE relocMode() {
return relocMode;
}
public static final Immediate imm(long value) {
return new Immediate(value, false);
}
public static final Immediate uimm(long value) {
return new Immediate(value, true);
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/InstructionDescription.java 0000664 0000000 0000000 00000053675 13344175732 0027213 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import java.util.EnumMap;
import java.util.Map;
import static jnr.a64asm.INST_CODE.*;
import static jnr.a64asm.InstructionGroup.*;
public final class InstructionDescription {
final INST_CODE code;
final int opcode;
final int mask;
final InstructionGroup group;
private static final Map table
= new EnumMap(INST_CODE.class);
private static final InstructionDescription MAKE_INST(INST_CODE code, int opcode, int mask, InstructionGroup group){
InstructionDescription id = new InstructionDescription(code, opcode, mask, group);
table.put(code, id);
return id;
}
InstructionDescription(INST_CODE code, int opCode, int mask,InstructionGroup group) {
this.code = code;
this.opcode = opCode;
this.mask = mask;
this.group = group;
}
public static final InstructionDescription find(INST_CODE code) {
InstructionDescription id = table.get(code);
if (id == null) {
throw new IllegalArgumentException("no description for " + code);
}
return id;
}
private static final InstructionDescription[] all = {
// Instruction code (enum) | instruction name | group | operator 1 flags| operator 2 flags| r| opCode1 | opcode2
MAKE_INST(INST_ADC_ADDSUB_CARRY, 0x1a000000, 0x7fe0fc00, addsub_carry),
MAKE_INST(INST_ADCS_ADDSUB_CARRY, 0x3a000000, 0x7fe0fc00, addsub_carry),
MAKE_INST(INST_ADD_ADDSUB_IMM, 0x11000000, 0x7f000000, addsub_imm),
MAKE_INST(INST_ADD_ADDSUB_SHIFT, 0xb000000, 0x7f200000, addsub_shift),
MAKE_INST(INST_ADDS_ADDSUB_IMM, 0x31000000, 0x7f000000, addsub_imm),
MAKE_INST(INST_ADD_EXT_ADDSUB_EXT, 0x0b200000, 0x7fe00000, addsub_ext),
MAKE_INST(INST_ADDS_ADDSUB_EXT, 0x2b200000, 0x7fe00000, addsub_ext),
MAKE_INST(INST_ADDS_ADDSUB_SHIFT, 0x2b000000, 0x7f200000, addsub_shift),
MAKE_INST(INST_ADR_PCRELADDR, 0x10000000, 0x9f000000, pcreladdr),
MAKE_INST(INST_ADRP_PCRELADDR, 0x90000000, 0x9f000000, pcreladdr),
MAKE_INST(INST_AND_LOG_IMM, 0x12000000, 0x7f800000, log_imm),
MAKE_INST(INST_AND_LOG_SHIFT, 0xa000000, 0x7f200000, log_shift),
MAKE_INST(INST_ANDS_LOG_IMM, 0x72000000, 0x7f800000, log_imm),
MAKE_INST(INST_ANDS_LOG_SHIFT, 0x6a000000, 0x7f200000, log_shift),
MAKE_INST(INST_ASR_BITFIELD, 0x13000000, 0x7f800000, bitfield),
MAKE_INST(INST_ASR_DP_2SRC, 0x1ac02800, 0x7fe0fc00, dp_2src),
MAKE_INST(INST_ASRV_DP_2SRC, 0x1ac02800, 0x7fe0fc00, dp_2src),
MAKE_INST(INST_AT_IC_SYSTEM, 0xd5080000, 0xfff80000, ic_system),
MAKE_INST(INST_B_C_CONDBRANCH, 0x14000000, 0xfc000000, condbranch),
MAKE_INST(INST_B_BRANCH_IMM, 0x54000000, 0xff000010, branch_imm),
MAKE_INST(INST_BCC_CONDBRANCH, 0x54000003, 0xff00001f, condbranch),
MAKE_INST(INST_BCS_CONDBRANCH, 0x54000002, 0xff00001f, condbranch),
MAKE_INST(INST_BEQ_CONDBRANCH, 0x54000000, 0xff00001f, condbranch),
MAKE_INST(INST_BFI_BITFIELD, 0x33000000, 0x7f800000, bitfield),
MAKE_INST(INST_BFM_BITFIELD, 0x33000000, 0x7f800000, bitfield),
MAKE_INST(INST_BFXIL_BITFIELD, 0x33000000, 0x7f800000, bitfield),
MAKE_INST(INST_BGE_CONDBRANCH, 0x5400000a, 0xff00001f, condbranch),
MAKE_INST(INST_BGT_CONDBRANCH, 0x5400000c, 0xff00001f, condbranch),
MAKE_INST(INST_BHI_CONDBRANCH, 0x54000008, 0xff00001f, condbranch),
MAKE_INST(INST_BHS_CONDBRANCH, 0x54000002, 0xff00001f, condbranch),
MAKE_INST(INST_BIC_LOG_IMM, 0x12000000, 0x7f800000, log_imm),
MAKE_INST(INST_BIC_LOG_SHIFT, 0xa200000, 0x7f200000, log_shift),
MAKE_INST(INST_BICS_LOG_SHIFT, 0x6a200000, 0x7f200000, log_shift),
MAKE_INST(INST_BL_BRANCH_IMM, 0x94000000, 0xfc000000, branch_imm),
MAKE_INST(INST_BLE_CONDBRANCH, 0x5400000d, 0xff00001f, condbranch),
MAKE_INST(INST_BLO_CONDBRANCH, 0x54000003, 0xff00001f, condbranch),
MAKE_INST(INST_BLR_BRANCH_REG, 0xd63f0000, 0xfffffc1f, branch_reg),
MAKE_INST(INST_BLS_CONDBRANCH, 0x54000009, 0xff00001f, condbranch),
MAKE_INST(INST_BLT_CONDBRANCH, 0x5400000b, 0xff00001f, condbranch),
MAKE_INST(INST_BMI_CONDBRANCH, 0x54000004, 0xff00001f, condbranch),
MAKE_INST(INST_BNE_CONDBRANCH, 0x54000001, 0xff00001f, condbranch),
MAKE_INST(INST_BPL_CONDBRANCH, 0x54000005, 0xff00001f, condbranch),
MAKE_INST(INST_BR_BRANCH_REG, 0xd61f0000, 0xfffffc1f, branch_reg),
MAKE_INST(INST_BRK_EXCEPTION, 0xd4200000, 0xffe0001f, exception),
MAKE_INST(INST_BVC_CONDBRANCH, 0x54000007, 0xff00001f, condbranch),
MAKE_INST(INST_BVS_CONDBRANCH, 0x54000006, 0xff00001f, condbranch),
MAKE_INST(INST_CBNZ_COMPBRANCH, 0x35000000, 0x7f000000, compbranch),
MAKE_INST(INST_CBZ_COMPBRANCH, 0x34000000, 0x7f000000, compbranch),
MAKE_INST(INST_CCMN_CONDCMP_IMM, 0x3a400800, 0x7fe00c10, condcmp_imm),
MAKE_INST(INST_CCMN_CONDCMP_REG, 0x3a400000, 0x7fe00c10, condcmp_reg),
MAKE_INST(INST_CCMP_CONDCMP_IMM, 0x7a400800, 0x7fe00c10, condcmp_imm),
MAKE_INST(INST_CCMP_CONDCMP_REG, 0x7a400000, 0x7fe00c10, condcmp_reg),
MAKE_INST(INST_CINC_CONDSEL, 0x1a800400, 0x7fe00c00, condsel),
MAKE_INST(INST_CINV_CONDSEL, 0x5a800000, 0x7fe00c00, condsel),
MAKE_INST(INST_CLREX_IC_SYSTEM, 0xd503305f, 0xfffff0ff, ic_system),
MAKE_INST(INST_CLS_DP_1SRC, 0x5ac01400, 0x7ffffc00, dp_1src),
MAKE_INST(INST_CLZ_DP_1SRC, 0x5ac01000, 0x7ffffc00, dp_1src),
MAKE_INST(INST_CMN_ADDSUB_EXT, 0x2b20001f, 0x7fe0001f, addsub_ext),
MAKE_INST(INST_CMN_ADDSUB_IMM, 0x3100001f, 0x7f00001f, addsub_imm),
MAKE_INST(INST_CMN_ADDSUB_SHIFT, 0x2b00001f, 0x7f20001f, addsub_shift),
MAKE_INST(INST_CMP_ADDSUB_EXT, 0x6b20001f, 0x7fe0001f, addsub_ext),
MAKE_INST(INST_CMP_ADDSUB_IMM, 0x7100001f, 0x7f00001f, addsub_imm),
MAKE_INST(INST_CMP_ADDSUB_SHIFT, 0x6b00001f, 0x7f20001f, addsub_shift),
MAKE_INST(INST_CNEG_CONDSEL, 0x5a800400, 0x7fe00c00, condsel),
MAKE_INST(INST_CSEL_CONDSEL, 0x1a800000, 0x7fe00c00, condsel),
MAKE_INST(INST_CSET_CONDSEL, 0x1a9f07e0, 0x7fff0fe0, condsel),
MAKE_INST(INST_CSETM_CONDSEL, 0x5a9f03e0, 0x7fff0fe0, condsel),
MAKE_INST(INST_CSINC_CONDSEL, 0x1a800400, 0x7fe00c00, condsel),
MAKE_INST(INST_CSINV_CONDSEL, 0x5a800000, 0x7fe00c00, condsel),
MAKE_INST(INST_CSNEG_CONDSEL, 0x5a800400, 0x7fe00c00, condsel),
MAKE_INST(INST_DC_IC_SYSTEM, 0xd5080000, 0xfff80000, ic_system),
MAKE_INST(INST_DCPS1_EXCEPTION, 0xd4a00001, 0xffe0001f, exception),
MAKE_INST(INST_DCPS2_EXCEPTION, 0xd4a00002, 0xffe0001f, exception),
MAKE_INST(INST_DCPS3_EXCEPTION, 0xd4a00003, 0xffe0001f, exception),
MAKE_INST(INST_DMB_IC_SYSTEM, 0xd50330bf, 0xfffff0ff, ic_system),
MAKE_INST(INST_DRPS_BRANCH_REG, 0xd6bf03e0, 0xffffffff, branch_reg),
MAKE_INST(INST_DSB_IC_SYSTEM, 0xd503309f, 0xfffff0ff, ic_system),
MAKE_INST(INST_EON_LOG_SHIFT, 0x4a200000, 0x7f200000, log_shift),
MAKE_INST(INST_EOR_LOG_IMM, 0x52000000, 0x7f800000, log_imm),
MAKE_INST(INST_EOR_LOG_SHIFT, 0x4a000000, 0x7f200000, log_shift),
MAKE_INST(INST_ERET_BRANCH_REG, 0xd69f03e0, 0xffffffff, branch_reg),
MAKE_INST(INST_EXTR_EXTRACT, 0x13800000, 0x7fa00000, extract),
MAKE_INST(INST_HINT_IC_SYSTEM, 0xd503201f, 0xfffff01f, ic_system),
MAKE_INST(INST_HLT_EXCEPTION, 0xd4400000, 0xffe0001f, exception),
MAKE_INST(INST_HVC_EXCEPTION, 0xd4000002, 0xffe0001f, exception),
MAKE_INST(INST_IC_IC_SYSTEM, 0xd5080000, 0xfff80000, ic_system),
MAKE_INST(INST_ISB_IC_SYSTEM, 0xd50330df, 0xfffff0ff, ic_system),
MAKE_INST(INST_LDAR_LDSTEXCL, 0x88dffc00, 0xbfe08000, ldstexcl),
MAKE_INST(INST_LDARB_LDSTEXCL, 0x8dffc00, 0xffe08000, ldstexcl),
MAKE_INST(INST_LDARH_LDSTEXCL, 0x48dffc00, 0xffe08000, ldstexcl),
MAKE_INST(INST_LDAXP_LDSTEXCL, 0x887f8000, 0xbfe08000, ldstexcl_op3),
MAKE_INST(INST_LDAXR_LDSTEXCL, 0x885ffc00, 0xbfe08000, ldstexcl),
MAKE_INST(INST_LDAXRB_LDSTEXCL, 0x85ffc00, 0xffe08000, ldstexcl),
MAKE_INST(INST_LDAXRH_LDSTEXCL, 0x485ffc00, 0xffe08000, ldstexcl),
MAKE_INST(INST_LDNP_LDSTNAPAIR_OFFS, 0x28400000, 0x7fc00000, ldstnapair_offs),
MAKE_INST(INST_LDNP_LDSTNAPAIR_OFFS_V, 0x2c400000, 0x3fc00000, ldstnapair_offs),
MAKE_INST(INST_LDP_POST_INDEXED_IDST_IMM9, 0x28c00000, 0x7ec00000, ldst_imm9_2reg),
MAKE_INST(INST_LDP_PRE_INDEXED_IDST_IMM9, 0x29c00000, 0x7ec00000, ldst_imm9_2reg),
MAKE_INST(INST_LDP_LDSTPAIR_OFF_LDST_POS, 0x29400000, 0x7ec00000, ldst_pos_2reg),
MAKE_INST(INST_LDPSW_POST_INDEXED, 0x68c00000, 0xffc00000, ldstpair_indexed),
MAKE_INST(INST_LDPSW_PRE_INDEXED, 0x69c00000, 0xffc00000, ldstpair_indexed),
MAKE_INST(INST_LDPSW_OFF, 0x69400000, 0xffc00000, ldstpair_off),
MAKE_INST(INST_LDR_IMM_POST, 0xb8400400, 0xbfe00400, ldst_imm9),
MAKE_INST(INST_LDR_IMM_PRE, 0xb8400C00, 0xbfe00c00, ldst_imm9),
MAKE_INST(INST_LDR_IMM_OFF, 0xb9400000, 0xbfc00000, ldst_pos),
MAKE_INST(INST_LDR_REG, 0xb8600800, 0xbfe00c00,ldst_regoff),
MAKE_INST(INST_LDR_LOADLIT, 0x18000000, 0xbf000000, loadlit),
MAKE_INST(INST_LDRB_IMM_POST, 0x38400400, 0xffe00c00, ldst_imm9),
MAKE_INST(INST_LDRB_IMM_PRE, 0x38400c00, 0xffe00c00, ldst_imm9),
MAKE_INST(INST_LDRB_IMM_OFF, 0x39400000, 0xffc00000, ldst_pos),
MAKE_INST(INST_LDRB_REG, 0x38600800, 0xffe00c00, ldst_regoff),
MAKE_INST(INST_LDRH_IMM_POST, 0x78400400, 0xffe00c00, ldst_imm9),
MAKE_INST(INST_LDRH_IMM_PRE, 0x78400c00, 0xffe00c00, ldst_imm9),
MAKE_INST(INST_LDRH_IMM_OFF, 0x79400000, 0xffc00000, ldst_pos),
MAKE_INST(INST_LDRH_REG, 0x78600800, 0xffe00c00, ldst_regoff),
MAKE_INST(INST_LDRSB_IMM_POST, 0x38800400, 0xffa00c00, ldst_imm9),
MAKE_INST(INST_LDRSB_IMM_PRE, 0x38800c00, 0xffa00c00, ldst_imm9),
MAKE_INST(INST_LDRSB_IMM_OFF, 0x39800000, 0xff800000, ldst_pos),
MAKE_INST(INST_LDRSB_REG, 0x38a00800, 0xffa00c00, ldst_regoff),
MAKE_INST(INST_LDRSH_IMM_POST, 0x78800400, 0xffa00c00, ldst_imm9),
MAKE_INST(INST_LDRSH_IMM_PRE, 0x78800c00, 0xffa00c00, ldst_imm9),
MAKE_INST(INST_LDRSH_IMM_OFF, 0x79800000, 0xff800000, ldst_pos),
MAKE_INST(INST_LDRSH_REG, 0x78a00800, 0xffa00c00, ldst_regoff),
MAKE_INST(INST_LDRSW_IMM_POST, 0xb8800400, 0xffe00c00, ldst_imm9),
MAKE_INST(INST_LDRSW_IMM_PRE, 0xb8800C00, 0xffe00c00, ldst_imm9),
MAKE_INST(INST_LDRSW_IMM_OFF, 0xb9800000, 0xffc00000, ldst_pos),
MAKE_INST(INST_LDRSW_REG, 0xb8a00800, 0xffe00c00, ldst_regoff),
MAKE_INST(INST_LDRSW_LOADLIT, 0x98000000, 0xff000000, loadlit),
MAKE_INST(INST_LDTR_LDST_UNPRIV, 0xb8400800, 0xbfe00c00, ldst_unpriv),
MAKE_INST(INST_LDTRB_LDST_UNPRIV, 0x38400800, 0xffe00c00, ldst_unpriv),
MAKE_INST(INST_LDTRH_LDST_UNPRIV, 0x78400800, 0xffe00c00, ldst_unpriv),
MAKE_INST(INST_LDTRSB_LDST_UNPRIV, 0x38800800, 0xffa00c00, ldst_unpriv),
MAKE_INST(INST_LDTRSH_LDST_UNPRIV, 0x78800800, 0xffa00c00, ldst_unpriv),
MAKE_INST(INST_LDTRSW_LDST_UNPRIV, 0xb8800800, 0xffe00c00, ldst_unpriv),
MAKE_INST(INST_LDUR_LDST_UNSCALED, 0x3c400000, 0x3f600c00, ldst_unscaled),
MAKE_INST(INST_LDUR_LDST_UNSCALED_X, 0xb8400000, 0xbfe00c00, ldst_unscaled),
MAKE_INST(INST_LDURB_LDST_UNSCALED, 0x38400000, 0xffe00c00, ldst_unscaled),
MAKE_INST(INST_LDURH_LDST_UNSCALED, 0x78400000, 0xffe00c00, ldst_unscaled),
MAKE_INST(INST_LDURSB_LDST_UNSCALED, 0x38800000, 0xffa00c00, ldst_unscaled),
MAKE_INST(INST_LDURSH_LDST_UNSCALED, 0x78800000, 0xffa00c00, ldst_unscaled),
MAKE_INST(INST_LDURSW_LDST_UNSCALED, 0xb8800000, 0xffe00c00, ldst_unscaled),
MAKE_INST(INST_LDXP_LDSTEXCL, 0x887f0000, 0xbfe08000, ldstexcl_op3),
MAKE_INST(INST_LDXR_LDSTEXCL, 0x885f7c00, 0xbfe08000, ldstexcl),
MAKE_INST(INST_LDXRB_LDSTEXCL, 0x85f7c00, 0xffe08000, ldstexcl),
MAKE_INST(INST_LDXRH_LDSTEXCL, 0x485f7c00, 0xffe08000, ldstexcl),
MAKE_INST(INST_LSL_BITFIELD, 0x53000000, 0x7f800000, bitfield),
MAKE_INST(INST_LSL_DP_2SRC, 0x1ac02000, 0x7fe0fc00, dp_2src),
MAKE_INST(INST_LSLV_DP_2SRC, 0x1ac02000, 0x7fe0fc00, dp_2src),
MAKE_INST(INST_LSR_BITFIELD, 0x53000000, 0x7f800000, bitfield),
MAKE_INST(INST_LSR_DP_2SRC, 0x1ac02400, 0x7fe0fc00, dp_2src),
MAKE_INST(INST_LSRV_DP_2SRC, 0x1ac02400, 0x7fe0fc00, dp_2src),
MAKE_INST(INST_MADD_DP_3SRC, 0x1b000000, 0x7fe08000, dp_3src),
MAKE_INST(INST_MNEG_DP_3SRC, 0x1b00fc00, 0x7fe0fc00, dp_3src),
MAKE_INST(INST_MOV_ADDSUB_IMM, 0x2a0003e0, 0x7ffffc00, addsub_imm),
MAKE_INST(INST_MOV_LOG_IMM, 0x320003e0, 0x7f8003e0, log_imm),
MAKE_INST(INST_MOV_LOG_SHIFT, 0x110003e0, 0x7f2003e0, log_shift),
MAKE_INST(INST_MOV_MOVEWIDE, 0x12800000, 0x7f800000, movewide),
MAKE_INST(INST_MOV_MOVEWIDE_X, 0x52800000, 0x7f800000, movewide),
MAKE_INST(INST_MOVK_MOVEWIDE, 0x72800000, 0x7f800000, movewide),
MAKE_INST(INST_MOVN_MOVEWIDE, 0x12800000, 0x7f800000, movewide),
MAKE_INST(INST_MOVZ_MOVEWIDE, 0x52800000, 0x7f800000, movewide),
MAKE_INST(INST_MRS_IC_SYSTEM, 0xd5300000, 0xfff00000, ic_system),
MAKE_INST(INST_MSR_IC_SYSTEM, 0xd500401f, 0xfff8f01f, ic_system),
MAKE_INST(INST_MSR_IC_SYSTEM_X, 0xd5100000, 0xfff00000, ic_system),
MAKE_INST(INST_MSUB_DP_3SRC, 0x1b008000, 0x7fe08000, dp_3src),
MAKE_INST(INST_MUL_DP_3SRC, 0x1b007c00, 0x7fe0fc00, dp_3src),
MAKE_INST(INST_MVN_LOG_SHIFT, 0x2a2003e0, 0x7f2003e0, log_shift),
MAKE_INST(INST_NEG_ADDSUB_SHIFT, 0x4b0003e0, 0x7f2003e0, addsub_shift),
MAKE_INST(INST_NEGS_ADDSUB_SHIFT, 0x6b0003e0, 0x7f2003e0, addsub_shift),
MAKE_INST(INST_NGC_ADDSUB_CARRY, 0x5a0003e0, 0x7fe0ffe0, addsub_carry),
MAKE_INST(INST_NGCS_ADDSUB_CARRY, 0x7a0003e0, 0x7fe0ffe0, addsub_carry),
MAKE_INST(INST_NOP_IC_SYSTEM, 0xd503201f, 0xffffffff, ic_system),
MAKE_INST(INST_ORN_LOG_SHIFT, 0x2a200000, 0x7f200000, log_shift),
MAKE_INST(INST_ORR_LOG_IMM, 0x32000000, 0x7f800000, log_imm),
MAKE_INST(INST_ORR_LOG_SHIFT, 0x2a000000, 0x7f200000, log_shift),
MAKE_INST(INST_PRFM_LDST_POS__IMMEDIATE, 0xf9800000, 0xffc00000, ldst_pos),
MAKE_INST(INST_PRFM_LDST_REGOFF__REGISTER, 0xf8a00800, 0xffe00c00, ldst_regoff),
MAKE_INST(INST_PRFM_LOADLIT__LITERAL, 0xd8000000, 0xff000000, loadlit),
MAKE_INST(INST_PRFUM_LDST_UNSCALED, 0xf8800000, 0xffe00c00, ldst_unscaled),
MAKE_INST(INST_RBIT_DP_1SRC, 0x5ac00000, 0x7ffffc00, dp_1src),
MAKE_INST(INST_RET_BRANCH_REG, 0xd65f0000, 0xfffffc1f, branch_reg),
MAKE_INST(INST_REV_DP_1SRC, 0x5ac00800, 0xfffffc00, dp_1src),
MAKE_INST(INST_REV_DP_1SRC_X, 0xdac00c00, 0x7ffffc00, dp_1src),
MAKE_INST(INST_REV16_DP_1SRC, 0x5ac00400, 0x7ffffc00, dp_1src),
MAKE_INST(INST_REV32_DP_1SRC, 0xdac00800, 0xfffffc00, dp_1src),
MAKE_INST(INST_ROR_DP_2SRC, 0x1ac02c00, 0x7fe0fc00, dp_2src),
MAKE_INST(INST_ROR_EXTRACT, 0x13800000, 0x7fa00000, extract),
MAKE_INST(INST_RORV_DP_2SRC, 0x1ac02c00, 0x7fe0fc00, dp_2src),
MAKE_INST(INST_SBC_ADDSUB_CARRY, 0x5a000000, 0x7fe0fc00, addsub_carry),
MAKE_INST(INST_SBCS_ADDSUB_CARRY, 0x7a000000, 0x7fe0fc00, addsub_carry),
MAKE_INST(INST_SBFIZ_BITFIELD, 0x13000000, 0x7f800000, bitfield),
MAKE_INST(INST_SBFM_BITFIELD, 0x13000000, 0x7f800000, bitfield),
MAKE_INST(INST_SBFX_BITFIELD, 0x13000000, 0x7f800000, bitfield),
MAKE_INST(INST_SDIV_DP_2SRC, 0x1ac00c00, 0x7fe0fc00, dp_2src),
MAKE_INST(INST_SEV_IC_SYSTEM, 0xd503209f, 0xffffffff, ic_system),
MAKE_INST(INST_SEVL_IC_SYSTEM, 0xd50320bf, 0xffffffff, ic_system),
MAKE_INST(INST_SMADDL_DP_3SRC, 0x9b200000, 0xffe08000, dp_3src),
MAKE_INST(INST_SMC_EXCEPTION, 0xd4000003, 0xffe0001f, exception),
MAKE_INST(INST_SMNEGL_DP_3SRC, 0x9b20fc00, 0xffe0fc00, dp_3src),
MAKE_INST(INST_SMSUBL_DP_3SRC, 0x9b208000, 0xffe08000, dp_3src),
MAKE_INST(INST_SMULH_DP_3SRC, 0x9b407c00, 0xffe08000, dp_3src),
MAKE_INST(INST_SMULL_DP_3SRC, 0x9b207c00, 0xffe0fc00, dp_3src),
MAKE_INST(INST_STLR_LDSTEXCL, 0x889ffc00, 0xbfe08000, ldstexcl),
MAKE_INST(INST_STLRB_LDSTEXCL, 0x89ffc00, 0xffe08000, ldstexcl),
MAKE_INST(INST_STLRH_LDSTEXCL, 0x489ffc00, 0xffe08000, ldstexcl),
MAKE_INST(INST_STLXP_LDSTEXCL, 0x88208000, 0xbfe08000, ldstexcl_op4),
MAKE_INST(INST_STLXR_LDSTEXCL, 0x8800fc00, 0xbfe08000, ldstexcl_op3),
MAKE_INST(INST_STLXRB_LDSTEXCL, 0x800fc00, 0xffe08000, ldstexcl_op3),
MAKE_INST(INST_STLXRH_LDSTEXCL, 0x4800fc00, 0xffe08000, ldstexcl_op3),
MAKE_INST(INST_STNP_LDSTNAPAIR_OFFS, 0x28000000, 0x7fc00000, ldstnapair_offs),
MAKE_INST(INST_STNP_LDSTNAPAIR_OFFS_X, 0x2c000000, 0x3fc00000, ldstnapair_offs),
MAKE_INST(INST_STP_LDSTPAIR_INDEXED_POST, 0x28800000, 0x7fc00000, ldstpair_indexed),
MAKE_INST(INST_STP_LDSTPAIR_INDEXED_PRE, 0x29800000, 0x7fc00000, ldstpair_indexed),
MAKE_INST(INST_STP_LDSTPAIR_OFF, 0x29000000, 0x7fc00000, ldstpair_off),
MAKE_INST(INST_STR_LDST_IMM9_PRE, 0xb8000c00, 0xbf600c00, ldst_imm9),
MAKE_INST(INST_STR_LDST_IMM9_POST, 0xb8000400, 0xbfe00c00, ldst_imm9),
MAKE_INST(INST_STR_LDST_POS, 0xb9000000, 0xbfc00000, ldst_pos),
MAKE_INST(INST_STR_LDST_REGOFF, 0xb8200800, 0xbfe00c00, ldst_regoff),
MAKE_INST(INST_STRB_LDST_IMM9_POST, 0x38000400, 0xffe00C00, ldst_imm9),
MAKE_INST(INST_STRB_LDST_OFFSET, 0x39000000, 0xffc00000, ldst_pos),
MAKE_INST(INST_STRB_LDST_REGOFF, 0x38200800, 0xffe00c00, ldst_regoff),
MAKE_INST(INST_STRB_LDST_PRE, 0x38000c00, 0xffe00c00, ldst_imm9),
MAKE_INST(INST_STRH_LDST_IMM_PRE, 0x78000c00, 0xffe00c00, ldst_imm9),
MAKE_INST(INST_STRH_LDST_IMM_POST, 0x78000400, 0xffe00c00, ldst_imm9),
MAKE_INST(INST_STRH_LDST_IMM_OFF, 0x79000000, 0xffc00000, ldst_pos),
MAKE_INST(INST_STRH_LDST_REGOFF, 0x78200800, 0xffe00c00, ldst_regoff),
MAKE_INST(INST_STTR_LDST_UNPRIV, 0xb8000800, 0xbfe00c00, ldst_unpriv),
MAKE_INST(INST_STTRB_LDST_UNPRIV, 0x38000800, 0xffe00c00, ldst_unpriv),
MAKE_INST(INST_STTRH_LDST_UNPRIV, 0x78000800, 0xffe00c00, ldst_unpriv),
MAKE_INST(INST_STUR_LDST_UNSCALED, 0x3c000000, 0x3f600c00, ldst_unscaled),
MAKE_INST(INST_STUR_LDST_UNSCALED_X, 0xb8000000, 0xbfe00c00, ldst_unscaled),
MAKE_INST(INST_STURB_LDST_UNSCALED, 0x38000000, 0xffe00c00, ldst_unscaled),
MAKE_INST(INST_STURH_LDST_UNSCALED, 0x78000000, 0xffe00c00, ldst_unscaled),
MAKE_INST(INST_STXP_LDSTEXCL, 0x88200000, 0xbfe08000, ldstexcl_op4),
MAKE_INST(INST_STXR_LDSTEXCL, 0x88007c00, 0xbfe08000, ldstexcl_op3),
MAKE_INST(INST_STXRB_LDSTEXCL, 0x8007c00, 0xffe08000, ldstexcl_op3),
MAKE_INST(INST_STXRH_LDSTEXCL, 0x48007c00, 0xffe08000, ldstexcl_op3),
MAKE_INST(INST_SUB_ADDSUB_EXT, 0x4b200000, 0x7fe00000, addsub_ext),
MAKE_INST(INST_SUB_ADDSUB_IMM, 0x51000000, 0x7f000000, addsub_imm),
MAKE_INST(INST_SUB_ADDSUB_SHIFT, 0x4b000000, 0x7f200000, addsub_shift),
MAKE_INST(INST_SUBS_ADDSUB_EXT, 0x6b200000, 0x7fe00000, addsub_ext),
MAKE_INST(INST_SUBS_ADDSUB_IMM, 0x71000000, 0x7f000000, addsub_imm),
MAKE_INST(INST_SUBS_ADDSUB_SHIFT, 0x6b000000, 0x7f200000, addsub_shift),
MAKE_INST(INST_SVC_EXCEPTION, 0xd4000001, 0xffe0001f, exception),
MAKE_INST(INST_SXTB_BITFIELD, 0x13001c00, 0x7fbffc00, bitfield),
MAKE_INST(INST_SXTH_BITFIELD, 0x13003c00, 0x7fbffc00, bitfield),
MAKE_INST(INST_SXTW_BITFIELD, 0x93407c00, 0xfffffc00, bitfield),
MAKE_INST(INST_SYS_IC_SYSTEM, 0xd5080000, 0xfff80000, ic_system),
MAKE_INST(INST_SYSL_IC_SYSTEM, 0xd5280000, 0xfff80000, ic_system),
MAKE_INST(INST_TBNZ_TESTBRANCH, 0x37000000, 0x7f000000, testbranch),
MAKE_INST(INST_TBZ_TESTBRANCH, 0x36000000, 0x7f000000, testbranch),
MAKE_INST(INST_TLBI_IC_SYSTEM, 0xd5080000, 0xfff80000, ic_system),
MAKE_INST(INST_TST_LOG_IMM, 0x7200001f, 0x7f80001f, log_imm),
MAKE_INST(INST_TST_LOG_SHIFT, 0x6a00001f, 0x7f20001f, log_shift),
MAKE_INST(INST_UBFIZ_BITFIELD, 0x53000000, 0x7f800000, bitfield),
MAKE_INST(INST_UBFM_BITFIELD, 0x53000000, 0x7f800000, bitfield),
MAKE_INST(INST_UBFX_BITFIELD, 0x53000000, 0x7f800000, bitfield),
MAKE_INST(INST_UDIV_DP_2SRC, 0x1ac00800, 0x7fe0fc00, dp_2src),
MAKE_INST(INST_UMADDL_DP_3SRC, 0x9ba00000, 0xffe08000, dp_3src),
MAKE_INST(INST_UMNEGL_DP_3SRC, 0x9ba0fc00, 0xffe0fc00, dp_3src),
MAKE_INST(INST_UMSUBL_DP_3SRC, 0x9ba08000, 0xffe08000, dp_3src),
MAKE_INST(INST_UMULH_DP_3SRC, 0x9bc07c00, 0xffe08000, dp_3src),
MAKE_INST(INST_UMULL_DP_3SRC, 0x9ba07c00, 0xffe0fc00, dp_3src),
MAKE_INST(INST_UXTB_BITFIELD, 0x53001c00, 0xfffffc00, bitfield),
MAKE_INST(INST_UXTH_BITFIELD, 0x53003c00, 0xfffffc00, bitfield),
MAKE_INST(INST_UXTW_LOG_SHIFT, 0xD3407C00, 0x7f2003e0, bitfield),
MAKE_INST(INST_WFE_IC_SYSTEM, 0xd503205f, 0xffffffff, ic_system),
MAKE_INST(INST_WFI_IC_SYSTEM, 0xd503207f, 0xffffffff, ic_system),
MAKE_INST(INST_YIELD_IC_SYSTEM, 0xd503203f, 0xffffffff, ic_system)
};
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/InstructionGroup.java 0000664 0000000 0000000 00000002412 13344175732 0026003 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public enum InstructionGroup {
addsub_carry,
addsub_ext,
addsub_imm,
addsub_shift,
bitfield,
branch_imm,
branch_reg,
compbranch,
condbranch,
condcmp_imm,
condcmp_reg,
condsel,
dp_1src,
dp_2src,
dp_3src,
exception,
extract,
ldst_imm9,
ldst_pos,
ldst_imm9_2reg,
ldst_pos_2reg,
ldst_regoff,
ldst_unpriv,
ldst_unscaled,
ldstexcl,
ldstexcl_op3,
ldstexcl_op4,
ldstnapair_offs,
ldstpair_off,
ldstpair_indexed,
loadlit,
log_imm,
log_shift,
movewide,
pcreladdr,
ic_system,
testbranch;
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/LABEL_STATE.java 0000664 0000000 0000000 00000001544 13344175732 0024231 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public enum LABEL_STATE {
/** Label is unused. */
LABEL_STATE_UNUSED,
/** Label is linked (waiting to be bound) */
LABEL_STATE_LINKED,
/** Label is bound */
LABEL_STATE_BOUND;
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Label.java 0000664 0000000 0000000 00000003636 13344175732 0023475 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import java.util.LinkedList;
import java.util.List;
import static jnr.a64asm.LABEL_STATE.*;
public final class Label extends Operand {
/** Label Id (0 means unknown). */
final int id;
/** State of label, see {@link LABEL_STATE}. */
LABEL_STATE state;
/** Position (always positive, information depends to @c state). */
int position;
final List links = new LinkedList();
public Label() {
this(0);
}
public Label(int id) {
super(OP.OP_LABEL, 4);
this.id = id;
this.state = LABEL_STATE_UNUSED;
this.position = -1;
}
/** Returns @c true if label is unused (not bound or linked). */
final boolean isUnused() {
return state == LABEL_STATE_UNUSED;
}
/** Returns @c true if label is linked. */
final boolean isLinked() {
return state == LABEL_STATE_LINKED;
}
/** Returns @c true if label is bound. */
final boolean isBound() {
return state == LABEL_STATE_BOUND;
}
/** Returns the position of bound or linked labels, -1 if label
* is unused.
*/
final int position() {
return position;
}
final void link(LinkData link) {
links.add(link);
state = LABEL_STATE_LINKED;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/LinkData.java 0000664 0000000 0000000 00000002004 13344175732 0024131 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
final class LinkData {
final int offset;
//! @brief Inlined displacement.
long displacement;
//! @brief RelocId if link must be absolute when relocated.
int relocId;
public LinkData(int offset, long displacement, int relocId) {
this.offset = offset;
this.displacement = displacement;
this.relocId = relocId;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Logger.java 0000664 0000000 0000000 00000001435 13344175732 0023670 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
/**
* Simple wrapper around logging
*/
public class Logger {
public void log(String msg) {}
public void logAlign(long m) {}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Mem.java 0000664 0000000 0000000 00000006330 13344175732 0023166 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import static jnr.a64asm.REG.*;
public class Mem extends Operand {
//! @brief Base register index, see @c REG.
private final int base;
//! @brief Index register index, see @c REG.
private final int index;
//! @brief Index register shift (0 to 3 included).
private final int shift;
private final Ext extend;
private final Label label;
private final long target;
private final long displacement;
Mem(Register base, int size) {
this(base.index(), NO_REG, 0, null, 0, 0, size, null);
}
Mem (Register base, Ext extend, int size){
this(base.index() ,NO_REG, 0, null, 0, 0, size, null);
}
Mem(Label label, long displacement, int size) {
this(NO_REG, NO_REG, 0, label, 0, displacement, size, null);
}
Mem(Register base, long displacement, int size) {
this(base.index(), NO_REG, 0, null, 0, displacement, size, null);
}
Mem(Register base, Register index, int shift, long displacement, int size) {
this(base.index(), index.index(), shift, null, 0, displacement, size, null);
}
Mem(Label label, Register index, int shift, long disp, int ptrSize) {
this(0, index.index(), shift, label, 0, disp, ptrSize, null);
}
Mem(long target, long disp, int ptrSize) {
this(NO_REG, NO_REG, 0, null, target, disp, ptrSize, null);
}
Mem(long target, Register index, int shift, long disp, int ptrSize) {
this(NO_REG, index.index(), shift, null, target, disp, ptrSize, null);
}
private Mem(int base, int index, int shift, Label label, long target, long displacement, int size, Ext extend) {
super(OP.OP_MEM, size);
assert(shift <= 3);
this.base = base;
this.index = index;
this.shift = shift;
this.label = label;
this.target = target;
this.displacement = displacement;
this.extend = extend;
}
public final boolean hasLabel() {
return label != null;
}
//! @brief Return if address has base register.
public final boolean hasBase() {
return base != NO_REG;
}
//! @brief Return if address has index register.
boolean hasIndex() {
return index != NO_REG;
}
public final int base() {
return base;
}
public final long displacement() {
return displacement;
}
public final int index() {
return index;
}
public final Label label() {
return label;
}
public final int shift() {
return shift;
}
public final long target() {
return target;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/OP.java 0000664 0000000 0000000 00000003646 13344175732 0022775 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
/** Operand types that can be encoded in Op operand */
public final class OP {
/** Invalid operand */
public static final int OP_NONE = 0;
/** Operand is register. */
public static final int OP_REG = 1;
/** Operand is memory. */
public static final int OP_MEM = 2;
/** Operand is immediate. */
public static final int OP_IMM = 3;
/** Operand is label. */
public static final int OP_LABEL = 4;
/** Operand is variable. */
public static final int OP_EXT = 5;
/** Operand is variable. */
public static final int OP_SHIFT = 6;
/** Operand is variable. */
public static final int OP_COND = 7;
/** Operand is variable. */
public static final int OP_PSTATEFIELD = 8;
/** Operand is variable. */
public static final int OP_SYSREG = 9;
/** Operand is variable. */
public static final int OP_VAR = 10;
/** Operand is prefetch operation. */
public static final int OP_PREFOP = 11;
/** Operand is */
public static final int OP_PREINDEX = 12;
/** Operand is */
public static final int OP_POSTINDEX = 13;
/** Operand is offset*/
public static final int OP_OFFSET = 14;
/** Operand is PRFop*/
public static final int OP_PRFOP = 15;
private OP() { }
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Offset.java 0000664 0000000 0000000 00000002125 13344175732 0023674 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import static jnr.a64asm.REG.*;
public final class Offset extends Operand {
private final Immediate offset;
private final Register basereg;
public Offset(Register base, Immediate offset) {
super(OP.OP_OFFSET, 0);
this.offset = offset;
this.basereg = base;
}
public final Immediate getOffset() {
return offset;
}
public final Register getRegister() {
return basereg;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Operand.java 0000664 0000000 0000000 00000005664 13344175732 0024051 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import static jnr.a64asm.OP.*;
public class Operand {
private final int op;
private final int size;
public Operand(int op, int size) {
this.op = op;
this.size = size;
}
/** Return type of operand, see @c OP. */
public int op() {
return op;
}
public int size() {
return size;
}
/** Return @c true if operand is none (@c OP_NONE). */
public boolean isNone() {
return op() == OP_NONE;
}
/** Return @c true if operand is any (general purpose, mmx or sse) register (@c OP_REG). */
public boolean isReg() {
return op() == OP_REG;
}
/** Return @c true if operand is memory address (@c OP_MEM). */
public boolean isMem() {
return op() == OP_MEM;
}
/** Return @c true if operand is immediate (@c OP_IMM). */
public boolean isImm() {
return op() == OP_IMM;
}
/** Return @c true if operand is label (@c OP_LABEL). */
public boolean isLabel() {
return op() == OP_LABEL;
}
/** Return @c true if operand is label (@c OP_LABEL). */
public boolean isExtend() {
return op() == OP_EXT;
}
public boolean isCond() {
return op() == OP_COND;
}
public boolean isPrefOp() {
return op() == OP_PREFOP;
}
public boolean isPreIndex() {
return op() == OP_PREINDEX;
}
public boolean isPostIndex() {
return op() == OP_POSTINDEX;
}
public boolean isOffset() {
return op() == OP_OFFSET;
}
public boolean isPrfop() {
return op() == OP_PRFOP;
}
/** Return @c true if operand is any register or memory. */
public final boolean isRegMem() {
return isMem() || isReg();
}
public final boolean isRegCode(int code) {
return this instanceof BaseReg && ((BaseReg) this).code() == code;
}
public final boolean isRegType(int type) {
return this instanceof BaseReg && ((BaseReg) this).type() == type;
}
public final boolean isRegIndex(int index) {
return this instanceof BaseReg && ((BaseReg) this).index() == index;
}
/** @brief Return @c true if operand is register of @a regType type or memory. */
public final boolean isRegMem(int regType) {
return isMem() || isRegType(regType);
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/OperandFlags.java 0000664 0000000 0000000 00000001567 13344175732 0025024 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public class OperandFlags {
public static final int // x86
O_G32 = 0x04,
O_G64 = 0x08,
O_MEM = 0x40,
O_IMM = 0x80,
O_G32_64 = O_G64 | O_G32;
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/PREF_ENUM.java 0000664 0000000 0000000 00000001602 13344175732 0024025 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public enum PREF_ENUM {
PLDL1KEEP, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
PSTL1KEEP, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
PLIL1KEEP, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM;
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/PRFOP_ENUM.java 0000664 0000000 0000000 00000003321 13344175732 0024157 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public final class PRFOP_ENUM extends Operand{
private final long value;
public static final int PLDL1KEEP = 0;
public static final int PLDL1STRM = 1;
public static final int PLDL2KEEP = 2;
public static final int PLDL2STRM = 3;
public static final int PLDL3KEEP = 4;
public static final int PLDL3STRM = 5;
//TBD,
//TBD1,
public static final int PLIL1KEEP = 8;
public static final int PLIL1STRM = 9;
public static final int PLIL2KEEP = 10;
public static final int PLIL2STRM = 11;
public static final int PLIL3KEEP = 12;
public static final int PLIL3STRM = 13;
//TBD2,
//TBD3,
public static final int PSTL1KEEP = 16;
public static final int PSTL1STRM = 17;
public static final int PSTL2KEEP = 18;
public static final int PSTL2STRM = 19;
public static final int PSTL3KEEP = 20;
public static final int PSTL3STRM = 21;
public PRFOP_ENUM( int value) {
super(OP.OP_PRFOP, 0);
this.value = value;
}
public final long intValue() {
return this.value;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Post_index.java 0000664 0000000 0000000 00000002163 13344175732 0024564 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
//import static jnr.a64asm.REG.*;
public final class Post_index extends Operand {
private final Immediate postIndex;
private final Register basereg;
public Post_index(Register base, Immediate postIndex) {
super(OP.OP_POSTINDEX, 0);
this.basereg = base;
this.postIndex = postIndex;
}
public final Immediate getPostIndex() {
return postIndex;
}
public final Register getRegister() {
return basereg;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Pre_index.java 0000664 0000000 0000000 00000002107 13344175732 0024363 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public final class Pre_index extends Operand {
private final Immediate preIndex;
private final Register basereg;
public Pre_index(Register base, Immediate preIndex) {
super(OP.OP_PREINDEX, 0);
this.basereg = base;
this.preIndex = preIndex;
}
public final Immediate getPreIndex() {
return preIndex;
}
public final Register getRegister() {
return basereg;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/PrefOp.java 0000664 0000000 0000000 00000001563 13344175732 0023646 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public class PrefOp extends Operand{
PREF_ENUM type;
PrefOp(long type, PREF_ENUM value){
super(OP.OP_PREFOP,0);
this.type = value;
}
public PREF_ENUM type() {
return type;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/REG.java 0000664 0000000 0000000 00000006346 13344175732 0023074 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public class REG {
private REG() {}
//! @brief Mask for register type.
public static final int REGTYPE_MASK = 0xF0,
//! @brief Mask for register code (index).
REGCODE_MASK = 0x0F,
//! @brief 64 bit general purpose register type.
REG_GPR = 0x00,
//! @brief 32 bit general purpose register type.
REG_GPT = 0x20,
REG_X0 = REG_GPR + 0, //argument and result registed from ro to r7
REG_X1 = REG_GPR + 1,
REG_X2 = REG_GPR + 2,
REG_X3 = REG_GPR + 3,
REG_X4 = REG_GPR + 4,
REG_X5 = REG_GPR + 5,
REG_X6 = REG_GPR + 6,
REG_X7 = REG_GPR + 7,
REG_X8 = REG_GPR + 8, //indirect result
REG_X9 = REG_GPR + 9, // x9 to x15 extra spare register
REG_X10 = REG_GPR + 10,
REG_X11 = REG_GPR + 11,
REG_X12 = REG_GPR + 12,
REG_X13 = REG_GPR + 13,
REG_X14 = REG_GPR + 14,
REG_X15 = REG_GPR + 15,
REG_X16 = REG_GPR + 16,// x16 to x17 intra call registers
REG_X17 = REG_GPR + 17,
REG_X18 = REG_GPR + 18,//platform specific (TLS) (instead of R9)
REG_X19 = REG_GPR + 19, //X19 to x28 callee saved register
REG_X20 = REG_GPR + 20,
REG_X21 = REG_GPR + 21,
REG_X22 = REG_GPR + 22,
REG_X23 = REG_GPR + 23,
REG_X24 = REG_GPR + 24,
REG_X25 = REG_GPR + 25,
REG_X26 = REG_GPR + 26,
REG_X27 = REG_GPR + 27,
REG_X28 = REG_GPR + 28,
REG_X29 = REG_GPR + 29, //frame pointer
REG_X30 = REG_GPR + 30, // link register
REG_X31 = REG_GPR + 31,
//! @brief 32 bit or 64 bit general purpose register type.
REG_W0 = REG_GPT + 0, //argument and result registed from ro to r7
REG_W1 = REG_GPT + 1,
REG_W2 = REG_GPT + 2,
REG_W3 = REG_GPT + 3,
REG_W4 = REG_GPT + 4,
REG_W5 = REG_GPT + 5,
REG_W6 = REG_GPT + 6,
REG_W7 = REG_GPT + 7,
REG_W8 = REG_GPT + 8, //indirect result
REG_W9 = REG_GPT + 9, // x9 to x15 extra spare register
REG_W10 = REG_GPT + 10,
REG_W11 = REG_GPT + 11,
REG_W12 = REG_GPT + 12,
REG_W13 = REG_GPT + 13,
REG_W14 = REG_GPT + 14,
REG_W15 = REG_GPT + 15,
REG_W16 = REG_GPT + 16,// x16 to x17 intra call registers
REG_W17 = REG_GPT + 17,
REG_W18 = REG_GPT + 18,//platform specific (TLS) (instead of R9)
REG_W19 = REG_GPT + 19, //X19 to x28 callee saved register
REG_W20 = REG_GPT + 20,
REG_W21 = REG_GPT + 21,
REG_W22 = REG_GPT + 22,
REG_W23 = REG_GPT + 23,
REG_W24 = REG_GPT + 24,
REG_W25 = REG_GPT + 25,
REG_W26 = REG_GPT + 26,
REG_W27 = REG_GPT + 27,
REG_W28 = REG_GPT + 28,
REG_W29 = REG_GPT + 29, //frame pointer
REG_W30 = REG_GPT + 30, // link register
NO_REG = 0xFF;
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/RELOC_MODE.java 0000664 0000000 0000000 00000001502 13344175732 0024114 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
/** Relocation info */
public enum RELOC_MODE {
/** No relocation. */
RELOC_NONE,
/** Overwrite relocation (immediates as constants). */
RELOC_OVERWRITE;
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Register.java 0000664 0000000 0000000 00000003614 13344175732 0024236 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import static jnr.a64asm.REG.*;
import static jnr.a64asm.SIZE.*;
import static jnr.a64asm.SYSREG_CODE.*;
public class Register extends BaseReg {
private static final Register[] gpb = new Register[32];
private static final Register[] gpw = new Register[32];
static {
for (int i = 0; i < 32; ++i) {
gpb[i] = new Register(REG_GPR | i, SIZE_DWORD);
gpw[i] = new Register(REG_GPT | i, SIZE_WORD);
}
}
Register(int code, int size) {
super(code, size);
}
public static final Register gpr(int reg) {
switch (reg & REGTYPE_MASK) {
case REG_GPR:
return gpb[reg & REGCODE_MASK];
case REG_GPT:
return gpw[reg & REGCODE_MASK];
}
throw new IllegalArgumentException("invalid register 0x" + Integer.toHexString(reg));
}
private static final Register gpr(Register[] cache, int idx) {
if (idx >= 0 && idx < 32) {
return cache[idx];
}
throw new IllegalArgumentException("invalid register index " + idx);
}
public static final Register gpb(int idx) {
return gpr(gpb, idx);
}
public static final Register gpw(int idx) {
return gpr(gpw, idx);
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/RelocData.java 0000664 0000000 0000000 00000002557 13344175732 0024315 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
/**
* Reloc to absolute address data
*/
class RelocData {
static enum Type {
ABSOLUTE_TO_ABSOLUTE,
RELATIVE_TO_ABSOLUTE,
ABSOLUTE_TO_RELATIVE,
ABSOLUTE_TO_RELATIVE_TRAMPOLINE;
};
/** Type of relocation. */
final Type type;
/** Size of relocation (4 or 8 bytes). */
final int size;
/** Offset from code begin address (in the emitted code data stream). */
final int offset;
/** Relative displacement or absolute address. */
final long destination;
public RelocData(Type type, int size, int offset, long destination) {
this.type = type;
this.size = size;
this.offset = offset;
this.destination = destination;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/SHIFT_ENUM.java 0000664 0000000 0000000 00000001557 13344175732 0024157 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public final class SHIFT_ENUM {
public static final int LSL = 0;
public static final int LSR = 1;
public static final int ASR = 2;
public static final int RESERVED = 3;
private SHIFT_ENUM() { }
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/SIZE.java 0000664 0000000 0000000 00000001614 13344175732 0023222 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
/** Size of registers and pointers */
public class SIZE {
public static final int SIZE_WORD = 32;
public static final int SIZE_DWORD = 64;
public static final int SIZE_QWORD = 128; //STNP, LDNP inst needs it
private SIZE() {}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/SYSREG_CODE.java 0000664 0000000 0000000 00000013604 13344175732 0024260 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public enum SYSREG_CODE {
SPSR_EL1,
ELR_EL1,
SP_EL0,
SPSEL,
DAIF,
CURRENTEL,
NZCV,
FPCR,
FPSR,
DSPSR_EL0,
DLR_EL0,
SPSR_EL2,
ELR_EL2,
SP_EL1,
SPSR_IRQ,
SPSR_ABT,
SPSR_UND,
SPSR_FIQ,
SPSR_EL3,
ELR_EL3,
SP_EL2,
SPSR_SVC,
SPSR_HYP,
MIDR_EL1,
CTR_EL0,
MPIDR_EL1,
REVIDR_EL1,
AIDR_EL1,
DCZID_EL0,
ID_DFR0_EL1,
ID_PFR0_EL1,
ID_PFR1_EL1,
ID_AFR0_EL1,
ID_MMFR0_EL1,
ID_MMFR1_EL1,
ID_MMFR2_EL1,
ID_MMFR3_EL1,
ID_ISAR0_EL1,
ID_ISAR1_EL1,
ID_ISAR2_EL1,
ID_ISAR3_EL1,
ID_ISAR4_EL1,
ID_ISAR5_EL1,
MVFR0_EL1,
MVFR1_EL1,
MVFR2_EL1,
CCSIDR_EL1,
ID_AA64PFR0_EL1,
ID_AA64PFR1_EL1,
ID_AA64DFR0_EL1,
ID_AA64DFR1_EL1,
ID_AA64ISAR0_EL1,
ID_AA64ISAR1_EL1,
ID_AA64MMFR0_EL1,
ID_AA64MMFR1_EL1,
ID_AA64AFR0_EL1,
ID_AA64AFR1_EL1,
CLIDR_EL1,
CSSELR_EL1,
VPIDR_EL2,
VMPIDR_EL2,
SCTLR_EL1,
SCTLR_EL2,
SCTLR_EL3,
ACTLR_EL1,
ACTLR_EL2,
ACTLR_EL3,
CPACR_EL1,
CPTR_EL2,
CPTR_EL3,
SCR_EL3,
HCR_EL2,
MDCR_EL2,
MDCR_EL3,
HSTR_EL2,
HACR_EL2,
TTBR0_EL1,
TTBR1_EL1,
TTBR0_EL2,
TTBR0_EL3,
VTTBR_EL2,
TCR_EL1,
TCR_EL2,
TCR_EL3,
VTCR_EL2,
AFSR0_EL1,
AFSR1_EL1,
AFSR0_EL2,
AFSR1_EL2,
AFSR0_EL3,
AFSR1_EL3,
ESR_EL1,
ESR_EL2,
ESR_EL3,
FPEXC32_EL2,
FAR_EL1,
FAR_EL2,
FAR_EL3,
HPFAR_EL2,
PAR_EL1,
MAIR_EL1,
MAIR_EL2,
MAIR_EL3,
AMAIR_EL1,
AMAIR_EL2,
AMAIR_EL3,
VBAR_EL1,
VBAR_EL2,
VBAR_EL3,
RVBAR_EL1,
RVBAR_EL2,
RVBAR_EL3,
RMR_EL1,
RMR_EL2,
RMR_EL3,
ISR_EL1,
CONTEXTIDR_EL1,
TPIDR_EL0,
TPIDRRO_EL0,
TPIDR_EL1,
TPIDR_EL2,
TPIDR_EL3,
TEECR32_EL1,
CNTFRQ_EL0,
CNTPCT_EL0,
CNTVCT_EL0,
CNTVOFF_EL2,
CNTKCTL_EL1,
CNTHCTL_EL2,
CNTP_TVAL_EL0,
CNTP_CTL_EL0,
CNTP_CVAL_EL0,
CNTV_TVAL_EL0,
CNTV_CTL_EL0,
CNTV_CVAL_EL0,
CNTHP_TVAL_EL2,
CNTHP_CTL_EL2,
CNTHP_CVAL_EL2,
CNTPS_TVAL_EL1,
CNTPS_CTL_EL1,
CNTPS_CVAL_EL1,
DACR32_EL2,
IFSR32_EL2,
TEEHBR32_EL1,
SDER32_EL3,
MDSCR_EL1,
MDCCSR_EL0,
MDCCINT_EL1,
DBGDTR_EL0,
DBGDTRRX_EL0,
DBGDTRTX_EL0,
OSDTRRX_EL1,
OSDTRTX_EL1,
OSECCR_EL1,
DBGVCR32_EL2,
DBGBVR0_EL1,
DBGBVR1_EL1,
DBGBVR2_EL1,
DBGBVR3_EL1,
DBGBVR4_EL1,
DBGBVR5_EL1,
DBGBVR6_EL1,
DBGBVR7_EL1,
DBGBVR8_EL1,
DBGBVR9_EL1,
DBGBVR10_EL1,
DBGBVR11_EL1,
DBGBVR12_EL1,
DBGBVR13_EL1,
DBGBVR14_EL1,
DBGBVR15_EL1,
DBGBCR0_EL1,
DBGBCR1_EL1,
DBGBCR2_EL1,
DBGBCR3_EL1,
DBGBCR4_EL1,
DBGBCR5_EL1,
DBGBCR6_EL1,
DBGBCR7_EL1,
DBGBCR8_EL1,
DBGBCR9_EL1,
DBGBCR10_EL1,
DBGBCR11_EL1,
DBGBCR12_EL1,
DBGBCR13_EL1,
DBGBCR14_EL1,
DBGBCR15_EL1,
DBGWVR0_EL1,
DBGWVR1_EL1,
DBGWVR2_EL1,
DBGWVR3_EL1,
DBGWVR4_EL1,
DBGWVR5_EL1,
DBGWVR6_EL1,
DBGWVR7_EL1,
DBGWVR8_EL1,
DBGWVR9_EL1,
DBGWVR10_EL1,
DBGWVR11_EL1,
DBGWVR12_EL1,
DBGWVR13_EL1,
DBGWVR14_EL1,
DBGWVR15_EL1,
DBGWCR0_EL1,
DBGWCR1_EL1,
DBGWCR2_EL1,
DBGWCR3_EL1,
DBGWCR4_EL1,
DBGWCR5_EL1,
DBGWCR6_EL1,
DBGWCR7_EL1,
DBGWCR8_EL1,
DBGWCR9_EL1,
DBGWCR10_EL1,
DBGWCR11_EL1,
DBGWCR12_EL1,
DBGWCR13_EL1,
DBGWCR14_EL1,
DBGWCR15_EL1,
MDRAR_EL1,
OSLAR_EL1,
OSLSR_EL1,
OSDLR_EL1,
DBGPRCR_EL1,
DBGCLAIMSET_EL1,
DBGCLAIMCLR_EL1,
DBGAUTHSTATUS_EL1,
PMCR_EL0,
PMCNTENSET_EL0,
PMCNTENCLR_EL0,
PMOVSCLR_EL0,
PMSWINC_EL0,
PMSELR_EL0,
PMCEID0_EL0,
PMCEID1_EL0,
PMCCNTR_EL0,
PMXEVTYPER_EL0,
PMXEVCNTR_EL0,
PMUSERENR_EL0,
PMINTENSET_EL1,
PMINTENCLR_EL1,
PMOVSSET_EL0,
PMEVCNTR0_EL0,
PMEVCNTR1_EL0,
PMEVCNTR2_EL0,
PMEVCNTR3_EL0,
PMEVCNTR4_EL0,
PMEVCNTR5_EL0,
PMEVCNTR6_EL0,
PMEVCNTR7_EL0,
PMEVCNTR8_EL0,
PMEVCNTR9_EL0,
PMEVCNTR10_EL0,
PMEVCNTR11_EL0,
PMEVCNTR12_EL0,
PMEVCNTR13_EL0,
PMEVCNTR14_EL0,
PMEVCNTR15_EL0,
PMEVCNTR16_EL0,
PMEVCNTR17_EL0,
PMEVCNTR18_EL0,
PMEVCNTR19_EL0,
PMEVCNTR20_EL0,
PMEVCNTR21_EL0,
PMEVCNTR22_EL0,
PMEVCNTR23_EL0,
PMEVCNTR24_EL0,
PMEVCNTR25_EL0,
PMEVCNTR26_EL0,
PMEVCNTR27_EL0,
PMEVCNTR28_EL0,
PMEVCNTR29_EL0,
PMEVCNTR30_EL0,
PMEVTYPER0_EL0,
PMEVTYPER1_EL0,
PMEVTYPER2_EL0,
PMEVTYPER3_EL0,
PMEVTYPER4_EL0,
PMEVTYPER5_EL0,
PMEVTYPER6_EL0,
PMEVTYPER7_EL0,
PMEVTYPER8_EL0,
PMEVTYPER9_EL0,
PMEVTYPER10_EL0,
PMEVTYPER11_EL0,
PMEVTYPER12_EL0,
PMEVTYPER13_EL0,
PMEVTYPER14_EL0,
PMEVTYPER15_EL0,
PMEVTYPER16_EL0,
PMEVTYPER17_EL0,
PMEVTYPER18_EL0,
PMEVTYPER19_EL0,
PMEVTYPER20_EL0,
PMEVTYPER21_EL0,
PMEVTYPER22_EL0,
PMEVTYPER23_EL0,
PMEVTYPER24_EL0,
PMEVTYPER25_EL0,
PMEVTYPER26_EL0,
PMEVTYPER27_EL0,
PMEVTYPER28_EL0,
PMEVTYPER29_EL0,
PMEVTYPER30_EL0,
PMCCFILTR_EL0,
SYSREG_MAX;
public static final SYSREG_CODE valueOf(int idx) {
return values()[idx];
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Serializer.java 0000664 0000000 0000000 00000002041 13344175732 0024554 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
/**
* Assembler instruction serializer.
*
* Serializer functionality is implemented in {@link SerializerCore} class
* and serializer intrinsics are implemented in {@link SerializerIntrinsics} class.
*
* Always use this class and never use {@link SerializerCore} or {@link SerializerIntrinsics}
* classes directly.
*/
public abstract class Serializer extends SerializerIntrinsics_a64 {
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/SerializerCore.java 0000664 0000000 0000000 00000007130 13344175732 0025371 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
//import static jnr.a64asm.INST_CODE.*;
/**
* Assembler intrinsics seralizer.
*
* SerializerCore is abstract class that is used by @c Assembler and @a Compiler.
* You probably never use this class directly, instead you use it to serialize
* intrinsics to @c Assembler or @c Compiler. @c SerializerIntrinsics implements
* all intruction intrinsics thats used and @c Serializer is public serializer
* class that should be used (instead of @c SerializerCore or @c SerializerInstrinsics).
*
* Note: Use always {@link Serializer} class, this class is only designed to
* decrease code size when exporting AsmJit library symbols. Some compilers
* (for example MSVC) are exporting inline symbols when class is declared
* to export them and {@link Serializer} class contains really huge count of
* symbols that will be never used (everything is inlined).
*/
public abstract class SerializerCore {
static final Operand _none = new Operand(OP.OP_NONE, 0) {};
//! @brief Emits a64/FPU or MM instruction.
//!
//! Operands @a o1, @a o2 or @a o3 can be @c NULL if they are not used.
//!
//! Hint: Use @c emitA64() helpers to emit instructions.
abstract void _emita64(INST_CODE code, Operand o1, Operand o2, Operand o3, Operand o4, Operand o5);
// Helpers to decrease binary code size. These four emit methods are just
// helpers thats used by serializer. They call _emita64() adding NULLs
// to first, second and third operand if needed.
//! @brief Emits instruction with no operand.
//!
//! Should be use as an alternative to @c _emita64() method.
void emitA64(INST_CODE code) {
_emita64(code, _none, _none, _none, _none, _none);
}
//! @brief Emits instruction with one operand.
//!
//! Should be use as an alternative to @c _emita64() method.
void emitA64(INST_CODE code, Operand o1) {
_emita64(code, o1, _none, _none, _none, _none);
}
//! @brief Emits instruction with two operands.
//!
//! Should be use as an alternative to @c _emita64() method.
void emitA64(INST_CODE code, Operand o1, Operand o2) {
_emita64(code, o1, o2, _none, _none, _none);
}
//! @brief Emits instruction with two operands.
//!
//! Should be use as an alternative to @c _emita64() method.
void emitA64(INST_CODE code, Operand o1, Operand o2, Operand o3) {
_emita64(code, o1, o2, o3, _none, _none);
}
//! @brief Emits instruction with two operands.
//!
//! Should be use as an alternative to @c _emita64() method.
void emitA64(INST_CODE code, Operand o1, Operand o2, Operand o3, Operand o4) {
_emita64(code, o1, o2, o3, o4, _none);
}
//! @brief Emits instruction with three operands.
//!
//! Should be use as an alternative to @c _emita64() method.
void emitA64(INST_CODE code, Operand o1, Operand o2, Operand o3, Operand o4, Operand o5) {
_emita64(code, o1, o2, o3, o4, o5);
}
abstract boolean is64();
};
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/SerializerIntrinsics_a64.java 0000664 0000000 0000000 00000076362 13344175732 0027315 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import static jnr.a64asm.INST_CODE.*;
import static jnr.a64asm.REG.*;
/**
* Assembler instruction serializer.
*/
public abstract class SerializerIntrinsics_a64 extends SerializerCore {
public final void adc(Register dst, Register Xn, Register Xm){
emitA64(INST_ADC_ADDSUB_CARRY, dst, Xn, Xm);
}
public final void adcs(Register Xd, Register Xn, Register Xm){
emitA64(INST_ADCS_ADDSUB_CARRY, Xd, Xn, Xm);
}
public final void add(Register Xd, Register Xn, Immediate val, Shift sft){
emitA64(INST_ADD_ADDSUB_IMM, Xd, Xn, val, sft);
}
public final void add(Register Xd, Register Xn, Register Xm, Shift sft){
emitA64(INST_ADD_ADDSUB_SHIFT, Xd, Xn, Xm, sft);
}
public final void add(Register Xd, Register Xn, Register Xm, Ext extnd){
emitA64(INST_ADD_EXT_ADDSUB_EXT, Xd, Xn, Xm, extnd);
}
public final void adds(Register Xd, Register Xn, Register Xm, Ext extnd){
emitA64(INST_ADDS_ADDSUB_EXT, Xd, Xn, Xm, extnd);
}
public final void adds(Register Xd, Register Xn, Immediate val, Shift sft){
emitA64(INST_ADDS_ADDSUB_IMM, Xd, Xn, val, sft);
}
public final void adds(Register Xd, Register Xn, Register Xm, Shift sft){
emitA64(INST_ADDS_ADDSUB_SHIFT, Xd, Xn, Xm, sft);
}
public final void adr(Register Xd, Label label){
emitA64(INST_ADR_PCRELADDR, Xd, label);
}
public final void adrp(Register Xd, Label label){
emitA64(INST_ADRP_PCRELADDR, Xd, label);
}
public final void and(Register Xd, Register Xn, Immediate val){
emitA64(INST_AND_LOG_IMM, Xd, Xn, val);
}
public final void and(Register Xd, Register Xn, Register Xm, Shift sft){
emitA64(INST_AND_LOG_SHIFT, Xd, Xn, Xm, sft);
}
public final void ands(Register Xd, Register Xn, Immediate val){
emitA64(INST_ANDS_LOG_IMM, Xd, Xn, val);
}
public final void ands(Register Xd, Register Xn, Register Xm, Shift sft){
emitA64(INST_ANDS_LOG_SHIFT, Xd, Xn, Xm, sft);
}
public final void asr(Register Xd, Register Xn, Immediate val){
emitA64(INST_ASR_BITFIELD, Xd, Xn, val);
}
public final void asr(Register Xd, Register Xn, Register Xm){
emitA64(INST_ASR_DP_2SRC, Xd, Xn, Xm);
}
public final void asrv(Register Xd, Register Xn, Register Xm){
emitA64(INST_ASRV_DP_2SRC, Xd, Xn, Xm);
}
public final void b(Immediate Xd){
emitA64(INST_B_BRANCH_IMM, Xd);
}
public final void bcc(Immediate Xd){
emitA64(INST_BCC_CONDBRANCH, Xd);
}
public final void bcs(Immediate Xd){
emitA64(INST_BCS_CONDBRANCH, Xd);
}
public final void beq(Immediate imm19){
emitA64(INST_BEQ_CONDBRANCH, imm19);
}
public final void bfi(Register Xd, Register Xn, Immediate val, Immediate width){
emitA64(INST_BFI_BITFIELD, Xd, Xn, val, width);
}
public final void bfm(Register Xd, Register Xn, Immediate val1, Immediate val2){
emitA64(INST_BFM_BITFIELD, Xd, Xn, val1, val2);
}
public final void bfxil(Register Xd, Register Xn, Immediate val, Immediate width){
emitA64(INST_BFXIL_BITFIELD, Xd, Xn, val, width);
}
public final void bge(Immediate label){
emitA64(INST_BGE_CONDBRANCH, label);
}
public final void bgt(Immediate label){
emitA64(INST_BGT_CONDBRANCH, label);
}
public final void bhi(Immediate label){
emitA64(INST_BHI_CONDBRANCH , label);
}
public final void bhs(Immediate label){
emitA64(INST_BHS_CONDBRANCH, label);
}
public final void bic(Register Xd, Register Xn, Register Xm, Shift sft){
emitA64(INST_BIC_LOG_SHIFT, Xd, Xn, Xm, sft);
}
public final void bics(Register Xd, Register Xn, Register Xm, Shift sft){
emitA64(INST_BICS_LOG_SHIFT, Xd, Xn, Xm, sft);
}
public final void bl(Immediate label){
emitA64(INST_BL_BRANCH_IMM, label);
}
public final void ble(Immediate label){
emitA64(INST_BLE_CONDBRANCH, label);
}
public final void blo(Immediate label){
emitA64(INST_BLO_CONDBRANCH, label);
}
public final void blr(Register Xn){
emitA64(INST_BLR_BRANCH_REG, Xn);
}
public final void bls(Immediate label){
emitA64(INST_BLS_CONDBRANCH, label);
}
public final void blt(Immediate label){
emitA64(INST_BLT_CONDBRANCH, label);
}
public final void bmi(Immediate label){
emitA64(INST_BMI_CONDBRANCH, label);
}
public final void bne(Immediate label){
emitA64(INST_BNE_CONDBRANCH, label);
}
public final void bpl(Immediate label){
emitA64(INST_BPL_CONDBRANCH, label);
}
public final void br(Register Xn){
emitA64(INST_BR_BRANCH_REG, Xn);
}
public final void brk(Immediate val){
emitA64(INST_BRK_EXCEPTION, val);
}
public final void bvc(Immediate label){
emitA64(INST_BVC_CONDBRANCH, label);
}
public final void bvs(Immediate label){
emitA64(INST_BVS_CONDBRANCH, label);
}
public final void cbnz(Register Xn, Label label){
emitA64(INST_CBNZ_COMPBRANCH, Xn, label);
}
public final void cbz(Register Xn, Label label){
emitA64(INST_CBZ_COMPBRANCH, Xn, label);
}
public final void ccmn(Register Xn, Immediate val, Immediate nzcv, Conditions cc){
emitA64(INST_CCMN_CONDCMP_IMM, Xn, val, nzcv, cc);
}
public final void ccmn(Register Xn, Register Xm, Immediate nzcv, Conditions cc){
emitA64(INST_CCMN_CONDCMP_REG, Xn, Xm, nzcv, cc);
}
public final void ccmp(Register Xn, Immediate val, Immediate nzcv, Conditions cc){
emitA64(INST_CCMP_CONDCMP_IMM, Xn, val, nzcv, cc);
}
public final void ccmp(Register Xn, Register Xm, Immediate nzcv, Conditions cc){
emitA64(INST_CCMP_CONDCMP_REG, Xn, Xm, nzcv, cc);
}
public final void cinc(Register Xd, Register Xn, Conditions cc){
emitA64(INST_CINC_CONDSEL, Xd, Xn, cc);
}
public final void cinv(Register Xd, Register Xn, Conditions cc){
emitA64(INST_CINV_CONDSEL, Xd, Xn, cc);
}
public final void clrex(Immediate val){
emitA64(INST_CLREX_IC_SYSTEM, val);
}
public final void cls(Register Xd, Register Xn){
emitA64(INST_CLS_DP_1SRC, Xd, Xn);
}
public final void clz(Register Xd, Register Xn){
emitA64(INST_CLZ_DP_1SRC, Xd, Xn);
}
public final void cmn(Register Xd, Register Xn, Ext extend){
emitA64(INST_CMN_ADDSUB_EXT, Xd, Xn, extend);
}
public final void cmn(Register Xd, Immediate val, Shift sft){
emitA64(INST_CMN_ADDSUB_IMM, Xd, val, sft);
}
public final void cmn(Register Xd, Register Xn, Shift sft){
emitA64(INST_CMN_ADDSUB_SHIFT, Xd, Xn, sft);
}
public final void cmp(Register Xd, Register Xn, Ext extend){
emitA64(INST_CMP_ADDSUB_EXT, Xd, Xn, extend);
}
public final void cmp(Register Xd, Immediate val, Shift sft){
emitA64(INST_CMP_ADDSUB_IMM, Xd, val, sft);
}
public final void cmp(Register Xd, Register Xn, Shift sft){
emitA64(INST_CMP_ADDSUB_SHIFT, Xd, Xn, sft);
}
public final void cneg(Register Xd, Register Xn, Conditions cc){
emitA64(INST_CNEG_CONDSEL, Xd, Xn, cc);
}
public final void csel(Register Xd, Register Xn, Register Xm, Conditions cc){
emitA64(INST_CSEL_CONDSEL, Xd, Xn, Xm, cc);
}
public final void cset(Register Xd, Conditions cc){
emitA64(INST_CSET_CONDSEL, Xd, cc);
}
public final void csetm(Register Xd, Conditions cc){
emitA64(INST_CSETM_CONDSEL, Xd, cc);
}
public final void csinc(Register Xd, Register Xn, Register Xm, Conditions cc){
emitA64(INST_CSINC_CONDSEL, Xd, Xn, Xm, cc);
}
public final void csinv(Register Xd, Register Xn, Register Xm, Conditions cc){
emitA64(INST_CSINV_CONDSEL, Xd, Xn, Xm, cc);
}
public final void csneg(Register Xd, Register Xn, Register Xm, Conditions cc){
emitA64(INST_CSNEG_CONDSEL, Xd, Xn, Xm, cc);
}
public final void dc(Register Xd, Register Xn){
emitA64(INST_DC_IC_SYSTEM, Xd, Xn);
}
public final void dcps1(Immediate val){
emitA64(INST_DCPS1_EXCEPTION, val);
}
public final void dcps2(Immediate val){
emitA64(INST_DCPS2_EXCEPTION, val);
}
public final void dcps3(Immediate val){
emitA64(INST_DCPS3_EXCEPTION, val);
}
public final void dmb(Immediate val){
emitA64(INST_DMB_IC_SYSTEM, val);
}
public final void drps(){
emitA64(INST_DRPS_BRANCH_REG);
}
public final void dsb(Immediate val){
emitA64(INST_DSB_IC_SYSTEM, val);
}
public final void eon(Register Xd, Register Xn, Register Xm, Shift sft){
emitA64(INST_EON_LOG_SHIFT, Xd, Xn, Xm, sft);
}
public final void eor(Register Xd, Register Xn, Immediate val){
emitA64(INST_EOR_LOG_IMM, Xd, Xn, val);
}
public final void eor(Register Xd, Register Xn, Register Xm, Shift sft){
emitA64(INST_EOR_LOG_SHIFT, Xd, Xn, Xm, sft);
}
public final void eret(){
emitA64(INST_ERET_BRANCH_REG);
}
public final void extr(Register Xd, Register Xn, Register Xm, Immediate val){
emitA64(INST_EXTR_EXTRACT, Xd, Xn, Xm, val);
}
public final void hint(Immediate val){
emitA64(INST_HINT_IC_SYSTEM, val);
}
public final void hlt(Immediate val){
emitA64(INST_HLT_EXCEPTION, val);
}
public final void hvc(Immediate val){
emitA64(INST_HVC_EXCEPTION, val);
}
public final void ic(Register Xd, Register Xn){
emitA64(INST_IC_IC_SYSTEM, Xd, Xn);
}
public final void isb(Immediate val){
emitA64(INST_ISB_IC_SYSTEM, val);
}
public final void ldar(Register Xd, Mem location){
emitA64(INST_LDAR_LDSTEXCL, Xd, location);
}
public final void ldarb(Register Xd, Mem location){
emitA64(INST_LDARB_LDSTEXCL, Xd, location);
}
public final void ldarh(Register Xd, Mem location){
emitA64(INST_LDARH_LDSTEXCL, Xd, location);
}
public final void ldaxp(Register Xd, Mem location){
emitA64(INST_LDAXP_LDSTEXCL, Xd, location);
}
public final void ldaxr(Register Xd, Mem location){
emitA64(INST_LDAXR_LDSTEXCL, Xd, location);
}
public final void ldaxrb(Register Xd, Mem location){
emitA64(INST_LDAXRB_LDSTEXCL, Xd, location);
}
public final void ldaxrh(Register Xd, Mem location){
emitA64(INST_LDAXRH_LDSTEXCL, Xd, location);
}
public final void ldnp(Register Xd, Register Xn, Register location, Immediate imm7){
emitA64(INST_LDNP_LDSTNAPAIR_OFFS, Xd, Xn, location, imm7);
}
public final void ldp(Register Xd, Register Xn, Post_index location){
emitA64(INST_LDP_POST_INDEXED_IDST_IMM9, Xd, Xn, location);
}
public final void ldp(Register Xd, Register Xn, Pre_index pindex){
emitA64(INST_LDP_PRE_INDEXED_IDST_IMM9, Xd, Xn, pindex);
}
public final void ldp(Register Xd, Register Xn, Offset offset){
emitA64(INST_LDP_LDSTPAIR_OFF_LDST_POS, Xd, Xn, offset);
}
public final void ldpsw(Register Xd, Register Xn, Mem location, Immediate val){
emitA64(INST_LDPSW_POST_INDEXED, Xd, Xn, location, val);
}
public final void ldpsw(Register Xd, Register Xn, Pre_index pindex){
emitA64(INST_LDPSW_PRE_INDEXED, Xd, Xn, pindex);
}
public final void ldpsw(Register Xd, Register Xn, Offset offset){
emitA64(INST_LDPSW_OFF, Xd, Xn, offset);
}
public final void ldr(Register Xd, Post_index postindex){
emitA64(INST_LDR_IMM_POST, Xd, postindex);
}
public final void ldr(Register Xd, Pre_index pindex){
emitA64(INST_LDR_IMM_PRE, Xd, pindex);
}
public final void ldr(Register Xd, Offset offset){
emitA64(INST_LDR_IMM_OFF, Xd, offset);
}
public final void ldr(Register Xd, Mem location){
emitA64(INST_LDR_REG, Xd, location);
}
public final void ldr(Register Xd, Immediate label){
emitA64(INST_LDR_LOADLIT, label);
}
public final void ldrb(Register Xd, Mem location, Immediate val){
emitA64(INST_LDRB_IMM_POST, Xd, location, val);
}
public final void ldrb(Register Xd, Pre_index pindex){
emitA64(INST_LDRB_IMM_PRE, Xd, pindex);
}
public final void ldrb(Register Xd, Offset offset){
emitA64(INST_LDRB_IMM_OFF, Xd, offset);
}
public final void ldrb(Register Xd, Mem location){
emitA64(INST_LDRB_REG, Xd, location);
}
public final void ldrh(Register Xd, Mem location, Immediate val){
emitA64(INST_LDRH_IMM_POST, Xd, location, val);
}
public final void ldrh(Register Xd, Pre_index pindex){
emitA64(INST_LDRH_IMM_PRE, Xd, pindex);
}
public final void ldrh(Register Xd, Offset offset){
emitA64(INST_LDRH_IMM_OFF, Xd, offset);
}
public final void ldrh(Register Xd, Mem location){
emitA64(INST_LDRH_REG, Xd, location);
}
public final void ldrsb(Register Xd, Mem location, Immediate val){
emitA64(INST_LDRSB_IMM_POST, Xd, location, val);
}
public final void ldrsb(Register Xd, Pre_index pindex){
emitA64(INST_LDRSB_IMM_PRE, Xd, pindex);
}
public final void ldrsb(Register Xd, Offset offset){
emitA64(INST_LDRSB_IMM_OFF, Xd, offset);
}
public final void ldrsb(Register Xd, Mem location){
emitA64(INST_LDRSB_REG, Xd, location);
}
public final void ldrsh(Register Xd, Mem location, Immediate val){
emitA64(INST_LDRSH_IMM_POST, Xd, location, val);
}
public final void ldrsh(Register Xd, Pre_index pindex){
emitA64(INST_LDRSH_IMM_PRE, Xd, pindex);
}
public final void ldrsh(Register Xd, Offset offset){
emitA64(INST_LDRSH_IMM_OFF, Xd, offset);
}
public final void ldrsh(Register Xd, Mem location){
emitA64(INST_LDRSH_REG, Xd, location);
}
public final void ldrsw(Register Xd, Mem location, Immediate val){
emitA64(INST_LDRSW_IMM_POST, Xd, location, val);
}
public final void ldrsw(Register Xd, Pre_index pindex){
emitA64(INST_LDRSW_IMM_PRE, Xd, pindex);
}
public final void ldrsw(Register Xd, Offset offset){
emitA64(INST_LDRSW_IMM_OFF, Xd, offset);
}
public final void ldrsw(Register Xd, Mem location){
emitA64(INST_LDRSW_REG, Xd, location);
}
public final void ldrsw(Register Xd, Label label){
emitA64(INST_LDRSW_LOADLIT, label);
}
public final void ldtr(Register Xd, Mem location){
emitA64(INST_LDTR_LDST_UNPRIV, Xd, location);
}
public final void ldtrb(Register Xd, Mem location){
emitA64(INST_LDTRB_LDST_UNPRIV, Xd, location);
}
public final void ldtrh(Register Xd, Mem location){
emitA64(INST_LDTRH_LDST_UNPRIV, Xd, location);
}
public final void ldtrsb(Register Xd, Mem location){
emitA64(INST_LDTRSB_LDST_UNPRIV, Xd, location);
}
public final void ldtrsh(Register Xd, Mem location){
emitA64(INST_LDTRSH_LDST_UNPRIV, Xd, location);
}
public final void ldtrsw(Register Xd, Mem location){
emitA64(INST_LDTRSW_LDST_UNPRIV, Xd, location);
}
public final void ldur(Register Xd, Mem location){
emitA64(INST_LDUR_LDST_UNSCALED_X, Xd, location);
}
public final void ldurb(Register Xd, Mem location){
emitA64(INST_LDURB_LDST_UNSCALED, Xd, location);
}
public final void ldurh(Register Xd, Mem location){
emitA64(INST_LDURH_LDST_UNSCALED, Xd, location);
}
public final void ldursb(Register Xd, Mem location){
emitA64(INST_LDURSB_LDST_UNSCALED, Xd, location);
}
public final void ldursh(Register Xd, Mem location){
emitA64(INST_LDURSH_LDST_UNSCALED, Xd, location);
}
public final void ldursw(Register Xd, Mem location){
emitA64(INST_LDURSW_LDST_UNSCALED, Xd, location);
}
public final void ldxp(Register Xd, Mem location){
emitA64(INST_LDXP_LDSTEXCL, Xd, location);
}
public final void ldxr(Register Xd, Mem location){
emitA64(INST_LDXR_LDSTEXCL, Xd, location);
}
public final void ldxrb(Register Xd, Mem location){
emitA64(INST_LDXRB_LDSTEXCL, Xd, location);
}
public final void ldxrh(Register Xd, Mem location){
emitA64(INST_LDXRH_LDSTEXCL, Xd, location);
}
public final void lsl(Register Xd, Register Xn, Immediate val){
emitA64(INST_LSL_BITFIELD, Xd, Xn, val);
}
public final void lsl(Register Xd, Register Xn, Register Xm){
emitA64(INST_LSL_DP_2SRC, Xd, Xn, Xm);
}
public final void lslv(Register Xd, Register Xn, Register Xm){
emitA64(INST_LSLV_DP_2SRC, Xd, Xn, Xm);
}
public final void lsr(Register Xd, Register Xn, Immediate val){
emitA64(INST_LSR_BITFIELD, Xd, Xn, val);
}
public final void lsr(Register Xd, Register Xn, Register Xm){
emitA64(INST_LSR_DP_2SRC, Xd, Xn, Xm);
}
public final void lsrv(Register Xd, Register Xn, Register Xm){
emitA64(INST_LSRV_DP_2SRC, Xd, Xn, Xm);
}
public final void madd(Register Xd, Register Xn, Register Xm, Register Xa){
emitA64(INST_MADD_DP_3SRC, Xd, Xn, Xm, Xa);
}
public final void mneg(Register Xd, Register Xn, Register Xm){
emitA64(INST_MNEG_DP_3SRC, Xd, Xn, Xm);
}
public final void mov(Register Xd, Register Xn){
if(Xd.code() < 31 && Xn.code() < 31)
emitA64(INST_MOV_ADDSUB_IMM, Xd, Xn);
else
emitA64(INST_MOV_LOG_SHIFT, Xd, Xn);
}
public final void mov(Register Xd, Shift sft){
emitA64(INST_MOV_LOG_SHIFT, Xd, sft);
}
public final void mov(Register Xd, Immediate val){
if(Xd.code() < 31 )
emitA64(INST_MOV_MOVEWIDE_X, Xd, val);
else
emitA64(INST_MOV_LOG_IMM, Xd, val);
}
public final void movk(Register Xd, Immediate val, Shift sft){
emitA64(INST_MOVK_MOVEWIDE, Xd, val, sft);
}
public final void movn(Register Xd, Immediate val, Shift sft){
emitA64(INST_MOVN_MOVEWIDE, Xd, val, sft);
}
public final void movz(Register Xd, Immediate val, Shift sft){
emitA64(INST_MOVZ_MOVEWIDE, Xd, val, sft);
}
public final void mrs(Register Xd, Register SysReg){
emitA64(INST_MRS_IC_SYSTEM, Xd, SysReg);
}
public final void msr(Register Xd, Immediate val){
emitA64(INST_MSR_IC_SYSTEM, Xd, val);
}
public final void msr(SysRegister srt, Register Xd){
emitA64(INST_MSR_IC_SYSTEM_X, srt, Xd);
}
public final void msub(Register Xd, Register Xn, Register Xm, Register Xa){
emitA64(INST_MSUB_DP_3SRC, Xd, Xn, Xm, Xa);
}
public final void mul(Register Xd, Register Xn, Register Xm){
emitA64(INST_MUL_DP_3SRC, Xd, Xn, Xm);
}
public final void mvn(Register Xd, Register Xn, Shift sft){
emitA64(INST_MVN_LOG_SHIFT, Xd, Xn, sft);
}
public final void neg(Register Xd, Register Xn, Shift sft){
emitA64(INST_NEG_ADDSUB_SHIFT, Xd, Xn, sft);
}
public final void negs(Register Xd, Register Xn, Shift sft){
emitA64(INST_NEGS_ADDSUB_SHIFT, Xd, Xn, sft);
}
public final void ngc(Register Xd, Register Xn){
emitA64(INST_NGC_ADDSUB_CARRY, Xd, Xn);
}
public final void ngcs(Register Xd, Register Xn){
emitA64(INST_NGCS_ADDSUB_CARRY, Xd, Xn);
}
public final void nop(){
emitA64(INST_NOP_IC_SYSTEM);
}
public final void orn(Register Xd, Register Xn, Register Xm, Shift sft){
emitA64(INST_ORN_LOG_SHIFT, Xd, Xn, Xm, sft);
}
public final void orr(Register Xd, Register Xm, Immediate val){
emitA64(INST_ORR_LOG_IMM, Xd, Xm, val);
}
public final void orr(Register Xd, Register Xn, Register Xm, Shift sft){
emitA64(INST_ORR_LOG_SHIFT, Xd, Xn, Xm, sft);
}
public final void prfm(PRFOP_ENUM Xd, Register Xn, Immediate imm12 ){
emitA64(INST_PRFM_LDST_POS__IMMEDIATE, Xd, Xn, imm12 );
}
public final void prfm(PRFOP_ENUM Xd, Immediate imm19){
emitA64(INST_PRFM_LOADLIT__LITERAL, Xd, imm19);
}
public final void prfm(PRFOP_ENUM label, Register Xn, Register Rm, Ext ext){
emitA64(INST_PRFM_LDST_REGOFF__REGISTER, label, Xn, Rm, ext);
}
public final void prfum(PRFOP_ENUM Xd, Register Xn, Immediate imm9 ){
emitA64(INST_PRFUM_LDST_UNSCALED, Xd, Xn, imm9);
}
public final void rbit(Register Xd, Register Xn){
emitA64(INST_RBIT_DP_1SRC, Xd, Xn);
}
public final void ret(Register Xd){
emitA64(INST_RET_BRANCH_REG, Xd);
}
public final void rev(Register Xd, Register Xn){
emitA64(INST_REV_DP_1SRC_X, Xd, Xn);
}
public final void rev16(Register Xd, Register Xn){
emitA64(INST_REV16_DP_1SRC, Xd, Xn);
}
public final void rev32(Register Xd, Register Xn){
emitA64(INST_REV32_DP_1SRC, Xd, Xn);
}
public final void ror(Register Xd, Register Xn, Register Xm){
emitA64(INST_ROR_DP_2SRC, Xd, Xn, Xm);
}
public final void ror(Register Xd, Register Xm, Immediate val){
emitA64(INST_ROR_EXTRACT, Xd, Xm, val);
}
public final void rorv(Register Xd, Register Xn, Register Xm){
emitA64(INST_RORV_DP_2SRC, Xd, Xn, Xm);
}
public final void sbc(Register Xd, Register Xn, Register Xm){
emitA64(INST_SBC_ADDSUB_CARRY, Xd, Xn, Xm);
}
public final void sbcs(Register Xd, Register Xn, Register Xm){
emitA64(INST_SBCS_ADDSUB_CARRY, Xd, Xn, Xm);
}
public final void sbfiz(Register Xd, Register Xn, Immediate lsb, Immediate width){
emitA64(INST_SBFIZ_BITFIELD, Xd, Xn, lsb, width);
}
public final void sbfm(Register Xd, Register Xn, Immediate val, Immediate val1){
emitA64(INST_SBFM_BITFIELD, Xd, Xn, val,val1);
}
public final void sbfx(Register Xd, Register Xn, Immediate val, Immediate val1){
emitA64(INST_SBFX_BITFIELD, Xd, Xn, val, val1);
}
public final void sdiv(Register Xd, Register Xn, Register Xm){
emitA64(INST_SDIV_DP_2SRC, Xd, Xn, Xm);
}
public final void sev(){
emitA64(INST_SEV_IC_SYSTEM);
}
public final void sevl(){
emitA64(INST_SEVL_IC_SYSTEM);
}
public final void smaddl(Register Xd, Register Wn, Register Wm, Register Xn){
emitA64(INST_SMADDL_DP_3SRC, Xd, Wn, Wm, Xn);
}
public final void smc(Immediate val){
emitA64(INST_SMC_EXCEPTION, val);
}
public final void smnegl(Register Xd, Register Wn, Register Wm){
emitA64(INST_SMNEGL_DP_3SRC, Xd, Wn, Wm);
}
public final void smsubl(Register Xd, Register Wn, Register Wm, Register Xn){
emitA64(INST_SMSUBL_DP_3SRC, Xd, Wn, Wm, Xn);
}
public final void smulh(Register Xd, Register Xn, Register Xm){
emitA64(INST_SMULH_DP_3SRC, Xd, Xn, Xm);
}
public final void smull(Register Xd, Register Wn, Register Wm){
emitA64(INST_SMULL_DP_3SRC, Xd, Wn, Wm);
}
public final void stlr(Register Xd, Mem location){
emitA64(INST_STLR_LDSTEXCL, Xd, location);
}
public final void stlrb(Register Xd, Register Xn, Immediate val){
emitA64(INST_STLRB_LDSTEXCL, Xd, Xn, val);
}
public final void stlrh(Register Xd, Mem location){
emitA64(INST_STLRH_LDSTEXCL, Xd, location);
}
public final void stlxp(Register Wd, Register Xn, Register Xm, Mem location){
emitA64(INST_STLXP_LDSTEXCL, Wd, Xn, Xm, location);
}
public final void stlxr(Register Wd, Register Xn, Mem location){
emitA64(INST_STLXR_LDSTEXCL, Wd, Xn, location);
}
public final void stlxrb(Register Wd, Register Wn, Mem location){
emitA64(INST_STLXRB_LDSTEXCL, Wd, Wn, location);
}
public final void stlxrh(Register Wd, Register Wn, Mem location){
emitA64(INST_STLXRH_LDSTEXCL, Wd, Wn, location);
}
public final void stnp(Register Xd, Register Xn, Mem location){
emitA64(INST_STNP_LDSTNAPAIR_OFFS, Xd, Xn, location);
}
public final void stp(Register Xd, Register Xn, Post_index location){
emitA64(INST_STP_LDSTPAIR_INDEXED_POST, Xd, Xn, location);
}
public final void stp(Register Xd, Register Xn, Pre_index pindex){
emitA64(INST_STP_LDSTPAIR_INDEXED_PRE, Xd, Xn, pindex);
}
public final void stp(Register Xd, Register Xn, Offset offset){
emitA64(INST_STP_LDSTPAIR_OFF, Xd, Xn, offset);
}
public final void str(Register Xd, Post_index postindex){
emitA64(INST_STR_LDST_IMM9_POST, Xd, postindex);
}
public final void str(Register Xd, Pre_index pindex){
emitA64(INST_STR_LDST_IMM9_PRE, Xd, pindex);
}
public final void str(Register Xd, Offset offset){
emitA64(INST_STR_LDST_POS, Xd, offset);
}
public final void str(Register Xt, Register Xn, Register Xm, Ext ext){
emitA64(INST_STR_LDST_REGOFF, Xt, Xn, Xm, ext);
}
public final void strb(Register Xd, Post_index pindex){
emitA64(INST_STRB_LDST_IMM9_POST, Xd, pindex);
}
public final void strb(Register Xd, Pre_index pindex){
emitA64(INST_STRB_LDST_PRE, Xd, pindex);
}
public final void strb(Register Xd, Offset offset){
emitA64(INST_STRB_LDST_OFFSET, Xd, offset);
}
public final void strb(Register Wt, Register Xn, Register Rm, Ext ext){
emitA64(INST_STRB_LDST_REGOFF, Wt, Xn, Rm, ext);
}
public final void strh(Register Xd, Post_index pindex){
emitA64(INST_STRH_LDST_IMM_POST, Xd, pindex);
}
public final void strh(Register Xd, Pre_index pindex){
emitA64(INST_STRH_LDST_IMM_PRE, Xd, pindex);
}
public final void strh(Register Xd, Offset offset){
emitA64(INST_STRH_LDST_IMM_OFF, Xd, offset);
}
public final void strh(Register Xd, Register Xn, Register Xm, Ext ext){
emitA64(INST_STRH_LDST_REGOFF, Xd, Xn, Xm, ext);
}
public final void sttr(Register Xd, Offset offset){
emitA64(INST_STTR_LDST_UNPRIV, Xd, offset);
}
public final void sttrb(Register Xd, Offset offset){
emitA64(INST_STTRB_LDST_UNPRIV, Xd, offset);
}
public final void sttrh(Register Xd, Offset offset){
emitA64(INST_STTRH_LDST_UNPRIV, Xd, offset);
}
public final void stur(Register Xd, Offset offset){
emitA64(INST_STUR_LDST_UNSCALED_X, Xd, offset);
}
public final void sturb(Register Xd, Offset offset){
emitA64(INST_STURB_LDST_UNSCALED, Xd, offset);
}
public final void sturh(Register Xd, Offset offset){
emitA64(INST_STURH_LDST_UNSCALED, Xd, offset);
}
public final void stxp(Register Xd, Register Xn, Register Xm, Register location, Immediate zero){
emitA64(INST_STXP_LDSTEXCL, Xd, Xn, Xm, location, zero);
}
public final void stxr(Register Xd, Register Xn, Offset location){
emitA64(INST_STXR_LDSTEXCL, Xd, Xn, location);
}
public final void stxrb(Register Xd, Register Xn, Offset location){
emitA64(INST_STXRB_LDSTEXCL, Xd, Xn, location);
}
public final void stxrh(Register Xd, Register Xn, Offset location){
emitA64(INST_STXRH_LDSTEXCL, Xd, Xn, location);
}
public final void sub(Register Xd, Register Xn, Register Xm, Ext extend){
emitA64(INST_SUB_ADDSUB_EXT, Xd, Xn, Xm, extend);
}
public final void sub(Register Xd, Register Xn, Immediate val, Shift sft){
emitA64(INST_SUB_ADDSUB_IMM, Xd, Xn, val, sft);
}
public final void sub(Register Xd, Register Xn, Register Xm, Shift sft){
emitA64(INST_SUB_ADDSUB_SHIFT, Xd, Xn, Xm, sft);
}
public final void subs(Register Xd, Register Xn, Register Xm, Ext extend){
emitA64(INST_SUBS_ADDSUB_EXT, Xd, Xn, Xm, extend);
}
public final void subs(Register Xd, Register Xn, Immediate val, Shift sft){
emitA64(INST_SUBS_ADDSUB_IMM, Xd, Xn, val, sft);
}
public final void subs(Register Xd, Register Xn, Register Xm, Shift sft){
emitA64(INST_SUBS_ADDSUB_SHIFT, Xd, Xn, Xm, sft);
}
public final void svc(Immediate val){
emitA64(INST_SVC_EXCEPTION, val);
}
public final void sxtb(Register Xd, Register Xn){
emitA64(INST_SXTB_BITFIELD, Xd, Xn);
}
public final void sxth(Register Xd, Register Xn){
emitA64(INST_SXTH_BITFIELD, Xd, Xn);
}
public final void sxtw(Register Xd, Register Xn){
emitA64(INST_SXTW_BITFIELD, Xd, Xn);
}
public final void tbnz(Register Xd, Immediate val, Label label){
emitA64(INST_TBNZ_TESTBRANCH, Xd, val, label);
}
public final void tbz(Register Xd, Immediate val, Label label){
emitA64(INST_TBZ_TESTBRANCH, Xd, val, label);
}
public final void tst(Register Xd, Immediate val){
emitA64(INST_TST_LOG_IMM, Xd, val);
}
public final void tst(Register Xd, Register Xn, Shift sft){
emitA64(INST_TST_LOG_SHIFT, Xd, Xn, sft);
}
public final void ubfiz(Register Xd, Register Xn, Immediate val, Immediate val1){
emitA64(INST_UBFIZ_BITFIELD, Xd, Xn, val, val1);
}
public final void ubfm(Register Xd, Register Xn, Immediate val, Immediate val1){
emitA64(INST_UBFM_BITFIELD, Xd, Xn, val, val1);
}
public final void ubfx(Register Xd, Register Xn, Immediate val, Immediate val1){
emitA64(INST_UBFX_BITFIELD, Xd, Xn, val, val1);
}
public final void udiv(Register Xd, Register Xn, Register Xm){
emitA64(INST_UDIV_DP_2SRC, Xd, Xn, Xm);
}
public final void umaddl(Register Xd, Register Xn, Register Xm, Register Xa){
emitA64(INST_UMADDL_DP_3SRC, Xd, Xn, Xm, Xa);
}
public final void umnegl(Register Xd, Register Xn, Register Xm){
emitA64(INST_UMNEGL_DP_3SRC, Xd, Xn, Xm);
}
public final void umsubl(Register Xd, Register Xn, Register Xm, Register Xa){
emitA64(INST_UMSUBL_DP_3SRC, Xd, Xn, Xm, Xa);
}
public final void umulh(Register Xd, Register Xn, Register Xm){
emitA64(INST_UMULH_DP_3SRC, Xd, Xn, Xm);
}
public final void umull(Register Xd, Register Xn, Register Xm){
emitA64(INST_UMULL_DP_3SRC, Xd, Xn, Xm);
}
public final void uxtb(Register Xd, Register Xn){
emitA64(INST_UXTB_BITFIELD, Xd, Xn);
}
public final void uxth(Register Xd, Register Xn){
emitA64(INST_UXTH_BITFIELD, Xd, Xn);
}
public final void uxtw(Register Xd, Register Xn){
emitA64(INST_UXTW_LOG_SHIFT, Xd, Xn);
}
public final void wfe(){
emitA64(INST_WFE_IC_SYSTEM);
}
public final void wfi(){
emitA64(INST_WFI_IC_SYSTEM);
}
public final void yield(){
emitA64(INST_YIELD_IC_SYSTEM);
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Shift.java 0000664 0000000 0000000 00000002015 13344175732 0023521 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public final class Shift extends Operand {
private final int value;
private final int type; /* type will be of SHIFT.java */
public Shift(int type, int value) {
super(OP.OP_SHIFT, 0);
this.value = value;
this.type = type;
}
public long value() {
return value;
}
public long type() {
return type;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/SysRegDescription.java 0000664 0000000 0000000 00000044315 13344175732 0026075 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import java.util.EnumMap;
import java.util.Map;
import static jnr.a64asm.SYSREG_CODE.*;
public final class SysRegDescription {
final SYSREG_CODE code;
final int reg_code;
private static final Map sysRegtable
= new EnumMap(SYSREG_CODE.class);
SysRegDescription(SYSREG_CODE code, int op0, int op1, int crn, int crm, int op2) {
this.code = code;
this.reg_code =((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5) ;
}
private static final SysRegDescription MAKE_SYSREGCODE(SYSREG_CODE code, int op0, int op1, int crn, int crm, int op2) {
SysRegDescription id = new SysRegDescription(code, op0, op1, crn, crm, op2);
sysRegtable.put(code, id);
return id;
}
/* for 3.9.3 Instructions for Accessing Special Purpose Registers */
private static final SysRegDescription MAKE_SYSREGCODE(SYSREG_CODE code, int op1, int crm, int op2) {
SysRegDescription id = new SysRegDescription(code,3,(op1),4,(crm),(op2));
sysRegtable.put(code, id);
return id;
}
public static final SysRegDescription find(SYSREG_CODE code) {
SysRegDescription id = sysRegtable.get(code);
if (id == null) {
throw new IllegalArgumentException("no description for " + code);
}
return id;
}
private static final SysRegDescription[] SYSREG_tb = {
// Instruction code (enum) | instruction name | group | operator 1 flags| operator 2 flags| r| opCode1 | opcode2
MAKE_SYSREGCODE(SPSR_EL1, 0,0,0),
MAKE_SYSREGCODE(ELR_EL1, 0,0,1),
MAKE_SYSREGCODE(SP_EL0, 0,1,0),
MAKE_SYSREGCODE(SPSEL, 0,2,0),
MAKE_SYSREGCODE(DAIF, 3,2,1),
MAKE_SYSREGCODE(CURRENTEL, 0,2,2),
MAKE_SYSREGCODE(NZCV, 3,2,0),
MAKE_SYSREGCODE(FPCR, 3,4,0),
MAKE_SYSREGCODE(FPSR, 3,4,1),
MAKE_SYSREGCODE(DSPSR_EL0, 3,5,0),
MAKE_SYSREGCODE(DLR_EL0, 3,5,1),
MAKE_SYSREGCODE(SPSR_EL2, 4,0,0),
MAKE_SYSREGCODE(ELR_EL2, 4,0,1),
MAKE_SYSREGCODE(SP_EL1, 4,1,0),
MAKE_SYSREGCODE(SPSR_IRQ, 4,3,0),
MAKE_SYSREGCODE(SPSR_ABT, 4,3,1),
MAKE_SYSREGCODE(SPSR_UND, 4,3,2),
MAKE_SYSREGCODE(SPSR_FIQ, 4,3,3),
MAKE_SYSREGCODE(SPSR_EL3, 6,0,0),
MAKE_SYSREGCODE(ELR_EL3, 6,0,1),
MAKE_SYSREGCODE(SP_EL2, 6,1,0),
MAKE_SYSREGCODE(SPSR_SVC, 0,0,0),
MAKE_SYSREGCODE(SPSR_HYP, 4,0,0),
MAKE_SYSREGCODE(MIDR_EL1, 3,0,0,0,0),
MAKE_SYSREGCODE(CTR_EL0, 3,3,0,0,1),
MAKE_SYSREGCODE(MPIDR_EL1, 3,0,0,0,5),
MAKE_SYSREGCODE(REVIDR_EL1, 3,0,0,0,6),
MAKE_SYSREGCODE(AIDR_EL1, 3,1,0,0,7),
MAKE_SYSREGCODE(DCZID_EL0, 3,3,0,0,7),
MAKE_SYSREGCODE(ID_DFR0_EL1, 3,0,0,1,2),
MAKE_SYSREGCODE(ID_PFR0_EL1, 3,0,0,1,0),
MAKE_SYSREGCODE(ID_PFR1_EL1, 3,0,0,1,1),
MAKE_SYSREGCODE(ID_AFR0_EL1, 3,0,0,1,3),
MAKE_SYSREGCODE(ID_MMFR0_EL1, 3,0,0,1,4),
MAKE_SYSREGCODE(ID_MMFR1_EL1, 3,0,0,1,5),
MAKE_SYSREGCODE(ID_MMFR2_EL1, 3,0,0,1,6),
MAKE_SYSREGCODE(ID_MMFR3_EL1, 3,0,0,1,7),
MAKE_SYSREGCODE(ID_ISAR0_EL1, 3,0,0,2,0),
MAKE_SYSREGCODE(ID_ISAR1_EL1, 3,0,0,2,1),
MAKE_SYSREGCODE(ID_ISAR2_EL1, 3,0,0,2,2),
MAKE_SYSREGCODE(ID_ISAR3_EL1, 3,0,0,2,3),
MAKE_SYSREGCODE(ID_ISAR4_EL1, 3,0,0,2,4),
MAKE_SYSREGCODE(ID_ISAR5_EL1, 3,0,0,2,5),
MAKE_SYSREGCODE(MVFR0_EL1, 3,0,0,3,0),
MAKE_SYSREGCODE(MVFR1_EL1, 3,0,0,3,1),
MAKE_SYSREGCODE(MVFR2_EL1, 3,0,0,3,2),
MAKE_SYSREGCODE(CCSIDR_EL1, 3,1,0,0,0),
MAKE_SYSREGCODE(ID_AA64PFR0_EL1, 3,0,0,4,0),
MAKE_SYSREGCODE(ID_AA64PFR1_EL1, 3,0,0,4,1),
MAKE_SYSREGCODE(ID_AA64DFR0_EL1, 3,0,0,5,0),
MAKE_SYSREGCODE(ID_AA64DFR1_EL1, 3,0,0,5,1),
MAKE_SYSREGCODE(ID_AA64ISAR0_EL1,3,0,0,6,0),
MAKE_SYSREGCODE(ID_AA64ISAR1_EL1,3,0,0,6,1),
MAKE_SYSREGCODE(ID_AA64MMFR0_EL1,3,0,0,7,0),
MAKE_SYSREGCODE(ID_AA64MMFR1_EL1,3,0,0,7,1),
MAKE_SYSREGCODE(ID_AA64AFR0_EL1, 3,0,0,5,4),
MAKE_SYSREGCODE(ID_AA64AFR1_EL1, 3,0,0,5,5),
MAKE_SYSREGCODE(CLIDR_EL1, 3,1,0,0,1),
MAKE_SYSREGCODE(CSSELR_EL1, 3,2,0,0,0),
MAKE_SYSREGCODE(VPIDR_EL2, 3,4,0,0,0),
MAKE_SYSREGCODE(VMPIDR_EL2, 3,4,0,0,5),
MAKE_SYSREGCODE(SCTLR_EL1, 3,0,1,0,0),
MAKE_SYSREGCODE(SCTLR_EL2, 3,4,1,0,0),
MAKE_SYSREGCODE(SCTLR_EL3, 3,6,1,0,0),
MAKE_SYSREGCODE(ACTLR_EL1, 3,0,1,0,1),
MAKE_SYSREGCODE(ACTLR_EL2, 3,4,1,0,1),
MAKE_SYSREGCODE(ACTLR_EL3, 3,6,1,0,1),
MAKE_SYSREGCODE(CPACR_EL1, 3,0,1,0,2),
MAKE_SYSREGCODE(CPTR_EL2, 3,4,1,1,2),
MAKE_SYSREGCODE(CPTR_EL3, 3,6,1,1,2),
MAKE_SYSREGCODE(SCR_EL3, 3,6,1,1,0),
MAKE_SYSREGCODE(HCR_EL2, 3,4,1,1,0),
MAKE_SYSREGCODE(MDCR_EL2, 3,4,1,1,1),
MAKE_SYSREGCODE(MDCR_EL3, 3,6,1,3,1),
MAKE_SYSREGCODE(HSTR_EL2, 3,4,1,1,3),
MAKE_SYSREGCODE(HACR_EL2, 3,4,1,1,7),
MAKE_SYSREGCODE(TTBR0_EL1, 3,0,2,0,0),
MAKE_SYSREGCODE(TTBR1_EL1, 3,0,2,0,1),
MAKE_SYSREGCODE(TTBR0_EL2, 3,4,2,0,0),
MAKE_SYSREGCODE(TTBR0_EL3, 3,6,2,0,0),
MAKE_SYSREGCODE(VTTBR_EL2, 3,4,2,1,0),
MAKE_SYSREGCODE(TCR_EL1, 3,0,2,0,2),
MAKE_SYSREGCODE(TCR_EL2, 3,4,2,0,2),
MAKE_SYSREGCODE(TCR_EL3, 3,6,2,0,2),
MAKE_SYSREGCODE(VTCR_EL2, 3,4,2,1,2),
MAKE_SYSREGCODE(AFSR0_EL1, 3,0,5,1,0),
MAKE_SYSREGCODE(AFSR1_EL1, 3,0,5,1,1),
MAKE_SYSREGCODE(AFSR0_EL2, 3,4,5,1,0),
MAKE_SYSREGCODE(AFSR1_EL2, 3,4,5,1,1),
MAKE_SYSREGCODE(AFSR0_EL3, 3,6,5,1,0),
MAKE_SYSREGCODE(AFSR1_EL3, 3,6,5,1,1),
MAKE_SYSREGCODE(ESR_EL1, 3,0,5,2,0),
MAKE_SYSREGCODE(ESR_EL2, 3,4,5,2,0),
MAKE_SYSREGCODE(ESR_EL3, 3,6,5,2,0),
MAKE_SYSREGCODE(FPEXC32_EL2, 3,4,5,3,0),
MAKE_SYSREGCODE(FAR_EL1, 3,0,6,0,0),
MAKE_SYSREGCODE(FAR_EL2, 3,4,6,0,0),
MAKE_SYSREGCODE(FAR_EL3, 3,6,6,0,0),
MAKE_SYSREGCODE(HPFAR_EL2, 3,4,6,0,4),
MAKE_SYSREGCODE(PAR_EL1, 3,0,7,4,0),
MAKE_SYSREGCODE(MAIR_EL1, 3,0,10,2,0),
MAKE_SYSREGCODE(MAIR_EL2, 3,4,10,2,0),
MAKE_SYSREGCODE(MAIR_EL3, 3,6,10,2,0),
MAKE_SYSREGCODE(AMAIR_EL1, 3,0,10,3,0),
MAKE_SYSREGCODE(AMAIR_EL2, 3,4,10,3,0),
MAKE_SYSREGCODE(AMAIR_EL3, 3,6,10,3,0),
MAKE_SYSREGCODE(VBAR_EL1, 3,0,12,0,0),
MAKE_SYSREGCODE(VBAR_EL2, 3,4,12,0,0),
MAKE_SYSREGCODE(VBAR_EL3, 3,6,12,0,0),
MAKE_SYSREGCODE(RVBAR_EL1, 3,0,12,0,1),
MAKE_SYSREGCODE(RVBAR_EL2, 3,4,12,0,1),
MAKE_SYSREGCODE(RVBAR_EL3, 3,6,12,0,1),
MAKE_SYSREGCODE(RMR_EL1, 3,0,12,0,2),
MAKE_SYSREGCODE(RMR_EL2, 3,4,12,0,2),
MAKE_SYSREGCODE(RMR_EL3, 3,6,12,0,2),
MAKE_SYSREGCODE(ISR_EL1, 3,0,12,1,0),
MAKE_SYSREGCODE(CONTEXTIDR_EL1, 3,0,13,0,1),
MAKE_SYSREGCODE(TPIDR_EL0, 3,3,13,0,2),
MAKE_SYSREGCODE(TPIDRRO_EL0, 3,3,13,0,3),
MAKE_SYSREGCODE(TPIDR_EL1, 3,0,13,0,4),
MAKE_SYSREGCODE(TPIDR_EL2, 3,4,13,0,2),
MAKE_SYSREGCODE(TPIDR_EL3, 3,6,13,0,2),
MAKE_SYSREGCODE(TEECR32_EL1, 2,2,0,0,0),
MAKE_SYSREGCODE(CNTFRQ_EL0, 3,3,14,0,0),
MAKE_SYSREGCODE(CNTPCT_EL0, 3,3,14,0,1),
MAKE_SYSREGCODE(CNTVCT_EL0, 3,3,14,0,2),
MAKE_SYSREGCODE(CNTVOFF_EL2, 3,4,14,0,3),
MAKE_SYSREGCODE(CNTKCTL_EL1, 3,0,14,1,0),
MAKE_SYSREGCODE(CNTHCTL_EL2, 3,4,14,1,0),
MAKE_SYSREGCODE(CNTP_TVAL_EL0, 3,3,14,2,0),
MAKE_SYSREGCODE(CNTP_CTL_EL0, 3,3,14,2,1),
MAKE_SYSREGCODE(CNTP_CVAL_EL0, 3,3,14,2,2),
MAKE_SYSREGCODE(CNTV_TVAL_EL0, 3,3,14,3,0),
MAKE_SYSREGCODE(CNTV_CTL_EL0, 3,3,14,3,1),
MAKE_SYSREGCODE(CNTV_CVAL_EL0, 3,3,14,3,2),
MAKE_SYSREGCODE(CNTHP_TVAL_EL2, 3,4,14,2,0),
MAKE_SYSREGCODE(CNTHP_CTL_EL2, 3,4,14,2,1),
MAKE_SYSREGCODE(CNTHP_CVAL_EL2, 3,4,14,2,2),
MAKE_SYSREGCODE(CNTPS_TVAL_EL1, 3,7,14,2,0),
MAKE_SYSREGCODE(CNTPS_CTL_EL1, 3,7,14,2,1),
MAKE_SYSREGCODE(CNTPS_CVAL_EL1, 3,7,14,2,2),
MAKE_SYSREGCODE(DACR32_EL2, 3,4,3,0,0),
MAKE_SYSREGCODE(IFSR32_EL2, 3,4,5,0,1),
MAKE_SYSREGCODE(TEEHBR32_EL1, 2,2,1,0,0),
MAKE_SYSREGCODE(SDER32_EL3, 3,6,1,1,1),
MAKE_SYSREGCODE(MDSCR_EL1, 2,0,0,2, 2),
MAKE_SYSREGCODE(MDCCSR_EL0, 2,3,0,1, 0),
MAKE_SYSREGCODE(MDCCINT_EL1, 2,0,0,2, 0),
MAKE_SYSREGCODE(DBGDTR_EL0, 2,3,0,4, 0),
MAKE_SYSREGCODE(DBGDTRRX_EL0, 2,3,0,5, 0),
MAKE_SYSREGCODE(DBGDTRTX_EL0, 2,3,0,5, 0),
MAKE_SYSREGCODE(OSDTRRX_EL1, 2,0,0,0, 2),
MAKE_SYSREGCODE(OSDTRTX_EL1, 2,0,0,3, 2),
MAKE_SYSREGCODE(OSECCR_EL1, 2,0,0,6, 2),
MAKE_SYSREGCODE(DBGVCR32_EL2, 2,4,0,7, 0),
MAKE_SYSREGCODE(DBGBVR0_EL1, 2,0,0,0, 4),
MAKE_SYSREGCODE(DBGBVR1_EL1, 2,0,0,1, 4),
MAKE_SYSREGCODE(DBGBVR2_EL1, 2,0,0,2, 4),
MAKE_SYSREGCODE(DBGBVR3_EL1, 2,0,0,3, 4),
MAKE_SYSREGCODE(DBGBVR4_EL1, 2,0,0,4, 4),
MAKE_SYSREGCODE(DBGBVR5_EL1, 2,0,0,5, 4),
MAKE_SYSREGCODE(DBGBVR6_EL1, 2,0,0,6, 4),
MAKE_SYSREGCODE(DBGBVR7_EL1, 2,0,0,7, 4),
MAKE_SYSREGCODE(DBGBVR8_EL1, 2,0,0,8, 4),
MAKE_SYSREGCODE(DBGBVR9_EL1, 2,0,0,9, 4),
MAKE_SYSREGCODE(DBGBVR10_EL1, 2,0,0,10,4),
MAKE_SYSREGCODE(DBGBVR11_EL1, 2,0,0,11,4),
MAKE_SYSREGCODE(DBGBVR12_EL1, 2,0,0,12,4),
MAKE_SYSREGCODE(DBGBVR13_EL1, 2,0,0,13,4),
MAKE_SYSREGCODE(DBGBVR14_EL1, 2,0,0,14,4),
MAKE_SYSREGCODE(DBGBVR15_EL1, 2,0,0,15,4),
MAKE_SYSREGCODE(DBGBCR0_EL1, 2,0,0,0, 5),
MAKE_SYSREGCODE(DBGBCR1_EL1, 2,0,0,1, 5),
MAKE_SYSREGCODE(DBGBCR2_EL1, 2,0,0,2, 5),
MAKE_SYSREGCODE(DBGBCR3_EL1, 2,0,0,3, 5),
MAKE_SYSREGCODE(DBGBCR4_EL1, 2,0,0,4, 5),
MAKE_SYSREGCODE(DBGBCR5_EL1, 2,0,0,5, 5),
MAKE_SYSREGCODE(DBGBCR6_EL1, 2,0,0,6, 5),
MAKE_SYSREGCODE(DBGBCR7_EL1, 2,0,0,7, 5),
MAKE_SYSREGCODE(DBGBCR8_EL1, 2,0,0,8, 5),
MAKE_SYSREGCODE(DBGBCR9_EL1, 2,0,0,9, 5),
MAKE_SYSREGCODE(DBGBCR10_EL1, 2,0,0,10,5),
MAKE_SYSREGCODE(DBGBCR11_EL1, 2,0,0,11,5),
MAKE_SYSREGCODE(DBGBCR12_EL1, 2,0,0,12,5),
MAKE_SYSREGCODE(DBGBCR13_EL1, 2,0,0,13,5),
MAKE_SYSREGCODE(DBGBCR14_EL1, 2,0,0,14,5),
MAKE_SYSREGCODE(DBGBCR15_EL1, 2,0,0,15,5),
MAKE_SYSREGCODE(DBGWVR0_EL1, 2,0,0,0, 6),
MAKE_SYSREGCODE(DBGWVR1_EL1, 2,0,0,1, 6),
MAKE_SYSREGCODE(DBGWVR2_EL1, 2,0,0,2, 6),
MAKE_SYSREGCODE(DBGWVR3_EL1, 2,0,0,3, 6),
MAKE_SYSREGCODE(DBGWVR4_EL1, 2,0,0,4, 6),
MAKE_SYSREGCODE(DBGWVR5_EL1, 2,0,0,5, 6),
MAKE_SYSREGCODE(DBGWVR6_EL1, 2,0,0,6, 6),
MAKE_SYSREGCODE(DBGWVR7_EL1, 2,0,0,7, 6),
MAKE_SYSREGCODE(DBGWVR8_EL1, 2,0,0,8, 6),
MAKE_SYSREGCODE(DBGWVR9_EL1, 2,0,0,9, 6),
MAKE_SYSREGCODE(DBGWVR10_EL1, 2,0,0,10,6),
MAKE_SYSREGCODE(DBGWVR11_EL1, 2,0,0,11,6),
MAKE_SYSREGCODE(DBGWVR12_EL1, 2,0,0,12,6),
MAKE_SYSREGCODE(DBGWVR13_EL1, 2,0,0,13,6),
MAKE_SYSREGCODE(DBGWVR14_EL1, 2,0,0,14,6),
MAKE_SYSREGCODE(DBGWVR15_EL1, 2,0,0,15,6),
MAKE_SYSREGCODE(DBGWCR0_EL1, 2,0,0,0, 7),
MAKE_SYSREGCODE(DBGWCR1_EL1, 2,0,0,1, 7),
MAKE_SYSREGCODE(DBGWCR2_EL1, 2,0,0,2, 7),
MAKE_SYSREGCODE(DBGWCR3_EL1, 2,0,0,3, 7),
MAKE_SYSREGCODE(DBGWCR4_EL1, 2,0,0,4, 7),
MAKE_SYSREGCODE(DBGWCR5_EL1, 2,0,0,5, 7),
MAKE_SYSREGCODE(DBGWCR6_EL1, 2,0,0,6, 7),
MAKE_SYSREGCODE(DBGWCR7_EL1, 2,0,0,7, 7),
MAKE_SYSREGCODE(DBGWCR8_EL1, 2,0,0,8, 7),
MAKE_SYSREGCODE(DBGWCR9_EL1, 2,0,0,9, 7),
MAKE_SYSREGCODE(DBGWCR10_EL1, 2,0,0,10,7),
MAKE_SYSREGCODE(DBGWCR11_EL1, 2,0,0,11,7),
MAKE_SYSREGCODE(DBGWCR12_EL1, 2,0,0,12,7),
MAKE_SYSREGCODE(DBGWCR13_EL1, 2,0,0,13,7),
MAKE_SYSREGCODE(DBGWCR14_EL1, 2,0,0,14,7),
MAKE_SYSREGCODE(DBGWCR15_EL1, 2,0,0,15,7),
MAKE_SYSREGCODE(MDRAR_EL1, 2,0,1,0, 0),
MAKE_SYSREGCODE(OSLAR_EL1, 2,0,1,0, 4),
MAKE_SYSREGCODE(OSLSR_EL1, 2,0,1,1, 4),
MAKE_SYSREGCODE(OSDLR_EL1, 2,0,1,3, 4),
MAKE_SYSREGCODE(DBGPRCR_EL1, 2,0,1,4, 4),
MAKE_SYSREGCODE(DBGCLAIMSET_EL1, 2,0,7,8, 6),
MAKE_SYSREGCODE(DBGCLAIMCLR_EL1, 2,0,7,9, 6),
MAKE_SYSREGCODE(DBGAUTHSTATUS_EL1,2,0,7,14,6),
MAKE_SYSREGCODE(PMCR_EL0, 3,3,9,12, 0),
MAKE_SYSREGCODE(PMCNTENSET_EL0, 3,3,9,12, 1),
MAKE_SYSREGCODE(PMCNTENCLR_EL0, 3,3,9,12, 2),
MAKE_SYSREGCODE(PMOVSCLR_EL0, 3,3,9,12, 3),
MAKE_SYSREGCODE(PMSWINC_EL0, 3,3,9,12, 4),
MAKE_SYSREGCODE(PMSELR_EL0, 3,3,9,12, 5),
MAKE_SYSREGCODE(PMCEID0_EL0, 3,3,9,12, 6),
MAKE_SYSREGCODE(PMCEID1_EL0, 3,3,9,12, 7),
MAKE_SYSREGCODE(PMCCNTR_EL0, 3,3,9,13, 0),
MAKE_SYSREGCODE(PMXEVTYPER_EL0, 3,3,9,13, 1),
MAKE_SYSREGCODE(PMXEVCNTR_EL0, 3,3,9,13, 2),
MAKE_SYSREGCODE(PMUSERENR_EL0, 3,3,9,14, 0),
MAKE_SYSREGCODE(PMINTENSET_EL1, 3,0,9,14, 1),
MAKE_SYSREGCODE(PMINTENCLR_EL1, 3,0,9,14, 2),
MAKE_SYSREGCODE(PMOVSSET_EL0, 3,3,9,14, 3),
MAKE_SYSREGCODE(PMEVCNTR0_EL0, 3,3,14,8, 0),
MAKE_SYSREGCODE(PMEVCNTR1_EL0, 3,3,14,8, 1),
MAKE_SYSREGCODE(PMEVCNTR2_EL0, 3,3,14,8, 2),
MAKE_SYSREGCODE(PMEVCNTR3_EL0, 3,3,14,8, 3),
MAKE_SYSREGCODE(PMEVCNTR4_EL0, 3,3,14,8, 4),
MAKE_SYSREGCODE(PMEVCNTR5_EL0, 3,3,14,8, 5),
MAKE_SYSREGCODE(PMEVCNTR6_EL0, 3,3,14,8, 6),
MAKE_SYSREGCODE(PMEVCNTR7_EL0, 3,3,14,8, 7),
MAKE_SYSREGCODE(PMEVCNTR8_EL0, 3,3,14,9, 0),
MAKE_SYSREGCODE(PMEVCNTR9_EL0, 3,3,14,9, 1),
MAKE_SYSREGCODE(PMEVCNTR10_EL0, 3,3,14,9, 2),
MAKE_SYSREGCODE(PMEVCNTR11_EL0, 3,3,14,9, 3),
MAKE_SYSREGCODE(PMEVCNTR12_EL0, 3,3,14,9, 4),
MAKE_SYSREGCODE(PMEVCNTR13_EL0, 3,3,14,9, 5),
MAKE_SYSREGCODE(PMEVCNTR14_EL0, 3,3,14,9, 6),
MAKE_SYSREGCODE(PMEVCNTR15_EL0, 3,3,14,9, 7),
MAKE_SYSREGCODE(PMEVCNTR16_EL0, 3,3,14,10,0),
MAKE_SYSREGCODE(PMEVCNTR17_EL0, 3,3,14,10,1),
MAKE_SYSREGCODE(PMEVCNTR18_EL0, 3,3,14,10,2),
MAKE_SYSREGCODE(PMEVCNTR19_EL0, 3,3,14,10,3),
MAKE_SYSREGCODE(PMEVCNTR20_EL0, 3,3,14,10,4),
MAKE_SYSREGCODE(PMEVCNTR21_EL0, 3,3,14,10,5),
MAKE_SYSREGCODE(PMEVCNTR22_EL0, 3,3,14,10,6),
MAKE_SYSREGCODE(PMEVCNTR23_EL0, 3,3,14,10,7),
MAKE_SYSREGCODE(PMEVCNTR24_EL0, 3,3,14,11,0),
MAKE_SYSREGCODE(PMEVCNTR25_EL0, 3,3,14,11,1),
MAKE_SYSREGCODE(PMEVCNTR26_EL0, 3,3,14,11,2),
MAKE_SYSREGCODE(PMEVCNTR27_EL0, 3,3,14,11,3),
MAKE_SYSREGCODE(PMEVCNTR28_EL0, 3,3,14,11,4),
MAKE_SYSREGCODE(PMEVCNTR29_EL0, 3,3,14,11,5),
MAKE_SYSREGCODE(PMEVCNTR30_EL0, 3,3,14,11,6),
MAKE_SYSREGCODE(PMEVTYPER0_EL0, 3,3,14,12,0),
MAKE_SYSREGCODE(PMEVTYPER1_EL0, 3,3,14,12,1),
MAKE_SYSREGCODE(PMEVTYPER2_EL0, 3,3,14,12,2),
MAKE_SYSREGCODE(PMEVTYPER3_EL0, 3,3,14,12,3),
MAKE_SYSREGCODE(PMEVTYPER4_EL0, 3,3,14,12,4),
MAKE_SYSREGCODE(PMEVTYPER5_EL0, 3,3,14,12,5),
MAKE_SYSREGCODE(PMEVTYPER6_EL0, 3,3,14,12,6),
MAKE_SYSREGCODE(PMEVTYPER7_EL0, 3,3,14,12,7),
MAKE_SYSREGCODE(PMEVTYPER8_EL0, 3,3,14,13,0),
MAKE_SYSREGCODE(PMEVTYPER9_EL0, 3,3,14,13,1),
MAKE_SYSREGCODE(PMEVTYPER10_EL0, 3,3,14,13,2),
MAKE_SYSREGCODE(PMEVTYPER11_EL0, 3,3,14,13,3),
MAKE_SYSREGCODE(PMEVTYPER12_EL0, 3,3,14,13,4),
MAKE_SYSREGCODE(PMEVTYPER13_EL0, 3,3,14,13,5),
MAKE_SYSREGCODE(PMEVTYPER14_EL0, 3,3,14,13,6),
MAKE_SYSREGCODE(PMEVTYPER15_EL0, 3,3,14,13,7),
MAKE_SYSREGCODE(PMEVTYPER16_EL0, 3,3,14,14,0),
MAKE_SYSREGCODE(PMEVTYPER17_EL0, 3,3,14,14,1),
MAKE_SYSREGCODE(PMEVTYPER18_EL0, 3,3,14,14,2),
MAKE_SYSREGCODE(PMEVTYPER19_EL0, 3,3,14,14,3),
MAKE_SYSREGCODE(PMEVTYPER20_EL0, 3,3,14,14,4),
MAKE_SYSREGCODE(PMEVTYPER21_EL0, 3,3,14,14,5),
MAKE_SYSREGCODE(PMEVTYPER22_EL0, 3,3,14,14,6),
MAKE_SYSREGCODE(PMEVTYPER23_EL0, 3,3,14,14,7),
MAKE_SYSREGCODE(PMEVTYPER24_EL0, 3,3,14,15,0),
MAKE_SYSREGCODE(PMEVTYPER25_EL0, 3,3,14,15,1),
MAKE_SYSREGCODE(PMEVTYPER26_EL0, 3,3,14,15,2),
MAKE_SYSREGCODE(PMEVTYPER27_EL0, 3,3,14,15,3),
MAKE_SYSREGCODE(PMEVTYPER28_EL0, 3,3,14,15,4),
MAKE_SYSREGCODE(PMEVTYPER29_EL0, 3,3,14,15,5),
MAKE_SYSREGCODE(PMEVTYPER30_EL0, 3,3,14,15,6),
MAKE_SYSREGCODE(PMCCFILTR_EL0, 3,3,14,15,7)
};
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/SysRegister.java 0000664 0000000 0000000 00000002666 13344175732 0024743 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
import static jnr.a64asm.SIZE.*;
import static jnr.a64asm.SYSREG_CODE.SPSR_EL1;
import static jnr.a64asm.SYSREG_CODE.SYSREG_MAX;
public class SysRegister extends Operand {
SYSREG_CODE sysRegEnum;
private static final SysRegister[] sys = new SysRegister[305];
public SysRegister(SYSREG_CODE sysRegEnum) {
super(OP.OP_SYSREG, SIZE_DWORD);
this.sysRegEnum = sysRegEnum;
}
static {
for (SYSREG_CODE i = SPSR_EL1; i.ordinal()< SYSREG_MAX.ordinal();) {
sys[i.ordinal()] = new SysRegister(i);
i = SYSREG_CODE.valueOf(i.ordinal() +1);
}
}
public static final SysRegister sysReg(SYSREG_CODE reg) {
return sys[reg.ordinal()];
}
public SYSREG_CODE getEnum(){
return this.sysRegEnum;
}
}
jnr-a64asm-jnr-a64asm-1.0.0/src/main/java/jnr/a64asm/Util.java 0000664 0000000 0000000 00000003311 13344175732 0023361 0 ustar 00root root 0000000 0000000 /*
* Copyright (C) 2018 Ossdev07
*
* This file is part of the JNR project.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package jnr.a64asm;
public final class Util {
private Util() {
}
/** Returns @c true if a given integer @a x is signed 8 bit integer */
static final boolean isInt8(long x) {
return x >= -128 && x <= 127;
}
/** Returns @c true if a given integer @a x is unsigned 8 bit integer */
static final boolean isUInt8(long x) {
return x >= 0 && x <= 255;
}
/** Returns @c true if a given integer @a x is signed 16 bit integer */
static final boolean isInt16(long x) {
return x >= -32768 && x <= 32767;
}
/** Returns @c true if a given integer @a x is unsigned 16 bit integer */
static final boolean isUInt16(long x) {
return x >= 0 && x <= 65535;
}
/** Returns @c true if a given integer @a x is signed 32 bit integer */
static final boolean isInt32(long x) {
return x >= Integer.MIN_VALUE && x <= Integer.MAX_VALUE;
}
/** Returns @c true if a given integer @a x is unsigned 32 bit integer */
static final boolean isUInt32(long x) {
return x >= 0 && x <= 0xffffffffL;
}
}