jnr-x86asm-0.1/ 0000755 0001750 0001750 00000000000 11425031554 013225 5 ustar twerner twerner jnr-x86asm-0.1/pom.xml 0000644 0001750 0001750 00000006535 11425031554 014553 0 ustar twerner twerner 4.0.0org.jruby.extrasjnr-x86asmjar0.1jnr-x86asmA pure-java X86 and X86_64 assemblerhttp://jnr.kenai.comGNU Lesser General Public License Version 3http://www.gnu.org/licenses/lgpl-3.0.txtreposcm:git:http://github.com/wmeissner/jnr-x86asm.githttp://github.com/wmeissner/jnr-x86asmcodehaus-jruby-repositoryJRuby Central Repositorydav:https://dav.codehaus.org/repository/jrubycodehaus-jruby-snapshot-repositoryJRuby Central Development Repositorydav:https://dav.codehaus.org/snapshots.repository/jrubymaven2-repository.dev.java.netJava.net Repository for Mavenhttp://download.java.net/maven/2/codehausCodehaus Repositorytruefalsehttp://repository.codehaus.orgmaven2-repository.dev.java.netJava.net Repository for Mavenhttp://download.java.net/maven/2/wmeissnerWayne Meissnerwmeissner@gmail.comtruetruejunitjunit4.5testsrctestorg.apache.maven.pluginsmaven-compiler-plugin2.0.21.51.5org.jvnet.wagon-svnwagon-svn1.8org.apache.maven.wagonwagon-webdav
jnr-x86asm-0.1/LICENSE 0000644 0001750 0001750 00000003741 11425031554 014237 0 ustar twerner twerner
This code is free software: you can redistribute it and/or modify it under
the terms of the GNU Lesser General Public License version 3 only, as
published by the Free Software Foundation.
This code is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
version 3 for more details.
You should have received a copy of the GNU Lesser General Public License
version 3 along with this work. If not, see .
Although the jnr-x86asm is covered under the LGPLv3 as stated above, some of the code is based
on the asmjit project (http://code.google.com/p/asmjit/) and the license for that project is reproduced here. This does _NOT_ mean jnr-x86asm is dual licensed, it is covered solely by the LPGLv3.
Copyright (c) 2008-2009, Petr Kobalicek
Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use,
copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following
conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
jnr-x86asm-0.1/COPYING.LESSER 0000644 0001750 0001750 00000016727 11425031554 015271 0 ustar twerner twerner GNU LESSER GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc.
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
This version of the GNU Lesser General Public License incorporates
the terms and conditions of version 3 of the GNU General Public
License, supplemented by the additional permissions listed below.
0. Additional Definitions.
As used herein, "this License" refers to version 3 of the GNU Lesser
General Public License, and the "GNU GPL" refers to version 3 of the GNU
General Public License.
"The Library" refers to a covered work governed by this License,
other than an Application or a Combined Work as defined below.
An "Application" is any work that makes use of an interface provided
by the Library, but which is not otherwise based on the Library.
Defining a subclass of a class defined by the Library is deemed a mode
of using an interface provided by the Library.
A "Combined Work" is a work produced by combining or linking an
Application with the Library. The particular version of the Library
with which the Combined Work was made is also called the "Linked
Version".
The "Minimal Corresponding Source" for a Combined Work means the
Corresponding Source for the Combined Work, excluding any source code
for portions of the Combined Work that, considered in isolation, are
based on the Application, and not on the Linked Version.
The "Corresponding Application Code" for a Combined Work means the
object code and/or source code for the Application, including any data
and utility programs needed for reproducing the Combined Work from the
Application, but excluding the System Libraries of the Combined Work.
1. Exception to Section 3 of the GNU GPL.
You may convey a covered work under sections 3 and 4 of this License
without being bound by section 3 of the GNU GPL.
2. Conveying Modified Versions.
If you modify a copy of the Library, and, in your modifications, a
facility refers to a function or data to be supplied by an Application
that uses the facility (other than as an argument passed when the
facility is invoked), then you may convey a copy of the modified
version:
a) under this License, provided that you make a good faith effort to
ensure that, in the event an Application does not supply the
function or data, the facility still operates, and performs
whatever part of its purpose remains meaningful, or
b) under the GNU GPL, with none of the additional permissions of
this License applicable to that copy.
3. Object Code Incorporating Material from Library Header Files.
The object code form of an Application may incorporate material from
a header file that is part of the Library. You may convey such object
code under terms of your choice, provided that, if the incorporated
material is not limited to numerical parameters, data structure
layouts and accessors, or small macros, inline functions and templates
(ten or fewer lines in length), you do both of the following:
a) Give prominent notice with each copy of the object code that the
Library is used in it and that the Library and its use are
covered by this License.
b) Accompany the object code with a copy of the GNU GPL and this license
document.
4. Combined Works.
You may convey a Combined Work under terms of your choice that,
taken together, effectively do not restrict modification of the
portions of the Library contained in the Combined Work and reverse
engineering for debugging such modifications, if you also do each of
the following:
a) Give prominent notice with each copy of the Combined Work that
the Library is used in it and that the Library and its use are
covered by this License.
b) Accompany the Combined Work with a copy of the GNU GPL and this license
document.
c) For a Combined Work that displays copyright notices during
execution, include the copyright notice for the Library among
these notices, as well as a reference directing the user to the
copies of the GNU GPL and this license document.
d) Do one of the following:
0) Convey the Minimal Corresponding Source under the terms of this
License, and the Corresponding Application Code in a form
suitable for, and under terms that permit, the user to
recombine or relink the Application with a modified version of
the Linked Version to produce a modified Combined Work, in the
manner specified by section 6 of the GNU GPL for conveying
Corresponding Source.
1) Use a suitable shared library mechanism for linking with the
Library. A suitable mechanism is one that (a) uses at run time
a copy of the Library already present on the user's computer
system, and (b) will operate properly with a modified version
of the Library that is interface-compatible with the Linked
Version.
e) Provide Installation Information, but only if you would otherwise
be required to provide such information under section 6 of the
GNU GPL, and only to the extent that such information is
necessary to install and execute a modified version of the
Combined Work produced by recombining or relinking the
Application with a modified version of the Linked Version. (If
you use option 4d0, the Installation Information must accompany
the Minimal Corresponding Source and Corresponding Application
Code. If you use option 4d1, you must provide the Installation
Information in the manner specified by section 6 of the GNU GPL
for conveying Corresponding Source.)
5. Combined Libraries.
You may place library facilities that are a work based on the
Library side by side in a single library together with other library
facilities that are not Applications and are not covered by this
License, and convey such a combined library under terms of your
choice, if you do both of the following:
a) Accompany the combined library with a copy of the same work based
on the Library, uncombined with any other library facilities,
conveyed under the terms of this License.
b) Give prominent notice with the combined library that part of it
is a work based on the Library, and explaining where to find the
accompanying uncombined form of the same work.
6. Revised Versions of the GNU Lesser General Public License.
The Free Software Foundation may publish revised and/or new versions
of the GNU Lesser General Public License from time to time. Such new
versions will be similar in spirit to the present version, but may
differ in detail to address new problems or concerns.
Each version is given a distinguishing version number. If the
Library as you received it specifies that a certain numbered version
of the GNU Lesser General Public License "or any later version"
applies to it, you have the option of following the terms and
conditions either of that published version or of any later version
published by the Free Software Foundation. If the Library as you
received it does not specify a version number of the GNU Lesser
General Public License, you may choose any version of the GNU Lesser
General Public License ever published by the Free Software Foundation.
If the Library as you received it specifies that a proxy can decide
whether future versions of the GNU Lesser General Public License shall
apply, that proxy's public statement of acceptance of any version is
permanent authorization for you to choose that version for the
Library.
jnr-x86asm-0.1/build.xml 0000644 0001750 0001750 00000007103 11425031554 015047 0 ustar twerner twerner
Builds, tests, and runs the project jnr-x86asm.
jnr-x86asm-0.1/COPYING 0000644 0001750 0001750 00000104513 11425031554 014264 0 ustar twerner twerner GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc.
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The GNU General Public License is a free, copyleft license for
software and other kinds of works.
The licenses for most software and other practical works are designed
to take away your freedom to share and change the works. By contrast,
the GNU General Public License is intended to guarantee your freedom to
share and change all versions of a program--to make sure it remains free
software for all its users. We, the Free Software Foundation, use the
GNU General Public License for most of our software; it applies also to
any other work released this way by its authors. You can apply it to
your programs, too.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
them if you wish), that you receive source code or can get it if you
want it, that you can change the software or use pieces of it in new
free programs, and that you know you can do these things.
To protect your rights, we need to prevent others from denying you
these rights or asking you to surrender the rights. Therefore, you have
certain responsibilities if you distribute copies of the software, or if
you modify it: responsibilities to respect the freedom of others.
For example, if you distribute copies of such a program, whether
gratis or for a fee, you must pass on to the recipients the same
freedoms that you received. You must make sure that they, too, receive
or can get the source code. And you must show them these terms so they
know their rights.
Developers that use the GNU GPL protect your rights with two steps:
(1) assert copyright on the software, and (2) offer you this License
giving you legal permission to copy, distribute and/or modify it.
For the developers' and authors' protection, the GPL clearly explains
that there is no warranty for this free software. For both users' and
authors' sake, the GPL requires that modified versions be marked as
changed, so that their problems will not be attributed erroneously to
authors of previous versions.
Some devices are designed to deny users access to install or run
modified versions of the software inside them, although the manufacturer
can do so. This is fundamentally incompatible with the aim of
protecting users' freedom to change the software. The systematic
pattern of such abuse occurs in the area of products for individuals to
use, which is precisely where it is most unacceptable. Therefore, we
have designed this version of the GPL to prohibit the practice for those
products. If such problems arise substantially in other domains, we
stand ready to extend this provision to those domains in future versions
of the GPL, as needed to protect the freedom of users.
Finally, every program is threatened constantly by software patents.
States should not allow patents to restrict development and use of
software on general-purpose computers, but in those that do, we wish to
avoid the special danger that patents applied to a free program could
make it effectively proprietary. To prevent this, the GPL assures that
patents cannot be used to render the program non-free.
The precise terms and conditions for copying, distribution and
modification follow.
TERMS AND CONDITIONS
0. Definitions.
"This License" refers to version 3 of the GNU General Public License.
"Copyright" also means copyright-like laws that apply to other kinds of
works, such as semiconductor masks.
"The Program" refers to any copyrightable work licensed under this
License. Each licensee is addressed as "you". "Licensees" and
"recipients" may be individuals or organizations.
To "modify" a work means to copy from or adapt all or part of the work
in a fashion requiring copyright permission, other than the making of an
exact copy. The resulting work is called a "modified version" of the
earlier work or a work "based on" the earlier work.
A "covered work" means either the unmodified Program or a work based
on the Program.
To "propagate" a work means to do anything with it that, without
permission, would make you directly or secondarily liable for
infringement under applicable copyright law, except executing it on a
computer or modifying a private copy. Propagation includes copying,
distribution (with or without modification), making available to the
public, and in some countries other activities as well.
To "convey" a work means any kind of propagation that enables other
parties to make or receive copies. Mere interaction with a user through
a computer network, with no transfer of a copy, is not conveying.
An interactive user interface displays "Appropriate Legal Notices"
to the extent that it includes a convenient and prominently visible
feature that (1) displays an appropriate copyright notice, and (2)
tells the user that there is no warranty for the work (except to the
extent that warranties are provided), that licensees may convey the
work under this License, and how to view a copy of this License. If
the interface presents a list of user commands or options, such as a
menu, a prominent item in the list meets this criterion.
1. Source Code.
The "source code" for a work means the preferred form of the work
for making modifications to it. "Object code" means any non-source
form of a work.
A "Standard Interface" means an interface that either is an official
standard defined by a recognized standards body, or, in the case of
interfaces specified for a particular programming language, one that
is widely used among developers working in that language.
The "System Libraries" of an executable work include anything, other
than the work as a whole, that (a) is included in the normal form of
packaging a Major Component, but which is not part of that Major
Component, and (b) serves only to enable use of the work with that
Major Component, or to implement a Standard Interface for which an
implementation is available to the public in source code form. A
"Major Component", in this context, means a major essential component
(kernel, window system, and so on) of the specific operating system
(if any) on which the executable work runs, or a compiler used to
produce the work, or an object code interpreter used to run it.
The "Corresponding Source" for a work in object code form means all
the source code needed to generate, install, and (for an executable
work) run the object code and to modify the work, including scripts to
control those activities. However, it does not include the work's
System Libraries, or general-purpose tools or generally available free
programs which are used unmodified in performing those activities but
which are not part of the work. For example, Corresponding Source
includes interface definition files associated with source files for
the work, and the source code for shared libraries and dynamically
linked subprograms that the work is specifically designed to require,
such as by intimate data communication or control flow between those
subprograms and other parts of the work.
The Corresponding Source need not include anything that users
can regenerate automatically from other parts of the Corresponding
Source.
The Corresponding Source for a work in source code form is that
same work.
2. Basic Permissions.
All rights granted under this License are granted for the term of
copyright on the Program, and are irrevocable provided the stated
conditions are met. This License explicitly affirms your unlimited
permission to run the unmodified Program. The output from running a
covered work is covered by this License only if the output, given its
content, constitutes a covered work. This License acknowledges your
rights of fair use or other equivalent, as provided by copyright law.
You may make, run and propagate covered works that you do not
convey, without conditions so long as your license otherwise remains
in force. You may convey covered works to others for the sole purpose
of having them make modifications exclusively for you, or provide you
with facilities for running those works, provided that you comply with
the terms of this License in conveying all material for which you do
not control copyright. Those thus making or running the covered works
for you must do so exclusively on your behalf, under your direction
and control, on terms that prohibit them from making any copies of
your copyrighted material outside their relationship with you.
Conveying under any other circumstances is permitted solely under
the conditions stated below. Sublicensing is not allowed; section 10
makes it unnecessary.
3. Protecting Users' Legal Rights From Anti-Circumvention Law.
No covered work shall be deemed part of an effective technological
measure under any applicable law fulfilling obligations under article
11 of the WIPO copyright treaty adopted on 20 December 1996, or
similar laws prohibiting or restricting circumvention of such
measures.
When you convey a covered work, you waive any legal power to forbid
circumvention of technological measures to the extent such circumvention
is effected by exercising rights under this License with respect to
the covered work, and you disclaim any intention to limit operation or
modification of the work as a means of enforcing, against the work's
users, your or third parties' legal rights to forbid circumvention of
technological measures.
4. Conveying Verbatim Copies.
You may convey verbatim copies of the Program's source code as you
receive it, in any medium, provided that you conspicuously and
appropriately publish on each copy an appropriate copyright notice;
keep intact all notices stating that this License and any
non-permissive terms added in accord with section 7 apply to the code;
keep intact all notices of the absence of any warranty; and give all
recipients a copy of this License along with the Program.
You may charge any price or no price for each copy that you convey,
and you may offer support or warranty protection for a fee.
5. Conveying Modified Source Versions.
You may convey a work based on the Program, or the modifications to
produce it from the Program, in the form of source code under the
terms of section 4, provided that you also meet all of these conditions:
a) The work must carry prominent notices stating that you modified
it, and giving a relevant date.
b) The work must carry prominent notices stating that it is
released under this License and any conditions added under section
7. This requirement modifies the requirement in section 4 to
"keep intact all notices".
c) You must license the entire work, as a whole, under this
License to anyone who comes into possession of a copy. This
License will therefore apply, along with any applicable section 7
additional terms, to the whole of the work, and all its parts,
regardless of how they are packaged. This License gives no
permission to license the work in any other way, but it does not
invalidate such permission if you have separately received it.
d) If the work has interactive user interfaces, each must display
Appropriate Legal Notices; however, if the Program has interactive
interfaces that do not display Appropriate Legal Notices, your
work need not make them do so.
A compilation of a covered work with other separate and independent
works, which are not by their nature extensions of the covered work,
and which are not combined with it such as to form a larger program,
in or on a volume of a storage or distribution medium, is called an
"aggregate" if the compilation and its resulting copyright are not
used to limit the access or legal rights of the compilation's users
beyond what the individual works permit. Inclusion of a covered work
in an aggregate does not cause this License to apply to the other
parts of the aggregate.
6. Conveying Non-Source Forms.
You may convey a covered work in object code form under the terms
of sections 4 and 5, provided that you also convey the
machine-readable Corresponding Source under the terms of this License,
in one of these ways:
a) Convey the object code in, or embodied in, a physical product
(including a physical distribution medium), accompanied by the
Corresponding Source fixed on a durable physical medium
customarily used for software interchange.
b) Convey the object code in, or embodied in, a physical product
(including a physical distribution medium), accompanied by a
written offer, valid for at least three years and valid for as
long as you offer spare parts or customer support for that product
model, to give anyone who possesses the object code either (1) a
copy of the Corresponding Source for all the software in the
product that is covered by this License, on a durable physical
medium customarily used for software interchange, for a price no
more than your reasonable cost of physically performing this
conveying of source, or (2) access to copy the
Corresponding Source from a network server at no charge.
c) Convey individual copies of the object code with a copy of the
written offer to provide the Corresponding Source. This
alternative is allowed only occasionally and noncommercially, and
only if you received the object code with such an offer, in accord
with subsection 6b.
d) Convey the object code by offering access from a designated
place (gratis or for a charge), and offer equivalent access to the
Corresponding Source in the same way through the same place at no
further charge. You need not require recipients to copy the
Corresponding Source along with the object code. If the place to
copy the object code is a network server, the Corresponding Source
may be on a different server (operated by you or a third party)
that supports equivalent copying facilities, provided you maintain
clear directions next to the object code saying where to find the
Corresponding Source. Regardless of what server hosts the
Corresponding Source, you remain obligated to ensure that it is
available for as long as needed to satisfy these requirements.
e) Convey the object code using peer-to-peer transmission, provided
you inform other peers where the object code and Corresponding
Source of the work are being offered to the general public at no
charge under subsection 6d.
A separable portion of the object code, whose source code is excluded
from the Corresponding Source as a System Library, need not be
included in conveying the object code work.
A "User Product" is either (1) a "consumer product", which means any
tangible personal property which is normally used for personal, family,
or household purposes, or (2) anything designed or sold for incorporation
into a dwelling. In determining whether a product is a consumer product,
doubtful cases shall be resolved in favor of coverage. For a particular
product received by a particular user, "normally used" refers to a
typical or common use of that class of product, regardless of the status
of the particular user or of the way in which the particular user
actually uses, or expects or is expected to use, the product. A product
is a consumer product regardless of whether the product has substantial
commercial, industrial or non-consumer uses, unless such uses represent
the only significant mode of use of the product.
"Installation Information" for a User Product means any methods,
procedures, authorization keys, or other information required to install
and execute modified versions of a covered work in that User Product from
a modified version of its Corresponding Source. The information must
suffice to ensure that the continued functioning of the modified object
code is in no case prevented or interfered with solely because
modification has been made.
If you convey an object code work under this section in, or with, or
specifically for use in, a User Product, and the conveying occurs as
part of a transaction in which the right of possession and use of the
User Product is transferred to the recipient in perpetuity or for a
fixed term (regardless of how the transaction is characterized), the
Corresponding Source conveyed under this section must be accompanied
by the Installation Information. But this requirement does not apply
if neither you nor any third party retains the ability to install
modified object code on the User Product (for example, the work has
been installed in ROM).
The requirement to provide Installation Information does not include a
requirement to continue to provide support service, warranty, or updates
for a work that has been modified or installed by the recipient, or for
the User Product in which it has been modified or installed. Access to a
network may be denied when the modification itself materially and
adversely affects the operation of the network or violates the rules and
protocols for communication across the network.
Corresponding Source conveyed, and Installation Information provided,
in accord with this section must be in a format that is publicly
documented (and with an implementation available to the public in
source code form), and must require no special password or key for
unpacking, reading or copying.
7. Additional Terms.
"Additional permissions" are terms that supplement the terms of this
License by making exceptions from one or more of its conditions.
Additional permissions that are applicable to the entire Program shall
be treated as though they were included in this License, to the extent
that they are valid under applicable law. If additional permissions
apply only to part of the Program, that part may be used separately
under those permissions, but the entire Program remains governed by
this License without regard to the additional permissions.
When you convey a copy of a covered work, you may at your option
remove any additional permissions from that copy, or from any part of
it. (Additional permissions may be written to require their own
removal in certain cases when you modify the work.) You may place
additional permissions on material, added by you to a covered work,
for which you have or can give appropriate copyright permission.
Notwithstanding any other provision of this License, for material you
add to a covered work, you may (if authorized by the copyright holders of
that material) supplement the terms of this License with terms:
a) Disclaiming warranty or limiting liability differently from the
terms of sections 15 and 16 of this License; or
b) Requiring preservation of specified reasonable legal notices or
author attributions in that material or in the Appropriate Legal
Notices displayed by works containing it; or
c) Prohibiting misrepresentation of the origin of that material, or
requiring that modified versions of such material be marked in
reasonable ways as different from the original version; or
d) Limiting the use for publicity purposes of names of licensors or
authors of the material; or
e) Declining to grant rights under trademark law for use of some
trade names, trademarks, or service marks; or
f) Requiring indemnification of licensors and authors of that
material by anyone who conveys the material (or modified versions of
it) with contractual assumptions of liability to the recipient, for
any liability that these contractual assumptions directly impose on
those licensors and authors.
All other non-permissive additional terms are considered "further
restrictions" within the meaning of section 10. If the Program as you
received it, or any part of it, contains a notice stating that it is
governed by this License along with a term that is a further
restriction, you may remove that term. If a license document contains
a further restriction but permits relicensing or conveying under this
License, you may add to a covered work material governed by the terms
of that license document, provided that the further restriction does
not survive such relicensing or conveying.
If you add terms to a covered work in accord with this section, you
must place, in the relevant source files, a statement of the
additional terms that apply to those files, or a notice indicating
where to find the applicable terms.
Additional terms, permissive or non-permissive, may be stated in the
form of a separately written license, or stated as exceptions;
the above requirements apply either way.
8. Termination.
You may not propagate or modify a covered work except as expressly
provided under this License. Any attempt otherwise to propagate or
modify it is void, and will automatically terminate your rights under
this License (including any patent licenses granted under the third
paragraph of section 11).
However, if you cease all violation of this License, then your
license from a particular copyright holder is reinstated (a)
provisionally, unless and until the copyright holder explicitly and
finally terminates your license, and (b) permanently, if the copyright
holder fails to notify you of the violation by some reasonable means
prior to 60 days after the cessation.
Moreover, your license from a particular copyright holder is
reinstated permanently if the copyright holder notifies you of the
violation by some reasonable means, this is the first time you have
received notice of violation of this License (for any work) from that
copyright holder, and you cure the violation prior to 30 days after
your receipt of the notice.
Termination of your rights under this section does not terminate the
licenses of parties who have received copies or rights from you under
this License. If your rights have been terminated and not permanently
reinstated, you do not qualify to receive new licenses for the same
material under section 10.
9. Acceptance Not Required for Having Copies.
You are not required to accept this License in order to receive or
run a copy of the Program. Ancillary propagation of a covered work
occurring solely as a consequence of using peer-to-peer transmission
to receive a copy likewise does not require acceptance. However,
nothing other than this License grants you permission to propagate or
modify any covered work. These actions infringe copyright if you do
not accept this License. Therefore, by modifying or propagating a
covered work, you indicate your acceptance of this License to do so.
10. Automatic Licensing of Downstream Recipients.
Each time you convey a covered work, the recipient automatically
receives a license from the original licensors, to run, modify and
propagate that work, subject to this License. You are not responsible
for enforcing compliance by third parties with this License.
An "entity transaction" is a transaction transferring control of an
organization, or substantially all assets of one, or subdividing an
organization, or merging organizations. If propagation of a covered
work results from an entity transaction, each party to that
transaction who receives a copy of the work also receives whatever
licenses to the work the party's predecessor in interest had or could
give under the previous paragraph, plus a right to possession of the
Corresponding Source of the work from the predecessor in interest, if
the predecessor has it or can get it with reasonable efforts.
You may not impose any further restrictions on the exercise of the
rights granted or affirmed under this License. For example, you may
not impose a license fee, royalty, or other charge for exercise of
rights granted under this License, and you may not initiate litigation
(including a cross-claim or counterclaim in a lawsuit) alleging that
any patent claim is infringed by making, using, selling, offering for
sale, or importing the Program or any portion of it.
11. Patents.
A "contributor" is a copyright holder who authorizes use under this
License of the Program or a work on which the Program is based. The
work thus licensed is called the contributor's "contributor version".
A contributor's "essential patent claims" are all patent claims
owned or controlled by the contributor, whether already acquired or
hereafter acquired, that would be infringed by some manner, permitted
by this License, of making, using, or selling its contributor version,
but do not include claims that would be infringed only as a
consequence of further modification of the contributor version. For
purposes of this definition, "control" includes the right to grant
patent sublicenses in a manner consistent with the requirements of
this License.
Each contributor grants you a non-exclusive, worldwide, royalty-free
patent license under the contributor's essential patent claims, to
make, use, sell, offer for sale, import and otherwise run, modify and
propagate the contents of its contributor version.
In the following three paragraphs, a "patent license" is any express
agreement or commitment, however denominated, not to enforce a patent
(such as an express permission to practice a patent or covenant not to
sue for patent infringement). To "grant" such a patent license to a
party means to make such an agreement or commitment not to enforce a
patent against the party.
If you convey a covered work, knowingly relying on a patent license,
and the Corresponding Source of the work is not available for anyone
to copy, free of charge and under the terms of this License, through a
publicly available network server or other readily accessible means,
then you must either (1) cause the Corresponding Source to be so
available, or (2) arrange to deprive yourself of the benefit of the
patent license for this particular work, or (3) arrange, in a manner
consistent with the requirements of this License, to extend the patent
license to downstream recipients. "Knowingly relying" means you have
actual knowledge that, but for the patent license, your conveying the
covered work in a country, or your recipient's use of the covered work
in a country, would infringe one or more identifiable patents in that
country that you have reason to believe are valid.
If, pursuant to or in connection with a single transaction or
arrangement, you convey, or propagate by procuring conveyance of, a
covered work, and grant a patent license to some of the parties
receiving the covered work authorizing them to use, propagate, modify
or convey a specific copy of the covered work, then the patent license
you grant is automatically extended to all recipients of the covered
work and works based on it.
A patent license is "discriminatory" if it does not include within
the scope of its coverage, prohibits the exercise of, or is
conditioned on the non-exercise of one or more of the rights that are
specifically granted under this License. You may not convey a covered
work if you are a party to an arrangement with a third party that is
in the business of distributing software, under which you make payment
to the third party based on the extent of your activity of conveying
the work, and under which the third party grants, to any of the
parties who would receive the covered work from you, a discriminatory
patent license (a) in connection with copies of the covered work
conveyed by you (or copies made from those copies), or (b) primarily
for and in connection with specific products or compilations that
contain the covered work, unless you entered into that arrangement,
or that patent license was granted, prior to 28 March 2007.
Nothing in this License shall be construed as excluding or limiting
any implied license or other defenses to infringement that may
otherwise be available to you under applicable patent law.
12. No Surrender of Others' Freedom.
If conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot convey a
covered work so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you may
not convey it at all. For example, if you agree to terms that obligate you
to collect a royalty for further conveying from those to whom you convey
the Program, the only way you could satisfy both those terms and this
License would be to refrain entirely from conveying the Program.
13. Use with the GNU Affero General Public License.
Notwithstanding any other provision of this License, you have
permission to link or combine any covered work with a work licensed
under version 3 of the GNU Affero General Public License into a single
combined work, and to convey the resulting work. The terms of this
License will continue to apply to the part which is the covered work,
but the special requirements of the GNU Affero General Public License,
section 13, concerning interaction through a network will apply to the
combination as such.
14. Revised Versions of this License.
The Free Software Foundation may publish revised and/or new versions of
the GNU General Public License from time to time. Such new versions will
be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the
Program specifies that a certain numbered version of the GNU General
Public License "or any later version" applies to it, you have the
option of following the terms and conditions either of that numbered
version or of any later version published by the Free Software
Foundation. If the Program does not specify a version number of the
GNU General Public License, you may choose any version ever published
by the Free Software Foundation.
If the Program specifies that a proxy can decide which future
versions of the GNU General Public License can be used, that proxy's
public statement of acceptance of a version permanently authorizes you
to choose that version for the Program.
Later license versions may give you additional or different
permissions. However, no additional obligations are imposed on any
author or copyright holder as a result of your choosing to follow a
later version.
15. Disclaimer of Warranty.
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
16. Limitation of Liability.
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES.
17. Interpretation of Sections 15 and 16.
If the disclaimer of warranty and limitation of liability provided
above cannot be given local legal effect according to their terms,
reviewing courts shall apply local law that most closely approximates
an absolute waiver of all civil liability in connection with the
Program, unless a warranty or assumption of liability accompanies a
copy of the Program in return for a fee.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
state the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
Copyright (C)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
Also add information on how to contact you by electronic and paper mail.
If the program does terminal interaction, make it output a short
notice like this when it starts in an interactive mode:
Copyright (C)
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
.
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
.
jnr-x86asm-0.1/.gitignore 0000755 0001750 0001750 00000000130 11425031554 015212 0 ustar twerner twerner !.gitignore
*.gz
*.zip
*.md5
*.sha1
*~
*.orig
*.rej
build
dist
target
nbproject/private
jnr-x86asm-0.1/COPYING.ASMJIT 0000644 0001750 0001750 00000002344 11425031554 015251 0 ustar twerner twerner While jnr-x86asm is covered under the LGPL version 3, it is based
on code from the AsmJit project, and that copyright is reproduced below.
Copyright (c) 2008-2009, Petr Kobalicek
Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use,
copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following
conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
jnr-x86asm-0.1/nbproject/ 0000755 0001750 0001750 00000000000 11425031554 015213 5 ustar twerner twerner jnr-x86asm-0.1/nbproject/project.xml 0000644 0001750 0001750 00000000767 11425031554 017415 0 ustar twerner twerner
org.netbeans.modules.java.j2seprojectjnr-x86asm
jnr-x86asm-0.1/nbproject/project.properties 0000644 0001750 0001750 00000003720 11425031554 021001 0 ustar twerner twerner application.title=jnr-x86asm
application.vendor=wayne
build.classes.dir=${build.dir}/classes
build.classes.excludes=**/*.java,**/*.form
# This directory is removed when the project is cleaned:
build.dir=build
build.generated.dir=${build.dir}/generated
build.generated.sources.dir=${build.dir}/generated-sources
# Only compile against the classpath explicitly listed here:
build.sysclasspath=ignore
build.test.classes.dir=${build.dir}/test/classes
build.test.results.dir=${build.dir}/test/results
# Uncomment to specify the preferred debugger connection transport:
#debug.transport=dt_socket
debug.classpath=\
${run.classpath}
debug.test.classpath=\
${run.test.classpath}
# This directory is removed when the project is cleaned:
dist.dir=dist
dist.jar=${dist.dir}/jnr-x86asm.jar
dist.javadoc.dir=${dist.dir}/javadoc
endorsed.classpath=
excludes=
includes=**
jar.compress=true
javac.classpath=
# Space-separated list of extra javac options
javac.compilerargs=
javac.deprecation=false
javac.source=1.5
javac.target=1.5
javac.test.classpath=\
${javac.classpath}:\
${build.classes.dir}:\
${libs.junit.classpath}:\
${libs.junit_4.classpath}
javadoc.additionalparam=
javadoc.author=false
javadoc.encoding=${source.encoding}
javadoc.noindex=false
javadoc.nonavbar=false
javadoc.notree=false
javadoc.private=false
javadoc.splitindex=true
javadoc.use=true
javadoc.version=false
javadoc.windowtitle=
jaxbwiz.endorsed.dirs="${netbeans.home}/../ide12/modules/ext/jaxb/api"
meta.inf.dir=${src.dir}/META-INF
platform.active=default_platform
run.classpath=\
${javac.classpath}:\
${build.classes.dir}
# Space-separated list of JVM arguments used when running the project
# (you may also define separate properties like run-sys-prop.name=value instead of -Dname=value
# or test-sys-prop.name=value to set system properties for unit tests):
run.jvmargs=
run.test.classpath=\
${javac.test.classpath}:\
${build.test.classes.dir}
source.encoding=UTF-8
src.dir=src
test.src.dir=test
jnr-x86asm-0.1/nbproject/genfiles.properties 0000644 0001750 0001750 00000000723 11425031554 021127 0 ustar twerner twerner build.xml.data.CRC32=71726615
build.xml.script.CRC32=798cf52a
build.xml.stylesheet.CRC32=958a1d3e@1.32.1.45
# This file is used by a NetBeans-based IDE to track changes in generated files such as build-impl.xml.
# Do not edit this file. You may delete it but then the IDE will never regenerate such files for you.
nbproject/build-impl.xml.data.CRC32=71726615
nbproject/build-impl.xml.script.CRC32=acc18bb5
nbproject/build-impl.xml.stylesheet.CRC32=576378a2@1.32.1.45
jnr-x86asm-0.1/nbproject/build-impl.xml 0000644 0001750 0001750 00000122710 11425031554 017776 0 ustar twerner twerner
Must set src.dirMust set test.src.dirMust set build.dirMust set dist.dirMust set build.classes.dirMust set dist.javadoc.dirMust set build.test.classes.dirMust set build.test.results.dirMust set build.classes.excludesMust set dist.jarMust set javac.includesMust select some files in the IDE or set javac.includesTo run this application from the command line without Ant, try:java -cp "${run.classpath.with.dist.jar}" ${main.class}To run this application from the command line without Ant, try:java -jar "${dist.jar.resolved}"Must select one file in the IDE or set run.classMust select one file in the IDE or set run.classMust select one file in the IDE or set debug.classMust select one file in the IDE or set debug.classMust set fix.includesMust select some files in the IDE or set javac.includesSome tests failed; see details above.Must select some files in the IDE or set test.includesSome tests failed; see details above.Must select one file in the IDE or set test.classMust select one file in the IDE or set applet.urlMust select one file in the IDE or set applet.url
jnr-x86asm-0.1/src/ 0000755 0001750 0001750 00000000000 11425031554 014014 5 ustar twerner twerner jnr-x86asm-0.1/src/com/ 0000755 0001750 0001750 00000000000 11425031554 014572 5 ustar twerner twerner jnr-x86asm-0.1/src/com/kenai/ 0000755 0001750 0001750 00000000000 11425031554 015661 5 ustar twerner twerner jnr-x86asm-0.1/src/com/kenai/jnr/ 0000755 0001750 0001750 00000000000 11425031554 016452 5 ustar twerner twerner jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/ 0000755 0001750 0001750 00000000000 11425031554 017600 5 ustar twerner twerner jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/InstructionGroup.java 0000644 0001750 0001750 00000007566 11425031554 024017 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
public enum InstructionGroup {
I_EMIT,
I_ALU,
I_BSWAP,
I_BT,
I_CALL,
I_CRC32,
I_ENTER,
I_IMUL,
I_INC_DEC,
I_J,
I_JMP,
I_LEA,
I_M,
I_MOV,
I_MOV_PTR,
I_MOVSX_MOVZX,
I_MOVSXD,
I_PUSH, // I_PUSH is implemented before I_POP
I_POP,
I_R_RM,
I_RM_B,
I_RM,
I_RM_R,
I_RET,
I_ROT,
I_SHLD_SHRD,
I_TEST,
I_XCHG,
// Group for x87 FP instructions in format mem or st(i), st(i) (fadd, fsub, fdiv, ...)
I_X87_FPU,
// Group for x87 FP instructions in format st(i), st(i)
I_X87_STI,
// Group for fld/fst/fstp instruction, internally uses I_X87_MEM group.
I_X87_MEM_STI,
// Group for x87 FP instructions that uses Word, DWord, QWord or TWord memory pointer.
I_X87_MEM,
// Group for x87 FSTSW/FNSTSW instructions
I_X87_FSTSW,
// Group for movbe instruction
I_MOVBE,
// Group for MMX/SSE instructions in format (X)MM|Reg|Mem <- (X)MM|Reg|Mem,
// 0x66 prefix must be set manually in opcodes.
// - Primary opcode is used for instructions in (X)MM <- (X)MM/Mem format,
// - Secondary opcode is used for instructions in (X)MM/Mem <- (X)MM format.
I_MMU_MOV,
// Group for movd and movq instructions.
I_MMU_MOVD,
I_MMU_MOVQ,
// Group for pextrd, pextrq and pextrw instructions (it's special instruction
// not similar to others)
I_MMU_PEXTR,
// Group for prefetch instruction
I_MMU_PREFETCH,
// Group for MMX/SSE instructions in format (X)MM|Reg <- (X)MM|Reg|Mem|Imm,
// 0x66 prefix is added for MMX instructions that used by SSE2 registers.
// - Primary opcode is used for instructions in (X)MM|Reg <- (X)MM|Reg|Mem format,
// - Secondary opcode is iused for instructions in (X)MM|Reg <- Imm format.
I_MMU_RMI,
I_MMU_RM_IMM8,
// Group for 3dNow instructions
I_MMU_RM_3DNOW;
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/Asm.java 0000644 0001750 0001750 00000065726 11425031554 021203 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
import static com.kenai.jnr.x86asm.REG.*;
import static com.kenai.jnr.x86asm.SIZE.*;
public final class Asm {
private Asm() {}
/** @deprecated Use {@link #X86_32} */
@Deprecated
public static final CPU I386 = CPU.I386;
public static final CPU X86_32 = CPU.X86_32;
public static final CPU X86_64 = CPU.X86_64;
/** No register, can be used only in @c Mem operand. */
public static final Register no_reg = new Register(NO_REG, 0);
/** 8 bit General purpose register. */
public static final Register al = Register.gpr(REG_AL);
/** 8 bit General purpose register. */
public static final Register cl = Register.gpr(REG_CL);
/** 8 bit General purpose register. */
public static final Register dl = Register.gpr(REG_DL);
/** 8 bit General purpose register. */
public static final Register bl = Register.gpr(REG_BL);
/** 8 bit General purpose register. */
public static final Register ah = Register.gpr(REG_AH);
/** 8 bit General purpose register. */
public static final Register ch = Register.gpr(REG_CH);
/** 8 bit General purpose register. */
public static final Register dh = Register.gpr(REG_DH);
/** 8 bit General purpose register. */
public static final Register bh = Register.gpr(REG_BH);
/** 8 bit General purpose register (64 bit mode only). */
public static final Register r8b = Register.gpr(REG_R8B);
/** 8 bit General purpose register (64 bit mode only). */
public static final Register r9b = Register.gpr(REG_R9B);
/** 8 bit General purpose register (64 bit mode only). */
public static final Register r10b = Register.gpr(REG_R10B);
/** 8 bit General purpose register (64 bit mode only). */
public static final Register r11b = Register.gpr(REG_R11B);
/** 8 bit General purpose register (64 bit mode only). */
public static final Register r12b = Register.gpr(REG_R12B);
/** 8 bit General purpose register (64 bit mode only). */
public static final Register r13b = Register.gpr(REG_R13B);
/** 8 bit General purpose register (64 bit mode only). */
public static final Register r14b = Register.gpr(REG_R14B);
/** 8 bit General purpose register (64 bit mode only). */
public static final Register r15b = Register.gpr(REG_R15B);
/** 16 bit General purpose register. */
public static final Register ax = Register.gpr(REG_AX);
/** 16 bit General purpose register. */
public static final Register cx = Register.gpr(REG_CX);
/** 16 bit General purpose register. */
public static final Register dx = Register.gpr(REG_DX);
/** 16 bit General purpose register. */
public static final Register bx = Register.gpr(REG_BX);
/** 16 bit General purpose register. */
public static final Register sp = Register.gpr(REG_SP);
/** 16 bit General purpose register. */
public static final Register bp = Register.gpr(REG_BP);
/** 16 bit General purpose register. */
public static final Register si = Register.gpr(REG_SI);
/** 16 bit General purpose register. */
public static final Register di = Register.gpr(REG_DI);
/** 16 bit General purpose register (64 bit mode only). */
public static final Register r8w = Register.gpr(REG_R8W);
/** 16 bit General purpose register (64 bit mode only). */
public static final Register r9w = Register.gpr(REG_R9W);
/** 16 bit General purpose register (64 bit mode only). */
public static final Register r10w = Register.gpr(REG_R10W);
/** 16 bit General purpose register (64 bit mode only). */
public static final Register r11w = Register.gpr(REG_R11W);
/** 16 bit General purpose register (64 bit mode only). */
public static final Register r12w = Register.gpr(REG_R12W);
/** 16 bit General purpose register (64 bit mode only). */
public static final Register r13w = Register.gpr(REG_R13W);
/** 16 bit General purpose register (64 bit mode only). */
public static final Register r14w = Register.gpr(REG_R14W);
/** 16 bit General purpose register (64 bit mode only). */
public static final Register r15w = Register.gpr(REG_R15W);
/** 32 bit General purpose register. */
public static final Register eax = Register.gpr(REG_EAX);
/** 32 bit General purpose register. */
public static final Register ecx = Register.gpr(REG_ECX);
/** 32 bit General purpose register. */
public static final Register edx = Register.gpr(REG_EDX);
/** 32 bit General purpose register. */
public static final Register ebx = Register.gpr(REG_EBX);
/** 32 bit General purpose register. */
public static final Register esp = Register.gpr(REG_ESP);
/** 32 bit General purpose register. */
public static final Register ebp = Register.gpr(REG_EBP);
/** 32 bit General purpose register. */
public static final Register esi = Register.gpr(REG_ESI);
/** 32 bit General purpose register. */
public static final Register edi = Register.gpr(REG_EDI);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register rax = Register.gpr(REG_RAX);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register rcx = Register.gpr(REG_RCX);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register rdx = Register.gpr(REG_RDX);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register rbx = Register.gpr(REG_RBX);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register rsp = Register.gpr(REG_RSP);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register rbp = Register.gpr(REG_RBP);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register rsi = Register.gpr(REG_RSI);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register rdi = Register.gpr(REG_RDI);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register r8 = Register.gpr(REG_R8);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register r9 = Register.gpr(REG_R9);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register r10 = Register.gpr(REG_R10);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register r11 = Register.gpr(REG_R11);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register r12 = Register.gpr(REG_R12);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register r13 = Register.gpr(REG_R13);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register r14 = Register.gpr(REG_R14);
/** 64 bit General purpose register (64 bit mode only). */
public static final Register r15 = Register.gpr(REG_R15);
/** 64 bit MMX register. */
public static final MMRegister mm0 = MMRegister.mm(0);
/** 64 bit MMX register. */
public static final MMRegister mm1 = MMRegister.mm(1);
/** 64 bit MMX register. */
public static final MMRegister mm2 = MMRegister.mm(2);
/** 64 bit MMX register. */
public static final MMRegister mm3 = MMRegister.mm(3);
/** 64 bit MMX register. */
public static final MMRegister mm4 = MMRegister.mm(4);
/** 64 bit MMX register. */
public static final MMRegister mm5 = MMRegister.mm(5);
/** 64 bit MMX register. */
public static final MMRegister mm6 = MMRegister.mm(6);
/** 64 bit MMX register. */
public static final MMRegister mm7 = MMRegister.mm(7);
/** 128 bit SSE register. */
public static final XMMRegister xmm0 = XMMRegister.xmm(0);
/** 128 bit SSE register. */
public static final XMMRegister xmm1 = XMMRegister.xmm(1);
/** 128 bit SSE register. */
public static final XMMRegister xmm2 = XMMRegister.xmm(2);
/** 128 bit SSE register. */
public static final XMMRegister xmm3 = XMMRegister.xmm(3);
/** 128 bit SSE register. */
public static final XMMRegister xmm4 = XMMRegister.xmm(4);
/** 128 bit SSE register. */
public static final XMMRegister xmm5 = XMMRegister.xmm(5);
/** 128 bit SSE register. */
public static final XMMRegister xmm6 = XMMRegister.xmm(6);
/** 128 bit SSE register. */
public static final XMMRegister xmm7 = XMMRegister.xmm(7);
/** 128 bit SSE register (64 bit mode only). */
public static final XMMRegister xmm8 = XMMRegister.xmm(8);
/** 128 bit SSE register (64 bit mode only). */
public static final XMMRegister xmm9 = XMMRegister.xmm(9);
/** 128 bit SSE register (64 bit mode only). */
public static final XMMRegister xmm10 = XMMRegister.xmm(10);
/** 128 bit SSE register (64 bit mode only). */
public static final XMMRegister xmm11 = XMMRegister.xmm(11);
/** 128 bit SSE register (64 bit mode only). */
public static final XMMRegister xmm12 = XMMRegister.xmm(12);
/** 128 bit SSE register (64 bit mode only). */
public static final XMMRegister xmm13 = XMMRegister.xmm(13);
/** 128 bit SSE register (64 bit mode only). */
public static final XMMRegister xmm14 = XMMRegister.xmm(14);
/** 128 bit SSE register (64 bit mode only). */
public static final XMMRegister xmm15 = XMMRegister.xmm(15);
static final Mem _ptr_build(Label label, long disp, int ptrSize) {
return new Mem(label, disp, ptrSize);
}
static final Mem _ptr_build(Label label, Register index, int shift, long disp, int ptrSize) {
return new Mem(label, index, shift, disp, ptrSize);
}
/** Absolute addressing */
static final Mem _ptr_build_abs(long target, long disp, SEGMENT segmentPrefix, int ptrSize) {
return new Mem(target, disp, segmentPrefix, ptrSize);
}
static final Mem _ptr_build_abs(long target, Register index, int shift, long disp, SEGMENT segmentPrefix, int ptrSize) {
return new Mem(target, index, shift, segmentPrefix, disp, ptrSize);
}
static final Mem _ptr_build(Register base, long disp, int ptrSize) {
return new Mem(base, disp, ptrSize);
}
static final Mem _ptr_build(Register base, Register index, int shift, long disp, int ptrSize) {
return new Mem(base, index, shift, disp, ptrSize);
}
// ============================================================================
// [AsmJit::Mem - ptr[displacement]]
// ============================================================================
/** Create pointer operand with not specified size. */
public static final Mem ptr(Label label, long disp) {
return _ptr_build(label, disp, 0);
}
/** Create pointer operand with not specified size. */
public static final Mem ptr(Label label) {
return _ptr_build(label, 0, 0);
}
/**Create byte pointer operand. */
public static final Mem byte_ptr(Label label, long disp) {
return _ptr_build(label, disp, SIZE_BYTE);
}
/**Create byte pointer operand. */
public static final Mem byte_ptr(Label label) {
return _ptr_build(label, 0, SIZE_BYTE);
}
/** Create word (2 Bytes) pointer operand. */
public static final Mem word_ptr(Label label, long disp) {
return _ptr_build(label, disp, SIZE_WORD);
}
/** Create word (2 Bytes) pointer operand. */
public static final Mem word_ptr(Label label) {
return _ptr_build(label, 0, SIZE_WORD);
}
/** Create dword (4 Bytes) pointer operand. */
public static final Mem dword_ptr(Label label, long disp) {
return _ptr_build(label, disp, SIZE_DWORD);
}
/** Create dword (4 Bytes) pointer operand. */
public static final Mem dword_ptr(Label label) {
return _ptr_build(label, 0, SIZE_DWORD);
}
/** Create qword (8 Bytes) pointer operand. */
public static final Mem qword_ptr(Label label, long disp) {
return _ptr_build(label, disp, SIZE_QWORD);
}
/** Create qword (8 Bytes) pointer operand. */
public static final Mem qword_ptr(Label label) {
return _ptr_build(label, 0, SIZE_QWORD);
}
/** Create tword (10 Bytes) pointer operand (used for 80 bit floating points). */
public static final Mem tword_ptr(Label label, long disp) {
return _ptr_build(label, disp, SIZE_TWORD);
}
/** Create tword (10 Bytes) pointer operand (used for 80 bit floating points). */
public static final Mem tword_ptr(Label label) {
return _ptr_build(label, 0, SIZE_TWORD);
}
/** Create dqword (16 Bytes) pointer operand. */
public static final Mem dqword_ptr(Label label, long disp) {
return _ptr_build(label, disp, SIZE_DQWORD);
}
/** Create dqword (16 Bytes) pointer operand. */
public static final Mem dqword_ptr(Label label) {
return _ptr_build(label, 0, SIZE_DQWORD);
}
/**
* Create mmword (8 bytes) pointer operand
*
* Note:This constructor is provided only for convenience for mmx programming.
*/
public static final Mem mmword_ptr(Label label, long disp) {
return _ptr_build(label, disp, SIZE_QWORD);
}
/**
* Create mmword (8 bytes) pointer operand
*
* Note:This constructor is provided only for convenience for mmx programming.
*/
public static final Mem mmword_ptr(Label label) {
return _ptr_build(label, 0, SIZE_QWORD);
}
/** Create xmmword (16 bytes) pointer operand
//!
//! @note This constructor is provided only for convenience for sse programming. */
public static final Mem xmmword_ptr(Label label, long disp) {
return _ptr_build(label, disp, SIZE_DQWORD);
}
/** Create xmmword (16 bytes) pointer operand
//!
//! @note This constructor is provided only for convenience for sse programming. */
public static final Mem xmmword_ptr(Label label) {
return _ptr_build(label, 0, SIZE_DQWORD);
}
/** Create pointer operand with not specified size. */
public static final Mem ptr(Label label, Register index, int shift, long disp) {
return _ptr_build(label, index, shift, disp, 0);
}
/** Create byte pointer operand. */
public static final Mem byte_ptr(Label label, Register index, int shift, long disp) {
return _ptr_build(label, index, shift, disp, SIZE_BYTE);
}
/** Create word (2 Bytes) pointer operand. */
public static final Mem word_ptr(Label label, Register index, int shift, long disp) {
return _ptr_build(label, index, shift, disp, SIZE_WORD);
}
/** Create dword (4 Bytes) pointer operand. */
public static final Mem dword_ptr(Label label, Register index, int shift, long disp) {
return _ptr_build(label, index, shift, disp, SIZE_DWORD);
}
/** Create qword (8 Bytes) pointer operand. */
public static final Mem qword_ptr(Label label, Register index, int shift, long disp) {
return _ptr_build(label, index, shift, disp, SIZE_QWORD);
}
/** Create tword (10 Bytes) pointer operand (used for 80 bit floating points). */
public static final Mem tword_ptr(Label label, Register index, int shift, long disp) {
return _ptr_build(label, index, shift, disp, SIZE_TWORD);
}
/** Create dqword (16 Bytes) pointer operand. */
public static final Mem dqword_ptr(Label label, Register index, int shift, long disp) {
return _ptr_build(label, index, shift, disp, SIZE_DQWORD);
}
/** Create mmword (8 bytes) pointer operand
//!
//! @note This constructor is provided only for convenience for mmx programming. */
public static final Mem mmword_ptr(Label label, Register index, int shift, long disp) {
return _ptr_build(label, index, shift, disp, SIZE_QWORD);
}
/** Create xmmword (16 bytes) pointer operand
//!
//! @note This constructor is provided only for convenience for sse programming. */
public static final Mem xmmword_ptr(Label label, Register index, int shift, long disp) {
return _ptr_build(label, index, shift, disp, SIZE_DQWORD);
}
/** Create pointer operand with not specified size. */
public static final Mem ptr_abs(long target, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, disp, segmentPrefix, 0);
}
/** Create byte pointer operand. */
public static final Mem byte_ptr_abs(long target, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, disp, segmentPrefix, SIZE_BYTE);
}
/** Create word (2 Bytes) pointer operand. */
public static final Mem word_ptr_abs(long target, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, disp, segmentPrefix, SIZE_WORD);
}
/** Create dword (4 Bytes) pointer operand. */
public static final Mem dword_ptr_abs(long target, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, disp, segmentPrefix, SIZE_DWORD);
}
/** Create qword (8 Bytes) pointer operand. */
public static final Mem qword_ptr_abs(long target, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, disp, segmentPrefix, SIZE_QWORD);
}
/** Create tword (10 Bytes) pointer operand (used for 80 bit floating points). */
public static final Mem tword_ptr_abs(long target, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, disp, segmentPrefix, SIZE_TWORD);
}
/** Create dqword (16 Bytes) pointer operand. */
public static final Mem dqword_ptr_abs(long target, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, disp, segmentPrefix, SIZE_DQWORD);
}
/** Create mmword (8 bytes) pointer operand
//!
//! @note This constructor is provided only for convenience for mmx programming. */
public static final Mem mmword_ptr_abs(long target, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, disp, segmentPrefix, SIZE_QWORD);
}
/** Create xmmword (16 bytes) pointer operand
//!
//! @note This constructor is provided only for convenience for sse programming. */
public static final Mem xmmword_ptr_abs(long target, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, disp, segmentPrefix, SIZE_DQWORD);
}
/** Create pointer operand with not specified size. */
public static final Mem ptr_abs(long target, Register index, int shift, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, index, shift, disp, segmentPrefix, 0);
}
/** Create byte pointer operand. */
public static final Mem byte_ptr_abs(long target, Register index, int shift, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, index, shift, disp, segmentPrefix, SIZE_BYTE);
}
/** Create word (2 Bytes) pointer operand. */
public static final Mem word_ptr_abs(long target, Register index, int shift, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, index, shift, disp, segmentPrefix, SIZE_WORD);
}
/** Create dword (4 Bytes) pointer operand. */
public static final Mem dword_ptr_abs(long target, Register index, int shift, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, index, shift, disp, segmentPrefix, SIZE_DWORD);
}
/** Create qword (8 Bytes) pointer operand. */
public static final Mem qword_ptr_abs(long target, Register index, int shift, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, index, shift, disp, segmentPrefix, SIZE_QWORD);
}
/** Create tword (10 Bytes) pointer operand (used for 80 bit floating points). */
public static final Mem tword_ptr_abs(long target, Register index, int shift, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, index, shift, disp, segmentPrefix, SIZE_TWORD);
}
/** Create dqword (16 Bytes) pointer operand. */
public static final Mem dqword_ptr_abs(long target, Register index, int shift, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, index, shift, disp, segmentPrefix, SIZE_DQWORD);
}
/** Create mmword (8 bytes) pointer operand
//!
//! @note This constructor is provided only for convenience for mmx programming. */
public static final Mem mmword_ptr_abs(long target, Register index, int shift, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, index, shift, disp, segmentPrefix, SIZE_QWORD);
}
/** Create xmmword (16 bytes) pointer operand
//!
//! @note This constructor is provided only for convenience for sse programming. */
public static final Mem xmmword_ptr_abs(long target, Register index, int shift, long disp, SEGMENT segmentPrefix) {
return _ptr_build_abs(target, index, shift, disp, segmentPrefix, SIZE_DQWORD);
}
// ============================================================================
// [AsmJit::Mem - ptr[base + displacement]]
// ============================================================================
/** Create pointer operand with not specified size. */
public static final Mem ptr(Register base, long disp) {
return _ptr_build(base, disp, 0);
}
/** Create byte pointer operand. */
public static final Mem byte_ptr(Register base, long disp) {
return _ptr_build(base, disp, SIZE_BYTE);
}
/** Create word (2 Bytes) pointer operand. */
public static final Mem word_ptr(Register base, long disp) {
return _ptr_build(base, disp, SIZE_WORD);
}
/** Create dword (4 Bytes) pointer operand. */
public static final Mem dword_ptr(Register base, long disp) {
return _ptr_build(base, disp, SIZE_DWORD);
}
/** Create qword (8 Bytes) pointer operand. */
public static final Mem qword_ptr(Register base, long disp) {
return _ptr_build(base, disp, SIZE_QWORD);
}
/** Create tword (10 Bytes) pointer operand (used for 80 bit floating points). */
public static final Mem tword_ptr(Register base, long disp) {
return _ptr_build(base, disp, SIZE_TWORD);
}
/** Create dqword (16 Bytes) pointer operand. */
public static final Mem dqword_ptr(Register base, long disp) {
return _ptr_build(base, disp, SIZE_DQWORD);
}
/** Create mmword (8 bytes) pointer operand
//!
//! @note This constructor is provided only for convenience for mmx programming. */
public static final Mem mmword_ptr(Register base, long disp) {
return _ptr_build(base, disp, SIZE_QWORD);
}
/** Create xmmword (16 bytes) pointer operand
//!
//! @note This constructor is provided only for convenience for sse programming. */
public static final Mem xmmword_ptr(Register base, long disp) {
return _ptr_build(base, disp, SIZE_DQWORD);
}
// ============================================================================
// [AsmJit::Mem - ptr[base + (index << shift) + displacement]]
// ============================================================================
/** Create pointer operand with not specified size. */
public static final Mem ptr(Register base, Register index, int shift, long disp) {
return _ptr_build(base, index, shift, disp, 0);
}
/** Create byte pointer operand. */
public static final Mem byte_ptr(Register base, Register index, int shift, long disp) {
return _ptr_build(base, index, shift, disp, SIZE_BYTE);
}
/** Create word (2 Bytes) pointer operand. */
public static final Mem word_ptr(Register base, Register index, int shift, long disp) {
return _ptr_build(base, index, shift, disp, SIZE_WORD);
}
/** Create dword (4 Bytes) pointer operand. */
public static final Mem dword_ptr(Register base, Register index, int shift, long disp) {
return _ptr_build(base, index, shift, disp, SIZE_DWORD);
}
/** Create qword (8 Bytes) pointer operand. */
public static final Mem qword_ptr(Register base, Register index, int shift, long disp) {
return _ptr_build(base, index, shift, disp, SIZE_QWORD);
}
/** Create tword (10 Bytes) pointer operand (used for 80 bit floating points). */
public static final Mem tword_ptr(Register base, Register index, int shift, long disp) {
return _ptr_build(base, index, shift, disp, SIZE_TWORD);
}
/** Create dqword (16 Bytes) pointer operand. */
public static final Mem dqword_ptr(Register base, Register index, int shift, long disp) {
return _ptr_build(base, index, shift, disp, SIZE_DQWORD);
}
/** Create mmword (8 Bytes) pointer operand).
//!
//! @note This constructor is provided only for convenience for mmx programming. */
public static final Mem mmword_ptr(Register base, Register index, int shift, long disp) {
return _ptr_build(base, index, shift, disp, SIZE_QWORD);
}
/** Create xmmword (16 Bytes) pointer operand.
//!
//! @note This constructor is provided only for convenience for sse programming. */
public static final Mem xmmword_ptr(Register base, Register index, int shift, long disp) {
return _ptr_build(base, index, shift, disp, SIZE_DQWORD);
}
public static final Immediate imm(long value) {
return Immediate.imm(value);
}
public static final Immediate uimm(long value) {
return Immediate.imm(value);
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/Logger.java 0000644 0001750 0001750 00000001551 11425031554 021664 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
package com.kenai.jnr.x86asm;
/**
* Simple wrapper around logging
*/
public class Logger {
public void log(String msg) {}
public void logAlign(long m) {}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/SerializerIntrinsics.java 0000644 0001750 0001750 00000567337 11425031554 024647 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
import static com.kenai.jnr.x86asm.INST_CODE.*;
import static com.kenai.jnr.x86asm.REG.*;
/**
* Assembler instruction serializer.
*/
public abstract class SerializerIntrinsics extends SerializerCore {
// -------------------------------------------------------------------------
// [Embed]
// -------------------------------------------------------------------------
// public final void db(UInt8 x) ASMJIT_NOTHROW { _embed(&x, 1); }
// public final void dw(UInt16 x) ASMJIT_NOTHROW { _embed(&x, 2); }
// public final void dd(UInt32 x) ASMJIT_NOTHROW { _embed(&x, 4); }
// public final void dq(UInt64 x) ASMJIT_NOTHROW { _embed(&x, 8); }
//
// public final void dint8(Int8 x) ASMJIT_NOTHROW { _embed(&x, sizeof(Int8)); }
// public final void duint8(UInt8 x) ASMJIT_NOTHROW { _embed(&x, sizeof(UInt8)); }
//
// public final void dint16(Int16 x) ASMJIT_NOTHROW { _embed(&x, sizeof(Int16)); }
// public final void duint16(UInt16 x) ASMJIT_NOTHROW { _embed(&x, sizeof(UInt16)); }
//
// public final void dint32(Int32 x) ASMJIT_NOTHROW { _embed(&x, sizeof(Int32)); }
// public final void duint32(UInt32 x) ASMJIT_NOTHROW { _embed(&x, sizeof(UInt32)); }
//
// public final void dint64(Int64 x) ASMJIT_NOTHROW { _embed(&x, sizeof(Int64)); }
// public final void duint64(UInt64 x) ASMJIT_NOTHROW { _embed(&x, sizeof(UInt64)); }
//
// public final void dsysint(SysInt x) ASMJIT_NOTHROW { _embed(&x, sizeof(SysInt)); }
// public final void dsysuint(SysUInt x) ASMJIT_NOTHROW { _embed(&x, sizeof(SysUInt)); }
//
// public final void dfloat(float x) ASMJIT_NOTHROW { _embed(&x, sizeof(float)); }
// public final void ddouble(double x) ASMJIT_NOTHROW { _embed(&x, sizeof(double)); }
//
// public final void dptr(void* x) ASMJIT_NOTHROW { _embed(&x, sizeof(void*)); }
//
// public final void dmm(const MMData& x) ASMJIT_NOTHROW { _embed(&x, sizeof(MMData)); }
// public final void dxmm(const XMMData& x) ASMJIT_NOTHROW { _embed(&x, sizeof(XMMData)); }
//
// public final void data(const void* data, SysUInt size) ASMJIT_NOTHROW { _embed(data, size); }
//
// template
// public final void dstruct(const T& x) ASMJIT_NOTHROW { _embed(&x, sizeof(T)); }
// -------------------------------------------------------------------------
// [X86 Instructions]
// -------------------------------------------------------------------------
/** Add with Carry. */
public final void adc(Register dst, Register src)
{
emitX86(INST_ADC, dst, src);
}
/** Add with Carry. */
public final void adc(Register dst, Mem src)
{
emitX86(INST_ADC, dst, src);
}
/** Add with Carry. */
public final void adc(Register dst, Immediate src)
{
emitX86(INST_ADC, dst, src);
}
/** Add with Carry. */
public final void adc(Mem dst, Register src)
{
emitX86(INST_ADC, dst, src);
}
/** Add with Carry. */
public final void adc(Mem dst, Immediate src)
{
emitX86(INST_ADC, dst, src);
}
/** Add. */
public final void add(Register dst, Register src)
{
emitX86(INST_ADD, dst, src);
}
/** Add. */
public final void add(Register dst, Mem src)
{
emitX86(INST_ADD, dst, src);
}
/** Add. */
public final void add(Register dst, Immediate src)
{
emitX86(INST_ADD, dst, src);
}
/** Add. */
public final void add(Mem dst, Register src)
{
emitX86(INST_ADD, dst, src);
}
/** Add. */
public final void add(Mem dst, Immediate src)
{
emitX86(INST_ADD, dst, src);
}
/** Logical And. */
public final void and_(Register dst, Register src)
{
emitX86(INST_AND, dst, src);
}
/** Logical And. */
public final void and_(Register dst, Mem src)
{
emitX86(INST_AND, dst, src);
}
/** Logical And. */
public final void and_(Register dst, Immediate src)
{
emitX86(INST_AND, dst, src);
}
/** Logical And. */
public final void and_(Mem dst, Register src)
{
emitX86(INST_AND, dst, src);
}
/** Logical And. */
public final void and_(Mem dst, Immediate src)
{
emitX86(INST_AND, dst, src);
}
/** Bit Scan Forward. */
public final void bsf(Register dst, Register src)
{
assert(!dst.isRegType(REG_GPB));
emitX86(INST_BSF, dst, src);
}
/** Bit Scan Forward. */
public final void bsf(Register dst, Mem src)
{
assert(!dst.isRegType(REG_GPB));
emitX86(INST_BSF, dst, src);
}
/** Bit Scan Reverse. */
public final void bsr(Register dst, Register src)
{
assert(!dst.isRegType(REG_GPB));
emitX86(INST_BSR, dst, src);
}
/** Bit Scan Reverse. */
public final void bsr(Register dst, Mem src)
{
assert(!dst.isRegType(REG_GPB));
emitX86(INST_BSR, dst, src);
}
/** Byte swap (32 bit or 64 bit registers only) (i486). */
public final void bswap(Register dst)
{
assert(dst.type() == REG_GPD || dst.type() == REG_GPQ);
emitX86(INST_BSWAP, dst);
}
/** Bit test. */
public final void bt(Register dst, Register src)
{
emitX86(INST_BT, dst, src);
}
/** Bit test. */
public final void bt(Register dst, Immediate src)
{
emitX86(INST_BT, dst, src);
}
/** Bit test. */
public final void bt(Mem dst, Register src)
{
emitX86(INST_BT, dst, src);
}
/** Bit test. */
public final void bt(Mem dst, Immediate src)
{
emitX86(INST_BT, dst, src);
}
/** Bit test and complement. */
public final void btc(Register dst, Register src)
{
emitX86(INST_BTC, dst, src);
}
/** Bit test and complement. */
public final void btc(Register dst, Immediate src)
{
emitX86(INST_BTC, dst, src);
}
/** Bit test and complement. */
public final void btc(Mem dst, Register src)
{
emitX86(INST_BTC, dst, src);
}
/** Bit test and complement. */
public final void btc(Mem dst, Immediate src)
{
emitX86(INST_BTC, dst, src);
}
/** Bit test and reset. */
public final void btr(Register dst, Register src)
{
emitX86(INST_BTR, dst, src);
}
/** Bit test and reset. */
public final void btr(Register dst, Immediate src)
{
emitX86(INST_BTR, dst, src);
}
/** Bit test and reset. */
public final void btr(Mem dst, Register src)
{
emitX86(INST_BTR, dst, src);
}
/** Bit test and reset. */
public final void btr(Mem dst, Immediate src)
{
emitX86(INST_BTR, dst, src);
}
/** Bit test and set. */
public final void bts(Register dst, Register src)
{
emitX86(INST_BTS, dst, src);
}
/** Bit test and set. */
public final void bts(Register dst, Immediate src)
{
emitX86(INST_BTS, dst, src);
}
/** Bit test and set. */
public final void bts(Mem dst, Register src)
{
emitX86(INST_BTS, dst, src);
}
/** Bit test and set. */
public final void bts(Mem dst, Immediate src)
{
emitX86(INST_BTS, dst, src);
}
/** Call Procedure. */
public final void call(Register dst)
{
assert(dst.isRegType(is64() ? REG_GPQ : REG_GPD));
emitX86(INST_CALL, dst);
}
/** Call Procedure. */
public final void call(Mem dst)
{
emitX86(INST_CALL, dst);
}
/** Call Procedure. */
public final void call(Immediate dst)
{
emitX86(INST_CALL, dst);
}
/** Jump. */
//! @overload
public final void call(long dst)
{
emitX86(INST_CALL, Immediate.imm(dst));
}
/** Call Procedure. */
public final void call(Label label)
{
emitX86(INST_CALL, label);
}
/** Convert Byte to Word (Sign Extend). */
//!
//! AX <- Sign Extend AL
public final void cbw()
{
emitX86(INST_CBW);
}
/** Convert Word to DWord (Sign Extend). */
//!
//! EAX <- Sign Extend AX
public final void cwde()
{
emitX86(INST_CWDE);
}
/** Convert DWord to QWord (Sign Extend). */
//!
//! RAX <- Sign Extend EAX
public final void cdqe()
{
emitX86(INST_CDQE);
}
/** Clear CARRY flag */
//!
//! This instruction clears the CF flag in the EFLAGS register.
public final void clc()
{
emitX86(INST_CLC);
}
/** Clear Direction flag */
//!
//! This instruction clears the DF flag in the EFLAGS register.
public final void cld()
{
emitX86(INST_CLD);
}
/** Complement Carry Flag. */
//!
//! This instruction complements the CF flag in the EFLAGS register.
//! (CF = NOT CF)
public final void cmc()
{
emitX86(INST_CMC);
}
/** Conditional Move. */
public final void cmov(CONDITION cc, Register dst, Register src)
{
emitX86(conditionToCMovCC(cc), dst, src);
}
/** Conditional Move. */
public final void cmov(CONDITION cc, Register dst, Mem src)
{
emitX86(conditionToCMovCC(cc), dst, src);
}
/** Conditional Move. */
public final void cmova (Register dst, Register src) { emitX86(INST_CMOVA , dst, src); }
/** Conditional Move. */
public final void cmova (Register dst, Mem src) { emitX86(INST_CMOVA , dst, src); }
/** Conditional Move. */
public final void cmovae (Register dst, Register src) { emitX86(INST_CMOVAE , dst, src); }
/** Conditional Move. */
public final void cmovae (Register dst, Mem src) { emitX86(INST_CMOVAE , dst, src); }
/** Conditional Move. */
public final void cmovb (Register dst, Register src) { emitX86(INST_CMOVB , dst, src); }
/** Conditional Move. */
public final void cmovb (Register dst, Mem src) { emitX86(INST_CMOVB , dst, src); }
/** Conditional Move. */
public final void cmovbe (Register dst, Register src) { emitX86(INST_CMOVBE , dst, src); }
/** Conditional Move. */
public final void cmovbe (Register dst, Mem src) { emitX86(INST_CMOVBE , dst, src); }
/** Conditional Move. */
public final void cmovc (Register dst, Register src) { emitX86(INST_CMOVC , dst, src); }
/** Conditional Move. */
public final void cmovc (Register dst, Mem src) { emitX86(INST_CMOVC , dst, src); }
/** Conditional Move. */
public final void cmove (Register dst, Register src) { emitX86(INST_CMOVE , dst, src); }
/** Conditional Move. */
public final void cmove (Register dst, Mem src) { emitX86(INST_CMOVE , dst, src); }
/** Conditional Move. */
public final void cmovg (Register dst, Register src) { emitX86(INST_CMOVG , dst, src); }
/** Conditional Move. */
public final void cmovg (Register dst, Mem src) { emitX86(INST_CMOVG , dst, src); }
/** Conditional Move. */
public final void cmovge (Register dst, Register src) { emitX86(INST_CMOVGE , dst, src); }
/** Conditional Move. */
public final void cmovge (Register dst, Mem src) { emitX86(INST_CMOVGE , dst, src); }
/** Conditional Move. */
public final void cmovl (Register dst, Register src) { emitX86(INST_CMOVL , dst, src); }
/** Conditional Move. */
public final void cmovl (Register dst, Mem src) { emitX86(INST_CMOVL , dst, src); }
/** Conditional Move. */
public final void cmovle (Register dst, Register src) { emitX86(INST_CMOVLE , dst, src); }
/** Conditional Move. */
public final void cmovle (Register dst, Mem src) { emitX86(INST_CMOVLE , dst, src); }
/** Conditional Move. */
public final void cmovna (Register dst, Register src) { emitX86(INST_CMOVNA , dst, src); }
/** Conditional Move. */
public final void cmovna (Register dst, Mem src) { emitX86(INST_CMOVNA , dst, src); }
/** Conditional Move. */
public final void cmovnae(Register dst, Register src) { emitX86(INST_CMOVNAE, dst, src); }
/** Conditional Move. */
public final void cmovnae(Register dst, Mem src) { emitX86(INST_CMOVNAE, dst, src); }
/** Conditional Move. */
public final void cmovnb (Register dst, Register src) { emitX86(INST_CMOVNB , dst, src); }
/** Conditional Move. */
public final void cmovnb (Register dst, Mem src) { emitX86(INST_CMOVNB , dst, src); }
/** Conditional Move. */
public final void cmovnbe(Register dst, Register src) { emitX86(INST_CMOVNBE, dst, src); }
/** Conditional Move. */
public final void cmovnbe(Register dst, Mem src) { emitX86(INST_CMOVNBE, dst, src); }
/** Conditional Move. */
public final void cmovnc (Register dst, Register src) { emitX86(INST_CMOVNC , dst, src); }
/** Conditional Move. */
public final void cmovnc (Register dst, Mem src) { emitX86(INST_CMOVNC , dst, src); }
/** Conditional Move. */
public final void cmovne (Register dst, Register src) { emitX86(INST_CMOVNE , dst, src); }
/** Conditional Move. */
public final void cmovne (Register dst, Mem src) { emitX86(INST_CMOVNE , dst, src); }
/** Conditional Move. */
public final void cmovng (Register dst, Register src) { emitX86(INST_CMOVNG , dst, src); }
/** Conditional Move. */
public final void cmovng (Register dst, Mem src) { emitX86(INST_CMOVNG , dst, src); }
/** Conditional Move. */
public final void cmovnge(Register dst, Register src) { emitX86(INST_CMOVNGE, dst, src); }
/** Conditional Move. */
public final void cmovnge(Register dst, Mem src) { emitX86(INST_CMOVNGE, dst, src); }
/** Conditional Move. */
public final void cmovnl (Register dst, Register src) { emitX86(INST_CMOVNL , dst, src); }
/** Conditional Move. */
public final void cmovnl (Register dst, Mem src) { emitX86(INST_CMOVNL , dst, src); }
/** Conditional Move. */
public final void cmovnle(Register dst, Register src) { emitX86(INST_CMOVNLE, dst, src); }
/** Conditional Move. */
public final void cmovnle(Register dst, Mem src) { emitX86(INST_CMOVNLE, dst, src); }
/** Conditional Move. */
public final void cmovno (Register dst, Register src) { emitX86(INST_CMOVNO , dst, src); }
/** Conditional Move. */
public final void cmovno (Register dst, Mem src) { emitX86(INST_CMOVNO , dst, src); }
/** Conditional Move. */
public final void cmovnp (Register dst, Register src) { emitX86(INST_CMOVNP , dst, src); }
/** Conditional Move. */
public final void cmovnp (Register dst, Mem src) { emitX86(INST_CMOVNP , dst, src); }
/** Conditional Move. */
public final void cmovns (Register dst, Register src) { emitX86(INST_CMOVNS , dst, src); }
/** Conditional Move. */
public final void cmovns (Register dst, Mem src) { emitX86(INST_CMOVNS , dst, src); }
/** Conditional Move. */
public final void cmovnz (Register dst, Register src) { emitX86(INST_CMOVNZ , dst, src); }
/** Conditional Move. */
public final void cmovnz (Register dst, Mem src) { emitX86(INST_CMOVNZ , dst, src); }
/** Conditional Move. */
public final void cmovo (Register dst, Register src) { emitX86(INST_CMOVO , dst, src); }
/** Conditional Move. */
public final void cmovo (Register dst, Mem src) { emitX86(INST_CMOVO , dst, src); }
/** Conditional Move. */
public final void cmovp (Register dst, Register src) { emitX86(INST_CMOVP , dst, src); }
/** Conditional Move. */
public final void cmovp (Register dst, Mem src) { emitX86(INST_CMOVP , dst, src); }
/** Conditional Move. */
public final void cmovpe (Register dst, Register src) { emitX86(INST_CMOVPE , dst, src); }
/** Conditional Move. */
public final void cmovpe (Register dst, Mem src) { emitX86(INST_CMOVPE , dst, src); }
/** Conditional Move. */
public final void cmovpo (Register dst, Register src) { emitX86(INST_CMOVPO , dst, src); }
/** Conditional Move. */
public final void cmovpo (Register dst, Mem src) { emitX86(INST_CMOVPO , dst, src); }
/** Conditional Move. */
public final void cmovs (Register dst, Register src) { emitX86(INST_CMOVS , dst, src); }
/** Conditional Move. */
public final void cmovs (Register dst, Mem src) { emitX86(INST_CMOVS , dst, src); }
/** Conditional Move. */
public final void cmovz (Register dst, Register src) { emitX86(INST_CMOVZ , dst, src); }
/** Conditional Move. */
public final void cmovz (Register dst, Mem src) { emitX86(INST_CMOVZ , dst, src); }
/** Compare Two Operands. */
public final void cmp(Register dst, Register src)
{
emitX86(INST_CMP, dst, src);
}
/** Compare Two Operands. */
public final void cmp(Register dst, Mem src)
{
emitX86(INST_CMP, dst, src);
}
/** Compare Two Operands. */
public final void cmp(Register dst, Immediate src)
{
emitX86(INST_CMP, dst, src);
}
/** Compare Two Operands. */
public final void cmp(Mem dst, Register src)
{
emitX86(INST_CMP, dst, src);
}
/** Compare Two Operands. */
public final void cmp(Mem dst, Immediate src)
{
emitX86(INST_CMP, dst, src);
}
/** Compare and Exchange (i486). */
public final void cmpxchg(Register dst, Register src)
{
emitX86(INST_CMPXCHG, dst, src);
}
/** Compare and Exchange (i486). */
public final void cmpxchg(Mem dst, Register src)
{
emitX86(INST_CMPXCHG, dst, src);
}
/** Compares the 64-bit value in EDX:EAX with the memory operand (Pentium). */
//!
//! If the values are equal, then this instruction stores the 64-bit value
//! in ECX:EBX into the memory operand and sets the zero flag. Otherwise,
//! this instruction copies the 64-bit memory operand into the EDX:EAX
//! registers and clears the zero flag.
public final void cmpxchg8b(Mem dst)
{
emitX86(INST_CMPXCHG8B, dst);
}
/** Compares the 128-bit value in RDX:RAX with the memory operand. */
//!
//! If the values are equal, then this instruction stores the 128-bit value
//! in RCX:RBX into the memory operand and sets the zero flag. Otherwise,
//! this instruction copies the 128-bit memory operand into the RDX:RAX
//! registers and clears the zero flag.
public final void cmpxchg16b(Mem dst)
{
emitX86(INST_CMPXCHG16B, dst);
}
/** CPU Identification (i486). */
public final void cpuid()
{
emitX86(INST_CPUID);
}
/** Decimal adjust AL after addition */
//!
//! This instruction adjusts the sum of two packed BCD values to create
//! a packed BCD result.
//!
//! @note This instruction is only available in 32 bit mode.
public final void daa()
{
emitX86(INST_DAA);
}
/** Decimal adjust AL after subtraction */
//!
//! This instruction adjusts the result of the subtraction of two packed
//! BCD values to create a packed BCD result.
//!
//! @note This instruction is only available in 32 bit mode.
public final void das()
{
emitX86(INST_DAS);
}
/** Decrement by 1. */
//! @note This instruction can be slower than sub(dst, 1)
public final void dec(Register dst)
{
emitX86(INST_DEC, dst);
}
/** Decrement by 1. */
//! @note This instruction can be slower than sub(dst, 1)
public final void dec(Mem dst)
{
emitX86(INST_DEC, dst);
}
/** Unsigned divide. */
//!
//! This instruction divides (unsigned) the value in the AL, AX, or EAX
//! register by the source operand and stores the result in the AX,
//! DX:AX, or EDX:EAX registers.
public final void div(Register src)
{
emitX86(INST_DIV, src);
}
/** Unsigned divide. */
//! @overload
public final void div(Mem src)
{
emitX86(INST_DIV, src);
}
/** Make Stack Frame for Procedure Parameters. */
public final void enter(Immediate imm16, Immediate imm8)
{
emitX86(INST_ENTER, imm16, imm8);
}
/** Signed divide. */
//!
//! This instruction divides (signed) the value in the AL, AX, or EAX
//! register by the source operand and stores the result in the AX,
//! DX:AX, or EDX:EAX registers.
public final void idiv(Register src)
{
emitX86(INST_IDIV, src);
}
/** Signed divide. */
//! @overload
public final void idiv(Mem src)
{
emitX86(INST_IDIV, src);
}
/** Signed multiply. */
//!
//! Source operand (in a general-purpose register or memory location)
//! is multiplied by the value in the AL, AX, or EAX register (depending
//! on the operand size) and the product is stored in the AX, DX:AX, or
//! EDX:EAX registers, respectively.
public final void imul(Register src)
{
emitX86(INST_IMUL, src);
}
//! @overload
public final void imul(Mem src)
{
emitX86(INST_IMUL, src);
}
/** Signed multiply. */
//!
//! Destination operand (the first operand) is multiplied by the source
//! operand (second operand). The destination operand is a generalpurpose
//! register and the source operand is an immediate value, a general-purpose
//! register, or a memory location. The product is then stored in the
//! destination operand location.
public final void imul(Register dst, Register src)
{
emitX86(INST_IMUL, dst, src);
}
/** Signed multiply. */
//! @overload
public final void imul(Register dst, Mem src)
{
emitX86(INST_IMUL, dst, src);
}
/** Signed multiply. */
//! @overload
public final void imul(Register dst, Immediate src)
{
emitX86(INST_IMUL, dst, src);
}
/** Signed multiply. */
//!
//! source operand (which can be a general-purpose register or a memory
//! location) is multiplied by the second source operand (an immediate
//! value). The product is then stored in the destination operand
//! (a general-purpose register).
public final void imul(Register dst, Register src, Immediate imm)
{
emitX86(INST_IMUL, dst, src, imm);
}
//! @overload
public final void imul(Register dst, Mem src, Immediate imm)
{
emitX86(INST_IMUL, dst, src, imm);
}
/** Increment by 1. */
//! @note This instruction can be slower than add(dst, 1)
public final void inc(Register dst)
{
emitX86(INST_INC, dst);
}
/** Increment by 1. */
//! @note This instruction can be slower than add(dst, 1)
public final void inc(Mem dst)
{
emitX86(INST_INC, dst);
}
/** Interrupt 3 � trap to debugger. */
public final void int3()
{
emitX86(INST_INT3);
}
/** Jump to label @a label if condition @a cc is met. */
//!
//! This instruction checks the state of one or more of the status flags in
//! the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags are in the
//! specified state (condition), performs a jump to the target instruction
//! specified by the destination operand. A condition code (cc) is associated
//! with each instruction to indicate the condition being tested for. If the
//! condition is not satisfied, the jump is not performed and execution
//! continues with the instruction following the Jcc instruction.
public final void j(CONDITION cc, Label label, int hint)
{
_emitJcc(conditionToJCC(cc), label, hint);
}
/** Jump to label @a label if condition is met. */
public final void ja (Label label, int hint) { _emitJcc(INST_JA , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jae (Label label, int hint) { _emitJcc(INST_JAE , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jb (Label label, int hint) { _emitJcc(INST_JB , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jbe (Label label, int hint) { _emitJcc(INST_JBE , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jc (Label label, int hint) { _emitJcc(INST_JC , label, hint); }
/** Jump to label @a label if condition is met. */
public final void je (Label label, int hint) { _emitJcc(INST_JE , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jg (Label label, int hint) { _emitJcc(INST_JG , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jge (Label label, int hint) { _emitJcc(INST_JGE , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jl (Label label, int hint) { _emitJcc(INST_JL , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jle (Label label, int hint) { _emitJcc(INST_JLE , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jna (Label label, int hint) { _emitJcc(INST_JNA , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnae(Label label, int hint) { _emitJcc(INST_JNAE, label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnb (Label label, int hint) { _emitJcc(INST_JNB , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnbe(Label label, int hint) { _emitJcc(INST_JNBE, label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnc (Label label, int hint) { _emitJcc(INST_JNC , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jne (Label label, int hint) { _emitJcc(INST_JNE , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jng (Label label, int hint) { _emitJcc(INST_JNG , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnge(Label label, int hint) { _emitJcc(INST_JNGE, label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnl (Label label, int hint) { _emitJcc(INST_JNL , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnle(Label label, int hint) { _emitJcc(INST_JNLE, label, hint); }
/** Jump to label @a label if condition is met. */
public final void jno (Label label, int hint) { _emitJcc(INST_JNO , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnp (Label label, int hint) { _emitJcc(INST_JNP , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jns (Label label, int hint) { _emitJcc(INST_JNS , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnz (Label label, int hint) { _emitJcc(INST_JNZ , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jo (Label label, int hint) { _emitJcc(INST_JO , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jp (Label label, int hint) { _emitJcc(INST_JP , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jpe (Label label, int hint) { _emitJcc(INST_JPE , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jpo (Label label, int hint) { _emitJcc(INST_JPO , label, hint); }
/** Jump to label @a label if condition is met. */
public final void js (Label label, int hint) { _emitJcc(INST_JS , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jz (Label label, int hint) { _emitJcc(INST_JZ , label, hint); }
/** Jump to label @a label if condition @a cc is met. */
//!
//! This instruction checks the state of one or more of the status flags in
//! the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags are in the
//! specified state (condition), performs a jump to the target instruction
//! specified by the destination operand. A condition code (cc) is associated
//! with each instruction to indicate the condition being tested for. If the
//! condition is not satisfied, the jump is not performed and execution
//! continues with the instruction following the Jcc instruction.
public final void j_short(CONDITION cc, Label label, int hint)
{
// Adjust returned condition to jxx_short version.
_emitJcc(INST_CODE.valueOf(conditionToJCC(cc).ordinal() + INST_J_SHORT.ordinal() - INST_J.ordinal()), label, hint);
}
/** Jump to label @a label if condition is met. */
public final void ja_short (Label label, int hint) { _emitJcc(INST_JA_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jae_short (Label label, int hint) { _emitJcc(INST_JAE_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jb_short (Label label, int hint) { _emitJcc(INST_JB_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jbe_short (Label label, int hint) { _emitJcc(INST_JBE_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jc_short (Label label, int hint) { _emitJcc(INST_JC_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void je_short (Label label, int hint) { _emitJcc(INST_JE_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jg_short (Label label, int hint) { _emitJcc(INST_JG_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jge_short (Label label, int hint) { _emitJcc(INST_JGE_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jl_short (Label label, int hint) { _emitJcc(INST_JL_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jle_short (Label label, int hint) { _emitJcc(INST_JLE_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jna_short (Label label, int hint) { _emitJcc(INST_JNA_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnae_short(Label label, int hint) { _emitJcc(INST_JNAE_SHORT, label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnb_short (Label label, int hint) { _emitJcc(INST_JNB_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnbe_short(Label label, int hint) { _emitJcc(INST_JNBE_SHORT, label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnc_short (Label label, int hint) { _emitJcc(INST_JNC_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jne_short (Label label, int hint) { _emitJcc(INST_JNE_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jng_short (Label label, int hint) { _emitJcc(INST_JNG_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnge_short(Label label, int hint) { _emitJcc(INST_JNGE_SHORT, label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnl_short (Label label, int hint) { _emitJcc(INST_JNL_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnle_short(Label label, int hint) { _emitJcc(INST_JNLE_SHORT, label, hint); }
/** Jump to label @a label if condition is met. */
public final void jno_short (Label label, int hint) { _emitJcc(INST_JNO_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnp_short (Label label, int hint) { _emitJcc(INST_JNP_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jns_short (Label label, int hint) { _emitJcc(INST_JNS_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jnz_short (Label label, int hint) { _emitJcc(INST_JNZ_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jo_short (Label label, int hint) { _emitJcc(INST_JO_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jp_short (Label label, int hint) { _emitJcc(INST_JP_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jpe_short (Label label, int hint) { _emitJcc(INST_JPE_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jpo_short (Label label, int hint) { _emitJcc(INST_JPO_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void js_short (Label label, int hint) { _emitJcc(INST_JS_SHORT , label, hint); }
/** Jump to label @a label if condition is met. */
public final void jz_short (Label label, int hint) { _emitJcc(INST_JZ_SHORT , label, hint); }
/** Jump. */
//! @overload
public final void jmp(Register dst)
{
emitX86(INST_JMP, dst);
}
/** Jump. */
//! @overload
public final void jmp(Mem dst)
{
emitX86(INST_JMP, dst);
}
/** Jump. */
//! @overload
public final void jmp(Immediate dst)
{
emitX86(INST_JMP, dst);
}
/** Jump. */
//! @overload
public final void jmp(long dst)
{
emitX86(INST_JMP, Immediate.imm(dst));
}
/** Jump. */
//!
//! This instruction transfers program control to a different point
//! in the instruction stream without recording return information.
//! The destination (target) operand specifies the label of the
//! instruction being jumped to.
public final void jmp(Label label)
{
emitX86(INST_JMP, label);
}
/** Jump, see @c jmp(). */
public final void jmp_short(Label label)
{
emitX86(INST_JMP_SHORT, label);
}
/** Load Effective Address */
//!
//! This instruction computes the effective address of the second
//! operand (the source operand) and stores it in the first operand
//! (destination operand). The source operand is a memory address
//! (offset part) specified with one of the processors addressing modes.
//! The destination operand is a general-purpose register.
public final void lea(Register dst, Mem src)
{
emitX86(INST_LEA, dst, src);
}
/** High Level Procedure Exit. */
public final void leave()
{
emitX86(INST_LEAVE);
}
/** Assert LOCK# Signal Prefix. */
//!
//! This instruction causes the processor�s LOCK# signal to be asserted
//! during execution of the accompanying instruction (turns the
//! instruction into an atomic instruction). In a multiprocessor environment,
//! the LOCK# signal insures that the processor has exclusive use of any shared
//! memory while the signal is asserted.
//!
//! The LOCK prefix can be prepended only to the following instructions and
//! to those forms of the instructions that use a memory operand: ADD, ADC,
//! AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD,
//! and XCHG. An undefined opcode exception will be generated if the LOCK
//! prefix is used with any other instruction. The XCHG instruction always
//! asserts the LOCK# signal regardless of the presence or absence of the LOCK
//! prefix.
public final void lock()
{
emitX86(INST_LOCK);
}
/** Move data from one register to another.
*
* This instruction copies the second operand (source operand) to the first
* operand (destination operand). The source operand can be an immediate
* value, general-purpose register, segment register, or memory location.
* The destination register can be a general-purpose register, segment
* register, or memory location. Both operands must be the same size, which
* can be a byte, a word, or a DWORD.
*
* @note To move MMX or SSE registers to/from GP registers or memory, use
* corresponding functions: @c movd(), @c movq(), etc. Passing MMX or SSE
* registers to @c mov() is illegal.
*/
public final void mov(Register dst, Register src)
{
emitX86(INST_MOV, dst, src);
}
/** Move. */
//! @overload
public final void mov(Register dst, Mem src)
{
emitX86(INST_MOV, dst, src);
}
/** Move. */
//! @overload
public final void mov(Register dst, Immediate src)
{
emitX86(INST_MOV, dst, src);
}
/** Move. */
//! @overload
public final void mov(Mem dst, Register src)
{
emitX86(INST_MOV, dst, src);
}
/** Move. */
//! @overload
public final void mov(Mem dst, Immediate src)
{
emitX86(INST_MOV, dst, src);
}
/** Move byte, word, dword or qword from absolute address @a src to
* AL, AX, EAX or RAX register.
*/
public final void mov_ptr(Register dst, long src)
{
assert dst.index() == 0;
emitX86(INST_MOV_PTR, dst, Immediate.imm(src));
}
/** Move byte, word, dword or qword from AL, AX, EAX or RAX register
* to absolute address @a dst.
*/
public final void mov_ptr(long dst, Register src)
{
assert src.index() == 0;
emitX86(INST_MOV_PTR, Immediate.imm(dst), src);
}
/** Move with Sign-Extension. */
//!
//! This instruction copies the contents of the source operand (register
//! or memory location) to the destination operand (register) and sign
//! extends the value to 16, 32 or 64 bits.
//!
//! @sa movsxd().
public final void movsx(Register dst, Register src)
{
emitX86(INST_MOVSX, dst, src);
}
/** Move with Sign-Extension. */
//! @overload
public final void movsx(Register dst, Mem src)
{
emitX86(INST_MOVSX, dst, src);
}
/** Move DWord to QWord with sign-extension. */
public final void movsxd(Register dst, Register src)
{
emitX86(INST_MOVSXD, dst, src);
}
/** Move DWord to QWord with sign-extension. */
//! @overload
public final void movsxd(Register dst, Mem src)
{
emitX86(INST_MOVSXD, dst, src);
}
/** Move with Zero-Extend. */
//!
//! This instruction copies the contents of the source operand (register
//! or memory location) to the destination operand (register) and zero
//! extends the value to 16 or 32 bits. The size of the converted value
//! depends on the operand-size attribute.
public final void movzx(Register dst, Register src)
{
emitX86(INST_MOVZX, dst, src);
}
/** Move with Zero-Extend. */
public final void movzx(Register dst, Mem src)
{
emitX86(INST_MOVZX, dst, src);
}
/** Unsigned multiply. */
//!
//! Source operand (in a general-purpose register or memory location)
//! is multiplied by the value in the AL, AX, or EAX register (depending
//! on the operand size) and the product is stored in the AX, DX:AX, or
//! EDX:EAX registers, respectively.
public final void mul(Register src)
{
emitX86(INST_MUL, src);
}
/** Unsigned multiply. */
//! @overload
public final void mul(Mem src)
{
emitX86(INST_MUL, src);
}
/** Two's Complement Negation. */
public final void neg(Register dst)
{
emitX86(INST_NEG, dst);
}
/** Two's Complement Negation. */
public final void neg(Mem dst)
{
emitX86(INST_NEG, dst);
}
/** No Operation. */
//!
//! This instruction performs no operation. This instruction is a one-byte
//! instruction that takes up space in the instruction stream but does not
//! affect the machine context, except the EIP register. The NOP instruction
//! is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.
public final void nop()
{
emitX86(INST_NOP);
}
/** One's Complement Negation. */
public final void not_(Register dst)
{
emitX86(INST_NOT, dst);
}
/** One's Complement Negation. */
public final void not_(Mem dst)
{
emitX86(INST_NOT, dst);
}
/** Logical Inclusive OR. */
public final void or_(Register dst, Register src)
{
emitX86(INST_OR, dst, src);
}
/** Logical Inclusive OR. */
public final void or_(Register dst, Mem src)
{
emitX86(INST_OR, dst, src);
}
/** Logical Inclusive OR. */
public final void or_(Register dst, Immediate src)
{
emitX86(INST_OR, dst, src);
}
/** Logical Inclusive OR. */
public final void or_(Mem dst, Register src)
{
emitX86(INST_OR, dst, src);
}
/** Logical Inclusive OR. */
public final void or_(Mem dst, Immediate src)
{
emitX86(INST_OR, dst, src);
}
/** Pop a Value from the Stack. */
//!
//! This instruction loads the value from the top of the stack to the location
//! specified with the destination operand and then increments the stack pointer.
//! The destination operand can be a general purpose register, memory location,
//! or segment register.
public final void pop(Register dst)
{
assert(dst.isRegType(REG_GPW) || dst.isRegType(is64() ? REG_GPQ : REG_GPD));
emitX86(INST_POP, dst);
}
public final void pop(Mem dst)
{
assert(dst.size() == 2 || dst.size() == (is64() ? 8 : 4));
emitX86(INST_POP, dst);
}
/** Pop All General-Purpose Registers. */
//!
//! Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX.
public final void popad()
{
emitX86(INST_POPAD);
}
/** Pop Stack into EFLAGS Register (32 bit or 64 bit). */
public final void popf()
{
if (!is64()) {
popfd();
} else {
popfq();
}
}
/** Pop Stack into EFLAGS Register (32 bit). */
public final void popfd() { emitX86(INST_POPFD); }
/** Pop Stack into EFLAGS Register (64 bit). */
public final void popfq() { emitX86(INST_POPFQ); }
/** Push WORD/DWORD/QWORD Onto the Stack. */
//!
//! @note 32 bit architecture pushed DWORD while 64 bit
//! pushes QWORD. 64 bit mode not provides instruction to
//! push 32 bit register/memory.
public final void push(Register src)
{
//assert(src.isRegType(REG_GPW) || src.isRegType(REG_GPN));
emitX86(INST_PUSH, src);
}
/** Push WORD/DWORD/QWORD Onto the Stack. */
public final void push(Mem src)
{
assert(src.size() == 2 || src.size() == (is64() ? 8 : 4));
emitX86(INST_PUSH, src);
}
/** Push WORD/DWORD/QWORD Onto the Stack. */
public final void push(Immediate src)
{
emitX86(INST_PUSH, src);
}
/** Push All General-Purpose Registers. */
//!
//! Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI.
public final void pushad()
{
emitX86(INST_PUSHAD);
}
/** Push EFLAGS Register (32 bit or 64 bit) onto the Stack. */
public final void pushf()
{
if (!is64()) {
pushfd();
} else {
pushfq();
}
}
/** Push EFLAGS Register (32 bit) onto the Stack. */
public final void pushfd() { emitX86(INST_PUSHFD); }
/** Push EFLAGS Register (64 bit) onto the Stack. */
public final void pushfq() { emitX86(INST_PUSHFQ); }
/** Rotate Bits Left. */
//! @note @a src register can be only @c cl.
public final void rcl(Register dst, Register src)
{
emitX86(INST_RCL, dst, src);
}
/** Rotate Bits Left. */
public final void rcl(Register dst, Immediate src)
{
emitX86(INST_RCL, dst, src);
}
/** Rotate Bits Left. */
//! @note @a src register can be only @c cl.
public final void rcl(Mem dst, Register src)
{
emitX86(INST_RCL, dst, src);
}
/** Rotate Bits Left. */
public final void rcl(Mem dst, Immediate src)
{
emitX86(INST_RCL, dst, src);
}
/** Rotate Bits Right. */
//! @note @a src register can be only @c cl.
public final void rcr(Register dst, Register src)
{
emitX86(INST_RCR, dst, src);
}
/** Rotate Bits Right. */
public final void rcr(Register dst, Immediate src)
{
emitX86(INST_RCR, dst, src);
}
/** Rotate Bits Right. */
//! @note @a src register can be only @c cl.
public final void rcr(Mem dst, Register src)
{
emitX86(INST_RCR, dst, src);
}
/** Rotate Bits Right. */
public final void rcr(Mem dst, Immediate src)
{
emitX86(INST_RCR, dst, src);
}
/** Read Time-Stamp Counter (Pentium). */
public final void rdtsc()
{
emitX86(INST_RDTSC);
}
/** Read Time-Stamp Counter and Processor ID (New). */
public final void rdtscp()
{
emitX86(INST_RDTSCP);
}
/** Return from Procedure. */
public final void ret()
{
emitX86(INST_RET);
}
/** Return from Procedure. */
public final void ret(Immediate imm16)
{
emitX86(INST_RET, imm16);
}
/** Rotate Bits Left. */
//! @note @a src register can be only @c cl.
public final void rol(Register dst, Register src)
{
emitX86(INST_ROL, dst, src);
}
/** Rotate Bits Left. */
public final void rol(Register dst, Immediate src)
{
emitX86(INST_ROL, dst, src);
}
/** Rotate Bits Left. */
//! @note @a src register can be only @c cl.
public final void rol(Mem dst, Register src)
{
emitX86(INST_ROL, dst, src);
}
/** Rotate Bits Left. */
public final void rol(Mem dst, Immediate src)
{
emitX86(INST_ROL, dst, src);
}
/** Rotate Bits Right. */
//! @note @a src register can be only @c cl.
public final void ror(Register dst, Register src)
{
emitX86(INST_ROR, dst, src);
}
/** Rotate Bits Right. */
public final void ror(Register dst, Immediate src)
{
emitX86(INST_ROR, dst, src);
}
/** Rotate Bits Right. */
//! @note @a src register can be only @c cl.
public final void ror(Mem dst, Register src)
{
emitX86(INST_ROR, dst, src);
}
/** Rotate Bits Right. */
public final void ror(Mem dst, Immediate src)
{
emitX86(INST_ROR, dst, src);
}
/** Store AH into Flags. */
public final void sahf()
{
emitX86(INST_SAHF);
}
/** Integer subtraction with borrow. */
public final void sbb(Register dst, Register src)
{
emitX86(INST_SBB, dst, src);
}
/** Integer subtraction with borrow. */
public final void sbb(Register dst, Mem src)
{
emitX86(INST_SBB, dst, src);
}
/** Integer subtraction with borrow. */
public final void sbb(Register dst, Immediate src)
{
emitX86(INST_SBB, dst, src);
}
/** Integer subtraction with borrow. */
public final void sbb(Mem dst, Register src)
{
emitX86(INST_SBB, dst, src);
}
/** Integer subtraction with borrow. */
public final void sbb(Mem dst, Immediate src)
{
emitX86(INST_SBB, dst, src);
}
/** Shift Bits Left. */
//! @note @a src register can be only @c cl.
public final void sal(Register dst, Register src)
{
emitX86(INST_SAL, dst, src);
}
/** Shift Bits Left. */
public final void sal(Register dst, Immediate src)
{
emitX86(INST_SAL, dst, src);
}
/** Shift Bits Left. */
//! @note @a src register can be only @c cl.
public final void sal(Mem dst, Register src)
{
emitX86(INST_SAL, dst, src);
}
/** Shift Bits Left. */
public final void sal(Mem dst, Immediate src)
{
emitX86(INST_SAL, dst, src);
}
/** Shift Bits Right. */
//! @note @a src register can be only @c cl.
public final void sar(Register dst, Register src)
{
emitX86(INST_SAR, dst, src);
}
/** Shift Bits Right. */
public final void sar(Register dst, Immediate src)
{
emitX86(INST_SAR, dst, src);
}
/** Shift Bits Right. */
//! @note @a src register can be only @c cl.
public final void sar(Mem dst, Register src)
{
emitX86(INST_SAR, dst, src);
}
/** Shift Bits Right. */
public final void sar(Mem dst, Immediate src)
{
emitX86(INST_SAR, dst, src);
}
/** Set Byte on Condition. */
public final void set(CONDITION cc, Register dst)
{
emitX86(conditionToSetCC(cc), dst);
}
/** Set Byte on Condition. */
public final void set(CONDITION cc, Mem dst)
{
emitX86(conditionToSetCC(cc), dst);
}
/** Set Byte on Condition. */
public final void seta (Register dst) { emitX86(INST_SETA , dst); }
/** Set Byte on Condition. */
public final void seta (Mem dst) { emitX86(INST_SETA , dst); }
/** Set Byte on Condition. */
public final void setae (Register dst) { emitX86(INST_SETAE , dst); }
/** Set Byte on Condition. */
public final void setae (Mem dst) { emitX86(INST_SETAE , dst); }
/** Set Byte on Condition. */
public final void setb (Register dst) { emitX86(INST_SETB , dst); }
/** Set Byte on Condition. */
public final void setb (Mem dst) { emitX86(INST_SETB , dst); }
/** Set Byte on Condition. */
public final void setbe (Register dst) { emitX86(INST_SETBE , dst); }
/** Set Byte on Condition. */
public final void setbe (Mem dst) { emitX86(INST_SETBE , dst); }
/** Set Byte on Condition. */
public final void setc (Register dst) { emitX86(INST_SETC , dst); }
/** Set Byte on Condition. */
public final void setc (Mem dst) { emitX86(INST_SETC , dst); }
/** Set Byte on Condition. */
public final void sete (Register dst) { emitX86(INST_SETE , dst); }
/** Set Byte on Condition. */
public final void sete (Mem dst) { emitX86(INST_SETE , dst); }
/** Set Byte on Condition. */
public final void setg (Register dst) { emitX86(INST_SETG , dst); }
/** Set Byte on Condition. */
public final void setg (Mem dst) { emitX86(INST_SETG , dst); }
/** Set Byte on Condition. */
public final void setge (Register dst) { emitX86(INST_SETGE , dst); }
/** Set Byte on Condition. */
public final void setge (Mem dst) { emitX86(INST_SETGE , dst); }
/** Set Byte on Condition. */
public final void setl (Register dst) { emitX86(INST_SETL , dst); }
/** Set Byte on Condition. */
public final void setl (Mem dst) { emitX86(INST_SETL , dst); }
/** Set Byte on Condition. */
public final void setle (Register dst) { emitX86(INST_SETLE , dst); }
/** Set Byte on Condition. */
public final void setle (Mem dst) { emitX86(INST_SETLE , dst); }
/** Set Byte on Condition. */
public final void setna (Register dst) { emitX86(INST_SETNA , dst); }
/** Set Byte on Condition. */
public final void setna (Mem dst) { emitX86(INST_SETNA , dst); }
/** Set Byte on Condition. */
public final void setnae(Register dst) { emitX86(INST_SETNAE, dst); }
/** Set Byte on Condition. */
public final void setnae(Mem dst) { emitX86(INST_SETNAE, dst); }
/** Set Byte on Condition. */
public final void setnb (Register dst) { emitX86(INST_SETNB , dst); }
/** Set Byte on Condition. */
public final void setnb (Mem dst) { emitX86(INST_SETNB , dst); }
/** Set Byte on Condition. */
public final void setnbe(Register dst) { emitX86(INST_SETNBE, dst); }
/** Set Byte on Condition. */
public final void setnbe(Mem dst) { emitX86(INST_SETNBE, dst); }
/** Set Byte on Condition. */
public final void setnc (Register dst) { emitX86(INST_SETNC , dst); }
/** Set Byte on Condition. */
public final void setnc (Mem dst) { emitX86(INST_SETNC , dst); }
/** Set Byte on Condition. */
public final void setne (Register dst) { emitX86(INST_SETNE , dst); }
/** Set Byte on Condition. */
public final void setne (Mem dst) { emitX86(INST_SETNE , dst); }
/** Set Byte on Condition. */
public final void setng (Register dst) { emitX86(INST_SETNG , dst); }
/** Set Byte on Condition. */
public final void setng (Mem dst) { emitX86(INST_SETNG , dst); }
/** Set Byte on Condition. */
public final void setnge(Register dst) { emitX86(INST_SETNGE, dst); }
/** Set Byte on Condition. */
public final void setnge(Mem dst) { emitX86(INST_SETNGE, dst); }
/** Set Byte on Condition. */
public final void setnl (Register dst) { emitX86(INST_SETNL , dst); }
/** Set Byte on Condition. */
public final void setnl (Mem dst) { emitX86(INST_SETNL , dst); }
/** Set Byte on Condition. */
public final void setnle(Register dst) { emitX86(INST_SETNLE, dst); }
/** Set Byte on Condition. */
public final void setnle(Mem dst) { emitX86(INST_SETNLE, dst); }
/** Set Byte on Condition. */
public final void setno (Register dst) { emitX86(INST_SETNO , dst); }
/** Set Byte on Condition. */
public final void setno (Mem dst) { emitX86(INST_SETNO , dst); }
/** Set Byte on Condition. */
public final void setnp (Register dst) { emitX86(INST_SETNP , dst); }
/** Set Byte on Condition. */
public final void setnp (Mem dst) { emitX86(INST_SETNP , dst); }
/** Set Byte on Condition. */
public final void setns (Register dst) { emitX86(INST_SETNS , dst); }
/** Set Byte on Condition. */
public final void setns (Mem dst) { emitX86(INST_SETNS , dst); }
/** Set Byte on Condition. */
public final void setnz (Register dst) { emitX86(INST_SETNZ , dst); }
/** Set Byte on Condition. */
public final void setnz (Mem dst) { emitX86(INST_SETNZ , dst); }
/** Set Byte on Condition. */
public final void seto (Register dst) { emitX86(INST_SETO , dst); }
/** Set Byte on Condition. */
public final void seto (Mem dst) { emitX86(INST_SETO , dst); }
/** Set Byte on Condition. */
public final void setp (Register dst) { emitX86(INST_SETP , dst); }
/** Set Byte on Condition. */
public final void setp (Mem dst) { emitX86(INST_SETP , dst); }
/** Set Byte on Condition. */
public final void setpe (Register dst) { emitX86(INST_SETPE , dst); }
/** Set Byte on Condition. */
public final void setpe (Mem dst) { emitX86(INST_SETPE , dst); }
/** Set Byte on Condition. */
public final void setpo (Register dst) { emitX86(INST_SETPO , dst); }
/** Set Byte on Condition. */
public final void setpo (Mem dst) { emitX86(INST_SETPO , dst); }
/** Set Byte on Condition. */
public final void sets (Register dst) { emitX86(INST_SETS , dst); }
/** Set Byte on Condition. */
public final void sets (Mem dst) { emitX86(INST_SETS , dst); }
/** Set Byte on Condition. */
public final void setz (Register dst) { emitX86(INST_SETZ , dst); }
/** Set Byte on Condition. */
public final void setz (Mem dst) { emitX86(INST_SETZ , dst); }
/** Shift Bits Left. */
//! @note @a src register can be only @c cl.
public final void shl(Register dst, Register src)
{
emitX86(INST_SHL, dst, src);
}
/** Shift Bits Left. */
public final void shl(Register dst, Immediate src)
{
emitX86(INST_SHL, dst, src);
}
/** Shift Bits Left. */
//! @note @a src register can be only @c cl.
public final void shl(Mem dst, Register src)
{
emitX86(INST_SHL, dst, src);
}
/** Shift Bits Left. */
public final void shl(Mem dst, Immediate src)
{
emitX86(INST_SHL, dst, src);
}
/** Shift Bits Right. */
//! @note @a src register can be only @c cl.
public final void shr(Register dst, Register src)
{
emitX86(INST_SHR, dst, src);
}
/** Shift Bits Right. */
public final void shr(Register dst, Immediate src)
{
emitX86(INST_SHR, dst, src);
}
/** Shift Bits Right. */
//! @note @a src register can be only @c cl.
public final void shr(Mem dst, Register src)
{
emitX86(INST_SHR, dst, src);
}
/** Shift Bits Right. */
public final void shr(Mem dst, Immediate src)
{
emitX86(INST_SHR, dst, src);
}
/** Double Precision Shift Left. */
//! @note src2 register can be only @c cl register.
public final void shld(Register dst, Register src1, Register src2)
{
emitX86(INST_SHLD, dst, src1, src2);
}
/** Double Precision Shift Left. */
public final void shld(Register dst, Register src1, Immediate src2)
{
emitX86(INST_SHLD, dst, src1, src2);
}
/** Double Precision Shift Left. */
//! @note src2 register can be only @c cl register.
public final void shld(Mem dst, Register src1, Register src2)
{
emitX86(INST_SHLD, dst, src1, src2);
}
/** Double Precision Shift Left. */
public final void shld(Mem dst, Register src1, Immediate src2)
{
emitX86(INST_SHLD, dst, src1, src2);
}
/** Double Precision Shift Right. */
//! @note src2 register can be only @c cl register.
public final void shrd(Register dst, Register src1, Register src2)
{
emitX86(INST_SHRD, dst, src1, src2);
}
/** Double Precision Shift Right. */
public final void shrd(Register dst, Register src1, Immediate src2)
{
emitX86(INST_SHRD, dst, src1, src2);
}
/** Double Precision Shift Right. */
//! @note src2 register can be only @c cl register.
public final void shrd(Mem dst, Register src1, Register src2)
{
emitX86(INST_SHRD, dst, src1, src2);
}
/** Double Precision Shift Right. */
public final void shrd(Mem dst, Register src1, Immediate src2)
{
emitX86(INST_SHRD, dst, src1, src2);
}
/** Set Carry Flag to 1. */
public final void stc()
{
emitX86(INST_STC);
}
/** Set Direction Flag to 1. */
public final void std()
{
emitX86(INST_STD);
}
/** Subtract. */
public final void sub(Register dst, Register src)
{
emitX86(INST_SUB, dst, src);
}
/** Subtract. */
public final void sub(Register dst, Mem src)
{
emitX86(INST_SUB, dst, src);
}
/** Subtract. */
public final void sub(Register dst, Immediate src)
{
emitX86(INST_SUB, dst, src);
}
/** Subtract. */
public final void sub(Mem dst, Register src)
{
emitX86(INST_SUB, dst, src);
}
/** Subtract. */
public final void sub(Mem dst, Immediate src)
{
emitX86(INST_SUB, dst, src);
}
/** Logical Compare. */
public final void test(Register op1, Register op2)
{
emitX86(INST_TEST, op1, op2);
}
/** Logical Compare. */
public final void test(Register op1, Immediate op2)
{
emitX86(INST_TEST, op1, op2);
}
/** Logical Compare. */
public final void test(Mem op1, Register op2)
{
emitX86(INST_TEST, op1, op2);
}
/** Logical Compare. */
public final void test(Mem op1, Immediate op2)
{
emitX86(INST_TEST, op1, op2);
}
/** Undefined instruction - Raise invalid opcode exception. */
public final void ud2()
{
emitX86(INST_UD2);
}
/** Exchange and Add. */
public final void xadd(Register dst, Register src)
{
emitX86(INST_XADD, dst, src);
}
/** Exchange and Add. */
public final void xadd(Mem dst, Register src)
{
emitX86(INST_XADD, dst, src);
}
/** Exchange Register/Memory with Register. */
public final void xchg(Register dst, Register src)
{
emitX86(INST_XCHG, dst, src);
}
/** Exchange Register/Memory with Register. */
public final void xchg(Mem dst, Register src)
{
emitX86(INST_XCHG, dst, src);
}
/** Exchange Register/Memory with Register. */
public final void xchg(Register dst, Mem src)
{
emitX86(INST_XCHG, src, dst);
}
/** Exchange Register/Memory with Register. */
public final void xor_(Register dst, Register src)
{
emitX86(INST_XOR, dst, src);
}
/** Exchange Register/Memory with Register. */
public final void xor_(Register dst, Mem src)
{
emitX86(INST_XOR, dst, src);
}
/** Exchange Register/Memory with Register. */
public final void xor_(Register dst, Immediate src)
{
emitX86(INST_XOR, dst, src);
}
/** Exchange Register/Memory with Register. */
public final void xor_(Mem dst, Register src)
{
emitX86(INST_XOR, dst, src);
}
/** Exchange Register/Memory with Register. */
public final void xor_(Mem dst, Immediate src)
{
emitX86(INST_XOR, dst, src);
}
// -------------------------------------------------------------------------
// [X87 Instructions (FPU)]
// -------------------------------------------------------------------------
/** Compute 2^x - 1 (FPU). */
public final void f2xm1()
{
emitX86(INST_F2XM1);
}
/** Absolute Value of st(0) (FPU). */
public final void fabs()
{
emitX86(INST_FABS);
}
/** Add @a src to @a dst and store result in @a dst (FPU). */
//!
//! @note One of dst or src must be st(0).
public final void fadd(X87Register dst, X87Register src)
{
assert dst.index() == 0 || src.index() == 0;
emitX86(INST_FADD, dst, src);
}
/** Add @a src to st(0) and store result in st(0) (FPU). */
//!
//! @note SP-FP or DP-FP determined by @a adr size.
public final void fadd(Mem src)
{
emitX86(INST_FADD, src);
}
/** Add st(0) to @a dst and POP register stack (FPU). */
public final void faddp(X87Register dst)
{
emitX86(INST_FADDP, dst);
}
/** Add st(0) to @a dst and POP register stack (FPU). */
public final void faddp()
{
faddp(X87Register.st(1));
}
/** Load Binary Coded Decimal (FPU). */
public final void fbld(Mem src)
{
emitX86(INST_FBLD, src);
}
/** Store BCD Integer and Pop (FPU). */
public final void fbstp(Mem dst)
{
emitX86(INST_FBSTP, dst);
}
/** Change st(0) Sign (FPU). */
public final void fchs()
{
emitX86(INST_FCHS);
}
/** Clear Exceptions (FPU). */
//!
//! Clear floating-point exception flags after checking for pending unmasked
//! floatingpoint exceptions.
//!
//! Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE),
//! the exception summary status flag (ES), the stack fault flag (SF), and
//! the busy flag (B) in the FPU status word. The FCLEX instruction checks
//! for and handles any pending unmasked floating-point exceptions before
//! clearing the exception flags.
public final void fclex()
{
emitX86(INST_FCLEX);
}
/** FP Conditional Move (FPU). */
public final void fcmovb(X87Register src)
{
emitX86(INST_FCMOVB, src);
}
/** FP Conditional Move (FPU). */
public final void fcmovbe(X87Register src)
{
emitX86(INST_FCMOVBE, src);
}
/** FP Conditional Move (FPU). */
public final void fcmove(X87Register src)
{
emitX86(INST_FCMOVE, src);
}
/** FP Conditional Move (FPU). */
public final void fcmovnb(X87Register src)
{
emitX86(INST_FCMOVNB, src);
}
/** FP Conditional Move (FPU). */
public final void fcmovnbe(X87Register src)
{
emitX86(INST_FCMOVNBE, src);
}
/** FP Conditional Move (FPU). */
public final void fcmovne(X87Register src)
{
emitX86(INST_FCMOVNE, src);
}
/** FP Conditional Move (FPU). */
public final void fcmovnu(X87Register src)
{
emitX86(INST_FCMOVNU, src);
}
/** FP Conditional Move (FPU). */
public final void fcmovu(X87Register src)
{
emitX86(INST_FCMOVU, src);
}
/** Compare st(0) with @a reg (FPU). */
public final void fcom(X87Register reg)
{
emitX86(INST_FCOM, reg);
}
public final void fcom()
{
fcom(X87Register.st(1));
}
/** Compare st(0) with 4 byte or 8 byte FP at @a src (FPU). */
public final void fcom(Mem src)
{
emitX86(INST_FCOM, src);
}
/** Compare st(0) with @a reg and pop the stack (FPU). */
public final void fcomp(X87Register reg)
{
emitX86(INST_FCOMP, reg);
}
public final void fcomp()
{
fcomp(X87Register.st(1));
}
/** Compare st(0) with 4 byte or 8 byte FP at @a adr and pop the */
//! stack (FPU).
public final void fcomp(Mem mem)
{
emitX86(INST_FCOMP, mem);
}
/** Compare st(0) with st(1) and pop register stack twice (FPU). */
public final void fcompp()
{
emitX86(INST_FCOMPP);
}
/** Compare st(0) and @a reg and Set EFLAGS (FPU). */
public final void fcomi(X87Register reg)
{
emitX86(INST_FCOMI, reg);
}
/** Compare st(0) and @a reg and Set EFLAGS and pop the stack (FPU). */
public final void fcomip(X87Register reg)
{
emitX86(INST_FCOMIP, reg);
}
/** Cosine (FPU). */
//!
//! This instruction calculates the cosine of the source operand in
//! register st(0) and stores the result in st(0).
public final void fcos()
{
emitX86(INST_FCOS);
}
/** Decrement Stack-Top Pointer (FPU). */
//!
//! Subtracts one from the TOP field of the FPU status word (decrements
//! the top-ofstack pointer). If the TOP field contains a 0, it is set
//! to 7. The effect of this instruction is to rotate the stack by one
//! position. The contents of the FPU data registers and tag register
//! are not affected.
public final void fdecstp()
{
emitX86(INST_FDECSTP);
}
/** Divide @a dst by @a src (FPU). */
//!
//! @note One of @a dst or @a src register must be st(0).
public final void fdiv(X87Register dst, X87Register src)
{
assert(dst.index() == 0 || src.index() == 0);
emitX86(INST_FDIV, dst, src);
}
/** Divide st(0) by 32 bit or 64 bit FP value (FPU). */
public final void fdiv(Mem src)
{
emitX86(INST_FDIV, src);
}
/** Divide @a reg by st(0) (FPU). */
public final void fdivp(X87Register reg)
{
emitX86(INST_FDIVP, reg);
}
public final void fdivp()
{
fdivp(X87Register.st(1));
}
/** Reverse Divide @a dst by @a src (FPU). */
//!
//! @note One of @a dst or @a src register must be st(0).
public final void fdivr(X87Register dst, X87Register src)
{
assert(dst.index() == 0 || src.index() == 0);
emitX86(INST_FDIVR, dst, src);
}
/** Reverse Divide st(0) by 32 bit or 64 bit FP value (FPU). */
public final void fdivr(Mem src)
{
emitX86(INST_FDIVR, src);
}
/** Reverse Divide @a reg by st(0) (FPU). */
public final void fdivrp(X87Register reg)
{
emitX86(INST_FDIVRP, reg);
}
public final void fdivrp()
{
emitX86(INST_FDIVRP, X87Register.st(1));
}
/** Free Floating-Point Register (FPU). */
//!
//! Sets the tag in the FPU tag register associated with register @a reg
//! to empty (11B). The contents of @a reg and the FPU stack-top pointer
//! (TOP) are not affected.
public final void ffree(X87Register reg)
{
emitX86(INST_FFREE, reg);
}
/** Add 16 bit or 32 bit integer to st(0) (FPU). */
public final void fiadd(Mem src)
{
assert(src.size() == 2 || src.size() == 4);
emitX86(INST_FIADD, src);
}
/** Compare st(0) with 16 bit or 32 bit Integer (FPU). */
public final void ficom(Mem src)
{
assert(src.size() == 2 || src.size() == 4);
emitX86(INST_FICOM, src);
}
/** Compare st(0) with 16 bit or 32 bit Integer and pop the stack (FPU). */
public final void ficomp(Mem src)
{
assert(src.size() == 2 || src.size() == 4);
emitX86(INST_FICOMP, src);
}
/** Divide st(0) by 32 bit or 16 bit integer (@a src) (FPU). */
public final void fidiv(Mem src)
{
assert(src.size() == 2 || src.size() == 4);
emitX86(INST_FIDIV, src);
}
/** Reverse Divide st(0) by 32 bit or 16 bit integer (@a src) (FPU). */
public final void fidivr(Mem src)
{
assert(src.size() == 2 || src.size() == 4);
emitX86(INST_FIDIVR, src);
}
/** Load 16 bit, 32 bit or 64 bit Integer and push it to the stack (FPU). */
//!
//! Converts the signed-integer source operand into double extended-precision
//! floating point format and pushes the value onto the FPU register stack.
//! The source operand can be a word, doubleword, or quadword integer. It is
//! loaded without rounding errors. The sign of the source operand is
//! preserved.
public final void fild(Mem src)
{
assert(src.size() == 2 || src.size() == 4 || src.size() == 8);
emitX86(INST_FILD, src);
}
/** Multiply st(0) by 16 bit or 32 bit integer and store it */
//! to st(0) (FPU).
public final void fimul(Mem src)
{
assert(src.size() == 2 || src.size() == 4);
emitX86(INST_FIMUL, src);
}
/** Increment Stack-Top Pointer (FPU). */
//!
//! Adds one to the TOP field of the FPU status word (increments the
//! top-of-stack pointer). If the TOP field contains a 7, it is set to 0.
//! The effect of this instruction is to rotate the stack by one position.
//! The contents of the FPU data registers and tag register are not affected.
//! This operation is not equivalent to popping the stack, because the tag
//! for the previous top-of-stack register is not marked empty.
public final void fincstp()
{
emitX86(INST_FINCSTP);
}
/** Initialize Floating-Point Unit (FPU). */
//!
//! Initialize FPU after checking for pending unmasked floating-point
//! exceptions.
public final void finit()
{
emitX86(INST_FINIT);
}
/** Subtract 16 bit or 32 bit integer from st(0) and store result to */
//! st(0) (FPU).
public final void fisub(Mem src)
{
assert(src.size() == 2 || src.size() == 4);
emitX86(INST_FISUB, src);
}
/** Reverse Subtract 16 bit or 32 bit integer from st(0) and */
//! store result to st(0) (FPU).
public final void fisubr(Mem src)
{
assert(src.size() == 2 || src.size() == 4);
emitX86(INST_FISUBR, src);
}
/** Initialize Floating-Point Unit (FPU). */
//!
//! Initialize FPU without checking for pending unmasked floating-point
//! exceptions.
public final void fninit()
{
emitX86(INST_FNINIT);
}
/** Store st(0) as 16 bit or 32 bit Integer to @a dst (FPU). */
public final void fist(Mem dst)
{
assert(dst.size() == 2 || dst.size() == 4);
emitX86(INST_FIST, dst);
}
/** Store st(0) as 16 bit, 32 bit or 64 bit Integer to @a dst and pop */
//! stack (FPU).
public final void fistp(Mem dst)
{
assert(dst.size() == 2 || dst.size() == 4 || dst.size() == 8);
emitX86(INST_FISTP, dst);
}
/** Push 32 bit, 64 bit or 80 bit Floating Point Value onto the FPU */
//! register stack (FPU).
public final void fld(Mem src)
{
assert(src.size() == 4 || src.size() == 8 || src.size() == 10);
emitX86(INST_FLD, src);
}
/** Push @a reg onto the FPU register stack (FPU). */
public final void fld(X87Register reg)
{
emitX86(INST_FLD, reg);
}
/** Push +1.0 onto the FPU register stack (FPU). */
public final void fld1()
{
emitX86(INST_FLD1);
}
/** Push log2(10) onto the FPU register stack (FPU). */
public final void fldl2t()
{
emitX86(INST_FLDL2T);
}
/** Push log2(e) onto the FPU register stack (FPU). */
public final void fldl2e()
{
emitX86(INST_FLDL2E);
}
/** Push pi onto the FPU register stack (FPU). */
public final void fldpi()
{
emitX86(INST_FLDPI);
}
/** Push log10(2) onto the FPU register stack (FPU). */
public final void fldlg2()
{
emitX86(INST_FLDLG2);
}
/** Push ln(2) onto the FPU register stack (FPU). */
public final void fldln2()
{
emitX86(INST_FLDLN2);
}
/** Push +0.0 onto the FPU register stack (FPU). */
public final void fldz()
{
emitX86(INST_FLDZ);
}
/** Load x87 FPU Control Word (2 bytes) (FPU). */
public final void fldcw(Mem src)
{
emitX86(INST_FLDCW, src);
}
/** Load x87 FPU Environment (14 or 28 bytes) (FPU). */
public final void fldenv(Mem src)
{
emitX86(INST_FLDENV, src);
}
/** Multiply @a dst by @a src and store result in @a dst (FPU). */
//!
//! @note One of dst or src must be st(0).
public final void fmul(X87Register dst, X87Register src)
{
assert(dst.index() == 0 || src.index() == 0);
emitX86(INST_FMUL, dst, src);
}
/** Multiply st(0) by @a src and store result in st(0) (FPU). */
//!
//! @note SP-FP or DP-FP determined by @a adr size.
public final void fmul(Mem src)
{
emitX86(INST_FMUL, src);
}
/** Multiply st(0) by @a dst and POP register stack (FPU). */
public final void fmulp(X87Register dst)
{
emitX86(INST_FMULP, dst);
}
public final void fmulp()
{
fmulp(X87Register.st(1));
}
/** Clear Exceptions (FPU). */
//!
//! Clear floating-point exception flags without checking for pending
//! unmasked floating-point exceptions.
//!
//! Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE),
//! the exception summary status flag (ES), the stack fault flag (SF), and
//! the busy flag (B) in the FPU status word. The FCLEX instruction does
//! not checks for and handles any pending unmasked floating-point exceptions
//! before clearing the exception flags.
public final void fnclex()
{
emitX86(INST_FNCLEX);
}
/** No Operation (FPU). */
public final void fnop()
{
emitX86(INST_FNOP);
}
/** Save FPU State (FPU). */
//!
//! Store FPU environment to m94byte or m108byte without
//! checking for pending unmasked FP exceptions.
//! Then re-initialize the FPU.
public final void fnsave(Mem dst)
{
emitX86(INST_FNSAVE, dst);
}
/** Store x87 FPU Environment (FPU). */
//!
//! Store FPU environment to @a dst (14 or 28 Bytes) without checking for
//! pending unmasked floating-point exceptions. Then mask all floating
//! point exceptions.
public final void fnstenv(Mem dst)
{
emitX86(INST_FNSTENV, dst);
}
/** Store x87 FPU Control Word (FPU). */
//!
//! Store FPU control word to @a dst (2 Bytes) without checking for pending
//! unmasked floating-point exceptions.
public final void fnstcw(Mem dst)
{
emitX86(INST_FNSTCW, dst);
}
/** Store x87 FPU Status Word (2 Bytes) (FPU). */
public final void fnstsw(Register dst)
{
assert(dst.isRegCode(REG_AX));
emitX86(INST_FNSTSW, dst);
}
/** Store x87 FPU Status Word (2 Bytes) (FPU). */
public final void fnstsw(Mem dst)
{
emitX86(INST_FNSTSW, dst);
}
/** Partial Arctangent (FPU). */
//!
//! Replace st(1) with arctan(st(1)/st(0)) and pop the register stack.
public final void fpatan()
{
emitX86(INST_FPATAN);
}
/** Partial Remainder (FPU). */
//!
//! Replace st(0) with the remainder obtained from dividing st(0) by st(1).
public final void fprem()
{
emitX86(INST_FPREM);
}
/** Partial Remainder (FPU). */
//!
//! Replace st(0) with the IEEE remainder obtained from dividing st(0) by
//! st(1).
public final void fprem1()
{
emitX86(INST_FPREM1);
}
/** Partial Tangent (FPU). */
//!
//! Replace st(0) with its tangent and push 1 onto the FPU stack.
public final void fptan()
{
emitX86(INST_FPTAN);
}
/** Round to Integer (FPU). */
//!
//! Rount st(0) to an Integer.
public final void frndint()
{
emitX86(INST_FRNDINT);
}
/** Restore FPU State (FPU). */
//!
//! Load FPU state from src (94 bytes or 108 bytes).
public final void frstor(Mem src)
{
emitX86(INST_FRSTOR, src);
}
/** Save FPU State (FPU). */
//!
//! Store FPU state to 94 or 108 bytes after checking for
//! pending unmasked FP exceptions. Then reinitialize
//! the FPU.
public final void fsave(Mem dst)
{
emitX86(INST_FSAVE, dst);
}
/** Scale (FPU). */
//!
//! Scale st(0) by st(1).
public final void fscale()
{
emitX86(INST_FSCALE);
}
/** Sine (FPU). */
//!
//! This instruction calculates the sine of the source operand in
//! register st(0) and stores the result in st(0).
public final void fsin()
{
emitX86(INST_FSIN);
}
/** Sine and Cosine (FPU). */
//!
//! Compute the sine and cosine of st(0); replace st(0) with
//! the sine, and push the cosine onto the register stack.
public final void fsincos()
{
emitX86(INST_FSINCOS);
}
/** Square Root (FPU). */
//!
//! Calculates square root of st(0) and stores the result in st(0).
public final void fsqrt()
{
emitX86(INST_FSQRT);
}
/** Store Floating Point Value (FPU). */
//!
//! Store st(0) as 32 bit or 64 bit floating point value to @a dst.
public final void fst(Mem dst)
{
assert(dst.size() == 4 || dst.size() == 8);
emitX86(INST_FST, dst);
}
/** Store Floating Point Value (FPU). */
//!
//! Store st(0) to !a reg.
public final void fst(X87Register reg)
{
emitX86(INST_FST, reg);
}
/** Store Floating Point Value and Pop Register Stack (FPU). */
//!
//! Store st(0) as 32 bit or 64 bit floating point value to @a dst
//! and pop register stack.
public final void fstp(Mem dst)
{
assert(dst.size() == 4 || dst.size() == 8 || dst.size() == 10);
emitX86(INST_FSTP, dst);
}
/** Store Floating Point Value and Pop Register Stack (FPU). */
//!
//! Store st(0) to !a reg and pop register stack.
public final void fstp(X87Register reg)
{
emitX86(INST_FSTP, reg);
}
/** Store x87 FPU Control Word (FPU). */
//!
//! Store FPU control word to @a dst (2 Bytes) after checking for pending
//! unmasked floating-point exceptions.
public final void fstcw(Mem dst)
{
emitX86(INST_FSTCW, dst);
}
/** Store x87 FPU Environment (FPU). */
//!
//! Store FPU environment to @a dst (14 or 28 Bytes) after checking for
//! pending unmasked floating-point exceptions. Then mask all floating
//! point exceptions.
public final void fstenv(Mem dst)
{
emitX86(INST_FSTENV, dst);
}
/** Store x87 FPU Status Word (2 Bytes) (FPU). */
public final void fstsw(Register dst)
{
assert(dst.isRegCode(REG_AX));
emitX86(INST_FSTSW, dst);
}
/** Store x87 FPU Status Word (2 Bytes) (FPU). */
public final void fstsw(Mem dst)
{
emitX86(INST_FSTSW, dst);
}
/** Subtract @a src from @a dst and store result in @a dst (FPU). */
//!
//! @note One of dst or src must be st(0).
public final void fsub(X87Register dst, X87Register src)
{
assert(dst.index() == 0 || src.index() == 0);
emitX86(INST_FSUB, dst, src);
}
/** Subtract @a src from st(0) and store result in st(0) (FPU). */
//!
//! @note SP-FP or DP-FP determined by @a adr size.
public final void fsub(Mem src)
{
assert(src.size() == 4 || src.size() == 8);
emitX86(INST_FSUB, src);
}
/** Subtract st(0) from @a dst and POP register stack (FPU). */
public final void fsubp(X87Register dst)
{
emitX86(INST_FSUBP, dst);
}
public final void fsubp()
{
emitX86(INST_FSUBP, X87Register.st(1));
}
/** Reverse Subtract @a src from @a dst and store result in @a dst (FPU). */
//!
//! @note One of dst or src must be st(0).
public final void fsubr(X87Register dst, X87Register src)
{
assert(dst.index() == 0 || src.index() == 0);
emitX86(INST_FSUBR, dst, src);
}
/** Reverse Subtract @a src from st(0) and store result in st(0) (FPU). */
//!
//! @note SP-FP or DP-FP determined by @a adr size.
public final void fsubr(Mem src)
{
assert(src.size() == 4 || src.size() == 8);
emitX86(INST_FSUBR, src);
}
/** Reverse Subtract st(0) from @a dst and POP register stack (FPU). */
public final void fsubrp(X87Register dst)
{
emitX86(INST_FSUBRP, dst);
}
public final void fsubrp()
{
emitX86(INST_FSUBRP, X87Register.st(1));
}
/** Floating point test - Compare st(0) with 0.0. (FPU). */
public final void ftst()
{
emitX86(INST_FTST);
}
/** Unordered Compare st(0) with @a reg (FPU). */
public final void fucom(X87Register reg)
{
emitX86(INST_FUCOM, reg);
}
public final void fucom()
{
emitX86(INST_FUCOM, X87Register.st(1));
}
/** Unordered Compare st(0) and @a reg, check for ordered values */
//! and Set EFLAGS (FPU).
public final void fucomi(X87Register reg)
{
emitX86(INST_FUCOMI, reg);
}
/** UnorderedCompare st(0) and @a reg, Check for ordered values */
//! and Set EFLAGS and pop the stack (FPU).
public final void fucomip(X87Register reg)
{
emitX86(INST_FUCOMIP, reg);
}
public final void fucomip()
{
emitX86(INST_FUCOMIP, X87Register.st(1));
}
/** Unordered Compare st(0) with @a reg and pop register stack (FPU). */
public final void fucomp(X87Register reg)
{
emitX86(INST_FUCOMP, reg);
}
public final void fucomp()
{
emitX86(INST_FUCOMP, X87Register.st(1));
}
/** Unordered compare st(0) with st(1) and pop register stack twice */
//! (FPU).
public final void fucompp()
{
emitX86(INST_FUCOMPP);
}
public final void fwait()
{
emitX86(INST_FWAIT);
}
/** Examine st(0) (FPU). */
//!
//! Examines the contents of the ST(0) register and sets the condition code
//! flags C0, C2, and C3 in the FPU status word to indicate the class of
//! value or number in the register.
public final void fxam()
{
emitX86(INST_FXAM);
}
/** Exchange Register Contents (FPU). */
//!
//! Exchange content of st(0) with @a reg.
public final void fxch(X87Register reg)
{
emitX86(INST_FXCH, reg);
}
public final void fxch()
{
emitX86(INST_FXCH, X87Register.st(1));
}
/** Restore FP And MMX(tm) State And Streaming SIMD Extension State */
//! (FPU, MMX, SSE).
//!
//! Load FP and MMX(tm) technology and Streaming SIMD Extension state from
//! src (512 bytes).
public final void fxrstor(Mem src)
{
emitX86(INST_FXRSTOR, src);
}
/** Store FP and MMX(tm) State and Streaming SIMD Extension State */
//! (FPU, MMX, SSE).
//!
//! Store FP and MMX(tm) technology state and Streaming SIMD Extension state
//! to dst (512 bytes).
public final void fxsave(Mem dst)
{
emitX86(INST_FXSAVE, dst);
}
/** Extract Exponent and Significand (FPU). */
//!
//! Separate value in st(0) into exponent and significand, store exponent
//! in st(0), and push the significand onto the register stack.
public final void fxtract()
{
emitX86(INST_FXTRACT);
}
/** Compute y * log2(x). */
//!
//! Replace st(1) with (st(1) * log2st(0)) and pop the register stack.
public final void fyl2x()
{
emitX86(INST_FYL2X);
}
/** Compute y * log_2(x+1). */
//!
//! Replace st(1) with (st(1) * (log2st(0) + 1.0)) and pop the register stack.
public final void fyl2xp1()
{
emitX86(INST_FYL2XP1);
}
// -------------------------------------------------------------------------
// [MMX]
// -------------------------------------------------------------------------
/** Empty MMX state. */
public final void emms()
{
emitX86(INST_EMMS);
}
/** Move DWord (MMX). */
public final void movd(Mem dst, MMRegister src)
{
emitX86(INST_MOVD, dst, src);
}
/** Move DWord (MMX). */
public final void movd(Register dst, MMRegister src)
{
emitX86(INST_MOVD, dst, src);
}
/** Move DWord (MMX). */
public final void movd(MMRegister dst, Mem src)
{
emitX86(INST_MOVD, dst, src);
}
/** Move DWord (MMX). */
public final void movd(MMRegister dst, Register src)
{
emitX86(INST_MOVD, dst, src);
}
/** Move QWord (MMX). */
public final void movq(MMRegister dst, MMRegister src)
{
emitX86(INST_MOVQ, dst, src);
}
/** Move QWord (MMX). */
public final void movq(Mem dst, MMRegister src)
{
emitX86(INST_MOVQ, dst, src);
}
/** Move QWord (MMX). */
public final void movq(Register dst, MMRegister src)
{
emitX86(INST_MOVQ, dst, src);
}
/** Move QWord (MMX). */
public final void movq(MMRegister dst, Mem src)
{
emitX86(INST_MOVQ, dst, src);
}
/** Move QWord (MMX). */
public final void movq(MMRegister dst, Register src)
{
emitX86(INST_MOVQ, dst, src);
}
/** Pack with Unsigned Saturation (MMX). */
public final void packuswb(MMRegister dst, MMRegister src)
{
emitX86(INST_PACKUSWB, dst, src);
}
/** Pack with Unsigned Saturation (MMX). */
public final void packuswb(MMRegister dst, Mem src)
{
emitX86(INST_PACKUSWB, dst, src);
}
/** Packed BYTE Add (MMX). */
public final void paddb(MMRegister dst, MMRegister src)
{
emitX86(INST_PADDB, dst, src);
}
/** Packed BYTE Add (MMX). */
public final void paddb(MMRegister dst, Mem src)
{
emitX86(INST_PADDB, dst, src);
}
/** Packed WORD Add (MMX). */
public final void paddw(MMRegister dst, MMRegister src)
{
emitX86(INST_PADDW, dst, src);
}
/** Packed WORD Add (MMX). */
public final void paddw(MMRegister dst, Mem src)
{
emitX86(INST_PADDW, dst, src);
}
/** Packed DWORD Add (MMX). */
public final void paddd(MMRegister dst, MMRegister src)
{
emitX86(INST_PADDD, dst, src);
}
/** Packed DWORD Add (MMX). */
public final void paddd(MMRegister dst, Mem src)
{
emitX86(INST_PADDD, dst, src);
}
/** Packed Add with Saturation (MMX). */
public final void paddsb(MMRegister dst, MMRegister src)
{
emitX86(INST_PADDSB, dst, src);
}
/** Packed Add with Saturation (MMX). */
public final void paddsb(MMRegister dst, Mem src)
{
emitX86(INST_PADDSB, dst, src);
}
/** Packed Add with Saturation (MMX). */
public final void paddsw(MMRegister dst, MMRegister src)
{
emitX86(INST_PADDSW, dst, src);
}
/** Packed Add with Saturation (MMX). */
public final void paddsw(MMRegister dst, Mem src)
{
emitX86(INST_PADDSW, dst, src);
}
/** Packed Add Unsigned with Saturation (MMX). */
public final void paddusb(MMRegister dst, MMRegister src)
{
emitX86(INST_PADDUSB, dst, src);
}
/** Packed Add Unsigned with Saturation (MMX). */
public final void paddusb(MMRegister dst, Mem src)
{
emitX86(INST_PADDUSB, dst, src);
}
/** Packed Add Unsigned with Saturation (MMX). */
public final void paddusw(MMRegister dst, MMRegister src)
{
emitX86(INST_PADDUSW, dst, src);
}
/** Packed Add Unsigned with Saturation (MMX). */
public final void paddusw(MMRegister dst, Mem src)
{
emitX86(INST_PADDUSW, dst, src);
}
/** Logical AND (MMX). */
public final void pand(MMRegister dst, MMRegister src)
{
emitX86(INST_PAND, dst, src);
}
/** Logical AND (MMX). */
public final void pand(MMRegister dst, Mem src)
{
emitX86(INST_PAND, dst, src);
}
/** Logical AND Not (MMX). */
public final void pandn(MMRegister dst, MMRegister src)
{
emitX86(INST_PANDN, dst, src);
}
/** Logical AND Not (MMX). */
public final void pandn(MMRegister dst, Mem src)
{
emitX86(INST_PANDN, dst, src);
}
/** Packed Compare for Equal (BYTES) (MMX). */
public final void pcmpeqb(MMRegister dst, MMRegister src)
{
emitX86(INST_PCMPEQB, dst, src);
}
/** Packed Compare for Equal (BYTES) (MMX). */
public final void pcmpeqb(MMRegister dst, Mem src)
{
emitX86(INST_PCMPEQB, dst, src);
}
/** Packed Compare for Equal (WORDS) (MMX). */
public final void pcmpeqw(MMRegister dst, MMRegister src)
{
emitX86(INST_PCMPEQW, dst, src);
}
/** Packed Compare for Equal (WORDS) (MMX). */
public final void pcmpeqw(MMRegister dst, Mem src)
{
emitX86(INST_PCMPEQW, dst, src);
}
/** Packed Compare for Equal (DWORDS) (MMX). */
public final void pcmpeqd(MMRegister dst, MMRegister src)
{
emitX86(INST_PCMPEQD, dst, src);
}
/** Packed Compare for Equal (DWORDS) (MMX). */
public final void pcmpeqd(MMRegister dst, Mem src)
{
emitX86(INST_PCMPEQD, dst, src);
}
/** Packed Compare for Greater Than (BYTES) (MMX). */
public final void pcmpgtb(MMRegister dst, MMRegister src)
{
emitX86(INST_PCMPGTB, dst, src);
}
/** Packed Compare for Greater Than (BYTES) (MMX). */
public final void pcmpgtb(MMRegister dst, Mem src)
{
emitX86(INST_PCMPGTB, dst, src);
}
/** Packed Compare for Greater Than (WORDS) (MMX). */
public final void pcmpgtw(MMRegister dst, MMRegister src)
{
emitX86(INST_PCMPGTW, dst, src);
}
/** Packed Compare for Greater Than (WORDS) (MMX). */
public final void pcmpgtw(MMRegister dst, Mem src)
{
emitX86(INST_PCMPGTW, dst, src);
}
/** Packed Compare for Greater Than (DWORDS) (MMX). */
public final void pcmpgtd(MMRegister dst, MMRegister src)
{
emitX86(INST_PCMPGTD, dst, src);
}
/** Packed Compare for Greater Than (DWORDS) (MMX). */
public final void pcmpgtd(MMRegister dst, Mem src)
{
emitX86(INST_PCMPGTD, dst, src);
}
/** Packed Multiply High (MMX). */
public final void pmulhw(MMRegister dst, MMRegister src)
{
emitX86(INST_PMULHW, dst, src);
}
/** Packed Multiply High (MMX). */
public final void pmulhw(MMRegister dst, Mem src)
{
emitX86(INST_PMULHW, dst, src);
}
/** Packed Multiply Low (MMX). */
public final void pmullw(MMRegister dst, MMRegister src)
{
emitX86(INST_PMULLW, dst, src);
}
/** Packed Multiply Low (MMX). */
public final void pmullw(MMRegister dst, Mem src)
{
emitX86(INST_PMULLW, dst, src);
}
/** Bitwise Logical OR (MMX). */
public final void por(MMRegister dst, MMRegister src)
{
emitX86(INST_POR, dst, src);
}
/** Bitwise Logical OR (MMX). */
public final void por(MMRegister dst, Mem src)
{
emitX86(INST_POR, dst, src);
}
/** Packed Multiply and Add (MMX). */
public final void pmaddwd(MMRegister dst, MMRegister src)
{
emitX86(INST_PMADDWD, dst, src);
}
/** Packed Multiply and Add (MMX). */
public final void pmaddwd(MMRegister dst, Mem src)
{
emitX86(INST_PMADDWD, dst, src);
}
/** Packed Shift Left Logical (MMX). */
public final void pslld(MMRegister dst, MMRegister src)
{
emitX86(INST_PSLLD, dst, src);
}
/** Packed Shift Left Logical (MMX). */
public final void pslld(MMRegister dst, Mem src)
{
emitX86(INST_PSLLD, dst, src);
}
/** Packed Shift Left Logical (MMX). */
public final void pslld(MMRegister dst, Immediate src)
{
emitX86(INST_PSLLD, dst, src);
}
/** Packed Shift Left Logical (MMX). */
public final void psllq(MMRegister dst, MMRegister src)
{
emitX86(INST_PSLLQ, dst, src);
}
/** Packed Shift Left Logical (MMX). */
public final void psllq(MMRegister dst, Mem src)
{
emitX86(INST_PSLLQ, dst, src);
}
/** Packed Shift Left Logical (MMX). */
public final void psllq(MMRegister dst, Immediate src)
{
emitX86(INST_PSLLQ, dst, src);
}
/** Packed Shift Left Logical (MMX). */
public final void psllw(MMRegister dst, MMRegister src)
{
emitX86(INST_PSLLW, dst, src);
}
/** Packed Shift Left Logical (MMX). */
public final void psllw(MMRegister dst, Mem src)
{
emitX86(INST_PSLLW, dst, src);
}
/** Packed Shift Left Logical (MMX). */
public final void psllw(MMRegister dst, Immediate src)
{
emitX86(INST_PSLLW, dst, src);
}
/** Packed Shift Right Arithmetic (MMX). */
public final void psrad(MMRegister dst, MMRegister src)
{
emitX86(INST_PSRAD, dst, src);
}
/** Packed Shift Right Arithmetic (MMX). */
public final void psrad(MMRegister dst, Mem src)
{
emitX86(INST_PSRAD, dst, src);
}
/** Packed Shift Right Arithmetic (MMX). */
public final void psrad(MMRegister dst, Immediate src)
{
emitX86(INST_PSRAD, dst, src);
}
/** Packed Shift Right Arithmetic (MMX). */
public final void psraw(MMRegister dst, MMRegister src)
{
emitX86(INST_PSRAW, dst, src);
}
/** Packed Shift Right Arithmetic (MMX). */
public final void psraw(MMRegister dst, Mem src)
{
emitX86(INST_PSRAW, dst, src);
}
/** Packed Shift Right Arithmetic (MMX). */
public final void psraw(MMRegister dst, Immediate src)
{
emitX86(INST_PSRAW, dst, src);
}
/** Packed Shift Right Logical (MMX). */
public final void psrld(MMRegister dst, MMRegister src)
{
emitX86(INST_PSRLD, dst, src);
}
/** Packed Shift Right Logical (MMX). */
public final void psrld(MMRegister dst, Mem src)
{
emitX86(INST_PSRLD, dst, src);
}
/** Packed Shift Right Logical (MMX). */
public final void psrld(MMRegister dst, Immediate src)
{
emitX86(INST_PSRLD, dst, src);
}
/** Packed Shift Right Logical (MMX). */
public final void psrlq(MMRegister dst, MMRegister src)
{
emitX86(INST_PSRLQ, dst, src);
}
/** Packed Shift Right Logical (MMX). */
public final void psrlq(MMRegister dst, Mem src)
{
emitX86(INST_PSRLQ, dst, src);
}
/** Packed Shift Right Logical (MMX). */
public final void psrlq(MMRegister dst, Immediate src)
{
emitX86(INST_PSRLQ, dst, src);
}
/** Packed Shift Right Logical (MMX). */
public final void psrlw(MMRegister dst, MMRegister src)
{
emitX86(INST_PSRLW, dst, src);
}
/** Packed Shift Right Logical (MMX). */
public final void psrlw(MMRegister dst, Mem src)
{
emitX86(INST_PSRLW, dst, src);
}
/** Packed Shift Right Logical (MMX). */
public final void psrlw(MMRegister dst, Immediate src)
{
emitX86(INST_PSRLW, dst, src);
}
/** Packed Subtract (MMX). */
public final void psubb(MMRegister dst, MMRegister src)
{
emitX86(INST_PSUBB, dst, src);
}
/** Packed Subtract (MMX). */
public final void psubb(MMRegister dst, Mem src)
{
emitX86(INST_PSUBB, dst, src);
}
/** Packed Subtract (MMX). */
public final void psubw(MMRegister dst, MMRegister src)
{
emitX86(INST_PSUBW, dst, src);
}
/** Packed Subtract (MMX). */
public final void psubw(MMRegister dst, Mem src)
{
emitX86(INST_PSUBW, dst, src);
}
/** Packed Subtract (MMX). */
public final void psubd(MMRegister dst, MMRegister src)
{
emitX86(INST_PSUBD, dst, src);
}
/** Packed Subtract (MMX). */
public final void psubd(MMRegister dst, Mem src)
{
emitX86(INST_PSUBD, dst, src);
}
/** Packed Subtract with Saturation (MMX). */
public final void psubsb(MMRegister dst, MMRegister src)
{
emitX86(INST_PSUBSB, dst, src);
}
/** Packed Subtract with Saturation (MMX). */
public final void psubsb(MMRegister dst, Mem src)
{
emitX86(INST_PSUBSB, dst, src);
}
/** Packed Subtract with Saturation (MMX). */
public final void psubsw(MMRegister dst, MMRegister src)
{
emitX86(INST_PSUBSW, dst, src);
}
/** Packed Subtract with Saturation (MMX). */
public final void psubsw(MMRegister dst, Mem src)
{
emitX86(INST_PSUBSW, dst, src);
}
/** Packed Subtract with Unsigned Saturation (MMX). */
public final void psubusb(MMRegister dst, MMRegister src)
{
emitX86(INST_PSUBUSB, dst, src);
}
/** Packed Subtract with Unsigned Saturation (MMX). */
public final void psubusb(MMRegister dst, Mem src)
{
emitX86(INST_PSUBUSB, dst, src);
}
/** Packed Subtract with Unsigned Saturation (MMX). */
public final void psubusw(MMRegister dst, MMRegister src)
{
emitX86(INST_PSUBUSW, dst, src);
}
/** Packed Subtract with Unsigned Saturation (MMX). */
public final void psubusw(MMRegister dst, Mem src)
{
emitX86(INST_PSUBUSW, dst, src);
}
/** Unpack High Packed Data (MMX). */
public final void punpckhbw(MMRegister dst, MMRegister src)
{
emitX86(INST_PUNPCKHBW, dst, src);
}
/** Unpack High Packed Data (MMX). */
public final void punpckhbw(MMRegister dst, Mem src)
{
emitX86(INST_PUNPCKHBW, dst, src);
}
/** Unpack High Packed Data (MMX). */
public final void punpckhwd(MMRegister dst, MMRegister src)
{
emitX86(INST_PUNPCKHWD, dst, src);
}
/** Unpack High Packed Data (MMX). */
public final void punpckhwd(MMRegister dst, Mem src)
{
emitX86(INST_PUNPCKHWD, dst, src);
}
/** Unpack High Packed Data (MMX). */
public final void punpckhdq(MMRegister dst, MMRegister src)
{
emitX86(INST_PUNPCKHDQ, dst, src);
}
/** Unpack High Packed Data (MMX). */
public final void punpckhdq(MMRegister dst, Mem src)
{
emitX86(INST_PUNPCKHDQ, dst, src);
}
/** Unpack High Packed Data (MMX). */
public final void punpcklbw(MMRegister dst, MMRegister src)
{
emitX86(INST_PUNPCKLBW, dst, src);
}
/** Unpack High Packed Data (MMX). */
public final void punpcklbw(MMRegister dst, Mem src)
{
emitX86(INST_PUNPCKLBW, dst, src);
}
/** Unpack High Packed Data (MMX). */
public final void punpcklwd(MMRegister dst, MMRegister src)
{
emitX86(INST_PUNPCKLWD, dst, src);
}
/** Unpack High Packed Data (MMX). */
public final void punpcklwd(MMRegister dst, Mem src)
{
emitX86(INST_PUNPCKLWD, dst, src);
}
/** Unpack High Packed Data (MMX). */
public final void punpckldq(MMRegister dst, MMRegister src)
{
emitX86(INST_PUNPCKLDQ, dst, src);
}
/** Unpack High Packed Data (MMX). */
public final void punpckldq(MMRegister dst, Mem src)
{
emitX86(INST_PUNPCKLDQ, dst, src);
}
/** Bitwise Exclusive OR (MMX). */
public final void pxor(MMRegister dst, MMRegister src)
{
emitX86(INST_PXOR, dst, src);
}
/** Bitwise Exclusive OR (MMX). */
public final void pxor(MMRegister dst, Mem src)
{
emitX86(INST_PXOR, dst, src);
}
// -------------------------------------------------------------------------
// [3dNow]
// -------------------------------------------------------------------------
/** Faster EMMS (3dNow!). */
//!
//! @note Use only for early AMD processors where is only 3dNow! or SSE. If
//! CPU contains SSE2, it's better to use @c emms() ( @c femms() is mapped
//! to @c emms() ).
public final void femms()
{
emitX86(INST_FEMMS);
}
/** Packed SP-FP to Integer Convert (3dNow!). */
public final void pf2id(MMRegister dst, MMRegister src)
{
emitX86(INST_PF2ID, dst, src);
}
/** Packed SP-FP to Integer Convert (3dNow!). */
public final void pf2id(MMRegister dst, Mem src)
{
emitX86(INST_PF2ID, dst, src);
}
/** Packed SP-FP to Integer Word Convert (3dNow!). */
public final void pf2iw(MMRegister dst, MMRegister src)
{
emitX86(INST_PF2IW, dst, src);
}
/** Packed SP-FP to Integer Word Convert (3dNow!). */
public final void pf2iw(MMRegister dst, Mem src)
{
emitX86(INST_PF2IW, dst, src);
}
/** Packed SP-FP Accumulate (3dNow!). */
public final void pfacc(MMRegister dst, MMRegister src)
{
emitX86(INST_PFACC, dst, src);
}
/** Packed SP-FP Accumulate (3dNow!). */
public final void pfacc(MMRegister dst, Mem src)
{
emitX86(INST_PFACC, dst, src);
}
/** Packed SP-FP Addition (3dNow!). */
public final void pfadd(MMRegister dst, MMRegister src)
{
emitX86(INST_PFADD, dst, src);
}
/** Packed SP-FP Addition (3dNow!). */
public final void pfadd(MMRegister dst, Mem src)
{
emitX86(INST_PFADD, dst, src);
}
/** Packed SP-FP Compare - dst == src (3dNow!). */
public final void pfcmpeq(MMRegister dst, MMRegister src)
{
emitX86(INST_PFCMPEQ, dst, src);
}
/** Packed SP-FP Compare - dst == src (3dNow!). */
public final void pfcmpeq(MMRegister dst, Mem src)
{
emitX86(INST_PFCMPEQ, dst, src);
}
/** Packed SP-FP Compare - dst >= src (3dNow!). */
public final void pfcmpge(MMRegister dst, MMRegister src)
{
emitX86(INST_PFCMPGE, dst, src);
}
/** Packed SP-FP Compare - dst >= src (3dNow!). */
public final void pfcmpge(MMRegister dst, Mem src)
{
emitX86(INST_PFCMPGE, dst, src);
}
/** Packed SP-FP Compare - dst > src (3dNow!). */
public final void pfcmpgt(MMRegister dst, MMRegister src)
{
emitX86(INST_PFCMPGT, dst, src);
}
/** Packed SP-FP Compare - dst > src (3dNow!). */
public final void pfcmpgt(MMRegister dst, Mem src)
{
emitX86(INST_PFCMPGT, dst, src);
}
/** Packed SP-FP Maximum (3dNow!). */
public final void pfmax(MMRegister dst, MMRegister src)
{
emitX86(INST_PFMAX, dst, src);
}
/** Packed SP-FP Maximum (3dNow!). */
public final void pfmax(MMRegister dst, Mem src)
{
emitX86(INST_PFMAX, dst, src);
}
/** Packed SP-FP Minimum (3dNow!). */
public final void pfmin(MMRegister dst, MMRegister src)
{
emitX86(INST_PFMIN, dst, src);
}
/** Packed SP-FP Minimum (3dNow!). */
public final void pfmin(MMRegister dst, Mem src)
{
emitX86(INST_PFMIN, dst, src);
}
/** Packed SP-FP Multiply (3dNow!). */
public final void pfmul(MMRegister dst, MMRegister src)
{
emitX86(INST_PFMUL, dst, src);
}
/** Packed SP-FP Multiply (3dNow!). */
public final void pfmul(MMRegister dst, Mem src)
{
emitX86(INST_PFMUL, dst, src);
}
/** Packed SP-FP Negative Accumulate (3dNow!). */
public final void pfnacc(MMRegister dst, MMRegister src)
{
emitX86(INST_PFNACC, dst, src);
}
/** Packed SP-FP Negative Accumulate (3dNow!). */
public final void pfnacc(MMRegister dst, Mem src)
{
emitX86(INST_PFNACC, dst, src);
}
/** Packed SP-FP Mixed Accumulate (3dNow!). */
public final void pfpnaxx(MMRegister dst, MMRegister src)
{
emitX86(INST_PFPNACC, dst, src);
}
/** Packed SP-FP Mixed Accumulate (3dNow!). */
public final void pfpnacc(MMRegister dst, Mem src)
{
emitX86(INST_PFPNACC, dst, src);
}
/** Packed SP-FP Reciprocal Approximation (3dNow!). */
public final void pfrcp(MMRegister dst, MMRegister src)
{
emitX86(INST_PFRCP, dst, src);
}
/** Packed SP-FP Reciprocal Approximation (3dNow!). */
public final void pfrcp(MMRegister dst, Mem src)
{
emitX86(INST_PFRCP, dst, src);
}
/** Packed SP-FP Reciprocal, First Iteration Step (3dNow!). */
public final void pfrcpit1(MMRegister dst, MMRegister src)
{
emitX86(INST_PFRCPIT1, dst, src);
}
/** Packed SP-FP Reciprocal, First Iteration Step (3dNow!). */
public final void pfrcpit1(MMRegister dst, Mem src)
{
emitX86(INST_PFRCPIT1, dst, src);
}
/** Packed SP-FP Reciprocal, Second Iteration Step (3dNow!). */
public final void pfrcpit2(MMRegister dst, MMRegister src)
{
emitX86(INST_PFRCPIT2, dst, src);
}
/** Packed SP-FP Reciprocal, Second Iteration Step (3dNow!). */
public final void pfrcpit2(MMRegister dst, Mem src)
{
emitX86(INST_PFRCPIT2, dst, src);
}
/** Packed SP-FP Reciprocal Square Root, First Iteration Step (3dNow!). */
public final void pfrsqit1(MMRegister dst, MMRegister src)
{
emitX86(INST_PFRSQIT1, dst, src);
}
/** Packed SP-FP Reciprocal Square Root, First Iteration Step (3dNow!). */
public final void pfrsqit1(MMRegister dst, Mem src)
{
emitX86(INST_PFRSQIT1, dst, src);
}
/** Packed SP-FP Reciprocal Square Root Approximation (3dNow!). */
public final void pfrsqrt(MMRegister dst, MMRegister src)
{
emitX86(INST_PFRSQRT, dst, src);
}
/** Packed SP-FP Reciprocal Square Root Approximation (3dNow!). */
public final void pfrsqrt(MMRegister dst, Mem src)
{
emitX86(INST_PFRSQRT, dst, src);
}
/** Packed SP-FP Subtract (3dNow!). */
public final void pfsub(MMRegister dst, MMRegister src)
{
emitX86(INST_PFSUB, dst, src);
}
/** Packed SP-FP Subtract (3dNow!). */
public final void pfsub(MMRegister dst, Mem src)
{
emitX86(INST_PFSUB, dst, src);
}
/** Packed SP-FP Reverse Subtract (3dNow!). */
public final void pfsubr(MMRegister dst, MMRegister src)
{
emitX86(INST_PFSUBR, dst, src);
}
/** Packed SP-FP Reverse Subtract (3dNow!). */
public final void pfsubr(MMRegister dst, Mem src)
{
emitX86(INST_PFSUBR, dst, src);
}
/** Packed DWords to SP-FP (3dNow!). */
public final void pi2fd(MMRegister dst, MMRegister src)
{
emitX86(INST_PI2FD, dst, src);
}
/** Packed DWords to SP-FP (3dNow!). */
public final void pi2fd(MMRegister dst, Mem src)
{
emitX86(INST_PI2FD, dst, src);
}
/** Packed Words to SP-FP (3dNow!). */
public final void pi2fw(MMRegister dst, MMRegister src)
{
emitX86(INST_PI2FW, dst, src);
}
/** Packed Words to SP-FP (3dNow!). */
public final void pi2fw(MMRegister dst, Mem src)
{
emitX86(INST_PI2FW, dst, src);
}
/** Packed swap DWord (3dNow!) */
public final void pswapd(MMRegister dst, MMRegister src)
{
emitX86(INST_PSWAPD, dst, src);
}
/** Packed swap DWord (3dNow!) */
public final void pswapd(MMRegister dst, Mem src)
{
emitX86(INST_PSWAPD, dst, src);
}
// -------------------------------------------------------------------------
// [SSE]
// -------------------------------------------------------------------------
/** Packed SP-FP Add (SSE). */
public final void addps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_ADDPS, dst, src);
}
/** Packed SP-FP Add (SSE). */
public final void addps(XMMRegister dst, Mem src)
{
emitX86(INST_ADDPS, dst, src);
}
/** Scalar SP-FP Add (SSE). */
public final void addss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_ADDSS, dst, src);
}
/** Scalar SP-FP Add (SSE). */
public final void addss(XMMRegister dst, Mem src)
{
emitX86(INST_ADDSS, dst, src);
}
/** Bit-wise Logical And Not For SP-FP (SSE). */
public final void andnps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_ANDNPS, dst, src);
}
/** Bit-wise Logical And Not For SP-FP (SSE). */
public final void andnps(XMMRegister dst, Mem src)
{
emitX86(INST_ANDNPS, dst, src);
}
/** Bit-wise Logical And For SP-FP (SSE). */
public final void andps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_ANDPS, dst, src);
}
/** Bit-wise Logical And For SP-FP (SSE). */
public final void andps(XMMRegister dst, Mem src)
{
emitX86(INST_ANDPS, dst, src);
}
/** Packed SP-FP Compare (SSE). */
public final void cmpps(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_CMPPS, dst, src, imm8);
}
/** Packed SP-FP Compare (SSE). */
public final void cmpps(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_CMPPS, dst, src, imm8);
}
/** Compare Scalar SP-FP Values (SSE). */
public final void cmpss(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_CMPSS, dst, src, imm8);
}
/** Compare Scalar SP-FP Values (SSE). */
public final void cmpss(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_CMPSS, dst, src, imm8);
}
/** Scalar Ordered SP-FP Compare and Set EFLAGS (SSE). */
public final void comiss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_COMISS, dst, src);
}
/** Scalar Ordered SP-FP Compare and Set EFLAGS (SSE). */
public final void comiss(XMMRegister dst, Mem src)
{
emitX86(INST_COMISS, dst, src);
}
/** Packed Signed INT32 to Packed SP-FP Conversion (SSE). */
public final void cvtpi2ps(XMMRegister dst, MMRegister src)
{
emitX86(INST_CVTPI2PS, dst, src);
}
/** Packed Signed INT32 to Packed SP-FP Conversion (SSE). */
public final void cvtpi2ps(XMMRegister dst, Mem src)
{
emitX86(INST_CVTPI2PS, dst, src);
}
/** Packed SP-FP to Packed INT32 Conversion (SSE). */
public final void cvtps2pi(MMRegister dst, XMMRegister src)
{
emitX86(INST_CVTPS2PI, dst, src);
}
/** Packed SP-FP to Packed INT32 Conversion (SSE). */
public final void cvtps2pi(MMRegister dst, Mem src)
{
emitX86(INST_CVTPS2PI, dst, src);
}
/** Scalar Signed INT32 to SP-FP Conversion (SSE). */
public final void cvtsi2ss(XMMRegister dst, Register src)
{
emitX86(INST_CVTSI2SS, dst, src);
}
/** Scalar Signed INT32 to SP-FP Conversion (SSE). */
public final void cvtsi2ss(XMMRegister dst, Mem src)
{
emitX86(INST_CVTSI2SS, dst, src);
}
/** Scalar SP-FP to Signed INT32 Conversion (SSE). */
public final void cvtss2si(Register dst, XMMRegister src)
{
emitX86(INST_CVTSS2SI, dst, src);
}
/** Scalar SP-FP to Signed INT32 Conversion (SSE). */
public final void cvtss2si(Register dst, Mem src)
{
emitX86(INST_CVTSS2SI, dst, src);
}
/** Packed SP-FP to Packed INT32 Conversion (truncate) (SSE). */
public final void cvttps2pi(MMRegister dst, XMMRegister src)
{
emitX86(INST_CVTTPS2PI, dst, src);
}
/** Packed SP-FP to Packed INT32 Conversion (truncate) (SSE). */
public final void cvttps2pi(MMRegister dst, Mem src)
{
emitX86(INST_CVTTPS2PI, dst, src);
}
/** Scalar SP-FP to Signed INT32 Conversion (truncate) (SSE). */
public final void cvttss2si(Register dst, XMMRegister src)
{
emitX86(INST_CVTTSS2SI, dst, src);
}
/** Scalar SP-FP to Signed INT32 Conversion (truncate) (SSE). */
public final void cvttss2si(Register dst, Mem src)
{
emitX86(INST_CVTTSS2SI, dst, src);
}
/** Packed SP-FP Divide (SSE). */
public final void divps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_DIVPS, dst, src);
}
/** Packed SP-FP Divide (SSE). */
public final void divps(XMMRegister dst, Mem src)
{
emitX86(INST_DIVPS, dst, src);
}
/** Scalar SP-FP Divide (SSE). */
public final void divss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_DIVSS, dst, src);
}
/** Scalar SP-FP Divide (SSE). */
public final void divss(XMMRegister dst, Mem src)
{
emitX86(INST_DIVSS, dst, src);
}
/** Load Streaming SIMD Extension Control/Status (SSE). */
public final void ldmxcsr(Mem src)
{
emitX86(INST_LDMXCSR, src);
}
/** Byte Mask Write (SSE). */
//!
//! @note The default memory location is specified by DS:EDI.
public final void maskmovq(MMRegister data, MMRegister mask)
{
emitX86(INST_MASKMOVQ, data, mask);
}
/** Packed SP-FP Maximum (SSE). */
public final void maxps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MAXPS, dst, src);
}
/** Packed SP-FP Maximum (SSE). */
public final void maxps(XMMRegister dst, Mem src)
{
emitX86(INST_MAXPS, dst, src);
}
/** Scalar SP-FP Maximum (SSE). */
public final void maxss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MAXSS, dst, src);
}
/** Scalar SP-FP Maximum (SSE). */
public final void maxss(XMMRegister dst, Mem src)
{
emitX86(INST_MAXSS, dst, src);
}
/** Packed SP-FP Minimum (SSE). */
public final void minps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MINPS, dst, src);
}
/** Packed SP-FP Minimum (SSE). */
public final void minps(XMMRegister dst, Mem src)
{
emitX86(INST_MINPS, dst, src);
}
/** Scalar SP-FP Minimum (SSE). */
public final void minss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MINSS, dst, src);
}
/** Scalar SP-FP Minimum (SSE). */
public final void minss(XMMRegister dst, Mem src)
{
emitX86(INST_MINSS, dst, src);
}
/** Move Aligned Packed SP-FP Values (SSE). */
public final void movaps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVAPS, dst, src);
}
/** Move Aligned Packed SP-FP Values (SSE). */
public final void movaps(XMMRegister dst, Mem src)
{
emitX86(INST_MOVAPS, dst, src);
}
/** Move Aligned Packed SP-FP Values (SSE). */
public final void movaps(Mem dst, XMMRegister src)
{
emitX86(INST_MOVAPS, dst, src);
}
/** Move DWord. */
public final void movd(Mem dst, XMMRegister src)
{
emitX86(INST_MOVD, dst, src);
}
/** Move DWord. */
public final void movd(Register dst, XMMRegister src)
{
emitX86(INST_MOVD, dst, src);
}
/** Move DWord. */
public final void movd(XMMRegister dst, Mem src)
{
emitX86(INST_MOVD, dst, src);
}
/** Move DWord. */
public final void movd(XMMRegister dst, Register src)
{
emitX86(INST_MOVD, dst, src);
}
/** Move QWord (SSE). */
public final void movq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVQ, dst, src);
}
/** Move QWord (SSE). */
public final void movq(Mem dst, XMMRegister src)
{
emitX86(INST_MOVQ, dst, src);
}
/** Move QWord (SSE). */
public final void movq(Register dst, XMMRegister src)
{
emitX86(INST_MOVQ, dst, src);
}
/** Move QWord (SSE). */
public final void movq(XMMRegister dst, Mem src)
{
emitX86(INST_MOVQ, dst, src);
}
/** Move QWord (SSE). */
public final void movq(XMMRegister dst, Register src)
{
emitX86(INST_MOVQ, dst, src);
}
/** Move 64 Bits Non Temporal (SSE). */
public final void movntq(Mem dst, MMRegister src)
{
emitX86(INST_MOVNTQ, dst, src);
}
/** High to Low Packed SP-FP (SSE). */
public final void movhlps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVHLPS, dst, src);
}
/** Move High Packed SP-FP (SSE). */
public final void movhps(XMMRegister dst, Mem src)
{
emitX86(INST_MOVHPS, dst, src);
}
/** Move High Packed SP-FP (SSE). */
public final void movhps(Mem dst, XMMRegister src)
{
emitX86(INST_MOVHPS, dst, src);
}
/** Move Low to High Packed SP-FP (SSE). */
public final void movlhps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVLHPS, dst, src);
}
/** Move Low Packed SP-FP (SSE). */
public final void movlps(XMMRegister dst, Mem src)
{
emitX86(INST_MOVLPS, dst, src);
}
/** Move Low Packed SP-FP (SSE). */
public final void movlps(Mem dst, XMMRegister src)
{
emitX86(INST_MOVLPS, dst, src);
}
/** Move Aligned Four Packed SP-FP Non Temporal (SSE). */
public final void movntps(Mem dst, XMMRegister src)
{
emitX86(INST_MOVNTPS, dst, src);
}
/** Move Scalar SP-FP (SSE). */
public final void movss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVSS, dst, src);
}
/** Move Scalar SP-FP (SSE). */
public final void movss(XMMRegister dst, Mem src)
{
emitX86(INST_MOVSS, dst, src);
}
/** Move Scalar SP-FP (SSE). */
public final void movss(Mem dst, XMMRegister src)
{
emitX86(INST_MOVSS, dst, src);
}
/** Move Unaligned Packed SP-FP Values (SSE). */
public final void movups(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVUPS, dst, src);
}
/** Move Unaligned Packed SP-FP Values (SSE). */
public final void movups(XMMRegister dst, Mem src)
{
emitX86(INST_MOVUPS, dst, src);
}
/** Move Unaligned Packed SP-FP Values (SSE). */
public final void movups(Mem dst, XMMRegister src)
{
emitX86(INST_MOVUPS, dst, src);
}
/** Packed SP-FP Multiply (SSE). */
public final void mulps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MULPS, dst, src);
}
/** Packed SP-FP Multiply (SSE). */
public final void mulps(XMMRegister dst, Mem src)
{
emitX86(INST_MULPS, dst, src);
}
/** Scalar SP-FP Multiply (SSE). */
public final void mulss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MULSS, dst, src);
}
/** Scalar SP-FP Multiply (SSE). */
public final void mulss(XMMRegister dst, Mem src)
{
emitX86(INST_MULSS, dst, src);
}
/** Bit-wise Logical OR for SP-FP Data (SSE). */
public final void orps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_ORPS, dst, src);
}
/** Bit-wise Logical OR for SP-FP Data (SSE). */
public final void orps(XMMRegister dst, Mem src)
{
emitX86(INST_ORPS, dst, src);
}
/** Packed Average (SSE). */
public final void pavgb(MMRegister dst, MMRegister src)
{
emitX86(INST_PAVGB, dst, src);
}
/** Packed Average (SSE). */
public final void pavgb(MMRegister dst, Mem src)
{
emitX86(INST_PAVGB, dst, src);
}
/** Packed Average (SSE). */
public final void pavgw(MMRegister dst, MMRegister src)
{
emitX86(INST_PAVGW, dst, src);
}
/** Packed Average (SSE). */
public final void pavgw(MMRegister dst, Mem src)
{
emitX86(INST_PAVGW, dst, src);
}
/** Extract Word (SSE). */
public final void pextrw(Register dst, MMRegister src, Immediate imm8)
{
emitX86(INST_PEXTRW, dst, src, imm8);
}
/** Insert Word (SSE). */
public final void pinsrw(MMRegister dst, Register src, Immediate imm8)
{
emitX86(INST_PINSRW, dst, src, imm8);
}
/** Insert Word (SSE). */
public final void pinsrw(MMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PINSRW, dst, src, imm8);
}
/** Packed Signed Integer Word Maximum (SSE). */
public final void pmaxsw(MMRegister dst, MMRegister src)
{
emitX86(INST_PMAXSW, dst, src);
}
/** Packed Signed Integer Word Maximum (SSE). */
public final void pmaxsw(MMRegister dst, Mem src)
{
emitX86(INST_PMAXSW, dst, src);
}
/** Packed Unsigned Integer Byte Maximum (SSE). */
public final void pmaxub(MMRegister dst, MMRegister src)
{
emitX86(INST_PMAXUB, dst, src);
}
/** Packed Unsigned Integer Byte Maximum (SSE). */
public final void pmaxub(MMRegister dst, Mem src)
{
emitX86(INST_PMAXUB, dst, src);
}
/** Packed Signed Integer Word Minimum (SSE). */
public final void pminsw(MMRegister dst, MMRegister src)
{
emitX86(INST_PMINSW, dst, src);
}
/** Packed Signed Integer Word Minimum (SSE). */
public final void pminsw(MMRegister dst, Mem src)
{
emitX86(INST_PMINSW, dst, src);
}
/** Packed Unsigned Integer Byte Minimum (SSE). */
public final void pminub(MMRegister dst, MMRegister src)
{
emitX86(INST_PMINUB, dst, src);
}
/** Packed Unsigned Integer Byte Minimum (SSE). */
public final void pminub(MMRegister dst, Mem src)
{
emitX86(INST_PMINUB, dst, src);
}
/** Move Byte Mask To Integer (SSE). */
public final void pmovmskb(Register dst, MMRegister src)
{
emitX86(INST_PMOVMSKB, dst, src);
}
/** Packed Multiply High Unsigned (SSE). */
public final void pmulhuw(MMRegister dst, MMRegister src)
{
emitX86(INST_PMULHUW, dst, src);
}
/** Packed Multiply High Unsigned (SSE). */
public final void pmulhuw(MMRegister dst, Mem src)
{
emitX86(INST_PMULHUW, dst, src);
}
/** Packed Sum of Absolute Differences (SSE). */
public final void psadbw(MMRegister dst, MMRegister src)
{
emitX86(INST_PSADBW, dst, src);
}
/** Packed Sum of Absolute Differences (SSE). */
public final void psadbw(MMRegister dst, Mem src)
{
emitX86(INST_PSADBW, dst, src);
}
/** Packed Shuffle word (SSE). */
public final void pshufw(MMRegister dst, MMRegister src, Immediate imm8)
{
emitX86(INST_PSHUFW, dst, src, imm8);
}
/** Packed Shuffle word (SSE). */
public final void pshufw(MMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PSHUFW, dst, src, imm8);
}
/** Packed SP-FP Reciprocal (SSE). */
public final void rcpps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_RCPPS, dst, src);
}
/** Packed SP-FP Reciprocal (SSE). */
public final void rcpps(XMMRegister dst, Mem src)
{
emitX86(INST_RCPPS, dst, src);
}
/** Scalar SP-FP Reciprocal (SSE). */
public final void rcpss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_RCPSS, dst, src);
}
/** Scalar SP-FP Reciprocal (SSE). */
public final void rcpss(XMMRegister dst, Mem src)
{
emitX86(INST_RCPSS, dst, src);
}
/** Prefetch (SSE). */
public final void prefetch(Mem mem, Immediate hint)
{
emitX86(INST_PREFETCH, mem, hint);
}
/** Compute Sum of Absolute Differences (SSE). */
public final void psadbw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSADBW, dst, src);
}
/** Compute Sum of Absolute Differences (SSE). */
public final void psadbw(XMMRegister dst, Mem src)
{
emitX86(INST_PSADBW, dst, src);
}
/** Packed SP-FP Square Root Reciprocal (SSE). */
public final void rsqrtps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_RSQRTPS, dst, src);
}
/** Packed SP-FP Square Root Reciprocal (SSE). */
public final void rsqrtps(XMMRegister dst, Mem src)
{
emitX86(INST_RSQRTPS, dst, src);
}
/** Scalar SP-FP Square Root Reciprocal (SSE). */
public final void rsqrtss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_RSQRTSS, dst, src);
}
/** Scalar SP-FP Square Root Reciprocal (SSE). */
public final void rsqrtss(XMMRegister dst, Mem src)
{
emitX86(INST_RSQRTSS, dst, src);
}
/** Store fence (SSE). */
public final void sfence()
{
emitX86(INST_SFENCE);
}
/** Shuffle SP-FP (SSE). */
public final void shufps(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_SHUFPS, dst, src, imm8);
}
/** Shuffle SP-FP (SSE). */
public final void shufps(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_SHUFPS, dst, src, imm8);
}
/** Packed SP-FP Square Root (SSE). */
public final void sqrtps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_SQRTPS, dst, src);
}
/** Packed SP-FP Square Root (SSE). */
public final void sqrtps(XMMRegister dst, Mem src)
{
emitX86(INST_SQRTPS, dst, src);
}
/** Scalar SP-FP Square Root (SSE). */
public final void sqrtss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_SQRTSS, dst, src);
}
/** Scalar SP-FP Square Root (SSE). */
public final void sqrtss(XMMRegister dst, Mem src)
{
emitX86(INST_SQRTSS, dst, src);
}
/** Store Streaming SIMD Extension Control/Status (SSE). */
public final void stmxcsr(Mem dst)
{
emitX86(INST_STMXCSR, dst);
}
/** Packed SP-FP Subtract (SSE). */
public final void subps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_SUBPS, dst, src);
}
/** Packed SP-FP Subtract (SSE). */
public final void subps(XMMRegister dst, Mem src)
{
emitX86(INST_SUBPS, dst, src);
}
/** Scalar SP-FP Subtract (SSE). */
public final void subss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_SUBSS, dst, src);
}
/** Scalar SP-FP Subtract (SSE). */
public final void subss(XMMRegister dst, Mem src)
{
emitX86(INST_SUBSS, dst, src);
}
/** Unordered Scalar SP-FP compare and set EFLAGS (SSE). */
public final void ucomiss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_UCOMISS, dst, src);
}
/** Unordered Scalar SP-FP compare and set EFLAGS (SSE). */
public final void ucomiss(XMMRegister dst, Mem src)
{
emitX86(INST_UCOMISS, dst, src);
}
/** Unpack High Packed SP-FP Data (SSE). */
public final void unpckhps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_UNPCKHPS, dst, src);
}
/** Unpack High Packed SP-FP Data (SSE). */
public final void unpckhps(XMMRegister dst, Mem src)
{
emitX86(INST_UNPCKHPS, dst, src);
}
/** Unpack Low Packed SP-FP Data (SSE). */
public final void unpcklps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_UNPCKLPS, dst, src);
}
/** Unpack Low Packed SP-FP Data (SSE). */
public final void unpcklps(XMMRegister dst, Mem src)
{
emitX86(INST_UNPCKLPS, dst, src);
}
/** Bit-wise Logical Xor for SP-FP Data (SSE). */
public final void xorps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_XORPS, dst, src);
}
/** Bit-wise Logical Xor for SP-FP Data (SSE). */
public final void xorps(XMMRegister dst, Mem src)
{
emitX86(INST_XORPS, dst, src);
}
// -------------------------------------------------------------------------
// [SSE2]
// -------------------------------------------------------------------------
/** Packed DP-FP Add (SSE2). */
public final void addpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_ADDPD, dst, src);
}
/** Packed DP-FP Add (SSE2). */
public final void addpd(XMMRegister dst, Mem src)
{
emitX86(INST_ADDPD, dst, src);
}
/** Scalar DP-FP Add (SSE2). */
public final void addsd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_ADDSD, dst, src);
}
/** Scalar DP-FP Add (SSE2). */
public final void addsd(XMMRegister dst, Mem src)
{
emitX86(INST_ADDSD, dst, src);
}
/** Bit-wise Logical And Not For DP-FP (SSE2). */
public final void andnpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_ANDNPD, dst, src);
}
/** Bit-wise Logical And Not For DP-FP (SSE2). */
public final void andnpd(XMMRegister dst, Mem src)
{
emitX86(INST_ANDNPD, dst, src);
}
/** Bit-wise Logical And For DP-FP (SSE2). */
public final void andpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_ANDPD, dst, src);
}
/** Bit-wise Logical And For DP-FP (SSE2). */
public final void andpd(XMMRegister dst, Mem src)
{
emitX86(INST_ANDPD, dst, src);
}
/** Flush Cache Line (SSE2). */
public final void clflush(Mem mem)
{
emitX86(INST_CLFLUSH, mem);
}
/** Packed DP-FP Compare (SSE2). */
public final void cmppd(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_CMPPD, dst, src, imm8);
}
/** Packed DP-FP Compare (SSE2). */
public final void cmppd(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_CMPPD, dst, src, imm8);
}
/** Compare Scalar SP-FP Values (SSE2). */
public final void cmpsd(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_CMPSD, dst, src, imm8);
}
/** Compare Scalar SP-FP Values (SSE2). */
public final void cmpsd(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_CMPSD, dst, src, imm8);
}
/** Scalar Ordered DP-FP Compare and Set EFLAGS (SSE2). */
public final void comisd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_COMISD, dst, src);
}
/** Scalar Ordered DP-FP Compare and Set EFLAGS (SSE2). */
public final void comisd(XMMRegister dst, Mem src)
{
emitX86(INST_COMISD, dst, src);
}
/** Convert Packed Dword Integers to Packed DP-FP Values (SSE2). */
public final void cvtdq2pd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_CVTDQ2PD, dst, src);
}
/** Convert Packed Dword Integers to Packed DP-FP Values (SSE2). */
public final void cvtdq2pd(XMMRegister dst, Mem src)
{
emitX86(INST_CVTDQ2PD, dst, src);
}
/** Convert Packed Dword Integers to Packed SP-FP Values (SSE2). */
public final void cvtdq2ps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_CVTDQ2PS, dst, src);
}
/** Convert Packed Dword Integers to Packed SP-FP Values (SSE2). */
public final void cvtdq2ps(XMMRegister dst, Mem src)
{
emitX86(INST_CVTDQ2PS, dst, src);
}
/** Convert Packed DP-FP Values to Packed Dword Integers (SSE2). */
public final void cvtpd2dq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_CVTPD2DQ, dst, src);
}
/** Convert Packed DP-FP Values to Packed Dword Integers (SSE2). */
public final void cvtpd2dq(XMMRegister dst, Mem src)
{
emitX86(INST_CVTPD2DQ, dst, src);
}
/** Convert Packed DP-FP Values to Packed Dword Integers (SSE2). */
public final void cvtpd2pi(MMRegister dst, XMMRegister src)
{
emitX86(INST_CVTPD2PI, dst, src);
}
/** Convert Packed DP-FP Values to Packed Dword Integers (SSE2). */
public final void cvtpd2pi(MMRegister dst, Mem src)
{
emitX86(INST_CVTPD2PI, dst, src);
}
/** Convert Packed DP-FP Values to Packed SP-FP Values (SSE2). */
public final void cvtpd2ps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_CVTPD2PS, dst, src);
}
/** Convert Packed DP-FP Values to Packed SP-FP Values (SSE2). */
public final void cvtpd2ps(XMMRegister dst, Mem src)
{
emitX86(INST_CVTPD2PS, dst, src);
}
/** Convert Packed Dword Integers to Packed DP-FP Values (SSE2). */
public final void cvtpi2pd(XMMRegister dst, MMRegister src)
{
emitX86(INST_CVTPI2PD, dst, src);
}
/** Convert Packed Dword Integers to Packed DP-FP Values (SSE2). */
public final void cvtpi2pd(XMMRegister dst, Mem src)
{
emitX86(INST_CVTPI2PD, dst, src);
}
/** Convert Packed SP-FP Values to Packed Dword Integers (SSE2). */
public final void cvtps2dq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_CVTPS2DQ, dst, src);
}
/** Convert Packed SP-FP Values to Packed Dword Integers (SSE2). */
public final void cvtps2dq(XMMRegister dst, Mem src)
{
emitX86(INST_CVTPS2DQ, dst, src);
}
/** Convert Packed SP-FP Values to Packed DP-FP Values (SSE2). */
public final void cvtps2pd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_CVTPS2PD, dst, src);
}
/** Convert Packed SP-FP Values to Packed DP-FP Values (SSE2). */
public final void cvtps2pd(XMMRegister dst, Mem src)
{
emitX86(INST_CVTPS2PD, dst, src);
}
/** Convert Scalar DP-FP Value to Dword Integer (SSE2). */
public final void cvtsd2si(Register dst, XMMRegister src)
{
emitX86(INST_CVTSD2SI, dst, src);
}
/** Convert Scalar DP-FP Value to Dword Integer (SSE2). */
public final void cvtsd2si(Register dst, Mem src)
{
emitX86(INST_CVTSD2SI, dst, src);
}
/** Convert Scalar DP-FP Value to Scalar SP-FP Value (SSE2). */
public final void cvtsd2ss(XMMRegister dst, XMMRegister src)
{
emitX86(INST_CVTSD2SS, dst, src);
}
/** Convert Scalar DP-FP Value to Scalar SP-FP Value (SSE2). */
public final void cvtsd2ss(XMMRegister dst, Mem src)
{
emitX86(INST_CVTSD2SS, dst, src);
}
/** Convert Dword Integer to Scalar DP-FP Value (SSE2). */
public final void cvtsi2sd(XMMRegister dst, Register src)
{
emitX86(INST_CVTSI2SD, dst, src);
}
/** Convert Dword Integer to Scalar DP-FP Value (SSE2). */
public final void cvtsi2sd(XMMRegister dst, Mem src)
{
emitX86(INST_CVTSI2SD, dst, src);
}
/** Convert Scalar SP-FP Value to Scalar DP-FP Value (SSE2). */
public final void cvtss2sd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_CVTSS2SD, dst, src);
}
/** Convert Scalar SP-FP Value to Scalar DP-FP Value (SSE2). */
public final void cvtss2sd(XMMRegister dst, Mem src)
{
emitX86(INST_CVTSS2SD, dst, src);
}
/** Convert with Truncation Packed DP-FP Values to Packed Dword Integers (SSE2). */
public final void cvttpd2pi(MMRegister dst, XMMRegister src)
{
emitX86(INST_CVTTPD2PI, dst, src);
}
/** Convert with Truncation Packed DP-FP Values to Packed Dword Integers (SSE2). */
public final void cvttpd2pi(MMRegister dst, Mem src)
{
emitX86(INST_CVTTPD2PI, dst, src);
}
/** Convert with Truncation Packed DP-FP Values to Packed Dword Integers (SSE2). */
public final void cvttpd2dq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_CVTTPD2DQ, dst, src);
}
/** Convert with Truncation Packed DP-FP Values to Packed Dword Integers (SSE2). */
public final void cvttpd2dq(XMMRegister dst, Mem src)
{
emitX86(INST_CVTTPD2DQ, dst, src);
}
/** Convert with Truncation Packed SP-FP Values to Packed Dword Integers (SSE2). */
public final void cvttps2dq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_CVTTPS2DQ, dst, src);
}
/** Convert with Truncation Packed SP-FP Values to Packed Dword Integers (SSE2). */
public final void cvttps2dq(XMMRegister dst, Mem src)
{
emitX86(INST_CVTTPS2DQ, dst, src);
}
/** Convert with Truncation Scalar DP-FP Value to Signed Dword Integer (SSE2). */
public final void cvttsd2si(Register dst, XMMRegister src)
{
emitX86(INST_CVTTSD2SI, dst, src);
}
/** Convert with Truncation Scalar DP-FP Value to Signed Dword Integer (SSE2). */
public final void cvttsd2si(Register dst, Mem src)
{
emitX86(INST_CVTTSD2SI, dst, src);
}
/** Packed DP-FP Divide (SSE2). */
public final void divpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_DIVPD, dst, src);
}
/** Packed DP-FP Divide (SSE2). */
public final void divpd(XMMRegister dst, Mem src)
{
emitX86(INST_DIVPD, dst, src);
}
/** Scalar DP-FP Divide (SSE2). */
public final void divsd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_DIVSD, dst, src);
}
/** Scalar DP-FP Divide (SSE2). */
public final void divsd(XMMRegister dst, Mem src)
{
emitX86(INST_DIVSD, dst, src);
}
/** Load Fence (SSE2). */
public final void lfence()
{
emitX86(INST_LFENCE);
}
/** Store Selected Bytes of Double Quadword (SSE2). */
//!
//! @note Target is DS:EDI.
public final void maskmovdqu(XMMRegister src, XMMRegister mask)
{
emitX86(INST_MASKMOVDQU, src, mask);
}
/** Return Maximum Packed Double-Precision FP Values (SSE2). */
public final void maxpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MAXPD, dst, src);
}
/** Return Maximum Packed Double-Precision FP Values (SSE2). */
public final void maxpd(XMMRegister dst, Mem src)
{
emitX86(INST_MAXPD, dst, src);
}
/** Return Maximum Scalar Double-Precision FP Value (SSE2). */
public final void maxsd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MAXSD, dst, src);
}
/** Return Maximum Scalar Double-Precision FP Value (SSE2). */
public final void maxsd(XMMRegister dst, Mem src)
{
emitX86(INST_MAXSD, dst, src);
}
/** Memory Fence (SSE2). */
public final void mfence()
{
emitX86(INST_MFENCE);
}
/** Return Minimum Packed DP-FP Values (SSE2). */
public final void minpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MINPD, dst, src);
}
/** Return Minimum Packed DP-FP Values (SSE2). */
public final void minpd(XMMRegister dst, Mem src)
{
emitX86(INST_MINPD, dst, src);
}
/** Return Minimum Scalar DP-FP Value (SSE2). */
public final void minsd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MINSD, dst, src);
}
/** Return Minimum Scalar DP-FP Value (SSE2). */
public final void minsd(XMMRegister dst, Mem src)
{
emitX86(INST_MINSD, dst, src);
}
/** Move Aligned DQWord (SSE2). */
public final void movdqa(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVDQA, dst, src);
}
/** Move Aligned DQWord (SSE2). */
public final void movdqa(XMMRegister dst, Mem src)
{
emitX86(INST_MOVDQA, dst, src);
}
/** Move Aligned DQWord (SSE2). */
public final void movdqa(Mem dst, XMMRegister src)
{
emitX86(INST_MOVDQA, dst, src);
}
/** Move Unaligned Double Quadword (SSE2). */
public final void movdqu(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVDQU, dst, src);
}
/** Move Unaligned Double Quadword (SSE2). */
public final void movdqu(XMMRegister dst, Mem src)
{
emitX86(INST_MOVDQU, dst, src);
}
/** Move Unaligned Double Quadword (SSE2). */
public final void movdqu(Mem dst, XMMRegister src)
{
emitX86(INST_MOVDQU, dst, src);
}
/** Extract Packed SP-FP Sign Mask (SSE2). */
public final void movmskps(Register dst, XMMRegister src)
{
emitX86(INST_MOVMSKPS, dst, src);
}
/** Extract Packed DP-FP Sign Mask (SSE2). */
public final void movmskpd(Register dst, XMMRegister src)
{
emitX86(INST_MOVMSKPD, dst, src);
}
/** Move Scalar Double-Precision FP Value (SSE2). */
public final void movsd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVSD, dst, src);
}
/** Move Scalar Double-Precision FP Value (SSE2). */
public final void movsd(XMMRegister dst, Mem src)
{
emitX86(INST_MOVSD, dst, src);
}
/** Move Scalar Double-Precision FP Value (SSE2). */
public final void movsd(Mem dst, XMMRegister src)
{
emitX86(INST_MOVSD, dst, src);
}
/** Move Aligned Packed Double-Precision FP Values (SSE2). */
public final void movapd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVAPD, dst, src);
}
/** Move Aligned Packed Double-Precision FP Values (SSE2). */
public final void movapd(XMMRegister dst, Mem src)
{
emitX86(INST_MOVAPD, dst, src);
}
/** Move Aligned Packed Double-Precision FP Values (SSE2). */
public final void movapd(Mem dst, XMMRegister src)
{
emitX86(INST_MOVAPD, dst, src);
}
/** Move Quadword from XMM to MMX Technology Register (SSE2). */
public final void movdq2q(MMRegister dst, XMMRegister src)
{
emitX86(INST_MOVDQ2Q, dst, src);
}
/** Move Quadword from MMX Technology to XMM Register (SSE2). */
public final void movq2dq(XMMRegister dst, MMRegister src)
{
emitX86(INST_MOVQ2DQ, dst, src);
}
/** Move High Packed Double-Precision FP Value (SSE2). */
public final void movhpd(XMMRegister dst, Mem src)
{
emitX86(INST_MOVHPD, dst, src);
}
/** Move High Packed Double-Precision FP Value (SSE2). */
public final void movhpd(Mem dst, XMMRegister src)
{
emitX86(INST_MOVHPD, dst, src);
}
/** Move Low Packed Double-Precision FP Value (SSE2). */
public final void movlpd(XMMRegister dst, Mem src)
{
emitX86(INST_MOVLPD, dst, src);
}
/** Move Low Packed Double-Precision FP Value (SSE2). */
public final void movlpd(Mem dst, XMMRegister src)
{
emitX86(INST_MOVLPD, dst, src);
}
/** Store Double Quadword Using Non-Temporal Hint (SSE2). */
public final void movntdq(Mem dst, XMMRegister src)
{
emitX86(INST_MOVNTDQ, dst, src);
}
/** Store Store DWORD Using Non-Temporal Hint (SSE2). */
public final void movnti(Mem dst, Register src)
{
emitX86(INST_MOVNTI, dst, src);
}
/** Store Packed Double-Precision FP Values Using Non-Temporal Hint (SSE2). */
public final void movntpd(Mem dst, XMMRegister src)
{
emitX86(INST_MOVNTPD, dst, src);
}
/** Move Unaligned Packed Double-Precision FP Values (SSE2). */
public final void movupd(XMMRegister dst, Mem src)
{
emitX86(INST_MOVUPD, dst, src);
}
/** Move Unaligned Packed Double-Precision FP Values (SSE2). */
public final void movupd(Mem dst, XMMRegister src)
{
emitX86(INST_MOVUPD, dst, src);
}
/** Packed DP-FP Multiply (SSE2). */
public final void mulpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MULPD, dst, src);
}
/** Packed DP-FP Multiply (SSE2). */
public final void mulpd(XMMRegister dst, Mem src)
{
emitX86(INST_MULPD, dst, src);
}
/** Scalar DP-FP Multiply (SSE2). */
public final void mulsd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MULSD, dst, src);
}
/** Scalar DP-FP Multiply (SSE2). */
public final void mulsd(XMMRegister dst, Mem src)
{
emitX86(INST_MULSD, dst, src);
}
/** Bit-wise Logical OR for DP-FP Data (SSE2). */
public final void orpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_ORPD, dst, src);
}
/** Bit-wise Logical OR for DP-FP Data (SSE2). */
public final void orpd(XMMRegister dst, Mem src)
{
emitX86(INST_ORPD, dst, src);
}
/** Pack with Signed Saturation (SSE2). */
public final void packsswb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PACKSSWB, dst, src);
}
/** Pack with Signed Saturation (SSE2). */
public final void packsswb(XMMRegister dst, Mem src)
{
emitX86(INST_PACKSSWB, dst, src);
}
/** Pack with Signed Saturation (SSE2). */
public final void packssdw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PACKSSDW, dst, src);
}
/** Pack with Signed Saturation (SSE2). */
public final void packssdw(XMMRegister dst, Mem src)
{
emitX86(INST_PACKSSDW, dst, src);
}
/** Pack with Unsigned Saturation (SSE2). */
public final void packuswb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PACKUSWB, dst, src);
}
/** Pack with Unsigned Saturation (SSE2). */
public final void packuswb(XMMRegister dst, Mem src)
{
emitX86(INST_PACKUSWB, dst, src);
}
/** Packed BYTE Add (SSE2). */
public final void paddb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PADDB, dst, src);
}
/** Packed BYTE Add (SSE2). */
public final void paddb(XMMRegister dst, Mem src)
{
emitX86(INST_PADDB, dst, src);
}
/** Packed WORD Add (SSE2). */
public final void paddw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PADDW, dst, src);
}
/** Packed WORD Add (SSE2). */
public final void paddw(XMMRegister dst, Mem src)
{
emitX86(INST_PADDW, dst, src);
}
/** Packed DWORD Add (SSE2). */
public final void paddd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PADDD, dst, src);
}
/** Packed DWORD Add (SSE2). */
public final void paddd(XMMRegister dst, Mem src)
{
emitX86(INST_PADDD, dst, src);
}
/** Packed QWORD Add (SSE2). */
public final void paddq(MMRegister dst, MMRegister src)
{
emitX86(INST_PADDQ, dst, src);
}
/** Packed QWORD Add (SSE2). */
public final void paddq(MMRegister dst, Mem src)
{
emitX86(INST_PADDQ, dst, src);
}
/** Packed QWORD Add (SSE2). */
public final void paddq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PADDQ, dst, src);
}
/** Packed QWORD Add (SSE2). */
public final void paddq(XMMRegister dst, Mem src)
{
emitX86(INST_PADDQ, dst, src);
}
/** Packed Add with Saturation (SSE2). */
public final void paddsb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PADDSB, dst, src);
}
/** Packed Add with Saturation (SSE2). */
public final void paddsb(XMMRegister dst, Mem src)
{
emitX86(INST_PADDSB, dst, src);
}
/** Packed Add with Saturation (SSE2). */
public final void paddsw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PADDSW, dst, src);
}
/** Packed Add with Saturation (SSE2). */
public final void paddsw(XMMRegister dst, Mem src)
{
emitX86(INST_PADDSW, dst, src);
}
/** Packed Add Unsigned with Saturation (SSE2). */
public final void paddusb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PADDUSB, dst, src);
}
/** Packed Add Unsigned with Saturation (SSE2). */
public final void paddusb(XMMRegister dst, Mem src)
{
emitX86(INST_PADDUSB, dst, src);
}
/** Packed Add Unsigned with Saturation (SSE2). */
public final void paddusw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PADDUSW, dst, src);
}
/** Packed Add Unsigned with Saturation (SSE2). */
public final void paddusw(XMMRegister dst, Mem src)
{
emitX86(INST_PADDUSW, dst, src);
}
/** Logical AND (SSE2). */
public final void pand(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PAND, dst, src);
}
/** Logical AND (SSE2). */
public final void pand(XMMRegister dst, Mem src)
{
emitX86(INST_PAND, dst, src);
}
/** Logical AND Not (SSE2). */
public final void pandn(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PANDN, dst, src);
}
/** Logical AND Not (SSE2). */
public final void pandn(XMMRegister dst, Mem src)
{
emitX86(INST_PANDN, dst, src);
}
/** Spin Loop Hint (SSE2). */
public final void pause()
{
emitX86(INST_PAUSE);
}
/** Packed Average (SSE2). */
public final void pavgb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PAVGB, dst, src);
}
/** Packed Average (SSE2). */
public final void pavgb(XMMRegister dst, Mem src)
{
emitX86(INST_PAVGB, dst, src);
}
/** Packed Average (SSE2). */
public final void pavgw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PAVGW, dst, src);
}
/** Packed Average (SSE2). */
public final void pavgw(XMMRegister dst, Mem src)
{
emitX86(INST_PAVGW, dst, src);
}
/** Packed Compare for Equal (BYTES) (SSE2). */
public final void pcmpeqb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PCMPEQB, dst, src);
}
/** Packed Compare for Equal (BYTES) (SSE2). */
public final void pcmpeqb(XMMRegister dst, Mem src)
{
emitX86(INST_PCMPEQB, dst, src);
}
/** Packed Compare for Equal (WORDS) (SSE2). */
public final void pcmpeqw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PCMPEQW, dst, src);
}
/** Packed Compare for Equal (WORDS) (SSE2). */
public final void pcmpeqw(XMMRegister dst, Mem src)
{
emitX86(INST_PCMPEQW, dst, src);
}
/** Packed Compare for Equal (DWORDS) (SSE2). */
public final void pcmpeqd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PCMPEQD, dst, src);
}
/** Packed Compare for Equal (DWORDS) (SSE2). */
public final void pcmpeqd(XMMRegister dst, Mem src)
{
emitX86(INST_PCMPEQD, dst, src);
}
/** Packed Compare for Greater Than (BYTES) (SSE2). */
public final void pcmpgtb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PCMPGTB, dst, src);
}
/** Packed Compare for Greater Than (BYTES) (SSE2). */
public final void pcmpgtb(XMMRegister dst, Mem src)
{
emitX86(INST_PCMPGTB, dst, src);
}
/** Packed Compare for Greater Than (WORDS) (SSE2). */
public final void pcmpgtw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PCMPGTW, dst, src);
}
/** Packed Compare for Greater Than (WORDS) (SSE2). */
public final void pcmpgtw(XMMRegister dst, Mem src)
{
emitX86(INST_PCMPGTW, dst, src);
}
/** Packed Compare for Greater Than (DWORDS) (SSE2). */
public final void pcmpgtd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PCMPGTD, dst, src);
}
/** Packed Compare for Greater Than (DWORDS) (SSE2). */
public final void pcmpgtd(XMMRegister dst, Mem src)
{
emitX86(INST_PCMPGTD, dst, src);
}
/** Packed Signed Integer Word Maximum (SSE2). */
public final void pmaxsw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMAXSW, dst, src);
}
/** Packed Signed Integer Word Maximum (SSE2). */
public final void pmaxsw(XMMRegister dst, Mem src)
{
emitX86(INST_PMAXSW, dst, src);
}
/** Packed Unsigned Integer Byte Maximum (SSE2). */
public final void pmaxub(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMAXUB, dst, src);
}
/** Packed Unsigned Integer Byte Maximum (SSE2). */
public final void pmaxub(XMMRegister dst, Mem src)
{
emitX86(INST_PMAXUB, dst, src);
}
/** Packed Signed Integer Word Minimum (SSE2). */
public final void pminsw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMINSW, dst, src);
}
/** Packed Signed Integer Word Minimum (SSE2). */
public final void pminsw(XMMRegister dst, Mem src)
{
emitX86(INST_PMINSW, dst, src);
}
/** Packed Unsigned Integer Byte Minimum (SSE2). */
public final void pminub(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMINUB, dst, src);
}
/** Packed Unsigned Integer Byte Minimum (SSE2). */
public final void pminub(XMMRegister dst, Mem src)
{
emitX86(INST_PMINUB, dst, src);
}
/** Move Byte Mask (SSE2). */
public final void pmovmskb(Register dst, XMMRegister src)
{
emitX86(INST_PMOVMSKB, dst, src);
}
/** Packed Multiply High (SSE2). */
public final void pmulhw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMULHW, dst, src);
}
/** Packed Multiply High (SSE2). */
public final void pmulhw(XMMRegister dst, Mem src)
{
emitX86(INST_PMULHW, dst, src);
}
/** Packed Multiply High Unsigned (SSE2). */
public final void pmulhuw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMULHUW, dst, src);
}
/** Packed Multiply High Unsigned (SSE2). */
public final void pmulhuw(XMMRegister dst, Mem src)
{
emitX86(INST_PMULHUW, dst, src);
}
/** Packed Multiply Low (SSE2). */
public final void pmullw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMULLW, dst, src);
}
/** Packed Multiply Low (SSE2). */
public final void pmullw(XMMRegister dst, Mem src)
{
emitX86(INST_PMULLW, dst, src);
}
/** Packed Multiply to QWORD (SSE2). */
public final void pmuludq(MMRegister dst, MMRegister src)
{
emitX86(INST_PMULUDQ, dst, src);
}
/** Packed Multiply to QWORD (SSE2). */
public final void pmuludq(MMRegister dst, Mem src)
{
emitX86(INST_PMULUDQ, dst, src);
}
/** Packed Multiply to QWORD (SSE2). */
public final void pmuludq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMULUDQ, dst, src);
}
/** Packed Multiply to QWORD (SSE2). */
public final void pmuludq(XMMRegister dst, Mem src)
{
emitX86(INST_PMULUDQ, dst, src);
}
/** Bitwise Logical OR (SSE2). */
public final void por(XMMRegister dst, XMMRegister src)
{
emitX86(INST_POR, dst, src);
}
/** Bitwise Logical OR (SSE2). */
public final void por(XMMRegister dst, Mem src)
{
emitX86(INST_POR, dst, src);
}
/** Packed Shift Left Logical (SSE2). */
public final void pslld(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSLLD, dst, src);
}
/** Packed Shift Left Logical (SSE2). */
public final void pslld(XMMRegister dst, Mem src)
{
emitX86(INST_PSLLD, dst, src);
}
/** Packed Shift Left Logical (SSE2). */
public final void pslld(XMMRegister dst, Immediate src)
{
emitX86(INST_PSLLD, dst, src);
}
/** Packed Shift Left Logical (SSE2). */
public final void psllq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSLLQ, dst, src);
}
/** Packed Shift Left Logical (SSE2). */
public final void psllq(XMMRegister dst, Mem src)
{
emitX86(INST_PSLLQ, dst, src);
}
/** Packed Shift Left Logical (SSE2). */
public final void psllq(XMMRegister dst, Immediate src)
{
emitX86(INST_PSLLQ, dst, src);
}
/** Packed Shift Left Logical (SSE2). */
public final void psllw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSLLW, dst, src);
}
/** Packed Shift Left Logical (SSE2). */
public final void psllw(XMMRegister dst, Mem src)
{
emitX86(INST_PSLLW, dst, src);
}
/** Packed Shift Left Logical (SSE2). */
public final void psllw(XMMRegister dst, Immediate src)
{
emitX86(INST_PSLLW, dst, src);
}
/** Packed Shift Left Logical (SSE2). */
public final void pslldq(XMMRegister dst, Immediate src)
{
emitX86(INST_PSLLDQ, dst, src);
}
/** Packed Shift Right Arithmetic (SSE2). */
public final void psrad(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSRAD, dst, src);
}
/** Packed Shift Right Arithmetic (SSE2). */
public final void psrad(XMMRegister dst, Mem src)
{
emitX86(INST_PSRAD, dst, src);
}
/** Packed Shift Right Arithmetic (SSE2). */
public final void psrad(XMMRegister dst, Immediate src)
{
emitX86(INST_PSRAD, dst, src);
}
/** Packed Shift Right Arithmetic (SSE2). */
public final void psraw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSRAW, dst, src);
}
/** Packed Shift Right Arithmetic (SSE2). */
public final void psraw(XMMRegister dst, Mem src)
{
emitX86(INST_PSRAW, dst, src);
}
/** Packed Shift Right Arithmetic (SSE2). */
public final void psraw(XMMRegister dst, Immediate src)
{
emitX86(INST_PSRAW, dst, src);
}
/** Packed Subtract (SSE2). */
public final void psubb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSUBB, dst, src);
}
/** Packed Subtract (SSE2). */
public final void psubb(XMMRegister dst, Mem src)
{
emitX86(INST_PSUBB, dst, src);
}
/** Packed Subtract (SSE2). */
public final void psubw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSUBW, dst, src);
}
/** Packed Subtract (SSE2). */
public final void psubw(XMMRegister dst, Mem src)
{
emitX86(INST_PSUBW, dst, src);
}
/** Packed Subtract (SSE2). */
public final void psubd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSUBD, dst, src);
}
/** Packed Subtract (SSE2). */
public final void psubd(XMMRegister dst, Mem src)
{
emitX86(INST_PSUBD, dst, src);
}
/** Packed Subtract (SSE2). */
public final void psubq(MMRegister dst, MMRegister src)
{
emitX86(INST_PSUBQ, dst, src);
}
/** Packed Subtract (SSE2). */
public final void psubq(MMRegister dst, Mem src)
{
emitX86(INST_PSUBQ, dst, src);
}
/** Packed Subtract (SSE2). */
public final void psubq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSUBQ, dst, src);
}
/** Packed Subtract (SSE2). */
public final void psubq(XMMRegister dst, Mem src)
{
emitX86(INST_PSUBQ, dst, src);
}
/** Packed Multiply and Add (SSE2). */
public final void pmaddwd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMADDWD, dst, src);
}
/** Packed Multiply and Add (SSE2). */
public final void pmaddwd(XMMRegister dst, Mem src)
{
emitX86(INST_PMADDWD, dst, src);
}
/** Shuffle Packed DWORDs (SSE2). */
public final void pshufd(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PSHUFD, dst, src, imm8);
}
/** Shuffle Packed DWORDs (SSE2). */
public final void pshufd(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PSHUFD, dst, src, imm8);
}
/** Shuffle Packed High Words (SSE2). */
public final void pshufhw(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PSHUFHW, dst, src, imm8);
}
/** Shuffle Packed High Words (SSE2). */
public final void pshufhw(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PSHUFHW, dst, src, imm8);
}
/** Shuffle Packed Low Words (SSE2). */
public final void pshuflw(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PSHUFLW, dst, src, imm8);
}
/** Shuffle Packed Low Words (SSE2). */
public final void pshuflw(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PSHUFLW, dst, src, imm8);
}
/** Packed Shift Right Logical (SSE2). */
public final void psrld(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSRLD, dst, src);
}
/** Packed Shift Right Logical (SSE2). */
public final void psrld(XMMRegister dst, Mem src)
{
emitX86(INST_PSRLD, dst, src);
}
/** Packed Shift Right Logical (SSE2). */
public final void psrld(XMMRegister dst, Immediate src)
{
emitX86(INST_PSRLD, dst, src);
}
/** Packed Shift Right Logical (SSE2). */
public final void psrlq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSRLQ, dst, src);
}
/** Packed Shift Right Logical (SSE2). */
public final void psrlq(XMMRegister dst, Mem src)
{
emitX86(INST_PSRLQ, dst, src);
}
/** Packed Shift Right Logical (SSE2). */
public final void psrlq(XMMRegister dst, Immediate src)
{
emitX86(INST_PSRLQ, dst, src);
}
/** DQWord Shift Right Logical (MMX). */
public final void psrldq(XMMRegister dst, Immediate src)
{
emitX86(INST_PSRLDQ, dst, src);
}
/** Packed Shift Right Logical (SSE2). */
public final void psrlw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSRLW, dst, src);
}
/** Packed Shift Right Logical (SSE2). */
public final void psrlw(XMMRegister dst, Mem src)
{
emitX86(INST_PSRLW, dst, src);
}
/** Packed Shift Right Logical (SSE2). */
public final void psrlw(XMMRegister dst, Immediate src)
{
emitX86(INST_PSRLW, dst, src);
}
/** Packed Subtract with Saturation (SSE2). */
public final void psubsb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSUBSB, dst, src);
}
/** Packed Subtract with Saturation (SSE2). */
public final void psubsb(XMMRegister dst, Mem src)
{
emitX86(INST_PSUBSB, dst, src);
}
/** Packed Subtract with Saturation (SSE2). */
public final void psubsw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSUBSW, dst, src);
}
/** Packed Subtract with Saturation (SSE2). */
public final void psubsw(XMMRegister dst, Mem src)
{
emitX86(INST_PSUBSW, dst, src);
}
/** Packed Subtract with Unsigned Saturation (SSE2). */
public final void psubusb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSUBUSB, dst, src);
}
/** Packed Subtract with Unsigned Saturation (SSE2). */
public final void psubusb(XMMRegister dst, Mem src)
{
emitX86(INST_PSUBUSB, dst, src);
}
/** Packed Subtract with Unsigned Saturation (SSE2). */
public final void psubusw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSUBUSW, dst, src);
}
/** Packed Subtract with Unsigned Saturation (SSE2). */
public final void psubusw(XMMRegister dst, Mem src)
{
emitX86(INST_PSUBUSW, dst, src);
}
/** Unpack High Data (SSE2). */
public final void punpckhbw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PUNPCKHBW, dst, src);
}
/** Unpack High Data (SSE2). */
public final void punpckhbw(XMMRegister dst, Mem src)
{
emitX86(INST_PUNPCKHBW, dst, src);
}
/** Unpack High Data (SSE2). */
public final void punpckhwd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PUNPCKHWD, dst, src);
}
/** Unpack High Data (SSE2). */
public final void punpckhwd(XMMRegister dst, Mem src)
{
emitX86(INST_PUNPCKHWD, dst, src);
}
/** Unpack High Data (SSE2). */
public final void punpckhdq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PUNPCKHDQ, dst, src);
}
/** Unpack High Data (SSE2). */
public final void punpckhdq(XMMRegister dst, Mem src)
{
emitX86(INST_PUNPCKHDQ, dst, src);
}
/** Unpack High Data (SSE2). */
public final void punpckhqdq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PUNPCKHQDQ, dst, src);
}
/** Unpack High Data (SSE2). */
public final void punpckhqdq(XMMRegister dst, Mem src)
{
emitX86(INST_PUNPCKHQDQ, dst, src);
}
/** Unpack Low Data (SSE2). */
public final void punpcklbw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PUNPCKLBW, dst, src);
}
/** Unpack Low Data (SSE2). */
public final void punpcklbw(XMMRegister dst, Mem src)
{
emitX86(INST_PUNPCKLBW, dst, src);
}
/** Unpack Low Data (SSE2). */
public final void punpcklwd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PUNPCKLWD, dst, src);
}
/** Unpack Low Data (SSE2). */
public final void punpcklwd(XMMRegister dst, Mem src)
{
emitX86(INST_PUNPCKLWD, dst, src);
}
/** Unpack Low Data (SSE2). */
public final void punpckldq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PUNPCKLDQ, dst, src);
}
/** Unpack Low Data (SSE2). */
public final void punpckldq(XMMRegister dst, Mem src)
{
emitX86(INST_PUNPCKLDQ, dst, src);
}
/** Unpack Low Data (SSE2). */
public final void punpcklqdq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PUNPCKLQDQ, dst, src);
}
/** Unpack Low Data (SSE2). */
public final void punpcklqdq(XMMRegister dst, Mem src)
{
emitX86(INST_PUNPCKLQDQ, dst, src);
}
/** Bitwise Exclusive OR (SSE2). */
public final void pxor(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PXOR, dst, src);
}
/** Bitwise Exclusive OR (SSE2). */
public final void pxor(XMMRegister dst, Mem src)
{
emitX86(INST_PXOR, dst, src);
}
/** Compute Square Roots of Packed DP-FP Values (SSE2). */
public final void sqrtpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_SQRTPD, dst, src);
}
/** Compute Square Roots of Packed DP-FP Values (SSE2). */
public final void sqrtpd(XMMRegister dst, Mem src)
{
emitX86(INST_SQRTPD, dst, src);
}
/** Compute Square Root of Scalar DP-FP Value (SSE2). */
public final void sqrtsd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_SQRTSD, dst, src);
}
/** Compute Square Root of Scalar DP-FP Value (SSE2). */
public final void sqrtsd(XMMRegister dst, Mem src)
{
emitX86(INST_SQRTSD, dst, src);
}
/** Packed DP-FP Subtract (SSE2). */
public final void subpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_SUBPD, dst, src);
}
/** Packed DP-FP Subtract (SSE2). */
public final void subpd(XMMRegister dst, Mem src)
{
emitX86(INST_SUBPD, dst, src);
}
/** Scalar DP-FP Subtract (SSE2). */
public final void subsd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_SUBSD, dst, src);
}
/** Scalar DP-FP Subtract (SSE2). */
public final void subsd(XMMRegister dst, Mem src)
{
emitX86(INST_SUBSD, dst, src);
}
/** Scalar Unordered DP-FP Compare and Set EFLAGS (SSE2). */
public final void ucomisd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_UCOMISD, dst, src);
}
/** Scalar Unordered DP-FP Compare and Set EFLAGS (SSE2). */
public final void ucomisd(XMMRegister dst, Mem src)
{
emitX86(INST_UCOMISD, dst, src);
}
/** Unpack and Interleave High Packed Double-Precision FP Values (SSE2). */
public final void unpckhpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_UNPCKHPD, dst, src);
}
/** Unpack and Interleave High Packed Double-Precision FP Values (SSE2). */
public final void unpckhpd(XMMRegister dst, Mem src)
{
emitX86(INST_UNPCKHPD, dst, src);
}
/** Unpack and Interleave Low Packed Double-Precision FP Values (SSE2). */
public final void unpcklpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_UNPCKLPD, dst, src);
}
/** Unpack and Interleave Low Packed Double-Precision FP Values (SSE2). */
public final void unpcklpd(XMMRegister dst, Mem src)
{
emitX86(INST_UNPCKLPD, dst, src);
}
/** Bit-wise Logical OR for DP-FP Data (SSE2). */
public final void xorpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_XORPD, dst, src);
}
/** Bit-wise Logical OR for DP-FP Data (SSE2). */
public final void xorpd(XMMRegister dst, Mem src)
{
emitX86(INST_XORPD, dst, src);
}
// -------------------------------------------------------------------------
// [SSE3]
// -------------------------------------------------------------------------
/** Packed DP-FP Add/Subtract (SSE3). */
public final void addsubpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_ADDSUBPD, dst, src);
}
/** Packed DP-FP Add/Subtract (SSE3). */
public final void addsubpd(XMMRegister dst, Mem src)
{
emitX86(INST_ADDSUBPD, dst, src);
}
/** Packed SP-FP Add/Subtract (SSE3). */
public final void addsubps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_ADDSUBPS, dst, src);
}
/** Packed SP-FP Add/Subtract (SSE3). */
public final void addsubps(XMMRegister dst, Mem src)
{
emitX86(INST_ADDSUBPS, dst, src);
}
/** Store Integer with Truncation (SSE3). */
public final void fisttp(Mem dst)
{
emitX86(INST_FISTTP, dst);
}
/** Packed DP-FP Horizontal Add (SSE3). */
public final void haddpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_HADDPD, dst, src);
}
/** Packed DP-FP Horizontal Add (SSE3). */
public final void haddpd(XMMRegister dst, Mem src)
{
emitX86(INST_HADDPD, dst, src);
}
/** Packed SP-FP Horizontal Add (SSE3). */
public final void haddps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_HADDPS, dst, src);
}
/** Packed SP-FP Horizontal Add (SSE3). */
public final void haddps(XMMRegister dst, Mem src)
{
emitX86(INST_HADDPS, dst, src);
}
/** Packed DP-FP Horizontal Subtract (SSE3). */
public final void hsubpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_HSUBPD, dst, src);
}
/** Packed DP-FP Horizontal Subtract (SSE3). */
public final void hsubpd(XMMRegister dst, Mem src)
{
emitX86(INST_HSUBPD, dst, src);
}
/** Packed SP-FP Horizontal Subtract (SSE3). */
public final void hsubps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_HSUBPS, dst, src);
}
/** Packed SP-FP Horizontal Subtract (SSE3). */
public final void hsubps(XMMRegister dst, Mem src)
{
emitX86(INST_HSUBPS, dst, src);
}
/** Load Unaligned Integer 128 Bits (SSE3). */
public final void lddqu(XMMRegister dst, Mem src)
{
emitX86(INST_LDDQU, dst, src);
}
/** Set Up Monitor Address (SSE3). */
public final void monitor()
{
emitX86(INST_MONITOR);
}
/** Move One DP-FP and Duplicate (SSE3). */
public final void movddup(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVDDUP, dst, src);
}
/** Move One DP-FP and Duplicate (SSE3). */
public final void movddup(XMMRegister dst, Mem src)
{
emitX86(INST_MOVDDUP, dst, src);
}
/** Move Packed SP-FP High and Duplicate (SSE3). */
public final void movshdup(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVSHDUP, dst, src);
}
/** Move Packed SP-FP High and Duplicate (SSE3). */
public final void movshdup(XMMRegister dst, Mem src)
{
emitX86(INST_MOVSHDUP, dst, src);
}
/** Move Packed SP-FP Low and Duplicate (SSE3). */
public final void movsldup(XMMRegister dst, XMMRegister src)
{
emitX86(INST_MOVSLDUP, dst, src);
}
/** Move Packed SP-FP Low and Duplicate (SSE3). */
public final void movsldup(XMMRegister dst, Mem src)
{
emitX86(INST_MOVSLDUP, dst, src);
}
/** Monitor Wait (SSE3). */
public final void mwait()
{
emitX86(INST_MWAIT);
}
// -------------------------------------------------------------------------
// [SSSE3]
// -------------------------------------------------------------------------
/** Packed SIGN (SSSE3). */
public final void psignb(MMRegister dst, MMRegister src)
{
emitX86(INST_PSIGNB, dst, src);
}
/** Packed SIGN (SSSE3). */
public final void psignb(MMRegister dst, Mem src)
{
emitX86(INST_PSIGNB, dst, src);
}
/** Packed SIGN (SSSE3). */
public final void psignb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSIGNB, dst, src);
}
/** Packed SIGN (SSSE3). */
public final void psignb(XMMRegister dst, Mem src)
{
emitX86(INST_PSIGNB, dst, src);
}
/** Packed SIGN (SSSE3). */
public final void psignw(MMRegister dst, MMRegister src)
{
emitX86(INST_PSIGNW, dst, src);
}
/** Packed SIGN (SSSE3). */
public final void psignw(MMRegister dst, Mem src)
{
emitX86(INST_PSIGNW, dst, src);
}
/** Packed SIGN (SSSE3). */
public final void psignw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSIGNW, dst, src);
}
/** Packed SIGN (SSSE3). */
public final void psignw(XMMRegister dst, Mem src)
{
emitX86(INST_PSIGNW, dst, src);
}
/** Packed SIGN (SSSE3). */
public final void psignd(MMRegister dst, MMRegister src)
{
emitX86(INST_PSIGND, dst, src);
}
/** Packed SIGN (SSSE3). */
public final void psignd(MMRegister dst, Mem src)
{
emitX86(INST_PSIGND, dst, src);
}
/** Packed SIGN (SSSE3). */
public final void psignd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSIGND, dst, src);
}
/** Packed SIGN (SSSE3). */
public final void psignd(XMMRegister dst, Mem src)
{
emitX86(INST_PSIGND, dst, src);
}
/** Packed Horizontal Add (SSSE3). */
public final void phaddw(MMRegister dst, MMRegister src)
{
emitX86(INST_PHADDW, dst, src);
}
/** Packed Horizontal Add (SSSE3). */
public final void phaddw(MMRegister dst, Mem src)
{
emitX86(INST_PHADDW, dst, src);
}
/** Packed Horizontal Add (SSSE3). */
public final void phaddw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PHADDW, dst, src);
}
/** Packed Horizontal Add (SSSE3). */
public final void phaddw(XMMRegister dst, Mem src)
{
emitX86(INST_PHADDW, dst, src);
}
/** Packed Horizontal Add (SSSE3). */
public final void phaddd(MMRegister dst, MMRegister src)
{
emitX86(INST_PHADDD, dst, src);
}
/** Packed Horizontal Add (SSSE3). */
public final void phaddd(MMRegister dst, Mem src)
{
emitX86(INST_PHADDD, dst, src);
}
/** Packed Horizontal Add (SSSE3). */
public final void phaddd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PHADDD, dst, src);
}
/** Packed Horizontal Add (SSSE3). */
public final void phaddd(XMMRegister dst, Mem src)
{
emitX86(INST_PHADDD, dst, src);
}
/** Packed Horizontal Add and Saturate (SSSE3). */
public final void phaddsw(MMRegister dst, MMRegister src)
{
emitX86(INST_PHADDSW, dst, src);
}
/** Packed Horizontal Add and Saturate (SSSE3). */
public final void phaddsw(MMRegister dst, Mem src)
{
emitX86(INST_PHADDSW, dst, src);
}
/** Packed Horizontal Add and Saturate (SSSE3). */
public final void phaddsw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PHADDSW, dst, src);
}
/** Packed Horizontal Add and Saturate (SSSE3). */
public final void phaddsw(XMMRegister dst, Mem src)
{
emitX86(INST_PHADDSW, dst, src);
}
/** Packed Horizontal Subtract (SSSE3). */
public final void phsubw(MMRegister dst, MMRegister src)
{
emitX86(INST_PHSUBW, dst, src);
}
/** Packed Horizontal Subtract (SSSE3). */
public final void phsubw(MMRegister dst, Mem src)
{
emitX86(INST_PHSUBW, dst, src);
}
/** Packed Horizontal Subtract (SSSE3). */
public final void phsubw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PHSUBW, dst, src);
}
/** Packed Horizontal Subtract (SSSE3). */
public final void phsubw(XMMRegister dst, Mem src)
{
emitX86(INST_PHSUBW, dst, src);
}
/** Packed Horizontal Subtract (SSSE3). */
public final void phsubd(MMRegister dst, MMRegister src)
{
emitX86(INST_PHSUBD, dst, src);
}
/** Packed Horizontal Subtract (SSSE3). */
public final void phsubd(MMRegister dst, Mem src)
{
emitX86(INST_PHSUBD, dst, src);
}
/** Packed Horizontal Subtract (SSSE3). */
public final void phsubd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PHSUBD, dst, src);
}
/** Packed Horizontal Subtract (SSSE3). */
public final void phsubd(XMMRegister dst, Mem src)
{
emitX86(INST_PHSUBD, dst, src);
}
/** Packed Horizontal Subtract and Saturate (SSSE3). */
public final void phsubsw(MMRegister dst, MMRegister src)
{
emitX86(INST_PHSUBSW, dst, src);
}
/** Packed Horizontal Subtract and Saturate (SSSE3). */
public final void phsubsw(MMRegister dst, Mem src)
{
emitX86(INST_PHSUBSW, dst, src);
}
/** Packed Horizontal Subtract and Saturate (SSSE3). */
public final void phsubsw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PHSUBSW, dst, src);
}
/** Packed Horizontal Subtract and Saturate (SSSE3). */
public final void phsubsw(XMMRegister dst, Mem src)
{
emitX86(INST_PHSUBSW, dst, src);
}
/** Multiply and Add Packed Signed and Unsigned Bytes (SSSE3). */
public final void pmaddubsw(MMRegister dst, MMRegister src)
{
emitX86(INST_PMADDUBSW, dst, src);
}
/** Multiply and Add Packed Signed and Unsigned Bytes (SSSE3). */
public final void pmaddubsw(MMRegister dst, Mem src)
{
emitX86(INST_PMADDUBSW, dst, src);
}
/** Multiply and Add Packed Signed and Unsigned Bytes (SSSE3). */
public final void pmaddubsw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMADDUBSW, dst, src);
}
/** Multiply and Add Packed Signed and Unsigned Bytes (SSSE3). */
public final void pmaddubsw(XMMRegister dst, Mem src)
{
emitX86(INST_PMADDUBSW, dst, src);
}
/** Packed Absolute Value (SSSE3). */
public final void pabsb(MMRegister dst, MMRegister src)
{
emitX86(INST_PABSB, dst, src);
}
/** Packed Absolute Value (SSSE3). */
public final void pabsb(MMRegister dst, Mem src)
{
emitX86(INST_PABSB, dst, src);
}
/** Packed Absolute Value (SSSE3). */
public final void pabsb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PABSB, dst, src);
}
/** Packed Absolute Value (SSSE3). */
public final void pabsb(XMMRegister dst, Mem src)
{
emitX86(INST_PABSB, dst, src);
}
/** Packed Absolute Value (SSSE3). */
public final void pabsw(MMRegister dst, MMRegister src)
{
emitX86(INST_PABSW, dst, src);
}
/** Packed Absolute Value (SSSE3). */
public final void pabsw(MMRegister dst, Mem src)
{
emitX86(INST_PABSW, dst, src);
}
/** Packed Absolute Value (SSSE3). */
public final void pabsw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PABSW, dst, src);
}
/** Packed Absolute Value (SSSE3). */
public final void pabsw(XMMRegister dst, Mem src)
{
emitX86(INST_PABSW, dst, src);
}
/** Packed Absolute Value (SSSE3). */
public final void pabsd(MMRegister dst, MMRegister src)
{
emitX86(INST_PABSD, dst, src);
}
/** Packed Absolute Value (SSSE3). */
public final void pabsd(MMRegister dst, Mem src)
{
emitX86(INST_PABSD, dst, src);
}
/** Packed Absolute Value (SSSE3). */
public final void pabsd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PABSD, dst, src);
}
/** Packed Absolute Value (SSSE3). */
public final void pabsd(XMMRegister dst, Mem src)
{
emitX86(INST_PABSD, dst, src);
}
/** Packed Multiply High with Round and Scale (SSSE3). */
public final void pmulhrsw(MMRegister dst, MMRegister src)
{
emitX86(INST_PMULHRSW, dst, src);
}
/** Packed Multiply High with Round and Scale (SSSE3). */
public final void pmulhrsw(MMRegister dst, Mem src)
{
emitX86(INST_PMULHRSW, dst, src);
}
/** Packed Multiply High with Round and Scale (SSSE3). */
public final void pmulhrsw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMULHRSW, dst, src);
}
/** Packed Multiply High with Round and Scale (SSSE3). */
public final void pmulhrsw(XMMRegister dst, Mem src)
{
emitX86(INST_PMULHRSW, dst, src);
}
/** Packed Shuffle Bytes (SSSE3). */
public final void pshufb(MMRegister dst, MMRegister src)
{
emitX86(INST_PSHUFB, dst, src);
}
/** Packed Shuffle Bytes (SSSE3). */
public final void pshufb(MMRegister dst, Mem src)
{
emitX86(INST_PSHUFB, dst, src);
}
/** Packed Shuffle Bytes (SSSE3). */
public final void pshufb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PSHUFB, dst, src);
}
/** Packed Shuffle Bytes (SSSE3). */
public final void pshufb(XMMRegister dst, Mem src)
{
emitX86(INST_PSHUFB, dst, src);
}
/** Packed Shuffle Bytes (SSSE3). */
public final void palignr(MMRegister dst, MMRegister src, Immediate imm8)
{
emitX86(INST_PALIGNR, dst, src, imm8);
}
/** Packed Shuffle Bytes (SSSE3). */
public final void palignr(MMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PALIGNR, dst, src, imm8);
}
/** Packed Shuffle Bytes (SSSE3). */
public final void palignr(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PALIGNR, dst, src, imm8);
}
/** Packed Shuffle Bytes (SSSE3). */
public final void palignr(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PALIGNR, dst, src, imm8);
}
// -------------------------------------------------------------------------
// [SSE4.1]
// -------------------------------------------------------------------------
/** Blend Packed DP-FP Values (SSE4.1). */
public final void blendpd(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_BLENDPD, dst, src, imm8);
}
/** Blend Packed DP-FP Values (SSE4.1). */
public final void blendpd(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_BLENDPD, dst, src, imm8);
}
/** Blend Packed SP-FP Values (SSE4.1). */
public final void blendps(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_BLENDPS, dst, src, imm8);
}
/** Blend Packed SP-FP Values (SSE4.1). */
public final void blendps(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_BLENDPS, dst, src, imm8);
}
/** Variable Blend Packed DP-FP Values (SSE4.1). */
public final void blendvpd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_BLENDVPD, dst, src);
}
/** Variable Blend Packed DP-FP Values (SSE4.1). */
public final void blendvpd(XMMRegister dst, Mem src)
{
emitX86(INST_BLENDVPD, dst, src);
}
/** Variable Blend Packed SP-FP Values (SSE4.1). */
public final void blendvps(XMMRegister dst, XMMRegister src)
{
emitX86(INST_BLENDVPS, dst, src);
}
/** Variable Blend Packed SP-FP Values (SSE4.1). */
public final void blendvps(XMMRegister dst, Mem src)
{
emitX86(INST_BLENDVPS, dst, src);
}
/** Dot Product of Packed DP-FP Values (SSE4.1). */
public final void dppd(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_DPPD, dst, src, imm8);
}
/** Dot Product of Packed DP-FP Values (SSE4.1). */
public final void dppd(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_DPPD, dst, src, imm8);
}
/** Dot Product of Packed SP-FP Values (SSE4.1). */
public final void dpps(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_DPPS, dst, src, imm8);
}
/** Dot Product of Packed SP-FP Values (SSE4.1). */
public final void dpps(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_DPPS, dst, src, imm8);
}
/** Extract Packed SP-FP Value @brief (SSE4.1). */
public final void extractps(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_EXTRACTPS, dst, src, imm8);
}
/** Extract Packed SP-FP Value @brief (SSE4.1). */
public final void extractps(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_EXTRACTPS, dst, src, imm8);
}
/** Load Double Quadword Non-Temporal Aligned Hint (SSE4.1). */
public final void movntdqa(XMMRegister dst, Mem src)
{
emitX86(INST_MOVNTDQA, dst, src);
}
/** Compute Multiple Packed Sums of Absolute Difference (SSE4.1). */
public final void mpsadbw(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_MPSADBW, dst, src, imm8);
}
/** Compute Multiple Packed Sums of Absolute Difference (SSE4.1). */
public final void mpsadbw(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_MPSADBW, dst, src, imm8);
}
/** Pack with Unsigned Saturation (SSE4.1). */
public final void packusdw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PACKUSDW, dst, src);
}
/** Pack with Unsigned Saturation (SSE4.1). */
public final void packusdw(XMMRegister dst, Mem src)
{
emitX86(INST_PACKUSDW, dst, src);
}
/** Variable Blend Packed Bytes (SSE4.1). */
public final void pblendvb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PBLENDVB, dst, src);
}
/** Variable Blend Packed Bytes (SSE4.1). */
public final void pblendvb(XMMRegister dst, Mem src)
{
emitX86(INST_PBLENDVB, dst, src);
}
/** Blend Packed Words (SSE4.1). */
public final void pblendw(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PBLENDW, dst, src, imm8);
}
/** Blend Packed Words (SSE4.1). */
public final void pblendw(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PBLENDW, dst, src, imm8);
}
/** Compare Packed Qword Data for Equal (SSE4.1). */
public final void pcmpeqq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PCMPEQQ, dst, src);
}
/** Compare Packed Qword Data for Equal (SSE4.1). */
public final void pcmpeqq(XMMRegister dst, Mem src)
{
emitX86(INST_PCMPEQQ, dst, src);
}
/** Extract Byte (SSE4.1). */
public final void pextrb(Register dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PEXTRB, dst, src, imm8);
}
/** Extract Byte (SSE4.1). */
public final void pextrb(Mem dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PEXTRB, dst, src, imm8);
}
/** Extract Dword (SSE4.1). */
public final void pextrd(Register dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PEXTRD, dst, src, imm8);
}
/** Extract Dword (SSE4.1). */
public final void pextrd(Mem dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PEXTRD, dst, src, imm8);
}
/** Extract Dword (SSE4.1). */
public final void pextrq(Register dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PEXTRQ, dst, src, imm8);
}
/** Extract Dword (SSE4.1). */
public final void pextrq(Mem dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PEXTRQ, dst, src, imm8);
}
/** Extract Word (SSE4.1). */
public final void pextrw(Register dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PEXTRW, dst, src, imm8);
}
/** Extract Word (SSE4.1). */
public final void pextrw(Mem dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PEXTRW, dst, src, imm8);
}
/** Packed Horizontal Word Minimum (SSE4.1). */
public final void phminposuw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PHMINPOSUW, dst, src);
}
/** Packed Horizontal Word Minimum (SSE4.1). */
public final void phminposuw(XMMRegister dst, Mem src)
{
emitX86(INST_PHMINPOSUW, dst, src);
}
/** Insert Byte (SSE4.1). */
public final void pinsrb(XMMRegister dst, Register src, Immediate imm8)
{
emitX86(INST_PINSRB, dst, src, imm8);
}
/** Insert Byte (SSE4.1). */
public final void pinsrb(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PINSRB, dst, src, imm8);
}
/** Insert Dword (SSE4.1). */
public final void pinsrd(XMMRegister dst, Register src, Immediate imm8)
{
emitX86(INST_PINSRD, dst, src, imm8);
}
/** Insert Dword (SSE4.1). */
public final void pinsrd(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PINSRD, dst, src, imm8);
}
/** Insert Dword (SSE4.1). */
public final void pinsrq(XMMRegister dst, Register src, Immediate imm8)
{
emitX86(INST_PINSRQ, dst, src, imm8);
}
/** Insert Dword (SSE4.1). */
public final void pinsrq(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PINSRQ, dst, src, imm8);
}
/** Insert Word (SSE2). */
public final void pinsrw(XMMRegister dst, Register src, Immediate imm8)
{
emitX86(INST_PINSRW, dst, src, imm8);
}
/** Insert Word (SSE2). */
public final void pinsrw(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PINSRW, dst, src, imm8);
}
/** Maximum of Packed Word Integers (SSE4.1). */
public final void pmaxuw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMAXUW, dst, src);
}
/** Maximum of Packed Word Integers (SSE4.1). */
public final void pmaxuw(XMMRegister dst, Mem src)
{
emitX86(INST_PMAXUW, dst, src);
}
/** Maximum of Packed Signed Byte Integers (SSE4.1). */
public final void pmaxsb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMAXSB, dst, src);
}
/** Maximum of Packed Signed Byte Integers (SSE4.1). */
public final void pmaxsb(XMMRegister dst, Mem src)
{
emitX86(INST_PMAXSB, dst, src);
}
/** Maximum of Packed Signed Dword Integers (SSE4.1). */
public final void pmaxsd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMAXSD, dst, src);
}
/** Maximum of Packed Signed Dword Integers (SSE4.1). */
public final void pmaxsd(XMMRegister dst, Mem src)
{
emitX86(INST_PMAXSD, dst, src);
}
/** Maximum of Packed Unsigned Dword Integers (SSE4.1). */
public final void pmaxud(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMAXUD, dst, src);
}
/** Maximum of Packed Unsigned Dword Integers (SSE4.1). */
public final void pmaxud(XMMRegister dst, Mem src)
{
emitX86(INST_PMAXUD, dst, src);
}
/** Minimum of Packed Signed Byte Integers (SSE4.1). */
public final void pminsb(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMINSB, dst, src);
}
/** Minimum of Packed Signed Byte Integers (SSE4.1). */
public final void pminsb(XMMRegister dst, Mem src)
{
emitX86(INST_PMINSB, dst, src);
}
/** Minimum of Packed Word Integers (SSE4.1). */
public final void pminuw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMINUW, dst, src);
}
/** Minimum of Packed Word Integers (SSE4.1). */
public final void pminuw(XMMRegister dst, Mem src)
{
emitX86(INST_PMINUW, dst, src);
}
/** Minimum of Packed Dword Integers (SSE4.1). */
public final void pminud(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMINUD, dst, src);
}
/** Minimum of Packed Dword Integers (SSE4.1). */
public final void pminud(XMMRegister dst, Mem src)
{
emitX86(INST_PMINUD, dst, src);
}
/** Minimum of Packed Dword Integers (SSE4.1). */
public final void pminsd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMINSD, dst, src);
}
/** Minimum of Packed Dword Integers (SSE4.1). */
public final void pminsd(XMMRegister dst, Mem src)
{
emitX86(INST_PMINSD, dst, src);
}
/** Packed Move with Sign Extend (SSE4.1). */
public final void pmovsxbw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMOVSXBW, dst, src);
}
/** Packed Move with Sign Extend (SSE4.1). */
public final void pmovsxbw(XMMRegister dst, Mem src)
{
emitX86(INST_PMOVSXBW, dst, src);
}
/** Packed Move with Sign Extend (SSE4.1). */
public final void pmovsxbd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMOVSXBD, dst, src);
}
/** Packed Move with Sign Extend (SSE4.1). */
public final void pmovsxbd(XMMRegister dst, Mem src)
{
emitX86(INST_PMOVSXBD, dst, src);
}
/** Packed Move with Sign Extend (SSE4.1). */
public final void pmovsxbq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMOVSXBQ, dst, src);
}
/** Packed Move with Sign Extend (SSE4.1). */
public final void pmovsxbq(XMMRegister dst, Mem src)
{
emitX86(INST_PMOVSXBQ, dst, src);
}
/** Packed Move with Sign Extend (SSE4.1). */
public final void pmovsxwd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMOVSXWD, dst, src);
}
/** Packed Move with Sign Extend (SSE4.1). */
public final void pmovsxwd(XMMRegister dst, Mem src)
{
emitX86(INST_PMOVSXWD, dst, src);
}
/** (SSE4.1). */
public final void pmovsxwq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMOVSXWQ, dst, src);
}
/** (SSE4.1). */
public final void pmovsxwq(XMMRegister dst, Mem src)
{
emitX86(INST_PMOVSXWQ, dst, src);
}
/** (SSE4.1). */
public final void pmovsxdq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMOVSXDQ, dst, src);
}
/** (SSE4.1). */
public final void pmovsxdq(XMMRegister dst, Mem src)
{
emitX86(INST_PMOVSXDQ, dst, src);
}
/** Packed Move with Zero Extend (SSE4.1). */
public final void pmovzxbw(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMOVZXBW, dst, src);
}
/** Packed Move with Zero Extend (SSE4.1). */
public final void pmovzxbw(XMMRegister dst, Mem src)
{
emitX86(INST_PMOVZXBW, dst, src);
}
/** Packed Move with Zero Extend (SSE4.1). */
public final void pmovzxbd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMOVZXBD, dst, src);
}
/** Packed Move with Zero Extend (SSE4.1). */
public final void pmovzxbd(XMMRegister dst, Mem src)
{
emitX86(INST_PMOVZXBD, dst, src);
}
/** Packed Move with Zero Extend (SSE4.1). */
public final void pmovzxbq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMOVZXBQ, dst, src);
}
/** Packed Move with Zero Extend (SSE4.1). */
public final void pmovzxbq(XMMRegister dst, Mem src)
{
emitX86(INST_PMOVZXBQ, dst, src);
}
/** Packed Move with Zero Extend (SSE4.1). */
public final void pmovzxwd(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMOVZXWD, dst, src);
}
/** Packed Move with Zero Extend (SSE4.1). */
public final void pmovzxwd(XMMRegister dst, Mem src)
{
emitX86(INST_PMOVZXWD, dst, src);
}
/** (SSE4.1). */
public final void pmovzxwq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMOVZXWQ, dst, src);
}
/** (SSE4.1). */
public final void pmovzxwq(XMMRegister dst, Mem src)
{
emitX86(INST_PMOVZXWQ, dst, src);
}
/** (SSE4.1). */
public final void pmovzxdq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMOVZXDQ, dst, src);
}
/** (SSE4.1). */
public final void pmovzxdq(XMMRegister dst, Mem src)
{
emitX86(INST_PMOVZXDQ, dst, src);
}
/** Multiply Packed Signed Dword Integers (SSE4.1). */
public final void pmuldq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMULDQ, dst, src);
}
/** Multiply Packed Signed Dword Integers (SSE4.1). */
public final void pmuldq(XMMRegister dst, Mem src)
{
emitX86(INST_PMULDQ, dst, src);
}
/** Multiply Packed Signed Integers and Store Low Result (SSE4.1). */
public final void pmulld(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PMULLD, dst, src);
}
/** Multiply Packed Signed Integers and Store Low Result (SSE4.1). */
public final void pmulld(XMMRegister dst, Mem src)
{
emitX86(INST_PMULLD, dst, src);
}
/** Logical Compare (SSE4.1). */
public final void ptest(XMMRegister op1, XMMRegister op2)
{
emitX86(INST_PTEST, op1, op2);
}
/** Logical Compare (SSE4.1). */
public final void ptest(XMMRegister op1, Mem op2)
{
emitX86(INST_PTEST, op1, op2);
}
//! Round Packed SP-FP Values @brief (SSE4.1).
public final void roundps(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_ROUNDPS, dst, src, imm8);
}
//! Round Packed SP-FP Values @brief (SSE4.1).
public final void roundps(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_ROUNDPS, dst, src, imm8);
}
/** Round Scalar SP-FP Values (SSE4.1). */
public final void roundss(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_ROUNDSS, dst, src, imm8);
}
/** Round Scalar SP-FP Values (SSE4.1). */
public final void roundss(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_ROUNDSS, dst, src, imm8);
}
/** Round Packed DP-FP Values (SSE4.1). */
public final void roundpd(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_ROUNDPD, dst, src, imm8);
}
/** Round Packed DP-FP Values (SSE4.1). */
public final void roundpd(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_ROUNDPD, dst, src, imm8);
}
/** Round Scalar DP-FP Values (SSE4.1). */
public final void roundsd(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_ROUNDSD, dst, src, imm8);
}
/** Round Scalar DP-FP Values (SSE4.1). */
public final void roundsd(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_ROUNDSD, dst, src, imm8);
}
// -------------------------------------------------------------------------
// [SSE4.2]
// -------------------------------------------------------------------------
/** Accumulate CRC32 Value (polynomial 0x11EDC6F41) (SSE4.2). */
public final void crc32(Register dst, Register src)
{
assert(dst.isRegType(REG_GPD) || dst.isRegType(REG_GPQ));
emitX86(INST_CRC32, dst, src);
}
/** Accumulate CRC32 Value (polynomial 0x11EDC6F41) (SSE4.2). */
public final void crc32(Register dst, Mem src)
{
assert(dst.isRegType(REG_GPD) || dst.isRegType(REG_GPQ));
emitX86(INST_CRC32, dst, src);
}
/** Packed Compare Explicit Length Strings, Return Index (SSE4.2). */
public final void pcmpestri(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PCMPESTRI, dst, src, imm8);
}
/** Packed Compare Explicit Length Strings, Return Index (SSE4.2). */
public final void pcmpestri(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PCMPESTRI, dst, src, imm8);
}
/** Packed Compare Explicit Length Strings, Return Mask (SSE4.2). */
public final void pcmpestrm(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PCMPESTRM, dst, src, imm8);
}
/** Packed Compare Explicit Length Strings, Return Mask (SSE4.2). */
public final void pcmpestrm(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PCMPESTRM, dst, src, imm8);
}
/** Packed Compare Implicit Length Strings, Return Index (SSE4.2). */
public final void pcmpistri(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PCMPISTRI, dst, src, imm8);
}
/** Packed Compare Implicit Length Strings, Return Index (SSE4.2). */
public final void pcmpistri(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PCMPISTRI, dst, src, imm8);
}
/** Packed Compare Implicit Length Strings, Return Mask (SSE4.2). */
public final void pcmpistrm(XMMRegister dst, XMMRegister src, Immediate imm8)
{
emitX86(INST_PCMPISTRM, dst, src, imm8);
}
/** Packed Compare Implicit Length Strings, Return Mask (SSE4.2). */
public final void pcmpistrm(XMMRegister dst, Mem src, Immediate imm8)
{
emitX86(INST_PCMPISTRM, dst, src, imm8);
}
/** Compare Packed Data for Greater Than (SSE4.2). */
public final void pcmpgtq(XMMRegister dst, XMMRegister src)
{
emitX86(INST_PCMPGTQ, dst, src);
}
/** Compare Packed Data for Greater Than (SSE4.2). */
public final void pcmpgtq(XMMRegister dst, Mem src)
{
emitX86(INST_PCMPGTQ, dst, src);
}
/** Return the Count of Number of Bits Set to 1 (SSE4.2). */
public final void popcnt(Register dst, Register src)
{
assert(!dst.isRegType(REG_GPB));
assert(src.type() == dst.type());
emitX86(INST_POPCNT, dst, src);
}
/** Return the Count of Number of Bits Set to 1 (SSE4.2). */
public final void popcnt(Register dst, Mem src)
{
assert(!dst.isRegType(REG_GPB));
emitX86(INST_POPCNT, dst, src);
}
// -------------------------------------------------------------------------
// [AMD only]
// -------------------------------------------------------------------------
/** Prefetch (3dNow - Amd). */
//!
//! Loads the entire 64-byte aligned memory sequence containing the
//! specified memory address into the L1 data cache. The position of
//! the specified memory address within the 64-byte cache line is
//! irrelevant. If a cache hit occurs, or if a memory fault is detected,
//! no bus cycle is initiated and the instruction is treated as a NOP.
public final void amd_prefetch(Mem mem)
{
emitX86(INST_AMD_PREFETCH, mem);
}
/** Prefetch and set cache to modified (3dNow - Amd). */
//!
//! The PREFETCHW instruction loads the prefetched line and sets the
//! cache-line state to Modified, in anticipation of subsequent data
//! writes to the line. The PREFETCH instruction, by contrast, typically
//! sets the cache-line state to Exclusive (depending on the hardware
//! implementation).
public final void amd_prefetchw(Mem mem)
{
emitX86(INST_AMD_PREFETCHW, mem);
}
// -------------------------------------------------------------------------
// [Intel only]
// -------------------------------------------------------------------------
/** Move Data After Swapping Bytes (SSE3 - Intel Atom). */
public final void movbe(Register dst, Mem src)
{
assert(!dst.isRegType(REG_GPB));
emitX86(INST_MOVBE, dst, src);
}
/** Move Data After Swapping Bytes (SSE3 - Intel Atom). */
public final void movbe(Mem dst, Register src)
{
assert(!src.isRegType(REG_GPB));
emitX86(INST_MOVBE, dst, src);
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/Assembler.java 0000644 0001750 0001750 00000172372 11425031554 022374 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
import java.nio.ByteBuffer;
import java.util.LinkedList;
import java.util.List;
import static com.kenai.jnr.x86asm.HINT.*;
import static com.kenai.jnr.x86asm.INST_CODE.*;
import static com.kenai.jnr.x86asm.InstructionGroup.*;
import static com.kenai.jnr.x86asm.OP.*;
import static com.kenai.jnr.x86asm.OperandFlags.*;
import static com.kenai.jnr.x86asm.PROPERTY.*;
import static com.kenai.jnr.x86asm.RELOC_MODE.*;
import static com.kenai.jnr.x86asm.REG.*;
import static com.kenai.jnr.x86asm.Util.*;
/**
* Low level code generation.
*/
public final class Assembler extends Serializer {
private final CodeBuffer _buffer = new CodeBuffer();
private final List _relocData = new LinkedList();
private final CpuInfo cpuInfo = CpuInfo.GENERIC;
private int _properties = 0;
/** Size of possible trampolines. */
int _trampolineSize;
private final Logger _logger = null;
private final CPU cpu;
@Override
boolean is64() {
return cpu == CPU.X86_64;
}
private static final int intValue(boolean b) {
return b ? 1 : 0;
}
public static final CPU I386 = CPU.I386;
public static final CPU X86_64 = CPU.X86_64;
public Assembler(CPU cpu) {
this.cpu = cpu;
}
public final int offset() {
return _buffer.offset();
}
/** Gets the required size of memory required to store all the generated code */
public final int codeSize() {
return _buffer.offset() + trampolineSize();
}
/** Return size of all possible trampolines needed to successfuly generate
* relative jumps to absolute addresses. This value is only non-zero if jmp
* of call instructions were used with immediate operand (this means jump or
* call absolute address directly).
*
* Currently only _emitJmpOrCallReloc() method can increase trampoline size
* value.
*/
int trampolineSize() {
return _trampolineSize;
}
//! @brief Set byte at position @a pos.
public final byte getByteAt(int pos) {
return _buffer.getByteAt(pos);
}
//! @brief Set word at position @a pos.
public final short getWordAt(int pos) {
return _buffer.getWordAt(pos);
}
//! @brief Set word at position @a pos.
public final int getDWordAt(int pos) {
return _buffer.getDWordAt(pos);
}
//! @brief Set word at position @a pos.
public final long getQWordAt(int pos) {
return _buffer.getQWordAt(pos);
}
//! @brief Set byte at position @a pos.
public final void setByteAt(int pos, byte x) {
_buffer.setByteAt(pos, x);
}
//! @brief Set word at position @a pos.
public final void setWordAt(int pos, short x) {
_buffer.setWordAt(pos, x);
}
//! @brief Set word at position @a pos.
public final void setDWordAt(int pos, int x) {
_buffer.setDWordAt(pos, x);
}
//! @brief Set word at position @a pos.
public final void setQWordAt(int pos, long x) {
_buffer.setQWordAt(pos, x);
}
//! @brief Set word at position @a pos.
public final int getInt32At(int pos) {
return (int) _buffer.getDWordAt(pos);
}
//! @brief Set int32 at position @a pos.
public final void setInt32At(int pos, long x) {
_buffer.setDWordAt(pos, (int) x);
}
public final void setVarAt(int pos, long i, boolean isUnsigned, int size) {
switch (size) {
case 1:
setByteAt(pos, (byte) i);
break;
case 2:
setWordAt(pos, (short) i);
break;
case 4:
setDWordAt(pos, (int) i);
break;
case 8:
setQWordAt(pos, i);
default:
throw new IllegalArgumentException("invalid size");
}
}
/** Emit Byte to internal buffer. */
final void _emitByte(int x) {
_buffer.emitByte((byte) x);
}
/** Emit Word (2 bytes) to internal buffer. */
final void _emitWord(int x) {
_buffer.emitWord((short) x);
}
/** Emit DWord (4 bytes) to internal buffer. */
final void _emitDWord(int x) {
_buffer.emitDWord(x);
}
/** Emit QWord (8 bytes) to internal buffer. */
final void _emitQWord(long x) {
_buffer.emitQWord(x);
}
/** Emit Int32 (4 bytes) to internal buffer. */
final void _emitInt32(int x) {
_buffer.emitDWord(x);
}
/** Emit system signed integer (4 or 8 bytes) to internal buffer. */
final void _emitSysInt(long x) {
if (is64()) {
_buffer.emitQWord(x);
} else {
_buffer.emitDWord((int) x);
}
}
//! @brief Emit single @a opCode without operands.
final void _emitOpCode(int opCode) {
// instruction prefix
if ((opCode & 0xFF000000) != 0) {
_emitByte((byte) ((opCode & 0xFF000000) >> 24));
}
// instruction opcodes
if ((opCode & 0x00FF0000) != 0) {
_emitByte((byte) ((opCode & 0x00FF0000) >> 16));
}
if ((opCode & 0x0000FF00) != 0) {
_emitByte((byte) ((opCode & 0x0000FF00) >> 8));
}
// last opcode is always emitted (can be also 0x00)
_emitByte((byte) (opCode & 0x000000FF));
}
void _emitSegmentPrefix(Operand rm) {
if (rm.isMem()) {
SEGMENT segmentPrefix = ((Mem) rm).segmentPrefix();
if (segmentPrefix != SEGMENT.SEGMENT_NONE) {
_emitByte(segmentPrefix.prefix());
}
}
}
void _emitImmediate(Immediate imm, int size) {
switch (size) {
case 1:
_emitByte(imm.byteValue());
break;
case 2:
_emitWord(imm.shortValue());
break;
case 4:
_emitDWord(imm.intValue());
break;
case 8:
if (!is64()) {
throw new IllegalArgumentException("64 bit immediate values not supported for 32bit");
}
_emitQWord(imm.longValue());
break;
default:
throw new IllegalArgumentException("invalid immediate operand size");
}
}
/** Emit REX prefix (64 bit mode only). */
void _emitRexR(int w, int opReg, int regCode) {
if (is64()) {
boolean r = (opReg & 0x8) != 0;
boolean b = (regCode & 0x8) != 0;
// w Default operand size(0=Default, 1=64 bits).
// r Register field (1=high bit extension of the ModR/M REG field).
// x Index field not used in RexR
// b Base field (1=high bit extension of the ModR/M or SIB Base field).
if (w != 0 || r || b || (_properties & (1 << PROPERTY_X86_FORCE_REX)) != 0) {
_emitByte(0x40 | (w << 3) | (intValue(r) << 2) | intValue(b));
}
}
}
void _emitRexR(boolean w, int opReg, int regCode) {
_emitRexR(intValue(w), opReg, regCode);
}
/** Emit REX prefix (64 bit mode only). */
void _emitRexRM(int w, int opReg, Operand rm) {
if (is64()) {
boolean r = (opReg & 0x8) != 0;
boolean x = false;
boolean b = false;
if (rm.isReg()) {
b = (((BaseReg) rm).code() & 0x8) != 0;
} else if (rm.isMem()) {
x = (((Mem) rm).index() & 0x8) != 0 && ((Mem) rm).index() != NO_REG;
b = (((Mem) rm).base() & 0x8) != 0 && ((Mem) rm).base() != NO_REG;
}
// w Default operand size(0=Default, 1=64 bits).
// r Register field (1=high bit extension of the ModR/M REG field).
// x Index field (1=high bit extension of the SIB Index field).
// b Base field (1=high bit extension of the ModR/M or SIB Base field).
if (w != 0 || r || x || b || (_properties & (1 << PROPERTY_X86_FORCE_REX)) != 0) {
_emitByte(0x40 | (w << 3) | (intValue(r) << 2) | (intValue(x) << 1) | intValue(b));
}
}
}
void _emitRexRM(boolean w, int opReg, Operand rm) {
_emitRexRM(intValue(w), opReg, rm);
}
void _emitModM(int opReg, Mem mem, int immSize) {
assert (mem.op() == OP_MEM);
int baseReg = mem.base() & 0x7;
int indexReg = mem.index() & 0x7;
long disp = mem.displacement();
int shift = mem.shift();
// [base + displacemnt]
if (mem.hasBase() && !mem.hasIndex()) {
// ESP/RSP/R12 == 4
if (baseReg == 4) {
int mod = 0;
if (disp != 0) {
mod = isInt8(disp) ? 1 : 2;
}
_emitMod(mod, opReg, 4);
_emitSib(0, 4, 4);
if (disp != 0) {
if (isInt8(disp)) {
_emitByte((byte) disp);
} else {
_emitInt32((int) disp);
}
}
} // EBP/RBP/R13 == 5
else if (baseReg != 5 && disp == 0) {
_emitMod(0, opReg, baseReg);
} else if (isInt8(disp)) {
_emitMod(1, opReg, baseReg);
_emitByte((byte) disp);
} else {
_emitMod(2, opReg, baseReg);
_emitInt32((int) disp);
}
}
// [base + index * scale + displacemnt]
else if (mem.hasBase() && mem.hasIndex()) {
// ASMJIT_ASSERT(indexReg != RID_ESP);
// EBP/RBP/R13 == 5
if (baseReg != 5 && disp == 0) {
_emitMod(0, opReg, 4);
_emitSib(shift, indexReg, baseReg);
} else if (isInt8(disp)) {
_emitMod(1, opReg, 4);
_emitSib(shift, indexReg, baseReg);
_emitByte((byte) disp);
} else {
_emitMod(2, opReg, 4);
_emitSib(shift, indexReg, baseReg);
_emitInt32((int) disp);
}
}
// Address | 32-bit mode | 64-bit mode
// ------------------------------+-------------+---------------
// [displacement] | ABSOLUTE | RELATIVE (RIP)
// [index * scale + displacemnt] | ABSOLUTE | ABSOLUTE (ZERO EXTENDED)
else {
// In 32 bit mode is used absolute addressing model.
// In 64 bit mode is used relative addressing model together with absolute
// addressing one. Main problem is that if instruction contains SIB then
// relative addressing (RIP) is not possible.
if (!is64()) {
if (mem.hasIndex()) {
// ASMJIT_ASSERT(mem.index() != 4); // ESP/RSP == 4
_emitMod(0, opReg, 4);
_emitSib(shift, indexReg, 5);
} else {
_emitMod(0, opReg, 5);
}
// X86 uses absolute addressing model, all relative addresses will be
// relocated to absolute ones.
if (mem.hasLabel()) {
Label label = mem.label();
int relocId = _relocData.size();
long destination = disp;
if (label.isBound()) {
destination += label.position();
// Dummy DWORD
_emitInt32(0);
} else {
_emitDisplacement(label, -4 - immSize, 4).relocId = relocId;
}
// Relative addressing will be relocated to absolute address.
RelocData rd = new RelocData(RelocData.Type.RELATIVE_TO_ABSOLUTE, 4, offset(), destination);
_relocData.add(rd);
} else {
// Absolute address
_emitInt32((int) (mem.target() + disp));
}
} else {
// X64 uses relative addressing model
if (mem.hasLabel()) {
Label label = mem.label();
if (mem.hasIndex()) {
// Indexing is not possible
throw new IllegalArgumentException("illegal addressing");
}
// Relative address (RIP +/- displacement)
_emitMod(0, opReg, 5);
disp -= (4 + immSize);
if (label.isBound()) {
disp += offset() - label.position();
_emitInt32((int) disp);
} else {
_emitDisplacement(label, disp, 4);
}
} else {
// Absolute address (truncated to 32 bits), this kind of address requires
// SIB byte (4)
_emitMod(0, opReg, 4);
if (mem.hasIndex()) {
// ASMJIT_ASSERT(mem.index() != 4); // ESP/RSP == 4
_emitSib(shift, indexReg, 5);
} else {
_emitSib(0, 4, 5);
}
// truncate to 32 bits
long target = mem.target() + disp;
if (target > 0xFFFFFFFFL) {
_logger.log("; Warning: Absolute address truncated to 32 bits\n");
}
_emitInt32((int) target);
}
}
}
}
void _emitX86Inl(int opCode, boolean i16bit, boolean rexw, int reg) {
_emitX86Inl(opCode, i16bit, intValue(rexw), reg);
}
void _emitX86Inl(int opCode, boolean i16bit, int rexw, int reg) {
// 16 bit prefix
if (i16bit) {
_emitByte(0x66);
}
// instruction prefix
if ((opCode & 0xFF000000) != 0) {
_emitByte(((opCode & 0xFF000000) >> 24));
}
// rex prefix
if (is64()) {
_emitRexR(rexw, 0, reg);
}
// instruction opcodes
if ((opCode & 0x00FF0000) != 0) {
_emitByte(((opCode & 0x00FF0000) >> 16));
}
if ((opCode & 0x0000FF00) != 0) {
_emitByte(((opCode & 0x0000FF00) >> 8));
}
_emitByte((opCode & 0x000000FF) + (reg & 0x7));
}
void _emitModRM(int opReg, Operand op, int immSize) {
assert (op.op() == OP_REG || op.op() == OP_MEM);
if (op.op() == OP_REG) {
_emitModR(opReg, ((BaseReg) op).code());
} else {
_emitModM(opReg, (Mem) op, immSize);
}
}
/** Emit MODR/M byte. */
void _emitMod(int m, int o, int r) {
_emitByte((byte) (((m & 0x03) << 6) | ((o & 0x07) << 3) | (r & 0x07)));
}
/** Emit SIB byte. */
void _emitSib(int s, int i, int b) {
_emitByte((byte) (((s & 0x03) << 6) | ((i & 0x07) << 3) | (b & 0x07)));
}
/** Emit Register / Register - calls _emitMod(3, opReg, r) */
void _emitModR(int opReg, int r) {
_emitMod(3, opReg, r);
}
/** Emit Register / Register - calls _emitMod(3, opReg, r.code()) */
void _emitModR(int opReg, BaseReg r) {
_emitMod(3, opReg, r.code());
}
void _emitX86RM(int opCode, boolean i16bit, boolean rexw, int o, Operand op, int immSize) {
_emitX86RM(opCode, i16bit, intValue(rexw), o, op, immSize);
}
void _emitX86RM(int opCode, boolean i16bit, int rexw, int o, Operand op, int immSize) {
// 16 bit prefix
if (i16bit) {
_emitByte(0x66);
}
// segment prefix
_emitSegmentPrefix(op);
// instruction prefix
if ((opCode & 0xFF000000) != 0) {
_emitByte(((opCode & 0xFF000000) >> 24));
}
// rex prefix
if (is64()) {
_emitRexRM(rexw, o, op);
}
// instruction opcodes
if ((opCode & 0x00FF0000) != 0) {
_emitByte((byte) ((opCode & 0x00FF0000) >> 16));
}
if ((opCode & 0x0000FF00) != 0) {
_emitByte((byte) ((opCode & 0x0000FF00) >> 8));
}
_emitByte((byte) (opCode & 0x000000FF));
// ModR/M
_emitModRM(o, op, immSize);
}
void _emitX86(INST_CODE code, Operand o1, Operand o2, Operand o3) {
InstructionDescription id = InstructionDescription.find(code);
switch (id.group) {
case I_EMIT:
{
_emitOpCode(id.opCode1);
return;
}
case I_ALU:
{
int opCode = id.opCode1;
int opReg = id.opCodeR;
// Mem <- Reg
if (o1.isMem() && o2.isReg())
{
_emitX86RM(opCode + intValue(!o2.isRegType(REG_GPB)),
o2.isRegType(REG_GPW),
o2.isRegType(REG_GPQ),
((Register) o2).code(),
o1,
0);
return;
}
// Reg <- Reg|Mem
if (o1.isReg() && o2.isRegMem())
{
_emitX86RM(opCode + 2 + intValue(!o1.isRegType(REG_GPB)),
o1.isRegType(REG_GPW),
o1.isRegType(REG_GPQ),
((Register) o1).code(),
o2,
0);
return;
}
// AL, AX, EAX, RAX register shortcuts
if (o1.isRegIndex(0) && o2.isImm())
{
if (o1.isRegType(REG_GPW))
_emitByte(0x66); // 16 bit
else if (o1.isRegType(REG_GPQ))
_emitByte(0x48); // REX.W
_emitByte((opReg << 3) | (0x04 + intValue(!o1.isRegType(REG_GPB))));
_emitImmediate(
(Immediate) o2, o1.size() <= 4 ? o1.size() : 4);
return;
}
if (o1.isRegMem() && o2.isImm())
{
final Immediate imm = (Immediate) o2;
int immSize = Util.isInt8(imm.value()) ? 1 : (o1.size() <= 4 ? o1.size() : 4);
_emitX86RM(id.opCode2 + (o1.size() != 1 ? (immSize != 1 ? 1 : 3) : 0),
o1.size() == 2,
o1.size() == 8,
opReg, o1,
immSize);
_emitImmediate(
(Immediate) o2,
immSize);
return;
}
break;
}
case I_BSWAP:
{
if (o1.isReg())
{
final Register dst = (Register) o1;
if (is64()) {
_emitRexR(dst.type() == REG_GPQ, 1, dst.code());
}
_emitByte(0x0F);
_emitModR(1, dst.code());
return;
}
break;
}
case I_BT:
{
if (o1.isRegMem() && o2.isReg())
{
final Operand dst = o1;
final Register src = (Register) o2;
_emitX86RM(id.opCode1,
src.isRegType(REG_GPW),
src.isRegType(REG_GPQ),
src.code(),
dst,
0);
return;
}
if (o1.isRegMem() && o2.isImm())
{
final Operand dst = o1;
final Immediate src = (Immediate) o2;
_emitX86RM(id.opCode2,
src.size() == 2,
src.size() == 8,
id.opCodeR,
dst,
1);
_emitImmediate(src, 1);
return;
}
break;
}
case I_CALL:
{
if (o1.isRegMem(is64() ? REG_GPQ : REG_GPD))
{
final Operand dst = o1;
_emitX86RM(0xFF,
false,
false, 2, dst,
0);
return;
}
if (o1.isImm())
{
final Immediate imm = (Immediate) o1;
_emitByte(0xE8);
_emitJmpOrCallReloc(I_CALL, imm.value());
return;
}
if (o1.isLabel())
{
Label label = (Label) o1;
if (label.isBound())
{
final int rel32_size = 5;
final int offs = label.position() - offset();
assert(offs <= 0);
_emitByte(0xE8);
_emitInt32((int)(offs - rel32_size));
}
else
{
_emitByte(0xE8);
_emitDisplacement(label, -4, 4);
}
return;
}
break;
}
case I_CRC32:
{
if (o1.isReg() && o2.isRegMem())
{
final Register dst = (Register) o1;
final Operand src = o2;
assert(dst.type() == REG_GPD || dst.type() == REG_GPQ);
_emitX86RM(id.opCode1 + intValue(src.size() != 1),
src.size() == 2,
dst.type() == 8, dst.code(), src,
0);
return;
}
break;
}
case I_ENTER:
{
if (o1.isImm() && o2.isImm())
{
_emitByte(0xC8);
_emitImmediate((Immediate) o1, 2);
_emitImmediate((Immediate) o2, 1);
}
break;
}
case I_IMUL:
{
// 1 operand
if (o1.isRegMem() && o2.isNone() && o3.isNone())
{
final Operand src = o1;
_emitX86RM(0xF6 + intValue(src.size() != 1),
src.size() == 2,
src.size() == 8, 5, src,
0);
return;
}
// 2 operands
else if (o1.isReg() && !o2.isNone() && o3.isNone())
{
final Register dst = (Register) o1;
assert(!dst.isRegType(REG_GPW));
if (o2.isRegMem())
{
final Operand src = o2;
_emitX86RM(0x0FAF,
dst.isRegType(REG_GPW),
dst.isRegType(REG_GPQ), dst.code(), src,
0);
return;
}
else if (o2.isImm())
{
final Immediate imm = (Immediate) o2;
if (isInt8(imm.value()) && imm.relocMode() == RELOC_NONE)
{
_emitX86RM(0x6B,
dst.isRegType(REG_GPW),
dst.isRegType(REG_GPQ), dst.code(), dst,
1);
_emitImmediate(imm, 1);
}
else
{
int immSize = dst.isRegType(REG_GPW) ? 2 : 4;
_emitX86RM(0x69,
dst.isRegType(REG_GPW),
dst.isRegType(REG_GPQ), dst.code(), dst,
immSize);
_emitImmediate(imm, immSize);
}
return;
}
}
// 3 operands
else if (o1.isReg() && o2.isRegMem() && o3.isImm())
{
final Register dst = (Register) o1;
final Operand src = o2;
final Immediate imm = (Immediate) o3;
if (isInt8(imm.value()) && imm.relocMode() == RELOC_NONE)
{
_emitX86RM(0x6B,
dst.isRegType(REG_GPW),
dst.isRegType(REG_GPQ), dst.code(), src,
1);
_emitImmediate(imm, 1);
}
else
{
int immSize = dst.isRegType(REG_GPW) ? 2 : 4;
_emitX86RM(0x69,
dst.isRegType(REG_GPW),
dst.isRegType(REG_GPQ), dst.code(), src,
immSize);
_emitImmediate(imm, immSize);
}
return;
}
break;
}
case I_INC_DEC:
{
if (o1.isRegMem())
{
final Operand dst = o1;
// INC [r16|r32] in 64 bit mode is not encodable.
if (!is64() && dst.isReg() && (dst.isRegType(REG_GPW) || dst.isRegType(REG_GPD)))
{
_emitX86Inl(id.opCode1,
dst.isRegType(REG_GPW),
0, ((BaseReg) dst).code());
return;
}
_emitX86RM(id.opCode2 + intValue(dst.size() != 1),
dst.size() == 2,
dst.size() == 8, id.opCodeR, dst,
0);
return;
}
break;
}
case I_J:
{
if (o1.isLabel())
{
Label label = (Label) o1;
boolean isShortJump = (code.ordinal() >= INST_J_SHORT.ordinal() && code.ordinal() <= INST_JMP_SHORT.ordinal());
final HINT hint = o2.isImm() ? HINT.valueOf((int) ((Immediate) o2).value()) : HINT.HINT_NONE;
// Emit jump hint if configured for that.
if (hint == HINT_TAKEN || hint == HINT_NOT_TAKEN
&& (_properties & (1 << PROPERTY_X86_JCC_HINTS)) != 0)
{
_emitByte(hint.value());
}
if (label.isBound())
{
final int rel8_size = 2;
final int rel32_size = 6;
final int offs = label.position() - offset();
assert(offs <= 0);
if (isInt8(offs - rel8_size))
{
_emitByte(0x70 | (id.opCode1 & 0xff));
_emitByte((byte) (offs - rel8_size));
}
else
{
if (isShortJump && _logger != null)
{
_logger.log("; WARNING: Emitting long conditional jump, but short jump instruction forced!");
}
_emitByte(0x0F);
_emitByte(0x80 | (id.opCode1 & 0xff));
_emitInt32((int) (offs - rel32_size));
}
}
else
{
if (isShortJump)
{
_emitByte(0x70 | (id.opCode1 & 0xff));
_emitDisplacement(label, -1, 1);
}
else
{
_emitByte(0x0F);
_emitByte(0x80 | (id.opCode1 & 0xff));
_emitDisplacement(label, -4, 4);
}
}
return;
}
break;
}
case I_JMP:
{
if (o1.isRegMem())
{
final Operand dst = o1;
_emitX86RM(0xFF,
false,
false, 4, dst,
0);
return;
}
if (o1.isImm())
{
final Immediate imm = (Immediate) o1;
_emitByte(0xE9);
_emitJmpOrCallReloc(I_JMP, imm.value());
return;
}
if (o1.isLabel())
{
Label label = (Label) o1;
boolean isShortJump = (code == INST_JMP_SHORT);
if (label.isBound())
{
final int rel8_size = 2;
final int rel32_size = 5;
final int offs = label.position() - offset();
if (isInt8(offs - rel8_size))
{
_emitByte(0xEB);
_emitByte((byte) (offs - rel8_size));
}
else
{
if (isShortJump && _logger != null)
{
_logger.log("; WARNING: Emitting long jump, but short jump instruction forced!");
}
_emitByte(0xE9);
_emitInt32((int)(offs - rel32_size));
}
}
else
{
if (isShortJump)
{
_emitByte(0xEB);
_emitDisplacement(label, -1, 1);
}
else
{
_emitByte(0xE9);
_emitDisplacement(label, -4, 4);
}
}
return;
}
break;
}
case I_LEA:
{
if (o1.isReg() && o2.isMem())
{
final Register dst = (Register) o1;
final Mem src = (Mem) o2;
_emitX86RM(0x8D,
dst.isRegType(REG_GPW),
dst.isRegType(REG_GPQ), dst.code(), src,
0);
return;
}
break;
}
case I_M:
{
if (o1.isMem())
{
_emitX86RM(id.opCode1, false, (byte) id.opCode2, id.opCodeR, (Mem) o1, 0);
return;
}
break;
}
case I_MOV:
{
final Operand dst = o1;
final Operand src = o2;
switch (dst.op() << 4 | src.op())
{
// Reg <- Reg/Mem
case (OP_REG << 4) | OP_REG:
{
assert(src.isRegType(REG_GPB) || src.isRegType(REG_GPW) ||
src.isRegType(REG_GPD) || src.isRegType(REG_GPQ));
// ... fall through ...
}
case (OP_REG << 4) | OP_MEM:
{
assert(dst.isRegType(REG_GPB) || dst.isRegType(REG_GPW) ||
dst.isRegType(REG_GPD) || dst.isRegType(REG_GPQ));
_emitX86RM(0x0000008A + intValue(!dst.isRegType(REG_GPB)),
dst.isRegType(REG_GPW),
dst.isRegType(REG_GPQ),
((Register) dst).code(),
src,
0);
return;
}
// Reg <- Imm
case (OP_REG << 4) | OP_IMM:
{
final Immediate isrc = (Immediate) o2;
// in 64 bit mode immediate can be 8 byte long!
int immSize = dst.size();
// Optimize instruction size by using 32 bit immediate if value can
// fit to it
if (is64() && immSize == 8 && isInt32(isrc.value()) && isrc.relocMode() == RELOC_NONE)
{
_emitX86RM(0xC7,
dst.isRegType(REG_GPW),
dst.isRegType(REG_GPQ),
0,
dst,
0);
immSize = 4;
}
else
{
_emitX86Inl((dst.size() == 1 ? 0xB0 : 0xB8),
dst.isRegType(REG_GPW),
dst.isRegType(REG_GPQ),
((Register) dst).code());
}
_emitImmediate(isrc, immSize);
return;
}
// Mem <- Reg
case (OP_MEM << 4) | OP_REG:
{
assert(src.isRegType(REG_GPB) || src.isRegType(REG_GPW) ||
src.isRegType(REG_GPD) || src.isRegType(REG_GPQ));
_emitX86RM(0x88 + intValue(!src.isRegType(REG_GPB)),
src.isRegType(REG_GPW),
src.isRegType(REG_GPQ),
((Register) src).code(),
dst,
0);
return;
}
// Mem <- Imm
case (OP_MEM << 4) | OP_IMM:
{
int immSize = dst.size() <= 4 ? dst.size() : 4;
_emitX86RM(0xC6 + intValue(dst.size() != 1),
dst.size() == 2,
dst.size() == 8,
0,
dst,
immSize);
_emitImmediate((Immediate) src,
immSize);
return;
}
}
break;
}
case I_MOV_PTR:
{
if ((o1.isReg() && o2.isImm()) || (o1.isImm() && o2.isReg()))
{
boolean reverse = o1.op() == OP_REG;
int opCode = !reverse ? 0xA0 : 0xA2;
final Register reg = (Register)(!reverse ? o1 : o2);
final Immediate imm = (Immediate)(!reverse ? o2 : o1);
if (reg.index() != 0) throw new IllegalStateException("reg.index() != 0");
if (reg.isRegType(REG_GPW)) _emitByte(0x66);
if (is64()) {
_emitRexR(reg.size() == 8, 0, 0);
}
_emitByte(opCode + intValue(reg.size() != 1));
_emitImmediate(imm, is64() ? 8 : 4);
return;
}
break;
}
case I_MOVSX_MOVZX:
{
if (o1.isReg() && o2.isRegMem())
{
final Register dst = (Register)(o1);
final Operand src = (o2);
if (dst.isRegType(REG_GPB)) throw new IllegalArgumentException("not gpb");
if (src.size() != 1 && src.size() != 2) throw new IllegalArgumentException("src.size !=1 && src.size != 2");
if (src.size() == 2 && dst.isRegType(REG_GPW)) throw new IllegalArgumentException("not gpw");
_emitX86RM(id.opCode1 + intValue(src.size() != 1),
dst.isRegType(REG_GPW),
dst.isRegType(REG_GPQ),
dst.code(),
src,
0);
return;
}
break;
}
case I_MOVSXD:
{
if (!is64()) {
throw new IllegalStateException("illegal instruction");
}
if (o1.isReg() && o2.isRegMem())
{
final Register dst = (Register)(o1);
final Operand src = (o2);
_emitX86RM(0x00000063,
false,
1, dst.code(), src,
0);
return;
}
break;
}
case I_PUSH:
{
// This section is only for immediates, memory/register operands are handled in I_POP.
if (o1.isImm())
{
final Immediate imm = (Immediate)(o1);
if (isInt8(imm.value()) && imm.relocMode() == RELOC_NONE)
{
_emitByte(0x6A);
_emitImmediate(imm, 1);
}
else
{
_emitByte(0x68);
_emitImmediate(imm, 4);
}
return;
}
// ... goto I_POP ...
}
case I_POP:
{
if (o1.isReg())
{
assert(o1.isRegType(REG_GPW) || o1.isRegType(is64() ? REG_GPQ : REG_GPD));
_emitX86Inl(id.opCode1, o1.isRegType(REG_GPW), 0, ((Register) o1).code());
return;
}
if (o1.isMem())
{
_emitX86RM(id.opCode2, o1.size() == 2, 0, id.opCodeR, (o1), 0);
return;
}
break;
}
case I_R_RM:
{
if (o1.isReg() && o2.isRegMem())
{
final Register dst = (Register)(o1);
assert(dst.type() != REG_GPB);
final Operand src = (o2);
_emitX86RM(id.opCode1,
dst.type() == REG_GPW,
dst.type() == REG_GPQ, dst.code(), src,
0);
return;
}
break;
}
case I_RM_B:
{
if (o1.isRegMem())
{
final Operand op = (o1);
_emitX86RM(id.opCode1, false, false, 0, op, 0);
return;
}
break;
}
case I_RM:
{
if (o1.isRegMem())
{
final Operand op = (o1);
_emitX86RM(id.opCode1 + intValue(op.size() != 1),
op.size() == 2,
op.size() == 8, id.opCodeR, op,
0);
return;
}
break;
}
case I_RM_R:
{
if (o1.isRegMem() && o2.isReg())
{
final Operand dst = (o1);
final Register src = (Register)(o2);
_emitX86RM(id.opCode1 + intValue(src.type() != REG_GPB),
src.type() == REG_GPW,
src.type() == REG_GPQ, src.code(), dst,
0);
return;
}
break;
}
case I_RET:
{
if (o1.isNone())
{
_emitByte(0xC3);
return;
}
else if (o1.isImm())
{
final Immediate imm = (Immediate)(o1);
assert(isUInt16(imm.value()));
if (imm.value() == 0 && imm.relocMode() == RELOC_NONE)
{
_emitByte(0xC3);
}
else
{
_emitByte(0xC2);
_emitImmediate(imm, 2);
}
return;
}
break;
}
case I_ROT:
{
if (o1.isRegMem() && (o2.isRegCode(REG_CL) || o2.isImm()))
{
// generate opcode. For these operations is base 0xC0 or 0xD0.
boolean useImm8 = (o2.isImm() &&
(((Immediate) o2).value() != 1 ||
((Immediate) o2).relocMode() != RELOC_NONE));
int opCode = useImm8 ? 0xC0 : 0xD0;
// size and operand type modifies the opcode
if (o1.size() != 1) opCode |= 0x01;
if (o2.op() == OP_REG) opCode |= 0x02;
_emitX86RM(opCode,
o1.size() == 2,
o1.size() == 8,
id.opCodeR, (o1),
intValue(useImm8));
if (useImm8)
_emitImmediate((Immediate)(o2), 1);
return;
}
break;
}
case I_SHLD_SHRD:
{
if (o1.isRegMem() && o2.isReg() && (o3.isImm() || (o3.isReg() && o3.isRegCode(REG_CL))))
{
final Operand dst = (o1);
final Register src1 = (Register)(o2);
final Operand src2 = (o3);
assert(dst.size() == src1.size());
_emitX86RM(id.opCode1 + intValue(src2.isReg()),
src1.isRegType(REG_GPW),
src1.isRegType(REG_GPQ),
src1.code(), dst,
intValue(src2.isImm()));
if (src2.isImm())
_emitImmediate((Immediate)(src2), 1);
return;
}
break;
}
case I_TEST:
{
if (o1.isRegMem() && o2.isReg())
{
assert(o1.size() == o2.size());
_emitX86RM(0x84 + intValue(o2.size() != 1),
o2.size() == 2, o2.size() == 8,
((BaseReg) o2).code(),
(o1),
0);
return;
}
if (o1.isRegIndex(0) && o2.isImm())
{
int immSize = o1.size() <= 4 ? o1.size() : 4;
if (o1.size() == 2) _emitByte(0x66); // 16 bit
if (is64()) {
_emitRexRM(o1.size() == 8, 0, (o1));
}
_emitByte(0xA8 + intValue(o1.size() != 1));
_emitImmediate((Immediate)(o2), immSize);
return;
}
if (o1.isRegMem() && o2.isImm())
{
int immSize = o1.size() <= 4 ? o1.size() : 4;
if (o1.size() == 2) _emitByte(0x66); // 16 bit
_emitSegmentPrefix((o1)); // segment prefix
if (is64()) _emitRexRM(o1.size() == 8, 0, (o1));
_emitByte(0xF6 + intValue(o1.size() != 1));
_emitModRM(0, (o1), immSize);
_emitImmediate((Immediate)(o2), immSize);
return;
}
break;
}
case I_XCHG:
{
if (o1.isRegMem() && o2.isReg())
{
final Operand dst = (o1);
final Register src = (Register)(o2);
if (src.isRegType(REG_GPW)) _emitByte(0x66); // 16 bit
_emitSegmentPrefix(dst); // segment prefix
if (is64()) _emitRexRM(src.isRegType(REG_GPQ), src.code(), dst);
// Special opcode for index 0 registers (AX, EAX, RAX vs register)
if ((dst.op() == OP_REG && dst.size() > 1) &&
(((Register) dst).code() == 0 ||
((Register) src).code() == 0))
{
int index = ((Register) dst).code() | src.code();
_emitByte((byte) (0x90 + index));
return;
}
_emitByte(0x86 + intValue(!src.isRegType(REG_GPB)));
_emitModRM(src.code(), dst, 0);
return;
}
break;
}
case I_MOVBE:
{
if (o1.isReg() && o2.isMem())
{
_emitX86RM(0x000F38F0,
o1.isRegType(REG_GPW),
o1.isRegType(REG_GPQ),
((Register) o1).code(),
(Mem)(o2),
0);
return;
}
if (o1.isMem() && o2.isReg())
{
_emitX86RM(0x000F38F1,
o2.isRegType(REG_GPW),
o2.isRegType(REG_GPQ),
((Register) o2).code(),
(Mem)(o1),
0);
return;
}
break;
}
case I_X87_FPU:
{
if (o1.isRegType(REG_X87))
{
int i1 = ((X87Register) o1).index();
int i2 = 0;
if (code != INST_FCOM && code != INST_FCOMP)
{
if (!o2.isRegType(REG_X87)) throw new IllegalArgumentException("not x87 reg");
i2 = ((X87Register) o2).index();
}
else if (i1 != 0 && i2 != 0)
{
throw new IllegalArgumentException("illegal instruction");
}
_emitByte(i1 == 0
? ((id.opCode1 & 0xFF000000) >> 24)
: ((id.opCode1 & 0x00FF0000) >> 16));
_emitByte(i1 == 0
? ((id.opCode1 & 0x0000FF00) >> 8) + i2
: ((id.opCode1 & 0x000000FF) ) + i1);
return;
}
if (o1.isMem() && (o1.size() == 4 || o1.size() == 8) && o2.isNone())
{
final Mem m = (Mem)(o1);
// segment prefix
_emitSegmentPrefix(m);
_emitByte(o1.size() == 4
? ((id.opCode1 & 0xFF000000) >> 24)
: ((id.opCode1 & 0x00FF0000) >> 16));
_emitModM(id.opCodeR, m, 0);
return;
}
break;
}
case I_X87_STI:
{
if (o1.isRegType(REG_X87))
{
int i = ((X87Register) o1).index();
_emitByte(((id.opCode1 & 0x0000FF00) >> 8));
_emitByte(((id.opCode1 & 0x000000FF) + i));
return;
}
break;
}
case I_X87_FSTSW:
{
if (o1.isReg() &&
((BaseReg) o1).type() <= REG_GPQ &&
((BaseReg) o1).index() == 0)
{
_emitOpCode(id.opCode2);
return;
}
if (o1.isMem())
{
_emitX86RM(id.opCode1, false, 0, id.opCodeR, (Mem)(o1), 0);
return;
}
break;
}
case I_X87_MEM_STI:
{
if (o1.isRegType(REG_X87))
{
_emitByte(((id.opCode2 & 0xFF000000) >> 24));
_emitByte(((id.opCode2 & 0x00FF0000) >> 16) +
((X87Register) o1).index());
return;
}
// ... fall through to I_X87_MEM ...
}
case I_X87_MEM:
{
if (!o1.isMem()) throw new IllegalArgumentException("not x87 mem");
final Mem m = (Mem)(o1);
int opCode = 0x00, mod = 0;
if (o1.size() == 2 && (id.o1Flags & O_FM_2) != 0)
{
opCode = ((id.opCode1 & 0xFF000000) >> 24);
mod = id.opCodeR;
}
if (o1.size() == 4 && (id.o1Flags & O_FM_4) != 0)
{
opCode = ((id.opCode1 & 0x00FF0000) >> 16);
mod = id.opCodeR;
}
if (o1.size() == 8 && (id.o1Flags & O_FM_8) != 0)
{
opCode = ((id.opCode1 & 0x0000FF00) >> 8);
mod = ((id.opCode1 & 0x000000FF) );
}
if (opCode != 0)
{
_emitSegmentPrefix(m);
_emitByte(opCode);
_emitModM(mod, m, 0);
return;
}
break;
}
case I_MMU_MOV:
{
assert(id.o1Flags != 0);
assert(id.o2Flags != 0);
// Check parameters (X)MM|GP32_64 <- (X)MM|GP32_64|Mem|Imm
if ((o1.isMem() && (id.o1Flags & O_MEM) == 0) ||
(o1.isRegType(REG_MM ) && (id.o1Flags & O_MM ) == 0) ||
(o1.isRegType(REG_XMM) && (id.o1Flags & O_XMM) == 0) ||
(o1.isRegType(REG_GPD) && (id.o1Flags & O_G32) == 0) ||
(o1.isRegType(REG_GPQ) && (id.o1Flags & O_G64) == 0) ||
(o2.isRegType(REG_MM ) && (id.o2Flags & O_MM ) == 0) ||
(o2.isRegType(REG_XMM) && (id.o2Flags & O_XMM) == 0) ||
(o2.isRegType(REG_GPD) && (id.o2Flags & O_G32) == 0) ||
(o2.isRegType(REG_GPQ) && (id.o2Flags & O_G64) == 0) ||
(o2.isMem() && (id.o2Flags & O_MEM) == 0) )
{
throw new IllegalArgumentException("illegal instruction");
}
// Illegal
if (o1.isMem() && o2.isMem()) throw new IllegalArgumentException("illegal instruction");
int rexw = ((id.o1Flags|id.o2Flags) & O_NOREX) != 0
? 0
: intValue(o1.isRegType(REG_GPQ) || o1.isRegType(REG_GPQ));
// (X)MM|Reg <- (X)MM|Reg
if (o1.isReg() && o2.isReg())
{
_emitMmu(id.opCode1, rexw,
((BaseReg) o1).code(),
(BaseReg)(o2),
0);
return;
}
// (X)MM|Reg <- Mem
if (o1.isReg() && o2.isMem())
{
_emitMmu(id.opCode1, rexw,
((BaseReg) o1).code(),
(Mem)(o2),
0);
return;
}
// Mem <- (X)MM|Reg
if (o1.isMem() && o2.isReg())
{
_emitMmu(id.opCode2, rexw,
((BaseReg) o2).code(),
(Mem)(o1),
0);
return;
}
break;
}
case I_MMU_MOVD:
{
if ((o1.isRegType(REG_MM) || o1.isRegType(REG_XMM)) && (o2.isRegType(REG_GPD) || o2.isMem()))
{
_emitMmu(o1.isRegType(REG_XMM) ? 0x66000F6E : 0x00000F6E, 0,
((BaseReg) o1).code(),
(o2),
0);
return;
}
if ((o1.isRegType(REG_GPD) || o1.isMem()) && (o2.isRegType(REG_MM) || o2.isRegType(REG_XMM)))
{
_emitMmu(o2.isRegType(REG_XMM) ? 0x66000F7E : 0x00000F7E, 0,
((BaseReg) o2).code(),
(o1),
0);
return;
}
break;
}
case I_MMU_MOVQ:
{
if (o1.isRegType(REG_MM) && o2.isRegType(REG_MM))
{
_emitMmu(0x00000F6F, 0,
((MMRegister) o1).code(),
(MMRegister)(o2),
0);
return;
}
if (o1.isRegType(REG_XMM) && o2.isRegType(REG_XMM))
{
_emitMmu(0xF3000F7E, 0,
((XMMRegister) o1).code(),
(XMMRegister)(o2),
0);
return;
}
// Convenience - movdq2q
if (o1.isRegType(REG_MM) && o2.isRegType(REG_XMM))
{
_emitMmu(0xF2000FD6, 0,
((MMRegister) o1).code(),
(XMMRegister)(o2),
0);
return;
}
// Convenience - movq2dq
if (o1.isRegType(REG_XMM) && o2.isRegType(REG_MM))
{
_emitMmu(0xF3000FD6, 0,
((XMMRegister) o1).code(),
(MMRegister)(o2),
0);
return;
}
if (o1.isRegType(REG_MM) && o2.isMem())
{
_emitMmu(0x00000F6F, 0,
((MMRegister) o1).code(),
(Mem)(o2),
0);
return;
}
if (o1.isRegType(REG_XMM) && o2.isMem())
{
_emitMmu(0xF3000F7E, 0,
((XMMRegister) o1).code(),
(Mem)(o2),
0);
return;
}
if (o1.isMem() && o2.isRegType(REG_MM))
{
_emitMmu(0x00000F7F, 0,
((MMRegister) o2).code(),
(Mem)(o1),
0);
return;
}
if (o1.isMem() && o2.isRegType(REG_XMM))
{
_emitMmu(0x66000FD6, 0,
((XMMRegister) o2).code(),
(Mem)(o1),
0);
return;
}
if (is64()) {
if ((o1.isRegType(REG_MM) || o1.isRegType(REG_XMM)) && (o2.isRegType(REG_GPQ) || o2.isMem()))
{
_emitMmu(o1.isRegType(REG_XMM) ? 0x66000F6E : 0x00000F6E, 1,
((BaseReg) o1).code(),
(o2),
0);
return;
}
if ((o1.isRegType(REG_GPQ) || o1.isMem()) && (o2.isRegType(REG_MM) || o2.isRegType(REG_XMM)))
{
_emitMmu(o2.isRegType(REG_XMM) ? 0x66000F7E : 0x00000F7E, 1,
((BaseReg) o2).code(),
(o1),
0);
return;
}
}
break;
}
case I_MMU_PREFETCH:
{
if (o1.isMem() && o2.isImm())
{
final Mem mem = (Mem)(o1);
final Immediate hint = (Immediate)(o2);
_emitMmu(0x00000F18, 0, (int) hint.value(), mem, 0);
return;
}
break;
}
case I_MMU_PEXTR:
{
if (!(o1.isRegMem() &&
(o2.isRegType(REG_XMM) || (code == INST_PEXTRW && o2.isRegType(REG_MM))) &&
o3.isImm()))
{
throw new IllegalStateException("illegal instruction");
}
int opCode = id.opCode1;
boolean isGpdGpq = o1.isRegType(REG_GPD) || o1.isRegType(REG_GPQ);
if (code == INST_PEXTRB && (o1.size() != 0 && o1.size() != 1) && !isGpdGpq) throw new IllegalStateException("illegal instruction");
if (code == INST_PEXTRW && (o1.size() != 0 && o1.size() != 2) && !isGpdGpq) throw new IllegalStateException("illegal instruction");
if (code == INST_PEXTRD && (o1.size() != 0 && o1.size() != 4) && !isGpdGpq) throw new IllegalStateException("illegal instruction");
if (code == INST_PEXTRQ && (o1.size() != 0 && o1.size() != 8) && !isGpdGpq) throw new IllegalStateException("illegal instruction");
if (o2.isRegType(REG_XMM)) opCode |= 0x66000000;
if (o1.isReg())
{
_emitMmu(opCode, id.opCodeR | intValue(o1.isRegType(REG_GPQ)),
((BaseReg) o2).code(),
(BaseReg)(o1), 1);
_emitImmediate(
(Immediate)(o3), 1);
return;
}
if (o1.isMem())
{
_emitMmu(opCode, id.opCodeR,
((BaseReg) o2).code(),
(Mem)(o1), 1);
_emitImmediate(
(Immediate)(o3), 1);
return;
}
break;
}
case I_MMU_RMI:
{
assert(id.o1Flags != 0);
assert(id.o2Flags != 0);
// Check parameters (X)MM|GP32_64 <- (X)MM|GP32_64|Mem|Imm
if (!o1.isReg() ||
(o1.isRegType(REG_MM ) && (id.o1Flags & O_MM ) == 0) ||
(o1.isRegType(REG_XMM) && (id.o1Flags & O_XMM) == 0) ||
(o1.isRegType(REG_GPD) && (id.o1Flags & O_G32) == 0) ||
(o1.isRegType(REG_GPQ) && (id.o1Flags & O_G64) == 0) ||
(o2.isRegType(REG_MM ) && (id.o2Flags & O_MM ) == 0) ||
(o2.isRegType(REG_XMM) && (id.o2Flags & O_XMM) == 0) ||
(o2.isRegType(REG_GPD) && (id.o2Flags & O_G32) == 0) ||
(o2.isRegType(REG_GPQ) && (id.o2Flags & O_G64) == 0) ||
(o2.isMem() && (id.o2Flags & O_MEM) == 0) ||
(o2.isImm() && (id.o2Flags & O_IMM) == 0))
{
throw new IllegalStateException("illegal instruction");
}
int prefix =
((id.o1Flags & O_MM_XMM) == O_MM_XMM && o1.isRegType(REG_XMM)) ||
((id.o2Flags & O_MM_XMM) == O_MM_XMM && o2.isRegType(REG_XMM))
? 0x66000000
: 0x00000000;
int rexw = ((id.o1Flags|id.o2Flags) & O_NOREX) != 0
? 0
: intValue(o1.isRegType(REG_GPQ) || o1.isRegType(REG_GPQ));
// (X)MM <- (X)MM (opcode1)
if (o2.isReg())
{
if ((id.o2Flags & (O_MM_XMM | O_G32_64)) == 0) throw new IllegalStateException("illegal instruction");
_emitMmu(id.opCode1 | prefix, rexw,
((BaseReg) o1).code(),
(BaseReg)(o2), 0);
return;
}
// (X)MM <- Mem (opcode1)
if (o2.isMem())
{
if ((id.o2Flags & O_MEM) == 0) throw new IllegalStateException("illegal instruction");
_emitMmu(id.opCode1 | prefix, rexw,
((BaseReg) o1).code(),
(Mem)(o2), 0);
return;
}
// (X)MM <- Imm (opcode2+opcodeR)
if (o2.isImm())
{
if ((id.o2Flags & O_IMM) == 0) throw new IllegalStateException("illegal instruction");
_emitMmu(id.opCode2 | prefix, rexw,
id.opCodeR,
(BaseReg)(o1), 1);
_emitImmediate(
(Immediate)(o2), 1);
return;
}
break;
}
case I_MMU_RM_IMM8:
{
assert(id.o1Flags != 0);
assert(id.o2Flags != 0);
// Check parameters (X)MM|GP32_64 <- (X)MM|GP32_64|Mem|Imm
if (!o1.isReg() ||
(o1.isRegType(REG_MM ) && (id.o1Flags & O_MM ) == 0) ||
(o1.isRegType(REG_XMM) && (id.o1Flags & O_XMM) == 0) ||
(o1.isRegType(REG_GPD) && (id.o1Flags & O_G32) == 0) ||
(o1.isRegType(REG_GPQ) && (id.o1Flags & O_G64) == 0) ||
(o2.isRegType(REG_MM ) && (id.o2Flags & O_MM ) == 0) ||
(o2.isRegType(REG_XMM) && (id.o2Flags & O_XMM) == 0) ||
(o2.isRegType(REG_GPD) && (id.o2Flags & O_G32) == 0) ||
(o2.isRegType(REG_GPQ) && (id.o2Flags & O_G64) == 0) ||
(o2.isMem() && (id.o2Flags & O_MEM) == 0) ||
!o3.isImm())
{
throw new IllegalStateException("illegal instruction");
}
int prefix =
((id.o1Flags & O_MM_XMM) == O_MM_XMM && o1.isRegType(REG_XMM)) ||
((id.o2Flags & O_MM_XMM) == O_MM_XMM && o2.isRegType(REG_XMM))
? 0x66000000
: 0x00000000;
int rexw = ((id.o1Flags|id.o2Flags) & O_NOREX) != 0
? 0
: intValue(o1.isRegType(REG_GPQ) || o1.isRegType(REG_GPQ));
// (X)MM <- (X)MM (opcode1)
if (o2.isReg())
{
if ((id.o2Flags & (O_MM_XMM | O_G32_64)) == 0) throw new IllegalStateException("illegal instruction");
_emitMmu(id.opCode1 | prefix, rexw,
((BaseReg) o1).code(),
(BaseReg)(o2), 1);
_emitImmediate((Immediate)(o3), 1);
return;
}
// (X)MM <- Mem (opcode1)
if (o2.isMem())
{
if ((id.o2Flags & O_MEM) == 0) throw new IllegalStateException("illegal instruction");
_emitMmu(id.opCode1 | prefix, rexw,
((BaseReg) o1).code(),
(Mem)(o2), 1);
_emitImmediate((Immediate)(o3), 1);
return;
}
break;
}
case I_MMU_RM_3DNOW:
{
if (o1.isRegType(REG_MM) && (o2.isRegType(REG_MM) || o2.isMem()))
{
_emitMmu(id.opCode1, 0,
((BaseReg) o1).code(),
(Mem)(o2), 1);
_emitByte(id.opCode2);
return;
}
break;
}
}
}
void _emitFpu(int opCode) {
_emitOpCode(opCode);
}
void _emitFpuSTI(int opCode, int sti) {
// illegal stack offset
assert (0 <= sti && sti < 8);
_emitOpCode(opCode + sti);
}
void _emitFpuMEM(int opCode, int opReg, Mem mem) {
// segment prefix
_emitSegmentPrefix(mem);
// instruction prefix
if ((opCode & 0xFF000000) != 0) {
_emitByte(((opCode & 0xFF000000) >> 24));
}
// rex prefix
if (is64()) {
_emitRexRM(0, opReg, mem);
}
// instruction opcodes
if ((opCode & 0x00FF0000) != 0) {
_emitByte(((opCode & 0x00FF0000) >> 16));
}
if ((opCode & 0x0000FF00) != 0) {
_emitByte(((opCode & 0x0000FF00) >> 8));
}
_emitByte(((opCode & 0x000000FF)));
_emitModM(opReg, mem, 0);
}
void _emitMmu(int opCode, int rexw, int opReg,
Operand src, int immSize) {
// Segment prefix.
_emitSegmentPrefix(src);
// Instruction prefix.
if ((opCode & 0xFF000000) != 0) {
_emitByte(((opCode & 0xFF000000) >> 24));
}
// Rex prefix
if (is64()) {
_emitRexRM(rexw, opReg, src);
}
// Instruction opcodes.
if ((opCode & 0x00FF0000) != 0) {
_emitByte(((opCode & 0x00FF0000) >> 16));
}
// No checking, MMX/SSE instructions have always two opcodes or more.
_emitByte(((opCode & 0x0000FF00) >> 8));
_emitByte(((opCode & 0x000000FF)));
if (src.isReg()) {
_emitModR(opReg, ((BaseReg) src).code());
} else {
_emitModM(opReg, (Mem) src, immSize);
}
}
LinkData _emitDisplacement(Label label, long inlinedDisplacement, int size) {
assert (!label.isBound());
assert (size == 1 || size == 4);
// Chain with label.
LinkData link = new LinkData(offset(), inlinedDisplacement, -1);
label.link(link);
// Emit dummy DWORD.
if (size == 1) {
_emitByte(0x01);
} else // if (size == 4)
{
_emitDWord(0x04040404);
}
return link;
}
void _emitJmpOrCallReloc(InstructionGroup instruction, long target) {
if (is64()) {
// If we are compiling in 64-bit mode, we can use trampoline if relative jump
// is not possible.
_trampolineSize += TrampolineWriter.TRAMPOLINE_SIZE;
}
RelocData rd = new RelocData(RelocData.Type.ABSOLUTE_TO_RELATIVE_TRAMPOLINE, 4, offset(), target);
_relocData.add(rd);
// Emit dummy 32-bit integer (will be overwritten by relocCode()).
_emitInt32(0);
}
public void relocCode(ByteBuffer buffer, long address) {
// Copy code to virtual memory (this is a given _dst pointer).
int csize = codeSize();
// We are copying exactly size of generated code. Extra code for trampolines
// is generated on-the-fly by relocator (this code not exists at now).
_buffer.copyTo(buffer);
// Relocate recorded locations.
for (RelocData r : _relocData) {
long val;
// Whether to use trampoline, can be only used if relocation type is
// ABSOLUTE_TO_RELATIVE_TRAMPOLINE.
boolean useTrampoline = false;
// Be sure that reloc data structure is correct.
assert ((r.offset + r.size) <= csize);
switch (r.type) {
case ABSOLUTE_TO_ABSOLUTE:
val = r.destination;
break;
case RELATIVE_TO_ABSOLUTE:
val = address + r.destination;
break;
case ABSOLUTE_TO_RELATIVE:
case ABSOLUTE_TO_RELATIVE_TRAMPOLINE:
val = r.destination - (address + r.offset + 4);
if (is64() && r.type == RelocData.Type.ABSOLUTE_TO_RELATIVE_TRAMPOLINE && !isInt32(val)) {
val = (long) buffer.position() - (r.offset + 4);
useTrampoline = true;
}
break;
default:
throw new IllegalStateException("invalid relocation type");
}
switch (r.size) {
case 4:
buffer.putInt(r.offset, (int) val);
break;
case 8:
buffer.putLong(r.offset, val);
break;
default:
throw new IllegalStateException("invalid relocation size");
}
if (is64() && useTrampoline) {
if (_logger != null) {
_logger.log(String.format("; Trampoline from %x -> %x\n", address + r.offset, r.destination));
}
TrampolineWriter.writeTrampoline(buffer, r.destination);
}
}
}
// NOPs optimized for Intel:
// Intel 64 and IA-32 Architectures Software Developer's Manual
// - Volume 2B
// - Instruction Set Reference N-Z
// - NOP
// NOPs optimized for AMD:
// Software Optimization Guide for AMD Family 10h Processors (Quad-Core)
// - 4.13 - Code Padding with Operand-Size Override and Multibyte NOP
// Intel and AMD
private static final int nop1[] = { 0x90 };
private static final int nop2[] = { 0x66, 0x90 };
private static final int nop3[] = { 0x0F, 0x1F, 0x00 };
private static final int nop4[] = { 0x0F, 0x1F, 0x40, 0x00 };
private static final int nop5[] = { 0x0F, 0x1F, 0x44, 0x00, 0x00 };
private static final int nop6[] = { 0x66, 0x0F, 0x1F, 0x44, 0x00, 0x00 };
private static final int nop7[] = { 0x0F, 0x1F, 0x80, 0x00, 0x00, 0x00, 0x00 };
private static final int nop8[] = { 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 };
private static final int nop9[] = { 0x66, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 };
// AMD
private static final int nop10[] = { 0x66, 0x66, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 };
private static final int nop11[] = { 0x66, 0x66, 0x66, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 };
public void align(long m) {
if (_logger != null) _logger.logAlign(m);
if (m < 1) return;
if (m > 64) {
assert (m <= 64);
return;
}
int i = (int) (m - (offset() % m));
if (i == m) return;
if ((_properties & (1 << PROPERTY_OPTIMIZE_ALIGN)) != 0) {
int n;
if (cpuInfo.vendor == CpuInfo.Vendor.INTEL &&
((cpuInfo.family & 0x0F) == 6 ||
(cpuInfo.family & 0x0F) == 15)) {
do {
int[] p;
switch (i) {
case 1: p = nop1; n = 1; break;
case 2: p = nop2; n = 2; break;
case 3: p = nop3; n = 3; break;
case 4: p = nop4; n = 4; break;
case 5: p = nop5; n = 5; break;
case 6: p = nop6; n = 6; break;
case 7: p = nop7; n = 7; break;
case 8: p = nop8; n = 8; break;
default: p = nop9; n = 9; break;
}
i -= n;
for (int idx = 0; n > 0; ++idx, --n) {
_emitByte(p[idx]);
}
} while (i > 0);
return;
}
if (cpuInfo.vendor == CpuInfo.Vendor.AMD
&& cpuInfo.family >= 0x0F) {
do {
int[] p;
switch (i) {
case 1: p = nop1 ; n = 1; break;
case 2: p = nop2 ; n = 2; break;
case 3: p = nop3 ; n = 3; break;
case 4: p = nop4 ; n = 4; break;
case 5: p = nop5 ; n = 5; break;
case 6: p = nop6 ; n = 6; break;
case 7: p = nop7 ; n = 7; break;
case 8: p = nop8 ; n = 8; break;
case 9: p = nop9 ; n = 9; break;
case 10: p = nop10; n = 10; break;
default: p = nop11; n = 11; break;
}
i -= n;
for (int idx = 0; n > 0; ++idx, --n) {
_emitByte(p[idx]);
}
} while (i > 0);
return;
}
if (!is64()) {
// legacy NOPs, 0x90 with 0x66 prefix.
do {
switch (i) {
default: _emitByte(0x66); i--;
case 3: _emitByte(0x66); i--;
case 2: _emitByte(0x66); i--;
case 1: _emitByte(0x90); i--;
}
} while (i > 0);
}
}
// legacy NOPs, only 0x90
// In 64-bit mode, we can't use 0x66 prefix
while (i-- > 0) {
_emitByte(0x90);
}
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/Register.java 0000644 0001750 0001750 00000004773 11425031554 022242 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
package com.kenai.jnr.x86asm;
import static com.kenai.jnr.x86asm.REG.*;
import static com.kenai.jnr.x86asm.SIZE.*;
public final class Register extends BaseReg {
private static final Register[] gpb = new Register[16];
private static final Register[] gpw = new Register[16];
private static final Register[] gpd = new Register[16];
private static final Register[] gpq = new Register[16];
static {
for (int i = 0; i < 16; ++i) {
gpb[i] = new Register(REG_GPB | i, SIZE_BYTE);
gpw[i] = new Register(REG_GPW | i, SIZE_WORD);
gpd[i] = new Register(REG_GPD | i, SIZE_DWORD);
gpq[i] = new Register(REG_GPQ | i, SIZE_QWORD);
}
}
Register(int code, int size) {
super(code, size);
}
public static final Register gpr(int reg) {
switch (reg & REGTYPE_MASK) {
case REG_GPB:
return gpb[reg & REGCODE_MASK];
case REG_GPW:
return gpw[reg & REGCODE_MASK];
case REG_GPD:
return gpd[reg & REGCODE_MASK];
case REG_GPQ:
return gpq[reg & REGCODE_MASK];
}
throw new IllegalArgumentException("invalid register 0x" + Integer.toHexString(reg));
}
private static final Register gpr(Register[] cache, int idx) {
if (idx >= 0 && idx < 16) {
return cache[idx];
}
throw new IllegalArgumentException("invalid register index " + idx);
}
public static final Register gpb(int idx) {
return gpr(gpb, idx);
}
public static final Register gpw(int idx) {
return gpr(gpw, idx);
}
public static final Register gpd(int idx) {
return gpr(gpd, idx);
}
public static final Register gpq(int idx) {
return gpr(gpq, idx);
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/Label.java 0000644 0001750 0001750 00000006444 11425031554 021472 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
import java.util.LinkedList;
import java.util.List;
import static com.kenai.jnr.x86asm.LABEL_STATE.*;
/**
*
*/
public final class Label extends Operand {
/** Label Id (0 means unknown). */
final int id;
/** State of label, see {@link LABEL_STATE}. */
LABEL_STATE state;
/** Position (always positive, information depends to @c state). */
int position;
final List links = new LinkedList();
public Label() {
this(0);
}
public Label(int id) {
super(OP.OP_LABEL, 4);
this.id = id;
this.state = LABEL_STATE_UNUSED;
this.position = -1;
}
/** Returns @c true if label is unused (not bound or linked). */
final boolean isUnused() {
return state == LABEL_STATE_UNUSED;
}
/** Returns @c true if label is linked. */
final boolean isLinked() {
return state == LABEL_STATE_LINKED;
}
/** Returns @c true if label is bound. */
final boolean isBound() {
return state == LABEL_STATE_BOUND;
}
/** Returns the position of bound or linked labels, -1 if label
* is unused.
*/
final int position() {
return position;
}
final void link(LinkData link) {
links.add(link);
state = LABEL_STATE_LINKED;
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/Serializer.java 0000644 0001750 0001750 00000004617 11425031554 022564 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
/**
* Assembler instruction serializer.
*
* Serializer functionality is implemented in {@link SerializerCore} class
* and serializer intrinsics are implemented in {@link SerializerIntrinsics} class.
*
* Always use this class and never use {@link SerializerCore} or {@link SerializerIntrinsics}
* classes directly.
*/
public abstract class Serializer extends SerializerIntrinsics {
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/CONDITION.java 0000644 0001750 0001750 00000007202 11425031554 021772 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
/**
*
*/
public enum CONDITION {
//! @brief No condition code.
C_NO_CONDITION (-1),
// Condition codes from processor manuals.
C_A (0x7),
C_AE (0x3),
C_B (0x2),
C_BE (0x6),
C_C (0x2),
C_E (0x4),
C_G (0xF),
C_GE (0xD),
C_L (0xC),
C_LE (0xE),
C_NA (0x6),
C_NAE (0x2),
C_NB (0x3),
C_NBE (0x7),
C_NC (0x3),
C_NE (0x5),
C_NG (0xE),
C_NGE (0xC),
C_NL (0xD),
C_NLE (0xF),
C_NO (0x1),
C_NP (0xB),
C_NS (0x9),
C_NZ (0x5),
C_O (0x0),
C_P (0xA),
C_PE (0xA),
C_PO (0xB),
C_S (0x8),
C_Z (0x4),
// Simplified condition codes
C_OVERFLOW (0x0),
C_NO_OVERFLOW (0x1),
C_BELOW (0x2),
C_ABOVE_EQUAL (0x3),
C_EQUAL (0x4),
C_NOT_EQUAL (0x5),
C_BELOW_EQUAL (0x6),
C_ABOVE (0x7),
C_SIGN (0x8),
C_NOT_SIGN (0x9),
C_PARITY_EVEN (0xA),
C_PARITY_ODD (0xB),
C_LESS (0xC),
C_GREATER_EQUAL (0xD),
C_LESS_EQUAL (0xE),
C_GREATER (0xF),
// aliases
C_ZERO (0x4),
C_NOT_ZERO (0x5),
C_NEGATIVE (0x8),
C_POSITIVE (0x9),
// x87 floating point only
C_FP_UNORDERED (16),
C_FP_NOT_UNORDERED(17);
private final int value;
CONDITION(int value) {
this.value = value;
}
public final int value() {
return this.value;
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/SerializerCore.java 0000644 0001750 0001750 00000015610 11425031554 023370 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
import static com.kenai.jnr.x86asm.INST_CODE.*;
/**
* Assembler intrinsics seralizer.
*
* SerializerCore is abstract class that is used by @c Assembler and @a Compiler.
* You probably never use this class directly, instead you use it to serialize
* intrinsics to @c Assembler or @c Compiler. @c SerializerIntrinsics implements
* all intruction intrinsics thats used and @c Serializer is public serializer
* class that should be used (instead of @c SerializerCore or @c SerializerInstrinsics).
*
* Note: Use always {@link Serializer} class, this class is only designed to
* decrease code size when exporting AsmJit library symbols. Some compilers
* (for example MSVC) are exporting inline symbols when class is declared
* to export them and {@link Serializer} class contains really huge count of
* symbols that will be never used (everything is inlined).
*/
public abstract class SerializerCore {
static final Operand _none = new Operand(OP.OP_NONE, 0) {};
//! @brief Emits X86/FPU or MM instruction.
//!
//! Operands @a o1, @a o2 or @a o3 can be @c NULL if they are not used.
//!
//! Hint: Use @c emitX86() helpers to emit instructions.
abstract void _emitX86(INST_CODE code, Operand o1, Operand o2, Operand o3);
// Helpers to decrease binary code size. These four emit methods are just
// helpers thats used by serializer. They call _emitX86() adding NULLs
// to first, second and third operand if needed.
//! @brief Emits instruction with no operand.
//!
//! Should be use as an alternative to @c _emitX86() method.
void emitX86(INST_CODE code) {
_emitX86(code, _none, _none, _none);
}
//! @brief Emits instruction with one operand.
//!
//! Should be use as an alternative to @c _emitX86() method.
void emitX86(INST_CODE code, Operand o1) {
_emitX86(code, o1, _none, _none);
}
//! @brief Emits instruction with two operands.
//!
//! Should be use as an alternative to @c _emitX86() method.
void emitX86(INST_CODE code, Operand o1, Operand o2) {
_emitX86(code, o1, o2, _none);
}
//! @brief Emits instruction with three operands.
//!
//! Should be use as an alternative to @c _emitX86() method.
void emitX86(INST_CODE code, Operand o1, Operand o2, Operand o3) {
_emitX86(code, o1, o2, o3);
}
//! @brief Private method for emitting jcc.
//! @internal This should be probably private.
void _emitJcc(INST_CODE code, Label label, final int hint) {
if (hint == 0) {
emitX86(code, label);
} else {
emitX86(code, label, Immediate.imm(hint));
}
}
//! @brief Private method for emitting jcc.
//! @internal This should be probably private.
void _emitJcc(INST_CODE code, Label label, final HINT hint) {
if (hint == HINT.HINT_NONE) {
emitX86(code, label);
} else {
emitX86(code, label, Immediate.imm(hint.value()));
}
}
abstract boolean is64();
//! @brief Translate condition code @a CC to AsmJit jump (jcc) instruction code.
//! @sa @c INST_CODE, @c INST_J.
static INST_CODE conditionToJCC(CONDITION cc) {
assert (cc.value() <= 0xF);
return _jcctable[cc.value()];
}
//! @brief Translate condition code @a CC to AsmJit cmov (cmovcc) instruction code.
//! @sa @c INST_CODE, @c INST_CMOV.
static INST_CODE conditionToCMovCC(CONDITION cc) {
assert (cc.value() <= 0xF);
return _cmovcctable[cc.value()];
}
//! @brief Translate condition code @a CC to AsmJit set (setcc) instruction code.
//! @sa @c INST_CODE, @c INST_SET.
static INST_CODE conditionToSetCC(CONDITION cc) {
assert (cc.value() <= 0xF);
return _setcctable[cc.value()];
}
/** Map used for jcc instructions. */
static INST_CODE[] _jcctable = {
INST_JO,
INST_JNO,
INST_JB,
INST_JAE,
INST_JE,
INST_JNE,
INST_JBE,
INST_JA,
INST_JS,
INST_JNS,
INST_JPE,
INST_JPO,
INST_JL,
INST_JGE,
INST_JLE,
INST_JG
};
/** Map used for cmovcc instructions. */
static INST_CODE[] _cmovcctable = {
INST_CMOVO,
INST_CMOVNO,
INST_CMOVB,
INST_CMOVAE,
INST_CMOVE,
INST_CMOVNE,
INST_CMOVBE,
INST_CMOVA,
INST_CMOVS,
INST_CMOVNS,
INST_CMOVPE,
INST_CMOVPO,
INST_CMOVL,
INST_CMOVGE,
INST_CMOVLE,
INST_CMOVG
};
static final INST_CODE[] _setcctable = {
INST_SETO,
INST_SETNO,
INST_SETB,
INST_SETAE,
INST_SETE,
INST_SETNE,
INST_SETBE,
INST_SETA,
INST_SETS,
INST_SETNS,
INST_SETPE,
INST_SETPO,
INST_SETL,
INST_SETGE,
INST_SETLE,
INST_SETG
};
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/OP.java 0000644 0001750 0001750 00000005052 11425031554 020763 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
/** Operand types that can be encoded in Op operand */
public final class OP {
/** Invalid operand */
public static final int OP_NONE = 0;
/** Operand is register. */
public static final int OP_REG = 1;
/** Operand is memory. */
public static final int OP_MEM = 2;
/** Operand is immediate. */
public static final int OP_IMM = 3;
/** Operand is label. */
public static final int OP_LABEL = 4;
/** Operand is variable. */
public static final int OP_VAR = 5;
private OP() { }
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/LABEL_STATE.java 0000644 0001750 0001750 00000004326 11425031554 022227 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
public enum LABEL_STATE {
/** Label is unused. */
LABEL_STATE_UNUSED,
/** Label is linked (waiting to be bound) */
LABEL_STATE_LINKED,
/** Label is bound */
LABEL_STATE_BOUND;
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/LinkData.java 0000644 0001750 0001750 00000004606 11425031554 022140 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
/**
*
*/
final class LinkData {
final int offset;
//! @brief Inlined displacement.
long displacement;
//! @brief RelocId if link must be absolute when relocated.
int relocId;
public LinkData(int offset, long displacement, int relocId) {
this.offset = offset;
this.displacement = displacement;
this.relocId = relocId;
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/Mem.java 0000644 0001750 0001750 00000007561 11425031554 021172 0 ustar twerner twerner // Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
import static com.kenai.jnr.x86asm.REG.*;
import static com.kenai.jnr.x86asm.SEGMENT.*;
/**
*
*/
public final class Mem extends Operand {
//! @brief Base register index, see @c REG.
private final int base;
//! @brief Index register index, see @c REG.
private final int index;
//! @brief Index register shift (0 to 3 included).
private final int shift;
//! @brief Segment override prefix, see @c AsmJit::SEGMENT.
private final SEGMENT segmentPrefix;
private final Label label;
private final long target;
private final long displacement;
Mem(Label label, long displacement, int size) {
this(NO_REG, NO_REG, 0, SEGMENT_NONE, label, 0, displacement, size);
}
Mem(Register base, long displacement, int size) {
this(base.index(), NO_REG, 0, SEGMENT_NONE, null, 0, displacement, size);
}
Mem(Register base, Register index, int shift, long displacement, int size) {
this(base.index(), index.index(), shift, SEGMENT_NONE, null, 0, displacement, size);
}
Mem(Label label, Register index, int shift, long disp, int ptrSize) {
this(0, index.index(), shift, SEGMENT_NONE, label, 0, disp, ptrSize);
}
Mem(long target, long disp, SEGMENT segmentPrefix, int ptrSize) {
this(NO_REG, NO_REG, 0, segmentPrefix, null, target, disp, ptrSize);
}
Mem(long target, Register index, int shift, SEGMENT segmentPrefix, long disp, int ptrSize) {
this(NO_REG, index.index(), shift, segmentPrefix, null, target, disp, ptrSize);
}
private Mem(int base, int index, int shift, SEGMENT segmentPrefix, Label label, long target, long displacement, int size) {
super(OP.OP_MEM, size);
assert(shift <= 3);
this.base = base;
this.index = index;
this.shift = shift;
this.segmentPrefix = segmentPrefix;
this.label = label;
this.target = target;
this.displacement = displacement;
}
public final boolean hasLabel() {
return label != null;
}
//! @brief Return if address has base register.
public final boolean hasBase() {
return base != NO_REG;
}
//! @brief Return if address has index register.
boolean hasIndex() {
return index != NO_REG;
}
public final SEGMENT segmentPrefix() {
return segmentPrefix;
}
public final int base() {
return base;
}
public final long displacement() {
return displacement;
}
public final int index() {
return index;
}
public final Label label() {
return label;
}
public final int shift() {
return shift;
}
public final long target() {
return target;
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/REG.java 0000644 0001750 0001750 00000015030 11425031554 021057 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
public class REG {
private REG() {}
//! @brief Mask for register type.
public static final int REGTYPE_MASK = 0xF0,
//! @brief Mask for register code (index).
REGCODE_MASK = 0x0F,
// First nibble contains register type (mask 0xF0), Second nibble contains
// register index code.
// [8 bit, 16 bit and 32 bit general purpose registers]
//! @brief 8 bit general purpose register type.
REG_GPB = 0x00,
//! @brief 16 bit general purpose register type.
REG_GPW = 0x10,
//! @brief 32 bit general purpose register type.
REG_GPD = 0x20,
// [64 bit registers (RAX, RBX, ...), not available in 32 bit mode]
//! @brief 64 bit general purpose register type.
REG_GPQ = 0x30,
//! @var REG_GPN
//! @brief 32 bit or 64 bit general purpose register type.
// native 32 bit or 64 bit registers
//#if defined(ASMJIT_X86)
// REG_GPN = REG_GPD,
//#else
// REG_GPN = REG_GPQ,
//#endif
//! @brief X87 (FPU) register type.
REG_X87 = 0x50,
//! @brief 64 bit mmx register type.
REG_MM = 0x60,
//! @brief 128 bit sse register type.
REG_XMM = 0x70,
// 8/16 bit registers
REG_AL = REG_GPB + 0,
REG_CL = REG_GPB + 1,
REG_DL = REG_GPB + 2,
REG_BL = REG_GPB + 3,
REG_AH = REG_GPB + 4,
REG_CH = REG_GPB + 5,
REG_DH = REG_GPB + 6,
REG_BH = REG_GPB + 7,
REG_R8B = REG_GPB + 8,
REG_R9B = REG_GPB + 9,
REG_R10B = REG_GPB + 10,
REG_R11B = REG_GPB + 11,
REG_R12B = REG_GPB + 12,
REG_R13B = REG_GPB + 13,
REG_R14B = REG_GPB + 14,
REG_R15B = REG_GPB + 15,
REG_AX = REG_GPW + 0,
REG_CX = REG_GPW + 1,
REG_DX = REG_GPW + 2,
REG_BX = REG_GPW + 3,
REG_SP = REG_GPW + 4,
REG_BP = REG_GPW + 5,
REG_SI = REG_GPW + 6,
REG_DI = REG_GPW + 7,
REG_R8W = REG_GPW + 8,
REG_R9W = REG_GPW + 9,
REG_R10W = REG_GPW + 10,
REG_R11W = REG_GPW + 11,
REG_R12W = REG_GPW + 12,
REG_R13W = REG_GPW + 13,
REG_R14W = REG_GPW + 14,
REG_R15W = REG_GPW + 15,
// 32 bit registers
REG_EAX = REG_GPD + 0,
REG_ECX = REG_GPD + 1,
REG_EDX = REG_GPD + 2,
REG_EBX = REG_GPD + 3,
REG_ESP = REG_GPD + 4,
REG_EBP = REG_GPD + 5,
REG_ESI = REG_GPD + 6,
REG_EDI = REG_GPD + 7,
REG_R8D = REG_GPD + 8,
REG_R9D = REG_GPD + 9,
REG_R10D = REG_GPD + 10,
REG_R11D = REG_GPD + 11,
REG_R12D = REG_GPD + 12,
REG_R13D = REG_GPD + 13,
REG_R14D = REG_GPD + 14,
REG_R15D = REG_GPD + 15,
// 64 bit registers
REG_RAX = REG_GPQ + 0,
REG_RCX = REG_GPQ + 1,
REG_RDX = REG_GPQ + 2,
REG_RBX = REG_GPQ + 3,
REG_RSP = REG_GPQ + 4,
REG_RBP = REG_GPQ + 5,
REG_RSI = REG_GPQ + 6,
REG_RDI = REG_GPQ + 7,
REG_R8 = REG_GPQ + 8,
REG_R9 = REG_GPQ + 9,
REG_R10 = REG_GPQ + 10,
REG_R11 = REG_GPQ + 11,
REG_R12 = REG_GPQ + 12,
REG_R13 = REG_GPQ + 13,
REG_R14 = REG_GPQ + 14,
REG_R15 = REG_GPQ + 15,
// MMX registers
REG_MM0 = REG_MM + 0,
REG_MM1 = REG_MM + 1,
REG_MM2 = REG_MM + 2,
REG_MM3 = REG_MM + 3,
REG_MM4 = REG_MM + 4,
REG_MM5 = REG_MM + 5,
REG_MM6 = REG_MM + 6,
REG_MM7 = REG_MM + 7,
// SSE registers
REG_XMM0 = REG_XMM + 0,
REG_XMM1 = REG_XMM + 1,
REG_XMM2 = REG_XMM + 2,
REG_XMM3 = REG_XMM + 3,
REG_XMM4 = REG_XMM + 4,
REG_XMM5 = REG_XMM + 5,
REG_XMM6 = REG_XMM + 6,
REG_XMM7 = REG_XMM + 7,
REG_XMM8 = REG_XMM + 8,
REG_XMM9 = REG_XMM + 9,
REG_XMM10 = REG_XMM + 10,
REG_XMM11 = REG_XMM + 11,
REG_XMM12 = REG_XMM + 12,
REG_XMM13 = REG_XMM + 13,
REG_XMM14 = REG_XMM + 14,
REG_XMM15 = REG_XMM + 15,
// native registers (depends if processor runs in 32 bit or 64 bit mode)
//#if defined(ASMJIT_X86)
// REG_NAX = REG_GPD , REG_NCX , REG_NDX , REG_NBX , REG_NSP , REG_NBP , REG_NSI , REG_NDI ,
//#else
// REG_NAX = REG_GPQ , REG_NCX , REG_NDX , REG_NBX , REG_NSP , REG_NBP , REG_NSI , REG_NDI ,
//#endif
//! @brief Invalid register code.
NO_REG = 0xFF;
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/SIZE.java 0000644 0001750 0001750 00000004771 11425031554 021226 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
/** Size of registers and pointers */
public class SIZE {
/** 1 byte size. */
public static final int SIZE_BYTE = 1;
/** 2 bytes size. */
public static final int SIZE_WORD = 2;
/** 4 bytes size. */
public static final int SIZE_DWORD= 4;
/** 8 bytes size. */
public static final int SIZE_QWORD = 8;
/** 10 bytes size. */
public static final int SIZE_TWORD = 10;
/** 16 bytes size. */
public static final int SIZE_DQWORD = 16;
private SIZE() {}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/XMMRegister.java 0000644 0001750 0001750 00000002455 11425031554 022617 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
package com.kenai.jnr.x86asm;
public final class XMMRegister extends BaseReg {
/** Internal cache of xmm registers */
static final XMMRegister[] cache = new XMMRegister[16];
static {
for (int i = 0; i < cache.length; ++i) {
cache[i] = new XMMRegister(REG.REG_XMM | i, 16);
}
}
private XMMRegister(int code, int size) {
super(code, size);
}
public static final XMMRegister xmm(int idx) {
if (idx >= 0 && idx < cache.length) {
return cache[idx];
}
throw new IllegalArgumentException("invalid xmm register");
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/PROPERTY.java 0000644 0001750 0001750 00000005106 11425031554 021731 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
/**
* Assembler/Compiler properties.
*/
public final class PROPERTY {
/**
* Optimize align for current processor.
*
* Default: @c true.
*/
public static final int PROPERTY_OPTIMIZE_ALIGN = 0;
/**
* Force rex prefix emitting.
*
* Default: @c false.
*
* @note This is X86/X86 property only.
*/
public static final int PROPERTY_X86_FORCE_REX = 1;
/**
* Emit hints added to jcc() instructions.
*
* Default: @c true.
*
* @note This is X86/X86 property only.
*/
public static final int PROPERTY_X86_JCC_HINTS = 2;
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/Operand.java 0000644 0001750 0001750 00000007374 11425031554 022046 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
import static com.kenai.jnr.x86asm.OP.*;
public class Operand {
private final int op;
private final int size;
public Operand(int op, int size) {
this.op = op;
this.size = size;
}
/** Return type of operand, see @c OP. */
public int op() {
return op;
}
public int size() {
return size;
}
/** Return @c true if operand is none (@c OP_NONE). */
public boolean isNone() {
return op() == OP_NONE;
}
/** Return @c true if operand is any (general purpose, mmx or sse) register (@c OP_REG). */
public boolean isReg() {
return op() == OP_REG;
}
/** Return @c true if operand is memory address (@c OP_MEM). */
public boolean isMem() {
return op() == OP_MEM;
}
/** Return @c true if operand is immediate (@c OP_IMM). */
public boolean isImm() {
return op() == OP_IMM;
}
/** Return @c true if operand is label (@c OP_LABEL). */
public boolean isLabel() {
return op() == OP_LABEL;
}
/** Return @c true if operand is any register or memory. */
public final boolean isRegMem() {
return isMem() || isReg();
}
public final boolean isRegCode(int code) {
return this instanceof BaseReg && ((BaseReg) this).code() == code;
}
public final boolean isRegType(int type) {
return this instanceof BaseReg && ((BaseReg) this).type() == type;
}
public final boolean isRegIndex(int index) {
return this instanceof BaseReg && ((BaseReg) this).index() == index;
}
/** @brief Return @c true if operand is register of @a regType type or memory. */
public final boolean isRegMem(int regType) {
return isMem() || isRegType(regType);
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/InstructionDescription.java 0000644 0001750 0001750 00000241636 11425031554 025204 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
import java.util.EnumMap;
import java.util.Map;
import static com.kenai.jnr.x86asm.INST_CODE.*;
import static com.kenai.jnr.x86asm.InstructionGroup.*;
import static com.kenai.jnr.x86asm.OperandFlags.*;
public final class InstructionDescription {
final INST_CODE code;
final String name;
final InstructionGroup group;
final int o1Flags;
final int o2Flags;
final int opCodeR;
final int opCode1;
final int opCode2;
private static final Map table
= new EnumMap(INST_CODE.class);
private static final InstructionDescription MAKE_INST(INST_CODE code, String name,
InstructionGroup group, int of1, int of2, int r, int op1, int op2) {
InstructionDescription id = new InstructionDescription(code, name, group, of2, of2, r, op1, op2);
table.put(code, id);
return id;
}
InstructionDescription(INST_CODE code, String name, InstructionGroup group, int o1flags, int o2flags, int opCodeR, int opCode1, int opCode2) {
this.code = code;
this.name = name;
this.group = group;
this.o1Flags = o1flags;
this.o2Flags = o2flags;
this.opCodeR = opCodeR;
this.opCode1 = opCode1;
this.opCode2 = opCode2;
}
public static final InstructionDescription find(INST_CODE code) {
InstructionDescription id = table.get(code);
if (id == null) {
throw new IllegalArgumentException("no description for " + code);
}
return id;
}
private static final InstructionDescription[] all = {
// Instruction code (enum) | instruction name | group | operator 1 flags| operator 2 flags| r| opCode1 | opcode2
MAKE_INST(INST_ADC , "adc" , I_ALU , 0 , 0 , 2, 0x00000010, 0x00000080),
MAKE_INST(INST_ADD , "add" , I_ALU , 0 , 0 , 0, 0x00000000, 0x00000080),
MAKE_INST(INST_ADDPD , "addpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F58, 0),
MAKE_INST(INST_ADDPS , "addps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F58, 0),
MAKE_INST(INST_ADDSD , "addsd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF2000F58, 0),
MAKE_INST(INST_ADDSS , "addss" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F58, 0),
MAKE_INST(INST_ADDSUBPD , "addsubpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000FD0, 0),
MAKE_INST(INST_ADDSUBPS , "addsubps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF2000FD0, 0),
MAKE_INST(INST_AMD_PREFETCH , "amd_prefetch" , I_M , O_MEM , 0 , 0, 0x00000F0D, 0),
MAKE_INST(INST_AMD_PREFETCHW , "amd_prefetchw" , I_M , O_MEM , 0 , 1, 0x00000F0D, 0),
MAKE_INST(INST_AND , "and" , I_ALU , 0 , 0 , 4, 0x00000020, 0x00000080),
MAKE_INST(INST_ANDNPD , "andnpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F55, 0),
MAKE_INST(INST_ANDNPS , "andnps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F55, 0),
MAKE_INST(INST_ANDPD , "andpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F54, 0),
MAKE_INST(INST_ANDPS , "andps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F54, 0),
MAKE_INST(INST_BLENDPD , "blendpd" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A0D, 0),
MAKE_INST(INST_BLENDPS , "blendps" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A0C, 0),
MAKE_INST(INST_BLENDVPD , "blendvpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3815, 0),
MAKE_INST(INST_BLENDVPS , "blendvps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3814, 0),
MAKE_INST(INST_BSF , "bsf" , I_R_RM , 0 , 0 , 0, 0x00000FBC, 0),
MAKE_INST(INST_BSR , "bsr" , I_R_RM , 0 , 0 , 0, 0x00000FBD, 0),
MAKE_INST(INST_BSWAP , "bswap" , I_BSWAP , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_BT , "bt" , I_BT ,O_G16_32_64|O_MEM,O_G16_32_64|O_IMM, 4, 0x00000FA3, 0x00000FBA),
MAKE_INST(INST_BTC , "btc" , I_BT ,O_G16_32_64|O_MEM,O_G16_32_64|O_IMM, 7, 0x00000FBB, 0x00000FBA),
MAKE_INST(INST_BTR , "btr" , I_BT ,O_G16_32_64|O_MEM,O_G16_32_64|O_IMM, 6, 0x00000FB3, 0x00000FBA),
MAKE_INST(INST_BTS , "bts" , I_BT ,O_G16_32_64|O_MEM,O_G16_32_64|O_IMM, 5, 0x00000FAB, 0x00000FBA),
MAKE_INST(INST_CALL , "call" , I_CALL , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_CBW , "cbw" , I_EMIT , 0 , 0 , 0, 0x66000099, 0),
MAKE_INST(INST_CDQE , "cdqe" , I_EMIT , 0 , 0 , 0, 0x48000099, 0),
MAKE_INST(INST_CLC , "clc" , I_EMIT , 0 , 0 , 0, 0x000000F8, 0),
MAKE_INST(INST_CLD , "cld" , I_EMIT , 0 , 0 , 0, 0x000000FC, 0),
MAKE_INST(INST_CLFLUSH , "clflush" , I_M , O_MEM , 0 , 7, 0x00000FAE, 0),
MAKE_INST(INST_CMC , "cmc" , I_EMIT , 0 , 0 , 0, 0x000000F5, 0),
MAKE_INST(INST_CMOVA , "cmova" , I_R_RM , 0 , 0 , 0, 0x00000F47, 0),
MAKE_INST(INST_CMOVAE , "cmovae" , I_R_RM , 0 , 0 , 0, 0x00000F43, 0),
MAKE_INST(INST_CMOVB , "cmovb" , I_R_RM , 0 , 0 , 0, 0x00000F42, 0),
MAKE_INST(INST_CMOVBE , "cmovbe" , I_R_RM , 0 , 0 , 0, 0x00000F46, 0),
MAKE_INST(INST_CMOVC , "cmovc" , I_R_RM , 0 , 0 , 0, 0x00000F42, 0),
MAKE_INST(INST_CMOVE , "cmove" , I_R_RM , 0 , 0 , 0, 0x00000F44, 0),
MAKE_INST(INST_CMOVG , "cmovg" , I_R_RM , 0 , 0 , 0, 0x00000F4F, 0),
MAKE_INST(INST_CMOVGE , "cmovge" , I_R_RM , 0 , 0 , 0, 0x00000F4D, 0),
MAKE_INST(INST_CMOVL , "cmovl" , I_R_RM , 0 , 0 , 0, 0x00000F4C, 0),
MAKE_INST(INST_CMOVLE , "cmovle" , I_R_RM , 0 , 0 , 0, 0x00000F4E, 0),
MAKE_INST(INST_CMOVNA , "cmovna" , I_R_RM , 0 , 0 , 0, 0x00000F46, 0),
MAKE_INST(INST_CMOVNAE , "cmovnae" , I_R_RM , 0 , 0 , 0, 0x00000F42, 0),
MAKE_INST(INST_CMOVNB , "cmovnb" , I_R_RM , 0 , 0 , 0, 0x00000F43, 0),
MAKE_INST(INST_CMOVNBE , "cmovnbe" , I_R_RM , 0 , 0 , 0, 0x00000F47, 0),
MAKE_INST(INST_CMOVNC , "cmovnc" , I_R_RM , 0 , 0 , 0, 0x00000F43, 0),
MAKE_INST(INST_CMOVNE , "cmovne" , I_R_RM , 0 , 0 , 0, 0x00000F45, 0),
MAKE_INST(INST_CMOVNG , "cmovng" , I_R_RM , 0 , 0 , 0, 0x00000F4E, 0),
MAKE_INST(INST_CMOVNGE , "cmovnge" , I_R_RM , 0 , 0 , 0, 0x00000F4C, 0),
MAKE_INST(INST_CMOVNL , "cmovnl" , I_R_RM , 0 , 0 , 0, 0x00000F4D, 0),
MAKE_INST(INST_CMOVNLE , "cmovnle" , I_R_RM , 0 , 0 , 0, 0x00000F4F, 0),
MAKE_INST(INST_CMOVNO , "cmovno" , I_R_RM , 0 , 0 , 0, 0x00000F41, 0),
MAKE_INST(INST_CMOVNP , "cmovnp" , I_R_RM , 0 , 0 , 0, 0x00000F4B, 0),
MAKE_INST(INST_CMOVNS , "cmovns" , I_R_RM , 0 , 0 , 0, 0x00000F49, 0),
MAKE_INST(INST_CMOVNZ , "cmovnz" , I_R_RM , 0 , 0 , 0, 0x00000F45, 0),
MAKE_INST(INST_CMOVO , "cmovo" , I_R_RM , 0 , 0 , 0, 0x00000F40, 0),
MAKE_INST(INST_CMOVP , "cmovp" , I_R_RM , 0 , 0 , 0, 0x00000F4A, 0),
MAKE_INST(INST_CMOVPE , "cmovpe" , I_R_RM , 0 , 0 , 0, 0x00000F4A, 0),
MAKE_INST(INST_CMOVPO , "cmovpo" , I_R_RM , 0 , 0 , 0, 0x00000F4B, 0),
MAKE_INST(INST_CMOVS , "cmovs" , I_R_RM , 0 , 0 , 0, 0x00000F48, 0),
MAKE_INST(INST_CMOVZ , "cmovz" , I_R_RM , 0 , 0 , 0, 0x00000F44, 0),
MAKE_INST(INST_CMP , "cmp" , I_ALU , 0 , 0 , 7, 0x00000038, 0x00000080),
MAKE_INST(INST_CMPPD , "cmppd" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x66000FC2, 0),
MAKE_INST(INST_CMPPS , "cmpps" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x00000FC2, 0),
MAKE_INST(INST_CMPSD , "cmpsd" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0xF2000FC2, 0),
MAKE_INST(INST_CMPSS , "cmpss" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0xF3000FC2, 0),
MAKE_INST(INST_CMPXCHG , "cmpxchg" , I_RM_R , 0 , 0 , 0, 0x00000FB0, 0),
MAKE_INST(INST_CMPXCHG16B , "cmpxchg16b" , I_M , O_MEM , 0 , 1, 0x00000FC7, 1 /* RexW */),
MAKE_INST(INST_CMPXCHG8B , "cmpxchg8b" , I_M , O_MEM , 0 , 1, 0x00000FC7, 0),
MAKE_INST(INST_COMISD , "comisd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F2F, 0),
MAKE_INST(INST_COMISS , "comiss" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F2F, 0),
MAKE_INST(INST_CPUID , "cpuid" , I_EMIT , 0 , 0 , 0, 0x00000FA2, 0),
MAKE_INST(INST_CRC32 , "crc32" , I_CRC32 , 0 , 0 , 0, 0xF20F38F0, 0),
MAKE_INST(INST_CVTDQ2PD , "cvtdq2pd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000FE6, 0),
MAKE_INST(INST_CVTDQ2PS , "cvtdq2ps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F5B, 0),
MAKE_INST(INST_CVTPD2DQ , "cvtpd2dq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF2000FE6, 0),
MAKE_INST(INST_CVTPD2PI , "cvtpd2pi" , I_MMU_RMI , O_MM , O_XMM_MEM , 0, 0x66000F2D, 0),
MAKE_INST(INST_CVTPD2PS , "cvtpd2ps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F5A, 0),
MAKE_INST(INST_CVTPI2PD , "cvtpi2pd" , I_MMU_RMI , O_XMM , O_MM_MEM , 0, 0x66000F2A, 0),
MAKE_INST(INST_CVTPI2PS , "cvtpi2ps" , I_MMU_RMI , O_XMM , O_MM_MEM , 0, 0x00000F2A, 0),
MAKE_INST(INST_CVTPS2DQ , "cvtps2dq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F5B, 0),
MAKE_INST(INST_CVTPS2PD , "cvtps2pd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F5A, 0),
MAKE_INST(INST_CVTPS2PI , "cvtps2pi" , I_MMU_RMI , O_MM , O_XMM_MEM , 0, 0x00000F2D, 0),
MAKE_INST(INST_CVTSD2SI , "cvtsd2si" , I_MMU_RMI , O_G32_64 , O_XMM_MEM , 0, 0xF2000F2D, 0),
MAKE_INST(INST_CVTSD2SS , "cvtsd2ss" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF2000F5A, 0),
MAKE_INST(INST_CVTSI2SD , "cvtsi2sd" , I_MMU_RMI , O_XMM , O_G32_64|O_MEM , 0, 0xF2000F2A, 0),
MAKE_INST(INST_CVTSI2SS , "cvtsi2ss" , I_MMU_RMI , O_XMM , O_G32_64|O_MEM , 0, 0xF3000F2A, 0),
MAKE_INST(INST_CVTSS2SD , "cvtss2sd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F5A, 0),
MAKE_INST(INST_CVTSS2SI , "cvtss2si" , I_MMU_RMI , O_G32_64 , O_XMM_MEM , 0, 0xF3000F2D, 0),
MAKE_INST(INST_CVTTPD2DQ , "cvttpd2dq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000FE6, 0),
MAKE_INST(INST_CVTTPD2PI , "cvttpd2pi" , I_MMU_RMI , O_MM , O_XMM_MEM , 0, 0x66000F2C, 0),
MAKE_INST(INST_CVTTPS2DQ , "cvttps2dq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F5B, 0),
MAKE_INST(INST_CVTTPS2PI , "cvttps2pi" , I_MMU_RMI , O_MM , O_XMM_MEM , 0, 0x00000F2C, 0),
MAKE_INST(INST_CVTTSD2SI , "cvttsd2si" , I_MMU_RMI , O_G32_64 , O_XMM_MEM , 0, 0xF2000F2C, 0),
MAKE_INST(INST_CVTTSS2SI , "cvttss2si" , I_MMU_RMI , O_G32_64 , O_XMM_MEM , 0, 0xF3000F2C, 0),
MAKE_INST(INST_CWDE , "cwde" , I_EMIT , 0 , 0 , 0, 0x00000099, 0),
MAKE_INST(INST_DAA , "daa" , I_EMIT , 0 , 0 , 0, 0x00000027, 0),
MAKE_INST(INST_DAS , "das" , I_EMIT , 0 , 0 , 0, 0x0000002F, 0),
MAKE_INST(INST_DEC , "dec" , I_INC_DEC , 0 , 0 , 1, 0x00000048, 0x000000FE),
MAKE_INST(INST_DIV , "div" , I_RM , 0 , 0 , 6, 0x000000F6, 0),
MAKE_INST(INST_DIVPD , "divpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F5E, 0),
MAKE_INST(INST_DIVPS , "divps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F5E, 0),
MAKE_INST(INST_DIVSD , "divsd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF2000F5E, 0),
MAKE_INST(INST_DIVSS , "divss" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F5E, 0),
MAKE_INST(INST_DPPD , "dppd" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A41, 0),
MAKE_INST(INST_DPPS , "dpps" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A40, 0),
MAKE_INST(INST_EMMS , "emms" , I_EMIT , 0 , 0 , 0, 0x00000F77, 0),
MAKE_INST(INST_ENTER , "enter" , I_ENTER , 0 , 0 , 0, 0x000000C8, 0),
MAKE_INST(INST_EXTRACTPS , "extractps" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A17, 0),
MAKE_INST(INST_F2XM1 , "f2xm1" , I_EMIT , 0 , 0 , 0, 0x0000D9F0, 0),
MAKE_INST(INST_FABS , "fabs" , I_EMIT , 0 , 0 , 0, 0x0000D9E1, 0),
MAKE_INST(INST_FADD , "fadd" , I_X87_FPU , 0 , 0 , 0, 0xD8C0DCC0, 0),
MAKE_INST(INST_FADDP , "faddp" , I_X87_STI , 0 , 0 , 0, 0x0000DEC0, 0),
MAKE_INST(INST_FBLD , "fbld" , I_M , O_MEM , 0 , 4, 0x000000DF, 0),
MAKE_INST(INST_FBSTP , "fbstp" , I_M , O_MEM , 0 , 6, 0x000000DF, 0),
MAKE_INST(INST_FCHS , "fchs" , I_EMIT , 0 , 0 , 0, 0x0000D9E0, 0),
MAKE_INST(INST_FCLEX , "fclex" , I_EMIT , 0 , 0 , 0, 0x9B00DBE2, 0),
MAKE_INST(INST_FCMOVB , "fcmovb" , I_X87_STI , 0 , 0 , 0, 0x0000DAC0, 0),
MAKE_INST(INST_FCMOVBE , "fcmovbe" , I_X87_STI , 0 , 0 , 0, 0x0000DAD0, 0),
MAKE_INST(INST_FCMOVE , "fcmove" , I_X87_STI , 0 , 0 , 0, 0x0000DAC8, 0),
MAKE_INST(INST_FCMOVNB , "fcmovnb" , I_X87_STI , 0 , 0 , 0, 0x0000DBC0, 0),
MAKE_INST(INST_FCMOVNBE , "fcmovnbe" , I_X87_STI , 0 , 0 , 0, 0x0000DBD0, 0),
MAKE_INST(INST_FCMOVNE , "fcmovne" , I_X87_STI , 0 , 0 , 0, 0x0000DBC8, 0),
MAKE_INST(INST_FCMOVNU , "fcmovnu" , I_X87_STI , 0 , 0 , 0, 0x0000DBD8, 0),
MAKE_INST(INST_FCMOVU , "fcmovu" , I_X87_STI , 0 , 0 , 0, 0x0000DAD8, 0),
MAKE_INST(INST_FCOM , "fcom" , I_X87_FPU , 0 , 0 , 2, 0xD8DCD0D0, 0),
MAKE_INST(INST_FCOMI , "fcomi" , I_X87_STI , 0 , 0 , 0, 0x0000DBF0, 0),
MAKE_INST(INST_FCOMIP , "fcomip" , I_X87_STI , 0 , 0 , 0, 0x0000DFF0, 0),
MAKE_INST(INST_FCOMP , "fcomp" , I_X87_FPU , 0 , 0 , 3, 0xD8DCD8D8, 0),
MAKE_INST(INST_FCOMPP , "fcompp" , I_EMIT , 0 , 0 , 0, 0x0000DED9, 0),
MAKE_INST(INST_FCOS , "fcos" , I_EMIT , 0 , 0 , 0, 0x0000D9FF, 0),
MAKE_INST(INST_FDECSTP , "fdecstp" , I_EMIT , 0 , 0 , 0, 0x0000D9F6, 0),
MAKE_INST(INST_FDIV , "fdiv" , I_X87_FPU , 0 , 0 , 6, 0xD8DCF0F8, 0),
MAKE_INST(INST_FDIVP , "fdivp" , I_X87_STI , 0 , 0 , 0, 0x0000DEF8, 0),
MAKE_INST(INST_FDIVR , "fdivr" , I_X87_FPU , 0 , 0 , 7, 0xD8DCF8F0, 0),
MAKE_INST(INST_FDIVRP , "fdivrp" , I_X87_STI , 0 , 0 , 0, 0x0000DEF0, 0),
MAKE_INST(INST_FEMMS , "femms" , I_EMIT , 0 , 0 , 0, 0x00000F0E, 0),
MAKE_INST(INST_FFREE , "ffree" , I_X87_STI , 0 , 0 , 0, 0x0000DDC0, 0),
MAKE_INST(INST_FIADD , "fiadd" , I_X87_MEM , O_FM_2_4 , 0 , 0, 0xDEDA0000, 0),
MAKE_INST(INST_FICOM , "ficom" , I_X87_MEM , O_FM_2_4 , 0 , 2, 0xDEDA0000, 0),
MAKE_INST(INST_FICOMP , "ficomp" , I_X87_MEM , O_FM_2_4 , 0 , 3, 0xDEDA0000, 0),
MAKE_INST(INST_FIDIV , "fidiv" , I_X87_MEM , O_FM_2_4 , 0 , 6, 0xDEDA0000, 0),
MAKE_INST(INST_FIDIVR , "fidivr" , I_X87_MEM , O_FM_2_4 , 0 , 7, 0xDEDA0000, 0),
MAKE_INST(INST_FILD , "fild" , I_X87_MEM , O_FM_2_4_8 , 0 , 0, 0xDFDBDF05, 0),
MAKE_INST(INST_FIMUL , "fimul" , I_X87_MEM , O_FM_2_4 , 0 , 1, 0xDEDA0000, 0),
MAKE_INST(INST_FINCSTP , "fincstp" , I_EMIT , 0 , 0 , 0, 0x0000D9F7, 0),
MAKE_INST(INST_FINIT , "finit" , I_EMIT , 0 , 0 , 0, 0x9B00DBE3, 0),
MAKE_INST(INST_FIST , "fist" , I_X87_MEM , O_FM_2_4 , 0 , 2, 0xDFDB0000, 0),
MAKE_INST(INST_FISTP , "fistp" , I_X87_MEM , O_FM_2_4_8 , 0 , 3, 0xDFDBDF07, 0),
MAKE_INST(INST_FISTTP , "fisttp" , I_X87_MEM , O_FM_2_4_8 , 0 , 1, 0xDFDBDD01, 0),
MAKE_INST(INST_FISUB , "fisub" , I_X87_MEM , O_FM_2_4 , 0 , 4, 0xDEDA0000, 0),
MAKE_INST(INST_FISUBR , "fisubr" , I_X87_MEM , O_FM_2_4 , 0 , 5, 0xDEDA0000, 0),
MAKE_INST(INST_FLD , "fld" , I_X87_MEM_STI , O_FM_4_8_10 , 0 , 0, 0x00D9DD00, 0xD9C0DB05),
MAKE_INST(INST_FLD1 , "fld1" , I_EMIT , 0 , 0 , 0, 0x0000D9E8, 0),
MAKE_INST(INST_FLDCW , "fldcw" , I_M , O_MEM , 0 , 5, 0x000000D9, 0),
MAKE_INST(INST_FLDENV , "fldenv" , I_M , O_MEM , 0 , 4, 0x000000D9, 0),
MAKE_INST(INST_FLDL2E , "fldl2e" , I_EMIT , 0 , 0 , 0, 0x0000D9EA, 0),
MAKE_INST(INST_FLDL2T , "fldl2t" , I_EMIT , 0 , 0 , 0, 0x0000D9E9, 0),
MAKE_INST(INST_FLDLG2 , "fldlg2" , I_EMIT , 0 , 0 , 0, 0x0000D9EC, 0),
MAKE_INST(INST_FLDLN2 , "fldln2" , I_EMIT , 0 , 0 , 0, 0x0000D9ED, 0),
MAKE_INST(INST_FLDPI , "fldpi" , I_EMIT , 0 , 0 , 0, 0x0000D9EB, 0),
MAKE_INST(INST_FLDZ , "fldz" , I_EMIT , 0 , 0 , 0, 0x0000D9EE, 0),
MAKE_INST(INST_FMUL , "fmul" , I_X87_FPU , 0 , 0 , 1, 0xD8DCC8C8, 0),
MAKE_INST(INST_FMULP , "fmulp" , I_X87_STI , 0 , 0 , 0, 0x0000DEC8, 0),
MAKE_INST(INST_FNCLEX , "fnclex" , I_EMIT , 0 , 0 , 0, 0x0000DBE2, 0),
MAKE_INST(INST_FNINIT , "fninit" , I_EMIT , 0 , 0 , 0, 0x0000DBE3, 0),
MAKE_INST(INST_FNOP , "fnop" , I_EMIT , 0 , 0 , 0, 0x0000D9D0, 0),
MAKE_INST(INST_FNSAVE , "fnsave" , I_M , O_MEM , 0 , 6, 0x000000DD, 0),
MAKE_INST(INST_FNSTCW , "fnstcw" , I_M , O_MEM , 0 , 7, 0x000000D9, 0),
MAKE_INST(INST_FNSTENV , "fnstenv" , I_M , O_MEM , 0 , 6, 0x000000D9, 0),
MAKE_INST(INST_FNSTSW , "fnstsw" , I_X87_FSTSW , O_MEM , 0 , 7, 0x000000DD, 0x0000DFE0),
MAKE_INST(INST_FPATAN , "fpatan" , I_EMIT , 0 , 0 , 0, 0x0000D9F3, 0),
MAKE_INST(INST_FPREM , "fprem" , I_EMIT , 0 , 0 , 0, 0x0000D9F8, 0),
MAKE_INST(INST_FPREM1 , "fprem1" , I_EMIT , 0 , 0 , 0, 0x0000D9F5, 0),
MAKE_INST(INST_FPTAN , "fptan" , I_EMIT , 0 , 0 , 0, 0x0000D9F2, 0),
MAKE_INST(INST_FRNDINT , "frndint" , I_EMIT , 0 , 0 , 0, 0x0000D9FC, 0),
MAKE_INST(INST_FRSTOR , "frstor" , I_M , O_MEM , 0 , 4, 0x000000DD, 0),
MAKE_INST(INST_FSAVE , "fsave" , I_M , O_MEM , 0 , 6, 0x9B0000DD, 0),
MAKE_INST(INST_FSCALE , "fscale" , I_EMIT , 0 , 0 , 0, 0x0000D9FD, 0),
MAKE_INST(INST_FSIN , "fsin" , I_EMIT , 0 , 0 , 0, 0x0000D9FE, 0),
MAKE_INST(INST_FSINCOS , "fsincos" , I_EMIT , 0 , 0 , 0, 0x0000D9FB, 0),
MAKE_INST(INST_FSQRT , "fsqrt" , I_EMIT , 0 , 0 , 0, 0x0000D9FA, 0),
MAKE_INST(INST_FST , "fst" , I_X87_MEM_STI , O_FM_4_8 , 0 , 2, 0x00D9DD02, 0xDDD00000),
MAKE_INST(INST_FSTCW , "fstcw" , I_M , O_MEM , 0 , 7, 0x9B0000D9, 0),
MAKE_INST(INST_FSTENV , "fstenv" , I_M , O_MEM , 0 , 6, 0x9B0000D9, 0),
MAKE_INST(INST_FSTP , "fstp" , I_X87_MEM_STI , O_FM_4_8_10 , 0 , 3, 0x00D9DD03, 0xDDD8DB07),
MAKE_INST(INST_FSTSW , "fstsw" , I_X87_FSTSW , O_MEM , 0 , 7, 0x9B0000DD, 0x9B00DFE0),
MAKE_INST(INST_FSUB , "fsub" , I_X87_FPU , 0 , 0 , 4, 0xD8DCE0E8, 0),
MAKE_INST(INST_FSUBP , "fsubp" , I_X87_STI , 0 , 0 , 0, 0x0000DEE8, 0),
MAKE_INST(INST_FSUBR , "fsubr" , I_X87_FPU , 0 , 0 , 5, 0xD8DCE8E0, 0),
MAKE_INST(INST_FSUBRP , "fsubrp" , I_X87_STI , 0 , 0 , 0, 0x0000DEE0, 0),
MAKE_INST(INST_FTST , "ftst" , I_EMIT , 0 , 0 , 0, 0x0000D9E4, 0),
MAKE_INST(INST_FUCOM , "fucom" , I_X87_STI , 0 , 0 , 0, 0x0000DDE0, 0),
MAKE_INST(INST_FUCOMI , "fucomi" , I_X87_STI , 0 , 0 , 0, 0x0000DBE8, 0),
MAKE_INST(INST_FUCOMIP , "fucomip" , I_X87_STI , 0 , 0 , 0, 0x0000DFE8, 0),
MAKE_INST(INST_FUCOMP , "fucomp" , I_X87_STI , 0 , 0 , 0, 0x0000DDE8, 0),
MAKE_INST(INST_FUCOMPP , "fucompp" , I_EMIT , 0 , 0 , 0, 0x0000DAE9, 0),
MAKE_INST(INST_FWAIT , "fwait" , I_EMIT , 0 , 0 , 0, 0x000000DB, 0),
MAKE_INST(INST_FXAM , "fxam" , I_EMIT , 0 , 0 , 0, 0x0000D9E5, 0),
MAKE_INST(INST_FXCH , "fxch" , I_X87_STI , 0 , 0 , 0, 0x0000D9C8, 0),
MAKE_INST(INST_FXRSTOR , "fxrstor" , I_M , 0 , 0 , 1, 0x00000FAE, 0),
MAKE_INST(INST_FXSAVE , "fxsave" , I_M , 0 , 0 , 0, 0x00000FAE, 0),
MAKE_INST(INST_FXTRACT , "fxtract" , I_EMIT , 0 , 0 , 0, 0x0000D9F4, 0),
MAKE_INST(INST_FYL2X , "fyl2x" , I_EMIT , 0 , 0 , 0, 0x0000D9F1, 0),
MAKE_INST(INST_FYL2XP1 , "fyl2xp1" , I_EMIT , 0 , 0 , 0, 0x0000D9F9, 0),
MAKE_INST(INST_HADDPD , "haddpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F7C, 0),
MAKE_INST(INST_HADDPS , "haddps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF2000F7C, 0),
MAKE_INST(INST_HSUBPD , "hsubpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F7D, 0),
MAKE_INST(INST_HSUBPS , "hsubps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF2000F7D, 0),
MAKE_INST(INST_IDIV , "idiv" , I_RM , 0 , 0 , 7, 0x000000F6, 0),
MAKE_INST(INST_IMUL , "imul" , I_IMUL , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_INC , "inc" , I_INC_DEC , 0 , 0 , 0, 0x00000040, 0x000000FE),
MAKE_INST(INST_INT3 , "int3" , I_EMIT , 0 , 0 , 0, 0x000000CC, 0),
MAKE_INST(INST_JA , "ja" , I_J , 0 , 0 , 0, 0x7 , 0),
MAKE_INST(INST_JAE , "jae" , I_J , 0 , 0 , 0, 0x3 , 0),
MAKE_INST(INST_JB , "jb" , I_J , 0 , 0 , 0, 0x2 , 0),
MAKE_INST(INST_JBE , "jbe" , I_J , 0 , 0 , 0, 0x6 , 0),
MAKE_INST(INST_JC , "jc" , I_J , 0 , 0 , 0, 0x2 , 0),
MAKE_INST(INST_JE , "je" , I_J , 0 , 0 , 0, 0x4 , 0),
MAKE_INST(INST_JG , "jg" , I_J , 0 , 0 , 0, 0xF , 0),
MAKE_INST(INST_JGE , "jge" , I_J , 0 , 0 , 0, 0xD , 0),
MAKE_INST(INST_JL , "jl" , I_J , 0 , 0 , 0, 0xC , 0),
MAKE_INST(INST_JLE , "jle" , I_J , 0 , 0 , 0, 0xE , 0),
MAKE_INST(INST_JNA , "jna" , I_J , 0 , 0 , 0, 0x6 , 0),
MAKE_INST(INST_JNAE , "jnae" , I_J , 0 , 0 , 0, 0x2 , 0),
MAKE_INST(INST_JNB , "jnb" , I_J , 0 , 0 , 0, 0x3 , 0),
MAKE_INST(INST_JNBE , "jnbe" , I_J , 0 , 0 , 0, 0x7 , 0),
MAKE_INST(INST_JNC , "jnc" , I_J , 0 , 0 , 0, 0x3 , 0),
MAKE_INST(INST_JNE , "jne" , I_J , 0 , 0 , 0, 0x5 , 0),
MAKE_INST(INST_JNG , "jng" , I_J , 0 , 0 , 0, 0xE , 0),
MAKE_INST(INST_JNGE , "jnge" , I_J , 0 , 0 , 0, 0xC , 0),
MAKE_INST(INST_JNL , "jnl" , I_J , 0 , 0 , 0, 0xD , 0),
MAKE_INST(INST_JNLE , "jnle" , I_J , 0 , 0 , 0, 0xF , 0),
MAKE_INST(INST_JNO , "jno" , I_J , 0 , 0 , 0, 0x1 , 0),
MAKE_INST(INST_JNP , "jnp" , I_J , 0 , 0 , 0, 0xB , 0),
MAKE_INST(INST_JNS , "jns" , I_J , 0 , 0 , 0, 0x9 , 0),
MAKE_INST(INST_JNZ , "jnz" , I_J , 0 , 0 , 0, 0x5 , 0),
MAKE_INST(INST_JO , "jo" , I_J , 0 , 0 , 0, 0x0 , 0),
MAKE_INST(INST_JP , "jp" , I_J , 0 , 0 , 0, 0xA , 0),
MAKE_INST(INST_JPE , "jpe" , I_J , 0 , 0 , 0, 0xA , 0),
MAKE_INST(INST_JPO , "jpo" , I_J , 0 , 0 , 0, 0xB , 0),
MAKE_INST(INST_JS , "js" , I_J , 0 , 0 , 0, 0x8 , 0),
MAKE_INST(INST_JZ , "jz" , I_J , 0 , 0 , 0, 0x4 , 0),
MAKE_INST(INST_JMP , "jmp" , I_JMP , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_JA_SHORT , "ja short" , I_J , 0 , 0 , 0, 0x7 , 0),
MAKE_INST(INST_JAE_SHORT , "jae short" , I_J , 0 , 0 , 0, 0x3 , 0),
MAKE_INST(INST_JB_SHORT , "jb short" , I_J , 0 , 0 , 0, 0x2 , 0),
MAKE_INST(INST_JBE_SHORT , "jbe short" , I_J , 0 , 0 , 0, 0x6 , 0),
MAKE_INST(INST_JC_SHORT , "jc short" , I_J , 0 , 0 , 0, 0x2 , 0),
MAKE_INST(INST_JE_SHORT , "je short" , I_J , 0 , 0 , 0, 0x4 , 0),
MAKE_INST(INST_JG_SHORT , "jg short" , I_J , 0 , 0 , 0, 0xF , 0),
MAKE_INST(INST_JGE_SHORT , "jge short" , I_J , 0 , 0 , 0, 0xD , 0),
MAKE_INST(INST_JL_SHORT , "jl short" , I_J , 0 , 0 , 0, 0xC , 0),
MAKE_INST(INST_JLE_SHORT , "jle short" , I_J , 0 , 0 , 0, 0xE , 0),
MAKE_INST(INST_JNA_SHORT , "jna short" , I_J , 0 , 0 , 0, 0x6 , 0),
MAKE_INST(INST_JNAE_SHORT , "jnae short" , I_J , 0 , 0 , 0, 0x2 , 0),
MAKE_INST(INST_JNB_SHORT , "jnb short" , I_J , 0 , 0 , 0, 0x3 , 0),
MAKE_INST(INST_JNBE_SHORT , "jnbe short" , I_J , 0 , 0 , 0, 0x7 , 0),
MAKE_INST(INST_JNC_SHORT , "jnc short" , I_J , 0 , 0 , 0, 0x3 , 0),
MAKE_INST(INST_JNE_SHORT , "jne short" , I_J , 0 , 0 , 0, 0x5 , 0),
MAKE_INST(INST_JNG_SHORT , "jng short" , I_J , 0 , 0 , 0, 0xE , 0),
MAKE_INST(INST_JNGE_SHORT , "jnge short" , I_J , 0 , 0 , 0, 0xC , 0),
MAKE_INST(INST_JNL_SHORT , "jnl short" , I_J , 0 , 0 , 0, 0xD , 0),
MAKE_INST(INST_JNLE_SHORT , "jnle short" , I_J , 0 , 0 , 0, 0xF , 0),
MAKE_INST(INST_JNO_SHORT , "jno short" , I_J , 0 , 0 , 0, 0x1 , 0),
MAKE_INST(INST_JNP_SHORT , "jnp short" , I_J , 0 , 0 , 0, 0xB , 0),
MAKE_INST(INST_JNS_SHORT , "jns short" , I_J , 0 , 0 , 0, 0x9 , 0),
MAKE_INST(INST_JNZ_SHORT , "jnz short" , I_J , 0 , 0 , 0, 0x5 , 0),
MAKE_INST(INST_JO_SHORT , "jo short" , I_J , 0 , 0 , 0, 0x0 , 0),
MAKE_INST(INST_JP_SHORT , "jp short" , I_J , 0 , 0 , 0, 0xA , 0),
MAKE_INST(INST_JPE_SHORT , "jpe short" , I_J , 0 , 0 , 0, 0xA , 0),
MAKE_INST(INST_JPO_SHORT , "jpo short" , I_J , 0 , 0 , 0, 0xB , 0),
MAKE_INST(INST_JS_SHORT , "js short" , I_J , 0 , 0 , 0, 0x8 , 0),
MAKE_INST(INST_JZ_SHORT , "jz short" , I_J , 0 , 0 , 0, 0x4 , 0),
MAKE_INST(INST_JMP_SHORT , "jmp short" , I_JMP , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_LDDQU , "lddqu" , I_MMU_RMI , O_XMM , O_MEM , 0, 0xF2000FF0, 0),
MAKE_INST(INST_LDMXCSR , "ldmxcsr" , I_M , O_MEM , 0 , 2, 0x00000FAE, 0),
MAKE_INST(INST_LEA , "lea" , I_LEA , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_LEAVE , "leave" , I_EMIT , 0 , 0 , 0, 0x000000C9, 0),
MAKE_INST(INST_LFENCE , "lfence" , I_EMIT , 0 , 0 , 0, 0x000FAEE8, 0),
MAKE_INST(INST_LOCK , "lock" , I_EMIT , 0 , 0 , 0, 0x000000F0, 0),
MAKE_INST(INST_MASKMOVDQU , "maskmovdqu" , I_MMU_RMI , O_XMM , O_XMM , 0, 0x66000F57, 0),
MAKE_INST(INST_MASKMOVQ , "maskmovq" , I_MMU_RMI , O_MM , O_MM , 0, 0x00000FF7, 0),
MAKE_INST(INST_MAXPD , "maxpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F5F, 0),
MAKE_INST(INST_MAXPS , "maxps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F5F, 0),
MAKE_INST(INST_MAXSD , "maxsd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF2000F5F, 0),
MAKE_INST(INST_MAXSS , "maxss" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F5F, 0),
MAKE_INST(INST_MFENCE , "mfence" , I_EMIT , 0 , 0 , 0, 0x000FAEF0, 0),
MAKE_INST(INST_MINPD , "minpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F5D, 0),
MAKE_INST(INST_MINPS , "minps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F5D, 0),
MAKE_INST(INST_MINSD , "minsd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF2000F5D, 0),
MAKE_INST(INST_MINSS , "minss" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F5D, 0),
MAKE_INST(INST_MONITOR , "monitor" , I_EMIT , 0 , 0 , 0, 0x000F01C8, 0),
MAKE_INST(INST_MOV , "mov" , I_MOV , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_MOVAPD , "movapd" , I_MMU_MOV , O_XMM_MEM , O_XMM_MEM , 0, 0x66000F28, 0x66000F29),
MAKE_INST(INST_MOVAPS , "movaps" , I_MMU_MOV , O_XMM_MEM , O_XMM_MEM , 0, 0x00000F28, 0x00000F29),
MAKE_INST(INST_MOVBE , "movbe" , I_MOVBE ,O_G16_32_64|O_MEM,O_G16_32_64|O_MEM, 0, 0x000F38F0, 0x000F38F1),
MAKE_INST(INST_MOVD , "movd" , I_MMU_MOVD , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_MOVDDUP , "movddup" , I_MMU_MOV , O_XMM , O_XMM_MEM , 0, 0xF2000F12, 0),
MAKE_INST(INST_MOVDQ2Q , "movdq2q" , I_MMU_MOV , O_MM , O_XMM , 0, 0xF2000FD6, 0),
MAKE_INST(INST_MOVDQA , "movdqa" , I_MMU_MOV , O_XMM_MEM , O_XMM_MEM , 0, 0x66000F6F, 0x66000F7F),
MAKE_INST(INST_MOVDQU , "movdqu" , I_MMU_MOV , O_XMM_MEM , O_XMM_MEM , 0, 0xF3000F6F, 0xF3000F7F),
MAKE_INST(INST_MOVHLPS , "movhlps" , I_MMU_MOV , O_XMM , O_XMM , 0, 0x00000F12, 0),
MAKE_INST(INST_MOVHPD , "movhpd" , I_MMU_MOV , O_XMM_MEM , O_XMM_MEM , 0, 0x66000F16, 0x66000F17),
MAKE_INST(INST_MOVHPS , "movhps" , I_MMU_MOV , O_XMM_MEM , O_XMM_MEM , 0, 0x00000F16, 0x00000F17),
MAKE_INST(INST_MOVLHPS , "movlhps" , I_MMU_MOV , O_XMM , O_XMM , 0, 0x00000F16, 0),
MAKE_INST(INST_MOVLPD , "movlpd" , I_MMU_MOV , O_XMM_MEM , O_XMM_MEM , 0, 0x66000F12, 0x66000F13),
MAKE_INST(INST_MOVLPS , "movlps" , I_MMU_MOV , O_XMM_MEM , O_XMM_MEM , 0, 0x00000F12, 0x00000F13),
MAKE_INST(INST_MOVMSKPD , "movmskpd" , I_MMU_MOV , O_G32_64|O_NOREX, O_XMM , 0, 0x66000F50, 0),
MAKE_INST(INST_MOVMSKPS , "movmskps" , I_MMU_MOV , O_G32_64|O_NOREX, O_XMM , 0, 0x00000F50, 0),
MAKE_INST(INST_MOVNTDQ , "movntdq" , I_MMU_MOV , O_MEM , O_XMM , 0, 0 , 0x66000FE7),
MAKE_INST(INST_MOVNTDQA , "movntdqa" , I_MMU_MOV , O_XMM , O_MEM , 0, 0x660F382A, 0),
MAKE_INST(INST_MOVNTI , "movnti" , I_MMU_MOV , O_MEM , O_G32_64 , 0, 0 , 0x00000FC3),
MAKE_INST(INST_MOVNTPD , "movntpd" , I_MMU_MOV , O_MEM , O_XMM , 0, 0 , 0x66000F2B),
MAKE_INST(INST_MOVNTPS , "movntps" , I_MMU_MOV , O_MEM , O_XMM , 0, 0 , 0x00000F2B),
MAKE_INST(INST_MOVNTQ , "movntq" , I_MMU_MOV , O_MEM , O_MM , 0, 0 , 0x00000FE7),
MAKE_INST(INST_MOVQ , "movq" , I_MMU_MOVQ , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_MOVQ2DQ , "movq2dq" , I_MMU_RMI , O_XMM , O_MM , 0, 0xF3000FD6, 0),
MAKE_INST(INST_MOVSD , "movsd" , I_MMU_MOV , O_XMM_MEM , O_XMM_MEM , 0, 0xF2000F10, 0xF2000F11),
MAKE_INST(INST_MOVSHDUP , "movshdup" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F16, 0),
MAKE_INST(INST_MOVSLDUP , "movsldup" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F12, 0),
MAKE_INST(INST_MOVSS , "movss" , I_MMU_MOV , O_XMM_MEM , O_XMM_MEM , 0, 0xF3000F10, 0xF3000F11),
MAKE_INST(INST_MOVSX , "movsx" , I_MOVSX_MOVZX , 0 , 0 , 0, 0x00000FBE, 0),
MAKE_INST(INST_MOVSXD , "movsxd" , I_MOVSXD , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_MOVUPD , "movupd" , I_MMU_MOV , O_XMM_MEM , O_XMM_MEM , 0, 0x66000F10, 0x66000F11),
MAKE_INST(INST_MOVUPS , "movups" , I_MMU_MOV , O_XMM_MEM , O_XMM_MEM , 0, 0x00000F10, 0x00000F11),
MAKE_INST(INST_MOVZX , "movzx" , I_MOVSX_MOVZX , 0 , 0 , 0, 0x00000FB6, 0),
MAKE_INST(INST_MOV_PTR , "mov" , I_MOV_PTR , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_MPSADBW , "mpsadbw" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A42, 0),
MAKE_INST(INST_MUL , "mul" , I_RM , 0 , 0 , 4, 0x000000F6, 0),
MAKE_INST(INST_MULPD , "mulpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F59, 0),
MAKE_INST(INST_MULPS , "mulps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F59, 0),
MAKE_INST(INST_MULSD , "mulsd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF2000F59, 0),
MAKE_INST(INST_MULSS , "mulss" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F59, 0),
MAKE_INST(INST_MWAIT , "mwait" , I_EMIT , 0 , 0 , 0, 0x000F01C9, 0),
MAKE_INST(INST_NEG , "neg" , I_RM , 0 , 0 , 3, 0x000000F6, 0),
MAKE_INST(INST_NOP , "nop" , I_EMIT , 0 , 0 , 0, 0x00000090, 0),
MAKE_INST(INST_NOT , "not" , I_RM , 0 , 0 , 2, 0x000000F6, 0),
MAKE_INST(INST_OR , "or" , I_ALU , 0 , 0 , 1, 0x00000008, 0x00000080),
MAKE_INST(INST_ORPD , "orpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F56, 0),
MAKE_INST(INST_ORPS , "orps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F56, 0),
MAKE_INST(INST_PABSB , "pabsb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F381C, 0),
MAKE_INST(INST_PABSD , "pabsd" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F381E, 0),
MAKE_INST(INST_PABSW , "pabsw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F381D, 0),
MAKE_INST(INST_PACKSSDW , "packssdw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F6B, 0),
MAKE_INST(INST_PACKSSWB , "packsswb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F63, 0),
MAKE_INST(INST_PACKUSDW , "packusdw" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F382B, 0),
MAKE_INST(INST_PACKUSWB , "packuswb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F67, 0),
MAKE_INST(INST_PADDB , "paddb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FFC, 0),
MAKE_INST(INST_PADDD , "paddd" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FFE, 0),
MAKE_INST(INST_PADDQ , "paddq" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FD4, 0),
MAKE_INST(INST_PADDSB , "paddsb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FEC, 0),
MAKE_INST(INST_PADDSW , "paddsw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FED, 0),
MAKE_INST(INST_PADDUSB , "paddusb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FDC, 0),
MAKE_INST(INST_PADDUSW , "paddusw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FDD, 0),
MAKE_INST(INST_PADDW , "paddw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FFD, 0),
MAKE_INST(INST_PALIGNR , "palignr" , I_MMU_RM_IMM8 , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F3A0F, 0),
MAKE_INST(INST_PAND , "pand" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FDB, 0),
MAKE_INST(INST_PANDN , "pandn" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FDF, 0),
MAKE_INST(INST_PAUSE , "pause" , I_EMIT , 0 , 0 , 0, 0xF3000090, 0),
MAKE_INST(INST_PAVGB , "pavgb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FE0, 0),
MAKE_INST(INST_PAVGW , "pavgw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FE3, 0),
MAKE_INST(INST_PBLENDVB , "pblendvb" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3810, 0),
MAKE_INST(INST_PBLENDW , "pblendw" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A0E, 0),
MAKE_INST(INST_PCMPEQB , "pcmpeqb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F74, 0),
MAKE_INST(INST_PCMPEQD , "pcmpeqd" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F76, 0),
MAKE_INST(INST_PCMPEQQ , "pcmpeqq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3829, 0),
MAKE_INST(INST_PCMPEQW , "pcmpeqw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F75, 0),
MAKE_INST(INST_PCMPESTRI , "pcmpestri" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A61, 0),
MAKE_INST(INST_PCMPESTRM , "pcmpestrm" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A60, 0),
MAKE_INST(INST_PCMPGTB , "pcmpgtb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F64, 0),
MAKE_INST(INST_PCMPGTD , "pcmpgtd" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F66, 0),
MAKE_INST(INST_PCMPGTQ , "pcmpgtq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3837, 0),
MAKE_INST(INST_PCMPGTW , "pcmpgtw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F65, 0),
MAKE_INST(INST_PCMPISTRI , "pcmpistri" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A63, 0),
MAKE_INST(INST_PCMPISTRM , "pcmpistrm" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A62, 0),
MAKE_INST(INST_PEXTRB , "pextrb" , I_MMU_PEXTR , O_G8|O_G32|O_MEM, O_XMM , 0, 0x000F3A14, 0),
MAKE_INST(INST_PEXTRD , "pextrd" , I_MMU_PEXTR , O_G32 |O_MEM, O_XMM , 0, 0x000F3A16, 0),
MAKE_INST(INST_PEXTRQ , "pextrq" , I_MMU_PEXTR , O_G32_64 |O_MEM, O_XMM , 1, 0x000F3A16, 0),
MAKE_INST(INST_PEXTRW , "pextrw" , I_MMU_PEXTR , O_G32 |O_MEM, O_XMM | O_MM , 0, 0x000F3A16, 0),
MAKE_INST(INST_PF2ID , "pf2id" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0x1D),
MAKE_INST(INST_PF2IW , "pf2iw" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0x1C),
MAKE_INST(INST_PFACC , "pfacc" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0xAE),
MAKE_INST(INST_PFADD , "pfadd" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0x9E),
MAKE_INST(INST_PFCMPEQ , "pfcmpeq" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0xB0),
MAKE_INST(INST_PFCMPGE , "pfcmpge" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0x90),
MAKE_INST(INST_PFCMPGT , "pfcmpgt" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0xA0),
MAKE_INST(INST_PFMAX , "pfmax" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0xA4),
MAKE_INST(INST_PFMIN , "pfmin" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0x94),
MAKE_INST(INST_PFMUL , "pfmul" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0xB4),
MAKE_INST(INST_PFNACC , "pfnacc" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0x8A),
MAKE_INST(INST_PFPNACC , "pfpnacc" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0x8E),
MAKE_INST(INST_PFRCP , "pfrcp" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0x96),
MAKE_INST(INST_PFRCPIT1 , "pfrcpit1" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0xA6),
MAKE_INST(INST_PFRCPIT2 , "pfrcpit2" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0xB6),
MAKE_INST(INST_PFRSQIT1 , "pfrsqit1" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0xA7),
MAKE_INST(INST_PFRSQRT , "pfrsqrt" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0x97),
MAKE_INST(INST_PFSUB , "pfsub" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0x9A),
MAKE_INST(INST_PFSUBR , "pfsubr" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0xAA),
MAKE_INST(INST_PHADDD , "phaddd" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F3802, 0),
MAKE_INST(INST_PHADDSW , "phaddsw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F3803, 0),
MAKE_INST(INST_PHADDW , "phaddw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F3801, 0),
MAKE_INST(INST_PHMINPOSUW , "phminposuw" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3841, 0),
MAKE_INST(INST_PHSUBD , "phsubd" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F3806, 0),
MAKE_INST(INST_PHSUBSW , "phsubsw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F3807, 0),
MAKE_INST(INST_PHSUBW , "phsubw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F3805, 0),
MAKE_INST(INST_PI2FD , "pi2fd" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0x0D),
MAKE_INST(INST_PI2FW , "pi2fw" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0x0C),
MAKE_INST(INST_PINSRB , "pinsrb" , I_MMU_RM_IMM8 , O_XMM , O_G32 | O_MEM , 0, 0x660F3A20, 0),
MAKE_INST(INST_PINSRD , "pinsrd" , I_MMU_RM_IMM8 , O_XMM , O_G32 | O_MEM , 0, 0x660F3A22, 0),
MAKE_INST(INST_PINSRQ , "pinsrq" , I_MMU_RM_IMM8 , O_XMM , O_G64 | O_MEM , 0, 0x660F3A22, 0),
MAKE_INST(INST_PINSRW , "pinsrw" , I_MMU_RM_IMM8 , O_MM_XMM , O_G32 | O_MEM , 0, 0x00000FC4, 0),
MAKE_INST(INST_PMADDUBSW , "pmaddubsw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F3804, 0),
MAKE_INST(INST_PMADDWD , "pmaddwd" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FF5, 0),
MAKE_INST(INST_PMAXSB , "pmaxsb" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F383C, 0),
MAKE_INST(INST_PMAXSD , "pmaxsd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F383D, 0),
MAKE_INST(INST_PMAXSW , "pmaxsw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FEE, 0),
MAKE_INST(INST_PMAXUB , "pmaxub" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FDE, 0),
MAKE_INST(INST_PMAXUD , "pmaxud" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F383F, 0),
MAKE_INST(INST_PMAXUW , "pmaxuw" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F383E, 0),
MAKE_INST(INST_PMINSB , "pminsb" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3838, 0),
MAKE_INST(INST_PMINSD , "pminsd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3839, 0),
MAKE_INST(INST_PMINSW , "pminsw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FEA, 0),
MAKE_INST(INST_PMINUB , "pminub" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FDA, 0),
MAKE_INST(INST_PMINUD , "pminud" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F383B, 0),
MAKE_INST(INST_PMINUW , "pminuw" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F383A, 0),
MAKE_INST(INST_PMOVMSKB , "pmovmskb" , I_MMU_RMI , O_G32_64 , O_MM_XMM , 0, 0x00000FD7, 0),
MAKE_INST(INST_PMOVSXBD , "pmovsxbd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3821, 0),
MAKE_INST(INST_PMOVSXBQ , "pmovsxbq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3822, 0),
MAKE_INST(INST_PMOVSXBW , "pmovsxbw" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3820, 0),
MAKE_INST(INST_PMOVSXDQ , "pmovsxdq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3825, 0),
MAKE_INST(INST_PMOVSXWD , "pmovsxwd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3823, 0),
MAKE_INST(INST_PMOVSXWQ , "pmovsxwq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3824, 0),
MAKE_INST(INST_PMOVZXBD , "pmovzxbd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3831, 0),
MAKE_INST(INST_PMOVZXBQ , "pmovzxbq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3832, 0),
MAKE_INST(INST_PMOVZXBW , "pmovzxbw" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3830, 0),
MAKE_INST(INST_PMOVZXDQ , "pmovzxdq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3835, 0),
MAKE_INST(INST_PMOVZXWD , "pmovzxwd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3833, 0),
MAKE_INST(INST_PMOVZXWQ , "pmovzxwq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3834, 0),
MAKE_INST(INST_PMULDQ , "pmuldq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3828, 0),
MAKE_INST(INST_PMULHRSW , "pmulhrsw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F380B, 0),
MAKE_INST(INST_PMULHUW , "pmulhuw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FE4, 0),
MAKE_INST(INST_PMULHW , "pmulhw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FE5, 0),
MAKE_INST(INST_PMULLD , "pmulld" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3840, 0),
MAKE_INST(INST_PMULLW , "pmullw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FD5, 0),
MAKE_INST(INST_PMULUDQ , "pmuludq" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FF4, 0),
MAKE_INST(INST_POP , "pop" , I_POP , 0 , 0 , 0, 0x00000058, 0x0000008F),
MAKE_INST(INST_POPAD , "popad" , I_EMIT , 0 , 0 , 0, 0x00000061, 0),
MAKE_INST(INST_POPCNT , "popcnt" , I_R_RM , 0 , 0 , 0, 0xF3000FB8, 0),
MAKE_INST(INST_POPFD , "popfd" , I_EMIT , 0 , 0 , 0, 0x0000009D, 0),
MAKE_INST(INST_POPFQ , "popfq" , I_EMIT , 0 , 0 , 0, 0x0000009D, 0),
MAKE_INST(INST_POR , "por" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FEB, 0),
MAKE_INST(INST_PREFETCH , "prefetch" , I_MMU_PREFETCH , O_MEM , O_IMM , 0, 0 , 0),
MAKE_INST(INST_PSADBW , "psadbw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FF6, 0),
MAKE_INST(INST_PSHUFB , "pshufb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F3800, 0),
MAKE_INST(INST_PSHUFD , "pshufd" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x66000F70, 0),
MAKE_INST(INST_PSHUFW , "pshufw" , I_MMU_RM_IMM8 , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F70, 0),
MAKE_INST(INST_PSHUFHW , "pshufhw" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0xF3000F70, 0),
MAKE_INST(INST_PSHUFLW , "pshuflw" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0xF2000F70, 0),
MAKE_INST(INST_PSIGNB , "psignb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F3808, 0),
MAKE_INST(INST_PSIGND , "psignd" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F380A, 0),
MAKE_INST(INST_PSIGNW , "psignw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x000F3809, 0),
MAKE_INST(INST_PSLLD , "pslld" , I_MMU_RMI , O_MM_XMM, O_IMM | O_MM_XMM_MEM , 6, 0x00000FF2, 0x00000F72),
MAKE_INST(INST_PSLLDQ , "pslldq" , I_MMU_RMI , O_XMM , O_IMM , 7, 0 , 0x66000F73),
MAKE_INST(INST_PSLLQ , "psllq" , I_MMU_RMI , O_MM_XMM, O_IMM | O_MM_XMM_MEM , 6, 0x00000FF3, 0x00000F73),
MAKE_INST(INST_PSLLW , "psllw" , I_MMU_RMI , O_MM_XMM, O_IMM | O_MM_XMM_MEM , 6, 0x00000FF1, 0x00000F71),
MAKE_INST(INST_PSRAD , "psrad" , I_MMU_RMI , O_MM_XMM, O_IMM | O_MM_XMM_MEM , 4, 0x00000FE2, 0x00000F72),
MAKE_INST(INST_PSRAW , "psraw" , I_MMU_RMI , O_MM_XMM, O_IMM | O_MM_XMM_MEM , 4, 0x00000FE1, 0x00000F71),
MAKE_INST(INST_PSRLD , "psrld" , I_MMU_RMI , O_MM_XMM, O_IMM | O_MM_XMM_MEM , 2, 0x00000FD2, 0x00000F72),
MAKE_INST(INST_PSRLDQ , "psrldq" , I_MMU_RMI , O_XMM , O_IMM , 3, 0 , 0x66000F73),
MAKE_INST(INST_PSRLQ , "psrlq" , I_MMU_RMI , O_MM_XMM, O_IMM | O_MM_XMM_MEM , 2, 0x00000FD3, 0x00000F73),
MAKE_INST(INST_PSRLW , "psrlw" , I_MMU_RMI , O_MM_XMM, O_IMM | O_MM_XMM_MEM , 2, 0x00000FD1, 0x00000F71),
MAKE_INST(INST_PSUBB , "psubb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FF8, 0),
MAKE_INST(INST_PSUBD , "psubd" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FFA, 0),
MAKE_INST(INST_PSUBQ , "psubq" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FFB, 0),
MAKE_INST(INST_PSUBSB , "psubsb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FE8, 0),
MAKE_INST(INST_PSUBSW , "psubsw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FE9, 0),
MAKE_INST(INST_PSUBUSB , "psubusb" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FD8, 0),
MAKE_INST(INST_PSUBUSW , "psubusw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FD9, 0),
MAKE_INST(INST_PSUBW , "psubw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FF9, 0),
MAKE_INST(INST_PSWAPD , "pswapd" , I_MMU_RM_3DNOW , O_MM , O_MM_MEM , 0, 0x00000F0F, 0xBB),
MAKE_INST(INST_PTEST , "ptest" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x660F3817, 0),
MAKE_INST(INST_PUNPCKHBW , "punpckhbw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F68, 0),
MAKE_INST(INST_PUNPCKHDQ , "punpckhdq" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F6A, 0),
MAKE_INST(INST_PUNPCKHQDQ , "punpckhqdq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F6D, 0),
MAKE_INST(INST_PUNPCKHWD , "punpckhwd" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F69, 0),
MAKE_INST(INST_PUNPCKLBW , "punpcklbw" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F60, 0),
MAKE_INST(INST_PUNPCKLDQ , "punpckldq" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F62, 0),
MAKE_INST(INST_PUNPCKLQDQ , "punpcklqdq" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F6C, 0),
MAKE_INST(INST_PUNPCKLWD , "punpcklwd" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000F61, 0),
MAKE_INST(INST_PUSH , "push" , I_PUSH , 0 , 0 , 6, 0x00000050, 0x000000FF),
MAKE_INST(INST_PUSHAD , "pushad" , I_EMIT , 0 , 0 , 0, 0x00000060, 0),
MAKE_INST(INST_PUSHFD , "pushfd" , I_EMIT , 0 , 0 , 0, 0x0000009C, 0),
MAKE_INST(INST_PUSHFQ , "pushfq" , I_EMIT , 0 , 0 , 0, 0x0000009C, 0),
MAKE_INST(INST_PXOR , "pxor" , I_MMU_RMI , O_MM_XMM , O_MM_XMM_MEM , 0, 0x00000FEF, 0),
MAKE_INST(INST_RCL , "rcl" , I_ROT , 0 , 0 , 2, 0 , 0),
MAKE_INST(INST_RCPPS , "rcpps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F53, 0),
MAKE_INST(INST_RCPSS , "rcpss" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F53, 0),
MAKE_INST(INST_RCR , "rcr" , I_ROT , 0 , 0 , 3, 0 , 0),
MAKE_INST(INST_RDTSC , "rdtsc" , I_EMIT , 0 , 0 , 0, 0x00000F31, 0),
MAKE_INST(INST_RDTSCP , "rdtscp" , I_EMIT , 0 , 0 , 0, 0x000F01F9, 0),
MAKE_INST(INST_RET , "ret" , I_RET , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_ROL , "rol" , I_ROT , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_ROR , "ror" , I_ROT , 0 , 0 , 1, 0 , 0),
MAKE_INST(INST_ROUNDPD , "roundpd" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A09, 0),
MAKE_INST(INST_ROUNDPS , "roundps" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A08, 0),
MAKE_INST(INST_ROUNDSD , "roundsd" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A0B, 0),
MAKE_INST(INST_ROUNDSS , "roundss" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x660F3A0A, 0),
MAKE_INST(INST_RSQRTPS , "rsqrtps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F52, 0),
MAKE_INST(INST_RSQRTSS , "rsqrtss" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F52, 0),
MAKE_INST(INST_SAHF , "sahf" , I_EMIT , 0 , 0 , 0, 0x0000009E, 0),
MAKE_INST(INST_SAL , "sal" , I_ROT , 0 , 0 , 4, 0 , 0),
MAKE_INST(INST_SAR , "sar" , I_ROT , 0 , 0 , 7, 0 , 0),
MAKE_INST(INST_SBB , "sbb" , I_ALU , 0 , 0 , 3, 0x00000018, 0x00000080),
MAKE_INST(INST_SETA , "seta" , I_RM_B , 0 , 0 , 0, 0x00000F97, 0),
MAKE_INST(INST_SETAE , "setae" , I_RM_B , 0 , 0 , 0, 0x00000F93, 0),
MAKE_INST(INST_SETB , "setb" , I_RM_B , 0 , 0 , 0, 0x00000F92, 0),
MAKE_INST(INST_SETBE , "setbe" , I_RM_B , 0 , 0 , 0, 0x00000F96, 0),
MAKE_INST(INST_SETC , "setc" , I_RM_B , 0 , 0 , 0, 0x00000F92, 0),
MAKE_INST(INST_SETE , "sete" , I_RM_B , 0 , 0 , 0, 0x00000F94, 0),
MAKE_INST(INST_SETG , "setg" , I_RM_B , 0 , 0 , 0, 0x00000F9F, 0),
MAKE_INST(INST_SETGE , "setge" , I_RM_B , 0 , 0 , 0, 0x00000F9D, 0),
MAKE_INST(INST_SETL , "setl" , I_RM_B , 0 , 0 , 0, 0x00000F9C, 0),
MAKE_INST(INST_SETLE , "setle" , I_RM_B , 0 , 0 , 0, 0x00000F9E, 0),
MAKE_INST(INST_SETNA , "setna" , I_RM_B , 0 , 0 , 0, 0x00000F96, 0),
MAKE_INST(INST_SETNAE , "setnae" , I_RM_B , 0 , 0 , 0, 0x00000F92, 0),
MAKE_INST(INST_SETNB , "setnb" , I_RM_B , 0 , 0 , 0, 0x00000F93, 0),
MAKE_INST(INST_SETNBE , "setnbe" , I_RM_B , 0 , 0 , 0, 0x00000F97, 0),
MAKE_INST(INST_SETNC , "setnc" , I_RM_B , 0 , 0 , 0, 0x00000F93, 0),
MAKE_INST(INST_SETNE , "setne" , I_RM_B , 0 , 0 , 0, 0x00000F95, 0),
MAKE_INST(INST_SETNG , "setng" , I_RM_B , 0 , 0 , 0, 0x00000F9E, 0),
MAKE_INST(INST_SETNGE , "setnge" , I_RM_B , 0 , 0 , 0, 0x00000F9C, 0),
MAKE_INST(INST_SETNL , "setnl" , I_RM_B , 0 , 0 , 0, 0x00000F9D, 0),
MAKE_INST(INST_SETNLE , "setnle" , I_RM_B , 0 , 0 , 0, 0x00000F9F, 0),
MAKE_INST(INST_SETNO , "setno" , I_RM_B , 0 , 0 , 0, 0x00000F91, 0),
MAKE_INST(INST_SETNP , "setnp" , I_RM_B , 0 , 0 , 0, 0x00000F9B, 0),
MAKE_INST(INST_SETNS , "setns" , I_RM_B , 0 , 0 , 0, 0x00000F99, 0),
MAKE_INST(INST_SETNZ , "setnz" , I_RM_B , 0 , 0 , 0, 0x00000F95, 0),
MAKE_INST(INST_SETO , "seto" , I_RM_B , 0 , 0 , 0, 0x00000F90, 0),
MAKE_INST(INST_SETP , "setp" , I_RM_B , 0 , 0 , 0, 0x00000F9A, 0),
MAKE_INST(INST_SETPE , "setpe" , I_RM_B , 0 , 0 , 0, 0x00000F9A, 0),
MAKE_INST(INST_SETPO , "setpo" , I_RM_B , 0 , 0 , 0, 0x00000F9B, 0),
MAKE_INST(INST_SETS , "sets" , I_RM_B , 0 , 0 , 0, 0x00000F98, 0),
MAKE_INST(INST_SETZ , "setz" , I_RM_B , 0 , 0 , 0, 0x00000F94, 0),
MAKE_INST(INST_SFENCE , "sfence" , I_EMIT , 0 , 0 , 0, 0x000FAEF8, 0),
MAKE_INST(INST_SHL , "shl" , I_ROT , 0 , 0 , 4, 0 , 0),
MAKE_INST(INST_SHLD , "shld" , I_SHLD_SHRD , 0 , 0 , 0, 0x00000FA4, 0),
MAKE_INST(INST_SHR , "shr" , I_ROT , 0 , 0 , 5, 0 , 0),
MAKE_INST(INST_SHRD , "shrd" , I_SHLD_SHRD , 0 , 0 , 0, 0x00000FAC, 0),
MAKE_INST(INST_SHUFPS , "shufps" , I_MMU_RM_IMM8 , O_XMM , O_XMM_MEM , 0, 0x00000FC6, 0),
MAKE_INST(INST_SQRTPD , "sqrtpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F51, 0),
MAKE_INST(INST_SQRTPS , "sqrtps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F51, 0),
MAKE_INST(INST_SQRTSD , "sqrtsd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF2000F51, 0),
MAKE_INST(INST_SQRTSS , "sqrtss" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F51, 0),
MAKE_INST(INST_STC , "stc" , I_EMIT , 0 , 0 , 0, 0x000000F9, 0),
MAKE_INST(INST_STD , "std" , I_EMIT , 0 , 0 , 0, 0x000000FD, 0),
MAKE_INST(INST_STMXCSR , "stmxcsr" , I_M , O_MEM , 0 , 3, 0x00000FAE, 0),
MAKE_INST(INST_SUB , "sub" , I_ALU , 0 , 0 , 5, 0x00000028, 0x00000080),
MAKE_INST(INST_SUBPD , "subpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F5C, 0),
MAKE_INST(INST_SUBPS , "subps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F5C, 0),
MAKE_INST(INST_SUBSD , "subsd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF2000F5C, 0),
MAKE_INST(INST_SUBSS , "subss" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0xF3000F5C, 0),
MAKE_INST(INST_TEST , "test" , I_TEST , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_UCOMISD , "ucomisd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F2E, 0),
MAKE_INST(INST_UCOMISS , "ucomiss" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F2E, 0),
MAKE_INST(INST_UD2 , "ud2" , I_EMIT , 0 , 0 , 0, 0x00000F0B, 0),
MAKE_INST(INST_UNPCKHPD , "unpckhpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F15, 0),
MAKE_INST(INST_UNPCKHPS , "unpckhps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F15, 0),
MAKE_INST(INST_UNPCKLPD , "unpcklpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F14, 0),
MAKE_INST(INST_UNPCKLPS , "unpcklps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F14, 0),
MAKE_INST(INST_XADD , "xadd" , I_RM_R , 0 , 0 , 0, 0x00000FC0, 0),
MAKE_INST(INST_XCHG , "xchg" , I_XCHG , 0 , 0 , 0, 0 , 0),
MAKE_INST(INST_XOR , "xor" , I_ALU , 0 , 0 , 6, 0x00000030, 0x00000080),
MAKE_INST(INST_XORPD , "xorpd" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x66000F57, 0),
MAKE_INST(INST_XORPS , "xorps" , I_MMU_RMI , O_XMM , O_XMM_MEM , 0, 0x00000F57, 0)
};
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/INST_CODE.java 0000644 0001750 0001750 00000045736 11425031554 022031 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
public enum INST_CODE {
INST_ADC, // X86/X64
INST_ADD, // X86/X64
INST_ADDPD,
INST_ADDPS,
INST_ADDSD,
INST_ADDSS,
INST_ADDSUBPD,
INST_ADDSUBPS,
INST_AMD_PREFETCH,
INST_AMD_PREFETCHW,
INST_AND, // X86/X64
INST_ANDNPD,
INST_ANDNPS,
INST_ANDPD,
INST_ANDPS,
INST_BLENDPD,
INST_BLENDPS,
INST_BLENDVPD,
INST_BLENDVPS,
INST_BSF, // X86/X64
INST_BSR, // X86/X64
INST_BSWAP, // X86/X64 (i486)
INST_BT, // X86/X64
INST_BTC, // X86/X64
INST_BTR, // X86/X64
INST_BTS, // X86/X64
INST_CALL, // X86/X64
INST_CBW, // X86/X64
INST_CDQE, // X64 only
INST_CLC, // X86/X64
INST_CLD, // X86/X64
INST_CLFLUSH,
INST_CMC, // X86/X64
INST_CMOVA, //X86/X64 (cmovcc) (i586)
INST_CMOVAE, // X86/X64 (cmovcc) (i586)
INST_CMOVB, // X86/X64 (cmovcc) (i586)
INST_CMOVBE, // X86/X64 (cmovcc) (i586)
INST_CMOVC, // X86/X64 (cmovcc) (i586)
INST_CMOVE, // X86/X64 (cmovcc) (i586)
INST_CMOVG, // X86/X64 (cmovcc) (i586)
INST_CMOVGE, // X86/X64 (cmovcc) (i586)
INST_CMOVL, // X86/X64 (cmovcc) (i586)
INST_CMOVLE, // X86/X64 (cmovcc) (i586)
INST_CMOVNA, // X86/X64 (cmovcc) (i586)
INST_CMOVNAE, // X86/X64 (cmovcc) (i586)
INST_CMOVNB, // X86/X64 (cmovcc) (i586)
INST_CMOVNBE, // X86/X64 (cmovcc) (i586)
INST_CMOVNC, // X86/X64 (cmovcc) (i586)
INST_CMOVNE, // X86/X64 (cmovcc) (i586)
INST_CMOVNG, // X86/X64 (cmovcc) (i586)
INST_CMOVNGE, // X86/X64 (cmovcc) (i586)
INST_CMOVNL, // X86/X64 (cmovcc) (i586)
INST_CMOVNLE, // X86/X64 (cmovcc) (i586)
INST_CMOVNO, // X86/X64 (cmovcc) (i586)
INST_CMOVNP, // X86/X64 (cmovcc) (i586)
INST_CMOVNS, // X86/X64 (cmovcc) (i586)
INST_CMOVNZ, // X86/X64 (cmovcc) (i586)
INST_CMOVO, // X86/X64 (cmovcc) (i586)
INST_CMOVP, // X86/X64 (cmovcc) (i586)
INST_CMOVPE, // X86/X64 (cmovcc) (i586)
INST_CMOVPO, // X86/X64 (cmovcc) (i586)
INST_CMOVS, // X86/X64 (cmovcc) (i586)
INST_CMOVZ, // X86/X64 (cmovcc) (i586)
INST_CMP, // X86/X64
INST_CMPPD,
INST_CMPPS,
INST_CMPSD,
INST_CMPSS,
INST_CMPXCHG, // X86/X64 (i486)
INST_CMPXCHG16B, // X64 only
INST_CMPXCHG8B, // X86/X64 (i586)
INST_COMISD,
INST_COMISS,
INST_CPUID, // X86/X64 (i486)
INST_CRC32,
INST_CVTDQ2PD,
INST_CVTDQ2PS,
INST_CVTPD2DQ,
INST_CVTPD2PI,
INST_CVTPD2PS,
INST_CVTPI2PD,
INST_CVTPI2PS,
INST_CVTPS2DQ,
INST_CVTPS2PD,
INST_CVTPS2PI,
INST_CVTSD2SI,
INST_CVTSD2SS,
INST_CVTSI2SD,
INST_CVTSI2SS,
INST_CVTSS2SD,
INST_CVTSS2SI,
INST_CVTTPD2DQ,
INST_CVTTPD2PI,
INST_CVTTPS2DQ,
INST_CVTTPS2PI,
INST_CVTTSD2SI,
INST_CVTTSS2SI,
INST_CWDE, // X86/X64
INST_DAA, // X86 only
INST_DAS, // X86 only
INST_DEC, // X86/X64
INST_DIV, // X86/X64
INST_DIVPD,
INST_DIVPS,
INST_DIVSD,
INST_DIVSS,
INST_DPPD,
INST_DPPS,
INST_EMMS, // MMX
INST_ENTER, // X86/X64
INST_EXTRACTPS,
INST_F2XM1, // X87
INST_FABS, // X87
INST_FADD, // X87
INST_FADDP, // X87
INST_FBLD, // X87
INST_FBSTP, // X87
INST_FCHS, // X87
INST_FCLEX, // X87
INST_FCMOVB, // X87
INST_FCMOVBE, // X87
INST_FCMOVE, // X87
INST_FCMOVNB, // X87
INST_FCMOVNBE, // X87
INST_FCMOVNE, // X87
INST_FCMOVNU, // X87
INST_FCMOVU, // X87
INST_FCOM, // X87
INST_FCOMI, // X87
INST_FCOMIP, // X87
INST_FCOMP, // X87
INST_FCOMPP, // X87
INST_FCOS, // X87
INST_FDECSTP, // X87
INST_FDIV, // X87
INST_FDIVP, // X87
INST_FDIVR, // X87
INST_FDIVRP, // X87
INST_FEMMS, // 3dNow!
INST_FFREE, // X87
INST_FIADD, // X87
INST_FICOM, // X87
INST_FICOMP, // X87
INST_FIDIV, // X87
INST_FIDIVR, // X87
INST_FILD, // X87
INST_FIMUL, // X87
INST_FINCSTP, // X87
INST_FINIT, // X87
INST_FIST, // X87
INST_FISTP, // X87
INST_FISTTP,
INST_FISUB, // X87
INST_FISUBR, // X87
INST_FLD, // X87
INST_FLD1, // X87
INST_FLDCW, // X87
INST_FLDENV, // X87
INST_FLDL2E, // X87
INST_FLDL2T, // X87
INST_FLDLG2, // X87
INST_FLDLN2, // X87
INST_FLDPI, // X87
INST_FLDZ, // X87
INST_FMUL, // X87
INST_FMULP, // X87
INST_FNCLEX, // X87
INST_FNINIT, // X87
INST_FNOP, // X87
INST_FNSAVE, // X87
INST_FNSTCW, // X87
INST_FNSTENV, // X87
INST_FNSTSW, // X87
INST_FPATAN, // X87
INST_FPREM, // X87
INST_FPREM1, // X87
INST_FPTAN, // X87
INST_FRNDINT, // X87
INST_FRSTOR, // X87
INST_FSAVE, // X87
INST_FSCALE, // X87
INST_FSIN, // X87
INST_FSINCOS, // X87
INST_FSQRT, // X87
INST_FST, // X87
INST_FSTCW, // X87
INST_FSTENV, // X87
INST_FSTP, // X87
INST_FSTSW, // X87
INST_FSUB, // X87
INST_FSUBP, // X87
INST_FSUBR, // X87
INST_FSUBRP, // X87
INST_FTST, // X87
INST_FUCOM, // X87
INST_FUCOMI, // X87
INST_FUCOMIP, // X87
INST_FUCOMP, // X87
INST_FUCOMPP, // X87
INST_FWAIT, // X87
INST_FXAM, // X87
INST_FXCH, // X87
INST_FXRSTOR, // X87
INST_FXSAVE, // X87
INST_FXTRACT, // X87
INST_FYL2X, // X87
INST_FYL2XP1, // X87
INST_HADDPD,
INST_HADDPS,
INST_HSUBPD,
INST_HSUBPS,
INST_IDIV, // X86/X64
INST_IMUL, // X86/X64
INST_INC, // X86/X64
INST_INT3, // X86/X64
INST_JA, // X86/X64 (jcc)
INST_JAE, // X86/X64 (jcc)
INST_JB, // X86/X64 (jcc)
INST_JBE, // X86/X64 (jcc)
INST_JC, // X86/X64 (jcc)
INST_JE, // X86/X64 (jcc)
INST_JG, // X86/X64 (jcc)
INST_JGE, // X86/X64 (jcc)
INST_JL, // X86/X64 (jcc)
INST_JLE, // X86/X64 (jcc)
INST_JNA, // X86/X64 (jcc)
INST_JNAE, // X86/X64 (jcc)
INST_JNB, // X86/X64 (jcc)
INST_JNBE, // X86/X64 (jcc)
INST_JNC, // X86/X64 (jcc)
INST_JNE, // X86/X64 (jcc)
INST_JNG, // X86/X64 (jcc)
INST_JNGE, // X86/X64 (jcc)
INST_JNL, // X86/X64 (jcc)
INST_JNLE, // X86/X64 (jcc)
INST_JNO, // X86/X64 (jcc)
INST_JNP, // X86/X64 (jcc)
INST_JNS, // X86/X64 (jcc)
INST_JNZ, // X86/X64 (jcc)
INST_JO, // X86/X64 (jcc)
INST_JP, // X86/X64 (jcc)
INST_JPE, // X86/X64 (jcc)
INST_JPO, // X86/X64 (jcc)
INST_JS, // X86/X64 (jcc)
INST_JZ, // X86/X64 (jcc)
INST_JMP, // X86/X64 (jmp)
INST_JA_SHORT, // X86/X64 (jcc short)
INST_JAE_SHORT, // X86/X64 (jcc short)
INST_JB_SHORT, // X86/X64 (jcc short)
INST_JBE_SHORT, // X86/X64 (jcc short)
INST_JC_SHORT, // X86/X64 (jcc short)
INST_JE_SHORT, // X86/X64 (jcc short)
INST_JG_SHORT, // X86/X64 (jcc short)
INST_JGE_SHORT, // X86/X64 (jcc short)
INST_JL_SHORT, // X86/X64 (jcc short)
INST_JLE_SHORT, // X86/X64 (jcc short)
INST_JNA_SHORT, // X86/X64 (jcc short)
INST_JNAE_SHORT, // X86/X64 (jcc short)
INST_JNB_SHORT, // X86/X64 (jcc short)
INST_JNBE_SHORT, // X86/X64 (jcc short)
INST_JNC_SHORT, // X86/X64 (jcc short)
INST_JNE_SHORT, // X86/X64 (jcc short)
INST_JNG_SHORT, // X86/X64 (jcc short)
INST_JNGE_SHORT, // X86/X64 (jcc short)
INST_JNL_SHORT, // X86/X64 (jcc short)
INST_JNLE_SHORT, // X86/X64 (jcc short)
INST_JNO_SHORT, // X86/X64 (jcc short)
INST_JNP_SHORT, // X86/X64 (jcc short)
INST_JNS_SHORT, // X86/X64 (jcc short)
INST_JNZ_SHORT, // X86/X64 (jcc short)
INST_JO_SHORT, // X86/X64 (jcc short)
INST_JP_SHORT, // X86/X64 (jcc short)
INST_JPE_SHORT, // X86/X64 (jcc short)
INST_JPO_SHORT, // X86/X64 (jcc short)
INST_JS_SHORT, // X86/X64 (jcc short)
INST_JZ_SHORT, // X86/X64 (jcc short)
INST_JMP_SHORT, // X86/Z64 (jmp short)
INST_LDDQU,
INST_LDMXCSR,
INST_LEA, // X86/X64
INST_LEAVE, // X86/X64
INST_LFENCE,
INST_LOCK, // X86/X64
INST_MASKMOVDQU,
INST_MASKMOVQ, // MMX Extensions
INST_MAXPD,
INST_MAXPS,
INST_MAXSD,
INST_MAXSS,
INST_MFENCE,
INST_MINPD,
INST_MINPS,
INST_MINSD,
INST_MINSS,
INST_MONITOR,
INST_MOV, // X86/X64
INST_MOVAPD,
INST_MOVAPS,
INST_MOVBE,
INST_MOVD,
INST_MOVDDUP,
INST_MOVDQ2Q,
INST_MOVDQA,
INST_MOVDQU,
INST_MOVHLPS,
INST_MOVHPD,
INST_MOVHPS,
INST_MOVLHPS,
INST_MOVLPD,
INST_MOVLPS,
INST_MOVMSKPD,
INST_MOVMSKPS,
INST_MOVNTDQ,
INST_MOVNTDQA,
INST_MOVNTI,
INST_MOVNTPD,
INST_MOVNTPS,
INST_MOVNTQ, // MMX Extensions
INST_MOVQ,
INST_MOVQ2DQ,
INST_MOVSD,
INST_MOVSHDUP,
INST_MOVSLDUP,
INST_MOVSS,
INST_MOVSX, // X86/X64
INST_MOVSXD, // X86/X64
INST_MOVUPD,
INST_MOVUPS,
INST_MOVZX, // X86/X64
INST_MOV_PTR, // X86/X64
INST_MPSADBW,
INST_MUL, // X86/X64
INST_MULPD,
INST_MULPS,
INST_MULSD,
INST_MULSS,
INST_MWAIT,
INST_NEG, // X86/X64
INST_NOP, // X86/X64
INST_NOT, // X86/X64
INST_OR, // X86/X64
INST_ORPD,
INST_ORPS,
INST_PABSB,
INST_PABSD,
INST_PABSW,
INST_PACKSSDW,
INST_PACKSSWB,
INST_PACKUSDW,
INST_PACKUSWB,
INST_PADDB,
INST_PADDD,
INST_PADDQ,
INST_PADDSB,
INST_PADDSW,
INST_PADDUSB,
INST_PADDUSW,
INST_PADDW,
INST_PALIGNR,
INST_PAND,
INST_PANDN,
INST_PAUSE,
INST_PAVGB, // MMX Extensions
INST_PAVGW, // MMX Extensions
INST_PBLENDVB,
INST_PBLENDW,
INST_PCMPEQB,
INST_PCMPEQD,
INST_PCMPEQQ,
INST_PCMPEQW,
INST_PCMPESTRI,
INST_PCMPESTRM,
INST_PCMPGTB,
INST_PCMPGTD,
INST_PCMPGTQ,
INST_PCMPGTW,
INST_PCMPISTRI,
INST_PCMPISTRM,
INST_PEXTRB,
INST_PEXTRD,
INST_PEXTRQ,
INST_PEXTRW, // MMX Extensions
INST_PF2ID, // 3dNow!
INST_PF2IW, // 3dNow! Extensions
INST_PFACC, // 3dNow!
INST_PFADD, // 3dNow!
INST_PFCMPEQ, // 3dNow!
INST_PFCMPGE, // 3dNow!
INST_PFCMPGT, // 3dNow!
INST_PFMAX, // 3dNow!
INST_PFMIN, // 3dNow!
INST_PFMUL, // 3dNow!
INST_PFNACC, // 3dNow! Extensions
INST_PFPNACC, // 3dNow! Extensions
INST_PFRCP, // 3dNow!
INST_PFRCPIT1, // 3dNow!
INST_PFRCPIT2, // 3dNow!
INST_PFRSQIT1, // 3dNow!
INST_PFRSQRT, // 3dNow!
INST_PFSUB, // 3dNow!
INST_PFSUBR, // 3dNow!
INST_PHADDD,
INST_PHADDSW,
INST_PHADDW,
INST_PHMINPOSUW,
INST_PHSUBD,
INST_PHSUBSW,
INST_PHSUBW,
INST_PI2FD, // 3dNow!
INST_PI2FW, // 3dNow! Extensions
INST_PINSRB,
INST_PINSRD,
INST_PINSRQ,
INST_PINSRW, // MMX Extensions
INST_PMADDUBSW,
INST_PMADDWD,
INST_PMAXSB,
INST_PMAXSD,
INST_PMAXSW, // MMX Extensions
INST_PMAXUB, // MMX Extensions
INST_PMAXUD,
INST_PMAXUW,
INST_PMINSB,
INST_PMINSD,
INST_PMINSW, // MMX Extensions
INST_PMINUB, // MMX Extensions
INST_PMINUD,
INST_PMINUW,
INST_PMOVMSKB, // MMX Extensions
INST_PMOVSXBD,
INST_PMOVSXBQ,
INST_PMOVSXBW,
INST_PMOVSXDQ,
INST_PMOVSXWD,
INST_PMOVSXWQ,
INST_PMOVZXBD,
INST_PMOVZXBQ,
INST_PMOVZXBW,
INST_PMOVZXDQ,
INST_PMOVZXWD,
INST_PMOVZXWQ,
INST_PMULDQ,
INST_PMULHRSW,
INST_PMULHUW, // MMX Extensions
INST_PMULHW,
INST_PMULLD,
INST_PMULLW,
INST_PMULUDQ,
INST_POP, // X86/X64
INST_POPAD, // X86 only
INST_POPCNT,
INST_POPFD, // X86 only
INST_POPFQ, // X64 only
INST_POR,
INST_PREFETCH, // MMX Extensions
INST_PSADBW, // MMX Extensions
INST_PSHUFB,
INST_PSHUFD,
INST_PSHUFW, // MMX Extensions
INST_PSHUFHW,
INST_PSHUFLW,
INST_PSIGNB,
INST_PSIGND,
INST_PSIGNW,
INST_PSLLD,
INST_PSLLDQ,
INST_PSLLQ,
INST_PSLLW,
INST_PSRAD,
INST_PSRAW,
INST_PSRLD,
INST_PSRLDQ,
INST_PSRLQ,
INST_PSRLW,
INST_PSUBB,
INST_PSUBD,
INST_PSUBQ,
INST_PSUBSB,
INST_PSUBSW,
INST_PSUBUSB,
INST_PSUBUSW,
INST_PSUBW,
INST_PSWAPD, // 3dNow! Extensions
INST_PTEST,
INST_PUNPCKHBW,
INST_PUNPCKHDQ,
INST_PUNPCKHQDQ,
INST_PUNPCKHWD,
INST_PUNPCKLBW,
INST_PUNPCKLDQ,
INST_PUNPCKLQDQ,
INST_PUNPCKLWD,
INST_PUSH, // X86/X64
INST_PUSHAD, // X86 only
INST_PUSHFD, // X86 only
INST_PUSHFQ, // X64 only
INST_PXOR,
INST_RCL, // X86/X64
INST_RCPPS,
INST_RCPSS,
INST_RCR, // X86/X64
INST_RDTSC, // X86/X64
INST_RDTSCP, // X86/X64
INST_RET, // X86/X64
INST_ROL, // X86/X64
INST_ROR, // X86/X64
INST_ROUNDPD,
INST_ROUNDPS,
INST_ROUNDSD,
INST_ROUNDSS,
INST_RSQRTPS,
INST_RSQRTSS,
INST_SAHF, // X86 only
INST_SAL, // X86/X64
INST_SAR, // X86/X64
INST_SBB, // X86/X64
INST_SETA, // X86/X64 (setcc)
INST_SETAE, // X86/X64 (setcc)
INST_SETB, // X86/X64 (setcc)
INST_SETBE, // X86/X64 (setcc)
INST_SETC, // X86/X64 (setcc)
INST_SETE, // X86/X64 (setcc)
INST_SETG, // X86/X64 (setcc)
INST_SETGE, // X86/X64 (setcc)
INST_SETL, // X86/X64 (setcc)
INST_SETLE, // X86/X64 (setcc)
INST_SETNA, // X86/X64 (setcc)
INST_SETNAE, // X86/X64 (setcc)
INST_SETNB, // X86/X64 (setcc)
INST_SETNBE, // X86/X64 (setcc)
INST_SETNC, // X86/X64 (setcc)
INST_SETNE, // X86/X64 (setcc)
INST_SETNG, // X86/X64 (setcc)
INST_SETNGE, // X86/X64 (setcc)
INST_SETNL, // X86/X64 (setcc)
INST_SETNLE, // X86/X64 (setcc)
INST_SETNO, // X86/X64 (setcc)
INST_SETNP, // X86/X64 (setcc)
INST_SETNS, // X86/X64 (setcc)
INST_SETNZ, // X86/X64 (setcc)
INST_SETO, // X86/X64 (setcc)
INST_SETP, // X86/X64 (setcc)
INST_SETPE, // X86/X64 (setcc)
INST_SETPO, // X86/X64 (setcc)
INST_SETS, // X86/X64 (setcc)
INST_SETZ, // X86/X64 (setcc)
INST_SFENCE, // MMX Extensions
INST_SHL, // X86/X64
INST_SHLD, // X86/X64
INST_SHR, // X86/X64
INST_SHRD, // X86/X64
INST_SHUFPS,
INST_SQRTPD,
INST_SQRTPS,
INST_SQRTSD,
INST_SQRTSS,
INST_STC, // X86/X64
INST_STD, // X86/X64
INST_STMXCSR,
INST_SUB, // X86/X64
INST_SUBPD,
INST_SUBPS,
INST_SUBSD,
INST_SUBSS,
INST_TEST, // X86/X64
INST_UCOMISD,
INST_UCOMISS,
INST_UD2, // X86/X64
INST_UNPCKHPD,
INST_UNPCKHPS,
INST_UNPCKLPD,
INST_UNPCKLPS,
INST_XADD, // X86/X64 (i486)
INST_XCHG, // X86/X64 (i386)
INST_XOR, // X86/X64
INST_XORPD,
INST_XORPS;
public static final INST_CODE INST_J = INST_JA;
public static final INST_CODE INST_J_SHORT = INST_JA_SHORT;
public final boolean isShortJump() {
return compareTo(INST_J_SHORT) >= 0 && compareTo(INST_JMP_SHORT) <= 0;
}
public static final INST_CODE valueOf(int idx) {
return values()[idx];
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/ERROR_CODE.java 0000644 0001750 0001750 00000006103 11425031554 022126 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
public enum ERROR_CODE {
/** No error (success). */
ERROR_NONE,
/** Memory allocation error (@c ASMJIT_MALLOC returned @c NULL). */
ERROR_NO_HEAP_MEMORY,
/** Virtual memory allocation error (@c VirtualMemory returned @c NULL). */
ERROR_NO_VIRTUAL_MEMORY,
/** Unknown instruction. This happens only if instruction code is
*out of bounds. Shouldn't happen. */
ERROR_UNKNOWN_INSTRUCTION,
/**
* Illegal instruction.
*
* Usually generated by AsmJit::AssemblerCore class when emitting instruction
* opcode. If this error is generated the target buffer is not affected by
* this invalid instruction. In debug mode you get assertion failure instead.
*/
ERROR_ILLEGAL_INSTRUCTION,
/** Illegal addressing used (unencodable). */
ERROR_ILLEGAL_ADDRESING,
/** Short jump instruction used, but displacement is out of bounds. */
ERROR_ILLEGAL_SHORT_JUMP,
/** Count of error codes by AsmJit. Can grow in future. */
_ERROR_COUNT;
public final int intValue() {
return ordinal();
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/Immediate.java 0000644 0001750 0001750 00000007055 11425031554 022350 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
/**
*
*/
public final class Immediate extends Operand {
private final long value;
private final boolean isUnsigned;
private final RELOC_MODE relocMode;
public Immediate(long value, boolean isUnsigned) {
super(OP.OP_IMM, 0);
this.value = value;
this.isUnsigned = isUnsigned;
this.relocMode = RELOC_MODE.RELOC_NONE;
}
public long value() {
return value;
}
public final byte byteValue() {
return (byte) value;
}
public final short shortValue() {
return (short) value;
}
public final int intValue() {
return (int) value;
}
public final long longValue() {
return value;
}
/** Return true if immediate is unsigned value. */
public final boolean isUnsigned() {
return isUnsigned;
}
/** Return relocation mode. */
RELOC_MODE relocMode() {
return relocMode;
}
/**
* Internal cache of common native long values
*/
private static final class Cache {
private Cache() {}
static final Immediate[] cache = new Immediate[256];
static {
for (int i = 0; i < cache.length; ++i) {
cache[i] = new Immediate(i - 128, false);
}
}
}
public static final Immediate imm(long value) {
return value >= -128 && value <= 127
? Cache.cache[128 + (int) value] : new Immediate(value, false);
}
public static final Immediate uimm(long value) {
return new Immediate(value, true);
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/RelocData.java 0000644 0001750 0001750 00000005362 11425031554 022307 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
/**
* Reloc to absolute address data
*/
class RelocData {
static enum Type {
ABSOLUTE_TO_ABSOLUTE,
RELATIVE_TO_ABSOLUTE,
ABSOLUTE_TO_RELATIVE,
ABSOLUTE_TO_RELATIVE_TRAMPOLINE;
};
/** Type of relocation. */
final Type type;
/** Size of relocation (4 or 8 bytes). */
final int size;
/** Offset from code begin address (in the emitted code data stream). */
final int offset;
/** Relative displacement or absolute address. */
final long destination;
public RelocData(Type type, int size, int offset, long destination) {
this.type = type;
this.size = size;
this.offset = offset;
this.destination = destination;
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/Util.java 0000644 0001750 0001750 00000006111 11425031554 021357 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
/**
*
*/
public final class Util {
private Util() {
}
/** Returns @c true if a given integer @a x is signed 8 bit integer */
static final boolean isInt8(long x) {
return x >= -128 && x <= 127;
}
/** Returns @c true if a given integer @a x is unsigned 8 bit integer */
static final boolean isUInt8(long x) {
return x >= 0 && x <= 255;
}
/** Returns @c true if a given integer @a x is signed 16 bit integer */
static final boolean isInt16(long x) {
return x >= -32768 && x <= 32767;
}
/** Returns @c true if a given integer @a x is unsigned 16 bit integer */
static final boolean isUInt16(long x) {
return x >= 0 && x <= 65535;
}
/** Returns @c true if a given integer @a x is signed 32 bit integer */
static final boolean isInt32(long x) {
return x >= Integer.MIN_VALUE && x <= Integer.MAX_VALUE;
}
/** Returns @c true if a given integer @a x is unsigned 32 bit integer */
static final boolean isUInt32(long x) {
return x >= 0 && x <= 0xffffffffL;
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/RID.java 0000644 0001750 0001750 00000005277 11425031554 021074 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
public class RID {
private RID() {
}
/** ID for AX/EAX/RAX registers. */
public static final int RID_EAX = 0;
/** ID for CX/ECX/RCX registers. */
public static final int RID_ECX = 1;
/** ID for DX/EDX/RDX registers. */
public static final int RID_EDX = 2;
/** ID for BX/EBX/RBX registers. */
public static final int RID_EBX = 3;
/** ID for SP/ESP/RSP registers. */
public static final int RID_ESP = 4;
/** ID for BP/EBP/RBP registers. */
public static final int RID_EBP = 5;
/** ID for SI/ESI/RSI registers. */
public static final int RID_ESI = 6;
/** ID for DI/EDI/RDI registers. */
public static final int RID_EDI = 7;
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/MMRegister.java 0000644 0001750 0001750 00000002445 11425031554 022466 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
package com.kenai.jnr.x86asm;
public final class MMRegister extends BaseReg {
/** Internal cache of mm registers */
static final MMRegister[] cache = new MMRegister[8];
static {
for (int i = 0; i < cache.length; ++i) {
cache[i] = new MMRegister(REG.REG_MM | i, 8);
}
}
private MMRegister(int code, int size) {
super(code, size);
}
public static final MMRegister mm(int code) {
if (code >= 0 && code < cache.length) {
return cache[code];
}
throw new IllegalArgumentException("invalid mm register");
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/HINT.java 0000644 0001750 0001750 00000005275 11425031554 021216 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
/**
* Condition hint, see @c AsmJit::Serializer::jz() and friends.
*/
public enum HINT {
/** No hint. */
HINT_NONE(0),
/** Condition will be taken (likely). */
HINT_TAKEN(0x3e),
/** Condition will be not taken (unlikely). */
HINT_NOT_TAKEN(0x2e);
private final int value;
HINT(int value) {
this.value = value;
}
public final int value() {
return value;
}
public static final HINT valueOf(int value) {
switch (value) {
case 0x3e:
return HINT_TAKEN;
case 0x2e:
return HINT_NOT_TAKEN;
default:
return HINT_NONE;
}
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/CodeBuffer.java 0000644 0001750 0001750 00000005443 11425031554 022455 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
package com.kenai.jnr.x86asm;
import java.nio.ByteBuffer;
import java.nio.ByteOrder;
/**
*
*/
final class CodeBuffer {
private ByteBuffer buf;
public CodeBuffer() {
buf = ByteBuffer.allocate(128).order(ByteOrder.LITTLE_ENDIAN);
}
public final void ensureSpace() {
if (buf.remaining() < 16) {
grow();
}
}
public void grow() {
int newSize = buf.capacity() * 2;
ByteBuffer newBuffer = ByteBuffer.allocate(newSize).order(ByteOrder.LITTLE_ENDIAN);
// Copy the data over
buf.flip();
newBuffer.put(buf);
buf = newBuffer;
}
final void copyTo(ByteBuffer dst) {
ByteBuffer dup = buf.duplicate();
dup.flip();
dst.put(dup);
}
public final int offset() {
return buf.position();
}
public int capacity() {
return buf.capacity();
}
public final void emitByte(byte x) {
buf.put(x);
}
public final void emitWord(short x) {
buf.putShort(x);
}
public final void emitDWord(int x) {
buf.putInt(x);
}
public final void emitQWord(long x) {
buf.putLong(x);
}
public final void emitData(ByteBuffer data, int len) {
ByteBuffer dup = data.duplicate();
if (dup.remaining() > len) {
dup.limit(dup.position() + len);
}
buf.put(dup);
}
public final byte getByteAt(int pos) {
return buf.get(pos);
}
public final short getWordAt(int pos) {
return buf.getShort(pos);
}
public final int getDWordAt(int pos) {
return buf.getInt(pos);
}
public final long getQWordAt(int pos) {
return buf.getLong(pos);
}
public final void setByteAt(int pos, byte x) {
buf.put(pos, x);
}
public final void setWordAt(int pos, short x) {
buf.putShort(pos, x);
}
public final void setDWordAt(int pos, int x) {
buf.putInt(pos, x);
}
public final void setQWordAt(int pos, long x) {
buf.putLong(pos, x);
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/BaseReg.java 0000644 0001750 0001750 00000005563 11425031554 021764 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
import static com.kenai.jnr.x86asm.REG.*;
public abstract class BaseReg extends Operand {
public final int code;
public BaseReg(int code, int size) {
super(OP.OP_REG, size);
this.code = code;
}
//! @brief Return register type, see @c REG.
public final int type() {
return code() & REGTYPE_MASK;
}
//! @brief Return register code, see @c REG.
public final int code() {
return code;
}
//! @brief Return register index (value from 0 to 7/15).
public final int index() {
return code() & REGCODE_MASK;
}
// public final boolean isRegCode(int code) {
// return code() == code;
// }
//
// public final boolean isRegType(int type) {
// return type() == type;
// }
//
// public final boolean isRegIndex(int index) {
// return index() == index;
// }
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/TrampolineWriter.java 0000644 0001750 0001750 00000005323 11425031554 023755 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
import java.nio.ByteBuffer;
/**
* Class used to determine size of trampoline and as trampoline writer.
*/
final class TrampolineWriter {
// Size of trampoline
public static final int TRAMPOLINE_JMP = 6;
public static final int TRAMPOLINE_ADDR = 8;
public static final int TRAMPOLINE_SIZE = TRAMPOLINE_JMP + TRAMPOLINE_ADDR;
// Write trampoline into code at address @a code that will jump to @a target.
static void writeTrampoline(ByteBuffer buf, long target) {
// Jmp.
buf.put((byte) 0xFF);
// ModM (RIP addressing).
buf.put((byte) 0x25);
// Offset (zero).
buf.putInt(0);
// Absolute address.
buf.putLong(target);
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/CPU.java 0000644 0001750 0001750 00000001465 11425031554 021100 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
package com.kenai.jnr.x86asm;
public enum CPU {
X86_32, X86_64;
public static final CPU I386 = X86_32;
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/OperandFlags.java 0000644 0001750 0001750 00000006102 11425031554 023007 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
public class OperandFlags {
public static final int // x86
O_G8 = 0x01,
O_G16 = 0x02,
O_G32 = 0x04,
O_G64 = 0x08,
O_MEM = 0x40,
O_IMM = 0x80,
O_G8_16_32_64 = O_G64 | O_G32 | O_G16 | O_G8,
O_G16_32_64 = O_G64 | O_G32 | O_G16,
O_G32_64 = O_G64 | O_G32,
// x87
O_FM_1 = 0x01,
O_FM_2 = 0x02,
O_FM_4 = 0x04,
O_FM_8 = 0x08,
O_FM_10 = 0x10,
O_FM_2_4 = O_FM_2 | O_FM_4,
O_FM_2_4_8 = O_FM_2 | O_FM_4 | O_FM_8,
O_FM_4_8 = O_FM_4 | O_FM_8,
O_FM_4_8_10 = O_FM_4 | O_FM_8 | O_FM_10,
// mm|xmm
O_NOREX = 0x01, // Used by MMX/SSE instructions, O_G8 is never used for them
O_MM = 0x10,
O_XMM = 0x20,
O_MM_MEM = O_MM | O_MEM,
O_XMM_MEM = O_XMM | O_MEM,
O_MM_XMM = O_MM | O_XMM,
O_MM_XMM_MEM = O_MM | O_XMM | O_MEM;
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/RELOC_MODE.java 0000644 0001750 0001750 00000004264 11425031554 022121 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
// While jnr-x86asm is covered under the LGPL version 3 as state above, it is based
// on code from the AsmJit project, and that copyright is reproduced below.
//
// Copyright (c) 2008-2009, Petr Kobalicek
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
package com.kenai.jnr.x86asm;
/** Relocation info */
public enum RELOC_MODE {
/** No relocation. */
RELOC_NONE,
/** Overwrite relocation (immediates as constants). */
RELOC_OVERWRITE;
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/CpuInfo.java 0000644 0001750 0001750 00000002141 11425031554 022004 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
package com.kenai.jnr.x86asm;
/**
* Information about target CPU
*/
public class CpuInfo {
final Vendor vendor;
final int family;
public enum Vendor {
INTEL,
AMD,
GENERIC;
}
public static final CpuInfo GENERIC = new CpuInfo(Vendor.GENERIC, 0);
public CpuInfo(Vendor vendor, int family) {
this.vendor = vendor;
this.family = family;
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/SEGMENT.java 0000644 0001750 0001750 00000002111 11425031554 021540 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
package com.kenai.jnr.x86asm;
/**
* Segment override prefixes.
*/
public enum SEGMENT {
SEGMENT_NONE(0), SEGMENT_CS(0x2E), SEGMENT_SS(0x36),
SEGMENT_DS(0x3E), SEGMENT_ES(0x26), SEGMENT_FS(0x64), SEGMENT_GS(0x64);
private final int prefix;
SEGMENT(int prefix) {
this.prefix = prefix;
}
public final int prefix() {
return this.prefix;
}
}
jnr-x86asm-0.1/src/com/kenai/jnr/x86asm/X87Register.java 0000644 0001750 0001750 00000002577 11425031554 022551 0 ustar twerner twerner /*
* Copyright (C) 2010 Wayne Meissner
*
* This file is part of jnr-x86asm.
*
* This code is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 3 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
* version 3 for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* version 3 along with this work. If not, see .
*/
package com.kenai.jnr.x86asm;
public final class X87Register extends BaseReg {
/** Internal cache of xmm registers */
static final X87Register[] cache = new X87Register[16];
static {
for (int i = 0; i < cache.length; ++i) {
cache[i] = new X87Register(REG.REG_X87 | i, 10);
}
}
private X87Register(int code, int size) {
super(code, size);
}
public static final X87Register st(int idx) {
return x87(idx);
}
public static final X87Register x87(int idx) {
if (idx >= 0 && idx < cache.length) {
return cache[idx];
}
throw new IllegalArgumentException("invalid x87 register");
}
}
jnr-x86asm-0.1/README 0000644 0001750 0001750 00000000325 11425031554 014105 0 ustar twerner twerner
This is a pure-java port of asmjit (http://code.google.com/p/asmjit/)
There has been no attempt to clean the code up or java-fy it, so looking at it
will make your eyes bleed and most probably send you insane.